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drm/i915: scramble reset support for DP port CRC on vlv
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_debugfs.c
CommitLineData
2017263e
BG		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 *
27 */
28
29#include <linux/seq_file.h>
b2c88f5b 30#include <linux/circ_buf.h>
926321d5 31#include <linux/ctype.h>
f3cd474b 32#include <linux/debugfs.h>
5a0e3ad6 33#include <linux/slab.h>
2d1a8a48 34#include <linux/export.h>
6d2b8885 35#include <linux/list_sort.h>
ec013e7f 36#include <asm/msr-index.h>
760285e7 37#include <drm/drmP.h>
4e5359cd 38#include "intel_drv.h"
e5c65260 39#include "intel_ringbuffer.h"
760285e7 40#include <drm/i915_drm.h>
2017263e
BG		 41#include "i915_drv.h"
42
2017263e
BG		 43#if defined(CONFIG_DEBUG_FS)
44
f13d3f73 45enum {
69dc4987 46 ACTIVE_LIST,
f13d3f73 47 INACTIVE_LIST,
d21d5975 48 PINNED_LIST,
f13d3f73 49};
2017263e 50
70d39fe4
CW		 51static const char *yesno(int v)
52{
53 return v ? "yes" : "no";
54}
55
497666d8
DL		 56/* As the drm_debugfs_init() routines are called before dev->dev_private is
57 * allocated we need to hook into the minor for release. */
58static int
59drm_add_fake_info_node(struct drm_minor *minor,
60 struct dentry *ent,
61 const void *key)
62{
63 struct drm_info_node *node;
64
65 node = kmalloc(sizeof(*node), GFP_KERNEL);
66 if (node == NULL) {
67 debugfs_remove(ent);
68 return -ENOMEM;
69 }
70
71 node->minor = minor;
72 node->dent = ent;
73 node->info_ent = (void *) key;
74
75 mutex_lock(&minor->debugfs_lock);
76 list_add(&node->list, &minor->debugfs_list);
77 mutex_unlock(&minor->debugfs_lock);
78
79 return 0;
80}
81
70d39fe4
CW		 82static int i915_capabilities(struct seq_file *m, void *data)
83{
84 struct drm_info_node *node = (struct drm_info_node *) m->private;
85 struct drm_device *dev = node->minor->dev;
86 const struct intel_device_info *info = INTEL_INFO(dev);
87
88 seq_printf(m, "gen: %d\n", info->gen);
03d00ac5 89 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
79fc46df
DL		 90#define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
91#define SEP_SEMICOLON ;
92 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
93#undef PRINT_FLAG
94#undef SEP_SEMICOLON
70d39fe4
CW		 95
96 return 0;
97}
2017263e 98
05394f39 99static const char *get_pin_flag(struct drm_i915_gem_object *obj)
a6172a80 100{
05394f39 101 if (obj->user_pin_count > 0)
a6172a80 102 return "P";
05394f39 103 else if (obj->pin_count > 0)
a6172a80
CW		 104 return "p";
105 else
106 return " ";
107}
108
05394f39 109static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
a6172a80 110{
0206e353
AJ		 111 switch (obj->tiling_mode) {
112 default:
113 case I915_TILING_NONE: return " ";
114 case I915_TILING_X: return "X";
115 case I915_TILING_Y: return "Y";
116 }
a6172a80
CW		 117}
118
1d693bcc
BW		 119static inline const char *get_global_flag(struct drm_i915_gem_object *obj)
120{
121 return obj->has_global_gtt_mapping ? "g" : " ";
122}
123
37811fcc
CW		 124static void
125describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
126{
1d693bcc 127 struct i915_vma *vma;
fb1ae911 128 seq_printf(m, "%pK: %s%s%s %8zdKiB %02x %02x %u %u %u%s%s%s",
37811fcc
CW		 129 &obj->base,
130 get_pin_flag(obj),
131 get_tiling_flag(obj),
1d693bcc 132 get_global_flag(obj),
a05a5862 133 obj->base.size / 1024,
37811fcc
CW		 134 obj->base.read_domains,
135 obj->base.write_domain,
0201f1ec
CW		 136 obj->last_read_seqno,
137 obj->last_write_seqno,
caea7476 138 obj->last_fenced_seqno,
84734a04 139 i915_cache_level_str(obj->cache_level),
37811fcc
CW		 140 obj->dirty ? " dirty" : "",
141 obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
142 if (obj->base.name)
143 seq_printf(m, " (name: %d)", obj->base.name);
c110a6d7
CW		 144 if (obj->pin_count)
145 seq_printf(m, " (pinned x %d)", obj->pin_count);
cc98b413
CW		 146 if (obj->pin_display)
147 seq_printf(m, " (display)");
37811fcc
CW		 148 if (obj->fence_reg != I915_FENCE_REG_NONE)
149 seq_printf(m, " (fence: %d)", obj->fence_reg);
1d693bcc
BW		 150 list_for_each_entry(vma, &obj->vma_list, vma_link) {
151 if (!i915_is_ggtt(vma->vm))
152 seq_puts(m, " (pp");
153 else
154 seq_puts(m, " (g");
155 seq_printf(m, "gtt offset: %08lx, size: %08lx)",
156 vma->node.start, vma->node.size);
157 }
c1ad11fc
CW		 158 if (obj->stolen)
159 seq_printf(m, " (stolen: %08lx)", obj->stolen->start);
6299f992
CW		 160 if (obj->pin_mappable || obj->fault_mappable) {
161 char s[3], *t = s;
162 if (obj->pin_mappable)
163 *t++ = 'p';
164 if (obj->fault_mappable)
165 *t++ = 'f';
166 *t = '\0';
167 seq_printf(m, " (%s mappable)", s);
168 }
69dc4987
CW		 169 if (obj->ring != NULL)
170 seq_printf(m, " (%s)", obj->ring->name);
37811fcc
CW		 171}
172
3ccfd19d
BW		 173static void describe_ctx(struct seq_file *m, struct i915_hw_context *ctx)
174{
175 seq_putc(m, ctx->is_initialized ? 'I' : 'i');
176 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
177 seq_putc(m, ' ');
178}
179
433e12f7 180static int i915_gem_object_list_info(struct seq_file *m, void *data)
2017263e
BG		 181{
182 struct drm_info_node *node = (struct drm_info_node *) m->private;
433e12f7
BG		 183 uintptr_t list = (uintptr_t) node->info_ent->data;
184 struct list_head *head;
2017263e 185 struct drm_device *dev = node->minor->dev;
5cef07e1
BW		 186 struct drm_i915_private *dev_priv = dev->dev_private;
187 struct i915_address_space *vm = &dev_priv->gtt.base;
ca191b13 188 struct i915_vma *vma;
8f2480fb
CW		 189 size_t total_obj_size, total_gtt_size;
190 int count, ret;
de227ef0
CW		 191
192 ret = mutex_lock_interruptible(&dev->struct_mutex);
193 if (ret)
194 return ret;
2017263e 195
ca191b13 196 /* FIXME: the user of this interface might want more than just GGTT */
433e12f7
BG		 197 switch (list) {
198 case ACTIVE_LIST:
267f0c90 199 seq_puts(m, "Active:\n");
5cef07e1 200 head = &vm->active_list;
433e12f7
BG		 201 break;
202 case INACTIVE_LIST:
267f0c90 203 seq_puts(m, "Inactive:\n");
5cef07e1 204 head = &vm->inactive_list;
433e12f7 205 break;
433e12f7 206 default:
de227ef0
CW		 207 mutex_unlock(&dev->struct_mutex);
208 return -EINVAL;
2017263e 209 }
2017263e 210
8f2480fb 211 total_obj_size = total_gtt_size = count = 0;
ca191b13
BW		 212 list_for_each_entry(vma, head, mm_list) {
213 seq_printf(m, " ");
214 describe_obj(m, vma->obj);
215 seq_printf(m, "\n");
216 total_obj_size += vma->obj->base.size;
217 total_gtt_size += vma->node.size;
8f2480fb 218 count++;
2017263e 219 }
de227ef0 220 mutex_unlock(&dev->struct_mutex);
5e118f41 221
8f2480fb
CW		 222 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
223 count, total_obj_size, total_gtt_size);
2017263e
BG		 224 return 0;
225}
226
6d2b8885
CW		 227static int obj_rank_by_stolen(void *priv,
228 struct list_head *A, struct list_head *B)
229{
230 struct drm_i915_gem_object *a =
b25cb2f8 231 container_of(A, struct drm_i915_gem_object, obj_exec_link);
6d2b8885 232 struct drm_i915_gem_object *b =
b25cb2f8 233 container_of(B, struct drm_i915_gem_object, obj_exec_link);
6d2b8885
CW		 234
235 return a->stolen->start - b->stolen->start;
236}
237
238static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
239{
240 struct drm_info_node *node = (struct drm_info_node *) m->private;
241 struct drm_device *dev = node->minor->dev;
242 struct drm_i915_private *dev_priv = dev->dev_private;
243 struct drm_i915_gem_object *obj;
244 size_t total_obj_size, total_gtt_size;
245 LIST_HEAD(stolen);
246 int count, ret;
247
248 ret = mutex_lock_interruptible(&dev->struct_mutex);
249 if (ret)
250 return ret;
251
252 total_obj_size = total_gtt_size = count = 0;
253 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
254 if (obj->stolen == NULL)
255 continue;
256
b25cb2f8 257 list_add(&obj->obj_exec_link, &stolen);
6d2b8885
CW		 258
259 total_obj_size += obj->base.size;
260 total_gtt_size += i915_gem_obj_ggtt_size(obj);
261 count++;
262 }
263 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
264 if (obj->stolen == NULL)
265 continue;
266
b25cb2f8 267 list_add(&obj->obj_exec_link, &stolen);
6d2b8885
CW		 268
269 total_obj_size += obj->base.size;
270 count++;
271 }
272 list_sort(NULL, &stolen, obj_rank_by_stolen);
273 seq_puts(m, "Stolen:\n");
274 while (!list_empty(&stolen)) {
b25cb2f8 275 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
6d2b8885
CW		 276 seq_puts(m, " ");
277 describe_obj(m, obj);
278 seq_putc(m, '\n');
b25cb2f8 279 list_del_init(&obj->obj_exec_link);
6d2b8885
CW		 280 }
281 mutex_unlock(&dev->struct_mutex);
282
283 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
284 count, total_obj_size, total_gtt_size);
285 return 0;
286}
287
6299f992
CW		 288#define count_objects(list, member) do { \
289 list_for_each_entry(obj, list, member) { \
f343c5f6 290 size += i915_gem_obj_ggtt_size(obj); \
6299f992
CW		 291 ++count; \
292 if (obj->map_and_fenceable) { \
f343c5f6 293 mappable_size += i915_gem_obj_ggtt_size(obj); \
6299f992
CW		 294 ++mappable_count; \
295 } \
296 } \
0206e353 297} while (0)
6299f992 298
2db8e9d6
CW		 299struct file_stats {
300 int count;
301 size_t total, active, inactive, unbound;
302};
303
304static int per_file_stats(int id, void *ptr, void *data)
305{
306 struct drm_i915_gem_object *obj = ptr;
307 struct file_stats *stats = data;
308
309 stats->count++;
310 stats->total += obj->base.size;
311
f343c5f6 312 if (i915_gem_obj_ggtt_bound(obj)) {
2db8e9d6
CW		 313 if (!list_empty(&obj->ring_list))
314 stats->active += obj->base.size;
315 else
316 stats->inactive += obj->base.size;
317 } else {
318 if (!list_empty(&obj->global_list))
319 stats->unbound += obj->base.size;
320 }
321
322 return 0;
323}
324
ca191b13
BW		 325#define count_vmas(list, member) do { \
326 list_for_each_entry(vma, list, member) { \
327 size += i915_gem_obj_ggtt_size(vma->obj); \
328 ++count; \
329 if (vma->obj->map_and_fenceable) { \
330 mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
331 ++mappable_count; \
332 } \
333 } \
334} while (0)
335
336static int i915_gem_object_info(struct seq_file *m, void* data)
73aa808f
CW		 337{
338 struct drm_info_node *node = (struct drm_info_node *) m->private;
339 struct drm_device *dev = node->minor->dev;
340 struct drm_i915_private *dev_priv = dev->dev_private;
b7abb714
CW		 341 u32 count, mappable_count, purgeable_count;
342 size_t size, mappable_size, purgeable_size;
6299f992 343 struct drm_i915_gem_object *obj;
5cef07e1 344 struct i915_address_space *vm = &dev_priv->gtt.base;
2db8e9d6 345 struct drm_file *file;
ca191b13 346 struct i915_vma *vma;
73aa808f
CW		 347 int ret;
348
349 ret = mutex_lock_interruptible(&dev->struct_mutex);
350 if (ret)
351 return ret;
352
6299f992
CW		 353 seq_printf(m, "%u objects, %zu bytes\n",
354 dev_priv->mm.object_count,
355 dev_priv->mm.object_memory);
356
357 size = count = mappable_size = mappable_count = 0;
35c20a60 358 count_objects(&dev_priv->mm.bound_list, global_list);
6299f992
CW		 359 seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n",
360 count, mappable_count, size, mappable_size);
361
362 size = count = mappable_size = mappable_count = 0;
ca191b13 363 count_vmas(&vm->active_list, mm_list);
6299f992
CW		 364 seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n",
365 count, mappable_count, size, mappable_size);
366
6299f992 367 size = count = mappable_size = mappable_count = 0;
ca191b13 368 count_vmas(&vm->inactive_list, mm_list);
6299f992
CW		 369 seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n",
370 count, mappable_count, size, mappable_size);
371
b7abb714 372 size = count = purgeable_size = purgeable_count = 0;
35c20a60 373 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
6c085a72 374 size += obj->base.size, ++count;
b7abb714
CW		 375 if (obj->madv == I915_MADV_DONTNEED)
376 purgeable_size += obj->base.size, ++purgeable_count;
377 }
6c085a72
CW		 378 seq_printf(m, "%u unbound objects, %zu bytes\n", count, size);
379
6299f992 380 size = count = mappable_size = mappable_count = 0;
35c20a60 381 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
6299f992 382 if (obj->fault_mappable) {
f343c5f6 383 size += i915_gem_obj_ggtt_size(obj);
6299f992
CW		 384 ++count;
385 }
386 if (obj->pin_mappable) {
f343c5f6 387 mappable_size += i915_gem_obj_ggtt_size(obj);
6299f992
CW		 388 ++mappable_count;
389 }
b7abb714
CW		 390 if (obj->madv == I915_MADV_DONTNEED) {
391 purgeable_size += obj->base.size;
392 ++purgeable_count;
393 }
6299f992 394 }
b7abb714
CW		 395 seq_printf(m, "%u purgeable objects, %zu bytes\n",
396 purgeable_count, purgeable_size);
6299f992
CW		 397 seq_printf(m, "%u pinned mappable objects, %zu bytes\n",
398 mappable_count, mappable_size);
399 seq_printf(m, "%u fault mappable objects, %zu bytes\n",
400 count, size);
401
93d18799 402 seq_printf(m, "%zu [%lu] gtt total\n",
853ba5d2
BW		 403 dev_priv->gtt.base.total,
404 dev_priv->gtt.mappable_end - dev_priv->gtt.base.start);
73aa808f 405
267f0c90 406 seq_putc(m, '\n');
2db8e9d6
CW		 407 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
408 struct file_stats stats;
409
410 memset(&stats, 0, sizeof(stats));
411 idr_for_each(&file->object_idr, per_file_stats, &stats);
412 seq_printf(m, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu unbound)\n",
413 get_pid_task(file->pid, PIDTYPE_PID)->comm,
414 stats.count,
415 stats.total,
416 stats.active,
417 stats.inactive,
418 stats.unbound);
419 }
420
73aa808f
CW		 421 mutex_unlock(&dev->struct_mutex);
422
423 return 0;
424}
425
aee56cff 426static int i915_gem_gtt_info(struct seq_file *m, void *data)
08c18323
CW		 427{
428 struct drm_info_node *node = (struct drm_info_node *) m->private;
429 struct drm_device *dev = node->minor->dev;
1b50247a 430 uintptr_t list = (uintptr_t) node->info_ent->data;
08c18323
CW		 431 struct drm_i915_private *dev_priv = dev->dev_private;
432 struct drm_i915_gem_object *obj;
433 size_t total_obj_size, total_gtt_size;
434 int count, ret;
435
436 ret = mutex_lock_interruptible(&dev->struct_mutex);
437 if (ret)
438 return ret;
439
440 total_obj_size = total_gtt_size = count = 0;
35c20a60 441 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
1b50247a
CW		 442 if (list == PINNED_LIST && obj->pin_count == 0)
443 continue;
444
267f0c90 445 seq_puts(m, " ");
08c18323 446 describe_obj(m, obj);
267f0c90 447 seq_putc(m, '\n');
08c18323 448 total_obj_size += obj->base.size;
f343c5f6 449 total_gtt_size += i915_gem_obj_ggtt_size(obj);
08c18323
CW		 450 count++;
451 }
452
453 mutex_unlock(&dev->struct_mutex);
454
455 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
456 count, total_obj_size, total_gtt_size);
457
458 return 0;
459}
460
4e5359cd
SF		 461static int i915_gem_pageflip_info(struct seq_file *m, void *data)
462{
463 struct drm_info_node *node = (struct drm_info_node *) m->private;
464 struct drm_device *dev = node->minor->dev;
465 unsigned long flags;
466 struct intel_crtc *crtc;
467
468 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
9db4a9c7
JB		 469 const char pipe = pipe_name(crtc->pipe);
470 const char plane = plane_name(crtc->plane);
4e5359cd
SF		 471 struct intel_unpin_work *work;
472
473 spin_lock_irqsave(&dev->event_lock, flags);
474 work = crtc->unpin_work;
475 if (work == NULL) {
9db4a9c7 476 seq_printf(m, "No flip due on pipe %c (plane %c)\n",
4e5359cd
SF		 477 pipe, plane);
478 } else {
e7d841ca 479 if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9db4a9c7 480 seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
4e5359cd
SF		 481 pipe, plane);
482 } else {
9db4a9c7 483 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
4e5359cd
SF		 484 pipe, plane);
485 }
486 if (work->enable_stall_check)
267f0c90 487 seq_puts(m, "Stall check enabled, ");
4e5359cd 488 else
267f0c90 489 seq_puts(m, "Stall check waiting for page flip ioctl, ");
e7d841ca 490 seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
4e5359cd
SF		 491
492 if (work->old_fb_obj) {
05394f39
CW		 493 struct drm_i915_gem_object *obj = work->old_fb_obj;
494 if (obj)
f343c5f6
BW		 495 seq_printf(m, "Old framebuffer gtt_offset 0x%08lx\n",
496 i915_gem_obj_ggtt_offset(obj));
4e5359cd
SF		 497 }
498 if (work->pending_flip_obj) {
05394f39
CW		 499 struct drm_i915_gem_object *obj = work->pending_flip_obj;
500 if (obj)
f343c5f6
BW		 501 seq_printf(m, "New framebuffer gtt_offset 0x%08lx\n",
502 i915_gem_obj_ggtt_offset(obj));
4e5359cd
SF		 503 }
504 }
505 spin_unlock_irqrestore(&dev->event_lock, flags);
506 }
507
508 return 0;
509}
510
2017263e
BG		 511static int i915_gem_request_info(struct seq_file *m, void *data)
512{
513 struct drm_info_node *node = (struct drm_info_node *) m->private;
514 struct drm_device *dev = node->minor->dev;
515 drm_i915_private_t *dev_priv = dev->dev_private;
a2c7f6fd 516 struct intel_ring_buffer *ring;
2017263e 517 struct drm_i915_gem_request *gem_request;
a2c7f6fd 518 int ret, count, i;
de227ef0
CW		 519
520 ret = mutex_lock_interruptible(&dev->struct_mutex);
521 if (ret)
522 return ret;
2017263e 523
c2c347a9 524 count = 0;
a2c7f6fd
CW		 525 for_each_ring(ring, dev_priv, i) {
526 if (list_empty(&ring->request_list))
527 continue;
528
529 seq_printf(m, "%s requests:\n", ring->name);
c2c347a9 530 list_for_each_entry(gem_request,
a2c7f6fd 531 &ring->request_list,
c2c347a9
CW		 532 list) {
533 seq_printf(m, " %d @ %d\n",
534 gem_request->seqno,
535 (int) (jiffies - gem_request->emitted_jiffies));
536 }
537 count++;
2017263e 538 }
de227ef0
CW		 539 mutex_unlock(&dev->struct_mutex);
540
c2c347a9 541 if (count == 0)
267f0c90 542 seq_puts(m, "No requests\n");
c2c347a9 543
2017263e
BG		 544 return 0;
545}
546
b2223497
CW		 547static void i915_ring_seqno_info(struct seq_file *m,
548 struct intel_ring_buffer *ring)
549{
550 if (ring->get_seqno) {
43a7b924 551 seq_printf(m, "Current sequence (%s): %u\n",
b2eadbc8 552 ring->name, ring->get_seqno(ring, false));
b2223497
CW		 553 }
554}
555
2017263e
BG		 556static int i915_gem_seqno_info(struct seq_file *m, void *data)
557{
558 struct drm_info_node *node = (struct drm_info_node *) m->private;
559 struct drm_device *dev = node->minor->dev;
560 drm_i915_private_t *dev_priv = dev->dev_private;
a2c7f6fd 561 struct intel_ring_buffer *ring;
1ec14ad3 562 int ret, i;
de227ef0
CW		 563
564 ret = mutex_lock_interruptible(&dev->struct_mutex);
565 if (ret)
566 return ret;
2017263e 567
a2c7f6fd
CW		 568 for_each_ring(ring, dev_priv, i)
569 i915_ring_seqno_info(m, ring);
de227ef0
CW		 570
571 mutex_unlock(&dev->struct_mutex);
572
2017263e
BG		 573 return 0;
574}
575
576
577static int i915_interrupt_info(struct seq_file *m, void *data)
578{
579 struct drm_info_node *node = (struct drm_info_node *) m->private;
580 struct drm_device *dev = node->minor->dev;
581 drm_i915_private_t *dev_priv = dev->dev_private;
a2c7f6fd 582 struct intel_ring_buffer *ring;
9db4a9c7 583 int ret, i, pipe;
de227ef0
CW		 584
585 ret = mutex_lock_interruptible(&dev->struct_mutex);
586 if (ret)
587 return ret;
2017263e 588
7e231dbe
JB		 589 if (IS_VALLEYVIEW(dev)) {
590 seq_printf(m, "Display IER:\t%08x\n",
591 I915_READ(VLV_IER));
592 seq_printf(m, "Display IIR:\t%08x\n",
593 I915_READ(VLV_IIR));
594 seq_printf(m, "Display IIR_RW:\t%08x\n",
595 I915_READ(VLV_IIR_RW));
596 seq_printf(m, "Display IMR:\t%08x\n",
597 I915_READ(VLV_IMR));
598 for_each_pipe(pipe)
599 seq_printf(m, "Pipe %c stat:\t%08x\n",
600 pipe_name(pipe),
601 I915_READ(PIPESTAT(pipe)));
602
603 seq_printf(m, "Master IER:\t%08x\n",
604 I915_READ(VLV_MASTER_IER));
605
606 seq_printf(m, "Render IER:\t%08x\n",
607 I915_READ(GTIER));
608 seq_printf(m, "Render IIR:\t%08x\n",
609 I915_READ(GTIIR));
610 seq_printf(m, "Render IMR:\t%08x\n",
611 I915_READ(GTIMR));
612
613 seq_printf(m, "PM IER:\t\t%08x\n",
614 I915_READ(GEN6_PMIER));
615 seq_printf(m, "PM IIR:\t\t%08x\n",
616 I915_READ(GEN6_PMIIR));
617 seq_printf(m, "PM IMR:\t\t%08x\n",
618 I915_READ(GEN6_PMIMR));
619
620 seq_printf(m, "Port hotplug:\t%08x\n",
621 I915_READ(PORT_HOTPLUG_EN));
622 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
623 I915_READ(VLV_DPFLIPSTAT));
624 seq_printf(m, "DPINVGTT:\t%08x\n",
625 I915_READ(DPINVGTT));
626
627 } else if (!HAS_PCH_SPLIT(dev)) {
5f6a1695
ZW		 628 seq_printf(m, "Interrupt enable: %08x\n",
629 I915_READ(IER));
630 seq_printf(m, "Interrupt identity: %08x\n",
631 I915_READ(IIR));
632 seq_printf(m, "Interrupt mask: %08x\n",
633 I915_READ(IMR));
9db4a9c7
JB		 634 for_each_pipe(pipe)
635 seq_printf(m, "Pipe %c stat: %08x\n",
636 pipe_name(pipe),
637 I915_READ(PIPESTAT(pipe)));
5f6a1695
ZW		 638 } else {
639 seq_printf(m, "North Display Interrupt enable: %08x\n",
640 I915_READ(DEIER));
641 seq_printf(m, "North Display Interrupt identity: %08x\n",
642 I915_READ(DEIIR));
643 seq_printf(m, "North Display Interrupt mask: %08x\n",
644 I915_READ(DEIMR));
645 seq_printf(m, "South Display Interrupt enable: %08x\n",
646 I915_READ(SDEIER));
647 seq_printf(m, "South Display Interrupt identity: %08x\n",
648 I915_READ(SDEIIR));
649 seq_printf(m, "South Display Interrupt mask: %08x\n",
650 I915_READ(SDEIMR));
651 seq_printf(m, "Graphics Interrupt enable: %08x\n",
652 I915_READ(GTIER));
653 seq_printf(m, "Graphics Interrupt identity: %08x\n",
654 I915_READ(GTIIR));
655 seq_printf(m, "Graphics Interrupt mask: %08x\n",
656 I915_READ(GTIMR));
657 }
2017263e
BG		 658 seq_printf(m, "Interrupts received: %d\n",
659 atomic_read(&dev_priv->irq_received));
a2c7f6fd 660 for_each_ring(ring, dev_priv, i) {
da64c6fc 661 if (IS_GEN6(dev) || IS_GEN7(dev)) {
a2c7f6fd
CW		 662 seq_printf(m,
663 "Graphics Interrupt mask (%s): %08x\n",
664 ring->name, I915_READ_IMR(ring));
9862e600 665 }
a2c7f6fd 666 i915_ring_seqno_info(m, ring);
9862e600 667 }
de227ef0
CW		 668 mutex_unlock(&dev->struct_mutex);
669
2017263e
BG		 670 return 0;
671}
672
a6172a80
CW		 673static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
674{
675 struct drm_info_node *node = (struct drm_info_node *) m->private;
676 struct drm_device *dev = node->minor->dev;
677 drm_i915_private_t *dev_priv = dev->dev_private;
de227ef0
CW		 678 int i, ret;
679
680 ret = mutex_lock_interruptible(&dev->struct_mutex);
681 if (ret)
682 return ret;
a6172a80
CW		 683
684 seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
685 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
686 for (i = 0; i < dev_priv->num_fence_regs; i++) {
05394f39 687 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
a6172a80 688
6c085a72
CW		 689 seq_printf(m, "Fence %d, pin count = %d, object = ",
690 i, dev_priv->fence_regs[i].pin_count);
c2c347a9 691 if (obj == NULL)
267f0c90 692 seq_puts(m, "unused");
c2c347a9 693 else
05394f39 694 describe_obj(m, obj);
267f0c90 695 seq_putc(m, '\n');
a6172a80
CW		 696 }
697
05394f39 698 mutex_unlock(&dev->struct_mutex);
a6172a80
CW		 699 return 0;
700}
701
2017263e
BG		 702static int i915_hws_info(struct seq_file *m, void *data)
703{
704 struct drm_info_node *node = (struct drm_info_node *) m->private;
705 struct drm_device *dev = node->minor->dev;
706 drm_i915_private_t *dev_priv = dev->dev_private;
4066c0ae 707 struct intel_ring_buffer *ring;
1a240d4d 708 const u32 *hws;
4066c0ae
CW		 709 int i;
710
1ec14ad3 711 ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
1a240d4d 712 hws = ring->status_page.page_addr;
2017263e
BG		 713 if (hws == NULL)
714 return 0;
715
716 for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
717 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
718 i * 4,
719 hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
720 }
721 return 0;
722}
723
d5442303
DV		 724static ssize_t
725i915_error_state_write(struct file *filp,
726 const char __user *ubuf,
727 size_t cnt,
728 loff_t *ppos)
729{
edc3d884 730 struct i915_error_state_file_priv *error_priv = filp->private_data;
d5442303 731 struct drm_device *dev = error_priv->dev;
22bcfc6a 732 int ret;
d5442303
DV		 733
734 DRM_DEBUG_DRIVER("Resetting error state\n");
735
22bcfc6a
DV		 736 ret = mutex_lock_interruptible(&dev->struct_mutex);
737 if (ret)
738 return ret;
739
d5442303
DV		 740 i915_destroy_error_state(dev);
741 mutex_unlock(&dev->struct_mutex);
742
743 return cnt;
744}
745
746static int i915_error_state_open(struct inode *inode, struct file *file)
747{
748 struct drm_device *dev = inode->i_private;
d5442303 749 struct i915_error_state_file_priv *error_priv;
d5442303
DV		 750
751 error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
752 if (!error_priv)
753 return -ENOMEM;
754
755 error_priv->dev = dev;
756
95d5bfb3 757 i915_error_state_get(dev, error_priv);
d5442303 758
edc3d884
MK		 759 file->private_data = error_priv;
760
761 return 0;
d5442303
DV		 762}
763
764static int i915_error_state_release(struct inode *inode, struct file *file)
765{
edc3d884 766 struct i915_error_state_file_priv *error_priv = file->private_data;
d5442303 767
95d5bfb3 768 i915_error_state_put(error_priv);
d5442303
DV		 769 kfree(error_priv);
770
edc3d884
MK		 771 return 0;
772}
773
4dc955f7
MK		 774static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
775 size_t count, loff_t *pos)
776{
777 struct i915_error_state_file_priv *error_priv = file->private_data;
778 struct drm_i915_error_state_buf error_str;
779 loff_t tmp_pos = 0;
780 ssize_t ret_count = 0;
781 int ret;
782
783 ret = i915_error_state_buf_init(&error_str, count, *pos);
784 if (ret)
785 return ret;
edc3d884 786
fc16b48b 787 ret = i915_error_state_to_str(&error_str, error_priv);
edc3d884
MK		 788 if (ret)
789 goto out;
790
edc3d884
MK		 791 ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
792 error_str.buf,
793 error_str.bytes);
794
795 if (ret_count < 0)
796 ret = ret_count;
797 else
798 *pos = error_str.start + ret_count;
799out:
4dc955f7 800 i915_error_state_buf_release(&error_str);
edc3d884 801 return ret ?: ret_count;
d5442303
DV		 802}
803
804static const struct file_operations i915_error_state_fops = {
805 .owner = THIS_MODULE,
806 .open = i915_error_state_open,
edc3d884 807 .read = i915_error_state_read,
d5442303
DV		 808 .write = i915_error_state_write,
809 .llseek = default_llseek,
810 .release = i915_error_state_release,
811};
812
647416f9
KC		 813static int
814i915_next_seqno_get(void *data, u64 *val)
40633219 815{
647416f9 816 struct drm_device *dev = data;
40633219 817 drm_i915_private_t *dev_priv = dev->dev_private;
40633219
MK		 818 int ret;
819
820 ret = mutex_lock_interruptible(&dev->struct_mutex);
821 if (ret)
822 return ret;
823
647416f9 824 *val = dev_priv->next_seqno;
40633219
MK		 825 mutex_unlock(&dev->struct_mutex);
826
647416f9 827 return 0;
40633219
MK		 828}
829
647416f9
KC		 830static int
831i915_next_seqno_set(void *data, u64 val)
832{
833 struct drm_device *dev = data;
40633219
MK		 834 int ret;
835
40633219
MK		 836 ret = mutex_lock_interruptible(&dev->struct_mutex);
837 if (ret)
838 return ret;
839
e94fbaa8 840 ret = i915_gem_set_seqno(dev, val);
40633219
MK		 841 mutex_unlock(&dev->struct_mutex);
842
647416f9 843 return ret;
40633219
MK		 844}
845
647416f9
KC		 846DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
847 i915_next_seqno_get, i915_next_seqno_set,
3a3b4f98 848 "0x%llx\n");
40633219 849
f97108d1
JB		 850static int i915_rstdby_delays(struct seq_file *m, void *unused)
851{
852 struct drm_info_node *node = (struct drm_info_node *) m->private;
853 struct drm_device *dev = node->minor->dev;
854 drm_i915_private_t *dev_priv = dev->dev_private;
616fdb5a
BW		 855 u16 crstanddelay;
856 int ret;
857
858 ret = mutex_lock_interruptible(&dev->struct_mutex);
859 if (ret)
860 return ret;
861
862 crstanddelay = I915_READ16(CRSTANDVID);
863
864 mutex_unlock(&dev->struct_mutex);
f97108d1
JB		 865
866 seq_printf(m, "w/ctx: %d, w/o ctx: %d\n", (crstanddelay >> 8) & 0x3f, (crstanddelay & 0x3f));
867
868 return 0;
869}
870
871static int i915_cur_delayinfo(struct seq_file *m, void *unused)
872{
873 struct drm_info_node *node = (struct drm_info_node *) m->private;
874 struct drm_device *dev = node->minor->dev;
875 drm_i915_private_t *dev_priv = dev->dev_private;
d1ebd816 876 int ret;
3b8d8d91 877
5c9669ce
TR		 878 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
879
3b8d8d91
JB		 880 if (IS_GEN5(dev)) {
881 u16 rgvswctl = I915_READ16(MEMSWCTL);
882 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
883
884 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
885 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
886 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
887 MEMSTAT_VID_SHIFT);
888 seq_printf(m, "Current P-state: %d\n",
889 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
0a073b84 890 } else if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) {
3b8d8d91
JB		 891 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
892 u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
893 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
8e8c06cd 894 u32 rpstat, cagf, reqf;
ccab5c82
JB		 895 u32 rpupei, rpcurup, rpprevup;
896 u32 rpdownei, rpcurdown, rpprevdown;
3b8d8d91
JB		 897 int max_freq;
898
899 /* RPSTAT1 is in the GT power well */
d1ebd816
BW		 900 ret = mutex_lock_interruptible(&dev->struct_mutex);
901 if (ret)
902 return ret;
903
fcca7926 904 gen6_gt_force_wake_get(dev_priv);
3b8d8d91 905
8e8c06cd
CW		 906 reqf = I915_READ(GEN6_RPNSWREQ);
907 reqf &= ~GEN6_TURBO_DISABLE;
908 if (IS_HASWELL(dev))
909 reqf >>= 24;
910 else
911 reqf >>= 25;
912 reqf *= GT_FREQUENCY_MULTIPLIER;
913
ccab5c82
JB		 914 rpstat = I915_READ(GEN6_RPSTAT1);
915 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
916 rpcurup = I915_READ(GEN6_RP_CUR_UP);
917 rpprevup = I915_READ(GEN6_RP_PREV_UP);
918 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
919 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
920 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
f82855d3
BW		 921 if (IS_HASWELL(dev))
922 cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
923 else
924 cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
925 cagf *= GT_FREQUENCY_MULTIPLIER;
ccab5c82 926
d1ebd816
BW		 927 gen6_gt_force_wake_put(dev_priv);
928 mutex_unlock(&dev->struct_mutex);
929
3b8d8d91 930 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
ccab5c82 931 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
3b8d8d91
JB		 932 seq_printf(m, "Render p-state ratio: %d\n",
933 (gt_perf_status & 0xff00) >> 8);
934 seq_printf(m, "Render p-state VID: %d\n",
935 gt_perf_status & 0xff);
936 seq_printf(m, "Render p-state limit: %d\n",
937 rp_state_limits & 0xff);
8e8c06cd 938 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
f82855d3 939 seq_printf(m, "CAGF: %dMHz\n", cagf);
ccab5c82
JB		 940 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
941 GEN6_CURICONT_MASK);
942 seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
943 GEN6_CURBSYTAVG_MASK);
944 seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
945 GEN6_CURBSYTAVG_MASK);
946 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
947 GEN6_CURIAVG_MASK);
948 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
949 GEN6_CURBSYTAVG_MASK);
950 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
951 GEN6_CURBSYTAVG_MASK);
3b8d8d91
JB		 952
953 max_freq = (rp_state_cap & 0xff0000) >> 16;
954 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
c8735b0c 955 max_freq * GT_FREQUENCY_MULTIPLIER);
3b8d8d91
JB		 956
957 max_freq = (rp_state_cap & 0xff00) >> 8;
958 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
c8735b0c 959 max_freq * GT_FREQUENCY_MULTIPLIER);
3b8d8d91
JB		 960
961 max_freq = rp_state_cap & 0xff;
962 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
c8735b0c 963 max_freq * GT_FREQUENCY_MULTIPLIER);
31c77388
BW		 964
965 seq_printf(m, "Max overclocked frequency: %dMHz\n",
966 dev_priv->rps.hw_max * GT_FREQUENCY_MULTIPLIER);
0a073b84
JB		 967 } else if (IS_VALLEYVIEW(dev)) {
968 u32 freq_sts, val;
969
259bd5d4 970 mutex_lock(&dev_priv->rps.hw_lock);
64936258 971 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
0a073b84
JB		 972 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
973 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
974
64936258 975 val = vlv_punit_read(dev_priv, PUNIT_FUSE_BUS1);
0a073b84
JB		 976 seq_printf(m, "max GPU freq: %d MHz\n",
977 vlv_gpu_freq(dev_priv->mem_freq, val));
978
64936258 979 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM);
0a073b84
JB		 980 seq_printf(m, "min GPU freq: %d MHz\n",
981 vlv_gpu_freq(dev_priv->mem_freq, val));
982
983 seq_printf(m, "current GPU freq: %d MHz\n",
984 vlv_gpu_freq(dev_priv->mem_freq,
985 (freq_sts >> 8) & 0xff));
259bd5d4 986 mutex_unlock(&dev_priv->rps.hw_lock);
3b8d8d91 987 } else {
267f0c90 988 seq_puts(m, "no P-state info available\n");
3b8d8d91 989 }
f97108d1
JB		 990
991 return 0;
992}
993
994static int i915_delayfreq_table(struct seq_file *m, void *unused)
995{
996 struct drm_info_node *node = (struct drm_info_node *) m->private;
997 struct drm_device *dev = node->minor->dev;
998 drm_i915_private_t *dev_priv = dev->dev_private;
999 u32 delayfreq;
616fdb5a
BW		 1000 int ret, i;
1001
1002 ret = mutex_lock_interruptible(&dev->struct_mutex);
1003 if (ret)
1004 return ret;
f97108d1
JB		 1005
1006 for (i = 0; i < 16; i++) {
1007 delayfreq = I915_READ(PXVFREQ_BASE + i * 4);
7648fa99
JB		 1008 seq_printf(m, "P%02dVIDFREQ: 0x%08x (VID: %d)\n", i, delayfreq,
1009 (delayfreq & PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT);
f97108d1
JB		 1010 }
1011
616fdb5a
BW		 1012 mutex_unlock(&dev->struct_mutex);
1013
f97108d1
JB		 1014 return 0;
1015}
1016
1017static inline int MAP_TO_MV(int map)
1018{
1019 return 1250 - (map * 25);
1020}
1021
1022static int i915_inttoext_table(struct seq_file *m, void *unused)
1023{
1024 struct drm_info_node *node = (struct drm_info_node *) m->private;
1025 struct drm_device *dev = node->minor->dev;
1026 drm_i915_private_t *dev_priv = dev->dev_private;
1027 u32 inttoext;
616fdb5a
BW		 1028 int ret, i;
1029
1030 ret = mutex_lock_interruptible(&dev->struct_mutex);
1031 if (ret)
1032 return ret;
f97108d1
JB		 1033
1034 for (i = 1; i <= 32; i++) {
1035 inttoext = I915_READ(INTTOEXT_BASE_ILK + i * 4);
1036 seq_printf(m, "INTTOEXT%02d: 0x%08x\n", i, inttoext);
1037 }
1038
616fdb5a
BW		 1039 mutex_unlock(&dev->struct_mutex);
1040
f97108d1
JB		 1041 return 0;
1042}
1043
4d85529d 1044static int ironlake_drpc_info(struct seq_file *m)
f97108d1
JB		 1045{
1046 struct drm_info_node *node = (struct drm_info_node *) m->private;
1047 struct drm_device *dev = node->minor->dev;
1048 drm_i915_private_t *dev_priv = dev->dev_private;
616fdb5a
BW		 1049 u32 rgvmodectl, rstdbyctl;
1050 u16 crstandvid;
1051 int ret;
1052
1053 ret = mutex_lock_interruptible(&dev->struct_mutex);
1054 if (ret)
1055 return ret;
1056
1057 rgvmodectl = I915_READ(MEMMODECTL);
1058 rstdbyctl = I915_READ(RSTDBYCTL);
1059 crstandvid = I915_READ16(CRSTANDVID);
1060
1061 mutex_unlock(&dev->struct_mutex);
f97108d1
JB		 1062
1063 seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
1064 "yes" : "no");
1065 seq_printf(m, "Boost freq: %d\n",
1066 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1067 MEMMODE_BOOST_FREQ_SHIFT);
1068 seq_printf(m, "HW control enabled: %s\n",
1069 rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");
1070 seq_printf(m, "SW control enabled: %s\n",
1071 rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");
1072 seq_printf(m, "Gated voltage change: %s\n",
1073 rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");
1074 seq_printf(m, "Starting frequency: P%d\n",
1075 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
7648fa99 1076 seq_printf(m, "Max P-state: P%d\n",
f97108d1 1077 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
7648fa99
JB		 1078 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1079 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1080 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1081 seq_printf(m, "Render standby enabled: %s\n",
1082 (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes");
267f0c90 1083 seq_puts(m, "Current RS state: ");
88271da3
JB		 1084 switch (rstdbyctl & RSX_STATUS_MASK) {
1085 case RSX_STATUS_ON:
267f0c90 1086 seq_puts(m, "on\n");
88271da3
JB		 1087 break;
1088 case RSX_STATUS_RC1:
267f0c90 1089 seq_puts(m, "RC1\n");
88271da3
JB		 1090 break;
1091 case RSX_STATUS_RC1E:
267f0c90 1092 seq_puts(m, "RC1E\n");
88271da3
JB		 1093 break;
1094 case RSX_STATUS_RS1:
267f0c90 1095 seq_puts(m, "RS1\n");
88271da3
JB		 1096 break;
1097 case RSX_STATUS_RS2:
267f0c90 1098 seq_puts(m, "RS2 (RC6)\n");
88271da3
JB		 1099 break;
1100 case RSX_STATUS_RS3:
267f0c90 1101 seq_puts(m, "RC3 (RC6+)\n");
88271da3
JB		 1102 break;
1103 default:
267f0c90 1104 seq_puts(m, "unknown\n");
88271da3
JB		 1105 break;
1106 }
f97108d1
JB		 1107
1108 return 0;
1109}
1110
4d85529d
BW		 1111static int gen6_drpc_info(struct seq_file *m)
1112{
1113
1114 struct drm_info_node *node = (struct drm_info_node *) m->private;
1115 struct drm_device *dev = node->minor->dev;
1116 struct drm_i915_private *dev_priv = dev->dev_private;
ecd8faea 1117 u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
93b525dc 1118 unsigned forcewake_count;
aee56cff 1119 int count = 0, ret;
4d85529d
BW		 1120
1121 ret = mutex_lock_interruptible(&dev->struct_mutex);
1122 if (ret)
1123 return ret;
1124
907b28c5
CW		 1125 spin_lock_irq(&dev_priv->uncore.lock);
1126 forcewake_count = dev_priv->uncore.forcewake_count;
1127 spin_unlock_irq(&dev_priv->uncore.lock);
93b525dc
DV		 1128
1129 if (forcewake_count) {
267f0c90
DL		 1130 seq_puts(m, "RC information inaccurate because somebody "
1131 "holds a forcewake reference \n");
4d85529d
BW		 1132 } else {
1133 /* NB: we cannot use forcewake, else we read the wrong values */
1134 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1135 udelay(10);
1136 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1137 }
1138
1139 gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS);
ed71f1b4 1140 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
4d85529d
BW		 1141
1142 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1143 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1144 mutex_unlock(&dev->struct_mutex);
44cbd338
BW		 1145 mutex_lock(&dev_priv->rps.hw_lock);
1146 sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1147 mutex_unlock(&dev_priv->rps.hw_lock);
4d85529d
BW		 1148
1149 seq_printf(m, "Video Turbo Mode: %s\n",
1150 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1151 seq_printf(m, "HW control enabled: %s\n",
1152 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1153 seq_printf(m, "SW control enabled: %s\n",
1154 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1155 GEN6_RP_MEDIA_SW_MODE));
fff24e21 1156 seq_printf(m, "RC1e Enabled: %s\n",
4d85529d
BW		 1157 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1158 seq_printf(m, "RC6 Enabled: %s\n",
1159 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1160 seq_printf(m, "Deep RC6 Enabled: %s\n",
1161 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1162 seq_printf(m, "Deepest RC6 Enabled: %s\n",
1163 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
267f0c90 1164 seq_puts(m, "Current RC state: ");
4d85529d
BW		 1165 switch (gt_core_status & GEN6_RCn_MASK) {
1166 case GEN6_RC0:
1167 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
267f0c90 1168 seq_puts(m, "Core Power Down\n");
4d85529d 1169 else
267f0c90 1170 seq_puts(m, "on\n");
4d85529d
BW		 1171 break;
1172 case GEN6_RC3:
267f0c90 1173 seq_puts(m, "RC3\n");
4d85529d
BW		 1174 break;
1175 case GEN6_RC6:
267f0c90 1176 seq_puts(m, "RC6\n");
4d85529d
BW		 1177 break;
1178 case GEN6_RC7:
267f0c90 1179 seq_puts(m, "RC7\n");
4d85529d
BW		 1180 break;
1181 default:
267f0c90 1182 seq_puts(m, "Unknown\n");
4d85529d
BW		 1183 break;
1184 }
1185
1186 seq_printf(m, "Core Power Down: %s\n",
1187 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
cce66a28
BW		 1188
1189 /* Not exactly sure what this is */
1190 seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1191 I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1192 seq_printf(m, "RC6 residency since boot: %u\n",
1193 I915_READ(GEN6_GT_GFX_RC6));
1194 seq_printf(m, "RC6+ residency since boot: %u\n",
1195 I915_READ(GEN6_GT_GFX_RC6p));
1196 seq_printf(m, "RC6++ residency since boot: %u\n",
1197 I915_READ(GEN6_GT_GFX_RC6pp));
1198
ecd8faea
BW		 1199 seq_printf(m, "RC6 voltage: %dmV\n",
1200 GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1201 seq_printf(m, "RC6+ voltage: %dmV\n",
1202 GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1203 seq_printf(m, "RC6++ voltage: %dmV\n",
1204 GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
4d85529d
BW		 1205 return 0;
1206}
1207
1208static int i915_drpc_info(struct seq_file *m, void *unused)
1209{
1210 struct drm_info_node *node = (struct drm_info_node *) m->private;
1211 struct drm_device *dev = node->minor->dev;
1212
1213 if (IS_GEN6(dev) || IS_GEN7(dev))
1214 return gen6_drpc_info(m);
1215 else
1216 return ironlake_drpc_info(m);
1217}
1218
b5e50c3f
JB		 1219static int i915_fbc_status(struct seq_file *m, void *unused)
1220{
1221 struct drm_info_node *node = (struct drm_info_node *) m->private;
1222 struct drm_device *dev = node->minor->dev;
b5e50c3f 1223 drm_i915_private_t *dev_priv = dev->dev_private;
b5e50c3f 1224
ee5382ae 1225 if (!I915_HAS_FBC(dev)) {
267f0c90 1226 seq_puts(m, "FBC unsupported on this chipset\n");
b5e50c3f
JB		 1227 return 0;
1228 }
1229
ee5382ae 1230 if (intel_fbc_enabled(dev)) {
267f0c90 1231 seq_puts(m, "FBC enabled\n");
b5e50c3f 1232 } else {
267f0c90 1233 seq_puts(m, "FBC disabled: ");
5c3fe8b0 1234 switch (dev_priv->fbc.no_fbc_reason) {
29ebf90f
CW		 1235 case FBC_OK:
1236 seq_puts(m, "FBC actived, but currently disabled in hardware");
1237 break;
1238 case FBC_UNSUPPORTED:
1239 seq_puts(m, "unsupported by this chipset");
1240 break;
bed4a673 1241 case FBC_NO_OUTPUT:
267f0c90 1242 seq_puts(m, "no outputs");
bed4a673 1243 break;
b5e50c3f 1244 case FBC_STOLEN_TOO_SMALL:
267f0c90 1245 seq_puts(m, "not enough stolen memory");
b5e50c3f
JB		 1246 break;
1247 case FBC_UNSUPPORTED_MODE:
267f0c90 1248 seq_puts(m, "mode not supported");
b5e50c3f
JB		 1249 break;
1250 case FBC_MODE_TOO_LARGE:
267f0c90 1251 seq_puts(m, "mode too large");
b5e50c3f
JB		 1252 break;
1253 case FBC_BAD_PLANE:
267f0c90 1254 seq_puts(m, "FBC unsupported on plane");
b5e50c3f
JB		 1255 break;
1256 case FBC_NOT_TILED:
267f0c90 1257 seq_puts(m, "scanout buffer not tiled");
b5e50c3f 1258 break;
9c928d16 1259 case FBC_MULTIPLE_PIPES:
267f0c90 1260 seq_puts(m, "multiple pipes are enabled");
9c928d16 1261 break;
c1a9f047 1262 case FBC_MODULE_PARAM:
267f0c90 1263 seq_puts(m, "disabled per module param (default off)");
c1a9f047 1264 break;
8a5729a3 1265 case FBC_CHIP_DEFAULT:
267f0c90 1266 seq_puts(m, "disabled per chip default");
8a5729a3 1267 break;
b5e50c3f 1268 default:
267f0c90 1269 seq_puts(m, "unknown reason");
b5e50c3f 1270 }
267f0c90 1271 seq_putc(m, '\n');
b5e50c3f
JB		 1272 }
1273 return 0;
1274}
1275
92d44621
PZ		 1276static int i915_ips_status(struct seq_file *m, void *unused)
1277{
1278 struct drm_info_node *node = (struct drm_info_node *) m->private;
1279 struct drm_device *dev = node->minor->dev;
1280 struct drm_i915_private *dev_priv = dev->dev_private;
1281
f5adf94e 1282 if (!HAS_IPS(dev)) {
92d44621
PZ		 1283 seq_puts(m, "not supported\n");
1284 return 0;
1285 }
1286
1287 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1288 seq_puts(m, "enabled\n");
1289 else
1290 seq_puts(m, "disabled\n");
1291
1292 return 0;
1293}
1294
4a9bef37
JB		 1295static int i915_sr_status(struct seq_file *m, void *unused)
1296{
1297 struct drm_info_node *node = (struct drm_info_node *) m->private;
1298 struct drm_device *dev = node->minor->dev;
1299 drm_i915_private_t *dev_priv = dev->dev_private;
1300 bool sr_enabled = false;
1301
1398261a 1302 if (HAS_PCH_SPLIT(dev))
5ba2aaaa 1303 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
a6c45cf0 1304 else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))
4a9bef37
JB		 1305 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1306 else if (IS_I915GM(dev))
1307 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1308 else if (IS_PINEVIEW(dev))
1309 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1310
5ba2aaaa
CW		 1311 seq_printf(m, "self-refresh: %s\n",
1312 sr_enabled ? "enabled" : "disabled");
4a9bef37
JB		 1313
1314 return 0;
1315}
1316
7648fa99
JB		 1317static int i915_emon_status(struct seq_file *m, void *unused)
1318{
1319 struct drm_info_node *node = (struct drm_info_node *) m->private;
1320 struct drm_device *dev = node->minor->dev;
1321 drm_i915_private_t *dev_priv = dev->dev_private;
1322 unsigned long temp, chipset, gfx;
de227ef0
CW		 1323 int ret;
1324
582be6b4
CW		 1325 if (!IS_GEN5(dev))
1326 return -ENODEV;
1327
de227ef0
CW		 1328 ret = mutex_lock_interruptible(&dev->struct_mutex);
1329 if (ret)
1330 return ret;
7648fa99
JB		 1331
1332 temp = i915_mch_val(dev_priv);
1333 chipset = i915_chipset_val(dev_priv);
1334 gfx = i915_gfx_val(dev_priv);
de227ef0 1335 mutex_unlock(&dev->struct_mutex);
7648fa99
JB		 1336
1337 seq_printf(m, "GMCH temp: %ld\n", temp);
1338 seq_printf(m, "Chipset power: %ld\n", chipset);
1339 seq_printf(m, "GFX power: %ld\n", gfx);
1340 seq_printf(m, "Total power: %ld\n", chipset + gfx);
1341
1342 return 0;
1343}
1344
23b2f8bb
JB		 1345static int i915_ring_freq_table(struct seq_file *m, void *unused)
1346{
1347 struct drm_info_node *node = (struct drm_info_node *) m->private;
1348 struct drm_device *dev = node->minor->dev;
1349 drm_i915_private_t *dev_priv = dev->dev_private;
1350 int ret;
1351 int gpu_freq, ia_freq;
1352
1c70c0ce 1353 if (!(IS_GEN6(dev) || IS_GEN7(dev))) {
267f0c90 1354 seq_puts(m, "unsupported on this chipset\n");
23b2f8bb
JB		 1355 return 0;
1356 }
1357
5c9669ce
TR		 1358 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1359
4fc688ce 1360 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
23b2f8bb
JB		 1361 if (ret)
1362 return ret;
1363
267f0c90 1364 seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
23b2f8bb 1365
c6a828d3
DV		 1366 for (gpu_freq = dev_priv->rps.min_delay;
1367 gpu_freq <= dev_priv->rps.max_delay;
23b2f8bb 1368 gpu_freq++) {
42c0526c
BW		 1369 ia_freq = gpu_freq;
1370 sandybridge_pcode_read(dev_priv,
1371 GEN6_PCODE_READ_MIN_FREQ_TABLE,
1372 &ia_freq);
3ebecd07
CW		 1373 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1374 gpu_freq * GT_FREQUENCY_MULTIPLIER,
1375 ((ia_freq >> 0) & 0xff) * 100,
1376 ((ia_freq >> 8) & 0xff) * 100);
23b2f8bb
JB		 1377 }
1378
4fc688ce 1379 mutex_unlock(&dev_priv->rps.hw_lock);
23b2f8bb
JB		 1380
1381 return 0;
1382}
1383
7648fa99
JB		 1384static int i915_gfxec(struct seq_file *m, void *unused)
1385{
1386 struct drm_info_node *node = (struct drm_info_node *) m->private;
1387 struct drm_device *dev = node->minor->dev;
1388 drm_i915_private_t *dev_priv = dev->dev_private;
616fdb5a
BW		 1389 int ret;
1390
1391 ret = mutex_lock_interruptible(&dev->struct_mutex);
1392 if (ret)
1393 return ret;
7648fa99
JB		 1394
1395 seq_printf(m, "GFXEC: %ld\n", (unsigned long)I915_READ(0x112f4));
1396
616fdb5a
BW		 1397 mutex_unlock(&dev->struct_mutex);
1398
7648fa99
JB		 1399 return 0;
1400}
1401
44834a67
CW		 1402static int i915_opregion(struct seq_file *m, void *unused)
1403{
1404 struct drm_info_node *node = (struct drm_info_node *) m->private;
1405 struct drm_device *dev = node->minor->dev;
1406 drm_i915_private_t *dev_priv = dev->dev_private;
1407 struct intel_opregion *opregion = &dev_priv->opregion;
0d38f009 1408 void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL);
44834a67
CW		 1409 int ret;
1410
0d38f009
DV		 1411 if (data == NULL)
1412 return -ENOMEM;
1413
44834a67
CW		 1414 ret = mutex_lock_interruptible(&dev->struct_mutex);
1415 if (ret)
0d38f009 1416 goto out;
44834a67 1417
0d38f009
DV		 1418 if (opregion->header) {
1419 memcpy_fromio(data, opregion->header, OPREGION_SIZE);
1420 seq_write(m, data, OPREGION_SIZE);
1421 }
44834a67
CW		 1422
1423 mutex_unlock(&dev->struct_mutex);
1424
0d38f009
DV		 1425out:
1426 kfree(data);
44834a67
CW		 1427 return 0;
1428}
1429
37811fcc
CW		 1430static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1431{
1432 struct drm_info_node *node = (struct drm_info_node *) m->private;
1433 struct drm_device *dev = node->minor->dev;
4520f53a 1434 struct intel_fbdev *ifbdev = NULL;
37811fcc 1435 struct intel_framebuffer *fb;
37811fcc 1436
4520f53a
DV		 1437#ifdef CONFIG_DRM_I915_FBDEV
1438 struct drm_i915_private *dev_priv = dev->dev_private;
1439 int ret = mutex_lock_interruptible(&dev->mode_config.mutex);
37811fcc
CW		 1440 if (ret)
1441 return ret;
1442
1443 ifbdev = dev_priv->fbdev;
1444 fb = to_intel_framebuffer(ifbdev->helper.fb);
1445
623f9783 1446 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
37811fcc
CW		 1447 fb->base.width,
1448 fb->base.height,
1449 fb->base.depth,
623f9783
DV		 1450 fb->base.bits_per_pixel,
1451 atomic_read(&fb->base.refcount.refcount));
05394f39 1452 describe_obj(m, fb->obj);
267f0c90 1453 seq_putc(m, '\n');
4b096ac1 1454 mutex_unlock(&dev->mode_config.mutex);
4520f53a 1455#endif
37811fcc 1456
4b096ac1 1457 mutex_lock(&dev->mode_config.fb_lock);
37811fcc 1458 list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) {
131a56dc 1459 if (ifbdev && &fb->base == ifbdev->helper.fb)
37811fcc
CW		 1460 continue;
1461
623f9783 1462 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
37811fcc
CW		 1463 fb->base.width,
1464 fb->base.height,
1465 fb->base.depth,
623f9783
DV		 1466 fb->base.bits_per_pixel,
1467 atomic_read(&fb->base.refcount.refcount));
05394f39 1468 describe_obj(m, fb->obj);
267f0c90 1469 seq_putc(m, '\n');
37811fcc 1470 }
4b096ac1 1471 mutex_unlock(&dev->mode_config.fb_lock);
37811fcc
CW		 1472
1473 return 0;
1474}
1475
e76d3630
BW		 1476static int i915_context_status(struct seq_file *m, void *unused)
1477{
1478 struct drm_info_node *node = (struct drm_info_node *) m->private;
1479 struct drm_device *dev = node->minor->dev;
1480 drm_i915_private_t *dev_priv = dev->dev_private;
a168c293 1481 struct intel_ring_buffer *ring;
a33afea5 1482 struct i915_hw_context *ctx;
a168c293 1483 int ret, i;
e76d3630
BW		 1484
1485 ret = mutex_lock_interruptible(&dev->mode_config.mutex);
1486 if (ret)
1487 return ret;
1488
3e373948 1489 if (dev_priv->ips.pwrctx) {
267f0c90 1490 seq_puts(m, "power context ");
3e373948 1491 describe_obj(m, dev_priv->ips.pwrctx);
267f0c90 1492 seq_putc(m, '\n');
dc501fbc 1493 }
e76d3630 1494
3e373948 1495 if (dev_priv->ips.renderctx) {
267f0c90 1496 seq_puts(m, "render context ");
3e373948 1497 describe_obj(m, dev_priv->ips.renderctx);
267f0c90 1498 seq_putc(m, '\n');
dc501fbc 1499 }
e76d3630 1500
a33afea5
BW		 1501 list_for_each_entry(ctx, &dev_priv->context_list, link) {
1502 seq_puts(m, "HW context ");
3ccfd19d 1503 describe_ctx(m, ctx);
a33afea5
BW		 1504 for_each_ring(ring, dev_priv, i)
1505 if (ring->default_context == ctx)
1506 seq_printf(m, "(default context %s) ", ring->name);
1507
1508 describe_obj(m, ctx->obj);
1509 seq_putc(m, '\n');
a168c293
BW		 1510 }
1511
e76d3630
BW		 1512 mutex_unlock(&dev->mode_config.mutex);
1513
1514 return 0;
1515}
1516
6d794d42
BW		 1517static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data)
1518{
1519 struct drm_info_node *node = (struct drm_info_node *) m->private;
1520 struct drm_device *dev = node->minor->dev;
1521 struct drm_i915_private *dev_priv = dev->dev_private;
9f1f46a4 1522 unsigned forcewake_count;
6d794d42 1523
907b28c5
CW		 1524 spin_lock_irq(&dev_priv->uncore.lock);
1525 forcewake_count = dev_priv->uncore.forcewake_count;
1526 spin_unlock_irq(&dev_priv->uncore.lock);
6d794d42 1527
9f1f46a4 1528 seq_printf(m, "forcewake count = %u\n", forcewake_count);
6d794d42
BW		 1529
1530 return 0;
1531}
1532
ea16a3cd
DV		 1533static const char *swizzle_string(unsigned swizzle)
1534{
aee56cff 1535 switch (swizzle) {
ea16a3cd
DV		 1536 case I915_BIT_6_SWIZZLE_NONE:
1537 return "none";
1538 case I915_BIT_6_SWIZZLE_9:
1539 return "bit9";
1540 case I915_BIT_6_SWIZZLE_9_10:
1541 return "bit9/bit10";
1542 case I915_BIT_6_SWIZZLE_9_11:
1543 return "bit9/bit11";
1544 case I915_BIT_6_SWIZZLE_9_10_11:
1545 return "bit9/bit10/bit11";
1546 case I915_BIT_6_SWIZZLE_9_17:
1547 return "bit9/bit17";
1548 case I915_BIT_6_SWIZZLE_9_10_17:
1549 return "bit9/bit10/bit17";
1550 case I915_BIT_6_SWIZZLE_UNKNOWN:
8a168ca7 1551 return "unknown";
ea16a3cd
DV		 1552 }
1553
1554 return "bug";
1555}
1556
1557static int i915_swizzle_info(struct seq_file *m, void *data)
1558{
1559 struct drm_info_node *node = (struct drm_info_node *) m->private;
1560 struct drm_device *dev = node->minor->dev;
1561 struct drm_i915_private *dev_priv = dev->dev_private;
22bcfc6a
DV		 1562 int ret;
1563
1564 ret = mutex_lock_interruptible(&dev->struct_mutex);
1565 if (ret)
1566 return ret;
ea16a3cd 1567
ea16a3cd
DV		 1568 seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
1569 swizzle_string(dev_priv->mm.bit_6_swizzle_x));
1570 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
1571 swizzle_string(dev_priv->mm.bit_6_swizzle_y));
1572
1573 if (IS_GEN3(dev) || IS_GEN4(dev)) {
1574 seq_printf(m, "DDC = 0x%08x\n",
1575 I915_READ(DCC));
1576 seq_printf(m, "C0DRB3 = 0x%04x\n",
1577 I915_READ16(C0DRB3));
1578 seq_printf(m, "C1DRB3 = 0x%04x\n",
1579 I915_READ16(C1DRB3));
3fa7d235
DV		 1580 } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
1581 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
1582 I915_READ(MAD_DIMM_C0));
1583 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
1584 I915_READ(MAD_DIMM_C1));
1585 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
1586 I915_READ(MAD_DIMM_C2));
1587 seq_printf(m, "TILECTL = 0x%08x\n",
1588 I915_READ(TILECTL));
1589 seq_printf(m, "ARB_MODE = 0x%08x\n",
1590 I915_READ(ARB_MODE));
1591 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
1592 I915_READ(DISP_ARB_CTL));
ea16a3cd
DV		 1593 }
1594 mutex_unlock(&dev->struct_mutex);
1595
1596 return 0;
1597}
1598
3cf17fc5
DV		 1599static int i915_ppgtt_info(struct seq_file *m, void *data)
1600{
1601 struct drm_info_node *node = (struct drm_info_node *) m->private;
1602 struct drm_device *dev = node->minor->dev;
1603 struct drm_i915_private *dev_priv = dev->dev_private;
1604 struct intel_ring_buffer *ring;
1605 int i, ret;
1606
1607
1608 ret = mutex_lock_interruptible(&dev->struct_mutex);
1609 if (ret)
1610 return ret;
1611 if (INTEL_INFO(dev)->gen == 6)
1612 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
1613
a2c7f6fd 1614 for_each_ring(ring, dev_priv, i) {
3cf17fc5
DV		 1615 seq_printf(m, "%s\n", ring->name);
1616 if (INTEL_INFO(dev)->gen == 7)
1617 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
1618 seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
1619 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
1620 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring)));
1621 }
1622 if (dev_priv->mm.aliasing_ppgtt) {
1623 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
1624
267f0c90 1625 seq_puts(m, "aliasing PPGTT:\n");
3cf17fc5
DV		 1626 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset);
1627 }
1628 seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
1629 mutex_unlock(&dev->struct_mutex);
1630
1631 return 0;
1632}
1633
57f350b6
JB		 1634static int i915_dpio_info(struct seq_file *m, void *data)
1635{
1636 struct drm_info_node *node = (struct drm_info_node *) m->private;
1637 struct drm_device *dev = node->minor->dev;
1638 struct drm_i915_private *dev_priv = dev->dev_private;
1639 int ret;
1640
1641
1642 if (!IS_VALLEYVIEW(dev)) {
267f0c90 1643 seq_puts(m, "unsupported\n");
57f350b6
JB		 1644 return 0;
1645 }
1646
09153000 1647 ret = mutex_lock_interruptible(&dev_priv->dpio_lock);
57f350b6
JB		 1648 if (ret)
1649 return ret;
1650
1651 seq_printf(m, "DPIO_CTL: 0x%08x\n", I915_READ(DPIO_CTL));
1652
1653 seq_printf(m, "DPIO_DIV_A: 0x%08x\n",
5e69f97f 1654 vlv_dpio_read(dev_priv, PIPE_A, _DPIO_DIV_A));
57f350b6 1655 seq_printf(m, "DPIO_DIV_B: 0x%08x\n",
5e69f97f 1656 vlv_dpio_read(dev_priv, PIPE_A, _DPIO_DIV_B));
57f350b6
JB		 1657
1658 seq_printf(m, "DPIO_REFSFR_A: 0x%08x\n",
5e69f97f 1659 vlv_dpio_read(dev_priv, PIPE_A, _DPIO_REFSFR_A));
57f350b6 1660 seq_printf(m, "DPIO_REFSFR_B: 0x%08x\n",
5e69f97f 1661 vlv_dpio_read(dev_priv, PIPE_A, _DPIO_REFSFR_B));
57f350b6
JB		 1662
1663 seq_printf(m, "DPIO_CORE_CLK_A: 0x%08x\n",
5e69f97f 1664 vlv_dpio_read(dev_priv, PIPE_A, _DPIO_CORE_CLK_A));
57f350b6 1665 seq_printf(m, "DPIO_CORE_CLK_B: 0x%08x\n",
5e69f97f 1666 vlv_dpio_read(dev_priv, PIPE_A, _DPIO_CORE_CLK_B));
57f350b6 1667
4abb2c39 1668 seq_printf(m, "DPIO_LPF_COEFF_A: 0x%08x\n",
5e69f97f 1669 vlv_dpio_read(dev_priv, PIPE_A, _DPIO_LPF_COEFF_A));
4abb2c39 1670 seq_printf(m, "DPIO_LPF_COEFF_B: 0x%08x\n",
5e69f97f 1671 vlv_dpio_read(dev_priv, PIPE_A, _DPIO_LPF_COEFF_B));
57f350b6
JB		 1672
1673 seq_printf(m, "DPIO_FASTCLK_DISABLE: 0x%08x\n",
5e69f97f 1674 vlv_dpio_read(dev_priv, PIPE_A, DPIO_FASTCLK_DISABLE));
57f350b6 1675
09153000 1676 mutex_unlock(&dev_priv->dpio_lock);
57f350b6
JB		 1677
1678 return 0;
1679}
1680
63573eb7
BW		 1681static int i915_llc(struct seq_file *m, void *data)
1682{
1683 struct drm_info_node *node = (struct drm_info_node *) m->private;
1684 struct drm_device *dev = node->minor->dev;
1685 struct drm_i915_private *dev_priv = dev->dev_private;
1686
1687 /* Size calculation for LLC is a bit of a pain. Ignore for now. */
1688 seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
1689 seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size);
1690
1691 return 0;
1692}
1693
e91fd8c6
RV		 1694static int i915_edp_psr_status(struct seq_file *m, void *data)
1695{
1696 struct drm_info_node *node = m->private;
1697 struct drm_device *dev = node->minor->dev;
1698 struct drm_i915_private *dev_priv = dev->dev_private;
a031d709
RV		 1699 u32 psrperf = 0;
1700 bool enabled = false;
e91fd8c6 1701
a031d709
RV		 1702 seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
1703 seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
e91fd8c6 1704
a031d709
RV		 1705 enabled = HAS_PSR(dev) &&
1706 I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
1707 seq_printf(m, "Enabled: %s\n", yesno(enabled));
e91fd8c6 1708
a031d709
RV		 1709 if (HAS_PSR(dev))
1710 psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) &
1711 EDP_PSR_PERF_CNT_MASK;
1712 seq_printf(m, "Performance_Counter: %u\n", psrperf);
e91fd8c6
RV		 1713
1714 return 0;
1715}
1716
ec013e7f
JB		 1717static int i915_energy_uJ(struct seq_file *m, void *data)
1718{
1719 struct drm_info_node *node = m->private;
1720 struct drm_device *dev = node->minor->dev;
1721 struct drm_i915_private *dev_priv = dev->dev_private;
1722 u64 power;
1723 u32 units;
1724
1725 if (INTEL_INFO(dev)->gen < 6)
1726 return -ENODEV;
1727
1728 rdmsrl(MSR_RAPL_POWER_UNIT, power);
1729 power = (power & 0x1f00) >> 8;
1730 units = 1000000 / (1 << power); /* convert to uJ */
1731 power = I915_READ(MCH_SECP_NRG_STTS);
1732 power *= units;
1733
1734 seq_printf(m, "%llu", (long long unsigned)power);
371db66a
PZ		 1735
1736 return 0;
1737}
1738
1739static int i915_pc8_status(struct seq_file *m, void *unused)
1740{
1741 struct drm_info_node *node = (struct drm_info_node *) m->private;
1742 struct drm_device *dev = node->minor->dev;
1743 struct drm_i915_private *dev_priv = dev->dev_private;
1744
1745 if (!IS_HASWELL(dev)) {
1746 seq_puts(m, "not supported\n");
1747 return 0;
1748 }
1749
1750 mutex_lock(&dev_priv->pc8.lock);
1751 seq_printf(m, "Requirements met: %s\n",
1752 yesno(dev_priv->pc8.requirements_met));
1753 seq_printf(m, "GPU idle: %s\n", yesno(dev_priv->pc8.gpu_idle));
1754 seq_printf(m, "Disable count: %d\n", dev_priv->pc8.disable_count);
1755 seq_printf(m, "IRQs disabled: %s\n",
1756 yesno(dev_priv->pc8.irqs_disabled));
1757 seq_printf(m, "Enabled: %s\n", yesno(dev_priv->pc8.enabled));
1758 mutex_unlock(&dev_priv->pc8.lock);
1759
ec013e7f
JB		 1760 return 0;
1761}
1762
07144428
DL		 1763struct pipe_crc_info {
1764 const char *name;
1765 struct drm_device *dev;
1766 enum pipe pipe;
1767};
1768
1769static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
1770{
be5c7a90
DL		 1771 struct pipe_crc_info *info = inode->i_private;
1772 struct drm_i915_private *dev_priv = info->dev->dev_private;
1773 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
1774
d538bbdf
DL		 1775 spin_lock_irq(&pipe_crc->lock);
1776
1777 if (pipe_crc->opened) {
1778 spin_unlock_irq(&pipe_crc->lock);
be5c7a90
DL		 1779 return -EBUSY; /* already open */
1780 }
1781
d538bbdf 1782 pipe_crc->opened = true;
07144428
DL		 1783 filep->private_data = inode->i_private;
1784
d538bbdf
DL		 1785 spin_unlock_irq(&pipe_crc->lock);
1786
07144428
DL		 1787 return 0;
1788}
1789
1790static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
1791{
be5c7a90
DL		 1792 struct pipe_crc_info *info = inode->i_private;
1793 struct drm_i915_private *dev_priv = info->dev->dev_private;
1794 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
1795
d538bbdf
DL		 1796 spin_lock_irq(&pipe_crc->lock);
1797 pipe_crc->opened = false;
1798 spin_unlock_irq(&pipe_crc->lock);
be5c7a90 1799
07144428
DL		 1800 return 0;
1801}
1802
1803/* (6 fields, 8 chars each, space separated (5) + '\n') */
1804#define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
1805/* account for \'0' */
1806#define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1)
1807
1808static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
8bf1e9f1 1809{
d538bbdf
DL		 1810 assert_spin_locked(&pipe_crc->lock);
1811 return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
1812 INTEL_PIPE_CRC_ENTRIES_NR);
07144428
DL		 1813}
1814
1815static ssize_t
1816i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
1817 loff_t *pos)
1818{
1819 struct pipe_crc_info *info = filep->private_data;
1820 struct drm_device *dev = info->dev;
1821 struct drm_i915_private *dev_priv = dev->dev_private;
1822 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
1823 char buf[PIPE_CRC_BUFFER_LEN];
1824 int head, tail, n_entries, n;
1825 ssize_t bytes_read;
1826
1827 /*
1828 * Don't allow user space to provide buffers not big enough to hold
1829 * a line of data.
1830 */
1831 if (count < PIPE_CRC_LINE_LEN)
1832 return -EINVAL;
1833
1834 if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
8bf1e9f1 1835 return 0;
07144428
DL		 1836
1837 /* nothing to read */
d538bbdf 1838 spin_lock_irq(&pipe_crc->lock);
07144428 1839 while (pipe_crc_data_count(pipe_crc) == 0) {
d538bbdf
DL		 1840 int ret;
1841
1842 if (filep->f_flags & O_NONBLOCK) {
1843 spin_unlock_irq(&pipe_crc->lock);
07144428 1844 return -EAGAIN;
d538bbdf 1845 }
07144428 1846
d538bbdf
DL		 1847 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
1848 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
1849 if (ret) {
1850 spin_unlock_irq(&pipe_crc->lock);
1851 return ret;
1852 }
8bf1e9f1
SH		 1853 }
1854
07144428 1855 /* We now have one or more entries to read */
d538bbdf
DL		 1856 head = pipe_crc->head;
1857 tail = pipe_crc->tail;
07144428
DL		 1858 n_entries = min((size_t)CIRC_CNT(head, tail, INTEL_PIPE_CRC_ENTRIES_NR),
1859 count / PIPE_CRC_LINE_LEN);
d538bbdf
DL		 1860 spin_unlock_irq(&pipe_crc->lock);
1861
07144428
DL		 1862 bytes_read = 0;
1863 n = 0;
1864 do {
b2c88f5b 1865 struct intel_pipe_crc_entry *entry = &pipe_crc->entries[tail];
07144428 1866 int ret;
8bf1e9f1 1867
07144428
DL		 1868 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
1869 "%8u %8x %8x %8x %8x %8x\n",
1870 entry->frame, entry->crc[0],
1871 entry->crc[1], entry->crc[2],
1872 entry->crc[3], entry->crc[4]);
1873
1874 ret = copy_to_user(user_buf + n * PIPE_CRC_LINE_LEN,
1875 buf, PIPE_CRC_LINE_LEN);
1876 if (ret == PIPE_CRC_LINE_LEN)
1877 return -EFAULT;
b2c88f5b
DL		 1878
1879 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
1880 tail = (tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
07144428
DL		 1881 n++;
1882 } while (--n_entries);
8bf1e9f1 1883
d538bbdf
DL		 1884 spin_lock_irq(&pipe_crc->lock);
1885 pipe_crc->tail = tail;
1886 spin_unlock_irq(&pipe_crc->lock);
1887
07144428
DL		 1888 return bytes_read;
1889}
1890
1891static const struct file_operations i915_pipe_crc_fops = {
1892 .owner = THIS_MODULE,
1893 .open = i915_pipe_crc_open,
1894 .read = i915_pipe_crc_read,
1895 .release = i915_pipe_crc_release,
1896};
1897
1898static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
1899 {
1900 .name = "i915_pipe_A_crc",
1901 .pipe = PIPE_A,
1902 },
1903 {
1904 .name = "i915_pipe_B_crc",
1905 .pipe = PIPE_B,
1906 },
1907 {
1908 .name = "i915_pipe_C_crc",
1909 .pipe = PIPE_C,
1910 },
1911};
1912
1913static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
1914 enum pipe pipe)
1915{
1916 struct drm_device *dev = minor->dev;
1917 struct dentry *ent;
1918 struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
1919
1920 info->dev = dev;
1921 ent = debugfs_create_file(info->name, S_IRUGO, root, info,
1922 &i915_pipe_crc_fops);
1923 if (IS_ERR(ent))
1924 return PTR_ERR(ent);
1925
1926 return drm_add_fake_info_node(minor, ent, info);
8bf1e9f1
SH		 1927}
1928
e8dfcf78 1929static const char * const pipe_crc_sources[] = {
926321d5
DV		 1930 "none",
1931 "plane1",
1932 "plane2",
1933 "pf",
5b3a856b 1934 "pipe",
3d099a05
DV		 1935 "TV",
1936 "DP-B",
1937 "DP-C",
1938 "DP-D",
46a19188 1939 "auto",
926321d5
DV		 1940};
1941
1942static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
1943{
1944 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
1945 return pipe_crc_sources[source];
1946}
1947
bd9db02f 1948static int display_crc_ctl_show(struct seq_file *m, void *data)
926321d5
DV		 1949{
1950 struct drm_device *dev = m->private;
1951 struct drm_i915_private *dev_priv = dev->dev_private;
1952 int i;
1953
1954 for (i = 0; i < I915_MAX_PIPES; i++)
1955 seq_printf(m, "%c %s\n", pipe_name(i),
1956 pipe_crc_source_name(dev_priv->pipe_crc[i].source));
1957
1958 return 0;
1959}
1960
bd9db02f 1961static int display_crc_ctl_open(struct inode *inode, struct file *file)
926321d5
DV		 1962{
1963 struct drm_device *dev = inode->i_private;
1964
bd9db02f 1965 return single_open(file, display_crc_ctl_show, dev);
926321d5
DV		 1966}
1967
46a19188 1968static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
52f843f6
DV		 1969 uint32_t *val)
1970{
46a19188
DV		 1971 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
1972 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
1973
1974 switch (*source) {
52f843f6
DV		 1975 case INTEL_PIPE_CRC_SOURCE_PIPE:
1976 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
1977 break;
1978 case INTEL_PIPE_CRC_SOURCE_NONE:
1979 *val = 0;
1980 break;
1981 default:
1982 return -EINVAL;
1983 }
1984
1985 return 0;
1986}
1987
46a19188
DV		 1988static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe,
1989 enum intel_pipe_crc_source *source)
1990{
1991 struct intel_encoder *encoder;
1992 struct intel_crtc *crtc;
1993 int ret = 0;
1994
1995 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
1996
1997 mutex_lock(&dev->mode_config.mutex);
1998 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
1999 base.head) {
2000 if (!encoder->base.crtc)
2001 continue;
2002
2003 crtc = to_intel_crtc(encoder->base.crtc);
2004
2005 if (crtc->pipe != pipe)
2006 continue;
2007
2008 switch (encoder->type) {
2009 case INTEL_OUTPUT_TVOUT:
2010 *source = INTEL_PIPE_CRC_SOURCE_TV;
2011 break;
2012 case INTEL_OUTPUT_DISPLAYPORT:
2013 case INTEL_OUTPUT_EDP:
2014 /* We can't get stable CRCs for DP ports somehow. */
2015 ret = -ENODEV;
2016 break;
2017 }
2018 }
2019 mutex_unlock(&dev->mode_config.mutex);
2020
2021 return ret;
2022}
2023
2024static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
2025 enum pipe pipe,
2026 enum intel_pipe_crc_source *source,
7ac0129b
DV		 2027 uint32_t *val)
2028{
8d2f24ca
DV		 2029 struct drm_i915_private *dev_priv = dev->dev_private;
2030 bool need_stable_symbols = false;
2031
46a19188
DV		 2032 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
2033 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
2034 if (ret)
2035 return ret;
2036 }
2037
2038 switch (*source) {
7ac0129b
DV		 2039 case INTEL_PIPE_CRC_SOURCE_PIPE:
2040 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
2041 break;
2042 case INTEL_PIPE_CRC_SOURCE_DP_B:
2043 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
8d2f24ca 2044 need_stable_symbols = true;
7ac0129b
DV		 2045 break;
2046 case INTEL_PIPE_CRC_SOURCE_DP_C:
2047 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
8d2f24ca 2048 need_stable_symbols = true;
7ac0129b
DV		 2049 break;
2050 case INTEL_PIPE_CRC_SOURCE_NONE:
2051 *val = 0;
2052 break;
2053 default:
2054 return -EINVAL;
2055 }
2056
8d2f24ca
DV		 2057 /*
2058 * When the pipe CRC tap point is after the transcoders we need
2059 * to tweak symbol-level features to produce a deterministic series of
2060 * symbols for a given frame. We need to reset those features only once
2061 * a frame (instead of every nth symbol):
2062 * - DC-balance: used to ensure a better clock recovery from the data
2063 * link (SDVO)
2064 * - DisplayPort scrambling: used for EMI reduction
2065 */
2066 if (need_stable_symbols) {
2067 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
2068
2069 WARN_ON(!IS_G4X(dev));
2070
2071 tmp |= DC_BALANCE_RESET_VLV;
2072 if (pipe == PIPE_A)
2073 tmp |= PIPE_A_SCRAMBLE_RESET;
2074 else
2075 tmp |= PIPE_B_SCRAMBLE_RESET;
2076
2077 I915_WRITE(PORT_DFT2_G4X, tmp);
2078 }
2079
7ac0129b
DV		 2080 return 0;
2081}
2082
4b79ebf7 2083static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
46a19188
DV		 2084 enum pipe pipe,
2085 enum intel_pipe_crc_source *source,
4b79ebf7
DV		 2086 uint32_t *val)
2087{
84093603
DV		 2088 struct drm_i915_private *dev_priv = dev->dev_private;
2089 bool need_stable_symbols = false;
2090
46a19188
DV		 2091 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
2092 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
2093 if (ret)
2094 return ret;
2095 }
2096
2097 switch (*source) {
4b79ebf7
DV		 2098 case INTEL_PIPE_CRC_SOURCE_PIPE:
2099 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
2100 break;
2101 case INTEL_PIPE_CRC_SOURCE_TV:
2102 if (!SUPPORTS_TV(dev))
2103 return -EINVAL;
2104 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
2105 break;
2106 case INTEL_PIPE_CRC_SOURCE_DP_B:
2107 if (!IS_G4X(dev))
2108 return -EINVAL;
2109 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
84093603 2110 need_stable_symbols = true;
4b79ebf7
DV		 2111 break;
2112 case INTEL_PIPE_CRC_SOURCE_DP_C:
2113 if (!IS_G4X(dev))
2114 return -EINVAL;
2115 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
84093603 2116 need_stable_symbols = true;
4b79ebf7
DV		 2117 break;
2118 case INTEL_PIPE_CRC_SOURCE_DP_D:
2119 if (!IS_G4X(dev))
2120 return -EINVAL;
2121 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
84093603 2122 need_stable_symbols = true;
4b79ebf7
DV		 2123 break;
2124 case INTEL_PIPE_CRC_SOURCE_NONE:
2125 *val = 0;
2126 break;
2127 default:
2128 return -EINVAL;
2129 }
2130
84093603
DV		 2131 /*
2132 * When the pipe CRC tap point is after the transcoders we need
2133 * to tweak symbol-level features to produce a deterministic series of
2134 * symbols for a given frame. We need to reset those features only once
2135 * a frame (instead of every nth symbol):
2136 * - DC-balance: used to ensure a better clock recovery from the data
2137 * link (SDVO)
2138 * - DisplayPort scrambling: used for EMI reduction
2139 */
2140 if (need_stable_symbols) {
2141 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
2142
2143 WARN_ON(!IS_G4X(dev));
2144
2145 I915_WRITE(PORT_DFT_I9XX,
2146 I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
2147
2148 if (pipe == PIPE_A)
2149 tmp |= PIPE_A_SCRAMBLE_RESET;
2150 else
2151 tmp |= PIPE_B_SCRAMBLE_RESET;
2152
2153 I915_WRITE(PORT_DFT2_G4X, tmp);
2154 }
2155
4b79ebf7
DV		 2156 return 0;
2157}
2158
8d2f24ca
DV		 2159static void vlv_undo_pipe_scramble_reset(struct drm_device *dev,
2160 enum pipe pipe)
2161{
2162 struct drm_i915_private *dev_priv = dev->dev_private;
2163 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
2164
2165 if (pipe == PIPE_A)
2166 tmp &= ~PIPE_A_SCRAMBLE_RESET;
2167 else
2168 tmp &= ~PIPE_B_SCRAMBLE_RESET;
2169 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
2170 tmp &= ~DC_BALANCE_RESET_VLV;
2171 I915_WRITE(PORT_DFT2_G4X, tmp);
2172
2173}
2174
84093603
DV		 2175static void g4x_undo_pipe_scramble_reset(struct drm_device *dev,
2176 enum pipe pipe)
2177{
2178 struct drm_i915_private *dev_priv = dev->dev_private;
2179 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
2180
2181 if (pipe == PIPE_A)
2182 tmp &= ~PIPE_A_SCRAMBLE_RESET;
2183 else
2184 tmp &= ~PIPE_B_SCRAMBLE_RESET;
2185 I915_WRITE(PORT_DFT2_G4X, tmp);
2186
2187 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
2188 I915_WRITE(PORT_DFT_I9XX,
2189 I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
2190 }
2191}
2192
46a19188 2193static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
5b3a856b
DV		 2194 uint32_t *val)
2195{
46a19188
DV		 2196 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
2197 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
2198
2199 switch (*source) {
5b3a856b
DV		 2200 case INTEL_PIPE_CRC_SOURCE_PLANE1:
2201 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
2202 break;
2203 case INTEL_PIPE_CRC_SOURCE_PLANE2:
2204 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
2205 break;
5b3a856b
DV		 2206 case INTEL_PIPE_CRC_SOURCE_PIPE:
2207 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
2208 break;
3d099a05 2209 case INTEL_PIPE_CRC_SOURCE_NONE:
5b3a856b
DV		 2210 *val = 0;
2211 break;
3d099a05
DV		 2212 default:
2213 return -EINVAL;
5b3a856b
DV		 2214 }
2215
2216 return 0;
2217}
2218
46a19188 2219static int ivb_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
5b3a856b
DV		 2220 uint32_t *val)
2221{
46a19188
DV		 2222 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
2223 *source = INTEL_PIPE_CRC_SOURCE_PF;
2224
2225 switch (*source) {
5b3a856b
DV		 2226 case INTEL_PIPE_CRC_SOURCE_PLANE1:
2227 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
2228 break;
2229 case INTEL_PIPE_CRC_SOURCE_PLANE2:
2230 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
2231 break;
2232 case INTEL_PIPE_CRC_SOURCE_PF:
2233 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
2234 break;
3d099a05 2235 case INTEL_PIPE_CRC_SOURCE_NONE:
5b3a856b
DV		 2236 *val = 0;
2237 break;
3d099a05
DV		 2238 default:
2239 return -EINVAL;
5b3a856b
DV		 2240 }
2241
2242 return 0;
2243}
2244
926321d5
DV		 2245static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
2246 enum intel_pipe_crc_source source)
2247{
2248 struct drm_i915_private *dev_priv = dev->dev_private;
cc3da175 2249 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
926321d5 2250 u32 val;
5b3a856b 2251 int ret;
926321d5 2252
cc3da175
DL		 2253 if (pipe_crc->source == source)
2254 return 0;
2255
ae676fcd
DL		 2256 /* forbid changing the source without going back to 'none' */
2257 if (pipe_crc->source && source)
2258 return -EINVAL;
2259
52f843f6 2260 if (IS_GEN2(dev))
46a19188 2261 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
52f843f6 2262 else if (INTEL_INFO(dev)->gen < 5)
46a19188 2263 ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
7ac0129b 2264 else if (IS_VALLEYVIEW(dev))
46a19188 2265 ret = vlv_pipe_crc_ctl_reg(dev,pipe, &source, &val);
4b79ebf7 2266 else if (IS_GEN5(dev) || IS_GEN6(dev))
46a19188 2267 ret = ilk_pipe_crc_ctl_reg(&source, &val);
5b3a856b 2268 else
46a19188 2269 ret = ivb_pipe_crc_ctl_reg(&source, &val);
5b3a856b
DV		 2270
2271 if (ret != 0)
2272 return ret;
2273
4b584369
DL		 2274 /* none -> real source transition */
2275 if (source) {
7cd6ccff
DL		 2276 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
2277 pipe_name(pipe), pipe_crc_source_name(source));
2278
e5f75aca
DL		 2279 pipe_crc->entries = kzalloc(sizeof(*pipe_crc->entries) *
2280 INTEL_PIPE_CRC_ENTRIES_NR,
2281 GFP_KERNEL);
2282 if (!pipe_crc->entries)
2283 return -ENOMEM;
2284
d538bbdf
DL		 2285 spin_lock_irq(&pipe_crc->lock);
2286 pipe_crc->head = 0;
2287 pipe_crc->tail = 0;
2288 spin_unlock_irq(&pipe_crc->lock);
4b584369
DL		 2289 }
2290
cc3da175 2291 pipe_crc->source = source;
926321d5 2292
926321d5
DV		 2293 I915_WRITE(PIPE_CRC_CTL(pipe), val);
2294 POSTING_READ(PIPE_CRC_CTL(pipe));
2295
e5f75aca
DL		 2296 /* real source -> none transition */
2297 if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
d538bbdf
DL		 2298 struct intel_pipe_crc_entry *entries;
2299
7cd6ccff
DL		 2300 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
2301 pipe_name(pipe));
2302
bcf17ab2
DV		 2303 intel_wait_for_vblank(dev, pipe);
2304
d538bbdf
DL		 2305 spin_lock_irq(&pipe_crc->lock);
2306 entries = pipe_crc->entries;
e5f75aca 2307 pipe_crc->entries = NULL;
d538bbdf
DL		 2308 spin_unlock_irq(&pipe_crc->lock);
2309
2310 kfree(entries);
84093603
DV		 2311
2312 if (IS_G4X(dev))
2313 g4x_undo_pipe_scramble_reset(dev, pipe);
8d2f24ca
DV		 2314 else if (IS_VALLEYVIEW(dev))
2315 vlv_undo_pipe_scramble_reset(dev, pipe);
e5f75aca
DL		 2316 }
2317
926321d5
DV		 2318 return 0;
2319}
2320
2321/*
2322 * Parse pipe CRC command strings:
b94dec87
DL		 2323 * command: wsp* object wsp+ name wsp+ source wsp*
2324 * object: 'pipe'
2325 * name: (A | B | C)
926321d5
DV		 2326 * source: (none | plane1 | plane2 | pf)
2327 * wsp: (#0x20 | #0x9 | #0xA)+
2328 *
2329 * eg.:
b94dec87
DL		 2330 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A
2331 * "pipe A none" -> Stop CRC
926321d5 2332 */
bd9db02f 2333static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
926321d5
DV		 2334{
2335 int n_words = 0;
2336
2337 while (*buf) {
2338 char *end;
2339
2340 /* skip leading white space */
2341 buf = skip_spaces(buf);
2342 if (!*buf)
2343 break; /* end of buffer */
2344
2345 /* find end of word */
2346 for (end = buf; *end && !isspace(*end); end++)
2347 ;
2348
2349 if (n_words == max_words) {
2350 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
2351 max_words);
2352 return -EINVAL; /* ran out of words[] before bytes */
2353 }
2354
2355 if (*end)
2356 *end++ = '\0';
2357 words[n_words++] = buf;
2358 buf = end;
2359 }
2360
2361 return n_words;
2362}
2363
b94dec87
DL		 2364enum intel_pipe_crc_object {
2365 PIPE_CRC_OBJECT_PIPE,
2366};
2367
e8dfcf78 2368static const char * const pipe_crc_objects[] = {
b94dec87
DL		 2369 "pipe",
2370};
2371
2372static int
bd9db02f 2373display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
b94dec87
DL		 2374{
2375 int i;
2376
2377 for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
2378 if (!strcmp(buf, pipe_crc_objects[i])) {
bd9db02f 2379 *o = i;
b94dec87
DL		 2380 return 0;
2381 }
2382
2383 return -EINVAL;
2384}
2385
bd9db02f 2386static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
926321d5
DV		 2387{
2388 const char name = buf[0];
2389
2390 if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
2391 return -EINVAL;
2392
2393 *pipe = name - 'A';
2394
2395 return 0;
2396}
2397
2398static int
bd9db02f 2399display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
926321d5
DV		 2400{
2401 int i;
2402
2403 for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
2404 if (!strcmp(buf, pipe_crc_sources[i])) {
bd9db02f 2405 *s = i;
926321d5
DV		 2406 return 0;
2407 }
2408
2409 return -EINVAL;
2410}
2411
bd9db02f 2412static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len)
926321d5 2413{
b94dec87 2414#define N_WORDS 3
926321d5 2415 int n_words;
b94dec87 2416 char *words[N_WORDS];
926321d5 2417 enum pipe pipe;
b94dec87 2418 enum intel_pipe_crc_object object;
926321d5
DV		 2419 enum intel_pipe_crc_source source;
2420
bd9db02f 2421 n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
b94dec87
DL		 2422 if (n_words != N_WORDS) {
2423 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
2424 N_WORDS);
2425 return -EINVAL;
2426 }
2427
bd9db02f 2428 if (display_crc_ctl_parse_object(words[0], &object) < 0) {
b94dec87 2429 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
926321d5
DV		 2430 return -EINVAL;
2431 }
2432
bd9db02f 2433 if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
b94dec87 2434 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
926321d5
DV		 2435 return -EINVAL;
2436 }
2437
bd9db02f 2438 if (display_crc_ctl_parse_source(words[2], &source) < 0) {
b94dec87 2439 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
926321d5
DV		 2440 return -EINVAL;
2441 }
2442
2443 return pipe_crc_set_source(dev, pipe, source);
2444}
2445
bd9db02f
DL		 2446static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
2447 size_t len, loff_t *offp)
926321d5
DV		 2448{
2449 struct seq_file *m = file->private_data;
2450 struct drm_device *dev = m->private;
2451 char *tmpbuf;
2452 int ret;
2453
2454 if (len == 0)
2455 return 0;
2456
2457 if (len > PAGE_SIZE - 1) {
2458 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
2459 PAGE_SIZE);
2460 return -E2BIG;
2461 }
2462
2463 tmpbuf = kmalloc(len + 1, GFP_KERNEL);
2464 if (!tmpbuf)
2465 return -ENOMEM;
2466
2467 if (copy_from_user(tmpbuf, ubuf, len)) {
2468 ret = -EFAULT;
2469 goto out;
2470 }
2471 tmpbuf[len] = '\0';
2472
bd9db02f 2473 ret = display_crc_ctl_parse(dev, tmpbuf, len);
926321d5
DV		 2474
2475out:
2476 kfree(tmpbuf);
2477 if (ret < 0)
2478 return ret;
2479
2480 *offp += len;
2481 return len;
2482}
2483
bd9db02f 2484static const struct file_operations i915_display_crc_ctl_fops = {
926321d5 2485 .owner = THIS_MODULE,
bd9db02f 2486 .open = display_crc_ctl_open,
926321d5
DV		 2487 .read = seq_read,
2488 .llseek = seq_lseek,
2489 .release = single_release,
bd9db02f 2490 .write = display_crc_ctl_write
926321d5
DV		 2491};
2492
647416f9
KC		 2493static int
2494i915_wedged_get(void *data, u64 *val)
f3cd474b 2495{
647416f9 2496 struct drm_device *dev = data;
f3cd474b 2497 drm_i915_private_t *dev_priv = dev->dev_private;
f3cd474b 2498
647416f9 2499 *val = atomic_read(&dev_priv->gpu_error.reset_counter);
f3cd474b 2500
647416f9 2501 return 0;
f3cd474b
CW		 2502}
2503
647416f9
KC		 2504static int
2505i915_wedged_set(void *data, u64 val)
f3cd474b 2506{
647416f9 2507 struct drm_device *dev = data;
f3cd474b 2508
647416f9 2509 DRM_INFO("Manually setting wedged to %llu\n", val);
527f9e90 2510 i915_handle_error(dev, val);
f3cd474b 2511
647416f9 2512 return 0;
f3cd474b
CW		 2513}
2514
647416f9
KC		 2515DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
2516 i915_wedged_get, i915_wedged_set,
3a3b4f98 2517 "%llu\n");
f3cd474b 2518
647416f9
KC		 2519static int
2520i915_ring_stop_get(void *data, u64 *val)
e5eb3d63 2521{
647416f9 2522 struct drm_device *dev = data;
e5eb3d63 2523 drm_i915_private_t *dev_priv = dev->dev_private;
e5eb3d63 2524
647416f9 2525 *val = dev_priv->gpu_error.stop_rings;
e5eb3d63 2526
647416f9 2527 return 0;
e5eb3d63
DV		 2528}
2529
647416f9
KC		 2530static int
2531i915_ring_stop_set(void *data, u64 val)
e5eb3d63 2532{
647416f9 2533 struct drm_device *dev = data;
e5eb3d63 2534 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 2535 int ret;
e5eb3d63 2536
647416f9 2537 DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val);
e5eb3d63 2538
22bcfc6a
DV		 2539 ret = mutex_lock_interruptible(&dev->struct_mutex);
2540 if (ret)
2541 return ret;
2542
99584db3 2543 dev_priv->gpu_error.stop_rings = val;
e5eb3d63
DV		 2544 mutex_unlock(&dev->struct_mutex);
2545
647416f9 2546 return 0;
e5eb3d63
DV		 2547}
2548
647416f9
KC		 2549DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops,
2550 i915_ring_stop_get, i915_ring_stop_set,
2551 "0x%08llx\n");
d5442303 2552
094f9a54
CW		 2553static int
2554i915_ring_missed_irq_get(void *data, u64 *val)
2555{
2556 struct drm_device *dev = data;
2557 struct drm_i915_private *dev_priv = dev->dev_private;
2558
2559 *val = dev_priv->gpu_error.missed_irq_rings;
2560 return 0;
2561}
2562
2563static int
2564i915_ring_missed_irq_set(void *data, u64 val)
2565{
2566 struct drm_device *dev = data;
2567 struct drm_i915_private *dev_priv = dev->dev_private;
2568 int ret;
2569
2570 /* Lock against concurrent debugfs callers */
2571 ret = mutex_lock_interruptible(&dev->struct_mutex);
2572 if (ret)
2573 return ret;
2574 dev_priv->gpu_error.missed_irq_rings = val;
2575 mutex_unlock(&dev->struct_mutex);
2576
2577 return 0;
2578}
2579
2580DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
2581 i915_ring_missed_irq_get, i915_ring_missed_irq_set,
2582 "0x%08llx\n");
2583
2584static int
2585i915_ring_test_irq_get(void *data, u64 *val)
2586{
2587 struct drm_device *dev = data;
2588 struct drm_i915_private *dev_priv = dev->dev_private;
2589
2590 *val = dev_priv->gpu_error.test_irq_rings;
2591
2592 return 0;
2593}
2594
2595static int
2596i915_ring_test_irq_set(void *data, u64 val)
2597{
2598 struct drm_device *dev = data;
2599 struct drm_i915_private *dev_priv = dev->dev_private;
2600 int ret;
2601
2602 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
2603
2604 /* Lock against concurrent debugfs callers */
2605 ret = mutex_lock_interruptible(&dev->struct_mutex);
2606 if (ret)
2607 return ret;
2608
2609 dev_priv->gpu_error.test_irq_rings = val;
2610 mutex_unlock(&dev->struct_mutex);
2611
2612 return 0;
2613}
2614
2615DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
2616 i915_ring_test_irq_get, i915_ring_test_irq_set,
2617 "0x%08llx\n");
2618
dd624afd
CW		 2619#define DROP_UNBOUND 0x1
2620#define DROP_BOUND 0x2
2621#define DROP_RETIRE 0x4
2622#define DROP_ACTIVE 0x8
2623#define DROP_ALL (DROP_UNBOUND | \
2624 DROP_BOUND | \
2625 DROP_RETIRE | \
2626 DROP_ACTIVE)
647416f9
KC		 2627static int
2628i915_drop_caches_get(void *data, u64 *val)
dd624afd 2629{
647416f9 2630 *val = DROP_ALL;
dd624afd 2631
647416f9 2632 return 0;
dd624afd
CW		 2633}
2634
647416f9
KC		 2635static int
2636i915_drop_caches_set(void *data, u64 val)
dd624afd 2637{
647416f9 2638 struct drm_device *dev = data;
dd624afd
CW		 2639 struct drm_i915_private *dev_priv = dev->dev_private;
2640 struct drm_i915_gem_object *obj, *next;
ca191b13
BW		 2641 struct i915_address_space *vm;
2642 struct i915_vma *vma, *x;
647416f9 2643 int ret;
dd624afd 2644
647416f9 2645 DRM_DEBUG_DRIVER("Dropping caches: 0x%08llx\n", val);
dd624afd
CW		 2646
2647 /* No need to check and wait for gpu resets, only libdrm auto-restarts
2648 * on ioctls on -EAGAIN. */
2649 ret = mutex_lock_interruptible(&dev->struct_mutex);
2650 if (ret)
2651 return ret;
2652
2653 if (val & DROP_ACTIVE) {
2654 ret = i915_gpu_idle(dev);
2655 if (ret)
2656 goto unlock;
2657 }
2658
2659 if (val & (DROP_RETIRE | DROP_ACTIVE))
2660 i915_gem_retire_requests(dev);
2661
2662 if (val & DROP_BOUND) {
ca191b13
BW		 2663 list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
2664 list_for_each_entry_safe(vma, x, &vm->inactive_list,
2665 mm_list) {
2666 if (vma->obj->pin_count)
2667 continue;
2668
2669 ret = i915_vma_unbind(vma);
2670 if (ret)
2671 goto unlock;
2672 }
31a46c9c 2673 }
dd624afd
CW		 2674 }
2675
2676 if (val & DROP_UNBOUND) {
35c20a60
BW		 2677 list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list,
2678 global_list)
dd624afd
CW		 2679 if (obj->pages_pin_count == 0) {
2680 ret = i915_gem_object_put_pages(obj);
2681 if (ret)
2682 goto unlock;
2683 }
2684 }
2685
2686unlock:
2687 mutex_unlock(&dev->struct_mutex);
2688
647416f9 2689 return ret;
dd624afd
CW		 2690}
2691
647416f9
KC		 2692DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
2693 i915_drop_caches_get, i915_drop_caches_set,
2694 "0x%08llx\n");
dd624afd 2695
647416f9
KC		 2696static int
2697i915_max_freq_get(void *data, u64 *val)
358733e9 2698{
647416f9 2699 struct drm_device *dev = data;
358733e9 2700 drm_i915_private_t *dev_priv = dev->dev_private;
647416f9 2701 int ret;
004777cb
DV		 2702
2703 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
2704 return -ENODEV;
2705
5c9669ce
TR		 2706 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
2707
4fc688ce 2708 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 2709 if (ret)
2710 return ret;
358733e9 2711
0a073b84
JB		 2712 if (IS_VALLEYVIEW(dev))
2713 *val = vlv_gpu_freq(dev_priv->mem_freq,
2714 dev_priv->rps.max_delay);
2715 else
2716 *val = dev_priv->rps.max_delay * GT_FREQUENCY_MULTIPLIER;
4fc688ce 2717 mutex_unlock(&dev_priv->rps.hw_lock);
358733e9 2718
647416f9 2719 return 0;
358733e9
JB		 2720}
2721
647416f9
KC		 2722static int
2723i915_max_freq_set(void *data, u64 val)
358733e9 2724{
647416f9 2725 struct drm_device *dev = data;
358733e9 2726 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 2727 int ret;
004777cb
DV		 2728
2729 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
2730 return -ENODEV;
358733e9 2731
5c9669ce
TR		 2732 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
2733
647416f9 2734 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
358733e9 2735
4fc688ce 2736 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 2737 if (ret)
2738 return ret;
2739
358733e9
JB		 2740 /*
2741 * Turbo will still be enabled, but won't go above the set value.
2742 */
0a073b84
JB		 2743 if (IS_VALLEYVIEW(dev)) {
2744 val = vlv_freq_opcode(dev_priv->mem_freq, val);
2745 dev_priv->rps.max_delay = val;
2746 gen6_set_rps(dev, val);
2747 } else {
2748 do_div(val, GT_FREQUENCY_MULTIPLIER);
2749 dev_priv->rps.max_delay = val;
2750 gen6_set_rps(dev, val);
2751 }
2752
4fc688ce 2753 mutex_unlock(&dev_priv->rps.hw_lock);
358733e9 2754
647416f9 2755 return 0;
358733e9
JB		 2756}
2757
647416f9
KC		 2758DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
2759 i915_max_freq_get, i915_max_freq_set,
3a3b4f98 2760 "%llu\n");
358733e9 2761
647416f9
KC		 2762static int
2763i915_min_freq_get(void *data, u64 *val)
1523c310 2764{
647416f9 2765 struct drm_device *dev = data;
1523c310 2766 drm_i915_private_t *dev_priv = dev->dev_private;
647416f9 2767 int ret;
004777cb
DV		 2768
2769 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
2770 return -ENODEV;
2771
5c9669ce
TR		 2772 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
2773
4fc688ce 2774 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 2775 if (ret)
2776 return ret;
1523c310 2777
0a073b84
JB		 2778 if (IS_VALLEYVIEW(dev))
2779 *val = vlv_gpu_freq(dev_priv->mem_freq,
2780 dev_priv->rps.min_delay);
2781 else
2782 *val = dev_priv->rps.min_delay * GT_FREQUENCY_MULTIPLIER;
4fc688ce 2783 mutex_unlock(&dev_priv->rps.hw_lock);
1523c310 2784
647416f9 2785 return 0;
1523c310
JB		 2786}
2787
647416f9
KC		 2788static int
2789i915_min_freq_set(void *data, u64 val)
1523c310 2790{
647416f9 2791 struct drm_device *dev = data;
1523c310 2792 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 2793 int ret;
004777cb
DV		 2794
2795 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
2796 return -ENODEV;
1523c310 2797
5c9669ce
TR		 2798 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
2799
647416f9 2800 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
1523c310 2801
4fc688ce 2802 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 2803 if (ret)
2804 return ret;
2805
1523c310
JB		 2806 /*
2807 * Turbo will still be enabled, but won't go below the set value.
2808 */
0a073b84
JB		 2809 if (IS_VALLEYVIEW(dev)) {
2810 val = vlv_freq_opcode(dev_priv->mem_freq, val);
2811 dev_priv->rps.min_delay = val;
2812 valleyview_set_rps(dev, val);
2813 } else {
2814 do_div(val, GT_FREQUENCY_MULTIPLIER);
2815 dev_priv->rps.min_delay = val;
2816 gen6_set_rps(dev, val);
2817 }
4fc688ce 2818 mutex_unlock(&dev_priv->rps.hw_lock);
1523c310 2819
647416f9 2820 return 0;
1523c310
JB		 2821}
2822
647416f9
KC		 2823DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
2824 i915_min_freq_get, i915_min_freq_set,
3a3b4f98 2825 "%llu\n");
1523c310 2826
647416f9
KC		 2827static int
2828i915_cache_sharing_get(void *data, u64 *val)
07b7ddd9 2829{
647416f9 2830 struct drm_device *dev = data;
07b7ddd9 2831 drm_i915_private_t *dev_priv = dev->dev_private;
07b7ddd9 2832 u32 snpcr;
647416f9 2833 int ret;
07b7ddd9 2834
004777cb
DV		 2835 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
2836 return -ENODEV;
2837
22bcfc6a
DV		 2838 ret = mutex_lock_interruptible(&dev->struct_mutex);
2839 if (ret)
2840 return ret;
2841
07b7ddd9
JB		 2842 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
2843 mutex_unlock(&dev_priv->dev->struct_mutex);
2844
647416f9 2845 *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
07b7ddd9 2846
647416f9 2847 return 0;
07b7ddd9
JB		 2848}
2849
647416f9
KC		 2850static int
2851i915_cache_sharing_set(void *data, u64 val)
07b7ddd9 2852{
647416f9 2853 struct drm_device *dev = data;
07b7ddd9 2854 struct drm_i915_private *dev_priv = dev->dev_private;
07b7ddd9 2855 u32 snpcr;
07b7ddd9 2856
004777cb
DV		 2857 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
2858 return -ENODEV;
2859
647416f9 2860 if (val > 3)
07b7ddd9
JB		 2861 return -EINVAL;
2862
647416f9 2863 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
07b7ddd9
JB		 2864
2865 /* Update the cache sharing policy here as well */
2866 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
2867 snpcr &= ~GEN6_MBC_SNPCR_MASK;
2868 snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
2869 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
2870
647416f9 2871 return 0;
07b7ddd9
JB		 2872}
2873
647416f9
KC		 2874DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
2875 i915_cache_sharing_get, i915_cache_sharing_set,
2876 "%llu\n");
07b7ddd9 2877
6d794d42
BW		 2878static int i915_forcewake_open(struct inode *inode, struct file *file)
2879{
2880 struct drm_device *dev = inode->i_private;
2881 struct drm_i915_private *dev_priv = dev->dev_private;
6d794d42 2882
075edca4 2883 if (INTEL_INFO(dev)->gen < 6)
6d794d42
BW		 2884 return 0;
2885
6d794d42 2886 gen6_gt_force_wake_get(dev_priv);
6d794d42
BW		 2887
2888 return 0;
2889}
2890
c43b5634 2891static int i915_forcewake_release(struct inode *inode, struct file *file)
6d794d42
BW		 2892{
2893 struct drm_device *dev = inode->i_private;
2894 struct drm_i915_private *dev_priv = dev->dev_private;
2895
075edca4 2896 if (INTEL_INFO(dev)->gen < 6)
6d794d42
BW		 2897 return 0;
2898
6d794d42 2899 gen6_gt_force_wake_put(dev_priv);
6d794d42
BW		 2900
2901 return 0;
2902}
2903
2904static const struct file_operations i915_forcewake_fops = {
2905 .owner = THIS_MODULE,
2906 .open = i915_forcewake_open,
2907 .release = i915_forcewake_release,
2908};
2909
2910static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
2911{
2912 struct drm_device *dev = minor->dev;
2913 struct dentry *ent;
2914
2915 ent = debugfs_create_file("i915_forcewake_user",
8eb57294 2916 S_IRUSR,
6d794d42
BW		 2917 root, dev,
2918 &i915_forcewake_fops);
2919 if (IS_ERR(ent))
2920 return PTR_ERR(ent);
2921
8eb57294 2922 return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
6d794d42
BW		 2923}
2924
6a9c308d
DV		 2925static int i915_debugfs_create(struct dentry *root,
2926 struct drm_minor *minor,
2927 const char *name,
2928 const struct file_operations *fops)
07b7ddd9
JB		 2929{
2930 struct drm_device *dev = minor->dev;
2931 struct dentry *ent;
2932
6a9c308d 2933 ent = debugfs_create_file(name,
07b7ddd9
JB		 2934 S_IRUGO | S_IWUSR,
2935 root, dev,
6a9c308d 2936 fops);
07b7ddd9
JB		 2937 if (IS_ERR(ent))
2938 return PTR_ERR(ent);
2939
6a9c308d 2940 return drm_add_fake_info_node(minor, ent, fops);
07b7ddd9
JB		 2941}
2942
27c202ad 2943static struct drm_info_list i915_debugfs_list[] = {
311bd68e 2944 {"i915_capabilities", i915_capabilities, 0},
73aa808f 2945 {"i915_gem_objects", i915_gem_object_info, 0},
08c18323 2946 {"i915_gem_gtt", i915_gem_gtt_info, 0},
1b50247a 2947 {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
433e12f7 2948 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
433e12f7 2949 {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
6d2b8885 2950 {"i915_gem_stolen", i915_gem_stolen_list_info },
4e5359cd 2951 {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
2017263e
BG		 2952 {"i915_gem_request", i915_gem_request_info, 0},
2953 {"i915_gem_seqno", i915_gem_seqno_info, 0},
a6172a80 2954 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
2017263e 2955 {"i915_gem_interrupt", i915_interrupt_info, 0},
1ec14ad3
CW		 2956 {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
2957 {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
2958 {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
9010ebfd 2959 {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
f97108d1
JB		 2960 {"i915_rstdby_delays", i915_rstdby_delays, 0},
2961 {"i915_cur_delayinfo", i915_cur_delayinfo, 0},
2962 {"i915_delayfreq_table", i915_delayfreq_table, 0},
2963 {"i915_inttoext_table", i915_inttoext_table, 0},
2964 {"i915_drpc_info", i915_drpc_info, 0},
7648fa99 2965 {"i915_emon_status", i915_emon_status, 0},
23b2f8bb 2966 {"i915_ring_freq_table", i915_ring_freq_table, 0},
7648fa99 2967 {"i915_gfxec", i915_gfxec, 0},
b5e50c3f 2968 {"i915_fbc_status", i915_fbc_status, 0},
92d44621 2969 {"i915_ips_status", i915_ips_status, 0},
4a9bef37 2970 {"i915_sr_status", i915_sr_status, 0},
44834a67 2971 {"i915_opregion", i915_opregion, 0},
37811fcc 2972 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
e76d3630 2973 {"i915_context_status", i915_context_status, 0},
6d794d42 2974 {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0},
ea16a3cd 2975 {"i915_swizzle_info", i915_swizzle_info, 0},
3cf17fc5 2976 {"i915_ppgtt_info", i915_ppgtt_info, 0},
57f350b6 2977 {"i915_dpio", i915_dpio_info, 0},
63573eb7 2978 {"i915_llc", i915_llc, 0},
e91fd8c6 2979 {"i915_edp_psr_status", i915_edp_psr_status, 0},
ec013e7f 2980 {"i915_energy_uJ", i915_energy_uJ, 0},
371db66a 2981 {"i915_pc8_status", i915_pc8_status, 0},
2017263e 2982};
27c202ad 2983#define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
2017263e 2984
2b4bd0e0 2985static struct i915_debugfs_files {
34b9674c
DV		 2986 const char *name;
2987 const struct file_operations *fops;
2988} i915_debugfs_files[] = {
2989 {"i915_wedged", &i915_wedged_fops},
2990 {"i915_max_freq", &i915_max_freq_fops},
2991 {"i915_min_freq", &i915_min_freq_fops},
2992 {"i915_cache_sharing", &i915_cache_sharing_fops},
2993 {"i915_ring_stop", &i915_ring_stop_fops},
094f9a54
CW		 2994 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
2995 {"i915_ring_test_irq", &i915_ring_test_irq_fops},
34b9674c
DV		 2996 {"i915_gem_drop_caches", &i915_drop_caches_fops},
2997 {"i915_error_state", &i915_error_state_fops},
2998 {"i915_next_seqno", &i915_next_seqno_fops},
bd9db02f 2999 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
34b9674c
DV		 3000};
3001
07144428
DL		 3002void intel_display_crc_init(struct drm_device *dev)
3003{
3004 struct drm_i915_private *dev_priv = dev->dev_private;
3005 int i;
3006
3007 for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
3008 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[i];
3009
d538bbdf
DL		 3010 pipe_crc->opened = false;
3011 spin_lock_init(&pipe_crc->lock);
07144428
DL		 3012 init_waitqueue_head(&pipe_crc->wq);
3013 }
3014}
3015
27c202ad 3016int i915_debugfs_init(struct drm_minor *minor)
2017263e 3017{
34b9674c 3018 int ret, i;
f3cd474b 3019
6d794d42 3020 ret = i915_forcewake_create(minor->debugfs_root, minor);
358733e9
JB		 3021 if (ret)
3022 return ret;
6a9c308d 3023
07144428
DL		 3024 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
3025 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
3026 if (ret)
3027 return ret;
3028 }
3029
34b9674c
DV		 3030 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
3031 ret = i915_debugfs_create(minor->debugfs_root, minor,
3032 i915_debugfs_files[i].name,
3033 i915_debugfs_files[i].fops);
3034 if (ret)
3035 return ret;
3036 }
40633219 3037
27c202ad
BG		 3038 return drm_debugfs_create_files(i915_debugfs_list,
3039 I915_DEBUGFS_ENTRIES,
2017263e
BG		 3040 minor->debugfs_root, minor);
3041}
3042
27c202ad 3043void i915_debugfs_cleanup(struct drm_minor *minor)
2017263e 3044{
34b9674c
DV		 3045 int i;
3046
27c202ad
BG		 3047 drm_debugfs_remove_files(i915_debugfs_list,
3048 I915_DEBUGFS_ENTRIES, minor);
07144428 3049
6d794d42
BW		 3050 drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
3051 1, minor);
07144428 3052
e309a997 3053 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
07144428
DL		 3054 struct drm_info_list *info_list =
3055 (struct drm_info_list *)&i915_pipe_crc_data[i];
3056
3057 drm_debugfs_remove_files(info_list, 1, minor);
3058 }
3059
34b9674c
DV		 3060 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
3061 struct drm_info_list *info_list =
3062 (struct drm_info_list *) i915_debugfs_files[i].fops;
3063
3064 drm_debugfs_remove_files(info_list, 1, minor);
3065 }
2017263e
BG		 3066}
3067
3068#endif /* CONFIG_DEBUG_FS */
Linux kernel - Deliverables
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