Commit | Line | Data |
---|---|---|
2017263e BG |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Keith Packard <keithp@keithp.com> | |
26 | * | |
27 | */ | |
28 | ||
29 | #include <linux/seq_file.h> | |
f3cd474b | 30 | #include <linux/debugfs.h> |
5a0e3ad6 | 31 | #include <linux/slab.h> |
2d1a8a48 | 32 | #include <linux/export.h> |
2017263e BG |
33 | #include "drmP.h" |
34 | #include "drm.h" | |
4e5359cd | 35 | #include "intel_drv.h" |
e5c65260 | 36 | #include "intel_ringbuffer.h" |
2017263e BG |
37 | #include "i915_drm.h" |
38 | #include "i915_drv.h" | |
39 | ||
40 | #define DRM_I915_RING_DEBUG 1 | |
41 | ||
42 | ||
43 | #if defined(CONFIG_DEBUG_FS) | |
44 | ||
f13d3f73 | 45 | enum { |
69dc4987 | 46 | ACTIVE_LIST, |
f13d3f73 CW |
47 | FLUSHING_LIST, |
48 | INACTIVE_LIST, | |
d21d5975 CW |
49 | PINNED_LIST, |
50 | DEFERRED_FREE_LIST, | |
f13d3f73 | 51 | }; |
2017263e | 52 | |
70d39fe4 CW |
53 | static const char *yesno(int v) |
54 | { | |
55 | return v ? "yes" : "no"; | |
56 | } | |
57 | ||
58 | static int i915_capabilities(struct seq_file *m, void *data) | |
59 | { | |
60 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
61 | struct drm_device *dev = node->minor->dev; | |
62 | const struct intel_device_info *info = INTEL_INFO(dev); | |
63 | ||
64 | seq_printf(m, "gen: %d\n", info->gen); | |
03d00ac5 | 65 | seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev)); |
70d39fe4 CW |
66 | #define B(x) seq_printf(m, #x ": %s\n", yesno(info->x)) |
67 | B(is_mobile); | |
70d39fe4 CW |
68 | B(is_i85x); |
69 | B(is_i915g); | |
70d39fe4 | 70 | B(is_i945gm); |
70d39fe4 CW |
71 | B(is_g33); |
72 | B(need_gfx_hws); | |
73 | B(is_g4x); | |
74 | B(is_pineview); | |
75 | B(is_broadwater); | |
76 | B(is_crestline); | |
70d39fe4 | 77 | B(has_fbc); |
70d39fe4 CW |
78 | B(has_pipe_cxsr); |
79 | B(has_hotplug); | |
80 | B(cursor_needs_physical); | |
81 | B(has_overlay); | |
82 | B(overlay_needs_physical); | |
a6c45cf0 | 83 | B(supports_tv); |
549f7365 CW |
84 | B(has_bsd_ring); |
85 | B(has_blt_ring); | |
70d39fe4 CW |
86 | #undef B |
87 | ||
88 | return 0; | |
89 | } | |
2017263e | 90 | |
05394f39 | 91 | static const char *get_pin_flag(struct drm_i915_gem_object *obj) |
a6172a80 | 92 | { |
05394f39 | 93 | if (obj->user_pin_count > 0) |
a6172a80 | 94 | return "P"; |
05394f39 | 95 | else if (obj->pin_count > 0) |
a6172a80 CW |
96 | return "p"; |
97 | else | |
98 | return " "; | |
99 | } | |
100 | ||
05394f39 | 101 | static const char *get_tiling_flag(struct drm_i915_gem_object *obj) |
a6172a80 | 102 | { |
0206e353 AJ |
103 | switch (obj->tiling_mode) { |
104 | default: | |
105 | case I915_TILING_NONE: return " "; | |
106 | case I915_TILING_X: return "X"; | |
107 | case I915_TILING_Y: return "Y"; | |
108 | } | |
a6172a80 CW |
109 | } |
110 | ||
93dfb40c | 111 | static const char *cache_level_str(int type) |
08c18323 CW |
112 | { |
113 | switch (type) { | |
93dfb40c CW |
114 | case I915_CACHE_NONE: return " uncached"; |
115 | case I915_CACHE_LLC: return " snooped (LLC)"; | |
116 | case I915_CACHE_LLC_MLC: return " snooped (LLC+MLC)"; | |
08c18323 CW |
117 | default: return ""; |
118 | } | |
119 | } | |
120 | ||
37811fcc CW |
121 | static void |
122 | describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj) | |
123 | { | |
a05a5862 | 124 | seq_printf(m, "%p: %s%s %8zdKiB %04x %04x %d %d%s%s%s", |
37811fcc CW |
125 | &obj->base, |
126 | get_pin_flag(obj), | |
127 | get_tiling_flag(obj), | |
a05a5862 | 128 | obj->base.size / 1024, |
37811fcc CW |
129 | obj->base.read_domains, |
130 | obj->base.write_domain, | |
131 | obj->last_rendering_seqno, | |
caea7476 | 132 | obj->last_fenced_seqno, |
93dfb40c | 133 | cache_level_str(obj->cache_level), |
37811fcc CW |
134 | obj->dirty ? " dirty" : "", |
135 | obj->madv == I915_MADV_DONTNEED ? " purgeable" : ""); | |
136 | if (obj->base.name) | |
137 | seq_printf(m, " (name: %d)", obj->base.name); | |
138 | if (obj->fence_reg != I915_FENCE_REG_NONE) | |
139 | seq_printf(m, " (fence: %d)", obj->fence_reg); | |
140 | if (obj->gtt_space != NULL) | |
a00b10c3 CW |
141 | seq_printf(m, " (gtt offset: %08x, size: %08x)", |
142 | obj->gtt_offset, (unsigned int)obj->gtt_space->size); | |
6299f992 CW |
143 | if (obj->pin_mappable || obj->fault_mappable) { |
144 | char s[3], *t = s; | |
145 | if (obj->pin_mappable) | |
146 | *t++ = 'p'; | |
147 | if (obj->fault_mappable) | |
148 | *t++ = 'f'; | |
149 | *t = '\0'; | |
150 | seq_printf(m, " (%s mappable)", s); | |
151 | } | |
69dc4987 CW |
152 | if (obj->ring != NULL) |
153 | seq_printf(m, " (%s)", obj->ring->name); | |
37811fcc CW |
154 | } |
155 | ||
433e12f7 | 156 | static int i915_gem_object_list_info(struct seq_file *m, void *data) |
2017263e BG |
157 | { |
158 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
433e12f7 BG |
159 | uintptr_t list = (uintptr_t) node->info_ent->data; |
160 | struct list_head *head; | |
2017263e BG |
161 | struct drm_device *dev = node->minor->dev; |
162 | drm_i915_private_t *dev_priv = dev->dev_private; | |
05394f39 | 163 | struct drm_i915_gem_object *obj; |
8f2480fb CW |
164 | size_t total_obj_size, total_gtt_size; |
165 | int count, ret; | |
de227ef0 CW |
166 | |
167 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
168 | if (ret) | |
169 | return ret; | |
2017263e | 170 | |
433e12f7 BG |
171 | switch (list) { |
172 | case ACTIVE_LIST: | |
173 | seq_printf(m, "Active:\n"); | |
69dc4987 | 174 | head = &dev_priv->mm.active_list; |
433e12f7 BG |
175 | break; |
176 | case INACTIVE_LIST: | |
a17458fc | 177 | seq_printf(m, "Inactive:\n"); |
433e12f7 BG |
178 | head = &dev_priv->mm.inactive_list; |
179 | break; | |
f13d3f73 CW |
180 | case PINNED_LIST: |
181 | seq_printf(m, "Pinned:\n"); | |
182 | head = &dev_priv->mm.pinned_list; | |
183 | break; | |
433e12f7 BG |
184 | case FLUSHING_LIST: |
185 | seq_printf(m, "Flushing:\n"); | |
186 | head = &dev_priv->mm.flushing_list; | |
187 | break; | |
d21d5975 CW |
188 | case DEFERRED_FREE_LIST: |
189 | seq_printf(m, "Deferred free:\n"); | |
190 | head = &dev_priv->mm.deferred_free_list; | |
191 | break; | |
433e12f7 | 192 | default: |
de227ef0 CW |
193 | mutex_unlock(&dev->struct_mutex); |
194 | return -EINVAL; | |
2017263e | 195 | } |
2017263e | 196 | |
8f2480fb | 197 | total_obj_size = total_gtt_size = count = 0; |
05394f39 | 198 | list_for_each_entry(obj, head, mm_list) { |
37811fcc | 199 | seq_printf(m, " "); |
05394f39 | 200 | describe_obj(m, obj); |
f4ceda89 | 201 | seq_printf(m, "\n"); |
05394f39 CW |
202 | total_obj_size += obj->base.size; |
203 | total_gtt_size += obj->gtt_space->size; | |
8f2480fb | 204 | count++; |
2017263e | 205 | } |
de227ef0 | 206 | mutex_unlock(&dev->struct_mutex); |
5e118f41 | 207 | |
8f2480fb CW |
208 | seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n", |
209 | count, total_obj_size, total_gtt_size); | |
2017263e BG |
210 | return 0; |
211 | } | |
212 | ||
6299f992 CW |
213 | #define count_objects(list, member) do { \ |
214 | list_for_each_entry(obj, list, member) { \ | |
215 | size += obj->gtt_space->size; \ | |
216 | ++count; \ | |
217 | if (obj->map_and_fenceable) { \ | |
218 | mappable_size += obj->gtt_space->size; \ | |
219 | ++mappable_count; \ | |
220 | } \ | |
221 | } \ | |
0206e353 | 222 | } while (0) |
6299f992 | 223 | |
73aa808f CW |
224 | static int i915_gem_object_info(struct seq_file *m, void* data) |
225 | { | |
226 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
227 | struct drm_device *dev = node->minor->dev; | |
228 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6299f992 CW |
229 | u32 count, mappable_count; |
230 | size_t size, mappable_size; | |
231 | struct drm_i915_gem_object *obj; | |
73aa808f CW |
232 | int ret; |
233 | ||
234 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
235 | if (ret) | |
236 | return ret; | |
237 | ||
6299f992 CW |
238 | seq_printf(m, "%u objects, %zu bytes\n", |
239 | dev_priv->mm.object_count, | |
240 | dev_priv->mm.object_memory); | |
241 | ||
242 | size = count = mappable_size = mappable_count = 0; | |
243 | count_objects(&dev_priv->mm.gtt_list, gtt_list); | |
244 | seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n", | |
245 | count, mappable_count, size, mappable_size); | |
246 | ||
247 | size = count = mappable_size = mappable_count = 0; | |
248 | count_objects(&dev_priv->mm.active_list, mm_list); | |
249 | count_objects(&dev_priv->mm.flushing_list, mm_list); | |
250 | seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n", | |
251 | count, mappable_count, size, mappable_size); | |
252 | ||
253 | size = count = mappable_size = mappable_count = 0; | |
254 | count_objects(&dev_priv->mm.pinned_list, mm_list); | |
255 | seq_printf(m, " %u [%u] pinned objects, %zu [%zu] bytes\n", | |
256 | count, mappable_count, size, mappable_size); | |
257 | ||
258 | size = count = mappable_size = mappable_count = 0; | |
259 | count_objects(&dev_priv->mm.inactive_list, mm_list); | |
260 | seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n", | |
261 | count, mappable_count, size, mappable_size); | |
262 | ||
263 | size = count = mappable_size = mappable_count = 0; | |
264 | count_objects(&dev_priv->mm.deferred_free_list, mm_list); | |
265 | seq_printf(m, " %u [%u] freed objects, %zu [%zu] bytes\n", | |
266 | count, mappable_count, size, mappable_size); | |
267 | ||
268 | size = count = mappable_size = mappable_count = 0; | |
269 | list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) { | |
270 | if (obj->fault_mappable) { | |
271 | size += obj->gtt_space->size; | |
272 | ++count; | |
273 | } | |
274 | if (obj->pin_mappable) { | |
275 | mappable_size += obj->gtt_space->size; | |
276 | ++mappable_count; | |
277 | } | |
278 | } | |
279 | seq_printf(m, "%u pinned mappable objects, %zu bytes\n", | |
280 | mappable_count, mappable_size); | |
281 | seq_printf(m, "%u fault mappable objects, %zu bytes\n", | |
282 | count, size); | |
283 | ||
284 | seq_printf(m, "%zu [%zu] gtt total\n", | |
285 | dev_priv->mm.gtt_total, dev_priv->mm.mappable_gtt_total); | |
73aa808f CW |
286 | |
287 | mutex_unlock(&dev->struct_mutex); | |
288 | ||
289 | return 0; | |
290 | } | |
291 | ||
08c18323 CW |
292 | static int i915_gem_gtt_info(struct seq_file *m, void* data) |
293 | { | |
294 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
295 | struct drm_device *dev = node->minor->dev; | |
296 | struct drm_i915_private *dev_priv = dev->dev_private; | |
297 | struct drm_i915_gem_object *obj; | |
298 | size_t total_obj_size, total_gtt_size; | |
299 | int count, ret; | |
300 | ||
301 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
302 | if (ret) | |
303 | return ret; | |
304 | ||
305 | total_obj_size = total_gtt_size = count = 0; | |
306 | list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) { | |
307 | seq_printf(m, " "); | |
308 | describe_obj(m, obj); | |
309 | seq_printf(m, "\n"); | |
310 | total_obj_size += obj->base.size; | |
311 | total_gtt_size += obj->gtt_space->size; | |
312 | count++; | |
313 | } | |
314 | ||
315 | mutex_unlock(&dev->struct_mutex); | |
316 | ||
317 | seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n", | |
318 | count, total_obj_size, total_gtt_size); | |
319 | ||
320 | return 0; | |
321 | } | |
322 | ||
73aa808f | 323 | |
4e5359cd SF |
324 | static int i915_gem_pageflip_info(struct seq_file *m, void *data) |
325 | { | |
326 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
327 | struct drm_device *dev = node->minor->dev; | |
328 | unsigned long flags; | |
329 | struct intel_crtc *crtc; | |
330 | ||
331 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { | |
9db4a9c7 JB |
332 | const char pipe = pipe_name(crtc->pipe); |
333 | const char plane = plane_name(crtc->plane); | |
4e5359cd SF |
334 | struct intel_unpin_work *work; |
335 | ||
336 | spin_lock_irqsave(&dev->event_lock, flags); | |
337 | work = crtc->unpin_work; | |
338 | if (work == NULL) { | |
9db4a9c7 | 339 | seq_printf(m, "No flip due on pipe %c (plane %c)\n", |
4e5359cd SF |
340 | pipe, plane); |
341 | } else { | |
342 | if (!work->pending) { | |
9db4a9c7 | 343 | seq_printf(m, "Flip queued on pipe %c (plane %c)\n", |
4e5359cd SF |
344 | pipe, plane); |
345 | } else { | |
9db4a9c7 | 346 | seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n", |
4e5359cd SF |
347 | pipe, plane); |
348 | } | |
349 | if (work->enable_stall_check) | |
350 | seq_printf(m, "Stall check enabled, "); | |
351 | else | |
352 | seq_printf(m, "Stall check waiting for page flip ioctl, "); | |
353 | seq_printf(m, "%d prepares\n", work->pending); | |
354 | ||
355 | if (work->old_fb_obj) { | |
05394f39 CW |
356 | struct drm_i915_gem_object *obj = work->old_fb_obj; |
357 | if (obj) | |
358 | seq_printf(m, "Old framebuffer gtt_offset 0x%08x\n", obj->gtt_offset); | |
4e5359cd SF |
359 | } |
360 | if (work->pending_flip_obj) { | |
05394f39 CW |
361 | struct drm_i915_gem_object *obj = work->pending_flip_obj; |
362 | if (obj) | |
363 | seq_printf(m, "New framebuffer gtt_offset 0x%08x\n", obj->gtt_offset); | |
4e5359cd SF |
364 | } |
365 | } | |
366 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
367 | } | |
368 | ||
369 | return 0; | |
370 | } | |
371 | ||
2017263e BG |
372 | static int i915_gem_request_info(struct seq_file *m, void *data) |
373 | { | |
374 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
375 | struct drm_device *dev = node->minor->dev; | |
376 | drm_i915_private_t *dev_priv = dev->dev_private; | |
377 | struct drm_i915_gem_request *gem_request; | |
c2c347a9 | 378 | int ret, count; |
de227ef0 CW |
379 | |
380 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
381 | if (ret) | |
382 | return ret; | |
2017263e | 383 | |
c2c347a9 | 384 | count = 0; |
1ec14ad3 | 385 | if (!list_empty(&dev_priv->ring[RCS].request_list)) { |
c2c347a9 CW |
386 | seq_printf(m, "Render requests:\n"); |
387 | list_for_each_entry(gem_request, | |
1ec14ad3 | 388 | &dev_priv->ring[RCS].request_list, |
c2c347a9 CW |
389 | list) { |
390 | seq_printf(m, " %d @ %d\n", | |
391 | gem_request->seqno, | |
392 | (int) (jiffies - gem_request->emitted_jiffies)); | |
393 | } | |
394 | count++; | |
395 | } | |
1ec14ad3 | 396 | if (!list_empty(&dev_priv->ring[VCS].request_list)) { |
c2c347a9 CW |
397 | seq_printf(m, "BSD requests:\n"); |
398 | list_for_each_entry(gem_request, | |
1ec14ad3 | 399 | &dev_priv->ring[VCS].request_list, |
c2c347a9 CW |
400 | list) { |
401 | seq_printf(m, " %d @ %d\n", | |
402 | gem_request->seqno, | |
403 | (int) (jiffies - gem_request->emitted_jiffies)); | |
404 | } | |
405 | count++; | |
406 | } | |
1ec14ad3 | 407 | if (!list_empty(&dev_priv->ring[BCS].request_list)) { |
c2c347a9 CW |
408 | seq_printf(m, "BLT requests:\n"); |
409 | list_for_each_entry(gem_request, | |
1ec14ad3 | 410 | &dev_priv->ring[BCS].request_list, |
c2c347a9 CW |
411 | list) { |
412 | seq_printf(m, " %d @ %d\n", | |
413 | gem_request->seqno, | |
414 | (int) (jiffies - gem_request->emitted_jiffies)); | |
415 | } | |
416 | count++; | |
2017263e | 417 | } |
de227ef0 CW |
418 | mutex_unlock(&dev->struct_mutex); |
419 | ||
c2c347a9 CW |
420 | if (count == 0) |
421 | seq_printf(m, "No requests\n"); | |
422 | ||
2017263e BG |
423 | return 0; |
424 | } | |
425 | ||
b2223497 CW |
426 | static void i915_ring_seqno_info(struct seq_file *m, |
427 | struct intel_ring_buffer *ring) | |
428 | { | |
429 | if (ring->get_seqno) { | |
430 | seq_printf(m, "Current sequence (%s): %d\n", | |
431 | ring->name, ring->get_seqno(ring)); | |
432 | seq_printf(m, "Waiter sequence (%s): %d\n", | |
433 | ring->name, ring->waiting_seqno); | |
434 | seq_printf(m, "IRQ sequence (%s): %d\n", | |
435 | ring->name, ring->irq_seqno); | |
436 | } | |
437 | } | |
438 | ||
2017263e BG |
439 | static int i915_gem_seqno_info(struct seq_file *m, void *data) |
440 | { | |
441 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
442 | struct drm_device *dev = node->minor->dev; | |
443 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1ec14ad3 | 444 | int ret, i; |
de227ef0 CW |
445 | |
446 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
447 | if (ret) | |
448 | return ret; | |
2017263e | 449 | |
1ec14ad3 CW |
450 | for (i = 0; i < I915_NUM_RINGS; i++) |
451 | i915_ring_seqno_info(m, &dev_priv->ring[i]); | |
de227ef0 CW |
452 | |
453 | mutex_unlock(&dev->struct_mutex); | |
454 | ||
2017263e BG |
455 | return 0; |
456 | } | |
457 | ||
458 | ||
459 | static int i915_interrupt_info(struct seq_file *m, void *data) | |
460 | { | |
461 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
462 | struct drm_device *dev = node->minor->dev; | |
463 | drm_i915_private_t *dev_priv = dev->dev_private; | |
9db4a9c7 | 464 | int ret, i, pipe; |
de227ef0 CW |
465 | |
466 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
467 | if (ret) | |
468 | return ret; | |
2017263e | 469 | |
bad720ff | 470 | if (!HAS_PCH_SPLIT(dev)) { |
5f6a1695 ZW |
471 | seq_printf(m, "Interrupt enable: %08x\n", |
472 | I915_READ(IER)); | |
473 | seq_printf(m, "Interrupt identity: %08x\n", | |
474 | I915_READ(IIR)); | |
475 | seq_printf(m, "Interrupt mask: %08x\n", | |
476 | I915_READ(IMR)); | |
9db4a9c7 JB |
477 | for_each_pipe(pipe) |
478 | seq_printf(m, "Pipe %c stat: %08x\n", | |
479 | pipe_name(pipe), | |
480 | I915_READ(PIPESTAT(pipe))); | |
5f6a1695 ZW |
481 | } else { |
482 | seq_printf(m, "North Display Interrupt enable: %08x\n", | |
483 | I915_READ(DEIER)); | |
484 | seq_printf(m, "North Display Interrupt identity: %08x\n", | |
485 | I915_READ(DEIIR)); | |
486 | seq_printf(m, "North Display Interrupt mask: %08x\n", | |
487 | I915_READ(DEIMR)); | |
488 | seq_printf(m, "South Display Interrupt enable: %08x\n", | |
489 | I915_READ(SDEIER)); | |
490 | seq_printf(m, "South Display Interrupt identity: %08x\n", | |
491 | I915_READ(SDEIIR)); | |
492 | seq_printf(m, "South Display Interrupt mask: %08x\n", | |
493 | I915_READ(SDEIMR)); | |
494 | seq_printf(m, "Graphics Interrupt enable: %08x\n", | |
495 | I915_READ(GTIER)); | |
496 | seq_printf(m, "Graphics Interrupt identity: %08x\n", | |
497 | I915_READ(GTIIR)); | |
498 | seq_printf(m, "Graphics Interrupt mask: %08x\n", | |
499 | I915_READ(GTIMR)); | |
500 | } | |
2017263e BG |
501 | seq_printf(m, "Interrupts received: %d\n", |
502 | atomic_read(&dev_priv->irq_received)); | |
9862e600 | 503 | for (i = 0; i < I915_NUM_RINGS; i++) { |
da64c6fc | 504 | if (IS_GEN6(dev) || IS_GEN7(dev)) { |
9862e600 CW |
505 | seq_printf(m, "Graphics Interrupt mask (%s): %08x\n", |
506 | dev_priv->ring[i].name, | |
507 | I915_READ_IMR(&dev_priv->ring[i])); | |
508 | } | |
1ec14ad3 | 509 | i915_ring_seqno_info(m, &dev_priv->ring[i]); |
9862e600 | 510 | } |
de227ef0 CW |
511 | mutex_unlock(&dev->struct_mutex); |
512 | ||
2017263e BG |
513 | return 0; |
514 | } | |
515 | ||
a6172a80 CW |
516 | static int i915_gem_fence_regs_info(struct seq_file *m, void *data) |
517 | { | |
518 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
519 | struct drm_device *dev = node->minor->dev; | |
520 | drm_i915_private_t *dev_priv = dev->dev_private; | |
de227ef0 CW |
521 | int i, ret; |
522 | ||
523 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
524 | if (ret) | |
525 | return ret; | |
a6172a80 CW |
526 | |
527 | seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start); | |
528 | seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs); | |
529 | for (i = 0; i < dev_priv->num_fence_regs; i++) { | |
05394f39 | 530 | struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj; |
a6172a80 | 531 | |
c2c347a9 CW |
532 | seq_printf(m, "Fenced object[%2d] = ", i); |
533 | if (obj == NULL) | |
534 | seq_printf(m, "unused"); | |
535 | else | |
05394f39 | 536 | describe_obj(m, obj); |
c2c347a9 | 537 | seq_printf(m, "\n"); |
a6172a80 CW |
538 | } |
539 | ||
05394f39 | 540 | mutex_unlock(&dev->struct_mutex); |
a6172a80 CW |
541 | return 0; |
542 | } | |
543 | ||
2017263e BG |
544 | static int i915_hws_info(struct seq_file *m, void *data) |
545 | { | |
546 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
547 | struct drm_device *dev = node->minor->dev; | |
548 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4066c0ae | 549 | struct intel_ring_buffer *ring; |
311bd68e | 550 | const volatile u32 __iomem *hws; |
4066c0ae CW |
551 | int i; |
552 | ||
1ec14ad3 | 553 | ring = &dev_priv->ring[(uintptr_t)node->info_ent->data]; |
311bd68e | 554 | hws = (volatile u32 __iomem *)ring->status_page.page_addr; |
2017263e BG |
555 | if (hws == NULL) |
556 | return 0; | |
557 | ||
558 | for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) { | |
559 | seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n", | |
560 | i * 4, | |
561 | hws[i], hws[i + 1], hws[i + 2], hws[i + 3]); | |
562 | } | |
563 | return 0; | |
564 | } | |
565 | ||
5cdf5881 CW |
566 | static void i915_dump_object(struct seq_file *m, |
567 | struct io_mapping *mapping, | |
05394f39 | 568 | struct drm_i915_gem_object *obj) |
6911a9b8 | 569 | { |
5cdf5881 | 570 | int page, page_count, i; |
6911a9b8 | 571 | |
05394f39 | 572 | page_count = obj->base.size / PAGE_SIZE; |
6911a9b8 | 573 | for (page = 0; page < page_count; page++) { |
5cdf5881 | 574 | u32 *mem = io_mapping_map_wc(mapping, |
05394f39 | 575 | obj->gtt_offset + page * PAGE_SIZE); |
6911a9b8 BG |
576 | for (i = 0; i < PAGE_SIZE; i += 4) |
577 | seq_printf(m, "%08x : %08x\n", i, mem[i / 4]); | |
5cdf5881 | 578 | io_mapping_unmap(mem); |
6911a9b8 BG |
579 | } |
580 | } | |
581 | ||
582 | static int i915_batchbuffer_info(struct seq_file *m, void *data) | |
583 | { | |
584 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
585 | struct drm_device *dev = node->minor->dev; | |
586 | drm_i915_private_t *dev_priv = dev->dev_private; | |
05394f39 | 587 | struct drm_i915_gem_object *obj; |
6911a9b8 BG |
588 | int ret; |
589 | ||
de227ef0 CW |
590 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
591 | if (ret) | |
592 | return ret; | |
6911a9b8 | 593 | |
05394f39 CW |
594 | list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) { |
595 | if (obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) { | |
596 | seq_printf(m, "--- gtt_offset = 0x%08x\n", obj->gtt_offset); | |
597 | i915_dump_object(m, dev_priv->mm.gtt_mapping, obj); | |
6911a9b8 BG |
598 | } |
599 | } | |
600 | ||
de227ef0 | 601 | mutex_unlock(&dev->struct_mutex); |
6911a9b8 BG |
602 | return 0; |
603 | } | |
604 | ||
605 | static int i915_ringbuffer_data(struct seq_file *m, void *data) | |
606 | { | |
607 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
608 | struct drm_device *dev = node->minor->dev; | |
609 | drm_i915_private_t *dev_priv = dev->dev_private; | |
c2c347a9 | 610 | struct intel_ring_buffer *ring; |
de227ef0 CW |
611 | int ret; |
612 | ||
613 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
614 | if (ret) | |
615 | return ret; | |
6911a9b8 | 616 | |
1ec14ad3 | 617 | ring = &dev_priv->ring[(uintptr_t)node->info_ent->data]; |
05394f39 | 618 | if (!ring->obj) { |
6911a9b8 | 619 | seq_printf(m, "No ringbuffer setup\n"); |
de227ef0 | 620 | } else { |
311bd68e | 621 | const u8 __iomem *virt = ring->virtual_start; |
de227ef0 | 622 | uint32_t off; |
6911a9b8 | 623 | |
c2c347a9 | 624 | for (off = 0; off < ring->size; off += 4) { |
de227ef0 CW |
625 | uint32_t *ptr = (uint32_t *)(virt + off); |
626 | seq_printf(m, "%08x : %08x\n", off, *ptr); | |
627 | } | |
6911a9b8 | 628 | } |
de227ef0 | 629 | mutex_unlock(&dev->struct_mutex); |
6911a9b8 BG |
630 | |
631 | return 0; | |
632 | } | |
633 | ||
634 | static int i915_ringbuffer_info(struct seq_file *m, void *data) | |
635 | { | |
636 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
637 | struct drm_device *dev = node->minor->dev; | |
638 | drm_i915_private_t *dev_priv = dev->dev_private; | |
c2c347a9 | 639 | struct intel_ring_buffer *ring; |
616fdb5a | 640 | int ret; |
c2c347a9 | 641 | |
1ec14ad3 | 642 | ring = &dev_priv->ring[(uintptr_t)node->info_ent->data]; |
c2c347a9 | 643 | if (ring->size == 0) |
1ec14ad3 | 644 | return 0; |
6911a9b8 | 645 | |
616fdb5a BW |
646 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
647 | if (ret) | |
648 | return ret; | |
649 | ||
c2c347a9 CW |
650 | seq_printf(m, "Ring %s:\n", ring->name); |
651 | seq_printf(m, " Head : %08x\n", I915_READ_HEAD(ring) & HEAD_ADDR); | |
652 | seq_printf(m, " Tail : %08x\n", I915_READ_TAIL(ring) & TAIL_ADDR); | |
653 | seq_printf(m, " Size : %08x\n", ring->size); | |
654 | seq_printf(m, " Active : %08x\n", intel_ring_get_active_head(ring)); | |
1ec14ad3 CW |
655 | seq_printf(m, " NOPID : %08x\n", I915_READ_NOPID(ring)); |
656 | if (IS_GEN6(dev)) { | |
657 | seq_printf(m, " Sync 0 : %08x\n", I915_READ_SYNC_0(ring)); | |
658 | seq_printf(m, " Sync 1 : %08x\n", I915_READ_SYNC_1(ring)); | |
659 | } | |
c2c347a9 CW |
660 | seq_printf(m, " Control : %08x\n", I915_READ_CTL(ring)); |
661 | seq_printf(m, " Start : %08x\n", I915_READ_START(ring)); | |
6911a9b8 | 662 | |
616fdb5a BW |
663 | mutex_unlock(&dev->struct_mutex); |
664 | ||
6911a9b8 BG |
665 | return 0; |
666 | } | |
667 | ||
e5c65260 CW |
668 | static const char *ring_str(int ring) |
669 | { | |
670 | switch (ring) { | |
3685092b CW |
671 | case RING_RENDER: return " render"; |
672 | case RING_BSD: return " bsd"; | |
673 | case RING_BLT: return " blt"; | |
e5c65260 CW |
674 | default: return ""; |
675 | } | |
676 | } | |
677 | ||
9df30794 CW |
678 | static const char *pin_flag(int pinned) |
679 | { | |
680 | if (pinned > 0) | |
681 | return " P"; | |
682 | else if (pinned < 0) | |
683 | return " p"; | |
684 | else | |
685 | return ""; | |
686 | } | |
687 | ||
688 | static const char *tiling_flag(int tiling) | |
689 | { | |
690 | switch (tiling) { | |
691 | default: | |
692 | case I915_TILING_NONE: return ""; | |
693 | case I915_TILING_X: return " X"; | |
694 | case I915_TILING_Y: return " Y"; | |
695 | } | |
696 | } | |
697 | ||
698 | static const char *dirty_flag(int dirty) | |
699 | { | |
700 | return dirty ? " dirty" : ""; | |
701 | } | |
702 | ||
703 | static const char *purgeable_flag(int purgeable) | |
704 | { | |
705 | return purgeable ? " purgeable" : ""; | |
706 | } | |
707 | ||
c724e8a9 CW |
708 | static void print_error_buffers(struct seq_file *m, |
709 | const char *name, | |
710 | struct drm_i915_error_buffer *err, | |
711 | int count) | |
712 | { | |
713 | seq_printf(m, "%s [%d]:\n", name, count); | |
714 | ||
715 | while (count--) { | |
833bcb00 | 716 | seq_printf(m, " %08x %8u %04x %04x %08x%s%s%s%s%s%s", |
c724e8a9 CW |
717 | err->gtt_offset, |
718 | err->size, | |
719 | err->read_domains, | |
720 | err->write_domain, | |
721 | err->seqno, | |
722 | pin_flag(err->pinned), | |
723 | tiling_flag(err->tiling), | |
724 | dirty_flag(err->dirty), | |
725 | purgeable_flag(err->purgeable), | |
a779e5ab | 726 | ring_str(err->ring), |
93dfb40c | 727 | cache_level_str(err->cache_level)); |
c724e8a9 CW |
728 | |
729 | if (err->name) | |
730 | seq_printf(m, " (name: %d)", err->name); | |
731 | if (err->fence_reg != I915_FENCE_REG_NONE) | |
732 | seq_printf(m, " (fence: %d)", err->fence_reg); | |
733 | ||
734 | seq_printf(m, "\n"); | |
735 | err++; | |
736 | } | |
737 | } | |
738 | ||
63eeaf38 JB |
739 | static int i915_error_state(struct seq_file *m, void *unused) |
740 | { | |
741 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
742 | struct drm_device *dev = node->minor->dev; | |
743 | drm_i915_private_t *dev_priv = dev->dev_private; | |
744 | struct drm_i915_error_state *error; | |
745 | unsigned long flags; | |
9df30794 | 746 | int i, page, offset, elt; |
63eeaf38 JB |
747 | |
748 | spin_lock_irqsave(&dev_priv->error_lock, flags); | |
749 | if (!dev_priv->first_error) { | |
750 | seq_printf(m, "no error state collected\n"); | |
751 | goto out; | |
752 | } | |
753 | ||
754 | error = dev_priv->first_error; | |
755 | ||
8a905236 JB |
756 | seq_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec, |
757 | error->time.tv_usec); | |
9df30794 | 758 | seq_printf(m, "PCI ID: 0x%04x\n", dev->pci_device); |
1d8f38f4 CW |
759 | seq_printf(m, "EIR: 0x%08x\n", error->eir); |
760 | seq_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er); | |
f406839f CW |
761 | if (INTEL_INFO(dev)->gen >= 6) { |
762 | seq_printf(m, "ERROR: 0x%08x\n", error->error); | |
1d8f38f4 CW |
763 | seq_printf(m, "Blitter command stream:\n"); |
764 | seq_printf(m, " ACTHD: 0x%08x\n", error->bcs_acthd); | |
1d8f38f4 | 765 | seq_printf(m, " IPEIR: 0x%08x\n", error->bcs_ipeir); |
e5c65260 | 766 | seq_printf(m, " IPEHR: 0x%08x\n", error->bcs_ipehr); |
1d8f38f4 CW |
767 | seq_printf(m, " INSTDONE: 0x%08x\n", error->bcs_instdone); |
768 | seq_printf(m, " seqno: 0x%08x\n", error->bcs_seqno); | |
add354dd CW |
769 | seq_printf(m, "Video (BSD) command stream:\n"); |
770 | seq_printf(m, " ACTHD: 0x%08x\n", error->vcs_acthd); | |
add354dd | 771 | seq_printf(m, " IPEIR: 0x%08x\n", error->vcs_ipeir); |
e5c65260 | 772 | seq_printf(m, " IPEHR: 0x%08x\n", error->vcs_ipehr); |
add354dd CW |
773 | seq_printf(m, " INSTDONE: 0x%08x\n", error->vcs_instdone); |
774 | seq_printf(m, " seqno: 0x%08x\n", error->vcs_seqno); | |
f406839f | 775 | } |
1d8f38f4 CW |
776 | seq_printf(m, "Render command stream:\n"); |
777 | seq_printf(m, " ACTHD: 0x%08x\n", error->acthd); | |
63eeaf38 JB |
778 | seq_printf(m, " IPEIR: 0x%08x\n", error->ipeir); |
779 | seq_printf(m, " IPEHR: 0x%08x\n", error->ipehr); | |
780 | seq_printf(m, " INSTDONE: 0x%08x\n", error->instdone); | |
a6c45cf0 | 781 | if (INTEL_INFO(dev)->gen >= 4) { |
63eeaf38 | 782 | seq_printf(m, " INSTDONE1: 0x%08x\n", error->instdone1); |
1d8f38f4 | 783 | seq_printf(m, " INSTPS: 0x%08x\n", error->instps); |
63eeaf38 | 784 | } |
1d8f38f4 CW |
785 | seq_printf(m, " INSTPM: 0x%08x\n", error->instpm); |
786 | seq_printf(m, " seqno: 0x%08x\n", error->seqno); | |
9df30794 | 787 | |
bf3301ab | 788 | for (i = 0; i < dev_priv->num_fence_regs; i++) |
748ebc60 CW |
789 | seq_printf(m, " fence[%d] = %08llx\n", i, error->fence[i]); |
790 | ||
c724e8a9 CW |
791 | if (error->active_bo) |
792 | print_error_buffers(m, "Active", | |
793 | error->active_bo, | |
794 | error->active_bo_count); | |
795 | ||
796 | if (error->pinned_bo) | |
797 | print_error_buffers(m, "Pinned", | |
798 | error->pinned_bo, | |
799 | error->pinned_bo_count); | |
9df30794 CW |
800 | |
801 | for (i = 0; i < ARRAY_SIZE(error->batchbuffer); i++) { | |
802 | if (error->batchbuffer[i]) { | |
803 | struct drm_i915_error_object *obj = error->batchbuffer[i]; | |
804 | ||
bcfb2e28 CW |
805 | seq_printf(m, "%s --- gtt_offset = 0x%08x\n", |
806 | dev_priv->ring[i].name, | |
807 | obj->gtt_offset); | |
9df30794 CW |
808 | offset = 0; |
809 | for (page = 0; page < obj->page_count; page++) { | |
810 | for (elt = 0; elt < PAGE_SIZE/4; elt++) { | |
811 | seq_printf(m, "%08x : %08x\n", offset, obj->pages[page][elt]); | |
812 | offset += 4; | |
813 | } | |
814 | } | |
815 | } | |
816 | } | |
817 | ||
e2f973d5 CW |
818 | for (i = 0; i < ARRAY_SIZE(error->ringbuffer); i++) { |
819 | if (error->ringbuffer[i]) { | |
820 | struct drm_i915_error_object *obj = error->ringbuffer[i]; | |
821 | seq_printf(m, "%s --- ringbuffer = 0x%08x\n", | |
822 | dev_priv->ring[i].name, | |
823 | obj->gtt_offset); | |
824 | offset = 0; | |
825 | for (page = 0; page < obj->page_count; page++) { | |
826 | for (elt = 0; elt < PAGE_SIZE/4; elt++) { | |
827 | seq_printf(m, "%08x : %08x\n", | |
828 | offset, | |
829 | obj->pages[page][elt]); | |
830 | offset += 4; | |
831 | } | |
9df30794 CW |
832 | } |
833 | } | |
834 | } | |
63eeaf38 | 835 | |
6ef3d427 CW |
836 | if (error->overlay) |
837 | intel_overlay_print_error_state(m, error->overlay); | |
838 | ||
c4a1d9e4 CW |
839 | if (error->display) |
840 | intel_display_print_error_state(m, dev, error->display); | |
841 | ||
63eeaf38 JB |
842 | out: |
843 | spin_unlock_irqrestore(&dev_priv->error_lock, flags); | |
844 | ||
845 | return 0; | |
846 | } | |
6911a9b8 | 847 | |
f97108d1 JB |
848 | static int i915_rstdby_delays(struct seq_file *m, void *unused) |
849 | { | |
850 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
851 | struct drm_device *dev = node->minor->dev; | |
852 | drm_i915_private_t *dev_priv = dev->dev_private; | |
616fdb5a BW |
853 | u16 crstanddelay; |
854 | int ret; | |
855 | ||
856 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
857 | if (ret) | |
858 | return ret; | |
859 | ||
860 | crstanddelay = I915_READ16(CRSTANDVID); | |
861 | ||
862 | mutex_unlock(&dev->struct_mutex); | |
f97108d1 JB |
863 | |
864 | seq_printf(m, "w/ctx: %d, w/o ctx: %d\n", (crstanddelay >> 8) & 0x3f, (crstanddelay & 0x3f)); | |
865 | ||
866 | return 0; | |
867 | } | |
868 | ||
869 | static int i915_cur_delayinfo(struct seq_file *m, void *unused) | |
870 | { | |
871 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
872 | struct drm_device *dev = node->minor->dev; | |
873 | drm_i915_private_t *dev_priv = dev->dev_private; | |
d1ebd816 | 874 | int ret; |
3b8d8d91 JB |
875 | |
876 | if (IS_GEN5(dev)) { | |
877 | u16 rgvswctl = I915_READ16(MEMSWCTL); | |
878 | u16 rgvstat = I915_READ16(MEMSTAT_ILK); | |
879 | ||
880 | seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf); | |
881 | seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f); | |
882 | seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >> | |
883 | MEMSTAT_VID_SHIFT); | |
884 | seq_printf(m, "Current P-state: %d\n", | |
885 | (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT); | |
1c70c0ce | 886 | } else if (IS_GEN6(dev) || IS_GEN7(dev)) { |
3b8d8d91 JB |
887 | u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS); |
888 | u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS); | |
889 | u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); | |
ccab5c82 JB |
890 | u32 rpstat; |
891 | u32 rpupei, rpcurup, rpprevup; | |
892 | u32 rpdownei, rpcurdown, rpprevdown; | |
3b8d8d91 JB |
893 | int max_freq; |
894 | ||
895 | /* RPSTAT1 is in the GT power well */ | |
d1ebd816 BW |
896 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
897 | if (ret) | |
898 | return ret; | |
899 | ||
fcca7926 | 900 | gen6_gt_force_wake_get(dev_priv); |
3b8d8d91 | 901 | |
ccab5c82 JB |
902 | rpstat = I915_READ(GEN6_RPSTAT1); |
903 | rpupei = I915_READ(GEN6_RP_CUR_UP_EI); | |
904 | rpcurup = I915_READ(GEN6_RP_CUR_UP); | |
905 | rpprevup = I915_READ(GEN6_RP_PREV_UP); | |
906 | rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI); | |
907 | rpcurdown = I915_READ(GEN6_RP_CUR_DOWN); | |
908 | rpprevdown = I915_READ(GEN6_RP_PREV_DOWN); | |
909 | ||
d1ebd816 BW |
910 | gen6_gt_force_wake_put(dev_priv); |
911 | mutex_unlock(&dev->struct_mutex); | |
912 | ||
3b8d8d91 | 913 | seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status); |
ccab5c82 | 914 | seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat); |
3b8d8d91 JB |
915 | seq_printf(m, "Render p-state ratio: %d\n", |
916 | (gt_perf_status & 0xff00) >> 8); | |
917 | seq_printf(m, "Render p-state VID: %d\n", | |
918 | gt_perf_status & 0xff); | |
919 | seq_printf(m, "Render p-state limit: %d\n", | |
920 | rp_state_limits & 0xff); | |
ccab5c82 | 921 | seq_printf(m, "CAGF: %dMHz\n", ((rpstat & GEN6_CAGF_MASK) >> |
e281fcaa | 922 | GEN6_CAGF_SHIFT) * 50); |
ccab5c82 JB |
923 | seq_printf(m, "RP CUR UP EI: %dus\n", rpupei & |
924 | GEN6_CURICONT_MASK); | |
925 | seq_printf(m, "RP CUR UP: %dus\n", rpcurup & | |
926 | GEN6_CURBSYTAVG_MASK); | |
927 | seq_printf(m, "RP PREV UP: %dus\n", rpprevup & | |
928 | GEN6_CURBSYTAVG_MASK); | |
929 | seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei & | |
930 | GEN6_CURIAVG_MASK); | |
931 | seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown & | |
932 | GEN6_CURBSYTAVG_MASK); | |
933 | seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown & | |
934 | GEN6_CURBSYTAVG_MASK); | |
3b8d8d91 JB |
935 | |
936 | max_freq = (rp_state_cap & 0xff0000) >> 16; | |
937 | seq_printf(m, "Lowest (RPN) frequency: %dMHz\n", | |
e281fcaa | 938 | max_freq * 50); |
3b8d8d91 JB |
939 | |
940 | max_freq = (rp_state_cap & 0xff00) >> 8; | |
941 | seq_printf(m, "Nominal (RP1) frequency: %dMHz\n", | |
e281fcaa | 942 | max_freq * 50); |
3b8d8d91 JB |
943 | |
944 | max_freq = rp_state_cap & 0xff; | |
945 | seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n", | |
e281fcaa | 946 | max_freq * 50); |
3b8d8d91 JB |
947 | } else { |
948 | seq_printf(m, "no P-state info available\n"); | |
949 | } | |
f97108d1 JB |
950 | |
951 | return 0; | |
952 | } | |
953 | ||
954 | static int i915_delayfreq_table(struct seq_file *m, void *unused) | |
955 | { | |
956 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
957 | struct drm_device *dev = node->minor->dev; | |
958 | drm_i915_private_t *dev_priv = dev->dev_private; | |
959 | u32 delayfreq; | |
616fdb5a BW |
960 | int ret, i; |
961 | ||
962 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
963 | if (ret) | |
964 | return ret; | |
f97108d1 JB |
965 | |
966 | for (i = 0; i < 16; i++) { | |
967 | delayfreq = I915_READ(PXVFREQ_BASE + i * 4); | |
7648fa99 JB |
968 | seq_printf(m, "P%02dVIDFREQ: 0x%08x (VID: %d)\n", i, delayfreq, |
969 | (delayfreq & PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT); | |
f97108d1 JB |
970 | } |
971 | ||
616fdb5a BW |
972 | mutex_unlock(&dev->struct_mutex); |
973 | ||
f97108d1 JB |
974 | return 0; |
975 | } | |
976 | ||
977 | static inline int MAP_TO_MV(int map) | |
978 | { | |
979 | return 1250 - (map * 25); | |
980 | } | |
981 | ||
982 | static int i915_inttoext_table(struct seq_file *m, void *unused) | |
983 | { | |
984 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
985 | struct drm_device *dev = node->minor->dev; | |
986 | drm_i915_private_t *dev_priv = dev->dev_private; | |
987 | u32 inttoext; | |
616fdb5a BW |
988 | int ret, i; |
989 | ||
990 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
991 | if (ret) | |
992 | return ret; | |
f97108d1 JB |
993 | |
994 | for (i = 1; i <= 32; i++) { | |
995 | inttoext = I915_READ(INTTOEXT_BASE_ILK + i * 4); | |
996 | seq_printf(m, "INTTOEXT%02d: 0x%08x\n", i, inttoext); | |
997 | } | |
998 | ||
616fdb5a BW |
999 | mutex_unlock(&dev->struct_mutex); |
1000 | ||
f97108d1 JB |
1001 | return 0; |
1002 | } | |
1003 | ||
4d85529d | 1004 | static int ironlake_drpc_info(struct seq_file *m) |
f97108d1 JB |
1005 | { |
1006 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1007 | struct drm_device *dev = node->minor->dev; | |
1008 | drm_i915_private_t *dev_priv = dev->dev_private; | |
616fdb5a BW |
1009 | u32 rgvmodectl, rstdbyctl; |
1010 | u16 crstandvid; | |
1011 | int ret; | |
1012 | ||
1013 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1014 | if (ret) | |
1015 | return ret; | |
1016 | ||
1017 | rgvmodectl = I915_READ(MEMMODECTL); | |
1018 | rstdbyctl = I915_READ(RSTDBYCTL); | |
1019 | crstandvid = I915_READ16(CRSTANDVID); | |
1020 | ||
1021 | mutex_unlock(&dev->struct_mutex); | |
f97108d1 JB |
1022 | |
1023 | seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ? | |
1024 | "yes" : "no"); | |
1025 | seq_printf(m, "Boost freq: %d\n", | |
1026 | (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >> | |
1027 | MEMMODE_BOOST_FREQ_SHIFT); | |
1028 | seq_printf(m, "HW control enabled: %s\n", | |
1029 | rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no"); | |
1030 | seq_printf(m, "SW control enabled: %s\n", | |
1031 | rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no"); | |
1032 | seq_printf(m, "Gated voltage change: %s\n", | |
1033 | rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no"); | |
1034 | seq_printf(m, "Starting frequency: P%d\n", | |
1035 | (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT); | |
7648fa99 | 1036 | seq_printf(m, "Max P-state: P%d\n", |
f97108d1 | 1037 | (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT); |
7648fa99 JB |
1038 | seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK)); |
1039 | seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f)); | |
1040 | seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f)); | |
1041 | seq_printf(m, "Render standby enabled: %s\n", | |
1042 | (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes"); | |
88271da3 JB |
1043 | seq_printf(m, "Current RS state: "); |
1044 | switch (rstdbyctl & RSX_STATUS_MASK) { | |
1045 | case RSX_STATUS_ON: | |
1046 | seq_printf(m, "on\n"); | |
1047 | break; | |
1048 | case RSX_STATUS_RC1: | |
1049 | seq_printf(m, "RC1\n"); | |
1050 | break; | |
1051 | case RSX_STATUS_RC1E: | |
1052 | seq_printf(m, "RC1E\n"); | |
1053 | break; | |
1054 | case RSX_STATUS_RS1: | |
1055 | seq_printf(m, "RS1\n"); | |
1056 | break; | |
1057 | case RSX_STATUS_RS2: | |
1058 | seq_printf(m, "RS2 (RC6)\n"); | |
1059 | break; | |
1060 | case RSX_STATUS_RS3: | |
1061 | seq_printf(m, "RC3 (RC6+)\n"); | |
1062 | break; | |
1063 | default: | |
1064 | seq_printf(m, "unknown\n"); | |
1065 | break; | |
1066 | } | |
f97108d1 JB |
1067 | |
1068 | return 0; | |
1069 | } | |
1070 | ||
4d85529d BW |
1071 | static int gen6_drpc_info(struct seq_file *m) |
1072 | { | |
1073 | ||
1074 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1075 | struct drm_device *dev = node->minor->dev; | |
1076 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1077 | u32 rpmodectl1, gt_core_status, rcctl1; | |
1078 | int count=0, ret; | |
1079 | ||
1080 | ||
1081 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1082 | if (ret) | |
1083 | return ret; | |
1084 | ||
1085 | if (atomic_read(&dev_priv->forcewake_count)) { | |
1086 | seq_printf(m, "RC information inaccurate because userspace " | |
1087 | "holds a reference \n"); | |
1088 | } else { | |
1089 | /* NB: we cannot use forcewake, else we read the wrong values */ | |
1090 | while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1)) | |
1091 | udelay(10); | |
1092 | seq_printf(m, "RC information accurate: %s\n", yesno(count < 51)); | |
1093 | } | |
1094 | ||
1095 | gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS); | |
1096 | trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4); | |
1097 | ||
1098 | rpmodectl1 = I915_READ(GEN6_RP_CONTROL); | |
1099 | rcctl1 = I915_READ(GEN6_RC_CONTROL); | |
1100 | mutex_unlock(&dev->struct_mutex); | |
1101 | ||
1102 | seq_printf(m, "Video Turbo Mode: %s\n", | |
1103 | yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO)); | |
1104 | seq_printf(m, "HW control enabled: %s\n", | |
1105 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); | |
1106 | seq_printf(m, "SW control enabled: %s\n", | |
1107 | yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) == | |
1108 | GEN6_RP_MEDIA_SW_MODE)); | |
1109 | seq_printf(m, "RC6 Enabled: %s\n", | |
1110 | yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE)); | |
1111 | seq_printf(m, "RC6 Enabled: %s\n", | |
1112 | yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE)); | |
1113 | seq_printf(m, "Deep RC6 Enabled: %s\n", | |
1114 | yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE)); | |
1115 | seq_printf(m, "Deepest RC6 Enabled: %s\n", | |
1116 | yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE)); | |
1117 | seq_printf(m, "Current RC state: "); | |
1118 | switch (gt_core_status & GEN6_RCn_MASK) { | |
1119 | case GEN6_RC0: | |
1120 | if (gt_core_status & GEN6_CORE_CPD_STATE_MASK) | |
1121 | seq_printf(m, "Core Power Down\n"); | |
1122 | else | |
1123 | seq_printf(m, "on\n"); | |
1124 | break; | |
1125 | case GEN6_RC3: | |
1126 | seq_printf(m, "RC3\n"); | |
1127 | break; | |
1128 | case GEN6_RC6: | |
1129 | seq_printf(m, "RC6\n"); | |
1130 | break; | |
1131 | case GEN6_RC7: | |
1132 | seq_printf(m, "RC7\n"); | |
1133 | break; | |
1134 | default: | |
1135 | seq_printf(m, "Unknown\n"); | |
1136 | break; | |
1137 | } | |
1138 | ||
1139 | seq_printf(m, "Core Power Down: %s\n", | |
1140 | yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK)); | |
1141 | return 0; | |
1142 | } | |
1143 | ||
1144 | static int i915_drpc_info(struct seq_file *m, void *unused) | |
1145 | { | |
1146 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1147 | struct drm_device *dev = node->minor->dev; | |
1148 | ||
1149 | if (IS_GEN6(dev) || IS_GEN7(dev)) | |
1150 | return gen6_drpc_info(m); | |
1151 | else | |
1152 | return ironlake_drpc_info(m); | |
1153 | } | |
1154 | ||
b5e50c3f JB |
1155 | static int i915_fbc_status(struct seq_file *m, void *unused) |
1156 | { | |
1157 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1158 | struct drm_device *dev = node->minor->dev; | |
b5e50c3f | 1159 | drm_i915_private_t *dev_priv = dev->dev_private; |
b5e50c3f | 1160 | |
ee5382ae | 1161 | if (!I915_HAS_FBC(dev)) { |
b5e50c3f JB |
1162 | seq_printf(m, "FBC unsupported on this chipset\n"); |
1163 | return 0; | |
1164 | } | |
1165 | ||
ee5382ae | 1166 | if (intel_fbc_enabled(dev)) { |
b5e50c3f JB |
1167 | seq_printf(m, "FBC enabled\n"); |
1168 | } else { | |
1169 | seq_printf(m, "FBC disabled: "); | |
1170 | switch (dev_priv->no_fbc_reason) { | |
bed4a673 CW |
1171 | case FBC_NO_OUTPUT: |
1172 | seq_printf(m, "no outputs"); | |
1173 | break; | |
b5e50c3f JB |
1174 | case FBC_STOLEN_TOO_SMALL: |
1175 | seq_printf(m, "not enough stolen memory"); | |
1176 | break; | |
1177 | case FBC_UNSUPPORTED_MODE: | |
1178 | seq_printf(m, "mode not supported"); | |
1179 | break; | |
1180 | case FBC_MODE_TOO_LARGE: | |
1181 | seq_printf(m, "mode too large"); | |
1182 | break; | |
1183 | case FBC_BAD_PLANE: | |
1184 | seq_printf(m, "FBC unsupported on plane"); | |
1185 | break; | |
1186 | case FBC_NOT_TILED: | |
1187 | seq_printf(m, "scanout buffer not tiled"); | |
1188 | break; | |
9c928d16 JB |
1189 | case FBC_MULTIPLE_PIPES: |
1190 | seq_printf(m, "multiple pipes are enabled"); | |
1191 | break; | |
c1a9f047 JB |
1192 | case FBC_MODULE_PARAM: |
1193 | seq_printf(m, "disabled per module param (default off)"); | |
1194 | break; | |
b5e50c3f JB |
1195 | default: |
1196 | seq_printf(m, "unknown reason"); | |
1197 | } | |
1198 | seq_printf(m, "\n"); | |
1199 | } | |
1200 | return 0; | |
1201 | } | |
1202 | ||
4a9bef37 JB |
1203 | static int i915_sr_status(struct seq_file *m, void *unused) |
1204 | { | |
1205 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1206 | struct drm_device *dev = node->minor->dev; | |
1207 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1208 | bool sr_enabled = false; | |
1209 | ||
1398261a | 1210 | if (HAS_PCH_SPLIT(dev)) |
5ba2aaaa | 1211 | sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN; |
a6c45cf0 | 1212 | else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev)) |
4a9bef37 JB |
1213 | sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN; |
1214 | else if (IS_I915GM(dev)) | |
1215 | sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN; | |
1216 | else if (IS_PINEVIEW(dev)) | |
1217 | sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN; | |
1218 | ||
5ba2aaaa CW |
1219 | seq_printf(m, "self-refresh: %s\n", |
1220 | sr_enabled ? "enabled" : "disabled"); | |
4a9bef37 JB |
1221 | |
1222 | return 0; | |
1223 | } | |
1224 | ||
7648fa99 JB |
1225 | static int i915_emon_status(struct seq_file *m, void *unused) |
1226 | { | |
1227 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1228 | struct drm_device *dev = node->minor->dev; | |
1229 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1230 | unsigned long temp, chipset, gfx; | |
de227ef0 CW |
1231 | int ret; |
1232 | ||
1233 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1234 | if (ret) | |
1235 | return ret; | |
7648fa99 JB |
1236 | |
1237 | temp = i915_mch_val(dev_priv); | |
1238 | chipset = i915_chipset_val(dev_priv); | |
1239 | gfx = i915_gfx_val(dev_priv); | |
de227ef0 | 1240 | mutex_unlock(&dev->struct_mutex); |
7648fa99 JB |
1241 | |
1242 | seq_printf(m, "GMCH temp: %ld\n", temp); | |
1243 | seq_printf(m, "Chipset power: %ld\n", chipset); | |
1244 | seq_printf(m, "GFX power: %ld\n", gfx); | |
1245 | seq_printf(m, "Total power: %ld\n", chipset + gfx); | |
1246 | ||
1247 | return 0; | |
1248 | } | |
1249 | ||
23b2f8bb JB |
1250 | static int i915_ring_freq_table(struct seq_file *m, void *unused) |
1251 | { | |
1252 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1253 | struct drm_device *dev = node->minor->dev; | |
1254 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1255 | int ret; | |
1256 | int gpu_freq, ia_freq; | |
1257 | ||
1c70c0ce | 1258 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) { |
23b2f8bb JB |
1259 | seq_printf(m, "unsupported on this chipset\n"); |
1260 | return 0; | |
1261 | } | |
1262 | ||
1263 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1264 | if (ret) | |
1265 | return ret; | |
1266 | ||
1267 | seq_printf(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\n"); | |
1268 | ||
1269 | for (gpu_freq = dev_priv->min_delay; gpu_freq <= dev_priv->max_delay; | |
1270 | gpu_freq++) { | |
1271 | I915_WRITE(GEN6_PCODE_DATA, gpu_freq); | |
1272 | I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | | |
1273 | GEN6_PCODE_READ_MIN_FREQ_TABLE); | |
1274 | if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & | |
1275 | GEN6_PCODE_READY) == 0, 10)) { | |
1276 | DRM_ERROR("pcode read of freq table timed out\n"); | |
1277 | continue; | |
1278 | } | |
1279 | ia_freq = I915_READ(GEN6_PCODE_DATA); | |
1280 | seq_printf(m, "%d\t\t%d\n", gpu_freq * 50, ia_freq * 100); | |
1281 | } | |
1282 | ||
1283 | mutex_unlock(&dev->struct_mutex); | |
1284 | ||
1285 | return 0; | |
1286 | } | |
1287 | ||
7648fa99 JB |
1288 | static int i915_gfxec(struct seq_file *m, void *unused) |
1289 | { | |
1290 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1291 | struct drm_device *dev = node->minor->dev; | |
1292 | drm_i915_private_t *dev_priv = dev->dev_private; | |
616fdb5a BW |
1293 | int ret; |
1294 | ||
1295 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1296 | if (ret) | |
1297 | return ret; | |
7648fa99 JB |
1298 | |
1299 | seq_printf(m, "GFXEC: %ld\n", (unsigned long)I915_READ(0x112f4)); | |
1300 | ||
616fdb5a BW |
1301 | mutex_unlock(&dev->struct_mutex); |
1302 | ||
7648fa99 JB |
1303 | return 0; |
1304 | } | |
1305 | ||
44834a67 CW |
1306 | static int i915_opregion(struct seq_file *m, void *unused) |
1307 | { | |
1308 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1309 | struct drm_device *dev = node->minor->dev; | |
1310 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1311 | struct intel_opregion *opregion = &dev_priv->opregion; | |
1312 | int ret; | |
1313 | ||
1314 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1315 | if (ret) | |
1316 | return ret; | |
1317 | ||
1318 | if (opregion->header) | |
1319 | seq_write(m, opregion->header, OPREGION_SIZE); | |
1320 | ||
1321 | mutex_unlock(&dev->struct_mutex); | |
1322 | ||
1323 | return 0; | |
1324 | } | |
1325 | ||
37811fcc CW |
1326 | static int i915_gem_framebuffer_info(struct seq_file *m, void *data) |
1327 | { | |
1328 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1329 | struct drm_device *dev = node->minor->dev; | |
1330 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1331 | struct intel_fbdev *ifbdev; | |
1332 | struct intel_framebuffer *fb; | |
1333 | int ret; | |
1334 | ||
1335 | ret = mutex_lock_interruptible(&dev->mode_config.mutex); | |
1336 | if (ret) | |
1337 | return ret; | |
1338 | ||
1339 | ifbdev = dev_priv->fbdev; | |
1340 | fb = to_intel_framebuffer(ifbdev->helper.fb); | |
1341 | ||
1342 | seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, obj ", | |
1343 | fb->base.width, | |
1344 | fb->base.height, | |
1345 | fb->base.depth, | |
1346 | fb->base.bits_per_pixel); | |
05394f39 | 1347 | describe_obj(m, fb->obj); |
37811fcc CW |
1348 | seq_printf(m, "\n"); |
1349 | ||
1350 | list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) { | |
1351 | if (&fb->base == ifbdev->helper.fb) | |
1352 | continue; | |
1353 | ||
1354 | seq_printf(m, "user size: %d x %d, depth %d, %d bpp, obj ", | |
1355 | fb->base.width, | |
1356 | fb->base.height, | |
1357 | fb->base.depth, | |
1358 | fb->base.bits_per_pixel); | |
05394f39 | 1359 | describe_obj(m, fb->obj); |
37811fcc CW |
1360 | seq_printf(m, "\n"); |
1361 | } | |
1362 | ||
1363 | mutex_unlock(&dev->mode_config.mutex); | |
1364 | ||
1365 | return 0; | |
1366 | } | |
1367 | ||
e76d3630 BW |
1368 | static int i915_context_status(struct seq_file *m, void *unused) |
1369 | { | |
1370 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1371 | struct drm_device *dev = node->minor->dev; | |
1372 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1373 | int ret; | |
1374 | ||
1375 | ret = mutex_lock_interruptible(&dev->mode_config.mutex); | |
1376 | if (ret) | |
1377 | return ret; | |
1378 | ||
dc501fbc BW |
1379 | if (dev_priv->pwrctx) { |
1380 | seq_printf(m, "power context "); | |
1381 | describe_obj(m, dev_priv->pwrctx); | |
1382 | seq_printf(m, "\n"); | |
1383 | } | |
e76d3630 | 1384 | |
dc501fbc BW |
1385 | if (dev_priv->renderctx) { |
1386 | seq_printf(m, "render context "); | |
1387 | describe_obj(m, dev_priv->renderctx); | |
1388 | seq_printf(m, "\n"); | |
1389 | } | |
e76d3630 BW |
1390 | |
1391 | mutex_unlock(&dev->mode_config.mutex); | |
1392 | ||
1393 | return 0; | |
1394 | } | |
1395 | ||
6d794d42 BW |
1396 | static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data) |
1397 | { | |
1398 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1399 | struct drm_device *dev = node->minor->dev; | |
1400 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9f1f46a4 | 1401 | unsigned forcewake_count; |
6d794d42 | 1402 | |
9f1f46a4 DV |
1403 | spin_lock_irq(&dev_priv->gt_lock); |
1404 | forcewake_count = dev_priv->forcewake_count; | |
1405 | spin_unlock_irq(&dev_priv->gt_lock); | |
1406 | ||
1407 | seq_printf(m, "forcewake count = %u\n", forcewake_count); | |
6d794d42 BW |
1408 | |
1409 | return 0; | |
1410 | } | |
1411 | ||
f3cd474b CW |
1412 | static int |
1413 | i915_wedged_open(struct inode *inode, | |
1414 | struct file *filp) | |
1415 | { | |
1416 | filp->private_data = inode->i_private; | |
1417 | return 0; | |
1418 | } | |
1419 | ||
1420 | static ssize_t | |
1421 | i915_wedged_read(struct file *filp, | |
1422 | char __user *ubuf, | |
1423 | size_t max, | |
1424 | loff_t *ppos) | |
1425 | { | |
1426 | struct drm_device *dev = filp->private_data; | |
1427 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1428 | char buf[80]; | |
1429 | int len; | |
1430 | ||
0206e353 | 1431 | len = snprintf(buf, sizeof(buf), |
f3cd474b CW |
1432 | "wedged : %d\n", |
1433 | atomic_read(&dev_priv->mm.wedged)); | |
1434 | ||
0206e353 AJ |
1435 | if (len > sizeof(buf)) |
1436 | len = sizeof(buf); | |
f4433a8d | 1437 | |
f3cd474b CW |
1438 | return simple_read_from_buffer(ubuf, max, ppos, buf, len); |
1439 | } | |
1440 | ||
1441 | static ssize_t | |
1442 | i915_wedged_write(struct file *filp, | |
1443 | const char __user *ubuf, | |
1444 | size_t cnt, | |
1445 | loff_t *ppos) | |
1446 | { | |
1447 | struct drm_device *dev = filp->private_data; | |
f3cd474b CW |
1448 | char buf[20]; |
1449 | int val = 1; | |
1450 | ||
1451 | if (cnt > 0) { | |
0206e353 | 1452 | if (cnt > sizeof(buf) - 1) |
f3cd474b CW |
1453 | return -EINVAL; |
1454 | ||
1455 | if (copy_from_user(buf, ubuf, cnt)) | |
1456 | return -EFAULT; | |
1457 | buf[cnt] = 0; | |
1458 | ||
1459 | val = simple_strtoul(buf, NULL, 0); | |
1460 | } | |
1461 | ||
1462 | DRM_INFO("Manually setting wedged to %d\n", val); | |
527f9e90 | 1463 | i915_handle_error(dev, val); |
f3cd474b CW |
1464 | |
1465 | return cnt; | |
1466 | } | |
1467 | ||
1468 | static const struct file_operations i915_wedged_fops = { | |
1469 | .owner = THIS_MODULE, | |
1470 | .open = i915_wedged_open, | |
1471 | .read = i915_wedged_read, | |
1472 | .write = i915_wedged_write, | |
6038f373 | 1473 | .llseek = default_llseek, |
f3cd474b CW |
1474 | }; |
1475 | ||
358733e9 JB |
1476 | static int |
1477 | i915_max_freq_open(struct inode *inode, | |
1478 | struct file *filp) | |
1479 | { | |
1480 | filp->private_data = inode->i_private; | |
1481 | return 0; | |
1482 | } | |
1483 | ||
1484 | static ssize_t | |
1485 | i915_max_freq_read(struct file *filp, | |
1486 | char __user *ubuf, | |
1487 | size_t max, | |
1488 | loff_t *ppos) | |
1489 | { | |
1490 | struct drm_device *dev = filp->private_data; | |
1491 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1492 | char buf[80]; | |
1493 | int len; | |
1494 | ||
0206e353 | 1495 | len = snprintf(buf, sizeof(buf), |
358733e9 JB |
1496 | "max freq: %d\n", dev_priv->max_delay * 50); |
1497 | ||
0206e353 AJ |
1498 | if (len > sizeof(buf)) |
1499 | len = sizeof(buf); | |
358733e9 JB |
1500 | |
1501 | return simple_read_from_buffer(ubuf, max, ppos, buf, len); | |
1502 | } | |
1503 | ||
1504 | static ssize_t | |
1505 | i915_max_freq_write(struct file *filp, | |
1506 | const char __user *ubuf, | |
1507 | size_t cnt, | |
1508 | loff_t *ppos) | |
1509 | { | |
1510 | struct drm_device *dev = filp->private_data; | |
1511 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1512 | char buf[20]; | |
1513 | int val = 1; | |
1514 | ||
1515 | if (cnt > 0) { | |
0206e353 | 1516 | if (cnt > sizeof(buf) - 1) |
358733e9 JB |
1517 | return -EINVAL; |
1518 | ||
1519 | if (copy_from_user(buf, ubuf, cnt)) | |
1520 | return -EFAULT; | |
1521 | buf[cnt] = 0; | |
1522 | ||
1523 | val = simple_strtoul(buf, NULL, 0); | |
1524 | } | |
1525 | ||
1526 | DRM_DEBUG_DRIVER("Manually setting max freq to %d\n", val); | |
1527 | ||
1528 | /* | |
1529 | * Turbo will still be enabled, but won't go above the set value. | |
1530 | */ | |
1531 | dev_priv->max_delay = val / 50; | |
1532 | ||
1533 | gen6_set_rps(dev, val / 50); | |
1534 | ||
1535 | return cnt; | |
1536 | } | |
1537 | ||
1538 | static const struct file_operations i915_max_freq_fops = { | |
1539 | .owner = THIS_MODULE, | |
1540 | .open = i915_max_freq_open, | |
1541 | .read = i915_max_freq_read, | |
1542 | .write = i915_max_freq_write, | |
1543 | .llseek = default_llseek, | |
1544 | }; | |
1545 | ||
07b7ddd9 JB |
1546 | static int |
1547 | i915_cache_sharing_open(struct inode *inode, | |
1548 | struct file *filp) | |
1549 | { | |
1550 | filp->private_data = inode->i_private; | |
1551 | return 0; | |
1552 | } | |
1553 | ||
1554 | static ssize_t | |
1555 | i915_cache_sharing_read(struct file *filp, | |
1556 | char __user *ubuf, | |
1557 | size_t max, | |
1558 | loff_t *ppos) | |
1559 | { | |
1560 | struct drm_device *dev = filp->private_data; | |
1561 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1562 | char buf[80]; | |
1563 | u32 snpcr; | |
1564 | int len; | |
1565 | ||
1566 | mutex_lock(&dev_priv->dev->struct_mutex); | |
1567 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); | |
1568 | mutex_unlock(&dev_priv->dev->struct_mutex); | |
1569 | ||
0206e353 | 1570 | len = snprintf(buf, sizeof(buf), |
07b7ddd9 JB |
1571 | "%d\n", (snpcr & GEN6_MBC_SNPCR_MASK) >> |
1572 | GEN6_MBC_SNPCR_SHIFT); | |
1573 | ||
0206e353 AJ |
1574 | if (len > sizeof(buf)) |
1575 | len = sizeof(buf); | |
07b7ddd9 JB |
1576 | |
1577 | return simple_read_from_buffer(ubuf, max, ppos, buf, len); | |
1578 | } | |
1579 | ||
1580 | static ssize_t | |
1581 | i915_cache_sharing_write(struct file *filp, | |
1582 | const char __user *ubuf, | |
1583 | size_t cnt, | |
1584 | loff_t *ppos) | |
1585 | { | |
1586 | struct drm_device *dev = filp->private_data; | |
1587 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1588 | char buf[20]; | |
1589 | u32 snpcr; | |
1590 | int val = 1; | |
1591 | ||
1592 | if (cnt > 0) { | |
0206e353 | 1593 | if (cnt > sizeof(buf) - 1) |
07b7ddd9 JB |
1594 | return -EINVAL; |
1595 | ||
1596 | if (copy_from_user(buf, ubuf, cnt)) | |
1597 | return -EFAULT; | |
1598 | buf[cnt] = 0; | |
1599 | ||
1600 | val = simple_strtoul(buf, NULL, 0); | |
1601 | } | |
1602 | ||
1603 | if (val < 0 || val > 3) | |
1604 | return -EINVAL; | |
1605 | ||
1606 | DRM_DEBUG_DRIVER("Manually setting uncore sharing to %d\n", val); | |
1607 | ||
1608 | /* Update the cache sharing policy here as well */ | |
1609 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); | |
1610 | snpcr &= ~GEN6_MBC_SNPCR_MASK; | |
1611 | snpcr |= (val << GEN6_MBC_SNPCR_SHIFT); | |
1612 | I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); | |
1613 | ||
1614 | return cnt; | |
1615 | } | |
1616 | ||
1617 | static const struct file_operations i915_cache_sharing_fops = { | |
1618 | .owner = THIS_MODULE, | |
1619 | .open = i915_cache_sharing_open, | |
1620 | .read = i915_cache_sharing_read, | |
1621 | .write = i915_cache_sharing_write, | |
1622 | .llseek = default_llseek, | |
1623 | }; | |
1624 | ||
f3cd474b CW |
1625 | /* As the drm_debugfs_init() routines are called before dev->dev_private is |
1626 | * allocated we need to hook into the minor for release. */ | |
1627 | static int | |
1628 | drm_add_fake_info_node(struct drm_minor *minor, | |
1629 | struct dentry *ent, | |
1630 | const void *key) | |
1631 | { | |
1632 | struct drm_info_node *node; | |
1633 | ||
1634 | node = kmalloc(sizeof(struct drm_info_node), GFP_KERNEL); | |
1635 | if (node == NULL) { | |
1636 | debugfs_remove(ent); | |
1637 | return -ENOMEM; | |
1638 | } | |
1639 | ||
1640 | node->minor = minor; | |
1641 | node->dent = ent; | |
1642 | node->info_ent = (void *) key; | |
b3e067c0 MS |
1643 | |
1644 | mutex_lock(&minor->debugfs_lock); | |
1645 | list_add(&node->list, &minor->debugfs_list); | |
1646 | mutex_unlock(&minor->debugfs_lock); | |
f3cd474b CW |
1647 | |
1648 | return 0; | |
1649 | } | |
1650 | ||
1651 | static int i915_wedged_create(struct dentry *root, struct drm_minor *minor) | |
1652 | { | |
1653 | struct drm_device *dev = minor->dev; | |
1654 | struct dentry *ent; | |
1655 | ||
1656 | ent = debugfs_create_file("i915_wedged", | |
1657 | S_IRUGO | S_IWUSR, | |
1658 | root, dev, | |
1659 | &i915_wedged_fops); | |
1660 | if (IS_ERR(ent)) | |
1661 | return PTR_ERR(ent); | |
1662 | ||
1663 | return drm_add_fake_info_node(minor, ent, &i915_wedged_fops); | |
1664 | } | |
9e3a6d15 | 1665 | |
6d794d42 BW |
1666 | static int i915_forcewake_open(struct inode *inode, struct file *file) |
1667 | { | |
1668 | struct drm_device *dev = inode->i_private; | |
1669 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1670 | int ret; | |
1671 | ||
1672 | if (!IS_GEN6(dev)) | |
1673 | return 0; | |
1674 | ||
1675 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1676 | if (ret) | |
1677 | return ret; | |
1678 | gen6_gt_force_wake_get(dev_priv); | |
1679 | mutex_unlock(&dev->struct_mutex); | |
1680 | ||
1681 | return 0; | |
1682 | } | |
1683 | ||
1684 | int i915_forcewake_release(struct inode *inode, struct file *file) | |
1685 | { | |
1686 | struct drm_device *dev = inode->i_private; | |
1687 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1688 | ||
1689 | if (!IS_GEN6(dev)) | |
1690 | return 0; | |
1691 | ||
1692 | /* | |
1693 | * It's bad that we can potentially hang userspace if struct_mutex gets | |
1694 | * forever stuck. However, if we cannot acquire this lock it means that | |
1695 | * almost certainly the driver has hung, is not unload-able. Therefore | |
1696 | * hanging here is probably a minor inconvenience not to be seen my | |
1697 | * almost every user. | |
1698 | */ | |
1699 | mutex_lock(&dev->struct_mutex); | |
1700 | gen6_gt_force_wake_put(dev_priv); | |
1701 | mutex_unlock(&dev->struct_mutex); | |
1702 | ||
1703 | return 0; | |
1704 | } | |
1705 | ||
1706 | static const struct file_operations i915_forcewake_fops = { | |
1707 | .owner = THIS_MODULE, | |
1708 | .open = i915_forcewake_open, | |
1709 | .release = i915_forcewake_release, | |
1710 | }; | |
1711 | ||
1712 | static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor) | |
1713 | { | |
1714 | struct drm_device *dev = minor->dev; | |
1715 | struct dentry *ent; | |
1716 | ||
1717 | ent = debugfs_create_file("i915_forcewake_user", | |
8eb57294 | 1718 | S_IRUSR, |
6d794d42 BW |
1719 | root, dev, |
1720 | &i915_forcewake_fops); | |
1721 | if (IS_ERR(ent)) | |
1722 | return PTR_ERR(ent); | |
1723 | ||
8eb57294 | 1724 | return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops); |
6d794d42 BW |
1725 | } |
1726 | ||
358733e9 JB |
1727 | static int i915_max_freq_create(struct dentry *root, struct drm_minor *minor) |
1728 | { | |
1729 | struct drm_device *dev = minor->dev; | |
1730 | struct dentry *ent; | |
1731 | ||
1732 | ent = debugfs_create_file("i915_max_freq", | |
1733 | S_IRUGO | S_IWUSR, | |
1734 | root, dev, | |
1735 | &i915_max_freq_fops); | |
1736 | if (IS_ERR(ent)) | |
1737 | return PTR_ERR(ent); | |
1738 | ||
1739 | return drm_add_fake_info_node(minor, ent, &i915_max_freq_fops); | |
1740 | } | |
1741 | ||
07b7ddd9 JB |
1742 | static int i915_cache_sharing_create(struct dentry *root, struct drm_minor *minor) |
1743 | { | |
1744 | struct drm_device *dev = minor->dev; | |
1745 | struct dentry *ent; | |
1746 | ||
1747 | ent = debugfs_create_file("i915_cache_sharing", | |
1748 | S_IRUGO | S_IWUSR, | |
1749 | root, dev, | |
1750 | &i915_cache_sharing_fops); | |
1751 | if (IS_ERR(ent)) | |
1752 | return PTR_ERR(ent); | |
1753 | ||
1754 | return drm_add_fake_info_node(minor, ent, &i915_cache_sharing_fops); | |
1755 | } | |
1756 | ||
27c202ad | 1757 | static struct drm_info_list i915_debugfs_list[] = { |
311bd68e | 1758 | {"i915_capabilities", i915_capabilities, 0}, |
73aa808f | 1759 | {"i915_gem_objects", i915_gem_object_info, 0}, |
08c18323 | 1760 | {"i915_gem_gtt", i915_gem_gtt_info, 0}, |
433e12f7 BG |
1761 | {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST}, |
1762 | {"i915_gem_flushing", i915_gem_object_list_info, 0, (void *) FLUSHING_LIST}, | |
1763 | {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST}, | |
f13d3f73 | 1764 | {"i915_gem_pinned", i915_gem_object_list_info, 0, (void *) PINNED_LIST}, |
d21d5975 | 1765 | {"i915_gem_deferred_free", i915_gem_object_list_info, 0, (void *) DEFERRED_FREE_LIST}, |
4e5359cd | 1766 | {"i915_gem_pageflip", i915_gem_pageflip_info, 0}, |
2017263e BG |
1767 | {"i915_gem_request", i915_gem_request_info, 0}, |
1768 | {"i915_gem_seqno", i915_gem_seqno_info, 0}, | |
a6172a80 | 1769 | {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0}, |
2017263e | 1770 | {"i915_gem_interrupt", i915_interrupt_info, 0}, |
1ec14ad3 CW |
1771 | {"i915_gem_hws", i915_hws_info, 0, (void *)RCS}, |
1772 | {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS}, | |
1773 | {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS}, | |
1774 | {"i915_ringbuffer_data", i915_ringbuffer_data, 0, (void *)RCS}, | |
1775 | {"i915_ringbuffer_info", i915_ringbuffer_info, 0, (void *)RCS}, | |
1776 | {"i915_bsd_ringbuffer_data", i915_ringbuffer_data, 0, (void *)VCS}, | |
1777 | {"i915_bsd_ringbuffer_info", i915_ringbuffer_info, 0, (void *)VCS}, | |
1778 | {"i915_blt_ringbuffer_data", i915_ringbuffer_data, 0, (void *)BCS}, | |
1779 | {"i915_blt_ringbuffer_info", i915_ringbuffer_info, 0, (void *)BCS}, | |
6911a9b8 | 1780 | {"i915_batchbuffers", i915_batchbuffer_info, 0}, |
63eeaf38 | 1781 | {"i915_error_state", i915_error_state, 0}, |
f97108d1 JB |
1782 | {"i915_rstdby_delays", i915_rstdby_delays, 0}, |
1783 | {"i915_cur_delayinfo", i915_cur_delayinfo, 0}, | |
1784 | {"i915_delayfreq_table", i915_delayfreq_table, 0}, | |
1785 | {"i915_inttoext_table", i915_inttoext_table, 0}, | |
1786 | {"i915_drpc_info", i915_drpc_info, 0}, | |
7648fa99 | 1787 | {"i915_emon_status", i915_emon_status, 0}, |
23b2f8bb | 1788 | {"i915_ring_freq_table", i915_ring_freq_table, 0}, |
7648fa99 | 1789 | {"i915_gfxec", i915_gfxec, 0}, |
b5e50c3f | 1790 | {"i915_fbc_status", i915_fbc_status, 0}, |
4a9bef37 | 1791 | {"i915_sr_status", i915_sr_status, 0}, |
44834a67 | 1792 | {"i915_opregion", i915_opregion, 0}, |
37811fcc | 1793 | {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0}, |
e76d3630 | 1794 | {"i915_context_status", i915_context_status, 0}, |
6d794d42 | 1795 | {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0}, |
2017263e | 1796 | }; |
27c202ad | 1797 | #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list) |
2017263e | 1798 | |
27c202ad | 1799 | int i915_debugfs_init(struct drm_minor *minor) |
2017263e | 1800 | { |
f3cd474b CW |
1801 | int ret; |
1802 | ||
1803 | ret = i915_wedged_create(minor->debugfs_root, minor); | |
1804 | if (ret) | |
1805 | return ret; | |
1806 | ||
6d794d42 | 1807 | ret = i915_forcewake_create(minor->debugfs_root, minor); |
358733e9 JB |
1808 | if (ret) |
1809 | return ret; | |
1810 | ret = i915_max_freq_create(minor->debugfs_root, minor); | |
07b7ddd9 JB |
1811 | if (ret) |
1812 | return ret; | |
1813 | ret = i915_cache_sharing_create(minor->debugfs_root, minor); | |
6d794d42 BW |
1814 | if (ret) |
1815 | return ret; | |
1816 | ||
27c202ad BG |
1817 | return drm_debugfs_create_files(i915_debugfs_list, |
1818 | I915_DEBUGFS_ENTRIES, | |
2017263e BG |
1819 | minor->debugfs_root, minor); |
1820 | } | |
1821 | ||
27c202ad | 1822 | void i915_debugfs_cleanup(struct drm_minor *minor) |
2017263e | 1823 | { |
27c202ad BG |
1824 | drm_debugfs_remove_files(i915_debugfs_list, |
1825 | I915_DEBUGFS_ENTRIES, minor); | |
6d794d42 BW |
1826 | drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops, |
1827 | 1, minor); | |
33db679b KH |
1828 | drm_debugfs_remove_files((struct drm_info_list *) &i915_wedged_fops, |
1829 | 1, minor); | |
358733e9 JB |
1830 | drm_debugfs_remove_files((struct drm_info_list *) &i915_max_freq_fops, |
1831 | 1, minor); | |
07b7ddd9 JB |
1832 | drm_debugfs_remove_files((struct drm_info_list *) &i915_cache_sharing_fops, |
1833 | 1, minor); | |
2017263e BG |
1834 | } |
1835 | ||
1836 | #endif /* CONFIG_DEBUG_FS */ |