Commit | Line | Data |
---|---|---|
2017263e BG |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Keith Packard <keithp@keithp.com> | |
26 | * | |
27 | */ | |
28 | ||
29 | #include <linux/seq_file.h> | |
926321d5 | 30 | #include <linux/ctype.h> |
f3cd474b | 31 | #include <linux/debugfs.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
2d1a8a48 | 33 | #include <linux/export.h> |
6d2b8885 | 34 | #include <linux/list_sort.h> |
ec013e7f | 35 | #include <asm/msr-index.h> |
760285e7 | 36 | #include <drm/drmP.h> |
4e5359cd | 37 | #include "intel_drv.h" |
e5c65260 | 38 | #include "intel_ringbuffer.h" |
760285e7 | 39 | #include <drm/i915_drm.h> |
2017263e BG |
40 | #include "i915_drv.h" |
41 | ||
2017263e BG |
42 | #if defined(CONFIG_DEBUG_FS) |
43 | ||
f13d3f73 | 44 | enum { |
69dc4987 | 45 | ACTIVE_LIST, |
f13d3f73 | 46 | INACTIVE_LIST, |
d21d5975 | 47 | PINNED_LIST, |
f13d3f73 | 48 | }; |
2017263e | 49 | |
70d39fe4 CW |
50 | static const char *yesno(int v) |
51 | { | |
52 | return v ? "yes" : "no"; | |
53 | } | |
54 | ||
55 | static int i915_capabilities(struct seq_file *m, void *data) | |
56 | { | |
57 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
58 | struct drm_device *dev = node->minor->dev; | |
59 | const struct intel_device_info *info = INTEL_INFO(dev); | |
60 | ||
61 | seq_printf(m, "gen: %d\n", info->gen); | |
03d00ac5 | 62 | seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev)); |
79fc46df DL |
63 | #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x)) |
64 | #define SEP_SEMICOLON ; | |
65 | DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON); | |
66 | #undef PRINT_FLAG | |
67 | #undef SEP_SEMICOLON | |
70d39fe4 CW |
68 | |
69 | return 0; | |
70 | } | |
2017263e | 71 | |
05394f39 | 72 | static const char *get_pin_flag(struct drm_i915_gem_object *obj) |
a6172a80 | 73 | { |
05394f39 | 74 | if (obj->user_pin_count > 0) |
a6172a80 | 75 | return "P"; |
05394f39 | 76 | else if (obj->pin_count > 0) |
a6172a80 CW |
77 | return "p"; |
78 | else | |
79 | return " "; | |
80 | } | |
81 | ||
05394f39 | 82 | static const char *get_tiling_flag(struct drm_i915_gem_object *obj) |
a6172a80 | 83 | { |
0206e353 AJ |
84 | switch (obj->tiling_mode) { |
85 | default: | |
86 | case I915_TILING_NONE: return " "; | |
87 | case I915_TILING_X: return "X"; | |
88 | case I915_TILING_Y: return "Y"; | |
89 | } | |
a6172a80 CW |
90 | } |
91 | ||
1d693bcc BW |
92 | static inline const char *get_global_flag(struct drm_i915_gem_object *obj) |
93 | { | |
94 | return obj->has_global_gtt_mapping ? "g" : " "; | |
95 | } | |
96 | ||
37811fcc CW |
97 | static void |
98 | describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj) | |
99 | { | |
1d693bcc | 100 | struct i915_vma *vma; |
fb1ae911 | 101 | seq_printf(m, "%pK: %s%s%s %8zdKiB %02x %02x %u %u %u%s%s%s", |
37811fcc CW |
102 | &obj->base, |
103 | get_pin_flag(obj), | |
104 | get_tiling_flag(obj), | |
1d693bcc | 105 | get_global_flag(obj), |
a05a5862 | 106 | obj->base.size / 1024, |
37811fcc CW |
107 | obj->base.read_domains, |
108 | obj->base.write_domain, | |
0201f1ec CW |
109 | obj->last_read_seqno, |
110 | obj->last_write_seqno, | |
caea7476 | 111 | obj->last_fenced_seqno, |
84734a04 | 112 | i915_cache_level_str(obj->cache_level), |
37811fcc CW |
113 | obj->dirty ? " dirty" : "", |
114 | obj->madv == I915_MADV_DONTNEED ? " purgeable" : ""); | |
115 | if (obj->base.name) | |
116 | seq_printf(m, " (name: %d)", obj->base.name); | |
c110a6d7 CW |
117 | if (obj->pin_count) |
118 | seq_printf(m, " (pinned x %d)", obj->pin_count); | |
cc98b413 CW |
119 | if (obj->pin_display) |
120 | seq_printf(m, " (display)"); | |
37811fcc CW |
121 | if (obj->fence_reg != I915_FENCE_REG_NONE) |
122 | seq_printf(m, " (fence: %d)", obj->fence_reg); | |
1d693bcc BW |
123 | list_for_each_entry(vma, &obj->vma_list, vma_link) { |
124 | if (!i915_is_ggtt(vma->vm)) | |
125 | seq_puts(m, " (pp"); | |
126 | else | |
127 | seq_puts(m, " (g"); | |
128 | seq_printf(m, "gtt offset: %08lx, size: %08lx)", | |
129 | vma->node.start, vma->node.size); | |
130 | } | |
c1ad11fc CW |
131 | if (obj->stolen) |
132 | seq_printf(m, " (stolen: %08lx)", obj->stolen->start); | |
6299f992 CW |
133 | if (obj->pin_mappable || obj->fault_mappable) { |
134 | char s[3], *t = s; | |
135 | if (obj->pin_mappable) | |
136 | *t++ = 'p'; | |
137 | if (obj->fault_mappable) | |
138 | *t++ = 'f'; | |
139 | *t = '\0'; | |
140 | seq_printf(m, " (%s mappable)", s); | |
141 | } | |
69dc4987 CW |
142 | if (obj->ring != NULL) |
143 | seq_printf(m, " (%s)", obj->ring->name); | |
37811fcc CW |
144 | } |
145 | ||
3ccfd19d BW |
146 | static void describe_ctx(struct seq_file *m, struct i915_hw_context *ctx) |
147 | { | |
148 | seq_putc(m, ctx->is_initialized ? 'I' : 'i'); | |
149 | seq_putc(m, ctx->remap_slice ? 'R' : 'r'); | |
150 | seq_putc(m, ' '); | |
151 | } | |
152 | ||
433e12f7 | 153 | static int i915_gem_object_list_info(struct seq_file *m, void *data) |
2017263e BG |
154 | { |
155 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
433e12f7 BG |
156 | uintptr_t list = (uintptr_t) node->info_ent->data; |
157 | struct list_head *head; | |
2017263e | 158 | struct drm_device *dev = node->minor->dev; |
5cef07e1 BW |
159 | struct drm_i915_private *dev_priv = dev->dev_private; |
160 | struct i915_address_space *vm = &dev_priv->gtt.base; | |
ca191b13 | 161 | struct i915_vma *vma; |
8f2480fb CW |
162 | size_t total_obj_size, total_gtt_size; |
163 | int count, ret; | |
de227ef0 CW |
164 | |
165 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
166 | if (ret) | |
167 | return ret; | |
2017263e | 168 | |
ca191b13 | 169 | /* FIXME: the user of this interface might want more than just GGTT */ |
433e12f7 BG |
170 | switch (list) { |
171 | case ACTIVE_LIST: | |
267f0c90 | 172 | seq_puts(m, "Active:\n"); |
5cef07e1 | 173 | head = &vm->active_list; |
433e12f7 BG |
174 | break; |
175 | case INACTIVE_LIST: | |
267f0c90 | 176 | seq_puts(m, "Inactive:\n"); |
5cef07e1 | 177 | head = &vm->inactive_list; |
433e12f7 | 178 | break; |
433e12f7 | 179 | default: |
de227ef0 CW |
180 | mutex_unlock(&dev->struct_mutex); |
181 | return -EINVAL; | |
2017263e | 182 | } |
2017263e | 183 | |
8f2480fb | 184 | total_obj_size = total_gtt_size = count = 0; |
ca191b13 BW |
185 | list_for_each_entry(vma, head, mm_list) { |
186 | seq_printf(m, " "); | |
187 | describe_obj(m, vma->obj); | |
188 | seq_printf(m, "\n"); | |
189 | total_obj_size += vma->obj->base.size; | |
190 | total_gtt_size += vma->node.size; | |
8f2480fb | 191 | count++; |
2017263e | 192 | } |
de227ef0 | 193 | mutex_unlock(&dev->struct_mutex); |
5e118f41 | 194 | |
8f2480fb CW |
195 | seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n", |
196 | count, total_obj_size, total_gtt_size); | |
2017263e BG |
197 | return 0; |
198 | } | |
199 | ||
6d2b8885 CW |
200 | static int obj_rank_by_stolen(void *priv, |
201 | struct list_head *A, struct list_head *B) | |
202 | { | |
203 | struct drm_i915_gem_object *a = | |
b25cb2f8 | 204 | container_of(A, struct drm_i915_gem_object, obj_exec_link); |
6d2b8885 | 205 | struct drm_i915_gem_object *b = |
b25cb2f8 | 206 | container_of(B, struct drm_i915_gem_object, obj_exec_link); |
6d2b8885 CW |
207 | |
208 | return a->stolen->start - b->stolen->start; | |
209 | } | |
210 | ||
211 | static int i915_gem_stolen_list_info(struct seq_file *m, void *data) | |
212 | { | |
213 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
214 | struct drm_device *dev = node->minor->dev; | |
215 | struct drm_i915_private *dev_priv = dev->dev_private; | |
216 | struct drm_i915_gem_object *obj; | |
217 | size_t total_obj_size, total_gtt_size; | |
218 | LIST_HEAD(stolen); | |
219 | int count, ret; | |
220 | ||
221 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
222 | if (ret) | |
223 | return ret; | |
224 | ||
225 | total_obj_size = total_gtt_size = count = 0; | |
226 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { | |
227 | if (obj->stolen == NULL) | |
228 | continue; | |
229 | ||
b25cb2f8 | 230 | list_add(&obj->obj_exec_link, &stolen); |
6d2b8885 CW |
231 | |
232 | total_obj_size += obj->base.size; | |
233 | total_gtt_size += i915_gem_obj_ggtt_size(obj); | |
234 | count++; | |
235 | } | |
236 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) { | |
237 | if (obj->stolen == NULL) | |
238 | continue; | |
239 | ||
b25cb2f8 | 240 | list_add(&obj->obj_exec_link, &stolen); |
6d2b8885 CW |
241 | |
242 | total_obj_size += obj->base.size; | |
243 | count++; | |
244 | } | |
245 | list_sort(NULL, &stolen, obj_rank_by_stolen); | |
246 | seq_puts(m, "Stolen:\n"); | |
247 | while (!list_empty(&stolen)) { | |
b25cb2f8 | 248 | obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link); |
6d2b8885 CW |
249 | seq_puts(m, " "); |
250 | describe_obj(m, obj); | |
251 | seq_putc(m, '\n'); | |
b25cb2f8 | 252 | list_del_init(&obj->obj_exec_link); |
6d2b8885 CW |
253 | } |
254 | mutex_unlock(&dev->struct_mutex); | |
255 | ||
256 | seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n", | |
257 | count, total_obj_size, total_gtt_size); | |
258 | return 0; | |
259 | } | |
260 | ||
6299f992 CW |
261 | #define count_objects(list, member) do { \ |
262 | list_for_each_entry(obj, list, member) { \ | |
f343c5f6 | 263 | size += i915_gem_obj_ggtt_size(obj); \ |
6299f992 CW |
264 | ++count; \ |
265 | if (obj->map_and_fenceable) { \ | |
f343c5f6 | 266 | mappable_size += i915_gem_obj_ggtt_size(obj); \ |
6299f992 CW |
267 | ++mappable_count; \ |
268 | } \ | |
269 | } \ | |
0206e353 | 270 | } while (0) |
6299f992 | 271 | |
2db8e9d6 CW |
272 | struct file_stats { |
273 | int count; | |
274 | size_t total, active, inactive, unbound; | |
275 | }; | |
276 | ||
277 | static int per_file_stats(int id, void *ptr, void *data) | |
278 | { | |
279 | struct drm_i915_gem_object *obj = ptr; | |
280 | struct file_stats *stats = data; | |
281 | ||
282 | stats->count++; | |
283 | stats->total += obj->base.size; | |
284 | ||
f343c5f6 | 285 | if (i915_gem_obj_ggtt_bound(obj)) { |
2db8e9d6 CW |
286 | if (!list_empty(&obj->ring_list)) |
287 | stats->active += obj->base.size; | |
288 | else | |
289 | stats->inactive += obj->base.size; | |
290 | } else { | |
291 | if (!list_empty(&obj->global_list)) | |
292 | stats->unbound += obj->base.size; | |
293 | } | |
294 | ||
295 | return 0; | |
296 | } | |
297 | ||
ca191b13 BW |
298 | #define count_vmas(list, member) do { \ |
299 | list_for_each_entry(vma, list, member) { \ | |
300 | size += i915_gem_obj_ggtt_size(vma->obj); \ | |
301 | ++count; \ | |
302 | if (vma->obj->map_and_fenceable) { \ | |
303 | mappable_size += i915_gem_obj_ggtt_size(vma->obj); \ | |
304 | ++mappable_count; \ | |
305 | } \ | |
306 | } \ | |
307 | } while (0) | |
308 | ||
309 | static int i915_gem_object_info(struct seq_file *m, void* data) | |
73aa808f CW |
310 | { |
311 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
312 | struct drm_device *dev = node->minor->dev; | |
313 | struct drm_i915_private *dev_priv = dev->dev_private; | |
b7abb714 CW |
314 | u32 count, mappable_count, purgeable_count; |
315 | size_t size, mappable_size, purgeable_size; | |
6299f992 | 316 | struct drm_i915_gem_object *obj; |
5cef07e1 | 317 | struct i915_address_space *vm = &dev_priv->gtt.base; |
2db8e9d6 | 318 | struct drm_file *file; |
ca191b13 | 319 | struct i915_vma *vma; |
73aa808f CW |
320 | int ret; |
321 | ||
322 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
323 | if (ret) | |
324 | return ret; | |
325 | ||
6299f992 CW |
326 | seq_printf(m, "%u objects, %zu bytes\n", |
327 | dev_priv->mm.object_count, | |
328 | dev_priv->mm.object_memory); | |
329 | ||
330 | size = count = mappable_size = mappable_count = 0; | |
35c20a60 | 331 | count_objects(&dev_priv->mm.bound_list, global_list); |
6299f992 CW |
332 | seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n", |
333 | count, mappable_count, size, mappable_size); | |
334 | ||
335 | size = count = mappable_size = mappable_count = 0; | |
ca191b13 | 336 | count_vmas(&vm->active_list, mm_list); |
6299f992 CW |
337 | seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n", |
338 | count, mappable_count, size, mappable_size); | |
339 | ||
6299f992 | 340 | size = count = mappable_size = mappable_count = 0; |
ca191b13 | 341 | count_vmas(&vm->inactive_list, mm_list); |
6299f992 CW |
342 | seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n", |
343 | count, mappable_count, size, mappable_size); | |
344 | ||
b7abb714 | 345 | size = count = purgeable_size = purgeable_count = 0; |
35c20a60 | 346 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) { |
6c085a72 | 347 | size += obj->base.size, ++count; |
b7abb714 CW |
348 | if (obj->madv == I915_MADV_DONTNEED) |
349 | purgeable_size += obj->base.size, ++purgeable_count; | |
350 | } | |
6c085a72 CW |
351 | seq_printf(m, "%u unbound objects, %zu bytes\n", count, size); |
352 | ||
6299f992 | 353 | size = count = mappable_size = mappable_count = 0; |
35c20a60 | 354 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
6299f992 | 355 | if (obj->fault_mappable) { |
f343c5f6 | 356 | size += i915_gem_obj_ggtt_size(obj); |
6299f992 CW |
357 | ++count; |
358 | } | |
359 | if (obj->pin_mappable) { | |
f343c5f6 | 360 | mappable_size += i915_gem_obj_ggtt_size(obj); |
6299f992 CW |
361 | ++mappable_count; |
362 | } | |
b7abb714 CW |
363 | if (obj->madv == I915_MADV_DONTNEED) { |
364 | purgeable_size += obj->base.size; | |
365 | ++purgeable_count; | |
366 | } | |
6299f992 | 367 | } |
b7abb714 CW |
368 | seq_printf(m, "%u purgeable objects, %zu bytes\n", |
369 | purgeable_count, purgeable_size); | |
6299f992 CW |
370 | seq_printf(m, "%u pinned mappable objects, %zu bytes\n", |
371 | mappable_count, mappable_size); | |
372 | seq_printf(m, "%u fault mappable objects, %zu bytes\n", | |
373 | count, size); | |
374 | ||
93d18799 | 375 | seq_printf(m, "%zu [%lu] gtt total\n", |
853ba5d2 BW |
376 | dev_priv->gtt.base.total, |
377 | dev_priv->gtt.mappable_end - dev_priv->gtt.base.start); | |
73aa808f | 378 | |
267f0c90 | 379 | seq_putc(m, '\n'); |
2db8e9d6 CW |
380 | list_for_each_entry_reverse(file, &dev->filelist, lhead) { |
381 | struct file_stats stats; | |
382 | ||
383 | memset(&stats, 0, sizeof(stats)); | |
384 | idr_for_each(&file->object_idr, per_file_stats, &stats); | |
385 | seq_printf(m, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu unbound)\n", | |
386 | get_pid_task(file->pid, PIDTYPE_PID)->comm, | |
387 | stats.count, | |
388 | stats.total, | |
389 | stats.active, | |
390 | stats.inactive, | |
391 | stats.unbound); | |
392 | } | |
393 | ||
73aa808f CW |
394 | mutex_unlock(&dev->struct_mutex); |
395 | ||
396 | return 0; | |
397 | } | |
398 | ||
aee56cff | 399 | static int i915_gem_gtt_info(struct seq_file *m, void *data) |
08c18323 CW |
400 | { |
401 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
402 | struct drm_device *dev = node->minor->dev; | |
1b50247a | 403 | uintptr_t list = (uintptr_t) node->info_ent->data; |
08c18323 CW |
404 | struct drm_i915_private *dev_priv = dev->dev_private; |
405 | struct drm_i915_gem_object *obj; | |
406 | size_t total_obj_size, total_gtt_size; | |
407 | int count, ret; | |
408 | ||
409 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
410 | if (ret) | |
411 | return ret; | |
412 | ||
413 | total_obj_size = total_gtt_size = count = 0; | |
35c20a60 | 414 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
1b50247a CW |
415 | if (list == PINNED_LIST && obj->pin_count == 0) |
416 | continue; | |
417 | ||
267f0c90 | 418 | seq_puts(m, " "); |
08c18323 | 419 | describe_obj(m, obj); |
267f0c90 | 420 | seq_putc(m, '\n'); |
08c18323 | 421 | total_obj_size += obj->base.size; |
f343c5f6 | 422 | total_gtt_size += i915_gem_obj_ggtt_size(obj); |
08c18323 CW |
423 | count++; |
424 | } | |
425 | ||
426 | mutex_unlock(&dev->struct_mutex); | |
427 | ||
428 | seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n", | |
429 | count, total_obj_size, total_gtt_size); | |
430 | ||
431 | return 0; | |
432 | } | |
433 | ||
4e5359cd SF |
434 | static int i915_gem_pageflip_info(struct seq_file *m, void *data) |
435 | { | |
436 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
437 | struct drm_device *dev = node->minor->dev; | |
438 | unsigned long flags; | |
439 | struct intel_crtc *crtc; | |
440 | ||
441 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { | |
9db4a9c7 JB |
442 | const char pipe = pipe_name(crtc->pipe); |
443 | const char plane = plane_name(crtc->plane); | |
4e5359cd SF |
444 | struct intel_unpin_work *work; |
445 | ||
446 | spin_lock_irqsave(&dev->event_lock, flags); | |
447 | work = crtc->unpin_work; | |
448 | if (work == NULL) { | |
9db4a9c7 | 449 | seq_printf(m, "No flip due on pipe %c (plane %c)\n", |
4e5359cd SF |
450 | pipe, plane); |
451 | } else { | |
e7d841ca | 452 | if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { |
9db4a9c7 | 453 | seq_printf(m, "Flip queued on pipe %c (plane %c)\n", |
4e5359cd SF |
454 | pipe, plane); |
455 | } else { | |
9db4a9c7 | 456 | seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n", |
4e5359cd SF |
457 | pipe, plane); |
458 | } | |
459 | if (work->enable_stall_check) | |
267f0c90 | 460 | seq_puts(m, "Stall check enabled, "); |
4e5359cd | 461 | else |
267f0c90 | 462 | seq_puts(m, "Stall check waiting for page flip ioctl, "); |
e7d841ca | 463 | seq_printf(m, "%d prepares\n", atomic_read(&work->pending)); |
4e5359cd SF |
464 | |
465 | if (work->old_fb_obj) { | |
05394f39 CW |
466 | struct drm_i915_gem_object *obj = work->old_fb_obj; |
467 | if (obj) | |
f343c5f6 BW |
468 | seq_printf(m, "Old framebuffer gtt_offset 0x%08lx\n", |
469 | i915_gem_obj_ggtt_offset(obj)); | |
4e5359cd SF |
470 | } |
471 | if (work->pending_flip_obj) { | |
05394f39 CW |
472 | struct drm_i915_gem_object *obj = work->pending_flip_obj; |
473 | if (obj) | |
f343c5f6 BW |
474 | seq_printf(m, "New framebuffer gtt_offset 0x%08lx\n", |
475 | i915_gem_obj_ggtt_offset(obj)); | |
4e5359cd SF |
476 | } |
477 | } | |
478 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
479 | } | |
480 | ||
481 | return 0; | |
482 | } | |
483 | ||
2017263e BG |
484 | static int i915_gem_request_info(struct seq_file *m, void *data) |
485 | { | |
486 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
487 | struct drm_device *dev = node->minor->dev; | |
488 | drm_i915_private_t *dev_priv = dev->dev_private; | |
a2c7f6fd | 489 | struct intel_ring_buffer *ring; |
2017263e | 490 | struct drm_i915_gem_request *gem_request; |
a2c7f6fd | 491 | int ret, count, i; |
de227ef0 CW |
492 | |
493 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
494 | if (ret) | |
495 | return ret; | |
2017263e | 496 | |
c2c347a9 | 497 | count = 0; |
a2c7f6fd CW |
498 | for_each_ring(ring, dev_priv, i) { |
499 | if (list_empty(&ring->request_list)) | |
500 | continue; | |
501 | ||
502 | seq_printf(m, "%s requests:\n", ring->name); | |
c2c347a9 | 503 | list_for_each_entry(gem_request, |
a2c7f6fd | 504 | &ring->request_list, |
c2c347a9 CW |
505 | list) { |
506 | seq_printf(m, " %d @ %d\n", | |
507 | gem_request->seqno, | |
508 | (int) (jiffies - gem_request->emitted_jiffies)); | |
509 | } | |
510 | count++; | |
2017263e | 511 | } |
de227ef0 CW |
512 | mutex_unlock(&dev->struct_mutex); |
513 | ||
c2c347a9 | 514 | if (count == 0) |
267f0c90 | 515 | seq_puts(m, "No requests\n"); |
c2c347a9 | 516 | |
2017263e BG |
517 | return 0; |
518 | } | |
519 | ||
b2223497 CW |
520 | static void i915_ring_seqno_info(struct seq_file *m, |
521 | struct intel_ring_buffer *ring) | |
522 | { | |
523 | if (ring->get_seqno) { | |
43a7b924 | 524 | seq_printf(m, "Current sequence (%s): %u\n", |
b2eadbc8 | 525 | ring->name, ring->get_seqno(ring, false)); |
b2223497 CW |
526 | } |
527 | } | |
528 | ||
2017263e BG |
529 | static int i915_gem_seqno_info(struct seq_file *m, void *data) |
530 | { | |
531 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
532 | struct drm_device *dev = node->minor->dev; | |
533 | drm_i915_private_t *dev_priv = dev->dev_private; | |
a2c7f6fd | 534 | struct intel_ring_buffer *ring; |
1ec14ad3 | 535 | int ret, i; |
de227ef0 CW |
536 | |
537 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
538 | if (ret) | |
539 | return ret; | |
2017263e | 540 | |
a2c7f6fd CW |
541 | for_each_ring(ring, dev_priv, i) |
542 | i915_ring_seqno_info(m, ring); | |
de227ef0 CW |
543 | |
544 | mutex_unlock(&dev->struct_mutex); | |
545 | ||
2017263e BG |
546 | return 0; |
547 | } | |
548 | ||
549 | ||
550 | static int i915_interrupt_info(struct seq_file *m, void *data) | |
551 | { | |
552 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
553 | struct drm_device *dev = node->minor->dev; | |
554 | drm_i915_private_t *dev_priv = dev->dev_private; | |
a2c7f6fd | 555 | struct intel_ring_buffer *ring; |
9db4a9c7 | 556 | int ret, i, pipe; |
de227ef0 CW |
557 | |
558 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
559 | if (ret) | |
560 | return ret; | |
2017263e | 561 | |
7e231dbe JB |
562 | if (IS_VALLEYVIEW(dev)) { |
563 | seq_printf(m, "Display IER:\t%08x\n", | |
564 | I915_READ(VLV_IER)); | |
565 | seq_printf(m, "Display IIR:\t%08x\n", | |
566 | I915_READ(VLV_IIR)); | |
567 | seq_printf(m, "Display IIR_RW:\t%08x\n", | |
568 | I915_READ(VLV_IIR_RW)); | |
569 | seq_printf(m, "Display IMR:\t%08x\n", | |
570 | I915_READ(VLV_IMR)); | |
571 | for_each_pipe(pipe) | |
572 | seq_printf(m, "Pipe %c stat:\t%08x\n", | |
573 | pipe_name(pipe), | |
574 | I915_READ(PIPESTAT(pipe))); | |
575 | ||
576 | seq_printf(m, "Master IER:\t%08x\n", | |
577 | I915_READ(VLV_MASTER_IER)); | |
578 | ||
579 | seq_printf(m, "Render IER:\t%08x\n", | |
580 | I915_READ(GTIER)); | |
581 | seq_printf(m, "Render IIR:\t%08x\n", | |
582 | I915_READ(GTIIR)); | |
583 | seq_printf(m, "Render IMR:\t%08x\n", | |
584 | I915_READ(GTIMR)); | |
585 | ||
586 | seq_printf(m, "PM IER:\t\t%08x\n", | |
587 | I915_READ(GEN6_PMIER)); | |
588 | seq_printf(m, "PM IIR:\t\t%08x\n", | |
589 | I915_READ(GEN6_PMIIR)); | |
590 | seq_printf(m, "PM IMR:\t\t%08x\n", | |
591 | I915_READ(GEN6_PMIMR)); | |
592 | ||
593 | seq_printf(m, "Port hotplug:\t%08x\n", | |
594 | I915_READ(PORT_HOTPLUG_EN)); | |
595 | seq_printf(m, "DPFLIPSTAT:\t%08x\n", | |
596 | I915_READ(VLV_DPFLIPSTAT)); | |
597 | seq_printf(m, "DPINVGTT:\t%08x\n", | |
598 | I915_READ(DPINVGTT)); | |
599 | ||
600 | } else if (!HAS_PCH_SPLIT(dev)) { | |
5f6a1695 ZW |
601 | seq_printf(m, "Interrupt enable: %08x\n", |
602 | I915_READ(IER)); | |
603 | seq_printf(m, "Interrupt identity: %08x\n", | |
604 | I915_READ(IIR)); | |
605 | seq_printf(m, "Interrupt mask: %08x\n", | |
606 | I915_READ(IMR)); | |
9db4a9c7 JB |
607 | for_each_pipe(pipe) |
608 | seq_printf(m, "Pipe %c stat: %08x\n", | |
609 | pipe_name(pipe), | |
610 | I915_READ(PIPESTAT(pipe))); | |
5f6a1695 ZW |
611 | } else { |
612 | seq_printf(m, "North Display Interrupt enable: %08x\n", | |
613 | I915_READ(DEIER)); | |
614 | seq_printf(m, "North Display Interrupt identity: %08x\n", | |
615 | I915_READ(DEIIR)); | |
616 | seq_printf(m, "North Display Interrupt mask: %08x\n", | |
617 | I915_READ(DEIMR)); | |
618 | seq_printf(m, "South Display Interrupt enable: %08x\n", | |
619 | I915_READ(SDEIER)); | |
620 | seq_printf(m, "South Display Interrupt identity: %08x\n", | |
621 | I915_READ(SDEIIR)); | |
622 | seq_printf(m, "South Display Interrupt mask: %08x\n", | |
623 | I915_READ(SDEIMR)); | |
624 | seq_printf(m, "Graphics Interrupt enable: %08x\n", | |
625 | I915_READ(GTIER)); | |
626 | seq_printf(m, "Graphics Interrupt identity: %08x\n", | |
627 | I915_READ(GTIIR)); | |
628 | seq_printf(m, "Graphics Interrupt mask: %08x\n", | |
629 | I915_READ(GTIMR)); | |
630 | } | |
2017263e BG |
631 | seq_printf(m, "Interrupts received: %d\n", |
632 | atomic_read(&dev_priv->irq_received)); | |
a2c7f6fd | 633 | for_each_ring(ring, dev_priv, i) { |
da64c6fc | 634 | if (IS_GEN6(dev) || IS_GEN7(dev)) { |
a2c7f6fd CW |
635 | seq_printf(m, |
636 | "Graphics Interrupt mask (%s): %08x\n", | |
637 | ring->name, I915_READ_IMR(ring)); | |
9862e600 | 638 | } |
a2c7f6fd | 639 | i915_ring_seqno_info(m, ring); |
9862e600 | 640 | } |
de227ef0 CW |
641 | mutex_unlock(&dev->struct_mutex); |
642 | ||
2017263e BG |
643 | return 0; |
644 | } | |
645 | ||
a6172a80 CW |
646 | static int i915_gem_fence_regs_info(struct seq_file *m, void *data) |
647 | { | |
648 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
649 | struct drm_device *dev = node->minor->dev; | |
650 | drm_i915_private_t *dev_priv = dev->dev_private; | |
de227ef0 CW |
651 | int i, ret; |
652 | ||
653 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
654 | if (ret) | |
655 | return ret; | |
a6172a80 CW |
656 | |
657 | seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start); | |
658 | seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs); | |
659 | for (i = 0; i < dev_priv->num_fence_regs; i++) { | |
05394f39 | 660 | struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj; |
a6172a80 | 661 | |
6c085a72 CW |
662 | seq_printf(m, "Fence %d, pin count = %d, object = ", |
663 | i, dev_priv->fence_regs[i].pin_count); | |
c2c347a9 | 664 | if (obj == NULL) |
267f0c90 | 665 | seq_puts(m, "unused"); |
c2c347a9 | 666 | else |
05394f39 | 667 | describe_obj(m, obj); |
267f0c90 | 668 | seq_putc(m, '\n'); |
a6172a80 CW |
669 | } |
670 | ||
05394f39 | 671 | mutex_unlock(&dev->struct_mutex); |
a6172a80 CW |
672 | return 0; |
673 | } | |
674 | ||
2017263e BG |
675 | static int i915_hws_info(struct seq_file *m, void *data) |
676 | { | |
677 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
678 | struct drm_device *dev = node->minor->dev; | |
679 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4066c0ae | 680 | struct intel_ring_buffer *ring; |
1a240d4d | 681 | const u32 *hws; |
4066c0ae CW |
682 | int i; |
683 | ||
1ec14ad3 | 684 | ring = &dev_priv->ring[(uintptr_t)node->info_ent->data]; |
1a240d4d | 685 | hws = ring->status_page.page_addr; |
2017263e BG |
686 | if (hws == NULL) |
687 | return 0; | |
688 | ||
689 | for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) { | |
690 | seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n", | |
691 | i * 4, | |
692 | hws[i], hws[i + 1], hws[i + 2], hws[i + 3]); | |
693 | } | |
694 | return 0; | |
695 | } | |
696 | ||
d5442303 DV |
697 | static ssize_t |
698 | i915_error_state_write(struct file *filp, | |
699 | const char __user *ubuf, | |
700 | size_t cnt, | |
701 | loff_t *ppos) | |
702 | { | |
edc3d884 | 703 | struct i915_error_state_file_priv *error_priv = filp->private_data; |
d5442303 | 704 | struct drm_device *dev = error_priv->dev; |
22bcfc6a | 705 | int ret; |
d5442303 DV |
706 | |
707 | DRM_DEBUG_DRIVER("Resetting error state\n"); | |
708 | ||
22bcfc6a DV |
709 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
710 | if (ret) | |
711 | return ret; | |
712 | ||
d5442303 DV |
713 | i915_destroy_error_state(dev); |
714 | mutex_unlock(&dev->struct_mutex); | |
715 | ||
716 | return cnt; | |
717 | } | |
718 | ||
719 | static int i915_error_state_open(struct inode *inode, struct file *file) | |
720 | { | |
721 | struct drm_device *dev = inode->i_private; | |
d5442303 | 722 | struct i915_error_state_file_priv *error_priv; |
d5442303 DV |
723 | |
724 | error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL); | |
725 | if (!error_priv) | |
726 | return -ENOMEM; | |
727 | ||
728 | error_priv->dev = dev; | |
729 | ||
95d5bfb3 | 730 | i915_error_state_get(dev, error_priv); |
d5442303 | 731 | |
edc3d884 MK |
732 | file->private_data = error_priv; |
733 | ||
734 | return 0; | |
d5442303 DV |
735 | } |
736 | ||
737 | static int i915_error_state_release(struct inode *inode, struct file *file) | |
738 | { | |
edc3d884 | 739 | struct i915_error_state_file_priv *error_priv = file->private_data; |
d5442303 | 740 | |
95d5bfb3 | 741 | i915_error_state_put(error_priv); |
d5442303 DV |
742 | kfree(error_priv); |
743 | ||
edc3d884 MK |
744 | return 0; |
745 | } | |
746 | ||
4dc955f7 MK |
747 | static ssize_t i915_error_state_read(struct file *file, char __user *userbuf, |
748 | size_t count, loff_t *pos) | |
749 | { | |
750 | struct i915_error_state_file_priv *error_priv = file->private_data; | |
751 | struct drm_i915_error_state_buf error_str; | |
752 | loff_t tmp_pos = 0; | |
753 | ssize_t ret_count = 0; | |
754 | int ret; | |
755 | ||
756 | ret = i915_error_state_buf_init(&error_str, count, *pos); | |
757 | if (ret) | |
758 | return ret; | |
edc3d884 | 759 | |
fc16b48b | 760 | ret = i915_error_state_to_str(&error_str, error_priv); |
edc3d884 MK |
761 | if (ret) |
762 | goto out; | |
763 | ||
edc3d884 MK |
764 | ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos, |
765 | error_str.buf, | |
766 | error_str.bytes); | |
767 | ||
768 | if (ret_count < 0) | |
769 | ret = ret_count; | |
770 | else | |
771 | *pos = error_str.start + ret_count; | |
772 | out: | |
4dc955f7 | 773 | i915_error_state_buf_release(&error_str); |
edc3d884 | 774 | return ret ?: ret_count; |
d5442303 DV |
775 | } |
776 | ||
777 | static const struct file_operations i915_error_state_fops = { | |
778 | .owner = THIS_MODULE, | |
779 | .open = i915_error_state_open, | |
edc3d884 | 780 | .read = i915_error_state_read, |
d5442303 DV |
781 | .write = i915_error_state_write, |
782 | .llseek = default_llseek, | |
783 | .release = i915_error_state_release, | |
784 | }; | |
785 | ||
647416f9 KC |
786 | static int |
787 | i915_next_seqno_get(void *data, u64 *val) | |
40633219 | 788 | { |
647416f9 | 789 | struct drm_device *dev = data; |
40633219 | 790 | drm_i915_private_t *dev_priv = dev->dev_private; |
40633219 MK |
791 | int ret; |
792 | ||
793 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
794 | if (ret) | |
795 | return ret; | |
796 | ||
647416f9 | 797 | *val = dev_priv->next_seqno; |
40633219 MK |
798 | mutex_unlock(&dev->struct_mutex); |
799 | ||
647416f9 | 800 | return 0; |
40633219 MK |
801 | } |
802 | ||
647416f9 KC |
803 | static int |
804 | i915_next_seqno_set(void *data, u64 val) | |
805 | { | |
806 | struct drm_device *dev = data; | |
40633219 MK |
807 | int ret; |
808 | ||
40633219 MK |
809 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
810 | if (ret) | |
811 | return ret; | |
812 | ||
e94fbaa8 | 813 | ret = i915_gem_set_seqno(dev, val); |
40633219 MK |
814 | mutex_unlock(&dev->struct_mutex); |
815 | ||
647416f9 | 816 | return ret; |
40633219 MK |
817 | } |
818 | ||
647416f9 KC |
819 | DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops, |
820 | i915_next_seqno_get, i915_next_seqno_set, | |
3a3b4f98 | 821 | "0x%llx\n"); |
40633219 | 822 | |
f97108d1 JB |
823 | static int i915_rstdby_delays(struct seq_file *m, void *unused) |
824 | { | |
825 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
826 | struct drm_device *dev = node->minor->dev; | |
827 | drm_i915_private_t *dev_priv = dev->dev_private; | |
616fdb5a BW |
828 | u16 crstanddelay; |
829 | int ret; | |
830 | ||
831 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
832 | if (ret) | |
833 | return ret; | |
834 | ||
835 | crstanddelay = I915_READ16(CRSTANDVID); | |
836 | ||
837 | mutex_unlock(&dev->struct_mutex); | |
f97108d1 JB |
838 | |
839 | seq_printf(m, "w/ctx: %d, w/o ctx: %d\n", (crstanddelay >> 8) & 0x3f, (crstanddelay & 0x3f)); | |
840 | ||
841 | return 0; | |
842 | } | |
843 | ||
844 | static int i915_cur_delayinfo(struct seq_file *m, void *unused) | |
845 | { | |
846 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
847 | struct drm_device *dev = node->minor->dev; | |
848 | drm_i915_private_t *dev_priv = dev->dev_private; | |
d1ebd816 | 849 | int ret; |
3b8d8d91 | 850 | |
5c9669ce TR |
851 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
852 | ||
3b8d8d91 JB |
853 | if (IS_GEN5(dev)) { |
854 | u16 rgvswctl = I915_READ16(MEMSWCTL); | |
855 | u16 rgvstat = I915_READ16(MEMSTAT_ILK); | |
856 | ||
857 | seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf); | |
858 | seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f); | |
859 | seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >> | |
860 | MEMSTAT_VID_SHIFT); | |
861 | seq_printf(m, "Current P-state: %d\n", | |
862 | (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT); | |
0a073b84 | 863 | } else if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) { |
3b8d8d91 JB |
864 | u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS); |
865 | u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS); | |
866 | u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); | |
8e8c06cd | 867 | u32 rpstat, cagf, reqf; |
ccab5c82 JB |
868 | u32 rpupei, rpcurup, rpprevup; |
869 | u32 rpdownei, rpcurdown, rpprevdown; | |
3b8d8d91 JB |
870 | int max_freq; |
871 | ||
872 | /* RPSTAT1 is in the GT power well */ | |
d1ebd816 BW |
873 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
874 | if (ret) | |
875 | return ret; | |
876 | ||
fcca7926 | 877 | gen6_gt_force_wake_get(dev_priv); |
3b8d8d91 | 878 | |
8e8c06cd CW |
879 | reqf = I915_READ(GEN6_RPNSWREQ); |
880 | reqf &= ~GEN6_TURBO_DISABLE; | |
881 | if (IS_HASWELL(dev)) | |
882 | reqf >>= 24; | |
883 | else | |
884 | reqf >>= 25; | |
885 | reqf *= GT_FREQUENCY_MULTIPLIER; | |
886 | ||
ccab5c82 JB |
887 | rpstat = I915_READ(GEN6_RPSTAT1); |
888 | rpupei = I915_READ(GEN6_RP_CUR_UP_EI); | |
889 | rpcurup = I915_READ(GEN6_RP_CUR_UP); | |
890 | rpprevup = I915_READ(GEN6_RP_PREV_UP); | |
891 | rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI); | |
892 | rpcurdown = I915_READ(GEN6_RP_CUR_DOWN); | |
893 | rpprevdown = I915_READ(GEN6_RP_PREV_DOWN); | |
f82855d3 BW |
894 | if (IS_HASWELL(dev)) |
895 | cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT; | |
896 | else | |
897 | cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT; | |
898 | cagf *= GT_FREQUENCY_MULTIPLIER; | |
ccab5c82 | 899 | |
d1ebd816 BW |
900 | gen6_gt_force_wake_put(dev_priv); |
901 | mutex_unlock(&dev->struct_mutex); | |
902 | ||
3b8d8d91 | 903 | seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status); |
ccab5c82 | 904 | seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat); |
3b8d8d91 JB |
905 | seq_printf(m, "Render p-state ratio: %d\n", |
906 | (gt_perf_status & 0xff00) >> 8); | |
907 | seq_printf(m, "Render p-state VID: %d\n", | |
908 | gt_perf_status & 0xff); | |
909 | seq_printf(m, "Render p-state limit: %d\n", | |
910 | rp_state_limits & 0xff); | |
8e8c06cd | 911 | seq_printf(m, "RPNSWREQ: %dMHz\n", reqf); |
f82855d3 | 912 | seq_printf(m, "CAGF: %dMHz\n", cagf); |
ccab5c82 JB |
913 | seq_printf(m, "RP CUR UP EI: %dus\n", rpupei & |
914 | GEN6_CURICONT_MASK); | |
915 | seq_printf(m, "RP CUR UP: %dus\n", rpcurup & | |
916 | GEN6_CURBSYTAVG_MASK); | |
917 | seq_printf(m, "RP PREV UP: %dus\n", rpprevup & | |
918 | GEN6_CURBSYTAVG_MASK); | |
919 | seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei & | |
920 | GEN6_CURIAVG_MASK); | |
921 | seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown & | |
922 | GEN6_CURBSYTAVG_MASK); | |
923 | seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown & | |
924 | GEN6_CURBSYTAVG_MASK); | |
3b8d8d91 JB |
925 | |
926 | max_freq = (rp_state_cap & 0xff0000) >> 16; | |
927 | seq_printf(m, "Lowest (RPN) frequency: %dMHz\n", | |
c8735b0c | 928 | max_freq * GT_FREQUENCY_MULTIPLIER); |
3b8d8d91 JB |
929 | |
930 | max_freq = (rp_state_cap & 0xff00) >> 8; | |
931 | seq_printf(m, "Nominal (RP1) frequency: %dMHz\n", | |
c8735b0c | 932 | max_freq * GT_FREQUENCY_MULTIPLIER); |
3b8d8d91 JB |
933 | |
934 | max_freq = rp_state_cap & 0xff; | |
935 | seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n", | |
c8735b0c | 936 | max_freq * GT_FREQUENCY_MULTIPLIER); |
31c77388 BW |
937 | |
938 | seq_printf(m, "Max overclocked frequency: %dMHz\n", | |
939 | dev_priv->rps.hw_max * GT_FREQUENCY_MULTIPLIER); | |
0a073b84 JB |
940 | } else if (IS_VALLEYVIEW(dev)) { |
941 | u32 freq_sts, val; | |
942 | ||
259bd5d4 | 943 | mutex_lock(&dev_priv->rps.hw_lock); |
64936258 | 944 | freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); |
0a073b84 JB |
945 | seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts); |
946 | seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq); | |
947 | ||
64936258 | 948 | val = vlv_punit_read(dev_priv, PUNIT_FUSE_BUS1); |
0a073b84 JB |
949 | seq_printf(m, "max GPU freq: %d MHz\n", |
950 | vlv_gpu_freq(dev_priv->mem_freq, val)); | |
951 | ||
64936258 | 952 | val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM); |
0a073b84 JB |
953 | seq_printf(m, "min GPU freq: %d MHz\n", |
954 | vlv_gpu_freq(dev_priv->mem_freq, val)); | |
955 | ||
956 | seq_printf(m, "current GPU freq: %d MHz\n", | |
957 | vlv_gpu_freq(dev_priv->mem_freq, | |
958 | (freq_sts >> 8) & 0xff)); | |
259bd5d4 | 959 | mutex_unlock(&dev_priv->rps.hw_lock); |
3b8d8d91 | 960 | } else { |
267f0c90 | 961 | seq_puts(m, "no P-state info available\n"); |
3b8d8d91 | 962 | } |
f97108d1 JB |
963 | |
964 | return 0; | |
965 | } | |
966 | ||
967 | static int i915_delayfreq_table(struct seq_file *m, void *unused) | |
968 | { | |
969 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
970 | struct drm_device *dev = node->minor->dev; | |
971 | drm_i915_private_t *dev_priv = dev->dev_private; | |
972 | u32 delayfreq; | |
616fdb5a BW |
973 | int ret, i; |
974 | ||
975 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
976 | if (ret) | |
977 | return ret; | |
f97108d1 JB |
978 | |
979 | for (i = 0; i < 16; i++) { | |
980 | delayfreq = I915_READ(PXVFREQ_BASE + i * 4); | |
7648fa99 JB |
981 | seq_printf(m, "P%02dVIDFREQ: 0x%08x (VID: %d)\n", i, delayfreq, |
982 | (delayfreq & PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT); | |
f97108d1 JB |
983 | } |
984 | ||
616fdb5a BW |
985 | mutex_unlock(&dev->struct_mutex); |
986 | ||
f97108d1 JB |
987 | return 0; |
988 | } | |
989 | ||
990 | static inline int MAP_TO_MV(int map) | |
991 | { | |
992 | return 1250 - (map * 25); | |
993 | } | |
994 | ||
995 | static int i915_inttoext_table(struct seq_file *m, void *unused) | |
996 | { | |
997 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
998 | struct drm_device *dev = node->minor->dev; | |
999 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1000 | u32 inttoext; | |
616fdb5a BW |
1001 | int ret, i; |
1002 | ||
1003 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1004 | if (ret) | |
1005 | return ret; | |
f97108d1 JB |
1006 | |
1007 | for (i = 1; i <= 32; i++) { | |
1008 | inttoext = I915_READ(INTTOEXT_BASE_ILK + i * 4); | |
1009 | seq_printf(m, "INTTOEXT%02d: 0x%08x\n", i, inttoext); | |
1010 | } | |
1011 | ||
616fdb5a BW |
1012 | mutex_unlock(&dev->struct_mutex); |
1013 | ||
f97108d1 JB |
1014 | return 0; |
1015 | } | |
1016 | ||
4d85529d | 1017 | static int ironlake_drpc_info(struct seq_file *m) |
f97108d1 JB |
1018 | { |
1019 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1020 | struct drm_device *dev = node->minor->dev; | |
1021 | drm_i915_private_t *dev_priv = dev->dev_private; | |
616fdb5a BW |
1022 | u32 rgvmodectl, rstdbyctl; |
1023 | u16 crstandvid; | |
1024 | int ret; | |
1025 | ||
1026 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1027 | if (ret) | |
1028 | return ret; | |
1029 | ||
1030 | rgvmodectl = I915_READ(MEMMODECTL); | |
1031 | rstdbyctl = I915_READ(RSTDBYCTL); | |
1032 | crstandvid = I915_READ16(CRSTANDVID); | |
1033 | ||
1034 | mutex_unlock(&dev->struct_mutex); | |
f97108d1 JB |
1035 | |
1036 | seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ? | |
1037 | "yes" : "no"); | |
1038 | seq_printf(m, "Boost freq: %d\n", | |
1039 | (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >> | |
1040 | MEMMODE_BOOST_FREQ_SHIFT); | |
1041 | seq_printf(m, "HW control enabled: %s\n", | |
1042 | rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no"); | |
1043 | seq_printf(m, "SW control enabled: %s\n", | |
1044 | rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no"); | |
1045 | seq_printf(m, "Gated voltage change: %s\n", | |
1046 | rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no"); | |
1047 | seq_printf(m, "Starting frequency: P%d\n", | |
1048 | (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT); | |
7648fa99 | 1049 | seq_printf(m, "Max P-state: P%d\n", |
f97108d1 | 1050 | (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT); |
7648fa99 JB |
1051 | seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK)); |
1052 | seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f)); | |
1053 | seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f)); | |
1054 | seq_printf(m, "Render standby enabled: %s\n", | |
1055 | (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes"); | |
267f0c90 | 1056 | seq_puts(m, "Current RS state: "); |
88271da3 JB |
1057 | switch (rstdbyctl & RSX_STATUS_MASK) { |
1058 | case RSX_STATUS_ON: | |
267f0c90 | 1059 | seq_puts(m, "on\n"); |
88271da3 JB |
1060 | break; |
1061 | case RSX_STATUS_RC1: | |
267f0c90 | 1062 | seq_puts(m, "RC1\n"); |
88271da3 JB |
1063 | break; |
1064 | case RSX_STATUS_RC1E: | |
267f0c90 | 1065 | seq_puts(m, "RC1E\n"); |
88271da3 JB |
1066 | break; |
1067 | case RSX_STATUS_RS1: | |
267f0c90 | 1068 | seq_puts(m, "RS1\n"); |
88271da3 JB |
1069 | break; |
1070 | case RSX_STATUS_RS2: | |
267f0c90 | 1071 | seq_puts(m, "RS2 (RC6)\n"); |
88271da3 JB |
1072 | break; |
1073 | case RSX_STATUS_RS3: | |
267f0c90 | 1074 | seq_puts(m, "RC3 (RC6+)\n"); |
88271da3 JB |
1075 | break; |
1076 | default: | |
267f0c90 | 1077 | seq_puts(m, "unknown\n"); |
88271da3 JB |
1078 | break; |
1079 | } | |
f97108d1 JB |
1080 | |
1081 | return 0; | |
1082 | } | |
1083 | ||
4d85529d BW |
1084 | static int gen6_drpc_info(struct seq_file *m) |
1085 | { | |
1086 | ||
1087 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1088 | struct drm_device *dev = node->minor->dev; | |
1089 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ecd8faea | 1090 | u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0; |
93b525dc | 1091 | unsigned forcewake_count; |
aee56cff | 1092 | int count = 0, ret; |
4d85529d BW |
1093 | |
1094 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1095 | if (ret) | |
1096 | return ret; | |
1097 | ||
907b28c5 CW |
1098 | spin_lock_irq(&dev_priv->uncore.lock); |
1099 | forcewake_count = dev_priv->uncore.forcewake_count; | |
1100 | spin_unlock_irq(&dev_priv->uncore.lock); | |
93b525dc DV |
1101 | |
1102 | if (forcewake_count) { | |
267f0c90 DL |
1103 | seq_puts(m, "RC information inaccurate because somebody " |
1104 | "holds a forcewake reference \n"); | |
4d85529d BW |
1105 | } else { |
1106 | /* NB: we cannot use forcewake, else we read the wrong values */ | |
1107 | while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1)) | |
1108 | udelay(10); | |
1109 | seq_printf(m, "RC information accurate: %s\n", yesno(count < 51)); | |
1110 | } | |
1111 | ||
1112 | gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS); | |
ed71f1b4 | 1113 | trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true); |
4d85529d BW |
1114 | |
1115 | rpmodectl1 = I915_READ(GEN6_RP_CONTROL); | |
1116 | rcctl1 = I915_READ(GEN6_RC_CONTROL); | |
1117 | mutex_unlock(&dev->struct_mutex); | |
44cbd338 BW |
1118 | mutex_lock(&dev_priv->rps.hw_lock); |
1119 | sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids); | |
1120 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4d85529d BW |
1121 | |
1122 | seq_printf(m, "Video Turbo Mode: %s\n", | |
1123 | yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO)); | |
1124 | seq_printf(m, "HW control enabled: %s\n", | |
1125 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); | |
1126 | seq_printf(m, "SW control enabled: %s\n", | |
1127 | yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) == | |
1128 | GEN6_RP_MEDIA_SW_MODE)); | |
fff24e21 | 1129 | seq_printf(m, "RC1e Enabled: %s\n", |
4d85529d BW |
1130 | yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE)); |
1131 | seq_printf(m, "RC6 Enabled: %s\n", | |
1132 | yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE)); | |
1133 | seq_printf(m, "Deep RC6 Enabled: %s\n", | |
1134 | yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE)); | |
1135 | seq_printf(m, "Deepest RC6 Enabled: %s\n", | |
1136 | yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE)); | |
267f0c90 | 1137 | seq_puts(m, "Current RC state: "); |
4d85529d BW |
1138 | switch (gt_core_status & GEN6_RCn_MASK) { |
1139 | case GEN6_RC0: | |
1140 | if (gt_core_status & GEN6_CORE_CPD_STATE_MASK) | |
267f0c90 | 1141 | seq_puts(m, "Core Power Down\n"); |
4d85529d | 1142 | else |
267f0c90 | 1143 | seq_puts(m, "on\n"); |
4d85529d BW |
1144 | break; |
1145 | case GEN6_RC3: | |
267f0c90 | 1146 | seq_puts(m, "RC3\n"); |
4d85529d BW |
1147 | break; |
1148 | case GEN6_RC6: | |
267f0c90 | 1149 | seq_puts(m, "RC6\n"); |
4d85529d BW |
1150 | break; |
1151 | case GEN6_RC7: | |
267f0c90 | 1152 | seq_puts(m, "RC7\n"); |
4d85529d BW |
1153 | break; |
1154 | default: | |
267f0c90 | 1155 | seq_puts(m, "Unknown\n"); |
4d85529d BW |
1156 | break; |
1157 | } | |
1158 | ||
1159 | seq_printf(m, "Core Power Down: %s\n", | |
1160 | yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK)); | |
cce66a28 BW |
1161 | |
1162 | /* Not exactly sure what this is */ | |
1163 | seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n", | |
1164 | I915_READ(GEN6_GT_GFX_RC6_LOCKED)); | |
1165 | seq_printf(m, "RC6 residency since boot: %u\n", | |
1166 | I915_READ(GEN6_GT_GFX_RC6)); | |
1167 | seq_printf(m, "RC6+ residency since boot: %u\n", | |
1168 | I915_READ(GEN6_GT_GFX_RC6p)); | |
1169 | seq_printf(m, "RC6++ residency since boot: %u\n", | |
1170 | I915_READ(GEN6_GT_GFX_RC6pp)); | |
1171 | ||
ecd8faea BW |
1172 | seq_printf(m, "RC6 voltage: %dmV\n", |
1173 | GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff))); | |
1174 | seq_printf(m, "RC6+ voltage: %dmV\n", | |
1175 | GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff))); | |
1176 | seq_printf(m, "RC6++ voltage: %dmV\n", | |
1177 | GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff))); | |
4d85529d BW |
1178 | return 0; |
1179 | } | |
1180 | ||
1181 | static int i915_drpc_info(struct seq_file *m, void *unused) | |
1182 | { | |
1183 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1184 | struct drm_device *dev = node->minor->dev; | |
1185 | ||
1186 | if (IS_GEN6(dev) || IS_GEN7(dev)) | |
1187 | return gen6_drpc_info(m); | |
1188 | else | |
1189 | return ironlake_drpc_info(m); | |
1190 | } | |
1191 | ||
b5e50c3f JB |
1192 | static int i915_fbc_status(struct seq_file *m, void *unused) |
1193 | { | |
1194 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1195 | struct drm_device *dev = node->minor->dev; | |
b5e50c3f | 1196 | drm_i915_private_t *dev_priv = dev->dev_private; |
b5e50c3f | 1197 | |
ee5382ae | 1198 | if (!I915_HAS_FBC(dev)) { |
267f0c90 | 1199 | seq_puts(m, "FBC unsupported on this chipset\n"); |
b5e50c3f JB |
1200 | return 0; |
1201 | } | |
1202 | ||
ee5382ae | 1203 | if (intel_fbc_enabled(dev)) { |
267f0c90 | 1204 | seq_puts(m, "FBC enabled\n"); |
b5e50c3f | 1205 | } else { |
267f0c90 | 1206 | seq_puts(m, "FBC disabled: "); |
5c3fe8b0 | 1207 | switch (dev_priv->fbc.no_fbc_reason) { |
29ebf90f CW |
1208 | case FBC_OK: |
1209 | seq_puts(m, "FBC actived, but currently disabled in hardware"); | |
1210 | break; | |
1211 | case FBC_UNSUPPORTED: | |
1212 | seq_puts(m, "unsupported by this chipset"); | |
1213 | break; | |
bed4a673 | 1214 | case FBC_NO_OUTPUT: |
267f0c90 | 1215 | seq_puts(m, "no outputs"); |
bed4a673 | 1216 | break; |
b5e50c3f | 1217 | case FBC_STOLEN_TOO_SMALL: |
267f0c90 | 1218 | seq_puts(m, "not enough stolen memory"); |
b5e50c3f JB |
1219 | break; |
1220 | case FBC_UNSUPPORTED_MODE: | |
267f0c90 | 1221 | seq_puts(m, "mode not supported"); |
b5e50c3f JB |
1222 | break; |
1223 | case FBC_MODE_TOO_LARGE: | |
267f0c90 | 1224 | seq_puts(m, "mode too large"); |
b5e50c3f JB |
1225 | break; |
1226 | case FBC_BAD_PLANE: | |
267f0c90 | 1227 | seq_puts(m, "FBC unsupported on plane"); |
b5e50c3f JB |
1228 | break; |
1229 | case FBC_NOT_TILED: | |
267f0c90 | 1230 | seq_puts(m, "scanout buffer not tiled"); |
b5e50c3f | 1231 | break; |
9c928d16 | 1232 | case FBC_MULTIPLE_PIPES: |
267f0c90 | 1233 | seq_puts(m, "multiple pipes are enabled"); |
9c928d16 | 1234 | break; |
c1a9f047 | 1235 | case FBC_MODULE_PARAM: |
267f0c90 | 1236 | seq_puts(m, "disabled per module param (default off)"); |
c1a9f047 | 1237 | break; |
8a5729a3 | 1238 | case FBC_CHIP_DEFAULT: |
267f0c90 | 1239 | seq_puts(m, "disabled per chip default"); |
8a5729a3 | 1240 | break; |
b5e50c3f | 1241 | default: |
267f0c90 | 1242 | seq_puts(m, "unknown reason"); |
b5e50c3f | 1243 | } |
267f0c90 | 1244 | seq_putc(m, '\n'); |
b5e50c3f JB |
1245 | } |
1246 | return 0; | |
1247 | } | |
1248 | ||
92d44621 PZ |
1249 | static int i915_ips_status(struct seq_file *m, void *unused) |
1250 | { | |
1251 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1252 | struct drm_device *dev = node->minor->dev; | |
1253 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1254 | ||
f5adf94e | 1255 | if (!HAS_IPS(dev)) { |
92d44621 PZ |
1256 | seq_puts(m, "not supported\n"); |
1257 | return 0; | |
1258 | } | |
1259 | ||
1260 | if (I915_READ(IPS_CTL) & IPS_ENABLE) | |
1261 | seq_puts(m, "enabled\n"); | |
1262 | else | |
1263 | seq_puts(m, "disabled\n"); | |
1264 | ||
1265 | return 0; | |
1266 | } | |
1267 | ||
4a9bef37 JB |
1268 | static int i915_sr_status(struct seq_file *m, void *unused) |
1269 | { | |
1270 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1271 | struct drm_device *dev = node->minor->dev; | |
1272 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1273 | bool sr_enabled = false; | |
1274 | ||
1398261a | 1275 | if (HAS_PCH_SPLIT(dev)) |
5ba2aaaa | 1276 | sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN; |
a6c45cf0 | 1277 | else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev)) |
4a9bef37 JB |
1278 | sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN; |
1279 | else if (IS_I915GM(dev)) | |
1280 | sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN; | |
1281 | else if (IS_PINEVIEW(dev)) | |
1282 | sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN; | |
1283 | ||
5ba2aaaa CW |
1284 | seq_printf(m, "self-refresh: %s\n", |
1285 | sr_enabled ? "enabled" : "disabled"); | |
4a9bef37 JB |
1286 | |
1287 | return 0; | |
1288 | } | |
1289 | ||
7648fa99 JB |
1290 | static int i915_emon_status(struct seq_file *m, void *unused) |
1291 | { | |
1292 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1293 | struct drm_device *dev = node->minor->dev; | |
1294 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1295 | unsigned long temp, chipset, gfx; | |
de227ef0 CW |
1296 | int ret; |
1297 | ||
582be6b4 CW |
1298 | if (!IS_GEN5(dev)) |
1299 | return -ENODEV; | |
1300 | ||
de227ef0 CW |
1301 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1302 | if (ret) | |
1303 | return ret; | |
7648fa99 JB |
1304 | |
1305 | temp = i915_mch_val(dev_priv); | |
1306 | chipset = i915_chipset_val(dev_priv); | |
1307 | gfx = i915_gfx_val(dev_priv); | |
de227ef0 | 1308 | mutex_unlock(&dev->struct_mutex); |
7648fa99 JB |
1309 | |
1310 | seq_printf(m, "GMCH temp: %ld\n", temp); | |
1311 | seq_printf(m, "Chipset power: %ld\n", chipset); | |
1312 | seq_printf(m, "GFX power: %ld\n", gfx); | |
1313 | seq_printf(m, "Total power: %ld\n", chipset + gfx); | |
1314 | ||
1315 | return 0; | |
1316 | } | |
1317 | ||
23b2f8bb JB |
1318 | static int i915_ring_freq_table(struct seq_file *m, void *unused) |
1319 | { | |
1320 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1321 | struct drm_device *dev = node->minor->dev; | |
1322 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1323 | int ret; | |
1324 | int gpu_freq, ia_freq; | |
1325 | ||
1c70c0ce | 1326 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) { |
267f0c90 | 1327 | seq_puts(m, "unsupported on this chipset\n"); |
23b2f8bb JB |
1328 | return 0; |
1329 | } | |
1330 | ||
5c9669ce TR |
1331 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
1332 | ||
4fc688ce | 1333 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
23b2f8bb JB |
1334 | if (ret) |
1335 | return ret; | |
1336 | ||
267f0c90 | 1337 | seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n"); |
23b2f8bb | 1338 | |
c6a828d3 DV |
1339 | for (gpu_freq = dev_priv->rps.min_delay; |
1340 | gpu_freq <= dev_priv->rps.max_delay; | |
23b2f8bb | 1341 | gpu_freq++) { |
42c0526c BW |
1342 | ia_freq = gpu_freq; |
1343 | sandybridge_pcode_read(dev_priv, | |
1344 | GEN6_PCODE_READ_MIN_FREQ_TABLE, | |
1345 | &ia_freq); | |
3ebecd07 CW |
1346 | seq_printf(m, "%d\t\t%d\t\t\t\t%d\n", |
1347 | gpu_freq * GT_FREQUENCY_MULTIPLIER, | |
1348 | ((ia_freq >> 0) & 0xff) * 100, | |
1349 | ((ia_freq >> 8) & 0xff) * 100); | |
23b2f8bb JB |
1350 | } |
1351 | ||
4fc688ce | 1352 | mutex_unlock(&dev_priv->rps.hw_lock); |
23b2f8bb JB |
1353 | |
1354 | return 0; | |
1355 | } | |
1356 | ||
7648fa99 JB |
1357 | static int i915_gfxec(struct seq_file *m, void *unused) |
1358 | { | |
1359 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1360 | struct drm_device *dev = node->minor->dev; | |
1361 | drm_i915_private_t *dev_priv = dev->dev_private; | |
616fdb5a BW |
1362 | int ret; |
1363 | ||
1364 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1365 | if (ret) | |
1366 | return ret; | |
7648fa99 JB |
1367 | |
1368 | seq_printf(m, "GFXEC: %ld\n", (unsigned long)I915_READ(0x112f4)); | |
1369 | ||
616fdb5a BW |
1370 | mutex_unlock(&dev->struct_mutex); |
1371 | ||
7648fa99 JB |
1372 | return 0; |
1373 | } | |
1374 | ||
44834a67 CW |
1375 | static int i915_opregion(struct seq_file *m, void *unused) |
1376 | { | |
1377 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1378 | struct drm_device *dev = node->minor->dev; | |
1379 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1380 | struct intel_opregion *opregion = &dev_priv->opregion; | |
0d38f009 | 1381 | void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL); |
44834a67 CW |
1382 | int ret; |
1383 | ||
0d38f009 DV |
1384 | if (data == NULL) |
1385 | return -ENOMEM; | |
1386 | ||
44834a67 CW |
1387 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1388 | if (ret) | |
0d38f009 | 1389 | goto out; |
44834a67 | 1390 | |
0d38f009 DV |
1391 | if (opregion->header) { |
1392 | memcpy_fromio(data, opregion->header, OPREGION_SIZE); | |
1393 | seq_write(m, data, OPREGION_SIZE); | |
1394 | } | |
44834a67 CW |
1395 | |
1396 | mutex_unlock(&dev->struct_mutex); | |
1397 | ||
0d38f009 DV |
1398 | out: |
1399 | kfree(data); | |
44834a67 CW |
1400 | return 0; |
1401 | } | |
1402 | ||
37811fcc CW |
1403 | static int i915_gem_framebuffer_info(struct seq_file *m, void *data) |
1404 | { | |
1405 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1406 | struct drm_device *dev = node->minor->dev; | |
4520f53a | 1407 | struct intel_fbdev *ifbdev = NULL; |
37811fcc | 1408 | struct intel_framebuffer *fb; |
37811fcc | 1409 | |
4520f53a DV |
1410 | #ifdef CONFIG_DRM_I915_FBDEV |
1411 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1412 | int ret = mutex_lock_interruptible(&dev->mode_config.mutex); | |
37811fcc CW |
1413 | if (ret) |
1414 | return ret; | |
1415 | ||
1416 | ifbdev = dev_priv->fbdev; | |
1417 | fb = to_intel_framebuffer(ifbdev->helper.fb); | |
1418 | ||
623f9783 | 1419 | seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, refcount %d, obj ", |
37811fcc CW |
1420 | fb->base.width, |
1421 | fb->base.height, | |
1422 | fb->base.depth, | |
623f9783 DV |
1423 | fb->base.bits_per_pixel, |
1424 | atomic_read(&fb->base.refcount.refcount)); | |
05394f39 | 1425 | describe_obj(m, fb->obj); |
267f0c90 | 1426 | seq_putc(m, '\n'); |
4b096ac1 | 1427 | mutex_unlock(&dev->mode_config.mutex); |
4520f53a | 1428 | #endif |
37811fcc | 1429 | |
4b096ac1 | 1430 | mutex_lock(&dev->mode_config.fb_lock); |
37811fcc CW |
1431 | list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) { |
1432 | if (&fb->base == ifbdev->helper.fb) | |
1433 | continue; | |
1434 | ||
623f9783 | 1435 | seq_printf(m, "user size: %d x %d, depth %d, %d bpp, refcount %d, obj ", |
37811fcc CW |
1436 | fb->base.width, |
1437 | fb->base.height, | |
1438 | fb->base.depth, | |
623f9783 DV |
1439 | fb->base.bits_per_pixel, |
1440 | atomic_read(&fb->base.refcount.refcount)); | |
05394f39 | 1441 | describe_obj(m, fb->obj); |
267f0c90 | 1442 | seq_putc(m, '\n'); |
37811fcc | 1443 | } |
4b096ac1 | 1444 | mutex_unlock(&dev->mode_config.fb_lock); |
37811fcc CW |
1445 | |
1446 | return 0; | |
1447 | } | |
1448 | ||
e76d3630 BW |
1449 | static int i915_context_status(struct seq_file *m, void *unused) |
1450 | { | |
1451 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1452 | struct drm_device *dev = node->minor->dev; | |
1453 | drm_i915_private_t *dev_priv = dev->dev_private; | |
a168c293 | 1454 | struct intel_ring_buffer *ring; |
a33afea5 | 1455 | struct i915_hw_context *ctx; |
a168c293 | 1456 | int ret, i; |
e76d3630 BW |
1457 | |
1458 | ret = mutex_lock_interruptible(&dev->mode_config.mutex); | |
1459 | if (ret) | |
1460 | return ret; | |
1461 | ||
3e373948 | 1462 | if (dev_priv->ips.pwrctx) { |
267f0c90 | 1463 | seq_puts(m, "power context "); |
3e373948 | 1464 | describe_obj(m, dev_priv->ips.pwrctx); |
267f0c90 | 1465 | seq_putc(m, '\n'); |
dc501fbc | 1466 | } |
e76d3630 | 1467 | |
3e373948 | 1468 | if (dev_priv->ips.renderctx) { |
267f0c90 | 1469 | seq_puts(m, "render context "); |
3e373948 | 1470 | describe_obj(m, dev_priv->ips.renderctx); |
267f0c90 | 1471 | seq_putc(m, '\n'); |
dc501fbc | 1472 | } |
e76d3630 | 1473 | |
a33afea5 BW |
1474 | list_for_each_entry(ctx, &dev_priv->context_list, link) { |
1475 | seq_puts(m, "HW context "); | |
3ccfd19d | 1476 | describe_ctx(m, ctx); |
a33afea5 BW |
1477 | for_each_ring(ring, dev_priv, i) |
1478 | if (ring->default_context == ctx) | |
1479 | seq_printf(m, "(default context %s) ", ring->name); | |
1480 | ||
1481 | describe_obj(m, ctx->obj); | |
1482 | seq_putc(m, '\n'); | |
a168c293 BW |
1483 | } |
1484 | ||
e76d3630 BW |
1485 | mutex_unlock(&dev->mode_config.mutex); |
1486 | ||
1487 | return 0; | |
1488 | } | |
1489 | ||
6d794d42 BW |
1490 | static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data) |
1491 | { | |
1492 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1493 | struct drm_device *dev = node->minor->dev; | |
1494 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9f1f46a4 | 1495 | unsigned forcewake_count; |
6d794d42 | 1496 | |
907b28c5 CW |
1497 | spin_lock_irq(&dev_priv->uncore.lock); |
1498 | forcewake_count = dev_priv->uncore.forcewake_count; | |
1499 | spin_unlock_irq(&dev_priv->uncore.lock); | |
6d794d42 | 1500 | |
9f1f46a4 | 1501 | seq_printf(m, "forcewake count = %u\n", forcewake_count); |
6d794d42 BW |
1502 | |
1503 | return 0; | |
1504 | } | |
1505 | ||
ea16a3cd DV |
1506 | static const char *swizzle_string(unsigned swizzle) |
1507 | { | |
aee56cff | 1508 | switch (swizzle) { |
ea16a3cd DV |
1509 | case I915_BIT_6_SWIZZLE_NONE: |
1510 | return "none"; | |
1511 | case I915_BIT_6_SWIZZLE_9: | |
1512 | return "bit9"; | |
1513 | case I915_BIT_6_SWIZZLE_9_10: | |
1514 | return "bit9/bit10"; | |
1515 | case I915_BIT_6_SWIZZLE_9_11: | |
1516 | return "bit9/bit11"; | |
1517 | case I915_BIT_6_SWIZZLE_9_10_11: | |
1518 | return "bit9/bit10/bit11"; | |
1519 | case I915_BIT_6_SWIZZLE_9_17: | |
1520 | return "bit9/bit17"; | |
1521 | case I915_BIT_6_SWIZZLE_9_10_17: | |
1522 | return "bit9/bit10/bit17"; | |
1523 | case I915_BIT_6_SWIZZLE_UNKNOWN: | |
8a168ca7 | 1524 | return "unknown"; |
ea16a3cd DV |
1525 | } |
1526 | ||
1527 | return "bug"; | |
1528 | } | |
1529 | ||
1530 | static int i915_swizzle_info(struct seq_file *m, void *data) | |
1531 | { | |
1532 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1533 | struct drm_device *dev = node->minor->dev; | |
1534 | struct drm_i915_private *dev_priv = dev->dev_private; | |
22bcfc6a DV |
1535 | int ret; |
1536 | ||
1537 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1538 | if (ret) | |
1539 | return ret; | |
ea16a3cd | 1540 | |
ea16a3cd DV |
1541 | seq_printf(m, "bit6 swizzle for X-tiling = %s\n", |
1542 | swizzle_string(dev_priv->mm.bit_6_swizzle_x)); | |
1543 | seq_printf(m, "bit6 swizzle for Y-tiling = %s\n", | |
1544 | swizzle_string(dev_priv->mm.bit_6_swizzle_y)); | |
1545 | ||
1546 | if (IS_GEN3(dev) || IS_GEN4(dev)) { | |
1547 | seq_printf(m, "DDC = 0x%08x\n", | |
1548 | I915_READ(DCC)); | |
1549 | seq_printf(m, "C0DRB3 = 0x%04x\n", | |
1550 | I915_READ16(C0DRB3)); | |
1551 | seq_printf(m, "C1DRB3 = 0x%04x\n", | |
1552 | I915_READ16(C1DRB3)); | |
3fa7d235 DV |
1553 | } else if (IS_GEN6(dev) || IS_GEN7(dev)) { |
1554 | seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n", | |
1555 | I915_READ(MAD_DIMM_C0)); | |
1556 | seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n", | |
1557 | I915_READ(MAD_DIMM_C1)); | |
1558 | seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n", | |
1559 | I915_READ(MAD_DIMM_C2)); | |
1560 | seq_printf(m, "TILECTL = 0x%08x\n", | |
1561 | I915_READ(TILECTL)); | |
1562 | seq_printf(m, "ARB_MODE = 0x%08x\n", | |
1563 | I915_READ(ARB_MODE)); | |
1564 | seq_printf(m, "DISP_ARB_CTL = 0x%08x\n", | |
1565 | I915_READ(DISP_ARB_CTL)); | |
ea16a3cd DV |
1566 | } |
1567 | mutex_unlock(&dev->struct_mutex); | |
1568 | ||
1569 | return 0; | |
1570 | } | |
1571 | ||
3cf17fc5 DV |
1572 | static int i915_ppgtt_info(struct seq_file *m, void *data) |
1573 | { | |
1574 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1575 | struct drm_device *dev = node->minor->dev; | |
1576 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1577 | struct intel_ring_buffer *ring; | |
1578 | int i, ret; | |
1579 | ||
1580 | ||
1581 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1582 | if (ret) | |
1583 | return ret; | |
1584 | if (INTEL_INFO(dev)->gen == 6) | |
1585 | seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE)); | |
1586 | ||
a2c7f6fd | 1587 | for_each_ring(ring, dev_priv, i) { |
3cf17fc5 DV |
1588 | seq_printf(m, "%s\n", ring->name); |
1589 | if (INTEL_INFO(dev)->gen == 7) | |
1590 | seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring))); | |
1591 | seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring))); | |
1592 | seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring))); | |
1593 | seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring))); | |
1594 | } | |
1595 | if (dev_priv->mm.aliasing_ppgtt) { | |
1596 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
1597 | ||
267f0c90 | 1598 | seq_puts(m, "aliasing PPGTT:\n"); |
3cf17fc5 DV |
1599 | seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset); |
1600 | } | |
1601 | seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK)); | |
1602 | mutex_unlock(&dev->struct_mutex); | |
1603 | ||
1604 | return 0; | |
1605 | } | |
1606 | ||
57f350b6 JB |
1607 | static int i915_dpio_info(struct seq_file *m, void *data) |
1608 | { | |
1609 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1610 | struct drm_device *dev = node->minor->dev; | |
1611 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1612 | int ret; | |
1613 | ||
1614 | ||
1615 | if (!IS_VALLEYVIEW(dev)) { | |
267f0c90 | 1616 | seq_puts(m, "unsupported\n"); |
57f350b6 JB |
1617 | return 0; |
1618 | } | |
1619 | ||
09153000 | 1620 | ret = mutex_lock_interruptible(&dev_priv->dpio_lock); |
57f350b6 JB |
1621 | if (ret) |
1622 | return ret; | |
1623 | ||
1624 | seq_printf(m, "DPIO_CTL: 0x%08x\n", I915_READ(DPIO_CTL)); | |
1625 | ||
1626 | seq_printf(m, "DPIO_DIV_A: 0x%08x\n", | |
5e69f97f | 1627 | vlv_dpio_read(dev_priv, PIPE_A, _DPIO_DIV_A)); |
57f350b6 | 1628 | seq_printf(m, "DPIO_DIV_B: 0x%08x\n", |
5e69f97f | 1629 | vlv_dpio_read(dev_priv, PIPE_A, _DPIO_DIV_B)); |
57f350b6 JB |
1630 | |
1631 | seq_printf(m, "DPIO_REFSFR_A: 0x%08x\n", | |
5e69f97f | 1632 | vlv_dpio_read(dev_priv, PIPE_A, _DPIO_REFSFR_A)); |
57f350b6 | 1633 | seq_printf(m, "DPIO_REFSFR_B: 0x%08x\n", |
5e69f97f | 1634 | vlv_dpio_read(dev_priv, PIPE_A, _DPIO_REFSFR_B)); |
57f350b6 JB |
1635 | |
1636 | seq_printf(m, "DPIO_CORE_CLK_A: 0x%08x\n", | |
5e69f97f | 1637 | vlv_dpio_read(dev_priv, PIPE_A, _DPIO_CORE_CLK_A)); |
57f350b6 | 1638 | seq_printf(m, "DPIO_CORE_CLK_B: 0x%08x\n", |
5e69f97f | 1639 | vlv_dpio_read(dev_priv, PIPE_A, _DPIO_CORE_CLK_B)); |
57f350b6 | 1640 | |
4abb2c39 | 1641 | seq_printf(m, "DPIO_LPF_COEFF_A: 0x%08x\n", |
5e69f97f | 1642 | vlv_dpio_read(dev_priv, PIPE_A, _DPIO_LPF_COEFF_A)); |
4abb2c39 | 1643 | seq_printf(m, "DPIO_LPF_COEFF_B: 0x%08x\n", |
5e69f97f | 1644 | vlv_dpio_read(dev_priv, PIPE_A, _DPIO_LPF_COEFF_B)); |
57f350b6 JB |
1645 | |
1646 | seq_printf(m, "DPIO_FASTCLK_DISABLE: 0x%08x\n", | |
5e69f97f | 1647 | vlv_dpio_read(dev_priv, PIPE_A, DPIO_FASTCLK_DISABLE)); |
57f350b6 | 1648 | |
09153000 | 1649 | mutex_unlock(&dev_priv->dpio_lock); |
57f350b6 JB |
1650 | |
1651 | return 0; | |
1652 | } | |
1653 | ||
63573eb7 BW |
1654 | static int i915_llc(struct seq_file *m, void *data) |
1655 | { | |
1656 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1657 | struct drm_device *dev = node->minor->dev; | |
1658 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1659 | ||
1660 | /* Size calculation for LLC is a bit of a pain. Ignore for now. */ | |
1661 | seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev))); | |
1662 | seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size); | |
1663 | ||
1664 | return 0; | |
1665 | } | |
1666 | ||
e91fd8c6 RV |
1667 | static int i915_edp_psr_status(struct seq_file *m, void *data) |
1668 | { | |
1669 | struct drm_info_node *node = m->private; | |
1670 | struct drm_device *dev = node->minor->dev; | |
1671 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a031d709 RV |
1672 | u32 psrperf = 0; |
1673 | bool enabled = false; | |
e91fd8c6 | 1674 | |
a031d709 RV |
1675 | seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support)); |
1676 | seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok)); | |
e91fd8c6 | 1677 | |
a031d709 RV |
1678 | enabled = HAS_PSR(dev) && |
1679 | I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE; | |
1680 | seq_printf(m, "Enabled: %s\n", yesno(enabled)); | |
e91fd8c6 | 1681 | |
a031d709 RV |
1682 | if (HAS_PSR(dev)) |
1683 | psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) & | |
1684 | EDP_PSR_PERF_CNT_MASK; | |
1685 | seq_printf(m, "Performance_Counter: %u\n", psrperf); | |
e91fd8c6 RV |
1686 | |
1687 | return 0; | |
1688 | } | |
1689 | ||
ec013e7f JB |
1690 | static int i915_energy_uJ(struct seq_file *m, void *data) |
1691 | { | |
1692 | struct drm_info_node *node = m->private; | |
1693 | struct drm_device *dev = node->minor->dev; | |
1694 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1695 | u64 power; | |
1696 | u32 units; | |
1697 | ||
1698 | if (INTEL_INFO(dev)->gen < 6) | |
1699 | return -ENODEV; | |
1700 | ||
1701 | rdmsrl(MSR_RAPL_POWER_UNIT, power); | |
1702 | power = (power & 0x1f00) >> 8; | |
1703 | units = 1000000 / (1 << power); /* convert to uJ */ | |
1704 | power = I915_READ(MCH_SECP_NRG_STTS); | |
1705 | power *= units; | |
1706 | ||
1707 | seq_printf(m, "%llu", (long long unsigned)power); | |
371db66a PZ |
1708 | |
1709 | return 0; | |
1710 | } | |
1711 | ||
1712 | static int i915_pc8_status(struct seq_file *m, void *unused) | |
1713 | { | |
1714 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1715 | struct drm_device *dev = node->minor->dev; | |
1716 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1717 | ||
1718 | if (!IS_HASWELL(dev)) { | |
1719 | seq_puts(m, "not supported\n"); | |
1720 | return 0; | |
1721 | } | |
1722 | ||
1723 | mutex_lock(&dev_priv->pc8.lock); | |
1724 | seq_printf(m, "Requirements met: %s\n", | |
1725 | yesno(dev_priv->pc8.requirements_met)); | |
1726 | seq_printf(m, "GPU idle: %s\n", yesno(dev_priv->pc8.gpu_idle)); | |
1727 | seq_printf(m, "Disable count: %d\n", dev_priv->pc8.disable_count); | |
1728 | seq_printf(m, "IRQs disabled: %s\n", | |
1729 | yesno(dev_priv->pc8.irqs_disabled)); | |
1730 | seq_printf(m, "Enabled: %s\n", yesno(dev_priv->pc8.enabled)); | |
1731 | mutex_unlock(&dev_priv->pc8.lock); | |
1732 | ||
ec013e7f JB |
1733 | return 0; |
1734 | } | |
1735 | ||
8bf1e9f1 SH |
1736 | static int i915_pipe_crc(struct seq_file *m, void *data) |
1737 | { | |
1738 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1739 | struct drm_device *dev = node->minor->dev; | |
1740 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1741 | enum pipe pipe = (enum pipe)node->info_ent->data; | |
1742 | const struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; | |
1743 | int i; | |
1744 | int start; | |
1745 | ||
926321d5 DV |
1746 | if (dev_priv->pipe_crc[pipe].source == INTEL_PIPE_CRC_SOURCE_NONE) { |
1747 | seq_puts(m, "none\n"); | |
8bf1e9f1 SH |
1748 | return 0; |
1749 | } | |
1750 | ||
1751 | start = atomic_read(&pipe_crc->slot) + 1; | |
1752 | seq_puts(m, " timestamp CRC1 CRC2 CRC3 CRC4 CRC5\n"); | |
1753 | for (i = 0; i < INTEL_PIPE_CRC_ENTRIES_NR; i++) { | |
1754 | const struct intel_pipe_crc_entry *entry = | |
1755 | &pipe_crc->entries[(start + i) % | |
1756 | INTEL_PIPE_CRC_ENTRIES_NR]; | |
1757 | ||
1758 | seq_printf(m, "%12u %8x %8x %8x %8x %8x\n", entry->timestamp, | |
1759 | entry->crc[0], entry->crc[1], entry->crc[2], | |
1760 | entry->crc[3], entry->crc[4]); | |
1761 | } | |
1762 | ||
1763 | return 0; | |
1764 | } | |
1765 | ||
926321d5 DV |
1766 | static const char *pipe_crc_sources[] = { |
1767 | "none", | |
1768 | "plane1", | |
1769 | "plane2", | |
1770 | "pf", | |
1771 | }; | |
1772 | ||
1773 | static const char *pipe_crc_source_name(enum intel_pipe_crc_source source) | |
1774 | { | |
1775 | BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX); | |
1776 | return pipe_crc_sources[source]; | |
1777 | } | |
1778 | ||
1779 | static int pipe_crc_ctl_show(struct seq_file *m, void *data) | |
1780 | { | |
1781 | struct drm_device *dev = m->private; | |
1782 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1783 | int i; | |
1784 | ||
1785 | for (i = 0; i < I915_MAX_PIPES; i++) | |
1786 | seq_printf(m, "%c %s\n", pipe_name(i), | |
1787 | pipe_crc_source_name(dev_priv->pipe_crc[i].source)); | |
1788 | ||
1789 | return 0; | |
1790 | } | |
1791 | ||
1792 | static int pipe_crc_ctl_open(struct inode *inode, struct file *file) | |
1793 | { | |
1794 | struct drm_device *dev = inode->i_private; | |
1795 | ||
1796 | return single_open(file, pipe_crc_ctl_show, dev); | |
1797 | } | |
1798 | ||
1799 | static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe, | |
1800 | enum intel_pipe_crc_source source) | |
1801 | { | |
1802 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1803 | u32 val; | |
1804 | ||
1805 | ||
1806 | return -ENODEV; | |
1807 | ||
1808 | if (!IS_IVYBRIDGE(dev)) | |
1809 | return -ENODEV; | |
1810 | ||
1811 | dev_priv->pipe_crc[pipe].source = source; | |
1812 | ||
1813 | switch (source) { | |
1814 | case INTEL_PIPE_CRC_SOURCE_PLANE1: | |
1815 | val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB; | |
1816 | break; | |
1817 | case INTEL_PIPE_CRC_SOURCE_PLANE2: | |
1818 | val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB; | |
1819 | break; | |
1820 | case INTEL_PIPE_CRC_SOURCE_PF: | |
1821 | val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB; | |
1822 | break; | |
1823 | case INTEL_PIPE_CRC_SOURCE_NONE: | |
1824 | default: | |
1825 | val = 0; | |
1826 | break; | |
1827 | } | |
1828 | ||
1829 | I915_WRITE(PIPE_CRC_CTL(pipe), val); | |
1830 | POSTING_READ(PIPE_CRC_CTL(pipe)); | |
1831 | ||
1832 | return 0; | |
1833 | } | |
1834 | ||
1835 | /* | |
1836 | * Parse pipe CRC command strings: | |
1837 | * command: wsp* pipe wsp+ source wsp* | |
1838 | * pipe: (A | B | C) | |
1839 | * source: (none | plane1 | plane2 | pf) | |
1840 | * wsp: (#0x20 | #0x9 | #0xA)+ | |
1841 | * | |
1842 | * eg.: | |
1843 | * "A plane1" -> Start CRC computations on plane1 of pipe A | |
1844 | * "A none" -> Stop CRC | |
1845 | */ | |
1846 | static int pipe_crc_ctl_tokenize(char *buf, char *words[], int max_words) | |
1847 | { | |
1848 | int n_words = 0; | |
1849 | ||
1850 | while (*buf) { | |
1851 | char *end; | |
1852 | ||
1853 | /* skip leading white space */ | |
1854 | buf = skip_spaces(buf); | |
1855 | if (!*buf) | |
1856 | break; /* end of buffer */ | |
1857 | ||
1858 | /* find end of word */ | |
1859 | for (end = buf; *end && !isspace(*end); end++) | |
1860 | ; | |
1861 | ||
1862 | if (n_words == max_words) { | |
1863 | DRM_DEBUG_DRIVER("too many words, allowed <= %d\n", | |
1864 | max_words); | |
1865 | return -EINVAL; /* ran out of words[] before bytes */ | |
1866 | } | |
1867 | ||
1868 | if (*end) | |
1869 | *end++ = '\0'; | |
1870 | words[n_words++] = buf; | |
1871 | buf = end; | |
1872 | } | |
1873 | ||
1874 | return n_words; | |
1875 | } | |
1876 | ||
1877 | static int pipe_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe) | |
1878 | { | |
1879 | const char name = buf[0]; | |
1880 | ||
1881 | if (name < 'A' || name >= pipe_name(I915_MAX_PIPES)) | |
1882 | return -EINVAL; | |
1883 | ||
1884 | *pipe = name - 'A'; | |
1885 | ||
1886 | return 0; | |
1887 | } | |
1888 | ||
1889 | static int | |
1890 | pipe_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *source) | |
1891 | { | |
1892 | int i; | |
1893 | ||
1894 | for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++) | |
1895 | if (!strcmp(buf, pipe_crc_sources[i])) { | |
1896 | *source = i; | |
1897 | return 0; | |
1898 | } | |
1899 | ||
1900 | return -EINVAL; | |
1901 | } | |
1902 | ||
1903 | static int pipe_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len) | |
1904 | { | |
1905 | #define MAX_WORDS 2 | |
1906 | int n_words; | |
1907 | char *words[MAX_WORDS]; | |
1908 | enum pipe pipe; | |
1909 | enum intel_pipe_crc_source source; | |
1910 | ||
1911 | n_words = pipe_crc_ctl_tokenize(buf, words, MAX_WORDS); | |
1912 | if (n_words != 2) { | |
1913 | DRM_DEBUG_DRIVER("tokenize failed, a command is 2 words\n"); | |
1914 | return -EINVAL; | |
1915 | } | |
1916 | ||
1917 | if (pipe_crc_ctl_parse_pipe(words[0], &pipe) < 0) { | |
1918 | DRM_DEBUG_DRIVER("unknown pipe %s\n", words[0]); | |
1919 | return -EINVAL; | |
1920 | } | |
1921 | ||
1922 | if (pipe_crc_ctl_parse_source(words[1], &source) < 0) { | |
1923 | DRM_DEBUG_DRIVER("unknown source %s\n", words[1]); | |
1924 | return -EINVAL; | |
1925 | } | |
1926 | ||
1927 | return pipe_crc_set_source(dev, pipe, source); | |
1928 | } | |
1929 | ||
1930 | static ssize_t pipe_crc_ctl_write(struct file *file, const char __user *ubuf, | |
1931 | size_t len, loff_t *offp) | |
1932 | { | |
1933 | struct seq_file *m = file->private_data; | |
1934 | struct drm_device *dev = m->private; | |
1935 | char *tmpbuf; | |
1936 | int ret; | |
1937 | ||
1938 | if (len == 0) | |
1939 | return 0; | |
1940 | ||
1941 | if (len > PAGE_SIZE - 1) { | |
1942 | DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n", | |
1943 | PAGE_SIZE); | |
1944 | return -E2BIG; | |
1945 | } | |
1946 | ||
1947 | tmpbuf = kmalloc(len + 1, GFP_KERNEL); | |
1948 | if (!tmpbuf) | |
1949 | return -ENOMEM; | |
1950 | ||
1951 | if (copy_from_user(tmpbuf, ubuf, len)) { | |
1952 | ret = -EFAULT; | |
1953 | goto out; | |
1954 | } | |
1955 | tmpbuf[len] = '\0'; | |
1956 | ||
1957 | ret = pipe_crc_ctl_parse(dev, tmpbuf, len); | |
1958 | ||
1959 | out: | |
1960 | kfree(tmpbuf); | |
1961 | if (ret < 0) | |
1962 | return ret; | |
1963 | ||
1964 | *offp += len; | |
1965 | return len; | |
1966 | } | |
1967 | ||
1968 | static const struct file_operations i915_pipe_crc_ctl_fops = { | |
1969 | .owner = THIS_MODULE, | |
1970 | .open = pipe_crc_ctl_open, | |
1971 | .read = seq_read, | |
1972 | .llseek = seq_lseek, | |
1973 | .release = single_release, | |
1974 | .write = pipe_crc_ctl_write | |
1975 | }; | |
1976 | ||
647416f9 KC |
1977 | static int |
1978 | i915_wedged_get(void *data, u64 *val) | |
f3cd474b | 1979 | { |
647416f9 | 1980 | struct drm_device *dev = data; |
f3cd474b | 1981 | drm_i915_private_t *dev_priv = dev->dev_private; |
f3cd474b | 1982 | |
647416f9 | 1983 | *val = atomic_read(&dev_priv->gpu_error.reset_counter); |
f3cd474b | 1984 | |
647416f9 | 1985 | return 0; |
f3cd474b CW |
1986 | } |
1987 | ||
647416f9 KC |
1988 | static int |
1989 | i915_wedged_set(void *data, u64 val) | |
f3cd474b | 1990 | { |
647416f9 | 1991 | struct drm_device *dev = data; |
f3cd474b | 1992 | |
647416f9 | 1993 | DRM_INFO("Manually setting wedged to %llu\n", val); |
527f9e90 | 1994 | i915_handle_error(dev, val); |
f3cd474b | 1995 | |
647416f9 | 1996 | return 0; |
f3cd474b CW |
1997 | } |
1998 | ||
647416f9 KC |
1999 | DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops, |
2000 | i915_wedged_get, i915_wedged_set, | |
3a3b4f98 | 2001 | "%llu\n"); |
f3cd474b | 2002 | |
647416f9 KC |
2003 | static int |
2004 | i915_ring_stop_get(void *data, u64 *val) | |
e5eb3d63 | 2005 | { |
647416f9 | 2006 | struct drm_device *dev = data; |
e5eb3d63 | 2007 | drm_i915_private_t *dev_priv = dev->dev_private; |
e5eb3d63 | 2008 | |
647416f9 | 2009 | *val = dev_priv->gpu_error.stop_rings; |
e5eb3d63 | 2010 | |
647416f9 | 2011 | return 0; |
e5eb3d63 DV |
2012 | } |
2013 | ||
647416f9 KC |
2014 | static int |
2015 | i915_ring_stop_set(void *data, u64 val) | |
e5eb3d63 | 2016 | { |
647416f9 | 2017 | struct drm_device *dev = data; |
e5eb3d63 | 2018 | struct drm_i915_private *dev_priv = dev->dev_private; |
647416f9 | 2019 | int ret; |
e5eb3d63 | 2020 | |
647416f9 | 2021 | DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val); |
e5eb3d63 | 2022 | |
22bcfc6a DV |
2023 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
2024 | if (ret) | |
2025 | return ret; | |
2026 | ||
99584db3 | 2027 | dev_priv->gpu_error.stop_rings = val; |
e5eb3d63 DV |
2028 | mutex_unlock(&dev->struct_mutex); |
2029 | ||
647416f9 | 2030 | return 0; |
e5eb3d63 DV |
2031 | } |
2032 | ||
647416f9 KC |
2033 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops, |
2034 | i915_ring_stop_get, i915_ring_stop_set, | |
2035 | "0x%08llx\n"); | |
d5442303 | 2036 | |
094f9a54 CW |
2037 | static int |
2038 | i915_ring_missed_irq_get(void *data, u64 *val) | |
2039 | { | |
2040 | struct drm_device *dev = data; | |
2041 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2042 | ||
2043 | *val = dev_priv->gpu_error.missed_irq_rings; | |
2044 | return 0; | |
2045 | } | |
2046 | ||
2047 | static int | |
2048 | i915_ring_missed_irq_set(void *data, u64 val) | |
2049 | { | |
2050 | struct drm_device *dev = data; | |
2051 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2052 | int ret; | |
2053 | ||
2054 | /* Lock against concurrent debugfs callers */ | |
2055 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
2056 | if (ret) | |
2057 | return ret; | |
2058 | dev_priv->gpu_error.missed_irq_rings = val; | |
2059 | mutex_unlock(&dev->struct_mutex); | |
2060 | ||
2061 | return 0; | |
2062 | } | |
2063 | ||
2064 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops, | |
2065 | i915_ring_missed_irq_get, i915_ring_missed_irq_set, | |
2066 | "0x%08llx\n"); | |
2067 | ||
2068 | static int | |
2069 | i915_ring_test_irq_get(void *data, u64 *val) | |
2070 | { | |
2071 | struct drm_device *dev = data; | |
2072 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2073 | ||
2074 | *val = dev_priv->gpu_error.test_irq_rings; | |
2075 | ||
2076 | return 0; | |
2077 | } | |
2078 | ||
2079 | static int | |
2080 | i915_ring_test_irq_set(void *data, u64 val) | |
2081 | { | |
2082 | struct drm_device *dev = data; | |
2083 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2084 | int ret; | |
2085 | ||
2086 | DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val); | |
2087 | ||
2088 | /* Lock against concurrent debugfs callers */ | |
2089 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
2090 | if (ret) | |
2091 | return ret; | |
2092 | ||
2093 | dev_priv->gpu_error.test_irq_rings = val; | |
2094 | mutex_unlock(&dev->struct_mutex); | |
2095 | ||
2096 | return 0; | |
2097 | } | |
2098 | ||
2099 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops, | |
2100 | i915_ring_test_irq_get, i915_ring_test_irq_set, | |
2101 | "0x%08llx\n"); | |
2102 | ||
dd624afd CW |
2103 | #define DROP_UNBOUND 0x1 |
2104 | #define DROP_BOUND 0x2 | |
2105 | #define DROP_RETIRE 0x4 | |
2106 | #define DROP_ACTIVE 0x8 | |
2107 | #define DROP_ALL (DROP_UNBOUND | \ | |
2108 | DROP_BOUND | \ | |
2109 | DROP_RETIRE | \ | |
2110 | DROP_ACTIVE) | |
647416f9 KC |
2111 | static int |
2112 | i915_drop_caches_get(void *data, u64 *val) | |
dd624afd | 2113 | { |
647416f9 | 2114 | *val = DROP_ALL; |
dd624afd | 2115 | |
647416f9 | 2116 | return 0; |
dd624afd CW |
2117 | } |
2118 | ||
647416f9 KC |
2119 | static int |
2120 | i915_drop_caches_set(void *data, u64 val) | |
dd624afd | 2121 | { |
647416f9 | 2122 | struct drm_device *dev = data; |
dd624afd CW |
2123 | struct drm_i915_private *dev_priv = dev->dev_private; |
2124 | struct drm_i915_gem_object *obj, *next; | |
ca191b13 BW |
2125 | struct i915_address_space *vm; |
2126 | struct i915_vma *vma, *x; | |
647416f9 | 2127 | int ret; |
dd624afd | 2128 | |
647416f9 | 2129 | DRM_DEBUG_DRIVER("Dropping caches: 0x%08llx\n", val); |
dd624afd CW |
2130 | |
2131 | /* No need to check and wait for gpu resets, only libdrm auto-restarts | |
2132 | * on ioctls on -EAGAIN. */ | |
2133 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
2134 | if (ret) | |
2135 | return ret; | |
2136 | ||
2137 | if (val & DROP_ACTIVE) { | |
2138 | ret = i915_gpu_idle(dev); | |
2139 | if (ret) | |
2140 | goto unlock; | |
2141 | } | |
2142 | ||
2143 | if (val & (DROP_RETIRE | DROP_ACTIVE)) | |
2144 | i915_gem_retire_requests(dev); | |
2145 | ||
2146 | if (val & DROP_BOUND) { | |
ca191b13 BW |
2147 | list_for_each_entry(vm, &dev_priv->vm_list, global_link) { |
2148 | list_for_each_entry_safe(vma, x, &vm->inactive_list, | |
2149 | mm_list) { | |
2150 | if (vma->obj->pin_count) | |
2151 | continue; | |
2152 | ||
2153 | ret = i915_vma_unbind(vma); | |
2154 | if (ret) | |
2155 | goto unlock; | |
2156 | } | |
31a46c9c | 2157 | } |
dd624afd CW |
2158 | } |
2159 | ||
2160 | if (val & DROP_UNBOUND) { | |
35c20a60 BW |
2161 | list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list, |
2162 | global_list) | |
dd624afd CW |
2163 | if (obj->pages_pin_count == 0) { |
2164 | ret = i915_gem_object_put_pages(obj); | |
2165 | if (ret) | |
2166 | goto unlock; | |
2167 | } | |
2168 | } | |
2169 | ||
2170 | unlock: | |
2171 | mutex_unlock(&dev->struct_mutex); | |
2172 | ||
647416f9 | 2173 | return ret; |
dd624afd CW |
2174 | } |
2175 | ||
647416f9 KC |
2176 | DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops, |
2177 | i915_drop_caches_get, i915_drop_caches_set, | |
2178 | "0x%08llx\n"); | |
dd624afd | 2179 | |
647416f9 KC |
2180 | static int |
2181 | i915_max_freq_get(void *data, u64 *val) | |
358733e9 | 2182 | { |
647416f9 | 2183 | struct drm_device *dev = data; |
358733e9 | 2184 | drm_i915_private_t *dev_priv = dev->dev_private; |
647416f9 | 2185 | int ret; |
004777cb DV |
2186 | |
2187 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) | |
2188 | return -ENODEV; | |
2189 | ||
5c9669ce TR |
2190 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
2191 | ||
4fc688ce | 2192 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
2193 | if (ret) |
2194 | return ret; | |
358733e9 | 2195 | |
0a073b84 JB |
2196 | if (IS_VALLEYVIEW(dev)) |
2197 | *val = vlv_gpu_freq(dev_priv->mem_freq, | |
2198 | dev_priv->rps.max_delay); | |
2199 | else | |
2200 | *val = dev_priv->rps.max_delay * GT_FREQUENCY_MULTIPLIER; | |
4fc688ce | 2201 | mutex_unlock(&dev_priv->rps.hw_lock); |
358733e9 | 2202 | |
647416f9 | 2203 | return 0; |
358733e9 JB |
2204 | } |
2205 | ||
647416f9 KC |
2206 | static int |
2207 | i915_max_freq_set(void *data, u64 val) | |
358733e9 | 2208 | { |
647416f9 | 2209 | struct drm_device *dev = data; |
358733e9 | 2210 | struct drm_i915_private *dev_priv = dev->dev_private; |
647416f9 | 2211 | int ret; |
004777cb DV |
2212 | |
2213 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) | |
2214 | return -ENODEV; | |
358733e9 | 2215 | |
5c9669ce TR |
2216 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
2217 | ||
647416f9 | 2218 | DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val); |
358733e9 | 2219 | |
4fc688ce | 2220 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
2221 | if (ret) |
2222 | return ret; | |
2223 | ||
358733e9 JB |
2224 | /* |
2225 | * Turbo will still be enabled, but won't go above the set value. | |
2226 | */ | |
0a073b84 JB |
2227 | if (IS_VALLEYVIEW(dev)) { |
2228 | val = vlv_freq_opcode(dev_priv->mem_freq, val); | |
2229 | dev_priv->rps.max_delay = val; | |
2230 | gen6_set_rps(dev, val); | |
2231 | } else { | |
2232 | do_div(val, GT_FREQUENCY_MULTIPLIER); | |
2233 | dev_priv->rps.max_delay = val; | |
2234 | gen6_set_rps(dev, val); | |
2235 | } | |
2236 | ||
4fc688ce | 2237 | mutex_unlock(&dev_priv->rps.hw_lock); |
358733e9 | 2238 | |
647416f9 | 2239 | return 0; |
358733e9 JB |
2240 | } |
2241 | ||
647416f9 KC |
2242 | DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops, |
2243 | i915_max_freq_get, i915_max_freq_set, | |
3a3b4f98 | 2244 | "%llu\n"); |
358733e9 | 2245 | |
647416f9 KC |
2246 | static int |
2247 | i915_min_freq_get(void *data, u64 *val) | |
1523c310 | 2248 | { |
647416f9 | 2249 | struct drm_device *dev = data; |
1523c310 | 2250 | drm_i915_private_t *dev_priv = dev->dev_private; |
647416f9 | 2251 | int ret; |
004777cb DV |
2252 | |
2253 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) | |
2254 | return -ENODEV; | |
2255 | ||
5c9669ce TR |
2256 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
2257 | ||
4fc688ce | 2258 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
2259 | if (ret) |
2260 | return ret; | |
1523c310 | 2261 | |
0a073b84 JB |
2262 | if (IS_VALLEYVIEW(dev)) |
2263 | *val = vlv_gpu_freq(dev_priv->mem_freq, | |
2264 | dev_priv->rps.min_delay); | |
2265 | else | |
2266 | *val = dev_priv->rps.min_delay * GT_FREQUENCY_MULTIPLIER; | |
4fc688ce | 2267 | mutex_unlock(&dev_priv->rps.hw_lock); |
1523c310 | 2268 | |
647416f9 | 2269 | return 0; |
1523c310 JB |
2270 | } |
2271 | ||
647416f9 KC |
2272 | static int |
2273 | i915_min_freq_set(void *data, u64 val) | |
1523c310 | 2274 | { |
647416f9 | 2275 | struct drm_device *dev = data; |
1523c310 | 2276 | struct drm_i915_private *dev_priv = dev->dev_private; |
647416f9 | 2277 | int ret; |
004777cb DV |
2278 | |
2279 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) | |
2280 | return -ENODEV; | |
1523c310 | 2281 | |
5c9669ce TR |
2282 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
2283 | ||
647416f9 | 2284 | DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val); |
1523c310 | 2285 | |
4fc688ce | 2286 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
2287 | if (ret) |
2288 | return ret; | |
2289 | ||
1523c310 JB |
2290 | /* |
2291 | * Turbo will still be enabled, but won't go below the set value. | |
2292 | */ | |
0a073b84 JB |
2293 | if (IS_VALLEYVIEW(dev)) { |
2294 | val = vlv_freq_opcode(dev_priv->mem_freq, val); | |
2295 | dev_priv->rps.min_delay = val; | |
2296 | valleyview_set_rps(dev, val); | |
2297 | } else { | |
2298 | do_div(val, GT_FREQUENCY_MULTIPLIER); | |
2299 | dev_priv->rps.min_delay = val; | |
2300 | gen6_set_rps(dev, val); | |
2301 | } | |
4fc688ce | 2302 | mutex_unlock(&dev_priv->rps.hw_lock); |
1523c310 | 2303 | |
647416f9 | 2304 | return 0; |
1523c310 JB |
2305 | } |
2306 | ||
647416f9 KC |
2307 | DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops, |
2308 | i915_min_freq_get, i915_min_freq_set, | |
3a3b4f98 | 2309 | "%llu\n"); |
1523c310 | 2310 | |
647416f9 KC |
2311 | static int |
2312 | i915_cache_sharing_get(void *data, u64 *val) | |
07b7ddd9 | 2313 | { |
647416f9 | 2314 | struct drm_device *dev = data; |
07b7ddd9 | 2315 | drm_i915_private_t *dev_priv = dev->dev_private; |
07b7ddd9 | 2316 | u32 snpcr; |
647416f9 | 2317 | int ret; |
07b7ddd9 | 2318 | |
004777cb DV |
2319 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) |
2320 | return -ENODEV; | |
2321 | ||
22bcfc6a DV |
2322 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
2323 | if (ret) | |
2324 | return ret; | |
2325 | ||
07b7ddd9 JB |
2326 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); |
2327 | mutex_unlock(&dev_priv->dev->struct_mutex); | |
2328 | ||
647416f9 | 2329 | *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT; |
07b7ddd9 | 2330 | |
647416f9 | 2331 | return 0; |
07b7ddd9 JB |
2332 | } |
2333 | ||
647416f9 KC |
2334 | static int |
2335 | i915_cache_sharing_set(void *data, u64 val) | |
07b7ddd9 | 2336 | { |
647416f9 | 2337 | struct drm_device *dev = data; |
07b7ddd9 | 2338 | struct drm_i915_private *dev_priv = dev->dev_private; |
07b7ddd9 | 2339 | u32 snpcr; |
07b7ddd9 | 2340 | |
004777cb DV |
2341 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) |
2342 | return -ENODEV; | |
2343 | ||
647416f9 | 2344 | if (val > 3) |
07b7ddd9 JB |
2345 | return -EINVAL; |
2346 | ||
647416f9 | 2347 | DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val); |
07b7ddd9 JB |
2348 | |
2349 | /* Update the cache sharing policy here as well */ | |
2350 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); | |
2351 | snpcr &= ~GEN6_MBC_SNPCR_MASK; | |
2352 | snpcr |= (val << GEN6_MBC_SNPCR_SHIFT); | |
2353 | I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); | |
2354 | ||
647416f9 | 2355 | return 0; |
07b7ddd9 JB |
2356 | } |
2357 | ||
647416f9 KC |
2358 | DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops, |
2359 | i915_cache_sharing_get, i915_cache_sharing_set, | |
2360 | "%llu\n"); | |
07b7ddd9 | 2361 | |
f3cd474b CW |
2362 | /* As the drm_debugfs_init() routines are called before dev->dev_private is |
2363 | * allocated we need to hook into the minor for release. */ | |
2364 | static int | |
2365 | drm_add_fake_info_node(struct drm_minor *minor, | |
2366 | struct dentry *ent, | |
2367 | const void *key) | |
2368 | { | |
2369 | struct drm_info_node *node; | |
2370 | ||
b14c5679 | 2371 | node = kmalloc(sizeof(*node), GFP_KERNEL); |
f3cd474b CW |
2372 | if (node == NULL) { |
2373 | debugfs_remove(ent); | |
2374 | return -ENOMEM; | |
2375 | } | |
2376 | ||
2377 | node->minor = minor; | |
2378 | node->dent = ent; | |
2379 | node->info_ent = (void *) key; | |
b3e067c0 MS |
2380 | |
2381 | mutex_lock(&minor->debugfs_lock); | |
2382 | list_add(&node->list, &minor->debugfs_list); | |
2383 | mutex_unlock(&minor->debugfs_lock); | |
f3cd474b CW |
2384 | |
2385 | return 0; | |
2386 | } | |
2387 | ||
6d794d42 BW |
2388 | static int i915_forcewake_open(struct inode *inode, struct file *file) |
2389 | { | |
2390 | struct drm_device *dev = inode->i_private; | |
2391 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6d794d42 | 2392 | |
075edca4 | 2393 | if (INTEL_INFO(dev)->gen < 6) |
6d794d42 BW |
2394 | return 0; |
2395 | ||
6d794d42 | 2396 | gen6_gt_force_wake_get(dev_priv); |
6d794d42 BW |
2397 | |
2398 | return 0; | |
2399 | } | |
2400 | ||
c43b5634 | 2401 | static int i915_forcewake_release(struct inode *inode, struct file *file) |
6d794d42 BW |
2402 | { |
2403 | struct drm_device *dev = inode->i_private; | |
2404 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2405 | ||
075edca4 | 2406 | if (INTEL_INFO(dev)->gen < 6) |
6d794d42 BW |
2407 | return 0; |
2408 | ||
6d794d42 | 2409 | gen6_gt_force_wake_put(dev_priv); |
6d794d42 BW |
2410 | |
2411 | return 0; | |
2412 | } | |
2413 | ||
2414 | static const struct file_operations i915_forcewake_fops = { | |
2415 | .owner = THIS_MODULE, | |
2416 | .open = i915_forcewake_open, | |
2417 | .release = i915_forcewake_release, | |
2418 | }; | |
2419 | ||
2420 | static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor) | |
2421 | { | |
2422 | struct drm_device *dev = minor->dev; | |
2423 | struct dentry *ent; | |
2424 | ||
2425 | ent = debugfs_create_file("i915_forcewake_user", | |
8eb57294 | 2426 | S_IRUSR, |
6d794d42 BW |
2427 | root, dev, |
2428 | &i915_forcewake_fops); | |
2429 | if (IS_ERR(ent)) | |
2430 | return PTR_ERR(ent); | |
2431 | ||
8eb57294 | 2432 | return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops); |
6d794d42 BW |
2433 | } |
2434 | ||
6a9c308d DV |
2435 | static int i915_debugfs_create(struct dentry *root, |
2436 | struct drm_minor *minor, | |
2437 | const char *name, | |
2438 | const struct file_operations *fops) | |
07b7ddd9 JB |
2439 | { |
2440 | struct drm_device *dev = minor->dev; | |
2441 | struct dentry *ent; | |
2442 | ||
6a9c308d | 2443 | ent = debugfs_create_file(name, |
07b7ddd9 JB |
2444 | S_IRUGO | S_IWUSR, |
2445 | root, dev, | |
6a9c308d | 2446 | fops); |
07b7ddd9 JB |
2447 | if (IS_ERR(ent)) |
2448 | return PTR_ERR(ent); | |
2449 | ||
6a9c308d | 2450 | return drm_add_fake_info_node(minor, ent, fops); |
07b7ddd9 JB |
2451 | } |
2452 | ||
27c202ad | 2453 | static struct drm_info_list i915_debugfs_list[] = { |
311bd68e | 2454 | {"i915_capabilities", i915_capabilities, 0}, |
73aa808f | 2455 | {"i915_gem_objects", i915_gem_object_info, 0}, |
08c18323 | 2456 | {"i915_gem_gtt", i915_gem_gtt_info, 0}, |
1b50247a | 2457 | {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST}, |
433e12f7 | 2458 | {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST}, |
433e12f7 | 2459 | {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST}, |
6d2b8885 | 2460 | {"i915_gem_stolen", i915_gem_stolen_list_info }, |
4e5359cd | 2461 | {"i915_gem_pageflip", i915_gem_pageflip_info, 0}, |
2017263e BG |
2462 | {"i915_gem_request", i915_gem_request_info, 0}, |
2463 | {"i915_gem_seqno", i915_gem_seqno_info, 0}, | |
a6172a80 | 2464 | {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0}, |
2017263e | 2465 | {"i915_gem_interrupt", i915_interrupt_info, 0}, |
1ec14ad3 CW |
2466 | {"i915_gem_hws", i915_hws_info, 0, (void *)RCS}, |
2467 | {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS}, | |
2468 | {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS}, | |
9010ebfd | 2469 | {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS}, |
f97108d1 JB |
2470 | {"i915_rstdby_delays", i915_rstdby_delays, 0}, |
2471 | {"i915_cur_delayinfo", i915_cur_delayinfo, 0}, | |
2472 | {"i915_delayfreq_table", i915_delayfreq_table, 0}, | |
2473 | {"i915_inttoext_table", i915_inttoext_table, 0}, | |
2474 | {"i915_drpc_info", i915_drpc_info, 0}, | |
7648fa99 | 2475 | {"i915_emon_status", i915_emon_status, 0}, |
23b2f8bb | 2476 | {"i915_ring_freq_table", i915_ring_freq_table, 0}, |
7648fa99 | 2477 | {"i915_gfxec", i915_gfxec, 0}, |
b5e50c3f | 2478 | {"i915_fbc_status", i915_fbc_status, 0}, |
92d44621 | 2479 | {"i915_ips_status", i915_ips_status, 0}, |
4a9bef37 | 2480 | {"i915_sr_status", i915_sr_status, 0}, |
44834a67 | 2481 | {"i915_opregion", i915_opregion, 0}, |
37811fcc | 2482 | {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0}, |
e76d3630 | 2483 | {"i915_context_status", i915_context_status, 0}, |
6d794d42 | 2484 | {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0}, |
ea16a3cd | 2485 | {"i915_swizzle_info", i915_swizzle_info, 0}, |
3cf17fc5 | 2486 | {"i915_ppgtt_info", i915_ppgtt_info, 0}, |
57f350b6 | 2487 | {"i915_dpio", i915_dpio_info, 0}, |
63573eb7 | 2488 | {"i915_llc", i915_llc, 0}, |
e91fd8c6 | 2489 | {"i915_edp_psr_status", i915_edp_psr_status, 0}, |
ec013e7f | 2490 | {"i915_energy_uJ", i915_energy_uJ, 0}, |
371db66a | 2491 | {"i915_pc8_status", i915_pc8_status, 0}, |
8bf1e9f1 SH |
2492 | {"i915_pipe_A_crc", i915_pipe_crc, 0, (void *)PIPE_A}, |
2493 | {"i915_pipe_B_crc", i915_pipe_crc, 0, (void *)PIPE_B}, | |
2494 | {"i915_pipe_C_crc", i915_pipe_crc, 0, (void *)PIPE_C}, | |
2017263e | 2495 | }; |
27c202ad | 2496 | #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list) |
2017263e | 2497 | |
2b4bd0e0 | 2498 | static struct i915_debugfs_files { |
34b9674c DV |
2499 | const char *name; |
2500 | const struct file_operations *fops; | |
2501 | } i915_debugfs_files[] = { | |
2502 | {"i915_wedged", &i915_wedged_fops}, | |
2503 | {"i915_max_freq", &i915_max_freq_fops}, | |
2504 | {"i915_min_freq", &i915_min_freq_fops}, | |
2505 | {"i915_cache_sharing", &i915_cache_sharing_fops}, | |
2506 | {"i915_ring_stop", &i915_ring_stop_fops}, | |
094f9a54 CW |
2507 | {"i915_ring_missed_irq", &i915_ring_missed_irq_fops}, |
2508 | {"i915_ring_test_irq", &i915_ring_test_irq_fops}, | |
34b9674c DV |
2509 | {"i915_gem_drop_caches", &i915_drop_caches_fops}, |
2510 | {"i915_error_state", &i915_error_state_fops}, | |
2511 | {"i915_next_seqno", &i915_next_seqno_fops}, | |
926321d5 | 2512 | {"i915_pipe_crc_ctl", &i915_pipe_crc_ctl_fops}, |
34b9674c DV |
2513 | }; |
2514 | ||
27c202ad | 2515 | int i915_debugfs_init(struct drm_minor *minor) |
2017263e | 2516 | { |
34b9674c | 2517 | int ret, i; |
f3cd474b | 2518 | |
6d794d42 | 2519 | ret = i915_forcewake_create(minor->debugfs_root, minor); |
358733e9 JB |
2520 | if (ret) |
2521 | return ret; | |
6a9c308d | 2522 | |
34b9674c DV |
2523 | for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) { |
2524 | ret = i915_debugfs_create(minor->debugfs_root, minor, | |
2525 | i915_debugfs_files[i].name, | |
2526 | i915_debugfs_files[i].fops); | |
2527 | if (ret) | |
2528 | return ret; | |
2529 | } | |
40633219 | 2530 | |
27c202ad BG |
2531 | return drm_debugfs_create_files(i915_debugfs_list, |
2532 | I915_DEBUGFS_ENTRIES, | |
2017263e BG |
2533 | minor->debugfs_root, minor); |
2534 | } | |
2535 | ||
27c202ad | 2536 | void i915_debugfs_cleanup(struct drm_minor *minor) |
2017263e | 2537 | { |
34b9674c DV |
2538 | int i; |
2539 | ||
27c202ad BG |
2540 | drm_debugfs_remove_files(i915_debugfs_list, |
2541 | I915_DEBUGFS_ENTRIES, minor); | |
6d794d42 BW |
2542 | drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops, |
2543 | 1, minor); | |
34b9674c DV |
2544 | for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) { |
2545 | struct drm_info_list *info_list = | |
2546 | (struct drm_info_list *) i915_debugfs_files[i].fops; | |
2547 | ||
2548 | drm_debugfs_remove_files(info_list, 1, minor); | |
2549 | } | |
2017263e BG |
2550 | } |
2551 | ||
2552 | #endif /* CONFIG_DEBUG_FS */ |