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drm/i915: Remove irq-related FIXME in reset code
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_debugfs.c
CommitLineData
2017263e
BG		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 *
27 */
28
29#include <linux/seq_file.h>
b2c88f5b 30#include <linux/circ_buf.h>
926321d5 31#include <linux/ctype.h>
f3cd474b 32#include <linux/debugfs.h>
5a0e3ad6 33#include <linux/slab.h>
2d1a8a48 34#include <linux/export.h>
6d2b8885 35#include <linux/list_sort.h>
ec013e7f 36#include <asm/msr-index.h>
760285e7 37#include <drm/drmP.h>
4e5359cd 38#include "intel_drv.h"
e5c65260 39#include "intel_ringbuffer.h"
760285e7 40#include <drm/i915_drm.h>
2017263e
BG		 41#include "i915_drv.h"
42
f13d3f73 43enum {
69dc4987 44 ACTIVE_LIST,
f13d3f73 45 INACTIVE_LIST,
d21d5975 46 PINNED_LIST,
f13d3f73 47};
2017263e 48
70d39fe4
CW		 49static const char *yesno(int v)
50{
51 return v ? "yes" : "no";
52}
53
497666d8
DL		 54/* As the drm_debugfs_init() routines are called before dev->dev_private is
55 * allocated we need to hook into the minor for release. */
56static int
57drm_add_fake_info_node(struct drm_minor *minor,
58 struct dentry *ent,
59 const void *key)
60{
61 struct drm_info_node *node;
62
63 node = kmalloc(sizeof(*node), GFP_KERNEL);
64 if (node == NULL) {
65 debugfs_remove(ent);
66 return -ENOMEM;
67 }
68
69 node->minor = minor;
70 node->dent = ent;
71 node->info_ent = (void *) key;
72
73 mutex_lock(&minor->debugfs_lock);
74 list_add(&node->list, &minor->debugfs_list);
75 mutex_unlock(&minor->debugfs_lock);
76
77 return 0;
78}
79
70d39fe4
CW		 80static int i915_capabilities(struct seq_file *m, void *data)
81{
9f25d007 82 struct drm_info_node *node = m->private;
70d39fe4
CW		 83 struct drm_device *dev = node->minor->dev;
84 const struct intel_device_info *info = INTEL_INFO(dev);
85
86 seq_printf(m, "gen: %d\n", info->gen);
03d00ac5 87 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
79fc46df
DL		 88#define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
89#define SEP_SEMICOLON ;
90 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
91#undef PRINT_FLAG
92#undef SEP_SEMICOLON
70d39fe4
CW		 93
94 return 0;
95}
2017263e 96
05394f39 97static const char *get_pin_flag(struct drm_i915_gem_object *obj)
a6172a80 98{
4feb7659 99 if (i915_gem_obj_is_pinned(obj))
a6172a80
CW		 100 return "p";
101 else
102 return " ";
103}
104
05394f39 105static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
a6172a80 106{
0206e353
AJ		 107 switch (obj->tiling_mode) {
108 default:
109 case I915_TILING_NONE: return " ";
110 case I915_TILING_X: return "X";
111 case I915_TILING_Y: return "Y";
112 }
a6172a80
CW		 113}
114
1d693bcc
BW		 115static inline const char *get_global_flag(struct drm_i915_gem_object *obj)
116{
aff43766 117 return i915_gem_obj_to_ggtt(obj) ? "g" : " ";
1d693bcc
BW		 118}
119
37811fcc
CW		 120static void
121describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
122{
1d693bcc 123 struct i915_vma *vma;
d7f46fc4
BW		 124 int pin_count = 0;
125
20e28fba 126 seq_printf(m, "%pK: %s%s%s %8zdKiB %02x %02x %x %x %x%s%s%s",
37811fcc
CW		 127 &obj->base,
128 get_pin_flag(obj),
129 get_tiling_flag(obj),
1d693bcc 130 get_global_flag(obj),
a05a5862 131 obj->base.size / 1024,
37811fcc
CW		 132 obj->base.read_domains,
133 obj->base.write_domain,
97b2a6a1
JH		 134 i915_gem_request_get_seqno(obj->last_read_req),
135 i915_gem_request_get_seqno(obj->last_write_req),
136 i915_gem_request_get_seqno(obj->last_fenced_req),
0a4cd7c8 137 i915_cache_level_str(to_i915(obj->base.dev), obj->cache_level),
37811fcc
CW		 138 obj->dirty ? " dirty" : "",
139 obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
140 if (obj->base.name)
141 seq_printf(m, " (name: %d)", obj->base.name);
ba0635ff 142 list_for_each_entry(vma, &obj->vma_list, vma_link) {
d7f46fc4
BW		 143 if (vma->pin_count > 0)
144 pin_count++;
ba0635ff
DC		 145 }
146 seq_printf(m, " (pinned x %d)", pin_count);
cc98b413
CW		 147 if (obj->pin_display)
148 seq_printf(m, " (display)");
37811fcc
CW		 149 if (obj->fence_reg != I915_FENCE_REG_NONE)
150 seq_printf(m, " (fence: %d)", obj->fence_reg);
1d693bcc
BW		 151 list_for_each_entry(vma, &obj->vma_list, vma_link) {
152 if (!i915_is_ggtt(vma->vm))
153 seq_puts(m, " (pp");
154 else
155 seq_puts(m, " (g");
440fd528 156 seq_printf(m, "gtt offset: %08llx, size: %08llx, type: %u)",
fe14d5f4
TU		 157 vma->node.start, vma->node.size,
158 vma->ggtt_view.type);
1d693bcc 159 }
c1ad11fc 160 if (obj->stolen)
440fd528 161 seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
6299f992
CW		 162 if (obj->pin_mappable || obj->fault_mappable) {
163 char s[3], *t = s;
164 if (obj->pin_mappable)
165 *t++ = 'p';
166 if (obj->fault_mappable)
167 *t++ = 'f';
168 *t = '\0';
169 seq_printf(m, " (%s mappable)", s);
170 }
41c52415
JH		 171 if (obj->last_read_req != NULL)
172 seq_printf(m, " (%s)",
173 i915_gem_request_get_ring(obj->last_read_req)->name);
d5a81ef1
DV		 174 if (obj->frontbuffer_bits)
175 seq_printf(m, " (frontbuffer: 0x%03x)", obj->frontbuffer_bits);
37811fcc
CW		 176}
177
273497e5 178static void describe_ctx(struct seq_file *m, struct intel_context *ctx)
3ccfd19d 179{
ea0c76f8 180 seq_putc(m, ctx->legacy_hw_ctx.initialized ? 'I' : 'i');
3ccfd19d
BW		 181 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
182 seq_putc(m, ' ');
183}
184
433e12f7 185static int i915_gem_object_list_info(struct seq_file *m, void *data)
2017263e 186{
9f25d007 187 struct drm_info_node *node = m->private;
433e12f7
BG		 188 uintptr_t list = (uintptr_t) node->info_ent->data;
189 struct list_head *head;
2017263e 190 struct drm_device *dev = node->minor->dev;
5cef07e1
BW		 191 struct drm_i915_private *dev_priv = dev->dev_private;
192 struct i915_address_space *vm = &dev_priv->gtt.base;
ca191b13 193 struct i915_vma *vma;
8f2480fb
CW		 194 size_t total_obj_size, total_gtt_size;
195 int count, ret;
de227ef0
CW		 196
197 ret = mutex_lock_interruptible(&dev->struct_mutex);
198 if (ret)
199 return ret;
2017263e 200
ca191b13 201 /* FIXME: the user of this interface might want more than just GGTT */
433e12f7
BG		 202 switch (list) {
203 case ACTIVE_LIST:
267f0c90 204 seq_puts(m, "Active:\n");
5cef07e1 205 head = &vm->active_list;
433e12f7
BG		 206 break;
207 case INACTIVE_LIST:
267f0c90 208 seq_puts(m, "Inactive:\n");
5cef07e1 209 head = &vm->inactive_list;
433e12f7 210 break;
433e12f7 211 default:
de227ef0
CW		 212 mutex_unlock(&dev->struct_mutex);
213 return -EINVAL;
2017263e 214 }
2017263e 215
8f2480fb 216 total_obj_size = total_gtt_size = count = 0;
ca191b13
BW		 217 list_for_each_entry(vma, head, mm_list) {
218 seq_printf(m, " ");
219 describe_obj(m, vma->obj);
220 seq_printf(m, "\n");
221 total_obj_size += vma->obj->base.size;
222 total_gtt_size += vma->node.size;
8f2480fb 223 count++;
2017263e 224 }
de227ef0 225 mutex_unlock(&dev->struct_mutex);
5e118f41 226
8f2480fb
CW		 227 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
228 count, total_obj_size, total_gtt_size);
2017263e
BG		 229 return 0;
230}
231
6d2b8885
CW		 232static int obj_rank_by_stolen(void *priv,
233 struct list_head *A, struct list_head *B)
234{
235 struct drm_i915_gem_object *a =
b25cb2f8 236 container_of(A, struct drm_i915_gem_object, obj_exec_link);
6d2b8885 237 struct drm_i915_gem_object *b =
b25cb2f8 238 container_of(B, struct drm_i915_gem_object, obj_exec_link);
6d2b8885
CW		 239
240 return a->stolen->start - b->stolen->start;
241}
242
243static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
244{
9f25d007 245 struct drm_info_node *node = m->private;
6d2b8885
CW		 246 struct drm_device *dev = node->minor->dev;
247 struct drm_i915_private *dev_priv = dev->dev_private;
248 struct drm_i915_gem_object *obj;
249 size_t total_obj_size, total_gtt_size;
250 LIST_HEAD(stolen);
251 int count, ret;
252
253 ret = mutex_lock_interruptible(&dev->struct_mutex);
254 if (ret)
255 return ret;
256
257 total_obj_size = total_gtt_size = count = 0;
258 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
259 if (obj->stolen == NULL)
260 continue;
261
b25cb2f8 262 list_add(&obj->obj_exec_link, &stolen);
6d2b8885
CW		 263
264 total_obj_size += obj->base.size;
265 total_gtt_size += i915_gem_obj_ggtt_size(obj);
266 count++;
267 }
268 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
269 if (obj->stolen == NULL)
270 continue;
271
b25cb2f8 272 list_add(&obj->obj_exec_link, &stolen);
6d2b8885
CW		 273
274 total_obj_size += obj->base.size;
275 count++;
276 }
277 list_sort(NULL, &stolen, obj_rank_by_stolen);
278 seq_puts(m, "Stolen:\n");
279 while (!list_empty(&stolen)) {
b25cb2f8 280 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
6d2b8885
CW		 281 seq_puts(m, " ");
282 describe_obj(m, obj);
283 seq_putc(m, '\n');
b25cb2f8 284 list_del_init(&obj->obj_exec_link);
6d2b8885
CW		 285 }
286 mutex_unlock(&dev->struct_mutex);
287
288 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
289 count, total_obj_size, total_gtt_size);
290 return 0;
291}
292
6299f992
CW		 293#define count_objects(list, member) do { \
294 list_for_each_entry(obj, list, member) { \
f343c5f6 295 size += i915_gem_obj_ggtt_size(obj); \
6299f992
CW		 296 ++count; \
297 if (obj->map_and_fenceable) { \
f343c5f6 298 mappable_size += i915_gem_obj_ggtt_size(obj); \
6299f992
CW		 299 ++mappable_count; \
300 } \
301 } \
0206e353 302} while (0)
6299f992 303
2db8e9d6 304struct file_stats {
6313c204 305 struct drm_i915_file_private *file_priv;
2db8e9d6 306 int count;
c67a17e9
CW		 307 size_t total, unbound;
308 size_t global, shared;
309 size_t active, inactive;
2db8e9d6
CW		 310};
311
312static int per_file_stats(int id, void *ptr, void *data)
313{
314 struct drm_i915_gem_object *obj = ptr;
315 struct file_stats *stats = data;
6313c204 316 struct i915_vma *vma;
2db8e9d6
CW		 317
318 stats->count++;
319 stats->total += obj->base.size;
320
c67a17e9
CW		 321 if (obj->base.name || obj->base.dma_buf)
322 stats->shared += obj->base.size;
323
6313c204
CW		 324 if (USES_FULL_PPGTT(obj->base.dev)) {
325 list_for_each_entry(vma, &obj->vma_list, vma_link) {
326 struct i915_hw_ppgtt *ppgtt;
327
328 if (!drm_mm_node_allocated(&vma->node))
329 continue;
330
331 if (i915_is_ggtt(vma->vm)) {
332 stats->global += obj->base.size;
333 continue;
334 }
335
336 ppgtt = container_of(vma->vm, struct i915_hw_ppgtt, base);
4d884705 337 if (ppgtt->file_priv != stats->file_priv)
6313c204
CW		 338 continue;
339
41c52415 340 if (obj->active) /* XXX per-vma statistic */
6313c204
CW		 341 stats->active += obj->base.size;
342 else
343 stats->inactive += obj->base.size;
344
345 return 0;
346 }
2db8e9d6 347 } else {
6313c204
CW		 348 if (i915_gem_obj_ggtt_bound(obj)) {
349 stats->global += obj->base.size;
41c52415 350 if (obj->active)
6313c204
CW		 351 stats->active += obj->base.size;
352 else
353 stats->inactive += obj->base.size;
354 return 0;
355 }
2db8e9d6
CW		 356 }
357
6313c204
CW		 358 if (!list_empty(&obj->global_list))
359 stats->unbound += obj->base.size;
360
2db8e9d6
CW		 361 return 0;
362}
363
493018dc
BV		 364#define print_file_stats(m, name, stats) \
365 seq_printf(m, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu global, %zu shared, %zu unbound)\n", \
366 name, \
367 stats.count, \
368 stats.total, \
369 stats.active, \
370 stats.inactive, \
371 stats.global, \
372 stats.shared, \
373 stats.unbound)
374
375static void print_batch_pool_stats(struct seq_file *m,
376 struct drm_i915_private *dev_priv)
377{
378 struct drm_i915_gem_object *obj;
379 struct file_stats stats;
380
381 memset(&stats, 0, sizeof(stats));
382
383 list_for_each_entry(obj,
384 &dev_priv->mm.batch_pool.cache_list,
385 batch_pool_list)
386 per_file_stats(0, obj, &stats);
387
388 print_file_stats(m, "batch pool", stats);
389}
390
ca191b13
BW		 391#define count_vmas(list, member) do { \
392 list_for_each_entry(vma, list, member) { \
393 size += i915_gem_obj_ggtt_size(vma->obj); \
394 ++count; \
395 if (vma->obj->map_and_fenceable) { \
396 mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
397 ++mappable_count; \
398 } \
399 } \
400} while (0)
401
402static int i915_gem_object_info(struct seq_file *m, void* data)
73aa808f 403{
9f25d007 404 struct drm_info_node *node = m->private;
73aa808f
CW		 405 struct drm_device *dev = node->minor->dev;
406 struct drm_i915_private *dev_priv = dev->dev_private;
b7abb714
CW		 407 u32 count, mappable_count, purgeable_count;
408 size_t size, mappable_size, purgeable_size;
6299f992 409 struct drm_i915_gem_object *obj;
5cef07e1 410 struct i915_address_space *vm = &dev_priv->gtt.base;
2db8e9d6 411 struct drm_file *file;
ca191b13 412 struct i915_vma *vma;
73aa808f
CW		 413 int ret;
414
415 ret = mutex_lock_interruptible(&dev->struct_mutex);
416 if (ret)
417 return ret;
418
6299f992
CW		 419 seq_printf(m, "%u objects, %zu bytes\n",
420 dev_priv->mm.object_count,
421 dev_priv->mm.object_memory);
422
423 size = count = mappable_size = mappable_count = 0;
35c20a60 424 count_objects(&dev_priv->mm.bound_list, global_list);
6299f992
CW		 425 seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n",
426 count, mappable_count, size, mappable_size);
427
428 size = count = mappable_size = mappable_count = 0;
ca191b13 429 count_vmas(&vm->active_list, mm_list);
6299f992
CW		 430 seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n",
431 count, mappable_count, size, mappable_size);
432
6299f992 433 size = count = mappable_size = mappable_count = 0;
ca191b13 434 count_vmas(&vm->inactive_list, mm_list);
6299f992
CW		 435 seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n",
436 count, mappable_count, size, mappable_size);
437
b7abb714 438 size = count = purgeable_size = purgeable_count = 0;
35c20a60 439 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
6c085a72 440 size += obj->base.size, ++count;
b7abb714
CW		 441 if (obj->madv == I915_MADV_DONTNEED)
442 purgeable_size += obj->base.size, ++purgeable_count;
443 }
6c085a72
CW		 444 seq_printf(m, "%u unbound objects, %zu bytes\n", count, size);
445
6299f992 446 size = count = mappable_size = mappable_count = 0;
35c20a60 447 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
6299f992 448 if (obj->fault_mappable) {
f343c5f6 449 size += i915_gem_obj_ggtt_size(obj);
6299f992
CW		 450 ++count;
451 }
452 if (obj->pin_mappable) {
f343c5f6 453 mappable_size += i915_gem_obj_ggtt_size(obj);
6299f992
CW		 454 ++mappable_count;
455 }
b7abb714
CW		 456 if (obj->madv == I915_MADV_DONTNEED) {
457 purgeable_size += obj->base.size;
458 ++purgeable_count;
459 }
6299f992 460 }
b7abb714
CW		 461 seq_printf(m, "%u purgeable objects, %zu bytes\n",
462 purgeable_count, purgeable_size);
6299f992
CW		 463 seq_printf(m, "%u pinned mappable objects, %zu bytes\n",
464 mappable_count, mappable_size);
465 seq_printf(m, "%u fault mappable objects, %zu bytes\n",
466 count, size);
467
93d18799 468 seq_printf(m, "%zu [%lu] gtt total\n",
853ba5d2
BW		 469 dev_priv->gtt.base.total,
470 dev_priv->gtt.mappable_end - dev_priv->gtt.base.start);
73aa808f 471
493018dc
BV		 472 seq_putc(m, '\n');
473 print_batch_pool_stats(m, dev_priv);
474
267f0c90 475 seq_putc(m, '\n');
2db8e9d6
CW		 476 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
477 struct file_stats stats;
3ec2f427 478 struct task_struct *task;
2db8e9d6
CW		 479
480 memset(&stats, 0, sizeof(stats));
6313c204 481 stats.file_priv = file->driver_priv;
5b5ffff0 482 spin_lock(&file->table_lock);
2db8e9d6 483 idr_for_each(&file->object_idr, per_file_stats, &stats);
5b5ffff0 484 spin_unlock(&file->table_lock);
3ec2f427
TH		 485 /*
486 * Although we have a valid reference on file->pid, that does
487 * not guarantee that the task_struct who called get_pid() is
488 * still alive (e.g. get_pid(current) => fork() => exit()).
489 * Therefore, we need to protect this ->comm access using RCU.
490 */
491 rcu_read_lock();
492 task = pid_task(file->pid, PIDTYPE_PID);
493018dc 493 print_file_stats(m, task ? task->comm : "<unknown>", stats);
3ec2f427 494 rcu_read_unlock();
2db8e9d6
CW		 495 }
496
73aa808f
CW		 497 mutex_unlock(&dev->struct_mutex);
498
499 return 0;
500}
501
aee56cff 502static int i915_gem_gtt_info(struct seq_file *m, void *data)
08c18323 503{
9f25d007 504 struct drm_info_node *node = m->private;
08c18323 505 struct drm_device *dev = node->minor->dev;
1b50247a 506 uintptr_t list = (uintptr_t) node->info_ent->data;
08c18323
CW		 507 struct drm_i915_private *dev_priv = dev->dev_private;
508 struct drm_i915_gem_object *obj;
509 size_t total_obj_size, total_gtt_size;
510 int count, ret;
511
512 ret = mutex_lock_interruptible(&dev->struct_mutex);
513 if (ret)
514 return ret;
515
516 total_obj_size = total_gtt_size = count = 0;
35c20a60 517 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
d7f46fc4 518 if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj))
1b50247a
CW		 519 continue;
520
267f0c90 521 seq_puts(m, " ");
08c18323 522 describe_obj(m, obj);
267f0c90 523 seq_putc(m, '\n');
08c18323 524 total_obj_size += obj->base.size;
f343c5f6 525 total_gtt_size += i915_gem_obj_ggtt_size(obj);
08c18323
CW		 526 count++;
527 }
528
529 mutex_unlock(&dev->struct_mutex);
530
531 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
532 count, total_obj_size, total_gtt_size);
533
534 return 0;
535}
536
4e5359cd
SF		 537static int i915_gem_pageflip_info(struct seq_file *m, void *data)
538{
9f25d007 539 struct drm_info_node *node = m->private;
4e5359cd 540 struct drm_device *dev = node->minor->dev;
d6bbafa1 541 struct drm_i915_private *dev_priv = dev->dev_private;
4e5359cd 542 struct intel_crtc *crtc;
8a270ebf
DV		 543 int ret;
544
545 ret = mutex_lock_interruptible(&dev->struct_mutex);
546 if (ret)
547 return ret;
4e5359cd 548
d3fcc808 549 for_each_intel_crtc(dev, crtc) {
9db4a9c7
JB		 550 const char pipe = pipe_name(crtc->pipe);
551 const char plane = plane_name(crtc->plane);
4e5359cd
SF		 552 struct intel_unpin_work *work;
553
5e2d7afc 554 spin_lock_irq(&dev->event_lock);
4e5359cd
SF		 555 work = crtc->unpin_work;
556 if (work == NULL) {
9db4a9c7 557 seq_printf(m, "No flip due on pipe %c (plane %c)\n",
4e5359cd
SF		 558 pipe, plane);
559 } else {
d6bbafa1
CW		 560 u32 addr;
561
e7d841ca 562 if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9db4a9c7 563 seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
4e5359cd
SF		 564 pipe, plane);
565 } else {
9db4a9c7 566 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
4e5359cd
SF		 567 pipe, plane);
568 }
3a8a946e
DV		 569 if (work->flip_queued_req) {
570 struct intel_engine_cs *ring =
571 i915_gem_request_get_ring(work->flip_queued_req);
572
20e28fba 573 seq_printf(m, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n",
3a8a946e 574 ring->name,
f06cc1b9 575 i915_gem_request_get_seqno(work->flip_queued_req),
d6bbafa1 576 dev_priv->next_seqno,
3a8a946e 577 ring->get_seqno(ring, true),
1b5a433a 578 i915_gem_request_completed(work->flip_queued_req, true));
d6bbafa1
CW		 579 } else
580 seq_printf(m, "Flip not associated with any ring\n");
581 seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
582 work->flip_queued_vblank,
583 work->flip_ready_vblank,
1e3feefd 584 drm_crtc_vblank_count(&crtc->base));
4e5359cd 585 if (work->enable_stall_check)
267f0c90 586 seq_puts(m, "Stall check enabled, ");
4e5359cd 587 else
267f0c90 588 seq_puts(m, "Stall check waiting for page flip ioctl, ");
e7d841ca 589 seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
4e5359cd 590
d6bbafa1
CW		 591 if (INTEL_INFO(dev)->gen >= 4)
592 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane)));
593 else
594 addr = I915_READ(DSPADDR(crtc->plane));
595 seq_printf(m, "Current scanout address 0x%08x\n", addr);
596
4e5359cd 597 if (work->pending_flip_obj) {
d6bbafa1
CW		 598 seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset);
599 seq_printf(m, "MMIO update completed? %d\n", addr == work->gtt_offset);
4e5359cd
SF		 600 }
601 }
5e2d7afc 602 spin_unlock_irq(&dev->event_lock);
4e5359cd
SF		 603 }
604
8a270ebf
DV		 605 mutex_unlock(&dev->struct_mutex);
606
4e5359cd
SF		 607 return 0;
608}
609
493018dc
BV		 610static int i915_gem_batch_pool_info(struct seq_file *m, void *data)
611{
612 struct drm_info_node *node = m->private;
613 struct drm_device *dev = node->minor->dev;
614 struct drm_i915_private *dev_priv = dev->dev_private;
615 struct drm_i915_gem_object *obj;
616 int count = 0;
617 int ret;
618
619 ret = mutex_lock_interruptible(&dev->struct_mutex);
620 if (ret)
621 return ret;
622
623 seq_puts(m, "cache:\n");
624 list_for_each_entry(obj,
625 &dev_priv->mm.batch_pool.cache_list,
626 batch_pool_list) {
627 seq_puts(m, " ");
628 describe_obj(m, obj);
629 seq_putc(m, '\n');
630 count++;
631 }
632
633 seq_printf(m, "total: %d\n", count);
634
635 mutex_unlock(&dev->struct_mutex);
636
637 return 0;
638}
639
2017263e
BG		 640static int i915_gem_request_info(struct seq_file *m, void *data)
641{
9f25d007 642 struct drm_info_node *node = m->private;
2017263e 643 struct drm_device *dev = node->minor->dev;
e277a1f8 644 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 645 struct intel_engine_cs *ring;
2017263e 646 struct drm_i915_gem_request *gem_request;
a2c7f6fd 647 int ret, count, i;
de227ef0
CW		 648
649 ret = mutex_lock_interruptible(&dev->struct_mutex);
650 if (ret)
651 return ret;
2017263e 652
c2c347a9 653 count = 0;
a2c7f6fd
CW		 654 for_each_ring(ring, dev_priv, i) {
655 if (list_empty(&ring->request_list))
656 continue;
657
658 seq_printf(m, "%s requests:\n", ring->name);
c2c347a9 659 list_for_each_entry(gem_request,
a2c7f6fd 660 &ring->request_list,
c2c347a9 661 list) {
20e28fba 662 seq_printf(m, " %x @ %d\n",
c2c347a9
CW		 663 gem_request->seqno,
664 (int) (jiffies - gem_request->emitted_jiffies));
665 }
666 count++;
2017263e 667 }
de227ef0
CW		 668 mutex_unlock(&dev->struct_mutex);
669
c2c347a9 670 if (count == 0)
267f0c90 671 seq_puts(m, "No requests\n");
c2c347a9 672
2017263e
BG		 673 return 0;
674}
675
b2223497 676static void i915_ring_seqno_info(struct seq_file *m,
a4872ba6 677 struct intel_engine_cs *ring)
b2223497
CW		 678{
679 if (ring->get_seqno) {
20e28fba 680 seq_printf(m, "Current sequence (%s): %x\n",
b2eadbc8 681 ring->name, ring->get_seqno(ring, false));
b2223497
CW		 682 }
683}
684
2017263e
BG		 685static int i915_gem_seqno_info(struct seq_file *m, void *data)
686{
9f25d007 687 struct drm_info_node *node = m->private;
2017263e 688 struct drm_device *dev = node->minor->dev;
e277a1f8 689 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 690 struct intel_engine_cs *ring;
1ec14ad3 691 int ret, i;
de227ef0
CW		 692
693 ret = mutex_lock_interruptible(&dev->struct_mutex);
694 if (ret)
695 return ret;
c8c8fb33 696 intel_runtime_pm_get(dev_priv);
2017263e 697
a2c7f6fd
CW		 698 for_each_ring(ring, dev_priv, i)
699 i915_ring_seqno_info(m, ring);
de227ef0 700
c8c8fb33 701 intel_runtime_pm_put(dev_priv);
de227ef0
CW		 702 mutex_unlock(&dev->struct_mutex);
703
2017263e
BG		 704 return 0;
705}
706
707
708static int i915_interrupt_info(struct seq_file *m, void *data)
709{
9f25d007 710 struct drm_info_node *node = m->private;
2017263e 711 struct drm_device *dev = node->minor->dev;
e277a1f8 712 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 713 struct intel_engine_cs *ring;
9db4a9c7 714 int ret, i, pipe;
de227ef0
CW		 715
716 ret = mutex_lock_interruptible(&dev->struct_mutex);
717 if (ret)
718 return ret;
c8c8fb33 719 intel_runtime_pm_get(dev_priv);
2017263e 720
74e1ca8c 721 if (IS_CHERRYVIEW(dev)) {
74e1ca8c
VS		 722 seq_printf(m, "Master Interrupt Control:\t%08x\n",
723 I915_READ(GEN8_MASTER_IRQ));
724
725 seq_printf(m, "Display IER:\t%08x\n",
726 I915_READ(VLV_IER));
727 seq_printf(m, "Display IIR:\t%08x\n",
728 I915_READ(VLV_IIR));
729 seq_printf(m, "Display IIR_RW:\t%08x\n",
730 I915_READ(VLV_IIR_RW));
731 seq_printf(m, "Display IMR:\t%08x\n",
732 I915_READ(VLV_IMR));
055e393f 733 for_each_pipe(dev_priv, pipe)
74e1ca8c
VS		 734 seq_printf(m, "Pipe %c stat:\t%08x\n",
735 pipe_name(pipe),
736 I915_READ(PIPESTAT(pipe)));
737
738 seq_printf(m, "Port hotplug:\t%08x\n",
739 I915_READ(PORT_HOTPLUG_EN));
740 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
741 I915_READ(VLV_DPFLIPSTAT));
742 seq_printf(m, "DPINVGTT:\t%08x\n",
743 I915_READ(DPINVGTT));
744
745 for (i = 0; i < 4; i++) {
746 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
747 i, I915_READ(GEN8_GT_IMR(i)));
748 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
749 i, I915_READ(GEN8_GT_IIR(i)));
750 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
751 i, I915_READ(GEN8_GT_IER(i)));
752 }
753
754 seq_printf(m, "PCU interrupt mask:\t%08x\n",
755 I915_READ(GEN8_PCU_IMR));
756 seq_printf(m, "PCU interrupt identity:\t%08x\n",
757 I915_READ(GEN8_PCU_IIR));
758 seq_printf(m, "PCU interrupt enable:\t%08x\n",
759 I915_READ(GEN8_PCU_IER));
760 } else if (INTEL_INFO(dev)->gen >= 8) {
a123f157
BW		 761 seq_printf(m, "Master Interrupt Control:\t%08x\n",
762 I915_READ(GEN8_MASTER_IRQ));
763
764 for (i = 0; i < 4; i++) {
765 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
766 i, I915_READ(GEN8_GT_IMR(i)));
767 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
768 i, I915_READ(GEN8_GT_IIR(i)));
769 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
770 i, I915_READ(GEN8_GT_IER(i)));
771 }
772
055e393f 773 for_each_pipe(dev_priv, pipe) {
f458ebbc 774 if (!intel_display_power_is_enabled(dev_priv,
22c59960
PZ		 775 POWER_DOMAIN_PIPE(pipe))) {
776 seq_printf(m, "Pipe %c power disabled\n",
777 pipe_name(pipe));
778 continue;
779 }
a123f157 780 seq_printf(m, "Pipe %c IMR:\t%08x\n",
07d27e20
DL		 781 pipe_name(pipe),
782 I915_READ(GEN8_DE_PIPE_IMR(pipe)));
a123f157 783 seq_printf(m, "Pipe %c IIR:\t%08x\n",
07d27e20
DL		 784 pipe_name(pipe),
785 I915_READ(GEN8_DE_PIPE_IIR(pipe)));
a123f157 786 seq_printf(m, "Pipe %c IER:\t%08x\n",
07d27e20
DL		 787 pipe_name(pipe),
788 I915_READ(GEN8_DE_PIPE_IER(pipe)));
a123f157
BW		 789 }
790
791 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
792 I915_READ(GEN8_DE_PORT_IMR));
793 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
794 I915_READ(GEN8_DE_PORT_IIR));
795 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
796 I915_READ(GEN8_DE_PORT_IER));
797
798 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
799 I915_READ(GEN8_DE_MISC_IMR));
800 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
801 I915_READ(GEN8_DE_MISC_IIR));
802 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
803 I915_READ(GEN8_DE_MISC_IER));
804
805 seq_printf(m, "PCU interrupt mask:\t%08x\n",
806 I915_READ(GEN8_PCU_IMR));
807 seq_printf(m, "PCU interrupt identity:\t%08x\n",
808 I915_READ(GEN8_PCU_IIR));
809 seq_printf(m, "PCU interrupt enable:\t%08x\n",
810 I915_READ(GEN8_PCU_IER));
811 } else if (IS_VALLEYVIEW(dev)) {
7e231dbe
JB		 812 seq_printf(m, "Display IER:\t%08x\n",
813 I915_READ(VLV_IER));
814 seq_printf(m, "Display IIR:\t%08x\n",
815 I915_READ(VLV_IIR));
816 seq_printf(m, "Display IIR_RW:\t%08x\n",
817 I915_READ(VLV_IIR_RW));
818 seq_printf(m, "Display IMR:\t%08x\n",
819 I915_READ(VLV_IMR));
055e393f 820 for_each_pipe(dev_priv, pipe)
7e231dbe
JB		 821 seq_printf(m, "Pipe %c stat:\t%08x\n",
822 pipe_name(pipe),
823 I915_READ(PIPESTAT(pipe)));
824
825 seq_printf(m, "Master IER:\t%08x\n",
826 I915_READ(VLV_MASTER_IER));
827
828 seq_printf(m, "Render IER:\t%08x\n",
829 I915_READ(GTIER));
830 seq_printf(m, "Render IIR:\t%08x\n",
831 I915_READ(GTIIR));
832 seq_printf(m, "Render IMR:\t%08x\n",
833 I915_READ(GTIMR));
834
835 seq_printf(m, "PM IER:\t\t%08x\n",
836 I915_READ(GEN6_PMIER));
837 seq_printf(m, "PM IIR:\t\t%08x\n",
838 I915_READ(GEN6_PMIIR));
839 seq_printf(m, "PM IMR:\t\t%08x\n",
840 I915_READ(GEN6_PMIMR));
841
842 seq_printf(m, "Port hotplug:\t%08x\n",
843 I915_READ(PORT_HOTPLUG_EN));
844 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
845 I915_READ(VLV_DPFLIPSTAT));
846 seq_printf(m, "DPINVGTT:\t%08x\n",
847 I915_READ(DPINVGTT));
848
849 } else if (!HAS_PCH_SPLIT(dev)) {
5f6a1695
ZW		 850 seq_printf(m, "Interrupt enable: %08x\n",
851 I915_READ(IER));
852 seq_printf(m, "Interrupt identity: %08x\n",
853 I915_READ(IIR));
854 seq_printf(m, "Interrupt mask: %08x\n",
855 I915_READ(IMR));
055e393f 856 for_each_pipe(dev_priv, pipe)
9db4a9c7
JB		 857 seq_printf(m, "Pipe %c stat: %08x\n",
858 pipe_name(pipe),
859 I915_READ(PIPESTAT(pipe)));
5f6a1695
ZW		 860 } else {
861 seq_printf(m, "North Display Interrupt enable: %08x\n",
862 I915_READ(DEIER));
863 seq_printf(m, "North Display Interrupt identity: %08x\n",
864 I915_READ(DEIIR));
865 seq_printf(m, "North Display Interrupt mask: %08x\n",
866 I915_READ(DEIMR));
867 seq_printf(m, "South Display Interrupt enable: %08x\n",
868 I915_READ(SDEIER));
869 seq_printf(m, "South Display Interrupt identity: %08x\n",
870 I915_READ(SDEIIR));
871 seq_printf(m, "South Display Interrupt mask: %08x\n",
872 I915_READ(SDEIMR));
873 seq_printf(m, "Graphics Interrupt enable: %08x\n",
874 I915_READ(GTIER));
875 seq_printf(m, "Graphics Interrupt identity: %08x\n",
876 I915_READ(GTIIR));
877 seq_printf(m, "Graphics Interrupt mask: %08x\n",
878 I915_READ(GTIMR));
879 }
a2c7f6fd 880 for_each_ring(ring, dev_priv, i) {
a123f157 881 if (INTEL_INFO(dev)->gen >= 6) {
a2c7f6fd
CW		 882 seq_printf(m,
883 "Graphics Interrupt mask (%s): %08x\n",
884 ring->name, I915_READ_IMR(ring));
9862e600 885 }
a2c7f6fd 886 i915_ring_seqno_info(m, ring);
9862e600 887 }
c8c8fb33 888 intel_runtime_pm_put(dev_priv);
de227ef0
CW		 889 mutex_unlock(&dev->struct_mutex);
890
2017263e
BG		 891 return 0;
892}
893
a6172a80
CW		 894static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
895{
9f25d007 896 struct drm_info_node *node = m->private;
a6172a80 897 struct drm_device *dev = node->minor->dev;
e277a1f8 898 struct drm_i915_private *dev_priv = dev->dev_private;
de227ef0
CW		 899 int i, ret;
900
901 ret = mutex_lock_interruptible(&dev->struct_mutex);
902 if (ret)
903 return ret;
a6172a80
CW		 904
905 seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
906 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
907 for (i = 0; i < dev_priv->num_fence_regs; i++) {
05394f39 908 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
a6172a80 909
6c085a72
CW		 910 seq_printf(m, "Fence %d, pin count = %d, object = ",
911 i, dev_priv->fence_regs[i].pin_count);
c2c347a9 912 if (obj == NULL)
267f0c90 913 seq_puts(m, "unused");
c2c347a9 914 else
05394f39 915 describe_obj(m, obj);
267f0c90 916 seq_putc(m, '\n');
a6172a80
CW		 917 }
918
05394f39 919 mutex_unlock(&dev->struct_mutex);
a6172a80
CW		 920 return 0;
921}
922
2017263e
BG		 923static int i915_hws_info(struct seq_file *m, void *data)
924{
9f25d007 925 struct drm_info_node *node = m->private;
2017263e 926 struct drm_device *dev = node->minor->dev;
e277a1f8 927 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 928 struct intel_engine_cs *ring;
1a240d4d 929 const u32 *hws;
4066c0ae
CW		 930 int i;
931
1ec14ad3 932 ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
1a240d4d 933 hws = ring->status_page.page_addr;
2017263e
BG		 934 if (hws == NULL)
935 return 0;
936
937 for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
938 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
939 i * 4,
940 hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
941 }
942 return 0;
943}
944
d5442303
DV		 945static ssize_t
946i915_error_state_write(struct file *filp,
947 const char __user *ubuf,
948 size_t cnt,
949 loff_t *ppos)
950{
edc3d884 951 struct i915_error_state_file_priv *error_priv = filp->private_data;
d5442303 952 struct drm_device *dev = error_priv->dev;
22bcfc6a 953 int ret;
d5442303
DV		 954
955 DRM_DEBUG_DRIVER("Resetting error state\n");
956
22bcfc6a
DV		 957 ret = mutex_lock_interruptible(&dev->struct_mutex);
958 if (ret)
959 return ret;
960
d5442303
DV		 961 i915_destroy_error_state(dev);
962 mutex_unlock(&dev->struct_mutex);
963
964 return cnt;
965}
966
967static int i915_error_state_open(struct inode *inode, struct file *file)
968{
969 struct drm_device *dev = inode->i_private;
d5442303 970 struct i915_error_state_file_priv *error_priv;
d5442303
DV		 971
972 error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
973 if (!error_priv)
974 return -ENOMEM;
975
976 error_priv->dev = dev;
977
95d5bfb3 978 i915_error_state_get(dev, error_priv);
d5442303 979
edc3d884
MK		 980 file->private_data = error_priv;
981
982 return 0;
d5442303
DV		 983}
984
985static int i915_error_state_release(struct inode *inode, struct file *file)
986{
edc3d884 987 struct i915_error_state_file_priv *error_priv = file->private_data;
d5442303 988
95d5bfb3 989 i915_error_state_put(error_priv);
d5442303
DV		 990 kfree(error_priv);
991
edc3d884
MK		 992 return 0;
993}
994
4dc955f7
MK		 995static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
996 size_t count, loff_t *pos)
997{
998 struct i915_error_state_file_priv *error_priv = file->private_data;
999 struct drm_i915_error_state_buf error_str;
1000 loff_t tmp_pos = 0;
1001 ssize_t ret_count = 0;
1002 int ret;
1003
0a4cd7c8 1004 ret = i915_error_state_buf_init(&error_str, to_i915(error_priv->dev), count, *pos);
4dc955f7
MK		 1005 if (ret)
1006 return ret;
edc3d884 1007
fc16b48b 1008 ret = i915_error_state_to_str(&error_str, error_priv);
edc3d884
MK		 1009 if (ret)
1010 goto out;
1011
edc3d884
MK		 1012 ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
1013 error_str.buf,
1014 error_str.bytes);
1015
1016 if (ret_count < 0)
1017 ret = ret_count;
1018 else
1019 *pos = error_str.start + ret_count;
1020out:
4dc955f7 1021 i915_error_state_buf_release(&error_str);
edc3d884 1022 return ret ?: ret_count;
d5442303
DV		 1023}
1024
1025static const struct file_operations i915_error_state_fops = {
1026 .owner = THIS_MODULE,
1027 .open = i915_error_state_open,
edc3d884 1028 .read = i915_error_state_read,
d5442303
DV		 1029 .write = i915_error_state_write,
1030 .llseek = default_llseek,
1031 .release = i915_error_state_release,
1032};
1033
647416f9
KC		 1034static int
1035i915_next_seqno_get(void *data, u64 *val)
40633219 1036{
647416f9 1037 struct drm_device *dev = data;
e277a1f8 1038 struct drm_i915_private *dev_priv = dev->dev_private;
40633219
MK		 1039 int ret;
1040
1041 ret = mutex_lock_interruptible(&dev->struct_mutex);
1042 if (ret)
1043 return ret;
1044
647416f9 1045 *val = dev_priv->next_seqno;
40633219
MK		 1046 mutex_unlock(&dev->struct_mutex);
1047
647416f9 1048 return 0;
40633219
MK		 1049}
1050
647416f9
KC		 1051static int
1052i915_next_seqno_set(void *data, u64 val)
1053{
1054 struct drm_device *dev = data;
40633219
MK		 1055 int ret;
1056
40633219
MK		 1057 ret = mutex_lock_interruptible(&dev->struct_mutex);
1058 if (ret)
1059 return ret;
1060
e94fbaa8 1061 ret = i915_gem_set_seqno(dev, val);
40633219
MK		 1062 mutex_unlock(&dev->struct_mutex);
1063
647416f9 1064 return ret;
40633219
MK		 1065}
1066
647416f9
KC		 1067DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
1068 i915_next_seqno_get, i915_next_seqno_set,
3a3b4f98 1069 "0x%llx\n");
40633219 1070
adb4bd12 1071static int i915_frequency_info(struct seq_file *m, void *unused)
f97108d1 1072{
9f25d007 1073 struct drm_info_node *node = m->private;
f97108d1 1074 struct drm_device *dev = node->minor->dev;
e277a1f8 1075 struct drm_i915_private *dev_priv = dev->dev_private;
c8c8fb33
PZ		 1076 int ret = 0;
1077
1078 intel_runtime_pm_get(dev_priv);
3b8d8d91 1079
5c9669ce
TR		 1080 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1081
3b8d8d91
JB		 1082 if (IS_GEN5(dev)) {
1083 u16 rgvswctl = I915_READ16(MEMSWCTL);
1084 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1085
1086 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1087 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1088 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1089 MEMSTAT_VID_SHIFT);
1090 seq_printf(m, "Current P-state: %d\n",
1091 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
daa3afb2
TR		 1092 } else if (IS_GEN6(dev) || (IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) ||
1093 IS_BROADWELL(dev)) {
3b8d8d91
JB		 1094 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1095 u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1096 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
0d8f9491 1097 u32 rpmodectl, rpinclimit, rpdeclimit;
8e8c06cd 1098 u32 rpstat, cagf, reqf;
ccab5c82
JB		 1099 u32 rpupei, rpcurup, rpprevup;
1100 u32 rpdownei, rpcurdown, rpprevdown;
9dd3c605 1101 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
3b8d8d91
JB		 1102 int max_freq;
1103
1104 /* RPSTAT1 is in the GT power well */
d1ebd816
BW		 1105 ret = mutex_lock_interruptible(&dev->struct_mutex);
1106 if (ret)
c8c8fb33 1107 goto out;
d1ebd816 1108
59bad947 1109 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
3b8d8d91 1110
8e8c06cd
CW		 1111 reqf = I915_READ(GEN6_RPNSWREQ);
1112 reqf &= ~GEN6_TURBO_DISABLE;
daa3afb2 1113 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8e8c06cd
CW		 1114 reqf >>= 24;
1115 else
1116 reqf >>= 25;
7c59a9c1 1117 reqf = intel_gpu_freq(dev_priv, reqf);
8e8c06cd 1118
0d8f9491
CW		 1119 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1120 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1121 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1122
ccab5c82
JB		 1123 rpstat = I915_READ(GEN6_RPSTAT1);
1124 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
1125 rpcurup = I915_READ(GEN6_RP_CUR_UP);
1126 rpprevup = I915_READ(GEN6_RP_PREV_UP);
1127 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
1128 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
1129 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
daa3afb2 1130 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
f82855d3
BW		 1131 cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1132 else
1133 cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
7c59a9c1 1134 cagf = intel_gpu_freq(dev_priv, cagf);
ccab5c82 1135
59bad947 1136 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
d1ebd816
BW		 1137 mutex_unlock(&dev->struct_mutex);
1138
9dd3c605
PZ		 1139 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1140 pm_ier = I915_READ(GEN6_PMIER);
1141 pm_imr = I915_READ(GEN6_PMIMR);
1142 pm_isr = I915_READ(GEN6_PMISR);
1143 pm_iir = I915_READ(GEN6_PMIIR);
1144 pm_mask = I915_READ(GEN6_PMINTRMSK);
1145 } else {
1146 pm_ier = I915_READ(GEN8_GT_IER(2));
1147 pm_imr = I915_READ(GEN8_GT_IMR(2));
1148 pm_isr = I915_READ(GEN8_GT_ISR(2));
1149 pm_iir = I915_READ(GEN8_GT_IIR(2));
1150 pm_mask = I915_READ(GEN6_PMINTRMSK);
1151 }
0d8f9491 1152 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
9dd3c605 1153 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
3b8d8d91 1154 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
3b8d8d91
JB		 1155 seq_printf(m, "Render p-state ratio: %d\n",
1156 (gt_perf_status & 0xff00) >> 8);
1157 seq_printf(m, "Render p-state VID: %d\n",
1158 gt_perf_status & 0xff);
1159 seq_printf(m, "Render p-state limit: %d\n",
1160 rp_state_limits & 0xff);
0d8f9491
CW		 1161 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1162 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1163 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1164 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
8e8c06cd 1165 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
f82855d3 1166 seq_printf(m, "CAGF: %dMHz\n", cagf);
ccab5c82
JB		 1167 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
1168 GEN6_CURICONT_MASK);
1169 seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
1170 GEN6_CURBSYTAVG_MASK);
1171 seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
1172 GEN6_CURBSYTAVG_MASK);
1173 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
1174 GEN6_CURIAVG_MASK);
1175 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
1176 GEN6_CURBSYTAVG_MASK);
1177 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
1178 GEN6_CURBSYTAVG_MASK);
3b8d8d91
JB		 1179
1180 max_freq = (rp_state_cap & 0xff0000) >> 16;
1181 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
7c59a9c1 1182 intel_gpu_freq(dev_priv, max_freq));
3b8d8d91
JB		 1183
1184 max_freq = (rp_state_cap & 0xff00) >> 8;
1185 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
7c59a9c1 1186 intel_gpu_freq(dev_priv, max_freq));
3b8d8d91
JB		 1187
1188 max_freq = rp_state_cap & 0xff;
1189 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
7c59a9c1 1190 intel_gpu_freq(dev_priv, max_freq));
31c77388
BW		 1191
1192 seq_printf(m, "Max overclocked frequency: %dMHz\n",
7c59a9c1 1193 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
0a073b84 1194 } else if (IS_VALLEYVIEW(dev)) {
03af2045 1195 u32 freq_sts;
0a073b84 1196
259bd5d4 1197 mutex_lock(&dev_priv->rps.hw_lock);
64936258 1198 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
0a073b84
JB		 1199 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1200 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1201
0a073b84 1202 seq_printf(m, "max GPU freq: %d MHz\n",
7c59a9c1 1203 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
0a073b84 1204
0a073b84 1205 seq_printf(m, "min GPU freq: %d MHz\n",
7c59a9c1 1206 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
03af2045 1207
7c59a9c1
VS		 1208 seq_printf(m,
1209 "efficient (RPe) frequency: %d MHz\n",
1210 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
0a073b84
JB		 1211
1212 seq_printf(m, "current GPU freq: %d MHz\n",
7c59a9c1 1213 intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
259bd5d4 1214 mutex_unlock(&dev_priv->rps.hw_lock);
3b8d8d91 1215 } else {
267f0c90 1216 seq_puts(m, "no P-state info available\n");
3b8d8d91 1217 }
f97108d1 1218
c8c8fb33
PZ		 1219out:
1220 intel_runtime_pm_put(dev_priv);
1221 return ret;
f97108d1
JB		 1222}
1223
f654449a
CW		 1224static int i915_hangcheck_info(struct seq_file *m, void *unused)
1225{
1226 struct drm_info_node *node = m->private;
ebbc7546
MK		 1227 struct drm_device *dev = node->minor->dev;
1228 struct drm_i915_private *dev_priv = dev->dev_private;
f654449a 1229 struct intel_engine_cs *ring;
ebbc7546
MK		 1230 u64 acthd[I915_NUM_RINGS];
1231 u32 seqno[I915_NUM_RINGS];
f654449a
CW		 1232 int i;
1233
1234 if (!i915.enable_hangcheck) {
1235 seq_printf(m, "Hangcheck disabled\n");
1236 return 0;
1237 }
1238
ebbc7546
MK		 1239 intel_runtime_pm_get(dev_priv);
1240
1241 for_each_ring(ring, dev_priv, i) {
1242 seqno[i] = ring->get_seqno(ring, false);
1243 acthd[i] = intel_ring_get_active_head(ring);
1244 }
1245
1246 intel_runtime_pm_put(dev_priv);
1247
f654449a
CW		 1248 if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) {
1249 seq_printf(m, "Hangcheck active, fires in %dms\n",
1250 jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires -
1251 jiffies));
1252 } else
1253 seq_printf(m, "Hangcheck inactive\n");
1254
1255 for_each_ring(ring, dev_priv, i) {
1256 seq_printf(m, "%s:\n", ring->name);
1257 seq_printf(m, "\tseqno = %x [current %x]\n",
ebbc7546 1258 ring->hangcheck.seqno, seqno[i]);
f654449a
CW		 1259 seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
1260 (long long)ring->hangcheck.acthd,
ebbc7546 1261 (long long)acthd[i]);
f654449a
CW		 1262 seq_printf(m, "\tmax ACTHD = 0x%08llx\n",
1263 (long long)ring->hangcheck.max_acthd);
ebbc7546
MK		 1264 seq_printf(m, "\tscore = %d\n", ring->hangcheck.score);
1265 seq_printf(m, "\taction = %d\n", ring->hangcheck.action);
f654449a
CW		 1266 }
1267
1268 return 0;
1269}
1270
4d85529d 1271static int ironlake_drpc_info(struct seq_file *m)
f97108d1 1272{
9f25d007 1273 struct drm_info_node *node = m->private;
f97108d1 1274 struct drm_device *dev = node->minor->dev;
e277a1f8 1275 struct drm_i915_private *dev_priv = dev->dev_private;
616fdb5a
BW		 1276 u32 rgvmodectl, rstdbyctl;
1277 u16 crstandvid;
1278 int ret;
1279
1280 ret = mutex_lock_interruptible(&dev->struct_mutex);
1281 if (ret)
1282 return ret;
c8c8fb33 1283 intel_runtime_pm_get(dev_priv);
616fdb5a
BW		 1284
1285 rgvmodectl = I915_READ(MEMMODECTL);
1286 rstdbyctl = I915_READ(RSTDBYCTL);
1287 crstandvid = I915_READ16(CRSTANDVID);
1288
c8c8fb33 1289 intel_runtime_pm_put(dev_priv);
616fdb5a 1290 mutex_unlock(&dev->struct_mutex);
f97108d1
JB		 1291
1292 seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
1293 "yes" : "no");
1294 seq_printf(m, "Boost freq: %d\n",
1295 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1296 MEMMODE_BOOST_FREQ_SHIFT);
1297 seq_printf(m, "HW control enabled: %s\n",
1298 rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");
1299 seq_printf(m, "SW control enabled: %s\n",
1300 rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");
1301 seq_printf(m, "Gated voltage change: %s\n",
1302 rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");
1303 seq_printf(m, "Starting frequency: P%d\n",
1304 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
7648fa99 1305 seq_printf(m, "Max P-state: P%d\n",
f97108d1 1306 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
7648fa99
JB		 1307 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1308 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1309 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1310 seq_printf(m, "Render standby enabled: %s\n",
1311 (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes");
267f0c90 1312 seq_puts(m, "Current RS state: ");
88271da3
JB		 1313 switch (rstdbyctl & RSX_STATUS_MASK) {
1314 case RSX_STATUS_ON:
267f0c90 1315 seq_puts(m, "on\n");
88271da3
JB		 1316 break;
1317 case RSX_STATUS_RC1:
267f0c90 1318 seq_puts(m, "RC1\n");
88271da3
JB		 1319 break;
1320 case RSX_STATUS_RC1E:
267f0c90 1321 seq_puts(m, "RC1E\n");
88271da3
JB		 1322 break;
1323 case RSX_STATUS_RS1:
267f0c90 1324 seq_puts(m, "RS1\n");
88271da3
JB		 1325 break;
1326 case RSX_STATUS_RS2:
267f0c90 1327 seq_puts(m, "RS2 (RC6)\n");
88271da3
JB		 1328 break;
1329 case RSX_STATUS_RS3:
267f0c90 1330 seq_puts(m, "RC3 (RC6+)\n");
88271da3
JB		 1331 break;
1332 default:
267f0c90 1333 seq_puts(m, "unknown\n");
88271da3
JB		 1334 break;
1335 }
f97108d1
JB		 1336
1337 return 0;
1338}
1339
f65367b5 1340static int i915_forcewake_domains(struct seq_file *m, void *data)
669ab5aa 1341{
b2cff0db
CW		 1342 struct drm_info_node *node = m->private;
1343 struct drm_device *dev = node->minor->dev;
1344 struct drm_i915_private *dev_priv = dev->dev_private;
1345 struct intel_uncore_forcewake_domain *fw_domain;
b2cff0db
CW		 1346 int i;
1347
1348 spin_lock_irq(&dev_priv->uncore.lock);
1349 for_each_fw_domain(fw_domain, dev_priv, i) {
1350 seq_printf(m, "%s.wake_count = %u\n",
05a2fb15 1351 intel_uncore_forcewake_domain_to_str(i),
b2cff0db
CW		 1352 fw_domain->wake_count);
1353 }
1354 spin_unlock_irq(&dev_priv->uncore.lock);
669ab5aa 1355
b2cff0db
CW		 1356 return 0;
1357}
1358
1359static int vlv_drpc_info(struct seq_file *m)
1360{
9f25d007 1361 struct drm_info_node *node = m->private;
669ab5aa
D		 1362 struct drm_device *dev = node->minor->dev;
1363 struct drm_i915_private *dev_priv = dev->dev_private;
6b312cd3 1364 u32 rpmodectl1, rcctl1, pw_status;
669ab5aa 1365
d46c0517
ID		 1366 intel_runtime_pm_get(dev_priv);
1367
6b312cd3 1368 pw_status = I915_READ(VLV_GTLC_PW_STATUS);
669ab5aa
D		 1369 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1370 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1371
d46c0517
ID		 1372 intel_runtime_pm_put(dev_priv);
1373
669ab5aa
D		 1374 seq_printf(m, "Video Turbo Mode: %s\n",
1375 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1376 seq_printf(m, "Turbo enabled: %s\n",
1377 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1378 seq_printf(m, "HW control enabled: %s\n",
1379 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1380 seq_printf(m, "SW control enabled: %s\n",
1381 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1382 GEN6_RP_MEDIA_SW_MODE));
1383 seq_printf(m, "RC6 Enabled: %s\n",
1384 yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1385 GEN6_RC_CTL_EI_MODE(1))));
1386 seq_printf(m, "Render Power Well: %s\n",
6b312cd3 1387 (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
669ab5aa 1388 seq_printf(m, "Media Power Well: %s\n",
6b312cd3 1389 (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
669ab5aa 1390
9cc19be5
ID		 1391 seq_printf(m, "Render RC6 residency since boot: %u\n",
1392 I915_READ(VLV_GT_RENDER_RC6));
1393 seq_printf(m, "Media RC6 residency since boot: %u\n",
1394 I915_READ(VLV_GT_MEDIA_RC6));
1395
f65367b5 1396 return i915_forcewake_domains(m, NULL);
669ab5aa
D		 1397}
1398
4d85529d
BW		 1399static int gen6_drpc_info(struct seq_file *m)
1400{
9f25d007 1401 struct drm_info_node *node = m->private;
4d85529d
BW		 1402 struct drm_device *dev = node->minor->dev;
1403 struct drm_i915_private *dev_priv = dev->dev_private;
ecd8faea 1404 u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
93b525dc 1405 unsigned forcewake_count;
aee56cff 1406 int count = 0, ret;
4d85529d
BW		 1407
1408 ret = mutex_lock_interruptible(&dev->struct_mutex);
1409 if (ret)
1410 return ret;
c8c8fb33 1411 intel_runtime_pm_get(dev_priv);
4d85529d 1412
907b28c5 1413 spin_lock_irq(&dev_priv->uncore.lock);
b2cff0db 1414 forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count;
907b28c5 1415 spin_unlock_irq(&dev_priv->uncore.lock);
93b525dc
DV		 1416
1417 if (forcewake_count) {
267f0c90
DL		 1418 seq_puts(m, "RC information inaccurate because somebody "
1419 "holds a forcewake reference \n");
4d85529d
BW		 1420 } else {
1421 /* NB: we cannot use forcewake, else we read the wrong values */
1422 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1423 udelay(10);
1424 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1425 }
1426
1427 gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS);
ed71f1b4 1428 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
4d85529d
BW		 1429
1430 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1431 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1432 mutex_unlock(&dev->struct_mutex);
44cbd338
BW		 1433 mutex_lock(&dev_priv->rps.hw_lock);
1434 sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1435 mutex_unlock(&dev_priv->rps.hw_lock);
4d85529d 1436
c8c8fb33
PZ		 1437 intel_runtime_pm_put(dev_priv);
1438
4d85529d
BW		 1439 seq_printf(m, "Video Turbo Mode: %s\n",
1440 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1441 seq_printf(m, "HW control enabled: %s\n",
1442 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1443 seq_printf(m, "SW control enabled: %s\n",
1444 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1445 GEN6_RP_MEDIA_SW_MODE));
fff24e21 1446 seq_printf(m, "RC1e Enabled: %s\n",
4d85529d
BW		 1447 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1448 seq_printf(m, "RC6 Enabled: %s\n",
1449 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1450 seq_printf(m, "Deep RC6 Enabled: %s\n",
1451 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1452 seq_printf(m, "Deepest RC6 Enabled: %s\n",
1453 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
267f0c90 1454 seq_puts(m, "Current RC state: ");
4d85529d
BW		 1455 switch (gt_core_status & GEN6_RCn_MASK) {
1456 case GEN6_RC0:
1457 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
267f0c90 1458 seq_puts(m, "Core Power Down\n");
4d85529d 1459 else
267f0c90 1460 seq_puts(m, "on\n");
4d85529d
BW		 1461 break;
1462 case GEN6_RC3:
267f0c90 1463 seq_puts(m, "RC3\n");
4d85529d
BW		 1464 break;
1465 case GEN6_RC6:
267f0c90 1466 seq_puts(m, "RC6\n");
4d85529d
BW		 1467 break;
1468 case GEN6_RC7:
267f0c90 1469 seq_puts(m, "RC7\n");
4d85529d
BW		 1470 break;
1471 default:
267f0c90 1472 seq_puts(m, "Unknown\n");
4d85529d
BW		 1473 break;
1474 }
1475
1476 seq_printf(m, "Core Power Down: %s\n",
1477 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
cce66a28
BW		 1478
1479 /* Not exactly sure what this is */
1480 seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1481 I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1482 seq_printf(m, "RC6 residency since boot: %u\n",
1483 I915_READ(GEN6_GT_GFX_RC6));
1484 seq_printf(m, "RC6+ residency since boot: %u\n",
1485 I915_READ(GEN6_GT_GFX_RC6p));
1486 seq_printf(m, "RC6++ residency since boot: %u\n",
1487 I915_READ(GEN6_GT_GFX_RC6pp));
1488
ecd8faea
BW		 1489 seq_printf(m, "RC6 voltage: %dmV\n",
1490 GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1491 seq_printf(m, "RC6+ voltage: %dmV\n",
1492 GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1493 seq_printf(m, "RC6++ voltage: %dmV\n",
1494 GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
4d85529d
BW		 1495 return 0;
1496}
1497
1498static int i915_drpc_info(struct seq_file *m, void *unused)
1499{
9f25d007 1500 struct drm_info_node *node = m->private;
4d85529d
BW		 1501 struct drm_device *dev = node->minor->dev;
1502
669ab5aa
D		 1503 if (IS_VALLEYVIEW(dev))
1504 return vlv_drpc_info(m);
ac66cf4b 1505 else if (INTEL_INFO(dev)->gen >= 6)
4d85529d
BW		 1506 return gen6_drpc_info(m);
1507 else
1508 return ironlake_drpc_info(m);
1509}
1510
b5e50c3f
JB		 1511static int i915_fbc_status(struct seq_file *m, void *unused)
1512{
9f25d007 1513 struct drm_info_node *node = m->private;
b5e50c3f 1514 struct drm_device *dev = node->minor->dev;
e277a1f8 1515 struct drm_i915_private *dev_priv = dev->dev_private;
b5e50c3f 1516
3a77c4c4 1517 if (!HAS_FBC(dev)) {
267f0c90 1518 seq_puts(m, "FBC unsupported on this chipset\n");
b5e50c3f
JB		 1519 return 0;
1520 }
1521
36623ef8
PZ		 1522 intel_runtime_pm_get(dev_priv);
1523
ee5382ae 1524 if (intel_fbc_enabled(dev)) {
267f0c90 1525 seq_puts(m, "FBC enabled\n");
b5e50c3f 1526 } else {
267f0c90 1527 seq_puts(m, "FBC disabled: ");
5c3fe8b0 1528 switch (dev_priv->fbc.no_fbc_reason) {
29ebf90f
CW		 1529 case FBC_OK:
1530 seq_puts(m, "FBC actived, but currently disabled in hardware");
1531 break;
1532 case FBC_UNSUPPORTED:
1533 seq_puts(m, "unsupported by this chipset");
1534 break;
bed4a673 1535 case FBC_NO_OUTPUT:
267f0c90 1536 seq_puts(m, "no outputs");
bed4a673 1537 break;
b5e50c3f 1538 case FBC_STOLEN_TOO_SMALL:
267f0c90 1539 seq_puts(m, "not enough stolen memory");
b5e50c3f
JB		 1540 break;
1541 case FBC_UNSUPPORTED_MODE:
267f0c90 1542 seq_puts(m, "mode not supported");
b5e50c3f
JB		 1543 break;
1544 case FBC_MODE_TOO_LARGE:
267f0c90 1545 seq_puts(m, "mode too large");
b5e50c3f
JB		 1546 break;
1547 case FBC_BAD_PLANE:
267f0c90 1548 seq_puts(m, "FBC unsupported on plane");
b5e50c3f
JB		 1549 break;
1550 case FBC_NOT_TILED:
267f0c90 1551 seq_puts(m, "scanout buffer not tiled");
b5e50c3f 1552 break;
9c928d16 1553 case FBC_MULTIPLE_PIPES:
267f0c90 1554 seq_puts(m, "multiple pipes are enabled");
9c928d16 1555 break;
c1a9f047 1556 case FBC_MODULE_PARAM:
267f0c90 1557 seq_puts(m, "disabled per module param (default off)");
c1a9f047 1558 break;
8a5729a3 1559 case FBC_CHIP_DEFAULT:
267f0c90 1560 seq_puts(m, "disabled per chip default");
8a5729a3 1561 break;
b5e50c3f 1562 default:
267f0c90 1563 seq_puts(m, "unknown reason");
b5e50c3f 1564 }
267f0c90 1565 seq_putc(m, '\n');
b5e50c3f 1566 }
36623ef8
PZ		 1567
1568 intel_runtime_pm_put(dev_priv);
1569
b5e50c3f
JB		 1570 return 0;
1571}
1572
da46f936
RV		 1573static int i915_fbc_fc_get(void *data, u64 *val)
1574{
1575 struct drm_device *dev = data;
1576 struct drm_i915_private *dev_priv = dev->dev_private;
1577
1578 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1579 return -ENODEV;
1580
1581 drm_modeset_lock_all(dev);
1582 *val = dev_priv->fbc.false_color;
1583 drm_modeset_unlock_all(dev);
1584
1585 return 0;
1586}
1587
1588static int i915_fbc_fc_set(void *data, u64 val)
1589{
1590 struct drm_device *dev = data;
1591 struct drm_i915_private *dev_priv = dev->dev_private;
1592 u32 reg;
1593
1594 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1595 return -ENODEV;
1596
1597 drm_modeset_lock_all(dev);
1598
1599 reg = I915_READ(ILK_DPFC_CONTROL);
1600 dev_priv->fbc.false_color = val;
1601
1602 I915_WRITE(ILK_DPFC_CONTROL, val ?
1603 (reg | FBC_CTL_FALSE_COLOR) :
1604 (reg & ~FBC_CTL_FALSE_COLOR));
1605
1606 drm_modeset_unlock_all(dev);
1607 return 0;
1608}
1609
1610DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops,
1611 i915_fbc_fc_get, i915_fbc_fc_set,
1612 "%llu\n");
1613
92d44621
PZ		 1614static int i915_ips_status(struct seq_file *m, void *unused)
1615{
9f25d007 1616 struct drm_info_node *node = m->private;
92d44621
PZ		 1617 struct drm_device *dev = node->minor->dev;
1618 struct drm_i915_private *dev_priv = dev->dev_private;
1619
f5adf94e 1620 if (!HAS_IPS(dev)) {
92d44621
PZ		 1621 seq_puts(m, "not supported\n");
1622 return 0;
1623 }
1624
36623ef8
PZ		 1625 intel_runtime_pm_get(dev_priv);
1626
0eaa53f0
RV		 1627 seq_printf(m, "Enabled by kernel parameter: %s\n",
1628 yesno(i915.enable_ips));
1629
1630 if (INTEL_INFO(dev)->gen >= 8) {
1631 seq_puts(m, "Currently: unknown\n");
1632 } else {
1633 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1634 seq_puts(m, "Currently: enabled\n");
1635 else
1636 seq_puts(m, "Currently: disabled\n");
1637 }
92d44621 1638
36623ef8
PZ		 1639 intel_runtime_pm_put(dev_priv);
1640
92d44621
PZ		 1641 return 0;
1642}
1643
4a9bef37
JB		 1644static int i915_sr_status(struct seq_file *m, void *unused)
1645{
9f25d007 1646 struct drm_info_node *node = m->private;
4a9bef37 1647 struct drm_device *dev = node->minor->dev;
e277a1f8 1648 struct drm_i915_private *dev_priv = dev->dev_private;
4a9bef37
JB		 1649 bool sr_enabled = false;
1650
36623ef8
PZ		 1651 intel_runtime_pm_get(dev_priv);
1652
1398261a 1653 if (HAS_PCH_SPLIT(dev))
5ba2aaaa 1654 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
a6c45cf0 1655 else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))
4a9bef37
JB		 1656 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1657 else if (IS_I915GM(dev))
1658 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1659 else if (IS_PINEVIEW(dev))
1660 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1661
36623ef8
PZ		 1662 intel_runtime_pm_put(dev_priv);
1663
5ba2aaaa
CW		 1664 seq_printf(m, "self-refresh: %s\n",
1665 sr_enabled ? "enabled" : "disabled");
4a9bef37
JB		 1666
1667 return 0;
1668}
1669
7648fa99
JB		 1670static int i915_emon_status(struct seq_file *m, void *unused)
1671{
9f25d007 1672 struct drm_info_node *node = m->private;
7648fa99 1673 struct drm_device *dev = node->minor->dev;
e277a1f8 1674 struct drm_i915_private *dev_priv = dev->dev_private;
7648fa99 1675 unsigned long temp, chipset, gfx;
de227ef0
CW		 1676 int ret;
1677
582be6b4
CW		 1678 if (!IS_GEN5(dev))
1679 return -ENODEV;
1680
de227ef0
CW		 1681 ret = mutex_lock_interruptible(&dev->struct_mutex);
1682 if (ret)
1683 return ret;
7648fa99
JB		 1684
1685 temp = i915_mch_val(dev_priv);
1686 chipset = i915_chipset_val(dev_priv);
1687 gfx = i915_gfx_val(dev_priv);
de227ef0 1688 mutex_unlock(&dev->struct_mutex);
7648fa99
JB		 1689
1690 seq_printf(m, "GMCH temp: %ld\n", temp);
1691 seq_printf(m, "Chipset power: %ld\n", chipset);
1692 seq_printf(m, "GFX power: %ld\n", gfx);
1693 seq_printf(m, "Total power: %ld\n", chipset + gfx);
1694
1695 return 0;
1696}
1697
23b2f8bb
JB		 1698static int i915_ring_freq_table(struct seq_file *m, void *unused)
1699{
9f25d007 1700 struct drm_info_node *node = m->private;
23b2f8bb 1701 struct drm_device *dev = node->minor->dev;
e277a1f8 1702 struct drm_i915_private *dev_priv = dev->dev_private;
5bfa0199 1703 int ret = 0;
23b2f8bb
JB		 1704 int gpu_freq, ia_freq;
1705
1c70c0ce 1706 if (!(IS_GEN6(dev) || IS_GEN7(dev))) {
267f0c90 1707 seq_puts(m, "unsupported on this chipset\n");
23b2f8bb
JB		 1708 return 0;
1709 }
1710
5bfa0199
PZ		 1711 intel_runtime_pm_get(dev_priv);
1712
5c9669ce
TR		 1713 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1714
4fc688ce 1715 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
23b2f8bb 1716 if (ret)
5bfa0199 1717 goto out;
23b2f8bb 1718
267f0c90 1719 seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
23b2f8bb 1720
b39fb297
BW		 1721 for (gpu_freq = dev_priv->rps.min_freq_softlimit;
1722 gpu_freq <= dev_priv->rps.max_freq_softlimit;
23b2f8bb 1723 gpu_freq++) {
42c0526c
BW		 1724 ia_freq = gpu_freq;
1725 sandybridge_pcode_read(dev_priv,
1726 GEN6_PCODE_READ_MIN_FREQ_TABLE,
1727 &ia_freq);
3ebecd07 1728 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
7c59a9c1 1729 intel_gpu_freq(dev_priv, gpu_freq),
3ebecd07
CW		 1730 ((ia_freq >> 0) & 0xff) * 100,
1731 ((ia_freq >> 8) & 0xff) * 100);
23b2f8bb
JB		 1732 }
1733
4fc688ce 1734 mutex_unlock(&dev_priv->rps.hw_lock);
23b2f8bb 1735
5bfa0199
PZ		 1736out:
1737 intel_runtime_pm_put(dev_priv);
1738 return ret;
23b2f8bb
JB		 1739}
1740
44834a67
CW		 1741static int i915_opregion(struct seq_file *m, void *unused)
1742{
9f25d007 1743 struct drm_info_node *node = m->private;
44834a67 1744 struct drm_device *dev = node->minor->dev;
e277a1f8 1745 struct drm_i915_private *dev_priv = dev->dev_private;
44834a67 1746 struct intel_opregion *opregion = &dev_priv->opregion;
0d38f009 1747 void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL);
44834a67
CW		 1748 int ret;
1749
0d38f009
DV		 1750 if (data == NULL)
1751 return -ENOMEM;
1752
44834a67
CW		 1753 ret = mutex_lock_interruptible(&dev->struct_mutex);
1754 if (ret)
0d38f009 1755 goto out;
44834a67 1756
0d38f009
DV		 1757 if (opregion->header) {
1758 memcpy_fromio(data, opregion->header, OPREGION_SIZE);
1759 seq_write(m, data, OPREGION_SIZE);
1760 }
44834a67
CW		 1761
1762 mutex_unlock(&dev->struct_mutex);
1763
0d38f009
DV		 1764out:
1765 kfree(data);
44834a67
CW		 1766 return 0;
1767}
1768
37811fcc
CW		 1769static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1770{
9f25d007 1771 struct drm_info_node *node = m->private;
37811fcc 1772 struct drm_device *dev = node->minor->dev;
4520f53a 1773 struct intel_fbdev *ifbdev = NULL;
37811fcc 1774 struct intel_framebuffer *fb;
37811fcc 1775
4520f53a
DV		 1776#ifdef CONFIG_DRM_I915_FBDEV
1777 struct drm_i915_private *dev_priv = dev->dev_private;
37811fcc
CW		 1778
1779 ifbdev = dev_priv->fbdev;
1780 fb = to_intel_framebuffer(ifbdev->helper.fb);
1781
c1ca506d 1782 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
37811fcc
CW		 1783 fb->base.width,
1784 fb->base.height,
1785 fb->base.depth,
623f9783 1786 fb->base.bits_per_pixel,
c1ca506d 1787 fb->base.modifier[0],
623f9783 1788 atomic_read(&fb->base.refcount.refcount));
05394f39 1789 describe_obj(m, fb->obj);
267f0c90 1790 seq_putc(m, '\n');
4520f53a 1791#endif
37811fcc 1792
4b096ac1 1793 mutex_lock(&dev->mode_config.fb_lock);
37811fcc 1794 list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) {
131a56dc 1795 if (ifbdev && &fb->base == ifbdev->helper.fb)
37811fcc
CW		 1796 continue;
1797
c1ca506d 1798 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
37811fcc
CW		 1799 fb->base.width,
1800 fb->base.height,
1801 fb->base.depth,
623f9783 1802 fb->base.bits_per_pixel,
c1ca506d 1803 fb->base.modifier[0],
623f9783 1804 atomic_read(&fb->base.refcount.refcount));
05394f39 1805 describe_obj(m, fb->obj);
267f0c90 1806 seq_putc(m, '\n');
37811fcc 1807 }
4b096ac1 1808 mutex_unlock(&dev->mode_config.fb_lock);
37811fcc
CW		 1809
1810 return 0;
1811}
1812
c9fe99bd
OM		 1813static void describe_ctx_ringbuf(struct seq_file *m,
1814 struct intel_ringbuffer *ringbuf)
1815{
1816 seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
1817 ringbuf->space, ringbuf->head, ringbuf->tail,
1818 ringbuf->last_retired_head);
1819}
1820
e76d3630
BW		 1821static int i915_context_status(struct seq_file *m, void *unused)
1822{
9f25d007 1823 struct drm_info_node *node = m->private;
e76d3630 1824 struct drm_device *dev = node->minor->dev;
e277a1f8 1825 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 1826 struct intel_engine_cs *ring;
273497e5 1827 struct intel_context *ctx;
a168c293 1828 int ret, i;
e76d3630 1829
f3d28878 1830 ret = mutex_lock_interruptible(&dev->struct_mutex);
e76d3630
BW		 1831 if (ret)
1832 return ret;
1833
3e373948 1834 if (dev_priv->ips.pwrctx) {
267f0c90 1835 seq_puts(m, "power context ");
3e373948 1836 describe_obj(m, dev_priv->ips.pwrctx);
267f0c90 1837 seq_putc(m, '\n');
dc501fbc 1838 }
e76d3630 1839
3e373948 1840 if (dev_priv->ips.renderctx) {
267f0c90 1841 seq_puts(m, "render context ");
3e373948 1842 describe_obj(m, dev_priv->ips.renderctx);
267f0c90 1843 seq_putc(m, '\n');
dc501fbc 1844 }
e76d3630 1845
a33afea5 1846 list_for_each_entry(ctx, &dev_priv->context_list, link) {
c9fe99bd
OM		 1847 if (!i915.enable_execlists &&
1848 ctx->legacy_hw_ctx.rcs_state == NULL)
b77f6997
CW		 1849 continue;
1850
a33afea5 1851 seq_puts(m, "HW context ");
3ccfd19d 1852 describe_ctx(m, ctx);
c9fe99bd 1853 for_each_ring(ring, dev_priv, i) {
a33afea5 1854 if (ring->default_context == ctx)
c9fe99bd
OM		 1855 seq_printf(m, "(default context %s) ",
1856 ring->name);
1857 }
1858
1859 if (i915.enable_execlists) {
1860 seq_putc(m, '\n');
1861 for_each_ring(ring, dev_priv, i) {
1862 struct drm_i915_gem_object *ctx_obj =
1863 ctx->engine[i].state;
1864 struct intel_ringbuffer *ringbuf =
1865 ctx->engine[i].ringbuf;
1866
1867 seq_printf(m, "%s: ", ring->name);
1868 if (ctx_obj)
1869 describe_obj(m, ctx_obj);
1870 if (ringbuf)
1871 describe_ctx_ringbuf(m, ringbuf);
1872 seq_putc(m, '\n');
1873 }
1874 } else {
1875 describe_obj(m, ctx->legacy_hw_ctx.rcs_state);
1876 }
a33afea5 1877
a33afea5 1878 seq_putc(m, '\n');
a168c293
BW		 1879 }
1880
f3d28878 1881 mutex_unlock(&dev->struct_mutex);
e76d3630
BW		 1882
1883 return 0;
1884}
1885
064ca1d2
TD		 1886static void i915_dump_lrc_obj(struct seq_file *m,
1887 struct intel_engine_cs *ring,
1888 struct drm_i915_gem_object *ctx_obj)
1889{
1890 struct page *page;
1891 uint32_t *reg_state;
1892 int j;
1893 unsigned long ggtt_offset = 0;
1894
1895 if (ctx_obj == NULL) {
1896 seq_printf(m, "Context on %s with no gem object\n",
1897 ring->name);
1898 return;
1899 }
1900
1901 seq_printf(m, "CONTEXT: %s %u\n", ring->name,
1902 intel_execlists_ctx_id(ctx_obj));
1903
1904 if (!i915_gem_obj_ggtt_bound(ctx_obj))
1905 seq_puts(m, "\tNot bound in GGTT\n");
1906 else
1907 ggtt_offset = i915_gem_obj_ggtt_offset(ctx_obj);
1908
1909 if (i915_gem_object_get_pages(ctx_obj)) {
1910 seq_puts(m, "\tFailed to get pages for context object\n");
1911 return;
1912 }
1913
1914 page = i915_gem_object_get_page(ctx_obj, 1);
1915 if (!WARN_ON(page == NULL)) {
1916 reg_state = kmap_atomic(page);
1917
1918 for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
1919 seq_printf(m, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n",
1920 ggtt_offset + 4096 + (j * 4),
1921 reg_state[j], reg_state[j + 1],
1922 reg_state[j + 2], reg_state[j + 3]);
1923 }
1924 kunmap_atomic(reg_state);
1925 }
1926
1927 seq_putc(m, '\n');
1928}
1929
c0ab1ae9
BW		 1930static int i915_dump_lrc(struct seq_file *m, void *unused)
1931{
1932 struct drm_info_node *node = (struct drm_info_node *) m->private;
1933 struct drm_device *dev = node->minor->dev;
1934 struct drm_i915_private *dev_priv = dev->dev_private;
1935 struct intel_engine_cs *ring;
1936 struct intel_context *ctx;
1937 int ret, i;
1938
1939 if (!i915.enable_execlists) {
1940 seq_printf(m, "Logical Ring Contexts are disabled\n");
1941 return 0;
1942 }
1943
1944 ret = mutex_lock_interruptible(&dev->struct_mutex);
1945 if (ret)
1946 return ret;
1947
1948 list_for_each_entry(ctx, &dev_priv->context_list, link) {
1949 for_each_ring(ring, dev_priv, i) {
064ca1d2
TD		 1950 if (ring->default_context != ctx)
1951 i915_dump_lrc_obj(m, ring,
1952 ctx->engine[i].state);
c0ab1ae9
BW		 1953 }
1954 }
1955
1956 mutex_unlock(&dev->struct_mutex);
1957
1958 return 0;
1959}
1960
4ba70e44
OM		 1961static int i915_execlists(struct seq_file *m, void *data)
1962{
1963 struct drm_info_node *node = (struct drm_info_node *)m->private;
1964 struct drm_device *dev = node->minor->dev;
1965 struct drm_i915_private *dev_priv = dev->dev_private;
1966 struct intel_engine_cs *ring;
1967 u32 status_pointer;
1968 u8 read_pointer;
1969 u8 write_pointer;
1970 u32 status;
1971 u32 ctx_id;
1972 struct list_head *cursor;
1973 int ring_id, i;
1974 int ret;
1975
1976 if (!i915.enable_execlists) {
1977 seq_puts(m, "Logical Ring Contexts are disabled\n");
1978 return 0;
1979 }
1980
1981 ret = mutex_lock_interruptible(&dev->struct_mutex);
1982 if (ret)
1983 return ret;
1984
fc0412ec
MT		 1985 intel_runtime_pm_get(dev_priv);
1986
4ba70e44 1987 for_each_ring(ring, dev_priv, ring_id) {
6d3d8274 1988 struct drm_i915_gem_request *head_req = NULL;
4ba70e44
OM		 1989 int count = 0;
1990 unsigned long flags;
1991
1992 seq_printf(m, "%s\n", ring->name);
1993
1994 status = I915_READ(RING_EXECLIST_STATUS(ring));
1995 ctx_id = I915_READ(RING_EXECLIST_STATUS(ring) + 4);
1996 seq_printf(m, "\tExeclist status: 0x%08X, context: %u\n",
1997 status, ctx_id);
1998
1999 status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(ring));
2000 seq_printf(m, "\tStatus pointer: 0x%08X\n", status_pointer);
2001
2002 read_pointer = ring->next_context_status_buffer;
2003 write_pointer = status_pointer & 0x07;
2004 if (read_pointer > write_pointer)
2005 write_pointer += 6;
2006 seq_printf(m, "\tRead pointer: 0x%08X, write pointer 0x%08X\n",
2007 read_pointer, write_pointer);
2008
2009 for (i = 0; i < 6; i++) {
2010 status = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + 8*i);
2011 ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + 8*i + 4);
2012
2013 seq_printf(m, "\tStatus buffer %d: 0x%08X, context: %u\n",
2014 i, status, ctx_id);
2015 }
2016
2017 spin_lock_irqsave(&ring->execlist_lock, flags);
2018 list_for_each(cursor, &ring->execlist_queue)
2019 count++;
2020 head_req = list_first_entry_or_null(&ring->execlist_queue,
6d3d8274 2021 struct drm_i915_gem_request, execlist_link);
4ba70e44
OM		 2022 spin_unlock_irqrestore(&ring->execlist_lock, flags);
2023
2024 seq_printf(m, "\t%d requests in queue\n", count);
2025 if (head_req) {
2026 struct drm_i915_gem_object *ctx_obj;
2027
6d3d8274 2028 ctx_obj = head_req->ctx->engine[ring_id].state;
4ba70e44
OM		 2029 seq_printf(m, "\tHead request id: %u\n",
2030 intel_execlists_ctx_id(ctx_obj));
2031 seq_printf(m, "\tHead request tail: %u\n",
6d3d8274 2032 head_req->tail);
4ba70e44
OM		 2033 }
2034
2035 seq_putc(m, '\n');
2036 }
2037
fc0412ec 2038 intel_runtime_pm_put(dev_priv);
4ba70e44
OM		 2039 mutex_unlock(&dev->struct_mutex);
2040
2041 return 0;
2042}
2043
ea16a3cd
DV		 2044static const char *swizzle_string(unsigned swizzle)
2045{
aee56cff 2046 switch (swizzle) {
ea16a3cd
DV		 2047 case I915_BIT_6_SWIZZLE_NONE:
2048 return "none";
2049 case I915_BIT_6_SWIZZLE_9:
2050 return "bit9";
2051 case I915_BIT_6_SWIZZLE_9_10:
2052 return "bit9/bit10";
2053 case I915_BIT_6_SWIZZLE_9_11:
2054 return "bit9/bit11";
2055 case I915_BIT_6_SWIZZLE_9_10_11:
2056 return "bit9/bit10/bit11";
2057 case I915_BIT_6_SWIZZLE_9_17:
2058 return "bit9/bit17";
2059 case I915_BIT_6_SWIZZLE_9_10_17:
2060 return "bit9/bit10/bit17";
2061 case I915_BIT_6_SWIZZLE_UNKNOWN:
8a168ca7 2062 return "unknown";
ea16a3cd
DV		 2063 }
2064
2065 return "bug";
2066}
2067
2068static int i915_swizzle_info(struct seq_file *m, void *data)
2069{
9f25d007 2070 struct drm_info_node *node = m->private;
ea16a3cd
DV		 2071 struct drm_device *dev = node->minor->dev;
2072 struct drm_i915_private *dev_priv = dev->dev_private;
22bcfc6a
DV		 2073 int ret;
2074
2075 ret = mutex_lock_interruptible(&dev->struct_mutex);
2076 if (ret)
2077 return ret;
c8c8fb33 2078 intel_runtime_pm_get(dev_priv);
ea16a3cd 2079
ea16a3cd
DV		 2080 seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
2081 swizzle_string(dev_priv->mm.bit_6_swizzle_x));
2082 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
2083 swizzle_string(dev_priv->mm.bit_6_swizzle_y));
2084
2085 if (IS_GEN3(dev) || IS_GEN4(dev)) {
2086 seq_printf(m, "DDC = 0x%08x\n",
2087 I915_READ(DCC));
656bfa3a
DV		 2088 seq_printf(m, "DDC2 = 0x%08x\n",
2089 I915_READ(DCC2));
ea16a3cd
DV		 2090 seq_printf(m, "C0DRB3 = 0x%04x\n",
2091 I915_READ16(C0DRB3));
2092 seq_printf(m, "C1DRB3 = 0x%04x\n",
2093 I915_READ16(C1DRB3));
9d3203e1 2094 } else if (INTEL_INFO(dev)->gen >= 6) {
3fa7d235
DV		 2095 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
2096 I915_READ(MAD_DIMM_C0));
2097 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
2098 I915_READ(MAD_DIMM_C1));
2099 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
2100 I915_READ(MAD_DIMM_C2));
2101 seq_printf(m, "TILECTL = 0x%08x\n",
2102 I915_READ(TILECTL));
5907f5fb 2103 if (INTEL_INFO(dev)->gen >= 8)
9d3203e1
BW		 2104 seq_printf(m, "GAMTARBMODE = 0x%08x\n",
2105 I915_READ(GAMTARBMODE));
2106 else
2107 seq_printf(m, "ARB_MODE = 0x%08x\n",
2108 I915_READ(ARB_MODE));
3fa7d235
DV		 2109 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
2110 I915_READ(DISP_ARB_CTL));
ea16a3cd 2111 }
656bfa3a
DV		 2112
2113 if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2114 seq_puts(m, "L-shaped memory detected\n");
2115
c8c8fb33 2116 intel_runtime_pm_put(dev_priv);
ea16a3cd
DV		 2117 mutex_unlock(&dev->struct_mutex);
2118
2119 return 0;
2120}
2121
1c60fef5
BW		 2122static int per_file_ctx(int id, void *ptr, void *data)
2123{
273497e5 2124 struct intel_context *ctx = ptr;
1c60fef5 2125 struct seq_file *m = data;
ae6c4806
DV		 2126 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2127
2128 if (!ppgtt) {
2129 seq_printf(m, " no ppgtt for context %d\n",
2130 ctx->user_handle);
2131 return 0;
2132 }
1c60fef5 2133
f83d6518
OM		 2134 if (i915_gem_context_is_default(ctx))
2135 seq_puts(m, " default context:\n");
2136 else
821d66dd 2137 seq_printf(m, " context %d:\n", ctx->user_handle);
1c60fef5
BW		 2138 ppgtt->debug_dump(ppgtt, m);
2139
2140 return 0;
2141}
2142
77df6772 2143static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev)
3cf17fc5 2144{
3cf17fc5 2145 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2146 struct intel_engine_cs *ring;
77df6772
BW		 2147 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2148 int unused, i;
3cf17fc5 2149
77df6772
BW		 2150 if (!ppgtt)
2151 return;
2152
2153 seq_printf(m, "Page directories: %d\n", ppgtt->num_pd_pages);
5abbcca3 2154 seq_printf(m, "Page tables: %d\n", ppgtt->num_pd_entries);
77df6772
BW		 2155 for_each_ring(ring, dev_priv, unused) {
2156 seq_printf(m, "%s\n", ring->name);
2157 for (i = 0; i < 4; i++) {
2158 u32 offset = 0x270 + i * 8;
2159 u64 pdp = I915_READ(ring->mmio_base + offset + 4);
2160 pdp <<= 32;
2161 pdp |= I915_READ(ring->mmio_base + offset);
a2a5b15c 2162 seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
77df6772
BW		 2163 }
2164 }
2165}
2166
2167static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2168{
2169 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2170 struct intel_engine_cs *ring;
1c60fef5 2171 struct drm_file *file;
77df6772 2172 int i;
3cf17fc5 2173
3cf17fc5
DV		 2174 if (INTEL_INFO(dev)->gen == 6)
2175 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
2176
a2c7f6fd 2177 for_each_ring(ring, dev_priv, i) {
3cf17fc5
DV		 2178 seq_printf(m, "%s\n", ring->name);
2179 if (INTEL_INFO(dev)->gen == 7)
2180 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
2181 seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
2182 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
2183 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring)));
2184 }
2185 if (dev_priv->mm.aliasing_ppgtt) {
2186 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2187
267f0c90 2188 seq_puts(m, "aliasing PPGTT:\n");
7324cc04 2189 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.pd_offset);
1c60fef5 2190
87d60b63 2191 ppgtt->debug_dump(ppgtt, m);
ae6c4806 2192 }
1c60fef5
BW		 2193
2194 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2195 struct drm_i915_file_private *file_priv = file->driver_priv;
1c60fef5 2196
1c60fef5
BW		 2197 seq_printf(m, "proc: %s\n",
2198 get_pid_task(file->pid, PIDTYPE_PID)->comm);
1c60fef5 2199 idr_for_each(&file_priv->context_idr, per_file_ctx, m);
3cf17fc5
DV		 2200 }
2201 seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
77df6772
BW		 2202}
2203
2204static int i915_ppgtt_info(struct seq_file *m, void *data)
2205{
9f25d007 2206 struct drm_info_node *node = m->private;
77df6772 2207 struct drm_device *dev = node->minor->dev;
c8c8fb33 2208 struct drm_i915_private *dev_priv = dev->dev_private;
77df6772
BW		 2209
2210 int ret = mutex_lock_interruptible(&dev->struct_mutex);
2211 if (ret)
2212 return ret;
c8c8fb33 2213 intel_runtime_pm_get(dev_priv);
77df6772
BW		 2214
2215 if (INTEL_INFO(dev)->gen >= 8)
2216 gen8_ppgtt_info(m, dev);
2217 else if (INTEL_INFO(dev)->gen >= 6)
2218 gen6_ppgtt_info(m, dev);
2219
c8c8fb33 2220 intel_runtime_pm_put(dev_priv);
3cf17fc5
DV		 2221 mutex_unlock(&dev->struct_mutex);
2222
2223 return 0;
2224}
2225
63573eb7
BW		 2226static int i915_llc(struct seq_file *m, void *data)
2227{
9f25d007 2228 struct drm_info_node *node = m->private;
63573eb7
BW		 2229 struct drm_device *dev = node->minor->dev;
2230 struct drm_i915_private *dev_priv = dev->dev_private;
2231
2232 /* Size calculation for LLC is a bit of a pain. Ignore for now. */
2233 seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
2234 seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size);
2235
2236 return 0;
2237}
2238
e91fd8c6
RV		 2239static int i915_edp_psr_status(struct seq_file *m, void *data)
2240{
2241 struct drm_info_node *node = m->private;
2242 struct drm_device *dev = node->minor->dev;
2243 struct drm_i915_private *dev_priv = dev->dev_private;
a031d709 2244 u32 psrperf = 0;
a6cbdb8e
RV		 2245 u32 stat[3];
2246 enum pipe pipe;
a031d709 2247 bool enabled = false;
e91fd8c6 2248
c8c8fb33
PZ		 2249 intel_runtime_pm_get(dev_priv);
2250
fa128fa6 2251 mutex_lock(&dev_priv->psr.lock);
a031d709
RV		 2252 seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
2253 seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
2807cf69 2254 seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
5755c78f 2255 seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
fa128fa6
DV		 2256 seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
2257 dev_priv->psr.busy_frontbuffer_bits);
2258 seq_printf(m, "Re-enable work scheduled: %s\n",
2259 yesno(work_busy(&dev_priv->psr.work.work)));
e91fd8c6 2260
a6cbdb8e
RV		 2261 if (HAS_PSR(dev)) {
2262 if (HAS_DDI(dev))
2263 enabled = I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
2264 else {
2265 for_each_pipe(dev_priv, pipe) {
2266 stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
2267 VLV_EDP_PSR_CURR_STATE_MASK;
2268 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2269 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2270 enabled = true;
2271 }
2272 }
2273 }
2274 seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));
2275
2276 if (!HAS_DDI(dev))
2277 for_each_pipe(dev_priv, pipe) {
2278 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2279 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2280 seq_printf(m, " pipe %c", pipe_name(pipe));
2281 }
2282 seq_puts(m, "\n");
e91fd8c6 2283
fb495814
RV		 2284 seq_printf(m, "Link standby: %s\n",
2285 yesno((bool)dev_priv->psr.link_standby));
2286
a6cbdb8e
RV		 2287 /* CHV PSR has no kind of performance counter */
2288 if (HAS_PSR(dev) && HAS_DDI(dev)) {
a031d709
RV		 2289 psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) &
2290 EDP_PSR_PERF_CNT_MASK;
a6cbdb8e
RV		 2291
2292 seq_printf(m, "Performance_Counter: %u\n", psrperf);
2293 }
fa128fa6 2294 mutex_unlock(&dev_priv->psr.lock);
e91fd8c6 2295
c8c8fb33 2296 intel_runtime_pm_put(dev_priv);
e91fd8c6
RV		 2297 return 0;
2298}
2299
d2e216d0
RV		 2300static int i915_sink_crc(struct seq_file *m, void *data)
2301{
2302 struct drm_info_node *node = m->private;
2303 struct drm_device *dev = node->minor->dev;
2304 struct intel_encoder *encoder;
2305 struct intel_connector *connector;
2306 struct intel_dp *intel_dp = NULL;
2307 int ret;
2308 u8 crc[6];
2309
2310 drm_modeset_lock_all(dev);
2311 list_for_each_entry(connector, &dev->mode_config.connector_list,
2312 base.head) {
2313
2314 if (connector->base.dpms != DRM_MODE_DPMS_ON)
2315 continue;
2316
b6ae3c7c
PZ		 2317 if (!connector->base.encoder)
2318 continue;
2319
d2e216d0
RV		 2320 encoder = to_intel_encoder(connector->base.encoder);
2321 if (encoder->type != INTEL_OUTPUT_EDP)
2322 continue;
2323
2324 intel_dp = enc_to_intel_dp(&encoder->base);
2325
2326 ret = intel_dp_sink_crc(intel_dp, crc);
2327 if (ret)
2328 goto out;
2329
2330 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2331 crc[0], crc[1], crc[2],
2332 crc[3], crc[4], crc[5]);
2333 goto out;
2334 }
2335 ret = -ENODEV;
2336out:
2337 drm_modeset_unlock_all(dev);
2338 return ret;
2339}
2340
ec013e7f
JB		 2341static int i915_energy_uJ(struct seq_file *m, void *data)
2342{
2343 struct drm_info_node *node = m->private;
2344 struct drm_device *dev = node->minor->dev;
2345 struct drm_i915_private *dev_priv = dev->dev_private;
2346 u64 power;
2347 u32 units;
2348
2349 if (INTEL_INFO(dev)->gen < 6)
2350 return -ENODEV;
2351
36623ef8
PZ		 2352 intel_runtime_pm_get(dev_priv);
2353
ec013e7f
JB		 2354 rdmsrl(MSR_RAPL_POWER_UNIT, power);
2355 power = (power & 0x1f00) >> 8;
2356 units = 1000000 / (1 << power); /* convert to uJ */
2357 power = I915_READ(MCH_SECP_NRG_STTS);
2358 power *= units;
2359
36623ef8
PZ		 2360 intel_runtime_pm_put(dev_priv);
2361
ec013e7f 2362 seq_printf(m, "%llu", (long long unsigned)power);
371db66a
PZ		 2363
2364 return 0;
2365}
2366
2367static int i915_pc8_status(struct seq_file *m, void *unused)
2368{
9f25d007 2369 struct drm_info_node *node = m->private;
371db66a
PZ		 2370 struct drm_device *dev = node->minor->dev;
2371 struct drm_i915_private *dev_priv = dev->dev_private;
2372
85b8d5c2 2373 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
371db66a
PZ		 2374 seq_puts(m, "not supported\n");
2375 return 0;
2376 }
2377
86c4ec0d 2378 seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy));
371db66a 2379 seq_printf(m, "IRQs disabled: %s\n",
9df7575f 2380 yesno(!intel_irqs_enabled(dev_priv)));
371db66a 2381
ec013e7f
JB		 2382 return 0;
2383}
2384
1da51581
ID		 2385static const char *power_domain_str(enum intel_display_power_domain domain)
2386{
2387 switch (domain) {
2388 case POWER_DOMAIN_PIPE_A:
2389 return "PIPE_A";
2390 case POWER_DOMAIN_PIPE_B:
2391 return "PIPE_B";
2392 case POWER_DOMAIN_PIPE_C:
2393 return "PIPE_C";
2394 case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
2395 return "PIPE_A_PANEL_FITTER";
2396 case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
2397 return "PIPE_B_PANEL_FITTER";
2398 case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
2399 return "PIPE_C_PANEL_FITTER";
2400 case POWER_DOMAIN_TRANSCODER_A:
2401 return "TRANSCODER_A";
2402 case POWER_DOMAIN_TRANSCODER_B:
2403 return "TRANSCODER_B";
2404 case POWER_DOMAIN_TRANSCODER_C:
2405 return "TRANSCODER_C";
2406 case POWER_DOMAIN_TRANSCODER_EDP:
2407 return "TRANSCODER_EDP";
319be8ae
ID		 2408 case POWER_DOMAIN_PORT_DDI_A_2_LANES:
2409 return "PORT_DDI_A_2_LANES";
2410 case POWER_DOMAIN_PORT_DDI_A_4_LANES:
2411 return "PORT_DDI_A_4_LANES";
2412 case POWER_DOMAIN_PORT_DDI_B_2_LANES:
2413 return "PORT_DDI_B_2_LANES";
2414 case POWER_DOMAIN_PORT_DDI_B_4_LANES:
2415 return "PORT_DDI_B_4_LANES";
2416 case POWER_DOMAIN_PORT_DDI_C_2_LANES:
2417 return "PORT_DDI_C_2_LANES";
2418 case POWER_DOMAIN_PORT_DDI_C_4_LANES:
2419 return "PORT_DDI_C_4_LANES";
2420 case POWER_DOMAIN_PORT_DDI_D_2_LANES:
2421 return "PORT_DDI_D_2_LANES";
2422 case POWER_DOMAIN_PORT_DDI_D_4_LANES:
2423 return "PORT_DDI_D_4_LANES";
2424 case POWER_DOMAIN_PORT_DSI:
2425 return "PORT_DSI";
2426 case POWER_DOMAIN_PORT_CRT:
2427 return "PORT_CRT";
2428 case POWER_DOMAIN_PORT_OTHER:
2429 return "PORT_OTHER";
1da51581
ID		 2430 case POWER_DOMAIN_VGA:
2431 return "VGA";
2432 case POWER_DOMAIN_AUDIO:
2433 return "AUDIO";
bd2bb1b9
PZ		 2434 case POWER_DOMAIN_PLLS:
2435 return "PLLS";
1407121a
S		 2436 case POWER_DOMAIN_AUX_A:
2437 return "AUX_A";
2438 case POWER_DOMAIN_AUX_B:
2439 return "AUX_B";
2440 case POWER_DOMAIN_AUX_C:
2441 return "AUX_C";
2442 case POWER_DOMAIN_AUX_D:
2443 return "AUX_D";
1da51581
ID		 2444 case POWER_DOMAIN_INIT:
2445 return "INIT";
2446 default:
5f77eeb0 2447 MISSING_CASE(domain);
1da51581
ID		 2448 return "?";
2449 }
2450}
2451
2452static int i915_power_domain_info(struct seq_file *m, void *unused)
2453{
9f25d007 2454 struct drm_info_node *node = m->private;
1da51581
ID		 2455 struct drm_device *dev = node->minor->dev;
2456 struct drm_i915_private *dev_priv = dev->dev_private;
2457 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2458 int i;
2459
2460 mutex_lock(&power_domains->lock);
2461
2462 seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2463 for (i = 0; i < power_domains->power_well_count; i++) {
2464 struct i915_power_well *power_well;
2465 enum intel_display_power_domain power_domain;
2466
2467 power_well = &power_domains->power_wells[i];
2468 seq_printf(m, "%-25s %d\n", power_well->name,
2469 power_well->count);
2470
2471 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
2472 power_domain++) {
2473 if (!(BIT(power_domain) & power_well->domains))
2474 continue;
2475
2476 seq_printf(m, " %-23s %d\n",
2477 power_domain_str(power_domain),
2478 power_domains->domain_use_count[power_domain]);
2479 }
2480 }
2481
2482 mutex_unlock(&power_domains->lock);
2483
2484 return 0;
2485}
2486
53f5e3ca
JB		 2487static void intel_seq_print_mode(struct seq_file *m, int tabs,
2488 struct drm_display_mode *mode)
2489{
2490 int i;
2491
2492 for (i = 0; i < tabs; i++)
2493 seq_putc(m, '\t');
2494
2495 seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2496 mode->base.id, mode->name,
2497 mode->vrefresh, mode->clock,
2498 mode->hdisplay, mode->hsync_start,
2499 mode->hsync_end, mode->htotal,
2500 mode->vdisplay, mode->vsync_start,
2501 mode->vsync_end, mode->vtotal,
2502 mode->type, mode->flags);
2503}
2504
2505static void intel_encoder_info(struct seq_file *m,
2506 struct intel_crtc *intel_crtc,
2507 struct intel_encoder *intel_encoder)
2508{
9f25d007 2509 struct drm_info_node *node = m->private;
53f5e3ca
JB		 2510 struct drm_device *dev = node->minor->dev;
2511 struct drm_crtc *crtc = &intel_crtc->base;
2512 struct intel_connector *intel_connector;
2513 struct drm_encoder *encoder;
2514
2515 encoder = &intel_encoder->base;
2516 seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
8e329a03 2517 encoder->base.id, encoder->name);
53f5e3ca
JB		 2518 for_each_connector_on_encoder(dev, encoder, intel_connector) {
2519 struct drm_connector *connector = &intel_connector->base;
2520 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2521 connector->base.id,
c23cc417 2522 connector->name,
53f5e3ca
JB		 2523 drm_get_connector_status_name(connector->status));
2524 if (connector->status == connector_status_connected) {
2525 struct drm_display_mode *mode = &crtc->mode;
2526 seq_printf(m, ", mode:\n");
2527 intel_seq_print_mode(m, 2, mode);
2528 } else {
2529 seq_putc(m, '\n');
2530 }
2531 }
2532}
2533
2534static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2535{
9f25d007 2536 struct drm_info_node *node = m->private;
53f5e3ca
JB		 2537 struct drm_device *dev = node->minor->dev;
2538 struct drm_crtc *crtc = &intel_crtc->base;
2539 struct intel_encoder *intel_encoder;
2540
5aa8a937
MR		 2541 if (crtc->primary->fb)
2542 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2543 crtc->primary->fb->base.id, crtc->x, crtc->y,
2544 crtc->primary->fb->width, crtc->primary->fb->height);
2545 else
2546 seq_puts(m, "\tprimary plane disabled\n");
53f5e3ca
JB		 2547 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2548 intel_encoder_info(m, intel_crtc, intel_encoder);
2549}
2550
2551static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2552{
2553 struct drm_display_mode *mode = panel->fixed_mode;
2554
2555 seq_printf(m, "\tfixed mode:\n");
2556 intel_seq_print_mode(m, 2, mode);
2557}
2558
2559static void intel_dp_info(struct seq_file *m,
2560 struct intel_connector *intel_connector)
2561{
2562 struct intel_encoder *intel_encoder = intel_connector->encoder;
2563 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2564
2565 seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2566 seq_printf(m, "\taudio support: %s\n", intel_dp->has_audio ? "yes" :
2567 "no");
2568 if (intel_encoder->type == INTEL_OUTPUT_EDP)
2569 intel_panel_info(m, &intel_connector->panel);
2570}
2571
2572static void intel_hdmi_info(struct seq_file *m,
2573 struct intel_connector *intel_connector)
2574{
2575 struct intel_encoder *intel_encoder = intel_connector->encoder;
2576 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2577
2578 seq_printf(m, "\taudio support: %s\n", intel_hdmi->has_audio ? "yes" :
2579 "no");
2580}
2581
2582static void intel_lvds_info(struct seq_file *m,
2583 struct intel_connector *intel_connector)
2584{
2585 intel_panel_info(m, &intel_connector->panel);
2586}
2587
2588static void intel_connector_info(struct seq_file *m,
2589 struct drm_connector *connector)
2590{
2591 struct intel_connector *intel_connector = to_intel_connector(connector);
2592 struct intel_encoder *intel_encoder = intel_connector->encoder;
f103fc7d 2593 struct drm_display_mode *mode;
53f5e3ca
JB		 2594
2595 seq_printf(m, "connector %d: type %s, status: %s\n",
c23cc417 2596 connector->base.id, connector->name,
53f5e3ca
JB		 2597 drm_get_connector_status_name(connector->status));
2598 if (connector->status == connector_status_connected) {
2599 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2600 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2601 connector->display_info.width_mm,
2602 connector->display_info.height_mm);
2603 seq_printf(m, "\tsubpixel order: %s\n",
2604 drm_get_subpixel_order_name(connector->display_info.subpixel_order));
2605 seq_printf(m, "\tCEA rev: %d\n",
2606 connector->display_info.cea_rev);
2607 }
36cd7444
DA		 2608 if (intel_encoder) {
2609 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2610 intel_encoder->type == INTEL_OUTPUT_EDP)
2611 intel_dp_info(m, intel_connector);
2612 else if (intel_encoder->type == INTEL_OUTPUT_HDMI)
2613 intel_hdmi_info(m, intel_connector);
2614 else if (intel_encoder->type == INTEL_OUTPUT_LVDS)
2615 intel_lvds_info(m, intel_connector);
2616 }
53f5e3ca 2617
f103fc7d
JB		 2618 seq_printf(m, "\tmodes:\n");
2619 list_for_each_entry(mode, &connector->modes, head)
2620 intel_seq_print_mode(m, 2, mode);
53f5e3ca
JB		 2621}
2622
065f2ec2
CW		 2623static bool cursor_active(struct drm_device *dev, int pipe)
2624{
2625 struct drm_i915_private *dev_priv = dev->dev_private;
2626 u32 state;
2627
2628 if (IS_845G(dev) || IS_I865G(dev))
2629 state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
065f2ec2 2630 else
5efb3e28 2631 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
065f2ec2
CW		 2632
2633 return state;
2634}
2635
2636static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y)
2637{
2638 struct drm_i915_private *dev_priv = dev->dev_private;
2639 u32 pos;
2640
5efb3e28 2641 pos = I915_READ(CURPOS(pipe));
065f2ec2
CW		 2642
2643 *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
2644 if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
2645 *x = -*x;
2646
2647 *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
2648 if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
2649 *y = -*y;
2650
2651 return cursor_active(dev, pipe);
2652}
2653
53f5e3ca
JB		 2654static int i915_display_info(struct seq_file *m, void *unused)
2655{
9f25d007 2656 struct drm_info_node *node = m->private;
53f5e3ca 2657 struct drm_device *dev = node->minor->dev;
b0e5ddf3 2658 struct drm_i915_private *dev_priv = dev->dev_private;
065f2ec2 2659 struct intel_crtc *crtc;
53f5e3ca
JB		 2660 struct drm_connector *connector;
2661
b0e5ddf3 2662 intel_runtime_pm_get(dev_priv);
53f5e3ca
JB		 2663 drm_modeset_lock_all(dev);
2664 seq_printf(m, "CRTC info\n");
2665 seq_printf(m, "---------\n");
d3fcc808 2666 for_each_intel_crtc(dev, crtc) {
065f2ec2
CW		 2667 bool active;
2668 int x, y;
53f5e3ca 2669
57127efa 2670 seq_printf(m, "CRTC %d: pipe: %c, active=%s (size=%dx%d)\n",
065f2ec2 2671 crtc->base.base.id, pipe_name(crtc->pipe),
6e3c9717
ACO		 2672 yesno(crtc->active), crtc->config->pipe_src_w,
2673 crtc->config->pipe_src_h);
a23dc658 2674 if (crtc->active) {
065f2ec2
CW		 2675 intel_crtc_info(m, crtc);
2676
a23dc658 2677 active = cursor_position(dev, crtc->pipe, &x, &y);
57127efa 2678 seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
4b0e333e 2679 yesno(crtc->cursor_base),
3dd512fb
MR		 2680 x, y, crtc->base.cursor->state->crtc_w,
2681 crtc->base.cursor->state->crtc_h,
57127efa 2682 crtc->cursor_addr, yesno(active));
a23dc658 2683 }
cace841c
DV		 2684
2685 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
2686 yesno(!crtc->cpu_fifo_underrun_disabled),
2687 yesno(!crtc->pch_fifo_underrun_disabled));
53f5e3ca
JB		 2688 }
2689
2690 seq_printf(m, "\n");
2691 seq_printf(m, "Connector info\n");
2692 seq_printf(m, "--------------\n");
2693 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2694 intel_connector_info(m, connector);
2695 }
2696 drm_modeset_unlock_all(dev);
b0e5ddf3 2697 intel_runtime_pm_put(dev_priv);
53f5e3ca
JB		 2698
2699 return 0;
2700}
2701
e04934cf
BW		 2702static int i915_semaphore_status(struct seq_file *m, void *unused)
2703{
2704 struct drm_info_node *node = (struct drm_info_node *) m->private;
2705 struct drm_device *dev = node->minor->dev;
2706 struct drm_i915_private *dev_priv = dev->dev_private;
2707 struct intel_engine_cs *ring;
2708 int num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
2709 int i, j, ret;
2710
2711 if (!i915_semaphore_is_enabled(dev)) {
2712 seq_puts(m, "Semaphores are disabled\n");
2713 return 0;
2714 }
2715
2716 ret = mutex_lock_interruptible(&dev->struct_mutex);
2717 if (ret)
2718 return ret;
03872064 2719 intel_runtime_pm_get(dev_priv);
e04934cf
BW		 2720
2721 if (IS_BROADWELL(dev)) {
2722 struct page *page;
2723 uint64_t *seqno;
2724
2725 page = i915_gem_object_get_page(dev_priv->semaphore_obj, 0);
2726
2727 seqno = (uint64_t *)kmap_atomic(page);
2728 for_each_ring(ring, dev_priv, i) {
2729 uint64_t offset;
2730
2731 seq_printf(m, "%s\n", ring->name);
2732
2733 seq_puts(m, " Last signal:");
2734 for (j = 0; j < num_rings; j++) {
2735 offset = i * I915_NUM_RINGS + j;
2736 seq_printf(m, "0x%08llx (0x%02llx) ",
2737 seqno[offset], offset * 8);
2738 }
2739 seq_putc(m, '\n');
2740
2741 seq_puts(m, " Last wait: ");
2742 for (j = 0; j < num_rings; j++) {
2743 offset = i + (j * I915_NUM_RINGS);
2744 seq_printf(m, "0x%08llx (0x%02llx) ",
2745 seqno[offset], offset * 8);
2746 }
2747 seq_putc(m, '\n');
2748
2749 }
2750 kunmap_atomic(seqno);
2751 } else {
2752 seq_puts(m, " Last signal:");
2753 for_each_ring(ring, dev_priv, i)
2754 for (j = 0; j < num_rings; j++)
2755 seq_printf(m, "0x%08x\n",
2756 I915_READ(ring->semaphore.mbox.signal[j]));
2757 seq_putc(m, '\n');
2758 }
2759
2760 seq_puts(m, "\nSync seqno:\n");
2761 for_each_ring(ring, dev_priv, i) {
2762 for (j = 0; j < num_rings; j++) {
2763 seq_printf(m, " 0x%08x ", ring->semaphore.sync_seqno[j]);
2764 }
2765 seq_putc(m, '\n');
2766 }
2767 seq_putc(m, '\n');
2768
03872064 2769 intel_runtime_pm_put(dev_priv);
e04934cf
BW		 2770 mutex_unlock(&dev->struct_mutex);
2771 return 0;
2772}
2773
728e29d7
DV		 2774static int i915_shared_dplls_info(struct seq_file *m, void *unused)
2775{
2776 struct drm_info_node *node = (struct drm_info_node *) m->private;
2777 struct drm_device *dev = node->minor->dev;
2778 struct drm_i915_private *dev_priv = dev->dev_private;
2779 int i;
2780
2781 drm_modeset_lock_all(dev);
2782 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
2783 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
2784
2785 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
1e6f2ddc 2786 seq_printf(m, " crtc_mask: 0x%08x, active: %d, on: %s\n",
3e369b76 2787 pll->config.crtc_mask, pll->active, yesno(pll->on));
728e29d7 2788 seq_printf(m, " tracked hardware state:\n");
3e369b76
ACO		 2789 seq_printf(m, " dpll: 0x%08x\n", pll->config.hw_state.dpll);
2790 seq_printf(m, " dpll_md: 0x%08x\n",
2791 pll->config.hw_state.dpll_md);
2792 seq_printf(m, " fp0: 0x%08x\n", pll->config.hw_state.fp0);
2793 seq_printf(m, " fp1: 0x%08x\n", pll->config.hw_state.fp1);
2794 seq_printf(m, " wrpll: 0x%08x\n", pll->config.hw_state.wrpll);
728e29d7
DV		 2795 }
2796 drm_modeset_unlock_all(dev);
2797
2798 return 0;
2799}
2800
1ed1ef9d 2801static int i915_wa_registers(struct seq_file *m, void *unused)
888b5995
AS		 2802{
2803 int i;
2804 int ret;
2805 struct drm_info_node *node = (struct drm_info_node *) m->private;
2806 struct drm_device *dev = node->minor->dev;
2807 struct drm_i915_private *dev_priv = dev->dev_private;
2808
888b5995
AS		 2809 ret = mutex_lock_interruptible(&dev->struct_mutex);
2810 if (ret)
2811 return ret;
2812
2813 intel_runtime_pm_get(dev_priv);
2814
7225342a
MK		 2815 seq_printf(m, "Workarounds applied: %d\n", dev_priv->workarounds.count);
2816 for (i = 0; i < dev_priv->workarounds.count; ++i) {
2fa60f6d
MK		 2817 u32 addr, mask, value, read;
2818 bool ok;
888b5995 2819
7225342a
MK		 2820 addr = dev_priv->workarounds.reg[i].addr;
2821 mask = dev_priv->workarounds.reg[i].mask;
2fa60f6d
MK		 2822 value = dev_priv->workarounds.reg[i].value;
2823 read = I915_READ(addr);
2824 ok = (value & mask) == (read & mask);
2825 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
2826 addr, value, mask, read, ok ? "OK" : "FAIL");
888b5995
AS		 2827 }
2828
2829 intel_runtime_pm_put(dev_priv);
2830 mutex_unlock(&dev->struct_mutex);
2831
2832 return 0;
2833}
2834
c5511e44
DL		 2835static int i915_ddb_info(struct seq_file *m, void *unused)
2836{
2837 struct drm_info_node *node = m->private;
2838 struct drm_device *dev = node->minor->dev;
2839 struct drm_i915_private *dev_priv = dev->dev_private;
2840 struct skl_ddb_allocation *ddb;
2841 struct skl_ddb_entry *entry;
2842 enum pipe pipe;
2843 int plane;
2844
2fcffe19
DL		 2845 if (INTEL_INFO(dev)->gen < 9)
2846 return 0;
2847
c5511e44
DL		 2848 drm_modeset_lock_all(dev);
2849
2850 ddb = &dev_priv->wm.skl_hw.ddb;
2851
2852 seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
2853
2854 for_each_pipe(dev_priv, pipe) {
2855 seq_printf(m, "Pipe %c\n", pipe_name(pipe));
2856
2857 for_each_plane(pipe, plane) {
2858 entry = &ddb->plane[pipe][plane];
2859 seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane + 1,
2860 entry->start, entry->end,
2861 skl_ddb_entry_size(entry));
2862 }
2863
2864 entry = &ddb->cursor[pipe];
2865 seq_printf(m, " %-13s%8u%8u%8u\n", "Cursor", entry->start,
2866 entry->end, skl_ddb_entry_size(entry));
2867 }
2868
2869 drm_modeset_unlock_all(dev);
2870
2871 return 0;
2872}
2873
07144428
DL		 2874struct pipe_crc_info {
2875 const char *name;
2876 struct drm_device *dev;
2877 enum pipe pipe;
2878};
2879
11bed958
DA		 2880static int i915_dp_mst_info(struct seq_file *m, void *unused)
2881{
2882 struct drm_info_node *node = (struct drm_info_node *) m->private;
2883 struct drm_device *dev = node->minor->dev;
2884 struct drm_encoder *encoder;
2885 struct intel_encoder *intel_encoder;
2886 struct intel_digital_port *intel_dig_port;
2887 drm_modeset_lock_all(dev);
2888 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2889 intel_encoder = to_intel_encoder(encoder);
2890 if (intel_encoder->type != INTEL_OUTPUT_DISPLAYPORT)
2891 continue;
2892 intel_dig_port = enc_to_dig_port(encoder);
2893 if (!intel_dig_port->dp.can_mst)
2894 continue;
2895
2896 drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr);
2897 }
2898 drm_modeset_unlock_all(dev);
2899 return 0;
2900}
2901
07144428
DL		 2902static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
2903{
be5c7a90
DL		 2904 struct pipe_crc_info *info = inode->i_private;
2905 struct drm_i915_private *dev_priv = info->dev->dev_private;
2906 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2907
7eb1c496
DV		 2908 if (info->pipe >= INTEL_INFO(info->dev)->num_pipes)
2909 return -ENODEV;
2910
d538bbdf
DL		 2911 spin_lock_irq(&pipe_crc->lock);
2912
2913 if (pipe_crc->opened) {
2914 spin_unlock_irq(&pipe_crc->lock);
be5c7a90
DL		 2915 return -EBUSY; /* already open */
2916 }
2917
d538bbdf 2918 pipe_crc->opened = true;
07144428
DL		 2919 filep->private_data = inode->i_private;
2920
d538bbdf
DL		 2921 spin_unlock_irq(&pipe_crc->lock);
2922
07144428
DL		 2923 return 0;
2924}
2925
2926static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
2927{
be5c7a90
DL		 2928 struct pipe_crc_info *info = inode->i_private;
2929 struct drm_i915_private *dev_priv = info->dev->dev_private;
2930 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2931
d538bbdf
DL		 2932 spin_lock_irq(&pipe_crc->lock);
2933 pipe_crc->opened = false;
2934 spin_unlock_irq(&pipe_crc->lock);
be5c7a90 2935
07144428
DL		 2936 return 0;
2937}
2938
2939/* (6 fields, 8 chars each, space separated (5) + '\n') */
2940#define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
2941/* account for \'0' */
2942#define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1)
2943
2944static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
8bf1e9f1 2945{
d538bbdf
DL		 2946 assert_spin_locked(&pipe_crc->lock);
2947 return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
2948 INTEL_PIPE_CRC_ENTRIES_NR);
07144428
DL		 2949}
2950
2951static ssize_t
2952i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
2953 loff_t *pos)
2954{
2955 struct pipe_crc_info *info = filep->private_data;
2956 struct drm_device *dev = info->dev;
2957 struct drm_i915_private *dev_priv = dev->dev_private;
2958 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2959 char buf[PIPE_CRC_BUFFER_LEN];
9ad6d99f 2960 int n_entries;
07144428
DL		 2961 ssize_t bytes_read;
2962
2963 /*
2964 * Don't allow user space to provide buffers not big enough to hold
2965 * a line of data.
2966 */
2967 if (count < PIPE_CRC_LINE_LEN)
2968 return -EINVAL;
2969
2970 if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
8bf1e9f1 2971 return 0;
07144428
DL		 2972
2973 /* nothing to read */
d538bbdf 2974 spin_lock_irq(&pipe_crc->lock);
07144428 2975 while (pipe_crc_data_count(pipe_crc) == 0) {
d538bbdf
DL		 2976 int ret;
2977
2978 if (filep->f_flags & O_NONBLOCK) {
2979 spin_unlock_irq(&pipe_crc->lock);
07144428 2980 return -EAGAIN;
d538bbdf 2981 }
07144428 2982
d538bbdf
DL		 2983 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
2984 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
2985 if (ret) {
2986 spin_unlock_irq(&pipe_crc->lock);
2987 return ret;
2988 }
8bf1e9f1
SH		 2989 }
2990
07144428 2991 /* We now have one or more entries to read */
9ad6d99f 2992 n_entries = count / PIPE_CRC_LINE_LEN;
d538bbdf 2993
07144428 2994 bytes_read = 0;
9ad6d99f
VS		 2995 while (n_entries > 0) {
2996 struct intel_pipe_crc_entry *entry =
2997 &pipe_crc->entries[pipe_crc->tail];
07144428 2998 int ret;
8bf1e9f1 2999
9ad6d99f
VS		 3000 if (CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3001 INTEL_PIPE_CRC_ENTRIES_NR) < 1)
3002 break;
3003
3004 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
3005 pipe_crc->tail = (pipe_crc->tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
3006
07144428
DL		 3007 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
3008 "%8u %8x %8x %8x %8x %8x\n",
3009 entry->frame, entry->crc[0],
3010 entry->crc[1], entry->crc[2],
3011 entry->crc[3], entry->crc[4]);
3012
9ad6d99f
VS		 3013 spin_unlock_irq(&pipe_crc->lock);
3014
3015 ret = copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN);
07144428
DL		 3016 if (ret == PIPE_CRC_LINE_LEN)
3017 return -EFAULT;
b2c88f5b 3018
9ad6d99f
VS		 3019 user_buf += PIPE_CRC_LINE_LEN;
3020 n_entries--;
3021
3022 spin_lock_irq(&pipe_crc->lock);
3023 }
8bf1e9f1 3024
d538bbdf
DL		 3025 spin_unlock_irq(&pipe_crc->lock);
3026
07144428
DL		 3027 return bytes_read;
3028}
3029
3030static const struct file_operations i915_pipe_crc_fops = {
3031 .owner = THIS_MODULE,
3032 .open = i915_pipe_crc_open,
3033 .read = i915_pipe_crc_read,
3034 .release = i915_pipe_crc_release,
3035};
3036
3037static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
3038 {
3039 .name = "i915_pipe_A_crc",
3040 .pipe = PIPE_A,
3041 },
3042 {
3043 .name = "i915_pipe_B_crc",
3044 .pipe = PIPE_B,
3045 },
3046 {
3047 .name = "i915_pipe_C_crc",
3048 .pipe = PIPE_C,
3049 },
3050};
3051
3052static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
3053 enum pipe pipe)
3054{
3055 struct drm_device *dev = minor->dev;
3056 struct dentry *ent;
3057 struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
3058
3059 info->dev = dev;
3060 ent = debugfs_create_file(info->name, S_IRUGO, root, info,
3061 &i915_pipe_crc_fops);
f3c5fe97
WY		 3062 if (!ent)
3063 return -ENOMEM;
07144428
DL		 3064
3065 return drm_add_fake_info_node(minor, ent, info);
8bf1e9f1
SH		 3066}
3067
e8dfcf78 3068static const char * const pipe_crc_sources[] = {
926321d5
DV		 3069 "none",
3070 "plane1",
3071 "plane2",
3072 "pf",
5b3a856b 3073 "pipe",
3d099a05
DV		 3074 "TV",
3075 "DP-B",
3076 "DP-C",
3077 "DP-D",
46a19188 3078 "auto",
926321d5
DV		 3079};
3080
3081static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
3082{
3083 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
3084 return pipe_crc_sources[source];
3085}
3086
bd9db02f 3087static int display_crc_ctl_show(struct seq_file *m, void *data)
926321d5
DV		 3088{
3089 struct drm_device *dev = m->private;
3090 struct drm_i915_private *dev_priv = dev->dev_private;
3091 int i;
3092
3093 for (i = 0; i < I915_MAX_PIPES; i++)
3094 seq_printf(m, "%c %s\n", pipe_name(i),
3095 pipe_crc_source_name(dev_priv->pipe_crc[i].source));
3096
3097 return 0;
3098}
3099
bd9db02f 3100static int display_crc_ctl_open(struct inode *inode, struct file *file)
926321d5
DV		 3101{
3102 struct drm_device *dev = inode->i_private;
3103
bd9db02f 3104 return single_open(file, display_crc_ctl_show, dev);
926321d5
DV		 3105}
3106
46a19188 3107static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
52f843f6
DV		 3108 uint32_t *val)
3109{
46a19188
DV		 3110 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3111 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3112
3113 switch (*source) {
52f843f6
DV		 3114 case INTEL_PIPE_CRC_SOURCE_PIPE:
3115 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
3116 break;
3117 case INTEL_PIPE_CRC_SOURCE_NONE:
3118 *val = 0;
3119 break;
3120 default:
3121 return -EINVAL;
3122 }
3123
3124 return 0;
3125}
3126
46a19188
DV		 3127static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe,
3128 enum intel_pipe_crc_source *source)
3129{
3130 struct intel_encoder *encoder;
3131 struct intel_crtc *crtc;
26756809 3132 struct intel_digital_port *dig_port;
46a19188
DV		 3133 int ret = 0;
3134
3135 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3136
6e9f798d 3137 drm_modeset_lock_all(dev);
b2784e15 3138 for_each_intel_encoder(dev, encoder) {
46a19188
DV		 3139 if (!encoder->base.crtc)
3140 continue;
3141
3142 crtc = to_intel_crtc(encoder->base.crtc);
3143
3144 if (crtc->pipe != pipe)
3145 continue;
3146
3147 switch (encoder->type) {
3148 case INTEL_OUTPUT_TVOUT:
3149 *source = INTEL_PIPE_CRC_SOURCE_TV;
3150 break;
3151 case INTEL_OUTPUT_DISPLAYPORT:
3152 case INTEL_OUTPUT_EDP:
26756809
DV		 3153 dig_port = enc_to_dig_port(&encoder->base);
3154 switch (dig_port->port) {
3155 case PORT_B:
3156 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
3157 break;
3158 case PORT_C:
3159 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
3160 break;
3161 case PORT_D:
3162 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
3163 break;
3164 default:
3165 WARN(1, "nonexisting DP port %c\n",
3166 port_name(dig_port->port));
3167 break;
3168 }
46a19188 3169 break;
6847d71b
PZ		 3170 default:
3171 break;
46a19188
DV		 3172 }
3173 }
6e9f798d 3174 drm_modeset_unlock_all(dev);
46a19188
DV		 3175
3176 return ret;
3177}
3178
3179static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
3180 enum pipe pipe,
3181 enum intel_pipe_crc_source *source,
7ac0129b
DV		 3182 uint32_t *val)
3183{
8d2f24ca
DV		 3184 struct drm_i915_private *dev_priv = dev->dev_private;
3185 bool need_stable_symbols = false;
3186
46a19188
DV		 3187 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3188 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3189 if (ret)
3190 return ret;
3191 }
3192
3193 switch (*source) {
7ac0129b
DV		 3194 case INTEL_PIPE_CRC_SOURCE_PIPE:
3195 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
3196 break;
3197 case INTEL_PIPE_CRC_SOURCE_DP_B:
3198 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
8d2f24ca 3199 need_stable_symbols = true;
7ac0129b
DV		 3200 break;
3201 case INTEL_PIPE_CRC_SOURCE_DP_C:
3202 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
8d2f24ca 3203 need_stable_symbols = true;
7ac0129b 3204 break;
2be57922
VS		 3205 case INTEL_PIPE_CRC_SOURCE_DP_D:
3206 if (!IS_CHERRYVIEW(dev))
3207 return -EINVAL;
3208 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV;
3209 need_stable_symbols = true;
3210 break;
7ac0129b
DV		 3211 case INTEL_PIPE_CRC_SOURCE_NONE:
3212 *val = 0;
3213 break;
3214 default:
3215 return -EINVAL;
3216 }
3217
8d2f24ca
DV		 3218 /*
3219 * When the pipe CRC tap point is after the transcoders we need
3220 * to tweak symbol-level features to produce a deterministic series of
3221 * symbols for a given frame. We need to reset those features only once
3222 * a frame (instead of every nth symbol):
3223 * - DC-balance: used to ensure a better clock recovery from the data
3224 * link (SDVO)
3225 * - DisplayPort scrambling: used for EMI reduction
3226 */
3227 if (need_stable_symbols) {
3228 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3229
8d2f24ca 3230 tmp |= DC_BALANCE_RESET_VLV;
eb736679
VS		 3231 switch (pipe) {
3232 case PIPE_A:
8d2f24ca 3233 tmp |= PIPE_A_SCRAMBLE_RESET;
eb736679
VS		 3234 break;
3235 case PIPE_B:
8d2f24ca 3236 tmp |= PIPE_B_SCRAMBLE_RESET;
eb736679
VS		 3237 break;
3238 case PIPE_C:
3239 tmp |= PIPE_C_SCRAMBLE_RESET;
3240 break;
3241 default:
3242 return -EINVAL;
3243 }
8d2f24ca
DV		 3244 I915_WRITE(PORT_DFT2_G4X, tmp);
3245 }
3246
7ac0129b
DV		 3247 return 0;
3248}
3249
4b79ebf7 3250static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
46a19188
DV		 3251 enum pipe pipe,
3252 enum intel_pipe_crc_source *source,
4b79ebf7
DV		 3253 uint32_t *val)
3254{
84093603
DV		 3255 struct drm_i915_private *dev_priv = dev->dev_private;
3256 bool need_stable_symbols = false;
3257
46a19188
DV		 3258 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3259 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3260 if (ret)
3261 return ret;
3262 }
3263
3264 switch (*source) {
4b79ebf7
DV		 3265 case INTEL_PIPE_CRC_SOURCE_PIPE:
3266 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
3267 break;
3268 case INTEL_PIPE_CRC_SOURCE_TV:
3269 if (!SUPPORTS_TV(dev))
3270 return -EINVAL;
3271 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
3272 break;
3273 case INTEL_PIPE_CRC_SOURCE_DP_B:
3274 if (!IS_G4X(dev))
3275 return -EINVAL;
3276 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
84093603 3277 need_stable_symbols = true;
4b79ebf7
DV		 3278 break;
3279 case INTEL_PIPE_CRC_SOURCE_DP_C:
3280 if (!IS_G4X(dev))
3281 return -EINVAL;
3282 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
84093603 3283 need_stable_symbols = true;
4b79ebf7
DV		 3284 break;
3285 case INTEL_PIPE_CRC_SOURCE_DP_D:
3286 if (!IS_G4X(dev))
3287 return -EINVAL;
3288 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
84093603 3289 need_stable_symbols = true;
4b79ebf7
DV		 3290 break;
3291 case INTEL_PIPE_CRC_SOURCE_NONE:
3292 *val = 0;
3293 break;
3294 default:
3295 return -EINVAL;
3296 }
3297
84093603
DV		 3298 /*
3299 * When the pipe CRC tap point is after the transcoders we need
3300 * to tweak symbol-level features to produce a deterministic series of
3301 * symbols for a given frame. We need to reset those features only once
3302 * a frame (instead of every nth symbol):
3303 * - DC-balance: used to ensure a better clock recovery from the data
3304 * link (SDVO)
3305 * - DisplayPort scrambling: used for EMI reduction
3306 */
3307 if (need_stable_symbols) {
3308 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3309
3310 WARN_ON(!IS_G4X(dev));
3311
3312 I915_WRITE(PORT_DFT_I9XX,
3313 I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
3314
3315 if (pipe == PIPE_A)
3316 tmp |= PIPE_A_SCRAMBLE_RESET;
3317 else
3318 tmp |= PIPE_B_SCRAMBLE_RESET;
3319
3320 I915_WRITE(PORT_DFT2_G4X, tmp);
3321 }
3322
4b79ebf7
DV		 3323 return 0;
3324}
3325
8d2f24ca
DV		 3326static void vlv_undo_pipe_scramble_reset(struct drm_device *dev,
3327 enum pipe pipe)
3328{
3329 struct drm_i915_private *dev_priv = dev->dev_private;
3330 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3331
eb736679
VS		 3332 switch (pipe) {
3333 case PIPE_A:
8d2f24ca 3334 tmp &= ~PIPE_A_SCRAMBLE_RESET;
eb736679
VS		 3335 break;
3336 case PIPE_B:
8d2f24ca 3337 tmp &= ~PIPE_B_SCRAMBLE_RESET;
eb736679
VS		 3338 break;
3339 case PIPE_C:
3340 tmp &= ~PIPE_C_SCRAMBLE_RESET;
3341 break;
3342 default:
3343 return;
3344 }
8d2f24ca
DV		 3345 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
3346 tmp &= ~DC_BALANCE_RESET_VLV;
3347 I915_WRITE(PORT_DFT2_G4X, tmp);
3348
3349}
3350
84093603
DV		 3351static void g4x_undo_pipe_scramble_reset(struct drm_device *dev,
3352 enum pipe pipe)
3353{
3354 struct drm_i915_private *dev_priv = dev->dev_private;
3355 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3356
3357 if (pipe == PIPE_A)
3358 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3359 else
3360 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3361 I915_WRITE(PORT_DFT2_G4X, tmp);
3362
3363 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
3364 I915_WRITE(PORT_DFT_I9XX,
3365 I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
3366 }
3367}
3368
46a19188 3369static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
5b3a856b
DV		 3370 uint32_t *val)
3371{
46a19188
DV		 3372 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3373 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3374
3375 switch (*source) {
5b3a856b
DV		 3376 case INTEL_PIPE_CRC_SOURCE_PLANE1:
3377 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
3378 break;
3379 case INTEL_PIPE_CRC_SOURCE_PLANE2:
3380 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
3381 break;
5b3a856b
DV		 3382 case INTEL_PIPE_CRC_SOURCE_PIPE:
3383 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
3384 break;
3d099a05 3385 case INTEL_PIPE_CRC_SOURCE_NONE:
5b3a856b
DV		 3386 *val = 0;
3387 break;
3d099a05
DV		 3388 default:
3389 return -EINVAL;
5b3a856b
DV		 3390 }
3391
3392 return 0;
3393}
3394
fabf6e51
DV		 3395static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device *dev)
3396{
3397 struct drm_i915_private *dev_priv = dev->dev_private;
3398 struct intel_crtc *crtc =
3399 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
3400
3401 drm_modeset_lock_all(dev);
3402 /*
3403 * If we use the eDP transcoder we need to make sure that we don't
3404 * bypass the pfit, since otherwise the pipe CRC source won't work. Only
3405 * relevant on hsw with pipe A when using the always-on power well
3406 * routing.
3407 */
6e3c9717
ACO		 3408 if (crtc->config->cpu_transcoder == TRANSCODER_EDP &&
3409 !crtc->config->pch_pfit.enabled) {
3410 crtc->config->pch_pfit.force_thru = true;
fabf6e51
DV		 3411
3412 intel_display_power_get(dev_priv,
3413 POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A));
3414
3415 dev_priv->display.crtc_disable(&crtc->base);
3416 dev_priv->display.crtc_enable(&crtc->base);
3417 }
3418 drm_modeset_unlock_all(dev);
3419}
3420
3421static void hsw_undo_trans_edp_pipe_A_crc_wa(struct drm_device *dev)
3422{
3423 struct drm_i915_private *dev_priv = dev->dev_private;
3424 struct intel_crtc *crtc =
3425 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
3426
3427 drm_modeset_lock_all(dev);
3428 /*
3429 * If we use the eDP transcoder we need to make sure that we don't
3430 * bypass the pfit, since otherwise the pipe CRC source won't work. Only
3431 * relevant on hsw with pipe A when using the always-on power well
3432 * routing.
3433 */
6e3c9717
ACO		 3434 if (crtc->config->pch_pfit.force_thru) {
3435 crtc->config->pch_pfit.force_thru = false;
fabf6e51
DV		 3436
3437 dev_priv->display.crtc_disable(&crtc->base);
3438 dev_priv->display.crtc_enable(&crtc->base);
3439
3440 intel_display_power_put(dev_priv,
3441 POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A));
3442 }
3443 drm_modeset_unlock_all(dev);
3444}
3445
3446static int ivb_pipe_crc_ctl_reg(struct drm_device *dev,
3447 enum pipe pipe,
3448 enum intel_pipe_crc_source *source,
5b3a856b
DV		 3449 uint32_t *val)
3450{
46a19188
DV		 3451 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3452 *source = INTEL_PIPE_CRC_SOURCE_PF;
3453
3454 switch (*source) {
5b3a856b
DV		 3455 case INTEL_PIPE_CRC_SOURCE_PLANE1:
3456 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
3457 break;
3458 case INTEL_PIPE_CRC_SOURCE_PLANE2:
3459 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
3460 break;
3461 case INTEL_PIPE_CRC_SOURCE_PF:
fabf6e51
DV		 3462 if (IS_HASWELL(dev) && pipe == PIPE_A)
3463 hsw_trans_edp_pipe_A_crc_wa(dev);
3464
5b3a856b
DV		 3465 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
3466 break;
3d099a05 3467 case INTEL_PIPE_CRC_SOURCE_NONE:
5b3a856b
DV		 3468 *val = 0;
3469 break;
3d099a05
DV		 3470 default:
3471 return -EINVAL;
5b3a856b
DV		 3472 }
3473
3474 return 0;
3475}
3476
926321d5
DV		 3477static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
3478 enum intel_pipe_crc_source source)
3479{
3480 struct drm_i915_private *dev_priv = dev->dev_private;
cc3da175 3481 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
8c740dce
PZ		 3482 struct intel_crtc *crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev,
3483 pipe));
432f3342 3484 u32 val = 0; /* shut up gcc */
5b3a856b 3485 int ret;
926321d5 3486
cc3da175
DL		 3487 if (pipe_crc->source == source)
3488 return 0;
3489
ae676fcd
DL		 3490 /* forbid changing the source without going back to 'none' */
3491 if (pipe_crc->source && source)
3492 return -EINVAL;
3493
9d8b0588
DV		 3494 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PIPE(pipe))) {
3495 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
3496 return -EIO;
3497 }
3498
52f843f6 3499 if (IS_GEN2(dev))
46a19188 3500 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
52f843f6 3501 else if (INTEL_INFO(dev)->gen < 5)
46a19188 3502 ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
7ac0129b 3503 else if (IS_VALLEYVIEW(dev))
fabf6e51 3504 ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val);
4b79ebf7 3505 else if (IS_GEN5(dev) || IS_GEN6(dev))
46a19188 3506 ret = ilk_pipe_crc_ctl_reg(&source, &val);
5b3a856b 3507 else
fabf6e51 3508 ret = ivb_pipe_crc_ctl_reg(dev, pipe, &source, &val);
5b3a856b
DV		 3509
3510 if (ret != 0)
3511 return ret;
3512
4b584369
DL		 3513 /* none -> real source transition */
3514 if (source) {
4252fbc3
VS		 3515 struct intel_pipe_crc_entry *entries;
3516
7cd6ccff
DL		 3517 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
3518 pipe_name(pipe), pipe_crc_source_name(source));
3519
3cf54b34
VS		 3520 entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR,
3521 sizeof(pipe_crc->entries[0]),
4252fbc3
VS		 3522 GFP_KERNEL);
3523 if (!entries)
e5f75aca
DL		 3524 return -ENOMEM;
3525
8c740dce
PZ		 3526 /*
3527 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
3528 * enabled and disabled dynamically based on package C states,
3529 * user space can't make reliable use of the CRCs, so let's just
3530 * completely disable it.
3531 */
3532 hsw_disable_ips(crtc);
3533
d538bbdf 3534 spin_lock_irq(&pipe_crc->lock);
64387b61 3535 kfree(pipe_crc->entries);
4252fbc3 3536 pipe_crc->entries = entries;
d538bbdf
DL		 3537 pipe_crc->head = 0;
3538 pipe_crc->tail = 0;
3539 spin_unlock_irq(&pipe_crc->lock);
4b584369
DL		 3540 }
3541
cc3da175 3542 pipe_crc->source = source;
926321d5 3543
926321d5
DV		 3544 I915_WRITE(PIPE_CRC_CTL(pipe), val);
3545 POSTING_READ(PIPE_CRC_CTL(pipe));
3546
e5f75aca
DL		 3547 /* real source -> none transition */
3548 if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
d538bbdf 3549 struct intel_pipe_crc_entry *entries;
a33d7105
DV		 3550 struct intel_crtc *crtc =
3551 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
d538bbdf 3552
7cd6ccff
DL		 3553 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
3554 pipe_name(pipe));
3555
a33d7105
DV		 3556 drm_modeset_lock(&crtc->base.mutex, NULL);
3557 if (crtc->active)
3558 intel_wait_for_vblank(dev, pipe);
3559 drm_modeset_unlock(&crtc->base.mutex);
bcf17ab2 3560
d538bbdf
DL		 3561 spin_lock_irq(&pipe_crc->lock);
3562 entries = pipe_crc->entries;
e5f75aca 3563 pipe_crc->entries = NULL;
9ad6d99f
VS		 3564 pipe_crc->head = 0;
3565 pipe_crc->tail = 0;
d538bbdf
DL		 3566 spin_unlock_irq(&pipe_crc->lock);
3567
3568 kfree(entries);
84093603
DV		 3569
3570 if (IS_G4X(dev))
3571 g4x_undo_pipe_scramble_reset(dev, pipe);
8d2f24ca
DV		 3572 else if (IS_VALLEYVIEW(dev))
3573 vlv_undo_pipe_scramble_reset(dev, pipe);
fabf6e51
DV		 3574 else if (IS_HASWELL(dev) && pipe == PIPE_A)
3575 hsw_undo_trans_edp_pipe_A_crc_wa(dev);
8c740dce
PZ		 3576
3577 hsw_enable_ips(crtc);
e5f75aca
DL		 3578 }
3579
926321d5
DV		 3580 return 0;
3581}
3582
3583/*
3584 * Parse pipe CRC command strings:
b94dec87
DL		 3585 * command: wsp* object wsp+ name wsp+ source wsp*
3586 * object: 'pipe'
3587 * name: (A | B | C)
926321d5
DV		 3588 * source: (none | plane1 | plane2 | pf)
3589 * wsp: (#0x20 | #0x9 | #0xA)+
3590 *
3591 * eg.:
b94dec87
DL		 3592 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A
3593 * "pipe A none" -> Stop CRC
926321d5 3594 */
bd9db02f 3595static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
926321d5
DV		 3596{
3597 int n_words = 0;
3598
3599 while (*buf) {
3600 char *end;
3601
3602 /* skip leading white space */
3603 buf = skip_spaces(buf);
3604 if (!*buf)
3605 break; /* end of buffer */
3606
3607 /* find end of word */
3608 for (end = buf; *end && !isspace(*end); end++)
3609 ;
3610
3611 if (n_words == max_words) {
3612 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
3613 max_words);
3614 return -EINVAL; /* ran out of words[] before bytes */
3615 }
3616
3617 if (*end)
3618 *end++ = '\0';
3619 words[n_words++] = buf;
3620 buf = end;
3621 }
3622
3623 return n_words;
3624}
3625
b94dec87
DL		 3626enum intel_pipe_crc_object {
3627 PIPE_CRC_OBJECT_PIPE,
3628};
3629
e8dfcf78 3630static const char * const pipe_crc_objects[] = {
b94dec87
DL		 3631 "pipe",
3632};
3633
3634static int
bd9db02f 3635display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
b94dec87
DL		 3636{
3637 int i;
3638
3639 for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
3640 if (!strcmp(buf, pipe_crc_objects[i])) {
bd9db02f 3641 *o = i;
b94dec87
DL		 3642 return 0;
3643 }
3644
3645 return -EINVAL;
3646}
3647
bd9db02f 3648static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
926321d5
DV		 3649{
3650 const char name = buf[0];
3651
3652 if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
3653 return -EINVAL;
3654
3655 *pipe = name - 'A';
3656
3657 return 0;
3658}
3659
3660static int
bd9db02f 3661display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
926321d5
DV		 3662{
3663 int i;
3664
3665 for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
3666 if (!strcmp(buf, pipe_crc_sources[i])) {
bd9db02f 3667 *s = i;
926321d5
DV		 3668 return 0;
3669 }
3670
3671 return -EINVAL;
3672}
3673
bd9db02f 3674static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len)
926321d5 3675{
b94dec87 3676#define N_WORDS 3
926321d5 3677 int n_words;
b94dec87 3678 char *words[N_WORDS];
926321d5 3679 enum pipe pipe;
b94dec87 3680 enum intel_pipe_crc_object object;
926321d5
DV		 3681 enum intel_pipe_crc_source source;
3682
bd9db02f 3683 n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
b94dec87
DL		 3684 if (n_words != N_WORDS) {
3685 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
3686 N_WORDS);
3687 return -EINVAL;
3688 }
3689
bd9db02f 3690 if (display_crc_ctl_parse_object(words[0], &object) < 0) {
b94dec87 3691 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
926321d5
DV		 3692 return -EINVAL;
3693 }
3694
bd9db02f 3695 if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
b94dec87 3696 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
926321d5
DV		 3697 return -EINVAL;
3698 }
3699
bd9db02f 3700 if (display_crc_ctl_parse_source(words[2], &source) < 0) {
b94dec87 3701 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
926321d5
DV		 3702 return -EINVAL;
3703 }
3704
3705 return pipe_crc_set_source(dev, pipe, source);
3706}
3707
bd9db02f
DL		 3708static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
3709 size_t len, loff_t *offp)
926321d5
DV		 3710{
3711 struct seq_file *m = file->private_data;
3712 struct drm_device *dev = m->private;
3713 char *tmpbuf;
3714 int ret;
3715
3716 if (len == 0)
3717 return 0;
3718
3719 if (len > PAGE_SIZE - 1) {
3720 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
3721 PAGE_SIZE);
3722 return -E2BIG;
3723 }
3724
3725 tmpbuf = kmalloc(len + 1, GFP_KERNEL);
3726 if (!tmpbuf)
3727 return -ENOMEM;
3728
3729 if (copy_from_user(tmpbuf, ubuf, len)) {
3730 ret = -EFAULT;
3731 goto out;
3732 }
3733 tmpbuf[len] = '\0';
3734
bd9db02f 3735 ret = display_crc_ctl_parse(dev, tmpbuf, len);
926321d5
DV		 3736
3737out:
3738 kfree(tmpbuf);
3739 if (ret < 0)
3740 return ret;
3741
3742 *offp += len;
3743 return len;
3744}
3745
bd9db02f 3746static const struct file_operations i915_display_crc_ctl_fops = {
926321d5 3747 .owner = THIS_MODULE,
bd9db02f 3748 .open = display_crc_ctl_open,
926321d5
DV		 3749 .read = seq_read,
3750 .llseek = seq_lseek,
3751 .release = single_release,
bd9db02f 3752 .write = display_crc_ctl_write
926321d5
DV		 3753};
3754
97e94b22 3755static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
369a1342
VS		 3756{
3757 struct drm_device *dev = m->private;
546c81fd 3758 int num_levels = ilk_wm_max_level(dev) + 1;
369a1342
VS		 3759 int level;
3760
3761 drm_modeset_lock_all(dev);
3762
3763 for (level = 0; level < num_levels; level++) {
3764 unsigned int latency = wm[level];
3765
97e94b22
DL		 3766 /*
3767 * - WM1+ latency values in 0.5us units
3768 * - latencies are in us on gen9
3769 */
3770 if (INTEL_INFO(dev)->gen >= 9)
3771 latency *= 10;
3772 else if (level > 0)
369a1342
VS		 3773 latency *= 5;
3774
3775 seq_printf(m, "WM%d %u (%u.%u usec)\n",
97e94b22 3776 level, wm[level], latency / 10, latency % 10);
369a1342
VS		 3777 }
3778
3779 drm_modeset_unlock_all(dev);
3780}
3781
3782static int pri_wm_latency_show(struct seq_file *m, void *data)
3783{
3784 struct drm_device *dev = m->private;
97e94b22
DL		 3785 struct drm_i915_private *dev_priv = dev->dev_private;
3786 const uint16_t *latencies;
3787
3788 if (INTEL_INFO(dev)->gen >= 9)
3789 latencies = dev_priv->wm.skl_latency;
3790 else
3791 latencies = to_i915(dev)->wm.pri_latency;
369a1342 3792
97e94b22 3793 wm_latency_show(m, latencies);
369a1342
VS		 3794
3795 return 0;
3796}
3797
3798static int spr_wm_latency_show(struct seq_file *m, void *data)
3799{
3800 struct drm_device *dev = m->private;
97e94b22
DL		 3801 struct drm_i915_private *dev_priv = dev->dev_private;
3802 const uint16_t *latencies;
3803
3804 if (INTEL_INFO(dev)->gen >= 9)
3805 latencies = dev_priv->wm.skl_latency;
3806 else
3807 latencies = to_i915(dev)->wm.spr_latency;
369a1342 3808
97e94b22 3809 wm_latency_show(m, latencies);
369a1342
VS		 3810
3811 return 0;
3812}
3813
3814static int cur_wm_latency_show(struct seq_file *m, void *data)
3815{
3816 struct drm_device *dev = m->private;
97e94b22
DL		 3817 struct drm_i915_private *dev_priv = dev->dev_private;
3818 const uint16_t *latencies;
3819
3820 if (INTEL_INFO(dev)->gen >= 9)
3821 latencies = dev_priv->wm.skl_latency;
3822 else
3823 latencies = to_i915(dev)->wm.cur_latency;
369a1342 3824
97e94b22 3825 wm_latency_show(m, latencies);
369a1342
VS		 3826
3827 return 0;
3828}
3829
3830static int pri_wm_latency_open(struct inode *inode, struct file *file)
3831{
3832 struct drm_device *dev = inode->i_private;
3833
9ad0257c 3834 if (HAS_GMCH_DISPLAY(dev))
369a1342
VS		 3835 return -ENODEV;
3836
3837 return single_open(file, pri_wm_latency_show, dev);
3838}
3839
3840static int spr_wm_latency_open(struct inode *inode, struct file *file)
3841{
3842 struct drm_device *dev = inode->i_private;
3843
9ad0257c 3844 if (HAS_GMCH_DISPLAY(dev))
369a1342
VS		 3845 return -ENODEV;
3846
3847 return single_open(file, spr_wm_latency_show, dev);
3848}
3849
3850static int cur_wm_latency_open(struct inode *inode, struct file *file)
3851{
3852 struct drm_device *dev = inode->i_private;
3853
9ad0257c 3854 if (HAS_GMCH_DISPLAY(dev))
369a1342
VS		 3855 return -ENODEV;
3856
3857 return single_open(file, cur_wm_latency_show, dev);
3858}
3859
3860static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
97e94b22 3861 size_t len, loff_t *offp, uint16_t wm[8])
369a1342
VS		 3862{
3863 struct seq_file *m = file->private_data;
3864 struct drm_device *dev = m->private;
97e94b22 3865 uint16_t new[8] = { 0 };
546c81fd 3866 int num_levels = ilk_wm_max_level(dev) + 1;
369a1342
VS		 3867 int level;
3868 int ret;
3869 char tmp[32];
3870
3871 if (len >= sizeof(tmp))
3872 return -EINVAL;
3873
3874 if (copy_from_user(tmp, ubuf, len))
3875 return -EFAULT;
3876
3877 tmp[len] = '\0';
3878
97e94b22
DL		 3879 ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
3880 &new[0], &new[1], &new[2], &new[3],
3881 &new[4], &new[5], &new[6], &new[7]);
369a1342
VS		 3882 if (ret != num_levels)
3883 return -EINVAL;
3884
3885 drm_modeset_lock_all(dev);
3886
3887 for (level = 0; level < num_levels; level++)
3888 wm[level] = new[level];
3889
3890 drm_modeset_unlock_all(dev);
3891
3892 return len;
3893}
3894
3895
3896static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
3897 size_t len, loff_t *offp)
3898{
3899 struct seq_file *m = file->private_data;
3900 struct drm_device *dev = m->private;
97e94b22
DL		 3901 struct drm_i915_private *dev_priv = dev->dev_private;
3902 uint16_t *latencies;
369a1342 3903
97e94b22
DL		 3904 if (INTEL_INFO(dev)->gen >= 9)
3905 latencies = dev_priv->wm.skl_latency;
3906 else
3907 latencies = to_i915(dev)->wm.pri_latency;
3908
3909 return wm_latency_write(file, ubuf, len, offp, latencies);
369a1342
VS		 3910}
3911
3912static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
3913 size_t len, loff_t *offp)
3914{
3915 struct seq_file *m = file->private_data;
3916 struct drm_device *dev = m->private;
97e94b22
DL		 3917 struct drm_i915_private *dev_priv = dev->dev_private;
3918 uint16_t *latencies;
369a1342 3919
97e94b22
DL		 3920 if (INTEL_INFO(dev)->gen >= 9)
3921 latencies = dev_priv->wm.skl_latency;
3922 else
3923 latencies = to_i915(dev)->wm.spr_latency;
3924
3925 return wm_latency_write(file, ubuf, len, offp, latencies);
369a1342
VS		 3926}
3927
3928static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
3929 size_t len, loff_t *offp)
3930{
3931 struct seq_file *m = file->private_data;
3932 struct drm_device *dev = m->private;
97e94b22
DL		 3933 struct drm_i915_private *dev_priv = dev->dev_private;
3934 uint16_t *latencies;
3935
3936 if (INTEL_INFO(dev)->gen >= 9)
3937 latencies = dev_priv->wm.skl_latency;
3938 else
3939 latencies = to_i915(dev)->wm.cur_latency;
369a1342 3940
97e94b22 3941 return wm_latency_write(file, ubuf, len, offp, latencies);
369a1342
VS		 3942}
3943
3944static const struct file_operations i915_pri_wm_latency_fops = {
3945 .owner = THIS_MODULE,
3946 .open = pri_wm_latency_open,
3947 .read = seq_read,
3948 .llseek = seq_lseek,
3949 .release = single_release,
3950 .write = pri_wm_latency_write
3951};
3952
3953static const struct file_operations i915_spr_wm_latency_fops = {
3954 .owner = THIS_MODULE,
3955 .open = spr_wm_latency_open,
3956 .read = seq_read,
3957 .llseek = seq_lseek,
3958 .release = single_release,
3959 .write = spr_wm_latency_write
3960};
3961
3962static const struct file_operations i915_cur_wm_latency_fops = {
3963 .owner = THIS_MODULE,
3964 .open = cur_wm_latency_open,
3965 .read = seq_read,
3966 .llseek = seq_lseek,
3967 .release = single_release,
3968 .write = cur_wm_latency_write
3969};
3970
647416f9
KC		 3971static int
3972i915_wedged_get(void *data, u64 *val)
f3cd474b 3973{
647416f9 3974 struct drm_device *dev = data;
e277a1f8 3975 struct drm_i915_private *dev_priv = dev->dev_private;
f3cd474b 3976
647416f9 3977 *val = atomic_read(&dev_priv->gpu_error.reset_counter);
f3cd474b 3978
647416f9 3979 return 0;
f3cd474b
CW		 3980}
3981
647416f9
KC		 3982static int
3983i915_wedged_set(void *data, u64 val)
f3cd474b 3984{
647416f9 3985 struct drm_device *dev = data;
d46c0517
ID		 3986 struct drm_i915_private *dev_priv = dev->dev_private;
3987
b8d24a06
MK		 3988 /*
3989 * There is no safeguard against this debugfs entry colliding
3990 * with the hangcheck calling same i915_handle_error() in
3991 * parallel, causing an explosion. For now we assume that the
3992 * test harness is responsible enough not to inject gpu hangs
3993 * while it is writing to 'i915_wedged'
3994 */
3995
3996 if (i915_reset_in_progress(&dev_priv->gpu_error))
3997 return -EAGAIN;
3998
d46c0517 3999 intel_runtime_pm_get(dev_priv);
f3cd474b 4000
58174462
MK		 4001 i915_handle_error(dev, val,
4002 "Manually setting wedged to %llu", val);
d46c0517
ID		 4003
4004 intel_runtime_pm_put(dev_priv);
4005
647416f9 4006 return 0;
f3cd474b
CW		 4007}
4008
647416f9
KC		 4009DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
4010 i915_wedged_get, i915_wedged_set,
3a3b4f98 4011 "%llu\n");
f3cd474b 4012
647416f9
KC		 4013static int
4014i915_ring_stop_get(void *data, u64 *val)
e5eb3d63 4015{
647416f9 4016 struct drm_device *dev = data;
e277a1f8 4017 struct drm_i915_private *dev_priv = dev->dev_private;
e5eb3d63 4018
647416f9 4019 *val = dev_priv->gpu_error.stop_rings;
e5eb3d63 4020
647416f9 4021 return 0;
e5eb3d63
DV		 4022}
4023
647416f9
KC		 4024static int
4025i915_ring_stop_set(void *data, u64 val)
e5eb3d63 4026{
647416f9 4027 struct drm_device *dev = data;
e5eb3d63 4028 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 4029 int ret;
e5eb3d63 4030
647416f9 4031 DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val);
e5eb3d63 4032
22bcfc6a
DV		 4033 ret = mutex_lock_interruptible(&dev->struct_mutex);
4034 if (ret)
4035 return ret;
4036
99584db3 4037 dev_priv->gpu_error.stop_rings = val;
e5eb3d63
DV		 4038 mutex_unlock(&dev->struct_mutex);
4039
647416f9 4040 return 0;
e5eb3d63
DV		 4041}
4042
647416f9
KC		 4043DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops,
4044 i915_ring_stop_get, i915_ring_stop_set,
4045 "0x%08llx\n");
d5442303 4046
094f9a54
CW		 4047static int
4048i915_ring_missed_irq_get(void *data, u64 *val)
4049{
4050 struct drm_device *dev = data;
4051 struct drm_i915_private *dev_priv = dev->dev_private;
4052
4053 *val = dev_priv->gpu_error.missed_irq_rings;
4054 return 0;
4055}
4056
4057static int
4058i915_ring_missed_irq_set(void *data, u64 val)
4059{
4060 struct drm_device *dev = data;
4061 struct drm_i915_private *dev_priv = dev->dev_private;
4062 int ret;
4063
4064 /* Lock against concurrent debugfs callers */
4065 ret = mutex_lock_interruptible(&dev->struct_mutex);
4066 if (ret)
4067 return ret;
4068 dev_priv->gpu_error.missed_irq_rings = val;
4069 mutex_unlock(&dev->struct_mutex);
4070
4071 return 0;
4072}
4073
4074DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
4075 i915_ring_missed_irq_get, i915_ring_missed_irq_set,
4076 "0x%08llx\n");
4077
4078static int
4079i915_ring_test_irq_get(void *data, u64 *val)
4080{
4081 struct drm_device *dev = data;
4082 struct drm_i915_private *dev_priv = dev->dev_private;
4083
4084 *val = dev_priv->gpu_error.test_irq_rings;
4085
4086 return 0;
4087}
4088
4089static int
4090i915_ring_test_irq_set(void *data, u64 val)
4091{
4092 struct drm_device *dev = data;
4093 struct drm_i915_private *dev_priv = dev->dev_private;
4094 int ret;
4095
4096 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
4097
4098 /* Lock against concurrent debugfs callers */
4099 ret = mutex_lock_interruptible(&dev->struct_mutex);
4100 if (ret)
4101 return ret;
4102
4103 dev_priv->gpu_error.test_irq_rings = val;
4104 mutex_unlock(&dev->struct_mutex);
4105
4106 return 0;
4107}
4108
4109DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
4110 i915_ring_test_irq_get, i915_ring_test_irq_set,
4111 "0x%08llx\n");
4112
dd624afd
CW		 4113#define DROP_UNBOUND 0x1
4114#define DROP_BOUND 0x2
4115#define DROP_RETIRE 0x4
4116#define DROP_ACTIVE 0x8
4117#define DROP_ALL (DROP_UNBOUND | \
4118 DROP_BOUND | \
4119 DROP_RETIRE | \
4120 DROP_ACTIVE)
647416f9
KC		 4121static int
4122i915_drop_caches_get(void *data, u64 *val)
dd624afd 4123{
647416f9 4124 *val = DROP_ALL;
dd624afd 4125
647416f9 4126 return 0;
dd624afd
CW		 4127}
4128
647416f9
KC		 4129static int
4130i915_drop_caches_set(void *data, u64 val)
dd624afd 4131{
647416f9 4132 struct drm_device *dev = data;
dd624afd 4133 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 4134 int ret;
dd624afd 4135
2f9fe5ff 4136 DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
dd624afd
CW		 4137
4138 /* No need to check and wait for gpu resets, only libdrm auto-restarts
4139 * on ioctls on -EAGAIN. */
4140 ret = mutex_lock_interruptible(&dev->struct_mutex);
4141 if (ret)
4142 return ret;
4143
4144 if (val & DROP_ACTIVE) {
4145 ret = i915_gpu_idle(dev);
4146 if (ret)
4147 goto unlock;
4148 }
4149
4150 if (val & (DROP_RETIRE | DROP_ACTIVE))
4151 i915_gem_retire_requests(dev);
4152
21ab4e74
CW		 4153 if (val & DROP_BOUND)
4154 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND);
4ad72b7f 4155
21ab4e74
CW		 4156 if (val & DROP_UNBOUND)
4157 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND);
dd624afd
CW		 4158
4159unlock:
4160 mutex_unlock(&dev->struct_mutex);
4161
647416f9 4162 return ret;
dd624afd
CW		 4163}
4164
647416f9
KC		 4165DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
4166 i915_drop_caches_get, i915_drop_caches_set,
4167 "0x%08llx\n");
dd624afd 4168
647416f9
KC		 4169static int
4170i915_max_freq_get(void *data, u64 *val)
358733e9 4171{
647416f9 4172 struct drm_device *dev = data;
e277a1f8 4173 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 4174 int ret;
004777cb 4175
daa3afb2 4176 if (INTEL_INFO(dev)->gen < 6)
004777cb
DV		 4177 return -ENODEV;
4178
5c9669ce
TR		 4179 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4180
4fc688ce 4181 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 4182 if (ret)
4183 return ret;
358733e9 4184
7c59a9c1 4185 *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
4fc688ce 4186 mutex_unlock(&dev_priv->rps.hw_lock);
358733e9 4187
647416f9 4188 return 0;
358733e9
JB		 4189}
4190
647416f9
KC		 4191static int
4192i915_max_freq_set(void *data, u64 val)
358733e9 4193{
647416f9 4194 struct drm_device *dev = data;
358733e9 4195 struct drm_i915_private *dev_priv = dev->dev_private;
bc4d91f6 4196 u32 hw_max, hw_min;
647416f9 4197 int ret;
004777cb 4198
daa3afb2 4199 if (INTEL_INFO(dev)->gen < 6)
004777cb 4200 return -ENODEV;
358733e9 4201
5c9669ce
TR		 4202 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4203
647416f9 4204 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
358733e9 4205
4fc688ce 4206 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 4207 if (ret)
4208 return ret;
4209
358733e9
JB		 4210 /*
4211 * Turbo will still be enabled, but won't go above the set value.
4212 */
bc4d91f6 4213 val = intel_freq_opcode(dev_priv, val);
dd0a1aa1 4214
bc4d91f6
AG		 4215 hw_max = dev_priv->rps.max_freq;
4216 hw_min = dev_priv->rps.min_freq;
dd0a1aa1 4217
b39fb297 4218 if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
dd0a1aa1
JM		 4219 mutex_unlock(&dev_priv->rps.hw_lock);
4220 return -EINVAL;
0a073b84
JB		 4221 }
4222
b39fb297 4223 dev_priv->rps.max_freq_softlimit = val;
dd0a1aa1 4224
ffe02b40 4225 intel_set_rps(dev, val);
dd0a1aa1 4226
4fc688ce 4227 mutex_unlock(&dev_priv->rps.hw_lock);
358733e9 4228
647416f9 4229 return 0;
358733e9
JB		 4230}
4231
647416f9
KC		 4232DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
4233 i915_max_freq_get, i915_max_freq_set,
3a3b4f98 4234 "%llu\n");
358733e9 4235
647416f9
KC		 4236static int
4237i915_min_freq_get(void *data, u64 *val)
1523c310 4238{
647416f9 4239 struct drm_device *dev = data;
e277a1f8 4240 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 4241 int ret;
004777cb 4242
daa3afb2 4243 if (INTEL_INFO(dev)->gen < 6)
004777cb
DV		 4244 return -ENODEV;
4245
5c9669ce
TR		 4246 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4247
4fc688ce 4248 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 4249 if (ret)
4250 return ret;
1523c310 4251
7c59a9c1 4252 *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
4fc688ce 4253 mutex_unlock(&dev_priv->rps.hw_lock);
1523c310 4254
647416f9 4255 return 0;
1523c310
JB		 4256}
4257
647416f9
KC		 4258static int
4259i915_min_freq_set(void *data, u64 val)
1523c310 4260{
647416f9 4261 struct drm_device *dev = data;
1523c310 4262 struct drm_i915_private *dev_priv = dev->dev_private;
bc4d91f6 4263 u32 hw_max, hw_min;
647416f9 4264 int ret;
004777cb 4265
daa3afb2 4266 if (INTEL_INFO(dev)->gen < 6)
004777cb 4267 return -ENODEV;
1523c310 4268
5c9669ce
TR		 4269 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4270
647416f9 4271 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
1523c310 4272
4fc688ce 4273 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 4274 if (ret)
4275 return ret;
4276
1523c310
JB		 4277 /*
4278 * Turbo will still be enabled, but won't go below the set value.
4279 */
bc4d91f6 4280 val = intel_freq_opcode(dev_priv, val);
dd0a1aa1 4281
bc4d91f6
AG		 4282 hw_max = dev_priv->rps.max_freq;
4283 hw_min = dev_priv->rps.min_freq;
dd0a1aa1 4284
b39fb297 4285 if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
dd0a1aa1
JM		 4286 mutex_unlock(&dev_priv->rps.hw_lock);
4287 return -EINVAL;
0a073b84 4288 }
dd0a1aa1 4289
b39fb297 4290 dev_priv->rps.min_freq_softlimit = val;
dd0a1aa1 4291
ffe02b40 4292 intel_set_rps(dev, val);
dd0a1aa1 4293
4fc688ce 4294 mutex_unlock(&dev_priv->rps.hw_lock);
1523c310 4295
647416f9 4296 return 0;
1523c310
JB		 4297}
4298
647416f9
KC		 4299DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
4300 i915_min_freq_get, i915_min_freq_set,
3a3b4f98 4301 "%llu\n");
1523c310 4302
647416f9
KC		 4303static int
4304i915_cache_sharing_get(void *data, u64 *val)
07b7ddd9 4305{
647416f9 4306 struct drm_device *dev = data;
e277a1f8 4307 struct drm_i915_private *dev_priv = dev->dev_private;
07b7ddd9 4308 u32 snpcr;
647416f9 4309 int ret;
07b7ddd9 4310
004777cb
DV		 4311 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
4312 return -ENODEV;
4313
22bcfc6a
DV		 4314 ret = mutex_lock_interruptible(&dev->struct_mutex);
4315 if (ret)
4316 return ret;
c8c8fb33 4317 intel_runtime_pm_get(dev_priv);
22bcfc6a 4318
07b7ddd9 4319 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
c8c8fb33
PZ		 4320
4321 intel_runtime_pm_put(dev_priv);
07b7ddd9
JB		 4322 mutex_unlock(&dev_priv->dev->struct_mutex);
4323
647416f9 4324 *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
07b7ddd9 4325
647416f9 4326 return 0;
07b7ddd9
JB		 4327}
4328
647416f9
KC		 4329static int
4330i915_cache_sharing_set(void *data, u64 val)
07b7ddd9 4331{
647416f9 4332 struct drm_device *dev = data;
07b7ddd9 4333 struct drm_i915_private *dev_priv = dev->dev_private;
07b7ddd9 4334 u32 snpcr;
07b7ddd9 4335
004777cb
DV		 4336 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
4337 return -ENODEV;
4338
647416f9 4339 if (val > 3)
07b7ddd9
JB		 4340 return -EINVAL;
4341
c8c8fb33 4342 intel_runtime_pm_get(dev_priv);
647416f9 4343 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
07b7ddd9
JB		 4344
4345 /* Update the cache sharing policy here as well */
4346 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4347 snpcr &= ~GEN6_MBC_SNPCR_MASK;
4348 snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
4349 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
4350
c8c8fb33 4351 intel_runtime_pm_put(dev_priv);
647416f9 4352 return 0;
07b7ddd9
JB		 4353}
4354
647416f9
KC		 4355DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
4356 i915_cache_sharing_get, i915_cache_sharing_set,
4357 "%llu\n");
07b7ddd9 4358
3873218f
JM		 4359static int i915_sseu_status(struct seq_file *m, void *unused)
4360{
4361 struct drm_info_node *node = (struct drm_info_node *) m->private;
4362 struct drm_device *dev = node->minor->dev;
7f992aba
JM		 4363 struct drm_i915_private *dev_priv = dev->dev_private;
4364 unsigned int s_tot = 0, ss_tot = 0, ss_per = 0, eu_tot = 0, eu_per = 0;
3873218f
JM		 4365
4366 if (INTEL_INFO(dev)->gen < 9)
4367 return -ENODEV;
4368
4369 seq_puts(m, "SSEU Device Info\n");
4370 seq_printf(m, " Available Slice Total: %u\n",
4371 INTEL_INFO(dev)->slice_total);
4372 seq_printf(m, " Available Subslice Total: %u\n",
4373 INTEL_INFO(dev)->subslice_total);
4374 seq_printf(m, " Available Subslice Per Slice: %u\n",
4375 INTEL_INFO(dev)->subslice_per_slice);
4376 seq_printf(m, " Available EU Total: %u\n",
4377 INTEL_INFO(dev)->eu_total);
4378 seq_printf(m, " Available EU Per Subslice: %u\n",
4379 INTEL_INFO(dev)->eu_per_subslice);
4380 seq_printf(m, " Has Slice Power Gating: %s\n",
4381 yesno(INTEL_INFO(dev)->has_slice_pg));
4382 seq_printf(m, " Has Subslice Power Gating: %s\n",
4383 yesno(INTEL_INFO(dev)->has_subslice_pg));
4384 seq_printf(m, " Has EU Power Gating: %s\n",
4385 yesno(INTEL_INFO(dev)->has_eu_pg));
4386
7f992aba
JM		 4387 seq_puts(m, "SSEU Device Status\n");
4388 if (IS_SKYLAKE(dev)) {
4389 const int s_max = 3, ss_max = 4;
4390 int s, ss;
4391 u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
4392
4393 s_reg[0] = I915_READ(GEN9_SLICE0_PGCTL_ACK);
4394 s_reg[1] = I915_READ(GEN9_SLICE1_PGCTL_ACK);
4395 s_reg[2] = I915_READ(GEN9_SLICE2_PGCTL_ACK);
4396 eu_reg[0] = I915_READ(GEN9_SLICE0_SS01_EU_PGCTL_ACK);
4397 eu_reg[1] = I915_READ(GEN9_SLICE0_SS23_EU_PGCTL_ACK);
4398 eu_reg[2] = I915_READ(GEN9_SLICE1_SS01_EU_PGCTL_ACK);
4399 eu_reg[3] = I915_READ(GEN9_SLICE1_SS23_EU_PGCTL_ACK);
4400 eu_reg[4] = I915_READ(GEN9_SLICE2_SS01_EU_PGCTL_ACK);
4401 eu_reg[5] = I915_READ(GEN9_SLICE2_SS23_EU_PGCTL_ACK);
4402 eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
4403 GEN9_PGCTL_SSA_EU19_ACK |
4404 GEN9_PGCTL_SSA_EU210_ACK |
4405 GEN9_PGCTL_SSA_EU311_ACK;
4406 eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
4407 GEN9_PGCTL_SSB_EU19_ACK |
4408 GEN9_PGCTL_SSB_EU210_ACK |
4409 GEN9_PGCTL_SSB_EU311_ACK;
4410
4411 for (s = 0; s < s_max; s++) {
4412 if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
4413 /* skip disabled slice */
4414 continue;
4415
4416 s_tot++;
4417 ss_per = INTEL_INFO(dev)->subslice_per_slice;
4418 ss_tot += ss_per;
4419 for (ss = 0; ss < ss_max; ss++) {
4420 unsigned int eu_cnt;
4421
4422 eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
4423 eu_mask[ss%2]);
4424 eu_tot += eu_cnt;
4425 eu_per = max(eu_per, eu_cnt);
4426 }
4427 }
4428 }
4429 seq_printf(m, " Enabled Slice Total: %u\n", s_tot);
4430 seq_printf(m, " Enabled Subslice Total: %u\n", ss_tot);
4431 seq_printf(m, " Enabled Subslice Per Slice: %u\n", ss_per);
4432 seq_printf(m, " Enabled EU Total: %u\n", eu_tot);
4433 seq_printf(m, " Enabled EU Per Subslice: %u\n", eu_per);
4434
3873218f
JM		 4435 return 0;
4436}
4437
6d794d42
BW		 4438static int i915_forcewake_open(struct inode *inode, struct file *file)
4439{
4440 struct drm_device *dev = inode->i_private;
4441 struct drm_i915_private *dev_priv = dev->dev_private;
6d794d42 4442
075edca4 4443 if (INTEL_INFO(dev)->gen < 6)
6d794d42
BW		 4444 return 0;
4445
6daccb0b 4446 intel_runtime_pm_get(dev_priv);
59bad947 4447 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6d794d42
BW		 4448
4449 return 0;
4450}
4451
c43b5634 4452static int i915_forcewake_release(struct inode *inode, struct file *file)
6d794d42
BW		 4453{
4454 struct drm_device *dev = inode->i_private;
4455 struct drm_i915_private *dev_priv = dev->dev_private;
4456
075edca4 4457 if (INTEL_INFO(dev)->gen < 6)
6d794d42
BW		 4458 return 0;
4459
59bad947 4460 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6daccb0b 4461 intel_runtime_pm_put(dev_priv);
6d794d42
BW		 4462
4463 return 0;
4464}
4465
4466static const struct file_operations i915_forcewake_fops = {
4467 .owner = THIS_MODULE,
4468 .open = i915_forcewake_open,
4469 .release = i915_forcewake_release,
4470};
4471
4472static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
4473{
4474 struct drm_device *dev = minor->dev;
4475 struct dentry *ent;
4476
4477 ent = debugfs_create_file("i915_forcewake_user",
8eb57294 4478 S_IRUSR,
6d794d42
BW		 4479 root, dev,
4480 &i915_forcewake_fops);
f3c5fe97
WY		 4481 if (!ent)
4482 return -ENOMEM;
6d794d42 4483
8eb57294 4484 return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
6d794d42
BW		 4485}
4486
6a9c308d
DV		 4487static int i915_debugfs_create(struct dentry *root,
4488 struct drm_minor *minor,
4489 const char *name,
4490 const struct file_operations *fops)
07b7ddd9
JB		 4491{
4492 struct drm_device *dev = minor->dev;
4493 struct dentry *ent;
4494
6a9c308d 4495 ent = debugfs_create_file(name,
07b7ddd9
JB		 4496 S_IRUGO | S_IWUSR,
4497 root, dev,
6a9c308d 4498 fops);
f3c5fe97
WY		 4499 if (!ent)
4500 return -ENOMEM;
07b7ddd9 4501
6a9c308d 4502 return drm_add_fake_info_node(minor, ent, fops);
07b7ddd9
JB		 4503}
4504
06c5bf8c 4505static const struct drm_info_list i915_debugfs_list[] = {
311bd68e 4506 {"i915_capabilities", i915_capabilities, 0},
73aa808f 4507 {"i915_gem_objects", i915_gem_object_info, 0},
08c18323 4508 {"i915_gem_gtt", i915_gem_gtt_info, 0},
1b50247a 4509 {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
433e12f7 4510 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
433e12f7 4511 {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
6d2b8885 4512 {"i915_gem_stolen", i915_gem_stolen_list_info },
4e5359cd 4513 {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
2017263e
BG		 4514 {"i915_gem_request", i915_gem_request_info, 0},
4515 {"i915_gem_seqno", i915_gem_seqno_info, 0},
a6172a80 4516 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
2017263e 4517 {"i915_gem_interrupt", i915_interrupt_info, 0},
1ec14ad3
CW		 4518 {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
4519 {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
4520 {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
9010ebfd 4521 {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
493018dc 4522 {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0},
adb4bd12 4523 {"i915_frequency_info", i915_frequency_info, 0},
f654449a 4524 {"i915_hangcheck_info", i915_hangcheck_info, 0},
f97108d1 4525 {"i915_drpc_info", i915_drpc_info, 0},
7648fa99 4526 {"i915_emon_status", i915_emon_status, 0},
23b2f8bb 4527 {"i915_ring_freq_table", i915_ring_freq_table, 0},
b5e50c3f 4528 {"i915_fbc_status", i915_fbc_status, 0},
92d44621 4529 {"i915_ips_status", i915_ips_status, 0},
4a9bef37 4530 {"i915_sr_status", i915_sr_status, 0},
44834a67 4531 {"i915_opregion", i915_opregion, 0},
37811fcc 4532 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
e76d3630 4533 {"i915_context_status", i915_context_status, 0},
c0ab1ae9 4534 {"i915_dump_lrc", i915_dump_lrc, 0},
4ba70e44 4535 {"i915_execlists", i915_execlists, 0},
f65367b5 4536 {"i915_forcewake_domains", i915_forcewake_domains, 0},
ea16a3cd 4537 {"i915_swizzle_info", i915_swizzle_info, 0},
3cf17fc5 4538 {"i915_ppgtt_info", i915_ppgtt_info, 0},
63573eb7 4539 {"i915_llc", i915_llc, 0},
e91fd8c6 4540 {"i915_edp_psr_status", i915_edp_psr_status, 0},
d2e216d0 4541 {"i915_sink_crc_eDP1", i915_sink_crc, 0},
ec013e7f 4542 {"i915_energy_uJ", i915_energy_uJ, 0},
371db66a 4543 {"i915_pc8_status", i915_pc8_status, 0},
1da51581 4544 {"i915_power_domain_info", i915_power_domain_info, 0},
53f5e3ca 4545 {"i915_display_info", i915_display_info, 0},
e04934cf 4546 {"i915_semaphore_status", i915_semaphore_status, 0},
728e29d7 4547 {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
11bed958 4548 {"i915_dp_mst_info", i915_dp_mst_info, 0},
1ed1ef9d 4549 {"i915_wa_registers", i915_wa_registers, 0},
c5511e44 4550 {"i915_ddb_info", i915_ddb_info, 0},
3873218f 4551 {"i915_sseu_status", i915_sseu_status, 0},
2017263e 4552};
27c202ad 4553#define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
2017263e 4554
06c5bf8c 4555static const struct i915_debugfs_files {
34b9674c
DV		 4556 const char *name;
4557 const struct file_operations *fops;
4558} i915_debugfs_files[] = {
4559 {"i915_wedged", &i915_wedged_fops},
4560 {"i915_max_freq", &i915_max_freq_fops},
4561 {"i915_min_freq", &i915_min_freq_fops},
4562 {"i915_cache_sharing", &i915_cache_sharing_fops},
4563 {"i915_ring_stop", &i915_ring_stop_fops},
094f9a54
CW		 4564 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
4565 {"i915_ring_test_irq", &i915_ring_test_irq_fops},
34b9674c
DV		 4566 {"i915_gem_drop_caches", &i915_drop_caches_fops},
4567 {"i915_error_state", &i915_error_state_fops},
4568 {"i915_next_seqno", &i915_next_seqno_fops},
bd9db02f 4569 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
369a1342
VS		 4570 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
4571 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
4572 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
da46f936 4573 {"i915_fbc_false_color", &i915_fbc_fc_fops},
34b9674c
DV		 4574};
4575
07144428
DL		 4576void intel_display_crc_init(struct drm_device *dev)
4577{
4578 struct drm_i915_private *dev_priv = dev->dev_private;
b378360e 4579 enum pipe pipe;
07144428 4580
055e393f 4581 for_each_pipe(dev_priv, pipe) {
b378360e 4582 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
07144428 4583
d538bbdf
DL		 4584 pipe_crc->opened = false;
4585 spin_lock_init(&pipe_crc->lock);
07144428
DL		 4586 init_waitqueue_head(&pipe_crc->wq);
4587 }
4588}
4589
27c202ad 4590int i915_debugfs_init(struct drm_minor *minor)
2017263e 4591{
34b9674c 4592 int ret, i;
f3cd474b 4593
6d794d42 4594 ret = i915_forcewake_create(minor->debugfs_root, minor);
358733e9
JB		 4595 if (ret)
4596 return ret;
6a9c308d 4597
07144428
DL		 4598 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
4599 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
4600 if (ret)
4601 return ret;
4602 }
4603
34b9674c
DV		 4604 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
4605 ret = i915_debugfs_create(minor->debugfs_root, minor,
4606 i915_debugfs_files[i].name,
4607 i915_debugfs_files[i].fops);
4608 if (ret)
4609 return ret;
4610 }
40633219 4611
27c202ad
BG		 4612 return drm_debugfs_create_files(i915_debugfs_list,
4613 I915_DEBUGFS_ENTRIES,
2017263e
BG		 4614 minor->debugfs_root, minor);
4615}
4616
27c202ad 4617void i915_debugfs_cleanup(struct drm_minor *minor)
2017263e 4618{
34b9674c
DV		 4619 int i;
4620
27c202ad
BG		 4621 drm_debugfs_remove_files(i915_debugfs_list,
4622 I915_DEBUGFS_ENTRIES, minor);
07144428 4623
6d794d42
BW		 4624 drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
4625 1, minor);
07144428 4626
e309a997 4627 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
07144428
DL		 4628 struct drm_info_list *info_list =
4629 (struct drm_info_list *)&i915_pipe_crc_data[i];
4630
4631 drm_debugfs_remove_files(info_list, 1, minor);
4632 }
4633
34b9674c
DV		 4634 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
4635 struct drm_info_list *info_list =
4636 (struct drm_info_list *) i915_debugfs_files[i].fops;
4637
4638 drm_debugfs_remove_files(info_list, 1, minor);
4639 }
2017263e 4640}
Linux kernel - Deliverables
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