[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_debugfs.c

/*
 * Copyright © 2008 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 *
 * Authors:
 *    Eric Anholt <eric@anholt.net>
 *    Keith Packard <keithp@keithp.com>
 *
 */

#include <linux/seq_file.h>
#include "drmP.h"
#include "drm.h"
#include "i915_drm.h"
#include "i915_drv.h"

#define DRM_I915_RING_DEBUG 1


#if defined(CONFIG_DEBUG_FS)

#define ACTIVE_LIST	1
#define FLUSHING_LIST	2
#define INACTIVE_LIST	3

static const char *get_pin_flag(struct drm_i915_gem_object *obj_priv)
{
	if (obj_priv->user_pin_count > 0)
		return "P";
	else if (obj_priv->pin_count > 0)
		return "p";
	else
		return " ";
}

static const char *get_tiling_flag(struct drm_i915_gem_object *obj_priv)
{
    switch (obj_priv->tiling_mode) {
    default:
    case I915_TILING_NONE: return " ";
    case I915_TILING_X: return "X";
    case I915_TILING_Y: return "Y";
    }
}

static int i915_gem_object_list_info(struct seq_file *m, void *data)
{
	struct drm_info_node *node = (struct drm_info_node *) m->private;
	uintptr_t list = (uintptr_t) node->info_ent->data;
	struct list_head *head;
	struct drm_device *dev = node->minor->dev;
	drm_i915_private_t *dev_priv = dev->dev_private;
	struct drm_i915_gem_object *obj_priv;
	spinlock_t *lock = NULL;

	switch (list) {
	case ACTIVE_LIST:
		seq_printf(m, "Active:\n");
		lock = &dev_priv->mm.active_list_lock;
		head = &dev_priv->mm.active_list;
		break;
	case INACTIVE_LIST:
		seq_printf(m, "Inactive:\n");
		head = &dev_priv->mm.inactive_list;
		break;
	case FLUSHING_LIST:
		seq_printf(m, "Flushing:\n");
		head = &dev_priv->mm.flushing_list;
		break;
	default:
		DRM_INFO("Ooops, unexpected list\n");
		return 0;
	}

	if (lock)
		spin_lock(lock);
	list_for_each_entry(obj_priv, head, list)
	{
		struct drm_gem_object *obj = obj_priv->obj;

		seq_printf(m, "    %p: %s %8zd %08x %08x %d %s",
			   obj,
			   get_pin_flag(obj_priv),
			   obj->size,
			   obj->read_domains, obj->write_domain,
			   obj_priv->last_rendering_seqno,
			   obj_priv->dirty ? "dirty" : "");

		if (obj->name)
			seq_printf(m, " (name: %d)", obj->name);
		if (obj_priv->fence_reg != I915_FENCE_REG_NONE)
			seq_printf(m, " (fence: %d)", obj_priv->fence_reg);
		if (obj_priv->gtt_space != NULL)
			seq_printf(m, " (gtt_offset: %08x)", obj_priv->gtt_offset);

		seq_printf(m, "\n");
	}

	if (lock)
	    spin_unlock(lock);
	return 0;
}

static int i915_gem_request_info(struct seq_file *m, void *data)
{
	struct drm_info_node *node = (struct drm_info_node *) m->private;
	struct drm_device *dev = node->minor->dev;
	drm_i915_private_t *dev_priv = dev->dev_private;
	struct drm_i915_gem_request *gem_request;

	seq_printf(m, "Request:\n");
	list_for_each_entry(gem_request, &dev_priv->mm.request_list, list) {
		seq_printf(m, "    %d @ %d\n",
			   gem_request->seqno,
			   (int) (jiffies - gem_request->emitted_jiffies));
	}
	return 0;
}

static int i915_gem_seqno_info(struct seq_file *m, void *data)
{
	struct drm_info_node *node = (struct drm_info_node *) m->private;
	struct drm_device *dev = node->minor->dev;
	drm_i915_private_t *dev_priv = dev->dev_private;

	if (dev_priv->hw_status_page != NULL) {
		seq_printf(m, "Current sequence: %d\n",
			   i915_get_gem_seqno(dev));
	} else {
		seq_printf(m, "Current sequence: hws uninitialized\n");
	}
	seq_printf(m, "Waiter sequence:  %d\n",
			dev_priv->mm.waiting_gem_seqno);
	seq_printf(m, "IRQ sequence:     %d\n", dev_priv->mm.irq_gem_seqno);
	return 0;
}


static int i915_interrupt_info(struct seq_file *m, void *data)
{
	struct drm_info_node *node = (struct drm_info_node *) m->private;
	struct drm_device *dev = node->minor->dev;
	drm_i915_private_t *dev_priv = dev->dev_private;

	if (!IS_IGDNG(dev)) {
		seq_printf(m, "Interrupt enable:    %08x\n",
			   I915_READ(IER));
		seq_printf(m, "Interrupt identity:  %08x\n",
			   I915_READ(IIR));
		seq_printf(m, "Interrupt mask:      %08x\n",
			   I915_READ(IMR));
		seq_printf(m, "Pipe A stat:         %08x\n",
			   I915_READ(PIPEASTAT));
		seq_printf(m, "Pipe B stat:         %08x\n",
			   I915_READ(PIPEBSTAT));
	} else {
		seq_printf(m, "North Display Interrupt enable:		%08x\n",
			   I915_READ(DEIER));
		seq_printf(m, "North Display Interrupt identity:	%08x\n",
			   I915_READ(DEIIR));
		seq_printf(m, "North Display Interrupt mask:		%08x\n",
			   I915_READ(DEIMR));
		seq_printf(m, "South Display Interrupt enable:		%08x\n",
			   I915_READ(SDEIER));
		seq_printf(m, "South Display Interrupt identity:	%08x\n",
			   I915_READ(SDEIIR));
		seq_printf(m, "South Display Interrupt mask:		%08x\n",
			   I915_READ(SDEIMR));
		seq_printf(m, "Graphics Interrupt enable:		%08x\n",
			   I915_READ(GTIER));
		seq_printf(m, "Graphics Interrupt identity:		%08x\n",
			   I915_READ(GTIIR));
		seq_printf(m, "Graphics Interrupt mask:		%08x\n",
			   I915_READ(GTIMR));
	}
	seq_printf(m, "Interrupts received: %d\n",
		   atomic_read(&dev_priv->irq_received));
	if (dev_priv->hw_status_page != NULL) {
		seq_printf(m, "Current sequence:    %d\n",
			   i915_get_gem_seqno(dev));
	} else {
		seq_printf(m, "Current sequence:    hws uninitialized\n");
	}
	seq_printf(m, "Waiter sequence:     %d\n",
		   dev_priv->mm.waiting_gem_seqno);
	seq_printf(m, "IRQ sequence:        %d\n",
		   dev_priv->mm.irq_gem_seqno);
	return 0;
}

static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
{
	struct drm_info_node *node = (struct drm_info_node *) m->private;
	struct drm_device *dev = node->minor->dev;
	drm_i915_private_t *dev_priv = dev->dev_private;
	int i;

	seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
	seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
	for (i = 0; i < dev_priv->num_fence_regs; i++) {
		struct drm_gem_object *obj = dev_priv->fence_regs[i].obj;

		if (obj == NULL) {
			seq_printf(m, "Fenced object[%2d] = unused\n", i);
		} else {
			struct drm_i915_gem_object *obj_priv;

			obj_priv = obj->driver_private;
			seq_printf(m, "Fenced object[%2d] = %p: %s "
				   "%08x %08zx %08x %s %08x %08x %d",
				   i, obj, get_pin_flag(obj_priv),
				   obj_priv->gtt_offset,
				   obj->size, obj_priv->stride,
				   get_tiling_flag(obj_priv),
				   obj->read_domains, obj->write_domain,
				   obj_priv->last_rendering_seqno);
			if (obj->name)
				seq_printf(m, " (name: %d)", obj->name);
			seq_printf(m, "\n");
		}
	}

	return 0;
}

static int i915_hws_info(struct seq_file *m, void *data)
{
	struct drm_info_node *node = (struct drm_info_node *) m->private;
	struct drm_device *dev = node->minor->dev;
	drm_i915_private_t *dev_priv = dev->dev_private;
	int i;
	volatile u32 *hws;

	hws = (volatile u32 *)dev_priv->hw_status_page;
	if (hws == NULL)
		return 0;

	for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
		seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
			   i * 4,
			   hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
	}
	return 0;
}

static void i915_dump_pages(struct seq_file *m, struct page **pages, int page_count)
{
	int page, i;
	uint32_t *mem;

	for (page = 0; page < page_count; page++) {
		mem = kmap_atomic(pages[page], KM_USER0);
		for (i = 0; i < PAGE_SIZE; i += 4)
			seq_printf(m, "%08x :  %08x\n", i, mem[i / 4]);
		kunmap_atomic(pages[page], KM_USER0);
	}
}

static int i915_batchbuffer_info(struct seq_file *m, void *data)
{
	struct drm_info_node *node = (struct drm_info_node *) m->private;
	struct drm_device *dev = node->minor->dev;
	drm_i915_private_t *dev_priv = dev->dev_private;
	struct drm_gem_object *obj;
	struct drm_i915_gem_object *obj_priv;
	int ret;

	spin_lock(&dev_priv->mm.active_list_lock);

	list_for_each_entry(obj_priv, &dev_priv->mm.active_list, list) {
		obj = obj_priv->obj;
		if (obj->read_domains & I915_GEM_DOMAIN_COMMAND) {
		    ret = i915_gem_object_get_pages(obj);
		    if (ret) {
			    DRM_ERROR("Failed to get pages: %d\n", ret);
			    spin_unlock(&dev_priv->mm.active_list_lock);
			    return ret;
		    }

		    seq_printf(m, "--- gtt_offset = 0x%08x\n", obj_priv->gtt_offset);
		    i915_dump_pages(m, obj_priv->pages, obj->size / PAGE_SIZE);

		    i915_gem_object_put_pages(obj);
		}
	}

	spin_unlock(&dev_priv->mm.active_list_lock);

	return 0;
}

static int i915_ringbuffer_data(struct seq_file *m, void *data)
{
	struct drm_info_node *node = (struct drm_info_node *) m->private;
	struct drm_device *dev = node->minor->dev;
	drm_i915_private_t *dev_priv = dev->dev_private;
	u8 *virt;
	uint32_t *ptr, off;

	if (!dev_priv->ring.ring_obj) {
		seq_printf(m, "No ringbuffer setup\n");
		return 0;
	}

	virt = dev_priv->ring.virtual_start;

	for (off = 0; off < dev_priv->ring.Size; off += 4) {
		ptr = (uint32_t *)(virt + off);
		seq_printf(m, "%08x :  %08x\n", off, *ptr);
	}

	return 0;
}

static int i915_ringbuffer_info(struct seq_file *m, void *data)
{
	struct drm_info_node *node = (struct drm_info_node *) m->private;
	struct drm_device *dev = node->minor->dev;
	drm_i915_private_t *dev_priv = dev->dev_private;
	unsigned int head, tail;

	head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
	tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;

	seq_printf(m, "RingHead :  %08x\n", head);
	seq_printf(m, "RingTail :  %08x\n", tail);
	seq_printf(m, "RingSize :  %08lx\n", dev_priv->ring.Size);
	seq_printf(m, "Acthd :     %08x\n", I915_READ(IS_I965G(dev) ? ACTHD_I965 : ACTHD));

	return 0;
}

static int i915_error_state(struct seq_file *m, void *unused)
{
	struct drm_info_node *node = (struct drm_info_node *) m->private;
	struct drm_device *dev = node->minor->dev;
	drm_i915_private_t *dev_priv = dev->dev_private;
	struct drm_i915_error_state *error;
	unsigned long flags;

	spin_lock_irqsave(&dev_priv->error_lock, flags);
	if (!dev_priv->first_error) {
		seq_printf(m, "no error state collected\n");
		goto out;
	}

	error = dev_priv->first_error;

	seq_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec,
		   error->time.tv_usec);
	seq_printf(m, "EIR: 0x%08x\n", error->eir);
	seq_printf(m, "  PGTBL_ER: 0x%08x\n", error->pgtbl_er);
	seq_printf(m, "  INSTPM: 0x%08x\n", error->instpm);
	seq_printf(m, "  IPEIR: 0x%08x\n", error->ipeir);
	seq_printf(m, "  IPEHR: 0x%08x\n", error->ipehr);
	seq_printf(m, "  INSTDONE: 0x%08x\n", error->instdone);
	seq_printf(m, "  ACTHD: 0x%08x\n", error->acthd);
	if (IS_I965G(dev)) {
		seq_printf(m, "  INSTPS: 0x%08x\n", error->instps);
		seq_printf(m, "  INSTDONE1: 0x%08x\n", error->instdone1);
	}

out:
	spin_unlock_irqrestore(&dev_priv->error_lock, flags);

	return 0;
}

static int i915_registers_info(struct seq_file *m, void *data) {
	struct drm_info_node *node = (struct drm_info_node *) m->private;
	struct drm_device *dev = node->minor->dev;
	drm_i915_private_t *dev_priv = dev->dev_private;
	uint32_t reg;

#define DUMP_RANGE(start, end) \
	for (reg=start; reg < end; reg += 4) \
	seq_printf(m, "%08x\t%08x\n", reg, I915_READ(reg));

	DUMP_RANGE(0x00000, 0x00fff);   /* VGA registers */
	DUMP_RANGE(0x02000, 0x02fff);   /* instruction, memory, interrupt control registers */
	DUMP_RANGE(0x03000, 0x031ff);   /* FENCE and PPGTT control registers */
	DUMP_RANGE(0x03200, 0x03fff);   /* frame buffer compression registers */
	DUMP_RANGE(0x05000, 0x05fff);   /* I/O control registers */
	DUMP_RANGE(0x06000, 0x06fff);   /* clock control registers */
	DUMP_RANGE(0x07000, 0x07fff);   /* 3D internal debug registers */
	DUMP_RANGE(0x07400, 0x088ff);   /* GPE debug registers */
	DUMP_RANGE(0x0a000, 0x0afff);   /* display palette registers */
	DUMP_RANGE(0x10000, 0x13fff);   /* MMIO MCHBAR */
	DUMP_RANGE(0x30000, 0x3ffff);   /* overlay registers */
	DUMP_RANGE(0x60000, 0x6ffff);   /* display engine pipeline registers */
	DUMP_RANGE(0x70000, 0x72fff);   /* display and cursor registers */
	DUMP_RANGE(0x73000, 0x73fff);   /* performance counters */

	return 0;
}


static struct drm_info_list i915_debugfs_list[] = {
	{"i915_regs", i915_registers_info, 0},
	{"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
	{"i915_gem_flushing", i915_gem_object_list_info, 0, (void *) FLUSHING_LIST},
	{"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
	{"i915_gem_request", i915_gem_request_info, 0},
	{"i915_gem_seqno", i915_gem_seqno_info, 0},
	{"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
	{"i915_gem_interrupt", i915_interrupt_info, 0},
	{"i915_gem_hws", i915_hws_info, 0},
	{"i915_ringbuffer_data", i915_ringbuffer_data, 0},
	{"i915_ringbuffer_info", i915_ringbuffer_info, 0},
	{"i915_batchbuffers", i915_batchbuffer_info, 0},
	{"i915_error_state", i915_error_state, 0},
};
#define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)

int i915_debugfs_init(struct drm_minor *minor)
{
	return drm_debugfs_create_files(i915_debugfs_list,
					I915_DEBUGFS_ENTRIES,
					minor->debugfs_root, minor);
}

void i915_debugfs_cleanup(struct drm_minor *minor)
{
	drm_debugfs_remove_files(i915_debugfs_list,
				 I915_DEBUGFS_ENTRIES, minor);
}

#endif /* CONFIG_DEBUG_FS */
Commit	Line	Data
2017263e BG	1	/*
	2	* Copyright © 2008 Intel Corporation
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice (including the next
	12	* paragraph) shall be included in all copies or substantial portions of the
	13	* Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
	21	* IN THE SOFTWARE.
	22	*
	23	* Authors:
	24	* Eric Anholt <eric@anholt.net>
	25	* Keith Packard <keithp@keithp.com>
	26	*
	27	*/
	28
	29	#include <linux/seq_file.h>
	30	#include "drmP.h"
	31	#include "drm.h"
	32	#include "i915_drm.h"
	33	#include "i915_drv.h"
	34
	35	#define DRM_I915_RING_DEBUG 1
	36
	37
	38	#if defined(CONFIG_DEBUG_FS)
	39
433e12f7 BG	40	#define ACTIVE_LIST 1
	41	#define FLUSHING_LIST 2
	42	#define INACTIVE_LIST 3
2017263e	43
a6172a80 CW	44	static const char get_pin_flag(struct drm_i915_gem_object obj_priv)
	45	{
	46	if (obj_priv->user_pin_count > 0)
	47	return "P";
	48	else if (obj_priv->pin_count > 0)
	49	return "p";
	50	else
	51	return " ";
	52	}
	53
	54	static const char get_tiling_flag(struct drm_i915_gem_object obj_priv)
	55	{
	56	switch (obj_priv->tiling_mode) {
	57	default:
	58	case I915_TILING_NONE: return " ";
	59	case I915_TILING_X: return "X";
	60	case I915_TILING_Y: return "Y";
	61	}
	62	}
	63
433e12f7	64	static int i915_gem_object_list_info(struct seq_file m, void data)
2017263e BG	65	{
2017263e BG	66	struct drm_info_node node = (struct drm_info_node ) m->private;
433e12f7 BG	67	uintptr_t list = (uintptr_t) node->info_ent->data;
433e12f7 BG	68	struct list_head *head;
2017263e BG	69	struct drm_device *dev = node->minor->dev;
	70	drm_i915_private_t *dev_priv = dev->dev_private;
	71	struct drm_i915_gem_object *obj_priv;
5e118f41	72	spinlock_t *lock = NULL;
2017263e	73
433e12f7 BG	74	switch (list) {
	75	case ACTIVE_LIST:
	76	seq_printf(m, "Active:\n");
5e118f41	77	lock = &dev_priv->mm.active_list_lock;
433e12f7 BG	78	head = &dev_priv->mm.active_list;
	79	break;
	80	case INACTIVE_LIST:
a17458fc	81	seq_printf(m, "Inactive:\n");
433e12f7 BG	82	head = &dev_priv->mm.inactive_list;
	83	break;
	84	case FLUSHING_LIST:
	85	seq_printf(m, "Flushing:\n");
	86	head = &dev_priv->mm.flushing_list;
	87	break;
	88	default:
	89	DRM_INFO("Ooops, unexpected list\n");
	90	return 0;
2017263e	91	}
2017263e	92
a17458fc BG	93	if (lock)
a17458fc BG	94	spin_lock(lock);
433e12f7	95	list_for_each_entry(obj_priv, head, list)
2017263e BG	96	{
2017263e BG	97	struct drm_gem_object *obj = obj_priv->obj;
f4ceda89	98
725ceaa0	99	seq_printf(m, " %p: %s %8zd %08x %08x %d %s",
f4ceda89	100	obj,
a6172a80	101	get_pin_flag(obj_priv),
725ceaa0	102	obj->size,
f4ceda89	103	obj->read_domains, obj->write_domain,
725ceaa0 CW	104	obj_priv->last_rendering_seqno,
725ceaa0 CW	105	obj_priv->dirty ? "dirty" : "");
f4ceda89 EA	106
	107	if (obj->name)
	108	seq_printf(m, " (name: %d)", obj->name);
	109	if (obj_priv->fence_reg != I915_FENCE_REG_NONE)
a01c75b3 BG	110	seq_printf(m, " (fence: %d)", obj_priv->fence_reg);
	111	if (obj_priv->gtt_space != NULL)
	112	seq_printf(m, " (gtt_offset: %08x)", obj_priv->gtt_offset);
	113
f4ceda89	114	seq_printf(m, "\n");
2017263e	115	}
5e118f41 CW	116
	117	if (lock)
	118	spin_unlock(lock);
2017263e BG	119	return 0;
	120	}
	121
	122	static int i915_gem_request_info(struct seq_file m, void data)
	123	{
	124	struct drm_info_node node = (struct drm_info_node ) m->private;
	125	struct drm_device *dev = node->minor->dev;
	126	drm_i915_private_t *dev_priv = dev->dev_private;
	127	struct drm_i915_gem_request *gem_request;
	128
	129	seq_printf(m, "Request:\n");
	130	list_for_each_entry(gem_request, &dev_priv->mm.request_list, list) {
	131	seq_printf(m, " %d @ %d\n",
	132	gem_request->seqno,
	133	(int) (jiffies - gem_request->emitted_jiffies));
	134	}
	135	return 0;
	136	}
	137
	138	static int i915_gem_seqno_info(struct seq_file m, void data)
	139	{
	140	struct drm_info_node node = (struct drm_info_node ) m->private;
	141	struct drm_device *dev = node->minor->dev;
	142	drm_i915_private_t *dev_priv = dev->dev_private;
	143
	144	if (dev_priv->hw_status_page != NULL) {
	145	seq_printf(m, "Current sequence: %d\n",
	146	i915_get_gem_seqno(dev));
	147	} else {
	148	seq_printf(m, "Current sequence: hws uninitialized\n");
	149	}
	150	seq_printf(m, "Waiter sequence: %d\n",
	151	dev_priv->mm.waiting_gem_seqno);
	152	seq_printf(m, "IRQ sequence: %d\n", dev_priv->mm.irq_gem_seqno);
	153	return 0;
	154	}
	155
	156
	157	static int i915_interrupt_info(struct seq_file m, void data)
	158	{
	159	struct drm_info_node node = (struct drm_info_node ) m->private;
	160	struct drm_device *dev = node->minor->dev;
	161	drm_i915_private_t *dev_priv = dev->dev_private;
	162
5f6a1695 ZW	163	if (!IS_IGDNG(dev)) {
	164	seq_printf(m, "Interrupt enable: %08x\n",
	165	I915_READ(IER));
	166	seq_printf(m, "Interrupt identity: %08x\n",
	167	I915_READ(IIR));
	168	seq_printf(m, "Interrupt mask: %08x\n",
	169	I915_READ(IMR));
	170	seq_printf(m, "Pipe A stat: %08x\n",
	171	I915_READ(PIPEASTAT));
	172	seq_printf(m, "Pipe B stat: %08x\n",
	173	I915_READ(PIPEBSTAT));
	174	} else {
	175	seq_printf(m, "North Display Interrupt enable: %08x\n",
	176	I915_READ(DEIER));
	177	seq_printf(m, "North Display Interrupt identity: %08x\n",
	178	I915_READ(DEIIR));
	179	seq_printf(m, "North Display Interrupt mask: %08x\n",
	180	I915_READ(DEIMR));
	181	seq_printf(m, "South Display Interrupt enable: %08x\n",
	182	I915_READ(SDEIER));
	183	seq_printf(m, "South Display Interrupt identity: %08x\n",
	184	I915_READ(SDEIIR));
	185	seq_printf(m, "South Display Interrupt mask: %08x\n",
	186	I915_READ(SDEIMR));
	187	seq_printf(m, "Graphics Interrupt enable: %08x\n",
	188	I915_READ(GTIER));
	189	seq_printf(m, "Graphics Interrupt identity: %08x\n",
	190	I915_READ(GTIIR));
	191	seq_printf(m, "Graphics Interrupt mask: %08x\n",
	192	I915_READ(GTIMR));
	193	}
2017263e BG	194	seq_printf(m, "Interrupts received: %d\n",
	195	atomic_read(&dev_priv->irq_received));
	196	if (dev_priv->hw_status_page != NULL) {
	197	seq_printf(m, "Current sequence: %d\n",
	198	i915_get_gem_seqno(dev));
	199	} else {
	200	seq_printf(m, "Current sequence: hws uninitialized\n");
	201	}
	202	seq_printf(m, "Waiter sequence: %d\n",
	203	dev_priv->mm.waiting_gem_seqno);
	204	seq_printf(m, "IRQ sequence: %d\n",
	205	dev_priv->mm.irq_gem_seqno);
	206	return 0;
	207	}
	208
a6172a80 CW	209	static int i915_gem_fence_regs_info(struct seq_file m, void data)
	210	{
	211	struct drm_info_node node = (struct drm_info_node ) m->private;
	212	struct drm_device *dev = node->minor->dev;
	213	drm_i915_private_t *dev_priv = dev->dev_private;
	214	int i;
	215
	216	seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
	217	seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
	218	for (i = 0; i < dev_priv->num_fence_regs; i++) {
	219	struct drm_gem_object *obj = dev_priv->fence_regs[i].obj;
	220
	221	if (obj == NULL) {
	222	seq_printf(m, "Fenced object[%2d] = unused\n", i);
	223	} else {
	224	struct drm_i915_gem_object *obj_priv;
	225
	226	obj_priv = obj->driver_private;
	227	seq_printf(m, "Fenced object[%2d] = %p: %s "
0b4d569d	228	"%08x %08zx %08x %s %08x %08x %d",
a6172a80 CW	229	i, obj, get_pin_flag(obj_priv),
	230	obj_priv->gtt_offset,
	231	obj->size, obj_priv->stride,
	232	get_tiling_flag(obj_priv),
	233	obj->read_domains, obj->write_domain,
	234	obj_priv->last_rendering_seqno);
	235	if (obj->name)
	236	seq_printf(m, " (name: %d)", obj->name);
	237	seq_printf(m, "\n");
	238	}
	239	}
	240
	241	return 0;
	242	}
	243
2017263e BG	244	static int i915_hws_info(struct seq_file m, void data)
	245	{
	246	struct drm_info_node node = (struct drm_info_node ) m->private;
	247	struct drm_device *dev = node->minor->dev;
	248	drm_i915_private_t *dev_priv = dev->dev_private;
	249	int i;
	250	volatile u32 *hws;
	251
	252	hws = (volatile u32 *)dev_priv->hw_status_page;
	253	if (hws == NULL)
	254	return 0;
	255
	256	for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
	257	seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
	258	i * 4,
	259	hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
	260	}
	261	return 0;
	262	}
	263
6911a9b8 BG	264	static void i915_dump_pages(struct seq_file m, struct page *pages, int page_count)
	265	{
	266	int page, i;
	267	uint32_t *mem;
	268
	269	for (page = 0; page < page_count; page++) {
ba86bf8b	270	mem = kmap_atomic(pages[page], KM_USER0);
6911a9b8 BG	271	for (i = 0; i < PAGE_SIZE; i += 4)
6911a9b8 BG	272	seq_printf(m, "%08x : %08x\n", i, mem[i / 4]);
ba86bf8b	273	kunmap_atomic(pages[page], KM_USER0);
6911a9b8 BG	274	}
	275	}
	276
	277	static int i915_batchbuffer_info(struct seq_file m, void data)
	278	{
	279	struct drm_info_node node = (struct drm_info_node ) m->private;
	280	struct drm_device *dev = node->minor->dev;
	281	drm_i915_private_t *dev_priv = dev->dev_private;
	282	struct drm_gem_object *obj;
	283	struct drm_i915_gem_object *obj_priv;
	284	int ret;
	285
	286	spin_lock(&dev_priv->mm.active_list_lock);
	287
	288	list_for_each_entry(obj_priv, &dev_priv->mm.active_list, list) {
	289	obj = obj_priv->obj;
	290	if (obj->read_domains & I915_GEM_DOMAIN_COMMAND) {
	291	ret = i915_gem_object_get_pages(obj);
	292	if (ret) {
	293	DRM_ERROR("Failed to get pages: %d\n", ret);
	294	spin_unlock(&dev_priv->mm.active_list_lock);
	295	return ret;
	296	}
	297
	298	seq_printf(m, "--- gtt_offset = 0x%08x\n", obj_priv->gtt_offset);
	299	i915_dump_pages(m, obj_priv->pages, obj->size / PAGE_SIZE);
	300
	301	i915_gem_object_put_pages(obj);
	302	}
	303	}
	304
	305	spin_unlock(&dev_priv->mm.active_list_lock);
	306
	307	return 0;
	308	}
	309
	310	static int i915_ringbuffer_data(struct seq_file m, void data)
	311	{
	312	struct drm_info_node node = (struct drm_info_node ) m->private;
	313	struct drm_device *dev = node->minor->dev;
	314	drm_i915_private_t *dev_priv = dev->dev_private;
	315	u8 *virt;
	316	uint32_t *ptr, off;
	317
	318	if (!dev_priv->ring.ring_obj) {
	319	seq_printf(m, "No ringbuffer setup\n");
	320	return 0;
	321	}
	322
	323	virt = dev_priv->ring.virtual_start;
	324
	325	for (off = 0; off < dev_priv->ring.Size; off += 4) {
	326	ptr = (uint32_t *)(virt + off);
	327	seq_printf(m, "%08x : %08x\n", off, *ptr);
	328	}
	329
	330	return 0;
	331	}
	332
	333	static int i915_ringbuffer_info(struct seq_file m, void data)
	334	{
	335	struct drm_info_node node = (struct drm_info_node ) m->private;
	336	struct drm_device *dev = node->minor->dev;
	337	drm_i915_private_t *dev_priv = dev->dev_private;
0ef82af7	338	unsigned int head, tail;
6911a9b8 BG	339
	340	head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
	341	tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
6911a9b8 BG	342
	343	seq_printf(m, "RingHead : %08x\n", head);
	344	seq_printf(m, "RingTail : %08x\n", tail);
6911a9b8	345	seq_printf(m, "RingSize : %08lx\n", dev_priv->ring.Size);
76cff81a	346	seq_printf(m, "Acthd : %08x\n", I915_READ(IS_I965G(dev) ? ACTHD_I965 : ACTHD));
6911a9b8 BG	347
	348	return 0;
	349	}
	350
63eeaf38 JB	351	static int i915_error_state(struct seq_file m, void unused)
	352	{
	353	struct drm_info_node node = (struct drm_info_node ) m->private;
	354	struct drm_device *dev = node->minor->dev;
	355	drm_i915_private_t *dev_priv = dev->dev_private;
	356	struct drm_i915_error_state *error;
	357	unsigned long flags;
	358
	359	spin_lock_irqsave(&dev_priv->error_lock, flags);
	360	if (!dev_priv->first_error) {
	361	seq_printf(m, "no error state collected\n");
	362	goto out;
	363	}
	364
	365	error = dev_priv->first_error;
	366
8a905236 JB	367	seq_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec,
8a905236 JB	368	error->time.tv_usec);
63eeaf38 JB	369	seq_printf(m, "EIR: 0x%08x\n", error->eir);
	370	seq_printf(m, " PGTBL_ER: 0x%08x\n", error->pgtbl_er);
	371	seq_printf(m, " INSTPM: 0x%08x\n", error->instpm);
	372	seq_printf(m, " IPEIR: 0x%08x\n", error->ipeir);
	373	seq_printf(m, " IPEHR: 0x%08x\n", error->ipehr);
	374	seq_printf(m, " INSTDONE: 0x%08x\n", error->instdone);
	375	seq_printf(m, " ACTHD: 0x%08x\n", error->acthd);
	376	if (IS_I965G(dev)) {
	377	seq_printf(m, " INSTPS: 0x%08x\n", error->instps);
	378	seq_printf(m, " INSTDONE1: 0x%08x\n", error->instdone1);
	379	}
	380
	381	out:
	382	spin_unlock_irqrestore(&dev_priv->error_lock, flags);
	383
	384	return 0;
	385	}
6911a9b8	386
9e3a6d15 BG	387	static int i915_registers_info(struct seq_file m, void data) {
	388	struct drm_info_node node = (struct drm_info_node ) m->private;
	389	struct drm_device *dev = node->minor->dev;
	390	drm_i915_private_t *dev_priv = dev->dev_private;
	391	uint32_t reg;
	392
	393	#define DUMP_RANGE(start, end) \
	394	for (reg=start; reg < end; reg += 4) \
	395	seq_printf(m, "%08x\t%08x\n", reg, I915_READ(reg));
	396
	397	DUMP_RANGE(0x00000, 0x00fff); /* VGA registers */
	398	DUMP_RANGE(0x02000, 0x02fff); /* instruction, memory, interrupt control registers */
	399	DUMP_RANGE(0x03000, 0x031ff); /* FENCE and PPGTT control registers */
	400	DUMP_RANGE(0x03200, 0x03fff); /* frame buffer compression registers */
	401	DUMP_RANGE(0x05000, 0x05fff); /* I/O control registers */
	402	DUMP_RANGE(0x06000, 0x06fff); /* clock control registers */
	403	DUMP_RANGE(0x07000, 0x07fff); /* 3D internal debug registers */
	404	DUMP_RANGE(0x07400, 0x088ff); /* GPE debug registers */
	405	DUMP_RANGE(0x0a000, 0x0afff); /* display palette registers */
	406	DUMP_RANGE(0x10000, 0x13fff); /* MMIO MCHBAR */
	407	DUMP_RANGE(0x30000, 0x3ffff); /* overlay registers */
	408	DUMP_RANGE(0x60000, 0x6ffff); /* display engine pipeline registers */
	409	DUMP_RANGE(0x70000, 0x72fff); /* display and cursor registers */
	410	DUMP_RANGE(0x73000, 0x73fff); /* performance counters */
	411
	412	return 0;
	413	}
	414
	415
27c202ad	416	static struct drm_info_list i915_debugfs_list[] = {
9e3a6d15	417	{"i915_regs", i915_registers_info, 0},
433e12f7 BG	418	{"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
	419	{"i915_gem_flushing", i915_gem_object_list_info, 0, (void *) FLUSHING_LIST},
	420	{"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
2017263e BG	421	{"i915_gem_request", i915_gem_request_info, 0},
2017263e BG	422	{"i915_gem_seqno", i915_gem_seqno_info, 0},
a6172a80	423	{"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
2017263e BG	424	{"i915_gem_interrupt", i915_interrupt_info, 0},
2017263e BG	425	{"i915_gem_hws", i915_hws_info, 0},
6911a9b8 BG	426	{"i915_ringbuffer_data", i915_ringbuffer_data, 0},
	427	{"i915_ringbuffer_info", i915_ringbuffer_info, 0},
	428	{"i915_batchbuffers", i915_batchbuffer_info, 0},
63eeaf38	429	{"i915_error_state", i915_error_state, 0},
2017263e	430	};
27c202ad	431	#define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
2017263e	432
27c202ad	433	int i915_debugfs_init(struct drm_minor *minor)
2017263e	434	{
27c202ad BG	435	return drm_debugfs_create_files(i915_debugfs_list,
27c202ad BG	436	I915_DEBUGFS_ENTRIES,
2017263e BG	437	minor->debugfs_root, minor);
	438	}
	439
27c202ad	440	void i915_debugfs_cleanup(struct drm_minor *minor)
2017263e	441	{
27c202ad BG	442	drm_debugfs_remove_files(i915_debugfs_list,
27c202ad BG	443	I915_DEBUGFS_ENTRIES, minor);
2017263e BG	444	}
	445
	446	#endif /* CONFIG_DEBUG_FS */
	447