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drm/i915: Deprecated UMS support
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_debugfs.c
CommitLineData
2017263e
BG		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 *
27 */
28
29#include <linux/seq_file.h>
b2c88f5b 30#include <linux/circ_buf.h>
926321d5 31#include <linux/ctype.h>
f3cd474b 32#include <linux/debugfs.h>
5a0e3ad6 33#include <linux/slab.h>
2d1a8a48 34#include <linux/export.h>
6d2b8885 35#include <linux/list_sort.h>
ec013e7f 36#include <asm/msr-index.h>
760285e7 37#include <drm/drmP.h>
4e5359cd 38#include "intel_drv.h"
e5c65260 39#include "intel_ringbuffer.h"
760285e7 40#include <drm/i915_drm.h>
2017263e
BG		 41#include "i915_drv.h"
42
2017263e
BG		 43#if defined(CONFIG_DEBUG_FS)
44
f13d3f73 45enum {
69dc4987 46 ACTIVE_LIST,
f13d3f73 47 INACTIVE_LIST,
d21d5975 48 PINNED_LIST,
f13d3f73 49};
2017263e 50
70d39fe4
CW		 51static const char *yesno(int v)
52{
53 return v ? "yes" : "no";
54}
55
497666d8
DL		 56/* As the drm_debugfs_init() routines are called before dev->dev_private is
57 * allocated we need to hook into the minor for release. */
58static int
59drm_add_fake_info_node(struct drm_minor *minor,
60 struct dentry *ent,
61 const void *key)
62{
63 struct drm_info_node *node;
64
65 node = kmalloc(sizeof(*node), GFP_KERNEL);
66 if (node == NULL) {
67 debugfs_remove(ent);
68 return -ENOMEM;
69 }
70
71 node->minor = minor;
72 node->dent = ent;
73 node->info_ent = (void *) key;
74
75 mutex_lock(&minor->debugfs_lock);
76 list_add(&node->list, &minor->debugfs_list);
77 mutex_unlock(&minor->debugfs_lock);
78
79 return 0;
80}
81
70d39fe4
CW		 82static int i915_capabilities(struct seq_file *m, void *data)
83{
84 struct drm_info_node *node = (struct drm_info_node *) m->private;
85 struct drm_device *dev = node->minor->dev;
86 const struct intel_device_info *info = INTEL_INFO(dev);
87
88 seq_printf(m, "gen: %d\n", info->gen);
03d00ac5 89 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
79fc46df
DL		 90#define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
91#define SEP_SEMICOLON ;
92 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
93#undef PRINT_FLAG
94#undef SEP_SEMICOLON
70d39fe4
CW		 95
96 return 0;
97}
2017263e 98
05394f39 99static const char *get_pin_flag(struct drm_i915_gem_object *obj)
a6172a80 100{
05394f39 101 if (obj->user_pin_count > 0)
a6172a80 102 return "P";
05394f39 103 else if (obj->pin_count > 0)
a6172a80
CW		 104 return "p";
105 else
106 return " ";
107}
108
05394f39 109static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
a6172a80 110{
0206e353
AJ		 111 switch (obj->tiling_mode) {
112 default:
113 case I915_TILING_NONE: return " ";
114 case I915_TILING_X: return "X";
115 case I915_TILING_Y: return "Y";
116 }
a6172a80
CW		 117}
118
1d693bcc
BW		 119static inline const char *get_global_flag(struct drm_i915_gem_object *obj)
120{
121 return obj->has_global_gtt_mapping ? "g" : " ";
122}
123
37811fcc
CW		 124static void
125describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
126{
1d693bcc 127 struct i915_vma *vma;
fb1ae911 128 seq_printf(m, "%pK: %s%s%s %8zdKiB %02x %02x %u %u %u%s%s%s",
37811fcc
CW		 129 &obj->base,
130 get_pin_flag(obj),
131 get_tiling_flag(obj),
1d693bcc 132 get_global_flag(obj),
a05a5862 133 obj->base.size / 1024,
37811fcc
CW		 134 obj->base.read_domains,
135 obj->base.write_domain,
0201f1ec
CW		 136 obj->last_read_seqno,
137 obj->last_write_seqno,
caea7476 138 obj->last_fenced_seqno,
84734a04 139 i915_cache_level_str(obj->cache_level),
37811fcc
CW		 140 obj->dirty ? " dirty" : "",
141 obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
142 if (obj->base.name)
143 seq_printf(m, " (name: %d)", obj->base.name);
c110a6d7
CW		 144 if (obj->pin_count)
145 seq_printf(m, " (pinned x %d)", obj->pin_count);
cc98b413
CW		 146 if (obj->pin_display)
147 seq_printf(m, " (display)");
37811fcc
CW		 148 if (obj->fence_reg != I915_FENCE_REG_NONE)
149 seq_printf(m, " (fence: %d)", obj->fence_reg);
1d693bcc
BW		 150 list_for_each_entry(vma, &obj->vma_list, vma_link) {
151 if (!i915_is_ggtt(vma->vm))
152 seq_puts(m, " (pp");
153 else
154 seq_puts(m, " (g");
155 seq_printf(m, "gtt offset: %08lx, size: %08lx)",
156 vma->node.start, vma->node.size);
157 }
c1ad11fc
CW		 158 if (obj->stolen)
159 seq_printf(m, " (stolen: %08lx)", obj->stolen->start);
6299f992
CW		 160 if (obj->pin_mappable || obj->fault_mappable) {
161 char s[3], *t = s;
162 if (obj->pin_mappable)
163 *t++ = 'p';
164 if (obj->fault_mappable)
165 *t++ = 'f';
166 *t = '\0';
167 seq_printf(m, " (%s mappable)", s);
168 }
69dc4987
CW		 169 if (obj->ring != NULL)
170 seq_printf(m, " (%s)", obj->ring->name);
37811fcc
CW		 171}
172
3ccfd19d
BW		 173static void describe_ctx(struct seq_file *m, struct i915_hw_context *ctx)
174{
175 seq_putc(m, ctx->is_initialized ? 'I' : 'i');
176 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
177 seq_putc(m, ' ');
178}
179
433e12f7 180static int i915_gem_object_list_info(struct seq_file *m, void *data)
2017263e
BG		 181{
182 struct drm_info_node *node = (struct drm_info_node *) m->private;
433e12f7
BG		 183 uintptr_t list = (uintptr_t) node->info_ent->data;
184 struct list_head *head;
2017263e 185 struct drm_device *dev = node->minor->dev;
5cef07e1
BW		 186 struct drm_i915_private *dev_priv = dev->dev_private;
187 struct i915_address_space *vm = &dev_priv->gtt.base;
ca191b13 188 struct i915_vma *vma;
8f2480fb
CW		 189 size_t total_obj_size, total_gtt_size;
190 int count, ret;
de227ef0
CW		 191
192 ret = mutex_lock_interruptible(&dev->struct_mutex);
193 if (ret)
194 return ret;
2017263e 195
ca191b13 196 /* FIXME: the user of this interface might want more than just GGTT */
433e12f7
BG		 197 switch (list) {
198 case ACTIVE_LIST:
267f0c90 199 seq_puts(m, "Active:\n");
5cef07e1 200 head = &vm->active_list;
433e12f7
BG		 201 break;
202 case INACTIVE_LIST:
267f0c90 203 seq_puts(m, "Inactive:\n");
5cef07e1 204 head = &vm->inactive_list;
433e12f7 205 break;
433e12f7 206 default:
de227ef0
CW		 207 mutex_unlock(&dev->struct_mutex);
208 return -EINVAL;
2017263e 209 }
2017263e 210
8f2480fb 211 total_obj_size = total_gtt_size = count = 0;
ca191b13
BW		 212 list_for_each_entry(vma, head, mm_list) {
213 seq_printf(m, " ");
214 describe_obj(m, vma->obj);
215 seq_printf(m, "\n");
216 total_obj_size += vma->obj->base.size;
217 total_gtt_size += vma->node.size;
8f2480fb 218 count++;
2017263e 219 }
de227ef0 220 mutex_unlock(&dev->struct_mutex);
5e118f41 221
8f2480fb
CW		 222 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
223 count, total_obj_size, total_gtt_size);
2017263e
BG		 224 return 0;
225}
226
6d2b8885
CW		 227static int obj_rank_by_stolen(void *priv,
228 struct list_head *A, struct list_head *B)
229{
230 struct drm_i915_gem_object *a =
b25cb2f8 231 container_of(A, struct drm_i915_gem_object, obj_exec_link);
6d2b8885 232 struct drm_i915_gem_object *b =
b25cb2f8 233 container_of(B, struct drm_i915_gem_object, obj_exec_link);
6d2b8885
CW		 234
235 return a->stolen->start - b->stolen->start;
236}
237
238static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
239{
240 struct drm_info_node *node = (struct drm_info_node *) m->private;
241 struct drm_device *dev = node->minor->dev;
242 struct drm_i915_private *dev_priv = dev->dev_private;
243 struct drm_i915_gem_object *obj;
244 size_t total_obj_size, total_gtt_size;
245 LIST_HEAD(stolen);
246 int count, ret;
247
248 ret = mutex_lock_interruptible(&dev->struct_mutex);
249 if (ret)
250 return ret;
251
252 total_obj_size = total_gtt_size = count = 0;
253 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
254 if (obj->stolen == NULL)
255 continue;
256
b25cb2f8 257 list_add(&obj->obj_exec_link, &stolen);
6d2b8885
CW		 258
259 total_obj_size += obj->base.size;
260 total_gtt_size += i915_gem_obj_ggtt_size(obj);
261 count++;
262 }
263 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
264 if (obj->stolen == NULL)
265 continue;
266
b25cb2f8 267 list_add(&obj->obj_exec_link, &stolen);
6d2b8885
CW		 268
269 total_obj_size += obj->base.size;
270 count++;
271 }
272 list_sort(NULL, &stolen, obj_rank_by_stolen);
273 seq_puts(m, "Stolen:\n");
274 while (!list_empty(&stolen)) {
b25cb2f8 275 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
6d2b8885
CW		 276 seq_puts(m, " ");
277 describe_obj(m, obj);
278 seq_putc(m, '\n');
b25cb2f8 279 list_del_init(&obj->obj_exec_link);
6d2b8885
CW		 280 }
281 mutex_unlock(&dev->struct_mutex);
282
283 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
284 count, total_obj_size, total_gtt_size);
285 return 0;
286}
287
6299f992
CW		 288#define count_objects(list, member) do { \
289 list_for_each_entry(obj, list, member) { \
f343c5f6 290 size += i915_gem_obj_ggtt_size(obj); \
6299f992
CW		 291 ++count; \
292 if (obj->map_and_fenceable) { \
f343c5f6 293 mappable_size += i915_gem_obj_ggtt_size(obj); \
6299f992
CW		 294 ++mappable_count; \
295 } \
296 } \
0206e353 297} while (0)
6299f992 298
2db8e9d6
CW		 299struct file_stats {
300 int count;
301 size_t total, active, inactive, unbound;
302};
303
304static int per_file_stats(int id, void *ptr, void *data)
305{
306 struct drm_i915_gem_object *obj = ptr;
307 struct file_stats *stats = data;
308
309 stats->count++;
310 stats->total += obj->base.size;
311
f343c5f6 312 if (i915_gem_obj_ggtt_bound(obj)) {
2db8e9d6
CW		 313 if (!list_empty(&obj->ring_list))
314 stats->active += obj->base.size;
315 else
316 stats->inactive += obj->base.size;
317 } else {
318 if (!list_empty(&obj->global_list))
319 stats->unbound += obj->base.size;
320 }
321
322 return 0;
323}
324
ca191b13
BW		 325#define count_vmas(list, member) do { \
326 list_for_each_entry(vma, list, member) { \
327 size += i915_gem_obj_ggtt_size(vma->obj); \
328 ++count; \
329 if (vma->obj->map_and_fenceable) { \
330 mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
331 ++mappable_count; \
332 } \
333 } \
334} while (0)
335
336static int i915_gem_object_info(struct seq_file *m, void* data)
73aa808f
CW		 337{
338 struct drm_info_node *node = (struct drm_info_node *) m->private;
339 struct drm_device *dev = node->minor->dev;
340 struct drm_i915_private *dev_priv = dev->dev_private;
b7abb714
CW		 341 u32 count, mappable_count, purgeable_count;
342 size_t size, mappable_size, purgeable_size;
6299f992 343 struct drm_i915_gem_object *obj;
5cef07e1 344 struct i915_address_space *vm = &dev_priv->gtt.base;
2db8e9d6 345 struct drm_file *file;
ca191b13 346 struct i915_vma *vma;
73aa808f
CW		 347 int ret;
348
349 ret = mutex_lock_interruptible(&dev->struct_mutex);
350 if (ret)
351 return ret;
352
6299f992
CW		 353 seq_printf(m, "%u objects, %zu bytes\n",
354 dev_priv->mm.object_count,
355 dev_priv->mm.object_memory);
356
357 size = count = mappable_size = mappable_count = 0;
35c20a60 358 count_objects(&dev_priv->mm.bound_list, global_list);
6299f992
CW		 359 seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n",
360 count, mappable_count, size, mappable_size);
361
362 size = count = mappable_size = mappable_count = 0;
ca191b13 363 count_vmas(&vm->active_list, mm_list);
6299f992
CW		 364 seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n",
365 count, mappable_count, size, mappable_size);
366
6299f992 367 size = count = mappable_size = mappable_count = 0;
ca191b13 368 count_vmas(&vm->inactive_list, mm_list);
6299f992
CW		 369 seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n",
370 count, mappable_count, size, mappable_size);
371
b7abb714 372 size = count = purgeable_size = purgeable_count = 0;
35c20a60 373 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
6c085a72 374 size += obj->base.size, ++count;
b7abb714
CW		 375 if (obj->madv == I915_MADV_DONTNEED)
376 purgeable_size += obj->base.size, ++purgeable_count;
377 }
6c085a72
CW		 378 seq_printf(m, "%u unbound objects, %zu bytes\n", count, size);
379
6299f992 380 size = count = mappable_size = mappable_count = 0;
35c20a60 381 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
6299f992 382 if (obj->fault_mappable) {
f343c5f6 383 size += i915_gem_obj_ggtt_size(obj);
6299f992
CW		 384 ++count;
385 }
386 if (obj->pin_mappable) {
f343c5f6 387 mappable_size += i915_gem_obj_ggtt_size(obj);
6299f992
CW		 388 ++mappable_count;
389 }
b7abb714
CW		 390 if (obj->madv == I915_MADV_DONTNEED) {
391 purgeable_size += obj->base.size;
392 ++purgeable_count;
393 }
6299f992 394 }
b7abb714
CW		 395 seq_printf(m, "%u purgeable objects, %zu bytes\n",
396 purgeable_count, purgeable_size);
6299f992
CW		 397 seq_printf(m, "%u pinned mappable objects, %zu bytes\n",
398 mappable_count, mappable_size);
399 seq_printf(m, "%u fault mappable objects, %zu bytes\n",
400 count, size);
401
93d18799 402 seq_printf(m, "%zu [%lu] gtt total\n",
853ba5d2
BW		 403 dev_priv->gtt.base.total,
404 dev_priv->gtt.mappable_end - dev_priv->gtt.base.start);
73aa808f 405
267f0c90 406 seq_putc(m, '\n');
2db8e9d6
CW		 407 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
408 struct file_stats stats;
409
410 memset(&stats, 0, sizeof(stats));
411 idr_for_each(&file->object_idr, per_file_stats, &stats);
412 seq_printf(m, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu unbound)\n",
413 get_pid_task(file->pid, PIDTYPE_PID)->comm,
414 stats.count,
415 stats.total,
416 stats.active,
417 stats.inactive,
418 stats.unbound);
419 }
420
73aa808f
CW		 421 mutex_unlock(&dev->struct_mutex);
422
423 return 0;
424}
425
aee56cff 426static int i915_gem_gtt_info(struct seq_file *m, void *data)
08c18323
CW		 427{
428 struct drm_info_node *node = (struct drm_info_node *) m->private;
429 struct drm_device *dev = node->minor->dev;
1b50247a 430 uintptr_t list = (uintptr_t) node->info_ent->data;
08c18323
CW		 431 struct drm_i915_private *dev_priv = dev->dev_private;
432 struct drm_i915_gem_object *obj;
433 size_t total_obj_size, total_gtt_size;
434 int count, ret;
435
436 ret = mutex_lock_interruptible(&dev->struct_mutex);
437 if (ret)
438 return ret;
439
440 total_obj_size = total_gtt_size = count = 0;
35c20a60 441 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
1b50247a
CW		 442 if (list == PINNED_LIST && obj->pin_count == 0)
443 continue;
444
267f0c90 445 seq_puts(m, " ");
08c18323 446 describe_obj(m, obj);
267f0c90 447 seq_putc(m, '\n');
08c18323 448 total_obj_size += obj->base.size;
f343c5f6 449 total_gtt_size += i915_gem_obj_ggtt_size(obj);
08c18323
CW		 450 count++;
451 }
452
453 mutex_unlock(&dev->struct_mutex);
454
455 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
456 count, total_obj_size, total_gtt_size);
457
458 return 0;
459}
460
4e5359cd
SF		 461static int i915_gem_pageflip_info(struct seq_file *m, void *data)
462{
463 struct drm_info_node *node = (struct drm_info_node *) m->private;
464 struct drm_device *dev = node->minor->dev;
465 unsigned long flags;
466 struct intel_crtc *crtc;
467
468 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
9db4a9c7
JB		 469 const char pipe = pipe_name(crtc->pipe);
470 const char plane = plane_name(crtc->plane);
4e5359cd
SF		 471 struct intel_unpin_work *work;
472
473 spin_lock_irqsave(&dev->event_lock, flags);
474 work = crtc->unpin_work;
475 if (work == NULL) {
9db4a9c7 476 seq_printf(m, "No flip due on pipe %c (plane %c)\n",
4e5359cd
SF		 477 pipe, plane);
478 } else {
e7d841ca 479 if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9db4a9c7 480 seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
4e5359cd
SF		 481 pipe, plane);
482 } else {
9db4a9c7 483 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
4e5359cd
SF		 484 pipe, plane);
485 }
486 if (work->enable_stall_check)
267f0c90 487 seq_puts(m, "Stall check enabled, ");
4e5359cd 488 else
267f0c90 489 seq_puts(m, "Stall check waiting for page flip ioctl, ");
e7d841ca 490 seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
4e5359cd
SF		 491
492 if (work->old_fb_obj) {
05394f39
CW		 493 struct drm_i915_gem_object *obj = work->old_fb_obj;
494 if (obj)
f343c5f6
BW		 495 seq_printf(m, "Old framebuffer gtt_offset 0x%08lx\n",
496 i915_gem_obj_ggtt_offset(obj));
4e5359cd
SF		 497 }
498 if (work->pending_flip_obj) {
05394f39
CW		 499 struct drm_i915_gem_object *obj = work->pending_flip_obj;
500 if (obj)
f343c5f6
BW		 501 seq_printf(m, "New framebuffer gtt_offset 0x%08lx\n",
502 i915_gem_obj_ggtt_offset(obj));
4e5359cd
SF		 503 }
504 }
505 spin_unlock_irqrestore(&dev->event_lock, flags);
506 }
507
508 return 0;
509}
510
2017263e
BG		 511static int i915_gem_request_info(struct seq_file *m, void *data)
512{
513 struct drm_info_node *node = (struct drm_info_node *) m->private;
514 struct drm_device *dev = node->minor->dev;
515 drm_i915_private_t *dev_priv = dev->dev_private;
a2c7f6fd 516 struct intel_ring_buffer *ring;
2017263e 517 struct drm_i915_gem_request *gem_request;
a2c7f6fd 518 int ret, count, i;
de227ef0
CW		 519
520 ret = mutex_lock_interruptible(&dev->struct_mutex);
521 if (ret)
522 return ret;
2017263e 523
c2c347a9 524 count = 0;
a2c7f6fd
CW		 525 for_each_ring(ring, dev_priv, i) {
526 if (list_empty(&ring->request_list))
527 continue;
528
529 seq_printf(m, "%s requests:\n", ring->name);
c2c347a9 530 list_for_each_entry(gem_request,
a2c7f6fd 531 &ring->request_list,
c2c347a9
CW		 532 list) {
533 seq_printf(m, " %d @ %d\n",
534 gem_request->seqno,
535 (int) (jiffies - gem_request->emitted_jiffies));
536 }
537 count++;
2017263e 538 }
de227ef0
CW		 539 mutex_unlock(&dev->struct_mutex);
540
c2c347a9 541 if (count == 0)
267f0c90 542 seq_puts(m, "No requests\n");
c2c347a9 543
2017263e
BG		 544 return 0;
545}
546
b2223497
CW		 547static void i915_ring_seqno_info(struct seq_file *m,
548 struct intel_ring_buffer *ring)
549{
550 if (ring->get_seqno) {
43a7b924 551 seq_printf(m, "Current sequence (%s): %u\n",
b2eadbc8 552 ring->name, ring->get_seqno(ring, false));
b2223497
CW		 553 }
554}
555
2017263e
BG		 556static int i915_gem_seqno_info(struct seq_file *m, void *data)
557{
558 struct drm_info_node *node = (struct drm_info_node *) m->private;
559 struct drm_device *dev = node->minor->dev;
560 drm_i915_private_t *dev_priv = dev->dev_private;
a2c7f6fd 561 struct intel_ring_buffer *ring;
1ec14ad3 562 int ret, i;
de227ef0
CW		 563
564 ret = mutex_lock_interruptible(&dev->struct_mutex);
565 if (ret)
566 return ret;
2017263e 567
a2c7f6fd
CW		 568 for_each_ring(ring, dev_priv, i)
569 i915_ring_seqno_info(m, ring);
de227ef0
CW		 570
571 mutex_unlock(&dev->struct_mutex);
572
2017263e
BG		 573 return 0;
574}
575
576
577static int i915_interrupt_info(struct seq_file *m, void *data)
578{
579 struct drm_info_node *node = (struct drm_info_node *) m->private;
580 struct drm_device *dev = node->minor->dev;
581 drm_i915_private_t *dev_priv = dev->dev_private;
a2c7f6fd 582 struct intel_ring_buffer *ring;
9db4a9c7 583 int ret, i, pipe;
de227ef0
CW		 584
585 ret = mutex_lock_interruptible(&dev->struct_mutex);
586 if (ret)
587 return ret;
2017263e 588
7e231dbe
JB		 589 if (IS_VALLEYVIEW(dev)) {
590 seq_printf(m, "Display IER:\t%08x\n",
591 I915_READ(VLV_IER));
592 seq_printf(m, "Display IIR:\t%08x\n",
593 I915_READ(VLV_IIR));
594 seq_printf(m, "Display IIR_RW:\t%08x\n",
595 I915_READ(VLV_IIR_RW));
596 seq_printf(m, "Display IMR:\t%08x\n",
597 I915_READ(VLV_IMR));
598 for_each_pipe(pipe)
599 seq_printf(m, "Pipe %c stat:\t%08x\n",
600 pipe_name(pipe),
601 I915_READ(PIPESTAT(pipe)));
602
603 seq_printf(m, "Master IER:\t%08x\n",
604 I915_READ(VLV_MASTER_IER));
605
606 seq_printf(m, "Render IER:\t%08x\n",
607 I915_READ(GTIER));
608 seq_printf(m, "Render IIR:\t%08x\n",
609 I915_READ(GTIIR));
610 seq_printf(m, "Render IMR:\t%08x\n",
611 I915_READ(GTIMR));
612
613 seq_printf(m, "PM IER:\t\t%08x\n",
614 I915_READ(GEN6_PMIER));
615 seq_printf(m, "PM IIR:\t\t%08x\n",
616 I915_READ(GEN6_PMIIR));
617 seq_printf(m, "PM IMR:\t\t%08x\n",
618 I915_READ(GEN6_PMIMR));
619
620 seq_printf(m, "Port hotplug:\t%08x\n",
621 I915_READ(PORT_HOTPLUG_EN));
622 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
623 I915_READ(VLV_DPFLIPSTAT));
624 seq_printf(m, "DPINVGTT:\t%08x\n",
625 I915_READ(DPINVGTT));
626
627 } else if (!HAS_PCH_SPLIT(dev)) {
5f6a1695
ZW		 628 seq_printf(m, "Interrupt enable: %08x\n",
629 I915_READ(IER));
630 seq_printf(m, "Interrupt identity: %08x\n",
631 I915_READ(IIR));
632 seq_printf(m, "Interrupt mask: %08x\n",
633 I915_READ(IMR));
9db4a9c7
JB		 634 for_each_pipe(pipe)
635 seq_printf(m, "Pipe %c stat: %08x\n",
636 pipe_name(pipe),
637 I915_READ(PIPESTAT(pipe)));
5f6a1695
ZW		 638 } else {
639 seq_printf(m, "North Display Interrupt enable: %08x\n",
640 I915_READ(DEIER));
641 seq_printf(m, "North Display Interrupt identity: %08x\n",
642 I915_READ(DEIIR));
643 seq_printf(m, "North Display Interrupt mask: %08x\n",
644 I915_READ(DEIMR));
645 seq_printf(m, "South Display Interrupt enable: %08x\n",
646 I915_READ(SDEIER));
647 seq_printf(m, "South Display Interrupt identity: %08x\n",
648 I915_READ(SDEIIR));
649 seq_printf(m, "South Display Interrupt mask: %08x\n",
650 I915_READ(SDEIMR));
651 seq_printf(m, "Graphics Interrupt enable: %08x\n",
652 I915_READ(GTIER));
653 seq_printf(m, "Graphics Interrupt identity: %08x\n",
654 I915_READ(GTIIR));
655 seq_printf(m, "Graphics Interrupt mask: %08x\n",
656 I915_READ(GTIMR));
657 }
2017263e
BG		 658 seq_printf(m, "Interrupts received: %d\n",
659 atomic_read(&dev_priv->irq_received));
a2c7f6fd 660 for_each_ring(ring, dev_priv, i) {
da64c6fc 661 if (IS_GEN6(dev) || IS_GEN7(dev)) {
a2c7f6fd
CW		 662 seq_printf(m,
663 "Graphics Interrupt mask (%s): %08x\n",
664 ring->name, I915_READ_IMR(ring));
9862e600 665 }
a2c7f6fd 666 i915_ring_seqno_info(m, ring);
9862e600 667 }
de227ef0
CW		 668 mutex_unlock(&dev->struct_mutex);
669
2017263e
BG		 670 return 0;
671}
672
a6172a80
CW		 673static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
674{
675 struct drm_info_node *node = (struct drm_info_node *) m->private;
676 struct drm_device *dev = node->minor->dev;
677 drm_i915_private_t *dev_priv = dev->dev_private;
de227ef0
CW		 678 int i, ret;
679
680 ret = mutex_lock_interruptible(&dev->struct_mutex);
681 if (ret)
682 return ret;
a6172a80
CW		 683
684 seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
685 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
686 for (i = 0; i < dev_priv->num_fence_regs; i++) {
05394f39 687 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
a6172a80 688
6c085a72
CW		 689 seq_printf(m, "Fence %d, pin count = %d, object = ",
690 i, dev_priv->fence_regs[i].pin_count);
c2c347a9 691 if (obj == NULL)
267f0c90 692 seq_puts(m, "unused");
c2c347a9 693 else
05394f39 694 describe_obj(m, obj);
267f0c90 695 seq_putc(m, '\n');
a6172a80
CW		 696 }
697
05394f39 698 mutex_unlock(&dev->struct_mutex);
a6172a80
CW		 699 return 0;
700}
701
2017263e
BG		 702static int i915_hws_info(struct seq_file *m, void *data)
703{
704 struct drm_info_node *node = (struct drm_info_node *) m->private;
705 struct drm_device *dev = node->minor->dev;
706 drm_i915_private_t *dev_priv = dev->dev_private;
4066c0ae 707 struct intel_ring_buffer *ring;
1a240d4d 708 const u32 *hws;
4066c0ae
CW		 709 int i;
710
1ec14ad3 711 ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
1a240d4d 712 hws = ring->status_page.page_addr;
2017263e
BG		 713 if (hws == NULL)
714 return 0;
715
716 for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
717 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
718 i * 4,
719 hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
720 }
721 return 0;
722}
723
d5442303
DV		 724static ssize_t
725i915_error_state_write(struct file *filp,
726 const char __user *ubuf,
727 size_t cnt,
728 loff_t *ppos)
729{
edc3d884 730 struct i915_error_state_file_priv *error_priv = filp->private_data;
d5442303 731 struct drm_device *dev = error_priv->dev;
22bcfc6a 732 int ret;
d5442303
DV		 733
734 DRM_DEBUG_DRIVER("Resetting error state\n");
735
22bcfc6a
DV		 736 ret = mutex_lock_interruptible(&dev->struct_mutex);
737 if (ret)
738 return ret;
739
d5442303
DV		 740 i915_destroy_error_state(dev);
741 mutex_unlock(&dev->struct_mutex);
742
743 return cnt;
744}
745
746static int i915_error_state_open(struct inode *inode, struct file *file)
747{
748 struct drm_device *dev = inode->i_private;
d5442303 749 struct i915_error_state_file_priv *error_priv;
d5442303
DV		 750
751 error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
752 if (!error_priv)
753 return -ENOMEM;
754
755 error_priv->dev = dev;
756
95d5bfb3 757 i915_error_state_get(dev, error_priv);
d5442303 758
edc3d884
MK		 759 file->private_data = error_priv;
760
761 return 0;
d5442303
DV		 762}
763
764static int i915_error_state_release(struct inode *inode, struct file *file)
765{
edc3d884 766 struct i915_error_state_file_priv *error_priv = file->private_data;
d5442303 767
95d5bfb3 768 i915_error_state_put(error_priv);
d5442303
DV		 769 kfree(error_priv);
770
edc3d884
MK		 771 return 0;
772}
773
4dc955f7
MK		 774static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
775 size_t count, loff_t *pos)
776{
777 struct i915_error_state_file_priv *error_priv = file->private_data;
778 struct drm_i915_error_state_buf error_str;
779 loff_t tmp_pos = 0;
780 ssize_t ret_count = 0;
781 int ret;
782
783 ret = i915_error_state_buf_init(&error_str, count, *pos);
784 if (ret)
785 return ret;
edc3d884 786
fc16b48b 787 ret = i915_error_state_to_str(&error_str, error_priv);
edc3d884
MK		 788 if (ret)
789 goto out;
790
edc3d884
MK		 791 ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
792 error_str.buf,
793 error_str.bytes);
794
795 if (ret_count < 0)
796 ret = ret_count;
797 else
798 *pos = error_str.start + ret_count;
799out:
4dc955f7 800 i915_error_state_buf_release(&error_str);
edc3d884 801 return ret ?: ret_count;
d5442303
DV		 802}
803
804static const struct file_operations i915_error_state_fops = {
805 .owner = THIS_MODULE,
806 .open = i915_error_state_open,
edc3d884 807 .read = i915_error_state_read,
d5442303
DV		 808 .write = i915_error_state_write,
809 .llseek = default_llseek,
810 .release = i915_error_state_release,
811};
812
647416f9
KC		 813static int
814i915_next_seqno_get(void *data, u64 *val)
40633219 815{
647416f9 816 struct drm_device *dev = data;
40633219 817 drm_i915_private_t *dev_priv = dev->dev_private;
40633219
MK		 818 int ret;
819
820 ret = mutex_lock_interruptible(&dev->struct_mutex);
821 if (ret)
822 return ret;
823
647416f9 824 *val = dev_priv->next_seqno;
40633219
MK		 825 mutex_unlock(&dev->struct_mutex);
826
647416f9 827 return 0;
40633219
MK		 828}
829
647416f9
KC		 830static int
831i915_next_seqno_set(void *data, u64 val)
832{
833 struct drm_device *dev = data;
40633219
MK		 834 int ret;
835
40633219
MK		 836 ret = mutex_lock_interruptible(&dev->struct_mutex);
837 if (ret)
838 return ret;
839
e94fbaa8 840 ret = i915_gem_set_seqno(dev, val);
40633219
MK		 841 mutex_unlock(&dev->struct_mutex);
842
647416f9 843 return ret;
40633219
MK		 844}
845
647416f9
KC		 846DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
847 i915_next_seqno_get, i915_next_seqno_set,
3a3b4f98 848 "0x%llx\n");
40633219 849
f97108d1
JB		 850static int i915_rstdby_delays(struct seq_file *m, void *unused)
851{
852 struct drm_info_node *node = (struct drm_info_node *) m->private;
853 struct drm_device *dev = node->minor->dev;
854 drm_i915_private_t *dev_priv = dev->dev_private;
616fdb5a
BW		 855 u16 crstanddelay;
856 int ret;
857
858 ret = mutex_lock_interruptible(&dev->struct_mutex);
859 if (ret)
860 return ret;
861
862 crstanddelay = I915_READ16(CRSTANDVID);
863
864 mutex_unlock(&dev->struct_mutex);
f97108d1
JB		 865
866 seq_printf(m, "w/ctx: %d, w/o ctx: %d\n", (crstanddelay >> 8) & 0x3f, (crstanddelay & 0x3f));
867
868 return 0;
869}
870
871static int i915_cur_delayinfo(struct seq_file *m, void *unused)
872{
873 struct drm_info_node *node = (struct drm_info_node *) m->private;
874 struct drm_device *dev = node->minor->dev;
875 drm_i915_private_t *dev_priv = dev->dev_private;
d1ebd816 876 int ret;
3b8d8d91 877
5c9669ce
TR		 878 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
879
3b8d8d91
JB		 880 if (IS_GEN5(dev)) {
881 u16 rgvswctl = I915_READ16(MEMSWCTL);
882 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
883
884 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
885 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
886 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
887 MEMSTAT_VID_SHIFT);
888 seq_printf(m, "Current P-state: %d\n",
889 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
0a073b84 890 } else if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) {
3b8d8d91
JB		 891 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
892 u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
893 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
8e8c06cd 894 u32 rpstat, cagf, reqf;
ccab5c82
JB		 895 u32 rpupei, rpcurup, rpprevup;
896 u32 rpdownei, rpcurdown, rpprevdown;
3b8d8d91
JB		 897 int max_freq;
898
899 /* RPSTAT1 is in the GT power well */
d1ebd816
BW		 900 ret = mutex_lock_interruptible(&dev->struct_mutex);
901 if (ret)
902 return ret;
903
fcca7926 904 gen6_gt_force_wake_get(dev_priv);
3b8d8d91 905
8e8c06cd
CW		 906 reqf = I915_READ(GEN6_RPNSWREQ);
907 reqf &= ~GEN6_TURBO_DISABLE;
908 if (IS_HASWELL(dev))
909 reqf >>= 24;
910 else
911 reqf >>= 25;
912 reqf *= GT_FREQUENCY_MULTIPLIER;
913
ccab5c82
JB		 914 rpstat = I915_READ(GEN6_RPSTAT1);
915 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
916 rpcurup = I915_READ(GEN6_RP_CUR_UP);
917 rpprevup = I915_READ(GEN6_RP_PREV_UP);
918 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
919 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
920 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
f82855d3
BW		 921 if (IS_HASWELL(dev))
922 cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
923 else
924 cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
925 cagf *= GT_FREQUENCY_MULTIPLIER;
ccab5c82 926
d1ebd816
BW		 927 gen6_gt_force_wake_put(dev_priv);
928 mutex_unlock(&dev->struct_mutex);
929
3b8d8d91 930 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
ccab5c82 931 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
3b8d8d91
JB		 932 seq_printf(m, "Render p-state ratio: %d\n",
933 (gt_perf_status & 0xff00) >> 8);
934 seq_printf(m, "Render p-state VID: %d\n",
935 gt_perf_status & 0xff);
936 seq_printf(m, "Render p-state limit: %d\n",
937 rp_state_limits & 0xff);
8e8c06cd 938 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
f82855d3 939 seq_printf(m, "CAGF: %dMHz\n", cagf);
ccab5c82
JB		 940 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
941 GEN6_CURICONT_MASK);
942 seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
943 GEN6_CURBSYTAVG_MASK);
944 seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
945 GEN6_CURBSYTAVG_MASK);
946 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
947 GEN6_CURIAVG_MASK);
948 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
949 GEN6_CURBSYTAVG_MASK);
950 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
951 GEN6_CURBSYTAVG_MASK);
3b8d8d91
JB		 952
953 max_freq = (rp_state_cap & 0xff0000) >> 16;
954 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
c8735b0c 955 max_freq * GT_FREQUENCY_MULTIPLIER);
3b8d8d91
JB		 956
957 max_freq = (rp_state_cap & 0xff00) >> 8;
958 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
c8735b0c 959 max_freq * GT_FREQUENCY_MULTIPLIER);
3b8d8d91
JB		 960
961 max_freq = rp_state_cap & 0xff;
962 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
c8735b0c 963 max_freq * GT_FREQUENCY_MULTIPLIER);
31c77388
BW		 964
965 seq_printf(m, "Max overclocked frequency: %dMHz\n",
966 dev_priv->rps.hw_max * GT_FREQUENCY_MULTIPLIER);
0a073b84
JB		 967 } else if (IS_VALLEYVIEW(dev)) {
968 u32 freq_sts, val;
969
259bd5d4 970 mutex_lock(&dev_priv->rps.hw_lock);
64936258 971 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
0a073b84
JB		 972 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
973 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
974
c5bd2bf6 975 val = valleyview_rps_max_freq(dev_priv);
0a073b84 976 seq_printf(m, "max GPU freq: %d MHz\n",
2ec3815f 977 vlv_gpu_freq(dev_priv, val));
0a073b84 978
c5bd2bf6 979 val = valleyview_rps_min_freq(dev_priv);
0a073b84 980 seq_printf(m, "min GPU freq: %d MHz\n",
2ec3815f 981 vlv_gpu_freq(dev_priv, val));
0a073b84
JB		 982
983 seq_printf(m, "current GPU freq: %d MHz\n",
2ec3815f 984 vlv_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
259bd5d4 985 mutex_unlock(&dev_priv->rps.hw_lock);
3b8d8d91 986 } else {
267f0c90 987 seq_puts(m, "no P-state info available\n");
3b8d8d91 988 }
f97108d1
JB		 989
990 return 0;
991}
992
993static int i915_delayfreq_table(struct seq_file *m, void *unused)
994{
995 struct drm_info_node *node = (struct drm_info_node *) m->private;
996 struct drm_device *dev = node->minor->dev;
997 drm_i915_private_t *dev_priv = dev->dev_private;
998 u32 delayfreq;
616fdb5a
BW		 999 int ret, i;
1000
1001 ret = mutex_lock_interruptible(&dev->struct_mutex);
1002 if (ret)
1003 return ret;
f97108d1
JB		 1004
1005 for (i = 0; i < 16; i++) {
1006 delayfreq = I915_READ(PXVFREQ_BASE + i * 4);
7648fa99
JB		 1007 seq_printf(m, "P%02dVIDFREQ: 0x%08x (VID: %d)\n", i, delayfreq,
1008 (delayfreq & PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT);
f97108d1
JB		 1009 }
1010
616fdb5a
BW		 1011 mutex_unlock(&dev->struct_mutex);
1012
f97108d1
JB		 1013 return 0;
1014}
1015
1016static inline int MAP_TO_MV(int map)
1017{
1018 return 1250 - (map * 25);
1019}
1020
1021static int i915_inttoext_table(struct seq_file *m, void *unused)
1022{
1023 struct drm_info_node *node = (struct drm_info_node *) m->private;
1024 struct drm_device *dev = node->minor->dev;
1025 drm_i915_private_t *dev_priv = dev->dev_private;
1026 u32 inttoext;
616fdb5a
BW		 1027 int ret, i;
1028
1029 ret = mutex_lock_interruptible(&dev->struct_mutex);
1030 if (ret)
1031 return ret;
f97108d1
JB		 1032
1033 for (i = 1; i <= 32; i++) {
1034 inttoext = I915_READ(INTTOEXT_BASE_ILK + i * 4);
1035 seq_printf(m, "INTTOEXT%02d: 0x%08x\n", i, inttoext);
1036 }
1037
616fdb5a
BW		 1038 mutex_unlock(&dev->struct_mutex);
1039
f97108d1
JB		 1040 return 0;
1041}
1042
4d85529d 1043static int ironlake_drpc_info(struct seq_file *m)
f97108d1
JB		 1044{
1045 struct drm_info_node *node = (struct drm_info_node *) m->private;
1046 struct drm_device *dev = node->minor->dev;
1047 drm_i915_private_t *dev_priv = dev->dev_private;
616fdb5a
BW		 1048 u32 rgvmodectl, rstdbyctl;
1049 u16 crstandvid;
1050 int ret;
1051
1052 ret = mutex_lock_interruptible(&dev->struct_mutex);
1053 if (ret)
1054 return ret;
1055
1056 rgvmodectl = I915_READ(MEMMODECTL);
1057 rstdbyctl = I915_READ(RSTDBYCTL);
1058 crstandvid = I915_READ16(CRSTANDVID);
1059
1060 mutex_unlock(&dev->struct_mutex);
f97108d1
JB		 1061
1062 seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
1063 "yes" : "no");
1064 seq_printf(m, "Boost freq: %d\n",
1065 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1066 MEMMODE_BOOST_FREQ_SHIFT);
1067 seq_printf(m, "HW control enabled: %s\n",
1068 rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");
1069 seq_printf(m, "SW control enabled: %s\n",
1070 rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");
1071 seq_printf(m, "Gated voltage change: %s\n",
1072 rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");
1073 seq_printf(m, "Starting frequency: P%d\n",
1074 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
7648fa99 1075 seq_printf(m, "Max P-state: P%d\n",
f97108d1 1076 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
7648fa99
JB		 1077 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1078 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1079 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1080 seq_printf(m, "Render standby enabled: %s\n",
1081 (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes");
267f0c90 1082 seq_puts(m, "Current RS state: ");
88271da3
JB		 1083 switch (rstdbyctl & RSX_STATUS_MASK) {
1084 case RSX_STATUS_ON:
267f0c90 1085 seq_puts(m, "on\n");
88271da3
JB		 1086 break;
1087 case RSX_STATUS_RC1:
267f0c90 1088 seq_puts(m, "RC1\n");
88271da3
JB		 1089 break;
1090 case RSX_STATUS_RC1E:
267f0c90 1091 seq_puts(m, "RC1E\n");
88271da3
JB		 1092 break;
1093 case RSX_STATUS_RS1:
267f0c90 1094 seq_puts(m, "RS1\n");
88271da3
JB		 1095 break;
1096 case RSX_STATUS_RS2:
267f0c90 1097 seq_puts(m, "RS2 (RC6)\n");
88271da3
JB		 1098 break;
1099 case RSX_STATUS_RS3:
267f0c90 1100 seq_puts(m, "RC3 (RC6+)\n");
88271da3
JB		 1101 break;
1102 default:
267f0c90 1103 seq_puts(m, "unknown\n");
88271da3
JB		 1104 break;
1105 }
f97108d1
JB		 1106
1107 return 0;
1108}
1109
4d85529d
BW		 1110static int gen6_drpc_info(struct seq_file *m)
1111{
1112
1113 struct drm_info_node *node = (struct drm_info_node *) m->private;
1114 struct drm_device *dev = node->minor->dev;
1115 struct drm_i915_private *dev_priv = dev->dev_private;
ecd8faea 1116 u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
93b525dc 1117 unsigned forcewake_count;
aee56cff 1118 int count = 0, ret;
4d85529d
BW		 1119
1120 ret = mutex_lock_interruptible(&dev->struct_mutex);
1121 if (ret)
1122 return ret;
1123
907b28c5
CW		 1124 spin_lock_irq(&dev_priv->uncore.lock);
1125 forcewake_count = dev_priv->uncore.forcewake_count;
1126 spin_unlock_irq(&dev_priv->uncore.lock);
93b525dc
DV		 1127
1128 if (forcewake_count) {
267f0c90
DL		 1129 seq_puts(m, "RC information inaccurate because somebody "
1130 "holds a forcewake reference \n");
4d85529d
BW		 1131 } else {
1132 /* NB: we cannot use forcewake, else we read the wrong values */
1133 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1134 udelay(10);
1135 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1136 }
1137
1138 gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS);
ed71f1b4 1139 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
4d85529d
BW		 1140
1141 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1142 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1143 mutex_unlock(&dev->struct_mutex);
44cbd338
BW		 1144 mutex_lock(&dev_priv->rps.hw_lock);
1145 sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1146 mutex_unlock(&dev_priv->rps.hw_lock);
4d85529d
BW		 1147
1148 seq_printf(m, "Video Turbo Mode: %s\n",
1149 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1150 seq_printf(m, "HW control enabled: %s\n",
1151 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1152 seq_printf(m, "SW control enabled: %s\n",
1153 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1154 GEN6_RP_MEDIA_SW_MODE));
fff24e21 1155 seq_printf(m, "RC1e Enabled: %s\n",
4d85529d
BW		 1156 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1157 seq_printf(m, "RC6 Enabled: %s\n",
1158 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1159 seq_printf(m, "Deep RC6 Enabled: %s\n",
1160 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1161 seq_printf(m, "Deepest RC6 Enabled: %s\n",
1162 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
267f0c90 1163 seq_puts(m, "Current RC state: ");
4d85529d
BW		 1164 switch (gt_core_status & GEN6_RCn_MASK) {
1165 case GEN6_RC0:
1166 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
267f0c90 1167 seq_puts(m, "Core Power Down\n");
4d85529d 1168 else
267f0c90 1169 seq_puts(m, "on\n");
4d85529d
BW		 1170 break;
1171 case GEN6_RC3:
267f0c90 1172 seq_puts(m, "RC3\n");
4d85529d
BW		 1173 break;
1174 case GEN6_RC6:
267f0c90 1175 seq_puts(m, "RC6\n");
4d85529d
BW		 1176 break;
1177 case GEN6_RC7:
267f0c90 1178 seq_puts(m, "RC7\n");
4d85529d
BW		 1179 break;
1180 default:
267f0c90 1181 seq_puts(m, "Unknown\n");
4d85529d
BW		 1182 break;
1183 }
1184
1185 seq_printf(m, "Core Power Down: %s\n",
1186 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
cce66a28
BW		 1187
1188 /* Not exactly sure what this is */
1189 seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1190 I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1191 seq_printf(m, "RC6 residency since boot: %u\n",
1192 I915_READ(GEN6_GT_GFX_RC6));
1193 seq_printf(m, "RC6+ residency since boot: %u\n",
1194 I915_READ(GEN6_GT_GFX_RC6p));
1195 seq_printf(m, "RC6++ residency since boot: %u\n",
1196 I915_READ(GEN6_GT_GFX_RC6pp));
1197
ecd8faea
BW		 1198 seq_printf(m, "RC6 voltage: %dmV\n",
1199 GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1200 seq_printf(m, "RC6+ voltage: %dmV\n",
1201 GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1202 seq_printf(m, "RC6++ voltage: %dmV\n",
1203 GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
4d85529d
BW		 1204 return 0;
1205}
1206
1207static int i915_drpc_info(struct seq_file *m, void *unused)
1208{
1209 struct drm_info_node *node = (struct drm_info_node *) m->private;
1210 struct drm_device *dev = node->minor->dev;
1211
1212 if (IS_GEN6(dev) || IS_GEN7(dev))
1213 return gen6_drpc_info(m);
1214 else
1215 return ironlake_drpc_info(m);
1216}
1217
b5e50c3f
JB		 1218static int i915_fbc_status(struct seq_file *m, void *unused)
1219{
1220 struct drm_info_node *node = (struct drm_info_node *) m->private;
1221 struct drm_device *dev = node->minor->dev;
b5e50c3f 1222 drm_i915_private_t *dev_priv = dev->dev_private;
b5e50c3f 1223
ee5382ae 1224 if (!I915_HAS_FBC(dev)) {
267f0c90 1225 seq_puts(m, "FBC unsupported on this chipset\n");
b5e50c3f
JB		 1226 return 0;
1227 }
1228
ee5382ae 1229 if (intel_fbc_enabled(dev)) {
267f0c90 1230 seq_puts(m, "FBC enabled\n");
b5e50c3f 1231 } else {
267f0c90 1232 seq_puts(m, "FBC disabled: ");
5c3fe8b0 1233 switch (dev_priv->fbc.no_fbc_reason) {
29ebf90f
CW		 1234 case FBC_OK:
1235 seq_puts(m, "FBC actived, but currently disabled in hardware");
1236 break;
1237 case FBC_UNSUPPORTED:
1238 seq_puts(m, "unsupported by this chipset");
1239 break;
bed4a673 1240 case FBC_NO_OUTPUT:
267f0c90 1241 seq_puts(m, "no outputs");
bed4a673 1242 break;
b5e50c3f 1243 case FBC_STOLEN_TOO_SMALL:
267f0c90 1244 seq_puts(m, "not enough stolen memory");
b5e50c3f
JB		 1245 break;
1246 case FBC_UNSUPPORTED_MODE:
267f0c90 1247 seq_puts(m, "mode not supported");
b5e50c3f
JB		 1248 break;
1249 case FBC_MODE_TOO_LARGE:
267f0c90 1250 seq_puts(m, "mode too large");
b5e50c3f
JB		 1251 break;
1252 case FBC_BAD_PLANE:
267f0c90 1253 seq_puts(m, "FBC unsupported on plane");
b5e50c3f
JB		 1254 break;
1255 case FBC_NOT_TILED:
267f0c90 1256 seq_puts(m, "scanout buffer not tiled");
b5e50c3f 1257 break;
9c928d16 1258 case FBC_MULTIPLE_PIPES:
267f0c90 1259 seq_puts(m, "multiple pipes are enabled");
9c928d16 1260 break;
c1a9f047 1261 case FBC_MODULE_PARAM:
267f0c90 1262 seq_puts(m, "disabled per module param (default off)");
c1a9f047 1263 break;
8a5729a3 1264 case FBC_CHIP_DEFAULT:
267f0c90 1265 seq_puts(m, "disabled per chip default");
8a5729a3 1266 break;
b5e50c3f 1267 default:
267f0c90 1268 seq_puts(m, "unknown reason");
b5e50c3f 1269 }
267f0c90 1270 seq_putc(m, '\n');
b5e50c3f
JB		 1271 }
1272 return 0;
1273}
1274
92d44621
PZ		 1275static int i915_ips_status(struct seq_file *m, void *unused)
1276{
1277 struct drm_info_node *node = (struct drm_info_node *) m->private;
1278 struct drm_device *dev = node->minor->dev;
1279 struct drm_i915_private *dev_priv = dev->dev_private;
1280
f5adf94e 1281 if (!HAS_IPS(dev)) {
92d44621
PZ		 1282 seq_puts(m, "not supported\n");
1283 return 0;
1284 }
1285
1286 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1287 seq_puts(m, "enabled\n");
1288 else
1289 seq_puts(m, "disabled\n");
1290
1291 return 0;
1292}
1293
4a9bef37
JB		 1294static int i915_sr_status(struct seq_file *m, void *unused)
1295{
1296 struct drm_info_node *node = (struct drm_info_node *) m->private;
1297 struct drm_device *dev = node->minor->dev;
1298 drm_i915_private_t *dev_priv = dev->dev_private;
1299 bool sr_enabled = false;
1300
1398261a 1301 if (HAS_PCH_SPLIT(dev))
5ba2aaaa 1302 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
a6c45cf0 1303 else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))
4a9bef37
JB		 1304 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1305 else if (IS_I915GM(dev))
1306 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1307 else if (IS_PINEVIEW(dev))
1308 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1309
5ba2aaaa
CW		 1310 seq_printf(m, "self-refresh: %s\n",
1311 sr_enabled ? "enabled" : "disabled");
4a9bef37
JB		 1312
1313 return 0;
1314}
1315
7648fa99
JB		 1316static int i915_emon_status(struct seq_file *m, void *unused)
1317{
1318 struct drm_info_node *node = (struct drm_info_node *) m->private;
1319 struct drm_device *dev = node->minor->dev;
1320 drm_i915_private_t *dev_priv = dev->dev_private;
1321 unsigned long temp, chipset, gfx;
de227ef0
CW		 1322 int ret;
1323
582be6b4
CW		 1324 if (!IS_GEN5(dev))
1325 return -ENODEV;
1326
de227ef0
CW		 1327 ret = mutex_lock_interruptible(&dev->struct_mutex);
1328 if (ret)
1329 return ret;
7648fa99
JB		 1330
1331 temp = i915_mch_val(dev_priv);
1332 chipset = i915_chipset_val(dev_priv);
1333 gfx = i915_gfx_val(dev_priv);
de227ef0 1334 mutex_unlock(&dev->struct_mutex);
7648fa99
JB		 1335
1336 seq_printf(m, "GMCH temp: %ld\n", temp);
1337 seq_printf(m, "Chipset power: %ld\n", chipset);
1338 seq_printf(m, "GFX power: %ld\n", gfx);
1339 seq_printf(m, "Total power: %ld\n", chipset + gfx);
1340
1341 return 0;
1342}
1343
23b2f8bb
JB		 1344static int i915_ring_freq_table(struct seq_file *m, void *unused)
1345{
1346 struct drm_info_node *node = (struct drm_info_node *) m->private;
1347 struct drm_device *dev = node->minor->dev;
1348 drm_i915_private_t *dev_priv = dev->dev_private;
1349 int ret;
1350 int gpu_freq, ia_freq;
1351
1c70c0ce 1352 if (!(IS_GEN6(dev) || IS_GEN7(dev))) {
267f0c90 1353 seq_puts(m, "unsupported on this chipset\n");
23b2f8bb
JB		 1354 return 0;
1355 }
1356
5c9669ce
TR		 1357 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1358
4fc688ce 1359 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
23b2f8bb
JB		 1360 if (ret)
1361 return ret;
1362
267f0c90 1363 seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
23b2f8bb 1364
c6a828d3
DV		 1365 for (gpu_freq = dev_priv->rps.min_delay;
1366 gpu_freq <= dev_priv->rps.max_delay;
23b2f8bb 1367 gpu_freq++) {
42c0526c
BW		 1368 ia_freq = gpu_freq;
1369 sandybridge_pcode_read(dev_priv,
1370 GEN6_PCODE_READ_MIN_FREQ_TABLE,
1371 &ia_freq);
3ebecd07
CW		 1372 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1373 gpu_freq * GT_FREQUENCY_MULTIPLIER,
1374 ((ia_freq >> 0) & 0xff) * 100,
1375 ((ia_freq >> 8) & 0xff) * 100);
23b2f8bb
JB		 1376 }
1377
4fc688ce 1378 mutex_unlock(&dev_priv->rps.hw_lock);
23b2f8bb
JB		 1379
1380 return 0;
1381}
1382
7648fa99
JB		 1383static int i915_gfxec(struct seq_file *m, void *unused)
1384{
1385 struct drm_info_node *node = (struct drm_info_node *) m->private;
1386 struct drm_device *dev = node->minor->dev;
1387 drm_i915_private_t *dev_priv = dev->dev_private;
616fdb5a
BW		 1388 int ret;
1389
1390 ret = mutex_lock_interruptible(&dev->struct_mutex);
1391 if (ret)
1392 return ret;
7648fa99
JB		 1393
1394 seq_printf(m, "GFXEC: %ld\n", (unsigned long)I915_READ(0x112f4));
1395
616fdb5a
BW		 1396 mutex_unlock(&dev->struct_mutex);
1397
7648fa99
JB		 1398 return 0;
1399}
1400
44834a67
CW		 1401static int i915_opregion(struct seq_file *m, void *unused)
1402{
1403 struct drm_info_node *node = (struct drm_info_node *) m->private;
1404 struct drm_device *dev = node->minor->dev;
1405 drm_i915_private_t *dev_priv = dev->dev_private;
1406 struct intel_opregion *opregion = &dev_priv->opregion;
0d38f009 1407 void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL);
44834a67
CW		 1408 int ret;
1409
0d38f009
DV		 1410 if (data == NULL)
1411 return -ENOMEM;
1412
44834a67
CW		 1413 ret = mutex_lock_interruptible(&dev->struct_mutex);
1414 if (ret)
0d38f009 1415 goto out;
44834a67 1416
0d38f009
DV		 1417 if (opregion->header) {
1418 memcpy_fromio(data, opregion->header, OPREGION_SIZE);
1419 seq_write(m, data, OPREGION_SIZE);
1420 }
44834a67
CW		 1421
1422 mutex_unlock(&dev->struct_mutex);
1423
0d38f009
DV		 1424out:
1425 kfree(data);
44834a67
CW		 1426 return 0;
1427}
1428
37811fcc
CW		 1429static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1430{
1431 struct drm_info_node *node = (struct drm_info_node *) m->private;
1432 struct drm_device *dev = node->minor->dev;
4520f53a 1433 struct intel_fbdev *ifbdev = NULL;
37811fcc 1434 struct intel_framebuffer *fb;
37811fcc 1435
4520f53a
DV		 1436#ifdef CONFIG_DRM_I915_FBDEV
1437 struct drm_i915_private *dev_priv = dev->dev_private;
1438 int ret = mutex_lock_interruptible(&dev->mode_config.mutex);
37811fcc
CW		 1439 if (ret)
1440 return ret;
1441
1442 ifbdev = dev_priv->fbdev;
1443 fb = to_intel_framebuffer(ifbdev->helper.fb);
1444
623f9783 1445 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
37811fcc
CW		 1446 fb->base.width,
1447 fb->base.height,
1448 fb->base.depth,
623f9783
DV		 1449 fb->base.bits_per_pixel,
1450 atomic_read(&fb->base.refcount.refcount));
05394f39 1451 describe_obj(m, fb->obj);
267f0c90 1452 seq_putc(m, '\n');
4b096ac1 1453 mutex_unlock(&dev->mode_config.mutex);
4520f53a 1454#endif
37811fcc 1455
4b096ac1 1456 mutex_lock(&dev->mode_config.fb_lock);
37811fcc 1457 list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) {
131a56dc 1458 if (ifbdev && &fb->base == ifbdev->helper.fb)
37811fcc
CW		 1459 continue;
1460
623f9783 1461 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
37811fcc
CW		 1462 fb->base.width,
1463 fb->base.height,
1464 fb->base.depth,
623f9783
DV		 1465 fb->base.bits_per_pixel,
1466 atomic_read(&fb->base.refcount.refcount));
05394f39 1467 describe_obj(m, fb->obj);
267f0c90 1468 seq_putc(m, '\n');
37811fcc 1469 }
4b096ac1 1470 mutex_unlock(&dev->mode_config.fb_lock);
37811fcc
CW		 1471
1472 return 0;
1473}
1474
e76d3630
BW		 1475static int i915_context_status(struct seq_file *m, void *unused)
1476{
1477 struct drm_info_node *node = (struct drm_info_node *) m->private;
1478 struct drm_device *dev = node->minor->dev;
1479 drm_i915_private_t *dev_priv = dev->dev_private;
a168c293 1480 struct intel_ring_buffer *ring;
a33afea5 1481 struct i915_hw_context *ctx;
a168c293 1482 int ret, i;
e76d3630
BW		 1483
1484 ret = mutex_lock_interruptible(&dev->mode_config.mutex);
1485 if (ret)
1486 return ret;
1487
3e373948 1488 if (dev_priv->ips.pwrctx) {
267f0c90 1489 seq_puts(m, "power context ");
3e373948 1490 describe_obj(m, dev_priv->ips.pwrctx);
267f0c90 1491 seq_putc(m, '\n');
dc501fbc 1492 }
e76d3630 1493
3e373948 1494 if (dev_priv->ips.renderctx) {
267f0c90 1495 seq_puts(m, "render context ");
3e373948 1496 describe_obj(m, dev_priv->ips.renderctx);
267f0c90 1497 seq_putc(m, '\n');
dc501fbc 1498 }
e76d3630 1499
a33afea5
BW		 1500 list_for_each_entry(ctx, &dev_priv->context_list, link) {
1501 seq_puts(m, "HW context ");
3ccfd19d 1502 describe_ctx(m, ctx);
a33afea5
BW		 1503 for_each_ring(ring, dev_priv, i)
1504 if (ring->default_context == ctx)
1505 seq_printf(m, "(default context %s) ", ring->name);
1506
1507 describe_obj(m, ctx->obj);
1508 seq_putc(m, '\n');
a168c293
BW		 1509 }
1510
e76d3630
BW		 1511 mutex_unlock(&dev->mode_config.mutex);
1512
1513 return 0;
1514}
1515
6d794d42
BW		 1516static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data)
1517{
1518 struct drm_info_node *node = (struct drm_info_node *) m->private;
1519 struct drm_device *dev = node->minor->dev;
1520 struct drm_i915_private *dev_priv = dev->dev_private;
9f1f46a4 1521 unsigned forcewake_count;
6d794d42 1522
907b28c5
CW		 1523 spin_lock_irq(&dev_priv->uncore.lock);
1524 forcewake_count = dev_priv->uncore.forcewake_count;
1525 spin_unlock_irq(&dev_priv->uncore.lock);
6d794d42 1526
9f1f46a4 1527 seq_printf(m, "forcewake count = %u\n", forcewake_count);
6d794d42
BW		 1528
1529 return 0;
1530}
1531
ea16a3cd
DV		 1532static const char *swizzle_string(unsigned swizzle)
1533{
aee56cff 1534 switch (swizzle) {
ea16a3cd
DV		 1535 case I915_BIT_6_SWIZZLE_NONE:
1536 return "none";
1537 case I915_BIT_6_SWIZZLE_9:
1538 return "bit9";
1539 case I915_BIT_6_SWIZZLE_9_10:
1540 return "bit9/bit10";
1541 case I915_BIT_6_SWIZZLE_9_11:
1542 return "bit9/bit11";
1543 case I915_BIT_6_SWIZZLE_9_10_11:
1544 return "bit9/bit10/bit11";
1545 case I915_BIT_6_SWIZZLE_9_17:
1546 return "bit9/bit17";
1547 case I915_BIT_6_SWIZZLE_9_10_17:
1548 return "bit9/bit10/bit17";
1549 case I915_BIT_6_SWIZZLE_UNKNOWN:
8a168ca7 1550 return "unknown";
ea16a3cd
DV		 1551 }
1552
1553 return "bug";
1554}
1555
1556static int i915_swizzle_info(struct seq_file *m, void *data)
1557{
1558 struct drm_info_node *node = (struct drm_info_node *) m->private;
1559 struct drm_device *dev = node->minor->dev;
1560 struct drm_i915_private *dev_priv = dev->dev_private;
22bcfc6a
DV		 1561 int ret;
1562
1563 ret = mutex_lock_interruptible(&dev->struct_mutex);
1564 if (ret)
1565 return ret;
ea16a3cd 1566
ea16a3cd
DV		 1567 seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
1568 swizzle_string(dev_priv->mm.bit_6_swizzle_x));
1569 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
1570 swizzle_string(dev_priv->mm.bit_6_swizzle_y));
1571
1572 if (IS_GEN3(dev) || IS_GEN4(dev)) {
1573 seq_printf(m, "DDC = 0x%08x\n",
1574 I915_READ(DCC));
1575 seq_printf(m, "C0DRB3 = 0x%04x\n",
1576 I915_READ16(C0DRB3));
1577 seq_printf(m, "C1DRB3 = 0x%04x\n",
1578 I915_READ16(C1DRB3));
3fa7d235
DV		 1579 } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
1580 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
1581 I915_READ(MAD_DIMM_C0));
1582 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
1583 I915_READ(MAD_DIMM_C1));
1584 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
1585 I915_READ(MAD_DIMM_C2));
1586 seq_printf(m, "TILECTL = 0x%08x\n",
1587 I915_READ(TILECTL));
1588 seq_printf(m, "ARB_MODE = 0x%08x\n",
1589 I915_READ(ARB_MODE));
1590 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
1591 I915_READ(DISP_ARB_CTL));
ea16a3cd
DV		 1592 }
1593 mutex_unlock(&dev->struct_mutex);
1594
1595 return 0;
1596}
1597
3cf17fc5
DV		 1598static int i915_ppgtt_info(struct seq_file *m, void *data)
1599{
1600 struct drm_info_node *node = (struct drm_info_node *) m->private;
1601 struct drm_device *dev = node->minor->dev;
1602 struct drm_i915_private *dev_priv = dev->dev_private;
1603 struct intel_ring_buffer *ring;
1604 int i, ret;
1605
1606
1607 ret = mutex_lock_interruptible(&dev->struct_mutex);
1608 if (ret)
1609 return ret;
1610 if (INTEL_INFO(dev)->gen == 6)
1611 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
1612
a2c7f6fd 1613 for_each_ring(ring, dev_priv, i) {
3cf17fc5
DV		 1614 seq_printf(m, "%s\n", ring->name);
1615 if (INTEL_INFO(dev)->gen == 7)
1616 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
1617 seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
1618 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
1619 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring)));
1620 }
1621 if (dev_priv->mm.aliasing_ppgtt) {
1622 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
1623
267f0c90 1624 seq_puts(m, "aliasing PPGTT:\n");
3cf17fc5
DV		 1625 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset);
1626 }
1627 seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
1628 mutex_unlock(&dev->struct_mutex);
1629
1630 return 0;
1631}
1632
57f350b6
JB		 1633static int i915_dpio_info(struct seq_file *m, void *data)
1634{
1635 struct drm_info_node *node = (struct drm_info_node *) m->private;
1636 struct drm_device *dev = node->minor->dev;
1637 struct drm_i915_private *dev_priv = dev->dev_private;
1638 int ret;
1639
1640
1641 if (!IS_VALLEYVIEW(dev)) {
267f0c90 1642 seq_puts(m, "unsupported\n");
57f350b6
JB		 1643 return 0;
1644 }
1645
09153000 1646 ret = mutex_lock_interruptible(&dev_priv->dpio_lock);
57f350b6
JB		 1647 if (ret)
1648 return ret;
1649
1650 seq_printf(m, "DPIO_CTL: 0x%08x\n", I915_READ(DPIO_CTL));
1651
ab3c759a
CML		 1652 seq_printf(m, "DPIO PLL DW3 CH0 : 0x%08x\n",
1653 vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW3(0)));
1654 seq_printf(m, "DPIO PLL DW3 CH1: 0x%08x\n",
1655 vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW3(1)));
1656
1657 seq_printf(m, "DPIO PLL DW5 CH0: 0x%08x\n",
1658 vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW5(0)));
1659 seq_printf(m, "DPIO PLL DW5 CH1: 0x%08x\n",
1660 vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW5(1)));
1661
1662 seq_printf(m, "DPIO PLL DW7 CH0: 0x%08x\n",
1663 vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW7(0)));
1664 seq_printf(m, "DPIO PLL DW7 CH1: 0x%08x\n",
1665 vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW7(1)));
1666
1667 seq_printf(m, "DPIO PLL DW10 CH0: 0x%08x\n",
1668 vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW10(0)));
1669 seq_printf(m, "DPIO PLL DW10 CH1: 0x%08x\n",
1670 vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW10(1)));
57f350b6
JB		 1671
1672 seq_printf(m, "DPIO_FASTCLK_DISABLE: 0x%08x\n",
ab3c759a 1673 vlv_dpio_read(dev_priv, PIPE_A, VLV_CMN_DW0));
57f350b6 1674
09153000 1675 mutex_unlock(&dev_priv->dpio_lock);
57f350b6
JB		 1676
1677 return 0;
1678}
1679
63573eb7
BW		 1680static int i915_llc(struct seq_file *m, void *data)
1681{
1682 struct drm_info_node *node = (struct drm_info_node *) m->private;
1683 struct drm_device *dev = node->minor->dev;
1684 struct drm_i915_private *dev_priv = dev->dev_private;
1685
1686 /* Size calculation for LLC is a bit of a pain. Ignore for now. */
1687 seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
1688 seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size);
1689
1690 return 0;
1691}
1692
e91fd8c6
RV		 1693static int i915_edp_psr_status(struct seq_file *m, void *data)
1694{
1695 struct drm_info_node *node = m->private;
1696 struct drm_device *dev = node->minor->dev;
1697 struct drm_i915_private *dev_priv = dev->dev_private;
a031d709
RV		 1698 u32 psrperf = 0;
1699 bool enabled = false;
e91fd8c6 1700
a031d709
RV		 1701 seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
1702 seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
e91fd8c6 1703
a031d709
RV		 1704 enabled = HAS_PSR(dev) &&
1705 I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
1706 seq_printf(m, "Enabled: %s\n", yesno(enabled));
e91fd8c6 1707
a031d709
RV		 1708 if (HAS_PSR(dev))
1709 psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) &
1710 EDP_PSR_PERF_CNT_MASK;
1711 seq_printf(m, "Performance_Counter: %u\n", psrperf);
e91fd8c6
RV		 1712
1713 return 0;
1714}
1715
ec013e7f
JB		 1716static int i915_energy_uJ(struct seq_file *m, void *data)
1717{
1718 struct drm_info_node *node = m->private;
1719 struct drm_device *dev = node->minor->dev;
1720 struct drm_i915_private *dev_priv = dev->dev_private;
1721 u64 power;
1722 u32 units;
1723
1724 if (INTEL_INFO(dev)->gen < 6)
1725 return -ENODEV;
1726
1727 rdmsrl(MSR_RAPL_POWER_UNIT, power);
1728 power = (power & 0x1f00) >> 8;
1729 units = 1000000 / (1 << power); /* convert to uJ */
1730 power = I915_READ(MCH_SECP_NRG_STTS);
1731 power *= units;
1732
1733 seq_printf(m, "%llu", (long long unsigned)power);
371db66a
PZ		 1734
1735 return 0;
1736}
1737
1738static int i915_pc8_status(struct seq_file *m, void *unused)
1739{
1740 struct drm_info_node *node = (struct drm_info_node *) m->private;
1741 struct drm_device *dev = node->minor->dev;
1742 struct drm_i915_private *dev_priv = dev->dev_private;
1743
1744 if (!IS_HASWELL(dev)) {
1745 seq_puts(m, "not supported\n");
1746 return 0;
1747 }
1748
1749 mutex_lock(&dev_priv->pc8.lock);
1750 seq_printf(m, "Requirements met: %s\n",
1751 yesno(dev_priv->pc8.requirements_met));
1752 seq_printf(m, "GPU idle: %s\n", yesno(dev_priv->pc8.gpu_idle));
1753 seq_printf(m, "Disable count: %d\n", dev_priv->pc8.disable_count);
1754 seq_printf(m, "IRQs disabled: %s\n",
1755 yesno(dev_priv->pc8.irqs_disabled));
1756 seq_printf(m, "Enabled: %s\n", yesno(dev_priv->pc8.enabled));
1757 mutex_unlock(&dev_priv->pc8.lock);
1758
ec013e7f
JB		 1759 return 0;
1760}
1761
07144428
DL		 1762struct pipe_crc_info {
1763 const char *name;
1764 struct drm_device *dev;
1765 enum pipe pipe;
1766};
1767
1768static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
1769{
be5c7a90
DL		 1770 struct pipe_crc_info *info = inode->i_private;
1771 struct drm_i915_private *dev_priv = info->dev->dev_private;
1772 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
1773
d538bbdf
DL		 1774 spin_lock_irq(&pipe_crc->lock);
1775
1776 if (pipe_crc->opened) {
1777 spin_unlock_irq(&pipe_crc->lock);
be5c7a90
DL		 1778 return -EBUSY; /* already open */
1779 }
1780
d538bbdf 1781 pipe_crc->opened = true;
07144428
DL		 1782 filep->private_data = inode->i_private;
1783
d538bbdf
DL		 1784 spin_unlock_irq(&pipe_crc->lock);
1785
07144428
DL		 1786 return 0;
1787}
1788
1789static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
1790{
be5c7a90
DL		 1791 struct pipe_crc_info *info = inode->i_private;
1792 struct drm_i915_private *dev_priv = info->dev->dev_private;
1793 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
1794
d538bbdf
DL		 1795 spin_lock_irq(&pipe_crc->lock);
1796 pipe_crc->opened = false;
1797 spin_unlock_irq(&pipe_crc->lock);
be5c7a90 1798
07144428
DL		 1799 return 0;
1800}
1801
1802/* (6 fields, 8 chars each, space separated (5) + '\n') */
1803#define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
1804/* account for \'0' */
1805#define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1)
1806
1807static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
8bf1e9f1 1808{
d538bbdf
DL		 1809 assert_spin_locked(&pipe_crc->lock);
1810 return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
1811 INTEL_PIPE_CRC_ENTRIES_NR);
07144428
DL		 1812}
1813
1814static ssize_t
1815i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
1816 loff_t *pos)
1817{
1818 struct pipe_crc_info *info = filep->private_data;
1819 struct drm_device *dev = info->dev;
1820 struct drm_i915_private *dev_priv = dev->dev_private;
1821 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
1822 char buf[PIPE_CRC_BUFFER_LEN];
1823 int head, tail, n_entries, n;
1824 ssize_t bytes_read;
1825
1826 /*
1827 * Don't allow user space to provide buffers not big enough to hold
1828 * a line of data.
1829 */
1830 if (count < PIPE_CRC_LINE_LEN)
1831 return -EINVAL;
1832
1833 if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
8bf1e9f1 1834 return 0;
07144428
DL		 1835
1836 /* nothing to read */
d538bbdf 1837 spin_lock_irq(&pipe_crc->lock);
07144428 1838 while (pipe_crc_data_count(pipe_crc) == 0) {
d538bbdf
DL		 1839 int ret;
1840
1841 if (filep->f_flags & O_NONBLOCK) {
1842 spin_unlock_irq(&pipe_crc->lock);
07144428 1843 return -EAGAIN;
d538bbdf 1844 }
07144428 1845
d538bbdf
DL		 1846 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
1847 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
1848 if (ret) {
1849 spin_unlock_irq(&pipe_crc->lock);
1850 return ret;
1851 }
8bf1e9f1
SH		 1852 }
1853
07144428 1854 /* We now have one or more entries to read */
d538bbdf
DL		 1855 head = pipe_crc->head;
1856 tail = pipe_crc->tail;
07144428
DL		 1857 n_entries = min((size_t)CIRC_CNT(head, tail, INTEL_PIPE_CRC_ENTRIES_NR),
1858 count / PIPE_CRC_LINE_LEN);
d538bbdf
DL		 1859 spin_unlock_irq(&pipe_crc->lock);
1860
07144428
DL		 1861 bytes_read = 0;
1862 n = 0;
1863 do {
b2c88f5b 1864 struct intel_pipe_crc_entry *entry = &pipe_crc->entries[tail];
07144428 1865 int ret;
8bf1e9f1 1866
07144428
DL		 1867 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
1868 "%8u %8x %8x %8x %8x %8x\n",
1869 entry->frame, entry->crc[0],
1870 entry->crc[1], entry->crc[2],
1871 entry->crc[3], entry->crc[4]);
1872
1873 ret = copy_to_user(user_buf + n * PIPE_CRC_LINE_LEN,
1874 buf, PIPE_CRC_LINE_LEN);
1875 if (ret == PIPE_CRC_LINE_LEN)
1876 return -EFAULT;
b2c88f5b
DL		 1877
1878 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
1879 tail = (tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
07144428
DL		 1880 n++;
1881 } while (--n_entries);
8bf1e9f1 1882
d538bbdf
DL		 1883 spin_lock_irq(&pipe_crc->lock);
1884 pipe_crc->tail = tail;
1885 spin_unlock_irq(&pipe_crc->lock);
1886
07144428
DL		 1887 return bytes_read;
1888}
1889
1890static const struct file_operations i915_pipe_crc_fops = {
1891 .owner = THIS_MODULE,
1892 .open = i915_pipe_crc_open,
1893 .read = i915_pipe_crc_read,
1894 .release = i915_pipe_crc_release,
1895};
1896
1897static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
1898 {
1899 .name = "i915_pipe_A_crc",
1900 .pipe = PIPE_A,
1901 },
1902 {
1903 .name = "i915_pipe_B_crc",
1904 .pipe = PIPE_B,
1905 },
1906 {
1907 .name = "i915_pipe_C_crc",
1908 .pipe = PIPE_C,
1909 },
1910};
1911
1912static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
1913 enum pipe pipe)
1914{
1915 struct drm_device *dev = minor->dev;
1916 struct dentry *ent;
1917 struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
1918
1919 info->dev = dev;
1920 ent = debugfs_create_file(info->name, S_IRUGO, root, info,
1921 &i915_pipe_crc_fops);
1922 if (IS_ERR(ent))
1923 return PTR_ERR(ent);
1924
1925 return drm_add_fake_info_node(minor, ent, info);
8bf1e9f1
SH		 1926}
1927
e8dfcf78 1928static const char * const pipe_crc_sources[] = {
926321d5
DV		 1929 "none",
1930 "plane1",
1931 "plane2",
1932 "pf",
5b3a856b 1933 "pipe",
3d099a05
DV		 1934 "TV",
1935 "DP-B",
1936 "DP-C",
1937 "DP-D",
46a19188 1938 "auto",
926321d5
DV		 1939};
1940
1941static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
1942{
1943 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
1944 return pipe_crc_sources[source];
1945}
1946
bd9db02f 1947static int display_crc_ctl_show(struct seq_file *m, void *data)
926321d5
DV		 1948{
1949 struct drm_device *dev = m->private;
1950 struct drm_i915_private *dev_priv = dev->dev_private;
1951 int i;
1952
1953 for (i = 0; i < I915_MAX_PIPES; i++)
1954 seq_printf(m, "%c %s\n", pipe_name(i),
1955 pipe_crc_source_name(dev_priv->pipe_crc[i].source));
1956
1957 return 0;
1958}
1959
bd9db02f 1960static int display_crc_ctl_open(struct inode *inode, struct file *file)
926321d5
DV		 1961{
1962 struct drm_device *dev = inode->i_private;
1963
bd9db02f 1964 return single_open(file, display_crc_ctl_show, dev);
926321d5
DV		 1965}
1966
46a19188 1967static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
52f843f6
DV		 1968 uint32_t *val)
1969{
46a19188
DV		 1970 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
1971 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
1972
1973 switch (*source) {
52f843f6
DV		 1974 case INTEL_PIPE_CRC_SOURCE_PIPE:
1975 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
1976 break;
1977 case INTEL_PIPE_CRC_SOURCE_NONE:
1978 *val = 0;
1979 break;
1980 default:
1981 return -EINVAL;
1982 }
1983
1984 return 0;
1985}
1986
46a19188
DV		 1987static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe,
1988 enum intel_pipe_crc_source *source)
1989{
1990 struct intel_encoder *encoder;
1991 struct intel_crtc *crtc;
26756809 1992 struct intel_digital_port *dig_port;
46a19188
DV		 1993 int ret = 0;
1994
1995 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
1996
1997 mutex_lock(&dev->mode_config.mutex);
1998 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
1999 base.head) {
2000 if (!encoder->base.crtc)
2001 continue;
2002
2003 crtc = to_intel_crtc(encoder->base.crtc);
2004
2005 if (crtc->pipe != pipe)
2006 continue;
2007
2008 switch (encoder->type) {
2009 case INTEL_OUTPUT_TVOUT:
2010 *source = INTEL_PIPE_CRC_SOURCE_TV;
2011 break;
2012 case INTEL_OUTPUT_DISPLAYPORT:
2013 case INTEL_OUTPUT_EDP:
26756809
DV		 2014 dig_port = enc_to_dig_port(&encoder->base);
2015 switch (dig_port->port) {
2016 case PORT_B:
2017 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
2018 break;
2019 case PORT_C:
2020 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
2021 break;
2022 case PORT_D:
2023 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
2024 break;
2025 default:
2026 WARN(1, "nonexisting DP port %c\n",
2027 port_name(dig_port->port));
2028 break;
2029 }
46a19188
DV		 2030 break;
2031 }
2032 }
2033 mutex_unlock(&dev->mode_config.mutex);
2034
2035 return ret;
2036}
2037
2038static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
2039 enum pipe pipe,
2040 enum intel_pipe_crc_source *source,
7ac0129b
DV		 2041 uint32_t *val)
2042{
8d2f24ca
DV		 2043 struct drm_i915_private *dev_priv = dev->dev_private;
2044 bool need_stable_symbols = false;
2045
46a19188
DV		 2046 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
2047 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
2048 if (ret)
2049 return ret;
2050 }
2051
2052 switch (*source) {
7ac0129b
DV		 2053 case INTEL_PIPE_CRC_SOURCE_PIPE:
2054 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
2055 break;
2056 case INTEL_PIPE_CRC_SOURCE_DP_B:
2057 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
8d2f24ca 2058 need_stable_symbols = true;
7ac0129b
DV		 2059 break;
2060 case INTEL_PIPE_CRC_SOURCE_DP_C:
2061 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
8d2f24ca 2062 need_stable_symbols = true;
7ac0129b
DV		 2063 break;
2064 case INTEL_PIPE_CRC_SOURCE_NONE:
2065 *val = 0;
2066 break;
2067 default:
2068 return -EINVAL;
2069 }
2070
8d2f24ca
DV		 2071 /*
2072 * When the pipe CRC tap point is after the transcoders we need
2073 * to tweak symbol-level features to produce a deterministic series of
2074 * symbols for a given frame. We need to reset those features only once
2075 * a frame (instead of every nth symbol):
2076 * - DC-balance: used to ensure a better clock recovery from the data
2077 * link (SDVO)
2078 * - DisplayPort scrambling: used for EMI reduction
2079 */
2080 if (need_stable_symbols) {
2081 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
2082
2083 WARN_ON(!IS_G4X(dev));
2084
2085 tmp |= DC_BALANCE_RESET_VLV;
2086 if (pipe == PIPE_A)
2087 tmp |= PIPE_A_SCRAMBLE_RESET;
2088 else
2089 tmp |= PIPE_B_SCRAMBLE_RESET;
2090
2091 I915_WRITE(PORT_DFT2_G4X, tmp);
2092 }
2093
7ac0129b
DV		 2094 return 0;
2095}
2096
4b79ebf7 2097static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
46a19188
DV		 2098 enum pipe pipe,
2099 enum intel_pipe_crc_source *source,
4b79ebf7
DV		 2100 uint32_t *val)
2101{
84093603
DV		 2102 struct drm_i915_private *dev_priv = dev->dev_private;
2103 bool need_stable_symbols = false;
2104
46a19188
DV		 2105 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
2106 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
2107 if (ret)
2108 return ret;
2109 }
2110
2111 switch (*source) {
4b79ebf7
DV		 2112 case INTEL_PIPE_CRC_SOURCE_PIPE:
2113 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
2114 break;
2115 case INTEL_PIPE_CRC_SOURCE_TV:
2116 if (!SUPPORTS_TV(dev))
2117 return -EINVAL;
2118 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
2119 break;
2120 case INTEL_PIPE_CRC_SOURCE_DP_B:
2121 if (!IS_G4X(dev))
2122 return -EINVAL;
2123 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
84093603 2124 need_stable_symbols = true;
4b79ebf7
DV		 2125 break;
2126 case INTEL_PIPE_CRC_SOURCE_DP_C:
2127 if (!IS_G4X(dev))
2128 return -EINVAL;
2129 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
84093603 2130 need_stable_symbols = true;
4b79ebf7
DV		 2131 break;
2132 case INTEL_PIPE_CRC_SOURCE_DP_D:
2133 if (!IS_G4X(dev))
2134 return -EINVAL;
2135 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
84093603 2136 need_stable_symbols = true;
4b79ebf7
DV		 2137 break;
2138 case INTEL_PIPE_CRC_SOURCE_NONE:
2139 *val = 0;
2140 break;
2141 default:
2142 return -EINVAL;
2143 }
2144
84093603
DV		 2145 /*
2146 * When the pipe CRC tap point is after the transcoders we need
2147 * to tweak symbol-level features to produce a deterministic series of
2148 * symbols for a given frame. We need to reset those features only once
2149 * a frame (instead of every nth symbol):
2150 * - DC-balance: used to ensure a better clock recovery from the data
2151 * link (SDVO)
2152 * - DisplayPort scrambling: used for EMI reduction
2153 */
2154 if (need_stable_symbols) {
2155 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
2156
2157 WARN_ON(!IS_G4X(dev));
2158
2159 I915_WRITE(PORT_DFT_I9XX,
2160 I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
2161
2162 if (pipe == PIPE_A)
2163 tmp |= PIPE_A_SCRAMBLE_RESET;
2164 else
2165 tmp |= PIPE_B_SCRAMBLE_RESET;
2166
2167 I915_WRITE(PORT_DFT2_G4X, tmp);
2168 }
2169
4b79ebf7
DV		 2170 return 0;
2171}
2172
8d2f24ca
DV		 2173static void vlv_undo_pipe_scramble_reset(struct drm_device *dev,
2174 enum pipe pipe)
2175{
2176 struct drm_i915_private *dev_priv = dev->dev_private;
2177 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
2178
2179 if (pipe == PIPE_A)
2180 tmp &= ~PIPE_A_SCRAMBLE_RESET;
2181 else
2182 tmp &= ~PIPE_B_SCRAMBLE_RESET;
2183 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
2184 tmp &= ~DC_BALANCE_RESET_VLV;
2185 I915_WRITE(PORT_DFT2_G4X, tmp);
2186
2187}
2188
84093603
DV		 2189static void g4x_undo_pipe_scramble_reset(struct drm_device *dev,
2190 enum pipe pipe)
2191{
2192 struct drm_i915_private *dev_priv = dev->dev_private;
2193 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
2194
2195 if (pipe == PIPE_A)
2196 tmp &= ~PIPE_A_SCRAMBLE_RESET;
2197 else
2198 tmp &= ~PIPE_B_SCRAMBLE_RESET;
2199 I915_WRITE(PORT_DFT2_G4X, tmp);
2200
2201 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
2202 I915_WRITE(PORT_DFT_I9XX,
2203 I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
2204 }
2205}
2206
46a19188 2207static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
5b3a856b
DV		 2208 uint32_t *val)
2209{
46a19188
DV		 2210 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
2211 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
2212
2213 switch (*source) {
5b3a856b
DV		 2214 case INTEL_PIPE_CRC_SOURCE_PLANE1:
2215 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
2216 break;
2217 case INTEL_PIPE_CRC_SOURCE_PLANE2:
2218 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
2219 break;
5b3a856b
DV		 2220 case INTEL_PIPE_CRC_SOURCE_PIPE:
2221 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
2222 break;
3d099a05 2223 case INTEL_PIPE_CRC_SOURCE_NONE:
5b3a856b
DV		 2224 *val = 0;
2225 break;
3d099a05
DV		 2226 default:
2227 return -EINVAL;
5b3a856b
DV		 2228 }
2229
2230 return 0;
2231}
2232
46a19188 2233static int ivb_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
5b3a856b
DV		 2234 uint32_t *val)
2235{
46a19188
DV		 2236 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
2237 *source = INTEL_PIPE_CRC_SOURCE_PF;
2238
2239 switch (*source) {
5b3a856b
DV		 2240 case INTEL_PIPE_CRC_SOURCE_PLANE1:
2241 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
2242 break;
2243 case INTEL_PIPE_CRC_SOURCE_PLANE2:
2244 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
2245 break;
2246 case INTEL_PIPE_CRC_SOURCE_PF:
2247 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
2248 break;
3d099a05 2249 case INTEL_PIPE_CRC_SOURCE_NONE:
5b3a856b
DV		 2250 *val = 0;
2251 break;
3d099a05
DV		 2252 default:
2253 return -EINVAL;
5b3a856b
DV		 2254 }
2255
2256 return 0;
2257}
2258
926321d5
DV		 2259static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
2260 enum intel_pipe_crc_source source)
2261{
2262 struct drm_i915_private *dev_priv = dev->dev_private;
cc3da175 2263 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
926321d5 2264 u32 val;
5b3a856b 2265 int ret;
926321d5 2266
cc3da175
DL		 2267 if (pipe_crc->source == source)
2268 return 0;
2269
ae676fcd
DL		 2270 /* forbid changing the source without going back to 'none' */
2271 if (pipe_crc->source && source)
2272 return -EINVAL;
2273
52f843f6 2274 if (IS_GEN2(dev))
46a19188 2275 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
52f843f6 2276 else if (INTEL_INFO(dev)->gen < 5)
46a19188 2277 ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
7ac0129b 2278 else if (IS_VALLEYVIEW(dev))
46a19188 2279 ret = vlv_pipe_crc_ctl_reg(dev,pipe, &source, &val);
4b79ebf7 2280 else if (IS_GEN5(dev) || IS_GEN6(dev))
46a19188 2281 ret = ilk_pipe_crc_ctl_reg(&source, &val);
5b3a856b 2282 else
46a19188 2283 ret = ivb_pipe_crc_ctl_reg(&source, &val);
5b3a856b
DV		 2284
2285 if (ret != 0)
2286 return ret;
2287
4b584369
DL		 2288 /* none -> real source transition */
2289 if (source) {
7cd6ccff
DL		 2290 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
2291 pipe_name(pipe), pipe_crc_source_name(source));
2292
e5f75aca
DL		 2293 pipe_crc->entries = kzalloc(sizeof(*pipe_crc->entries) *
2294 INTEL_PIPE_CRC_ENTRIES_NR,
2295 GFP_KERNEL);
2296 if (!pipe_crc->entries)
2297 return -ENOMEM;
2298
d538bbdf
DL		 2299 spin_lock_irq(&pipe_crc->lock);
2300 pipe_crc->head = 0;
2301 pipe_crc->tail = 0;
2302 spin_unlock_irq(&pipe_crc->lock);
4b584369
DL		 2303 }
2304
cc3da175 2305 pipe_crc->source = source;
926321d5 2306
926321d5
DV		 2307 I915_WRITE(PIPE_CRC_CTL(pipe), val);
2308 POSTING_READ(PIPE_CRC_CTL(pipe));
2309
e5f75aca
DL		 2310 /* real source -> none transition */
2311 if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
d538bbdf
DL		 2312 struct intel_pipe_crc_entry *entries;
2313
7cd6ccff
DL		 2314 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
2315 pipe_name(pipe));
2316
bcf17ab2
DV		 2317 intel_wait_for_vblank(dev, pipe);
2318
d538bbdf
DL		 2319 spin_lock_irq(&pipe_crc->lock);
2320 entries = pipe_crc->entries;
e5f75aca 2321 pipe_crc->entries = NULL;
d538bbdf
DL		 2322 spin_unlock_irq(&pipe_crc->lock);
2323
2324 kfree(entries);
84093603
DV		 2325
2326 if (IS_G4X(dev))
2327 g4x_undo_pipe_scramble_reset(dev, pipe);
8d2f24ca
DV		 2328 else if (IS_VALLEYVIEW(dev))
2329 vlv_undo_pipe_scramble_reset(dev, pipe);
e5f75aca
DL		 2330 }
2331
926321d5
DV		 2332 return 0;
2333}
2334
2335/*
2336 * Parse pipe CRC command strings:
b94dec87
DL		 2337 * command: wsp* object wsp+ name wsp+ source wsp*
2338 * object: 'pipe'
2339 * name: (A | B | C)
926321d5
DV		 2340 * source: (none | plane1 | plane2 | pf)
2341 * wsp: (#0x20 | #0x9 | #0xA)+
2342 *
2343 * eg.:
b94dec87
DL		 2344 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A
2345 * "pipe A none" -> Stop CRC
926321d5 2346 */
bd9db02f 2347static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
926321d5
DV		 2348{
2349 int n_words = 0;
2350
2351 while (*buf) {
2352 char *end;
2353
2354 /* skip leading white space */
2355 buf = skip_spaces(buf);
2356 if (!*buf)
2357 break; /* end of buffer */
2358
2359 /* find end of word */
2360 for (end = buf; *end && !isspace(*end); end++)
2361 ;
2362
2363 if (n_words == max_words) {
2364 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
2365 max_words);
2366 return -EINVAL; /* ran out of words[] before bytes */
2367 }
2368
2369 if (*end)
2370 *end++ = '\0';
2371 words[n_words++] = buf;
2372 buf = end;
2373 }
2374
2375 return n_words;
2376}
2377
b94dec87
DL		 2378enum intel_pipe_crc_object {
2379 PIPE_CRC_OBJECT_PIPE,
2380};
2381
e8dfcf78 2382static const char * const pipe_crc_objects[] = {
b94dec87
DL		 2383 "pipe",
2384};
2385
2386static int
bd9db02f 2387display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
b94dec87
DL		 2388{
2389 int i;
2390
2391 for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
2392 if (!strcmp(buf, pipe_crc_objects[i])) {
bd9db02f 2393 *o = i;
b94dec87
DL		 2394 return 0;
2395 }
2396
2397 return -EINVAL;
2398}
2399
bd9db02f 2400static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
926321d5
DV		 2401{
2402 const char name = buf[0];
2403
2404 if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
2405 return -EINVAL;
2406
2407 *pipe = name - 'A';
2408
2409 return 0;
2410}
2411
2412static int
bd9db02f 2413display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
926321d5
DV		 2414{
2415 int i;
2416
2417 for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
2418 if (!strcmp(buf, pipe_crc_sources[i])) {
bd9db02f 2419 *s = i;
926321d5
DV		 2420 return 0;
2421 }
2422
2423 return -EINVAL;
2424}
2425
bd9db02f 2426static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len)
926321d5 2427{
b94dec87 2428#define N_WORDS 3
926321d5 2429 int n_words;
b94dec87 2430 char *words[N_WORDS];
926321d5 2431 enum pipe pipe;
b94dec87 2432 enum intel_pipe_crc_object object;
926321d5
DV		 2433 enum intel_pipe_crc_source source;
2434
bd9db02f 2435 n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
b94dec87
DL		 2436 if (n_words != N_WORDS) {
2437 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
2438 N_WORDS);
2439 return -EINVAL;
2440 }
2441
bd9db02f 2442 if (display_crc_ctl_parse_object(words[0], &object) < 0) {
b94dec87 2443 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
926321d5
DV		 2444 return -EINVAL;
2445 }
2446
bd9db02f 2447 if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
b94dec87 2448 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
926321d5
DV		 2449 return -EINVAL;
2450 }
2451
bd9db02f 2452 if (display_crc_ctl_parse_source(words[2], &source) < 0) {
b94dec87 2453 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
926321d5
DV		 2454 return -EINVAL;
2455 }
2456
2457 return pipe_crc_set_source(dev, pipe, source);
2458}
2459
bd9db02f
DL		 2460static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
2461 size_t len, loff_t *offp)
926321d5
DV		 2462{
2463 struct seq_file *m = file->private_data;
2464 struct drm_device *dev = m->private;
2465 char *tmpbuf;
2466 int ret;
2467
2468 if (len == 0)
2469 return 0;
2470
2471 if (len > PAGE_SIZE - 1) {
2472 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
2473 PAGE_SIZE);
2474 return -E2BIG;
2475 }
2476
2477 tmpbuf = kmalloc(len + 1, GFP_KERNEL);
2478 if (!tmpbuf)
2479 return -ENOMEM;
2480
2481 if (copy_from_user(tmpbuf, ubuf, len)) {
2482 ret = -EFAULT;
2483 goto out;
2484 }
2485 tmpbuf[len] = '\0';
2486
bd9db02f 2487 ret = display_crc_ctl_parse(dev, tmpbuf, len);
926321d5
DV		 2488
2489out:
2490 kfree(tmpbuf);
2491 if (ret < 0)
2492 return ret;
2493
2494 *offp += len;
2495 return len;
2496}
2497
bd9db02f 2498static const struct file_operations i915_display_crc_ctl_fops = {
926321d5 2499 .owner = THIS_MODULE,
bd9db02f 2500 .open = display_crc_ctl_open,
926321d5
DV		 2501 .read = seq_read,
2502 .llseek = seq_lseek,
2503 .release = single_release,
bd9db02f 2504 .write = display_crc_ctl_write
926321d5
DV		 2505};
2506
647416f9
KC		 2507static int
2508i915_wedged_get(void *data, u64 *val)
f3cd474b 2509{
647416f9 2510 struct drm_device *dev = data;
f3cd474b 2511 drm_i915_private_t *dev_priv = dev->dev_private;
f3cd474b 2512
647416f9 2513 *val = atomic_read(&dev_priv->gpu_error.reset_counter);
f3cd474b 2514
647416f9 2515 return 0;
f3cd474b
CW		 2516}
2517
647416f9
KC		 2518static int
2519i915_wedged_set(void *data, u64 val)
f3cd474b 2520{
647416f9 2521 struct drm_device *dev = data;
f3cd474b 2522
647416f9 2523 DRM_INFO("Manually setting wedged to %llu\n", val);
527f9e90 2524 i915_handle_error(dev, val);
f3cd474b 2525
647416f9 2526 return 0;
f3cd474b
CW		 2527}
2528
647416f9
KC		 2529DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
2530 i915_wedged_get, i915_wedged_set,
3a3b4f98 2531 "%llu\n");
f3cd474b 2532
647416f9
KC		 2533static int
2534i915_ring_stop_get(void *data, u64 *val)
e5eb3d63 2535{
647416f9 2536 struct drm_device *dev = data;
e5eb3d63 2537 drm_i915_private_t *dev_priv = dev->dev_private;
e5eb3d63 2538
647416f9 2539 *val = dev_priv->gpu_error.stop_rings;
e5eb3d63 2540
647416f9 2541 return 0;
e5eb3d63
DV		 2542}
2543
647416f9
KC		 2544static int
2545i915_ring_stop_set(void *data, u64 val)
e5eb3d63 2546{
647416f9 2547 struct drm_device *dev = data;
e5eb3d63 2548 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 2549 int ret;
e5eb3d63 2550
647416f9 2551 DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val);
e5eb3d63 2552
22bcfc6a
DV		 2553 ret = mutex_lock_interruptible(&dev->struct_mutex);
2554 if (ret)
2555 return ret;
2556
99584db3 2557 dev_priv->gpu_error.stop_rings = val;
e5eb3d63
DV		 2558 mutex_unlock(&dev->struct_mutex);
2559
647416f9 2560 return 0;
e5eb3d63
DV		 2561}
2562
647416f9
KC		 2563DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops,
2564 i915_ring_stop_get, i915_ring_stop_set,
2565 "0x%08llx\n");
d5442303 2566
094f9a54
CW		 2567static int
2568i915_ring_missed_irq_get(void *data, u64 *val)
2569{
2570 struct drm_device *dev = data;
2571 struct drm_i915_private *dev_priv = dev->dev_private;
2572
2573 *val = dev_priv->gpu_error.missed_irq_rings;
2574 return 0;
2575}
2576
2577static int
2578i915_ring_missed_irq_set(void *data, u64 val)
2579{
2580 struct drm_device *dev = data;
2581 struct drm_i915_private *dev_priv = dev->dev_private;
2582 int ret;
2583
2584 /* Lock against concurrent debugfs callers */
2585 ret = mutex_lock_interruptible(&dev->struct_mutex);
2586 if (ret)
2587 return ret;
2588 dev_priv->gpu_error.missed_irq_rings = val;
2589 mutex_unlock(&dev->struct_mutex);
2590
2591 return 0;
2592}
2593
2594DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
2595 i915_ring_missed_irq_get, i915_ring_missed_irq_set,
2596 "0x%08llx\n");
2597
2598static int
2599i915_ring_test_irq_get(void *data, u64 *val)
2600{
2601 struct drm_device *dev = data;
2602 struct drm_i915_private *dev_priv = dev->dev_private;
2603
2604 *val = dev_priv->gpu_error.test_irq_rings;
2605
2606 return 0;
2607}
2608
2609static int
2610i915_ring_test_irq_set(void *data, u64 val)
2611{
2612 struct drm_device *dev = data;
2613 struct drm_i915_private *dev_priv = dev->dev_private;
2614 int ret;
2615
2616 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
2617
2618 /* Lock against concurrent debugfs callers */
2619 ret = mutex_lock_interruptible(&dev->struct_mutex);
2620 if (ret)
2621 return ret;
2622
2623 dev_priv->gpu_error.test_irq_rings = val;
2624 mutex_unlock(&dev->struct_mutex);
2625
2626 return 0;
2627}
2628
2629DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
2630 i915_ring_test_irq_get, i915_ring_test_irq_set,
2631 "0x%08llx\n");
2632
dd624afd
CW		 2633#define DROP_UNBOUND 0x1
2634#define DROP_BOUND 0x2
2635#define DROP_RETIRE 0x4
2636#define DROP_ACTIVE 0x8
2637#define DROP_ALL (DROP_UNBOUND | \
2638 DROP_BOUND | \
2639 DROP_RETIRE | \
2640 DROP_ACTIVE)
647416f9
KC		 2641static int
2642i915_drop_caches_get(void *data, u64 *val)
dd624afd 2643{
647416f9 2644 *val = DROP_ALL;
dd624afd 2645
647416f9 2646 return 0;
dd624afd
CW		 2647}
2648
647416f9
KC		 2649static int
2650i915_drop_caches_set(void *data, u64 val)
dd624afd 2651{
647416f9 2652 struct drm_device *dev = data;
dd624afd
CW		 2653 struct drm_i915_private *dev_priv = dev->dev_private;
2654 struct drm_i915_gem_object *obj, *next;
ca191b13
BW		 2655 struct i915_address_space *vm;
2656 struct i915_vma *vma, *x;
647416f9 2657 int ret;
dd624afd 2658
647416f9 2659 DRM_DEBUG_DRIVER("Dropping caches: 0x%08llx\n", val);
dd624afd
CW		 2660
2661 /* No need to check and wait for gpu resets, only libdrm auto-restarts
2662 * on ioctls on -EAGAIN. */
2663 ret = mutex_lock_interruptible(&dev->struct_mutex);
2664 if (ret)
2665 return ret;
2666
2667 if (val & DROP_ACTIVE) {
2668 ret = i915_gpu_idle(dev);
2669 if (ret)
2670 goto unlock;
2671 }
2672
2673 if (val & (DROP_RETIRE | DROP_ACTIVE))
2674 i915_gem_retire_requests(dev);
2675
2676 if (val & DROP_BOUND) {
ca191b13
BW		 2677 list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
2678 list_for_each_entry_safe(vma, x, &vm->inactive_list,
2679 mm_list) {
2680 if (vma->obj->pin_count)
2681 continue;
2682
2683 ret = i915_vma_unbind(vma);
2684 if (ret)
2685 goto unlock;
2686 }
31a46c9c 2687 }
dd624afd
CW		 2688 }
2689
2690 if (val & DROP_UNBOUND) {
35c20a60
BW		 2691 list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list,
2692 global_list)
dd624afd
CW		 2693 if (obj->pages_pin_count == 0) {
2694 ret = i915_gem_object_put_pages(obj);
2695 if (ret)
2696 goto unlock;
2697 }
2698 }
2699
2700unlock:
2701 mutex_unlock(&dev->struct_mutex);
2702
647416f9 2703 return ret;
dd624afd
CW		 2704}
2705
647416f9
KC		 2706DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
2707 i915_drop_caches_get, i915_drop_caches_set,
2708 "0x%08llx\n");
dd624afd 2709
647416f9
KC		 2710static int
2711i915_max_freq_get(void *data, u64 *val)
358733e9 2712{
647416f9 2713 struct drm_device *dev = data;
358733e9 2714 drm_i915_private_t *dev_priv = dev->dev_private;
647416f9 2715 int ret;
004777cb
DV		 2716
2717 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
2718 return -ENODEV;
2719
5c9669ce
TR		 2720 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
2721
4fc688ce 2722 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 2723 if (ret)
2724 return ret;
358733e9 2725
0a073b84 2726 if (IS_VALLEYVIEW(dev))
2ec3815f 2727 *val = vlv_gpu_freq(dev_priv, dev_priv->rps.max_delay);
0a073b84
JB		 2728 else
2729 *val = dev_priv->rps.max_delay * GT_FREQUENCY_MULTIPLIER;
4fc688ce 2730 mutex_unlock(&dev_priv->rps.hw_lock);
358733e9 2731
647416f9 2732 return 0;
358733e9
JB		 2733}
2734
647416f9
KC		 2735static int
2736i915_max_freq_set(void *data, u64 val)
358733e9 2737{
647416f9 2738 struct drm_device *dev = data;
358733e9 2739 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 2740 int ret;
004777cb
DV		 2741
2742 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
2743 return -ENODEV;
358733e9 2744
5c9669ce
TR		 2745 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
2746
647416f9 2747 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
358733e9 2748
4fc688ce 2749 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 2750 if (ret)
2751 return ret;
2752
358733e9
JB		 2753 /*
2754 * Turbo will still be enabled, but won't go above the set value.
2755 */
0a073b84 2756 if (IS_VALLEYVIEW(dev)) {
2ec3815f 2757 val = vlv_freq_opcode(dev_priv, val);
0a073b84 2758 dev_priv->rps.max_delay = val;
6917c7b9 2759 valleyview_set_rps(dev, val);
0a073b84
JB		 2760 } else {
2761 do_div(val, GT_FREQUENCY_MULTIPLIER);
2762 dev_priv->rps.max_delay = val;
2763 gen6_set_rps(dev, val);
2764 }
2765
4fc688ce 2766 mutex_unlock(&dev_priv->rps.hw_lock);
358733e9 2767
647416f9 2768 return 0;
358733e9
JB		 2769}
2770
647416f9
KC		 2771DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
2772 i915_max_freq_get, i915_max_freq_set,
3a3b4f98 2773 "%llu\n");
358733e9 2774
647416f9
KC		 2775static int
2776i915_min_freq_get(void *data, u64 *val)
1523c310 2777{
647416f9 2778 struct drm_device *dev = data;
1523c310 2779 drm_i915_private_t *dev_priv = dev->dev_private;
647416f9 2780 int ret;
004777cb
DV		 2781
2782 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
2783 return -ENODEV;
2784
5c9669ce
TR		 2785 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
2786
4fc688ce 2787 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 2788 if (ret)
2789 return ret;
1523c310 2790
0a073b84 2791 if (IS_VALLEYVIEW(dev))
2ec3815f 2792 *val = vlv_gpu_freq(dev_priv, dev_priv->rps.min_delay);
0a073b84
JB		 2793 else
2794 *val = dev_priv->rps.min_delay * GT_FREQUENCY_MULTIPLIER;
4fc688ce 2795 mutex_unlock(&dev_priv->rps.hw_lock);
1523c310 2796
647416f9 2797 return 0;
1523c310
JB		 2798}
2799
647416f9
KC		 2800static int
2801i915_min_freq_set(void *data, u64 val)
1523c310 2802{
647416f9 2803 struct drm_device *dev = data;
1523c310 2804 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 2805 int ret;
004777cb
DV		 2806
2807 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
2808 return -ENODEV;
1523c310 2809
5c9669ce
TR		 2810 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
2811
647416f9 2812 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
1523c310 2813
4fc688ce 2814 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 2815 if (ret)
2816 return ret;
2817
1523c310
JB		 2818 /*
2819 * Turbo will still be enabled, but won't go below the set value.
2820 */
0a073b84 2821 if (IS_VALLEYVIEW(dev)) {
2ec3815f 2822 val = vlv_freq_opcode(dev_priv, val);
0a073b84
JB		 2823 dev_priv->rps.min_delay = val;
2824 valleyview_set_rps(dev, val);
2825 } else {
2826 do_div(val, GT_FREQUENCY_MULTIPLIER);
2827 dev_priv->rps.min_delay = val;
2828 gen6_set_rps(dev, val);
2829 }
4fc688ce 2830 mutex_unlock(&dev_priv->rps.hw_lock);
1523c310 2831
647416f9 2832 return 0;
1523c310
JB		 2833}
2834
647416f9
KC		 2835DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
2836 i915_min_freq_get, i915_min_freq_set,
3a3b4f98 2837 "%llu\n");
1523c310 2838
647416f9
KC		 2839static int
2840i915_cache_sharing_get(void *data, u64 *val)
07b7ddd9 2841{
647416f9 2842 struct drm_device *dev = data;
07b7ddd9 2843 drm_i915_private_t *dev_priv = dev->dev_private;
07b7ddd9 2844 u32 snpcr;
647416f9 2845 int ret;
07b7ddd9 2846
004777cb
DV		 2847 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
2848 return -ENODEV;
2849
22bcfc6a
DV		 2850 ret = mutex_lock_interruptible(&dev->struct_mutex);
2851 if (ret)
2852 return ret;
2853
07b7ddd9
JB		 2854 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
2855 mutex_unlock(&dev_priv->dev->struct_mutex);
2856
647416f9 2857 *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
07b7ddd9 2858
647416f9 2859 return 0;
07b7ddd9
JB		 2860}
2861
647416f9
KC		 2862static int
2863i915_cache_sharing_set(void *data, u64 val)
07b7ddd9 2864{
647416f9 2865 struct drm_device *dev = data;
07b7ddd9 2866 struct drm_i915_private *dev_priv = dev->dev_private;
07b7ddd9 2867 u32 snpcr;
07b7ddd9 2868
004777cb
DV		 2869 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
2870 return -ENODEV;
2871
647416f9 2872 if (val > 3)
07b7ddd9
JB		 2873 return -EINVAL;
2874
647416f9 2875 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
07b7ddd9
JB		 2876
2877 /* Update the cache sharing policy here as well */
2878 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
2879 snpcr &= ~GEN6_MBC_SNPCR_MASK;
2880 snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
2881 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
2882
647416f9 2883 return 0;
07b7ddd9
JB		 2884}
2885
647416f9
KC		 2886DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
2887 i915_cache_sharing_get, i915_cache_sharing_set,
2888 "%llu\n");
07b7ddd9 2889
6d794d42
BW		 2890static int i915_forcewake_open(struct inode *inode, struct file *file)
2891{
2892 struct drm_device *dev = inode->i_private;
2893 struct drm_i915_private *dev_priv = dev->dev_private;
6d794d42 2894
075edca4 2895 if (INTEL_INFO(dev)->gen < 6)
6d794d42
BW		 2896 return 0;
2897
6d794d42 2898 gen6_gt_force_wake_get(dev_priv);
6d794d42
BW		 2899
2900 return 0;
2901}
2902
c43b5634 2903static int i915_forcewake_release(struct inode *inode, struct file *file)
6d794d42
BW		 2904{
2905 struct drm_device *dev = inode->i_private;
2906 struct drm_i915_private *dev_priv = dev->dev_private;
2907
075edca4 2908 if (INTEL_INFO(dev)->gen < 6)
6d794d42
BW		 2909 return 0;
2910
6d794d42 2911 gen6_gt_force_wake_put(dev_priv);
6d794d42
BW		 2912
2913 return 0;
2914}
2915
2916static const struct file_operations i915_forcewake_fops = {
2917 .owner = THIS_MODULE,
2918 .open = i915_forcewake_open,
2919 .release = i915_forcewake_release,
2920};
2921
2922static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
2923{
2924 struct drm_device *dev = minor->dev;
2925 struct dentry *ent;
2926
2927 ent = debugfs_create_file("i915_forcewake_user",
8eb57294 2928 S_IRUSR,
6d794d42
BW		 2929 root, dev,
2930 &i915_forcewake_fops);
2931 if (IS_ERR(ent))
2932 return PTR_ERR(ent);
2933
8eb57294 2934 return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
6d794d42
BW		 2935}
2936
6a9c308d
DV		 2937static int i915_debugfs_create(struct dentry *root,
2938 struct drm_minor *minor,
2939 const char *name,
2940 const struct file_operations *fops)
07b7ddd9
JB		 2941{
2942 struct drm_device *dev = minor->dev;
2943 struct dentry *ent;
2944
6a9c308d 2945 ent = debugfs_create_file(name,
07b7ddd9
JB		 2946 S_IRUGO | S_IWUSR,
2947 root, dev,
6a9c308d 2948 fops);
07b7ddd9
JB		 2949 if (IS_ERR(ent))
2950 return PTR_ERR(ent);
2951
6a9c308d 2952 return drm_add_fake_info_node(minor, ent, fops);
07b7ddd9
JB		 2953}
2954
27c202ad 2955static struct drm_info_list i915_debugfs_list[] = {
311bd68e 2956 {"i915_capabilities", i915_capabilities, 0},
73aa808f 2957 {"i915_gem_objects", i915_gem_object_info, 0},
08c18323 2958 {"i915_gem_gtt", i915_gem_gtt_info, 0},
1b50247a 2959 {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
433e12f7 2960 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
433e12f7 2961 {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
6d2b8885 2962 {"i915_gem_stolen", i915_gem_stolen_list_info },
4e5359cd 2963 {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
2017263e
BG		 2964 {"i915_gem_request", i915_gem_request_info, 0},
2965 {"i915_gem_seqno", i915_gem_seqno_info, 0},
a6172a80 2966 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
2017263e 2967 {"i915_gem_interrupt", i915_interrupt_info, 0},
1ec14ad3
CW		 2968 {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
2969 {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
2970 {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
9010ebfd 2971 {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
f97108d1
JB		 2972 {"i915_rstdby_delays", i915_rstdby_delays, 0},
2973 {"i915_cur_delayinfo", i915_cur_delayinfo, 0},
2974 {"i915_delayfreq_table", i915_delayfreq_table, 0},
2975 {"i915_inttoext_table", i915_inttoext_table, 0},
2976 {"i915_drpc_info", i915_drpc_info, 0},
7648fa99 2977 {"i915_emon_status", i915_emon_status, 0},
23b2f8bb 2978 {"i915_ring_freq_table", i915_ring_freq_table, 0},
7648fa99 2979 {"i915_gfxec", i915_gfxec, 0},
b5e50c3f 2980 {"i915_fbc_status", i915_fbc_status, 0},
92d44621 2981 {"i915_ips_status", i915_ips_status, 0},
4a9bef37 2982 {"i915_sr_status", i915_sr_status, 0},
44834a67 2983 {"i915_opregion", i915_opregion, 0},
37811fcc 2984 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
e76d3630 2985 {"i915_context_status", i915_context_status, 0},
6d794d42 2986 {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0},
ea16a3cd 2987 {"i915_swizzle_info", i915_swizzle_info, 0},
3cf17fc5 2988 {"i915_ppgtt_info", i915_ppgtt_info, 0},
57f350b6 2989 {"i915_dpio", i915_dpio_info, 0},
63573eb7 2990 {"i915_llc", i915_llc, 0},
e91fd8c6 2991 {"i915_edp_psr_status", i915_edp_psr_status, 0},
ec013e7f 2992 {"i915_energy_uJ", i915_energy_uJ, 0},
371db66a 2993 {"i915_pc8_status", i915_pc8_status, 0},
2017263e 2994};
27c202ad 2995#define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
2017263e 2996
2b4bd0e0 2997static struct i915_debugfs_files {
34b9674c
DV		 2998 const char *name;
2999 const struct file_operations *fops;
3000} i915_debugfs_files[] = {
3001 {"i915_wedged", &i915_wedged_fops},
3002 {"i915_max_freq", &i915_max_freq_fops},
3003 {"i915_min_freq", &i915_min_freq_fops},
3004 {"i915_cache_sharing", &i915_cache_sharing_fops},
3005 {"i915_ring_stop", &i915_ring_stop_fops},
094f9a54
CW		 3006 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
3007 {"i915_ring_test_irq", &i915_ring_test_irq_fops},
34b9674c
DV		 3008 {"i915_gem_drop_caches", &i915_drop_caches_fops},
3009 {"i915_error_state", &i915_error_state_fops},
3010 {"i915_next_seqno", &i915_next_seqno_fops},
bd9db02f 3011 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
34b9674c
DV		 3012};
3013
07144428
DL		 3014void intel_display_crc_init(struct drm_device *dev)
3015{
3016 struct drm_i915_private *dev_priv = dev->dev_private;
3017 int i;
3018
3019 for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
3020 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[i];
3021
d538bbdf
DL		 3022 pipe_crc->opened = false;
3023 spin_lock_init(&pipe_crc->lock);
07144428
DL		 3024 init_waitqueue_head(&pipe_crc->wq);
3025 }
3026}
3027
27c202ad 3028int i915_debugfs_init(struct drm_minor *minor)
2017263e 3029{
34b9674c 3030 int ret, i;
f3cd474b 3031
6d794d42 3032 ret = i915_forcewake_create(minor->debugfs_root, minor);
358733e9
JB		 3033 if (ret)
3034 return ret;
6a9c308d 3035
07144428
DL		 3036 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
3037 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
3038 if (ret)
3039 return ret;
3040 }
3041
34b9674c
DV		 3042 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
3043 ret = i915_debugfs_create(minor->debugfs_root, minor,
3044 i915_debugfs_files[i].name,
3045 i915_debugfs_files[i].fops);
3046 if (ret)
3047 return ret;
3048 }
40633219 3049
27c202ad
BG		 3050 return drm_debugfs_create_files(i915_debugfs_list,
3051 I915_DEBUGFS_ENTRIES,
2017263e
BG		 3052 minor->debugfs_root, minor);
3053}
3054
27c202ad 3055void i915_debugfs_cleanup(struct drm_minor *minor)
2017263e 3056{
34b9674c
DV		 3057 int i;
3058
27c202ad
BG		 3059 drm_debugfs_remove_files(i915_debugfs_list,
3060 I915_DEBUGFS_ENTRIES, minor);
07144428 3061
6d794d42
BW		 3062 drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
3063 1, minor);
07144428 3064
e309a997 3065 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
07144428
DL		 3066 struct drm_info_list *info_list =
3067 (struct drm_info_list *)&i915_pipe_crc_data[i];
3068
3069 drm_debugfs_remove_files(info_list, 1, minor);
3070 }
3071
34b9674c
DV		 3072 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
3073 struct drm_info_list *info_list =
3074 (struct drm_info_list *) i915_debugfs_files[i].fops;
3075
3076 drm_debugfs_remove_files(info_list, 1, minor);
3077 }
2017263e
BG		 3078}
3079
3080#endif /* CONFIG_DEBUG_FS */
Linux kernel - Deliverables
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