Commit | Line | Data |
---|---|---|
2017263e BG |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Keith Packard <keithp@keithp.com> | |
26 | * | |
27 | */ | |
28 | ||
29 | #include <linux/seq_file.h> | |
f3cd474b | 30 | #include <linux/debugfs.h> |
5a0e3ad6 | 31 | #include <linux/slab.h> |
2d1a8a48 | 32 | #include <linux/export.h> |
2017263e BG |
33 | #include "drmP.h" |
34 | #include "drm.h" | |
4e5359cd | 35 | #include "intel_drv.h" |
e5c65260 | 36 | #include "intel_ringbuffer.h" |
2017263e BG |
37 | #include "i915_drm.h" |
38 | #include "i915_drv.h" | |
39 | ||
40 | #define DRM_I915_RING_DEBUG 1 | |
41 | ||
42 | ||
43 | #if defined(CONFIG_DEBUG_FS) | |
44 | ||
f13d3f73 | 45 | enum { |
69dc4987 | 46 | ACTIVE_LIST, |
f13d3f73 CW |
47 | FLUSHING_LIST, |
48 | INACTIVE_LIST, | |
d21d5975 | 49 | PINNED_LIST, |
f13d3f73 | 50 | }; |
2017263e | 51 | |
70d39fe4 CW |
52 | static const char *yesno(int v) |
53 | { | |
54 | return v ? "yes" : "no"; | |
55 | } | |
56 | ||
57 | static int i915_capabilities(struct seq_file *m, void *data) | |
58 | { | |
59 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
60 | struct drm_device *dev = node->minor->dev; | |
61 | const struct intel_device_info *info = INTEL_INFO(dev); | |
62 | ||
63 | seq_printf(m, "gen: %d\n", info->gen); | |
03d00ac5 | 64 | seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev)); |
70d39fe4 CW |
65 | #define B(x) seq_printf(m, #x ": %s\n", yesno(info->x)) |
66 | B(is_mobile); | |
70d39fe4 CW |
67 | B(is_i85x); |
68 | B(is_i915g); | |
70d39fe4 | 69 | B(is_i945gm); |
70d39fe4 CW |
70 | B(is_g33); |
71 | B(need_gfx_hws); | |
72 | B(is_g4x); | |
73 | B(is_pineview); | |
74 | B(is_broadwater); | |
75 | B(is_crestline); | |
70d39fe4 | 76 | B(has_fbc); |
70d39fe4 CW |
77 | B(has_pipe_cxsr); |
78 | B(has_hotplug); | |
79 | B(cursor_needs_physical); | |
80 | B(has_overlay); | |
81 | B(overlay_needs_physical); | |
a6c45cf0 | 82 | B(supports_tv); |
549f7365 CW |
83 | B(has_bsd_ring); |
84 | B(has_blt_ring); | |
3d29b842 | 85 | B(has_llc); |
70d39fe4 CW |
86 | #undef B |
87 | ||
88 | return 0; | |
89 | } | |
2017263e | 90 | |
05394f39 | 91 | static const char *get_pin_flag(struct drm_i915_gem_object *obj) |
a6172a80 | 92 | { |
05394f39 | 93 | if (obj->user_pin_count > 0) |
a6172a80 | 94 | return "P"; |
05394f39 | 95 | else if (obj->pin_count > 0) |
a6172a80 CW |
96 | return "p"; |
97 | else | |
98 | return " "; | |
99 | } | |
100 | ||
05394f39 | 101 | static const char *get_tiling_flag(struct drm_i915_gem_object *obj) |
a6172a80 | 102 | { |
0206e353 AJ |
103 | switch (obj->tiling_mode) { |
104 | default: | |
105 | case I915_TILING_NONE: return " "; | |
106 | case I915_TILING_X: return "X"; | |
107 | case I915_TILING_Y: return "Y"; | |
108 | } | |
a6172a80 CW |
109 | } |
110 | ||
93dfb40c | 111 | static const char *cache_level_str(int type) |
08c18323 CW |
112 | { |
113 | switch (type) { | |
93dfb40c CW |
114 | case I915_CACHE_NONE: return " uncached"; |
115 | case I915_CACHE_LLC: return " snooped (LLC)"; | |
116 | case I915_CACHE_LLC_MLC: return " snooped (LLC+MLC)"; | |
08c18323 CW |
117 | default: return ""; |
118 | } | |
119 | } | |
120 | ||
37811fcc CW |
121 | static void |
122 | describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj) | |
123 | { | |
a05a5862 | 124 | seq_printf(m, "%p: %s%s %8zdKiB %04x %04x %d %d%s%s%s", |
37811fcc CW |
125 | &obj->base, |
126 | get_pin_flag(obj), | |
127 | get_tiling_flag(obj), | |
a05a5862 | 128 | obj->base.size / 1024, |
37811fcc CW |
129 | obj->base.read_domains, |
130 | obj->base.write_domain, | |
131 | obj->last_rendering_seqno, | |
caea7476 | 132 | obj->last_fenced_seqno, |
93dfb40c | 133 | cache_level_str(obj->cache_level), |
37811fcc CW |
134 | obj->dirty ? " dirty" : "", |
135 | obj->madv == I915_MADV_DONTNEED ? " purgeable" : ""); | |
136 | if (obj->base.name) | |
137 | seq_printf(m, " (name: %d)", obj->base.name); | |
138 | if (obj->fence_reg != I915_FENCE_REG_NONE) | |
139 | seq_printf(m, " (fence: %d)", obj->fence_reg); | |
140 | if (obj->gtt_space != NULL) | |
a00b10c3 CW |
141 | seq_printf(m, " (gtt offset: %08x, size: %08x)", |
142 | obj->gtt_offset, (unsigned int)obj->gtt_space->size); | |
6299f992 CW |
143 | if (obj->pin_mappable || obj->fault_mappable) { |
144 | char s[3], *t = s; | |
145 | if (obj->pin_mappable) | |
146 | *t++ = 'p'; | |
147 | if (obj->fault_mappable) | |
148 | *t++ = 'f'; | |
149 | *t = '\0'; | |
150 | seq_printf(m, " (%s mappable)", s); | |
151 | } | |
69dc4987 CW |
152 | if (obj->ring != NULL) |
153 | seq_printf(m, " (%s)", obj->ring->name); | |
37811fcc CW |
154 | } |
155 | ||
433e12f7 | 156 | static int i915_gem_object_list_info(struct seq_file *m, void *data) |
2017263e BG |
157 | { |
158 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
433e12f7 BG |
159 | uintptr_t list = (uintptr_t) node->info_ent->data; |
160 | struct list_head *head; | |
2017263e BG |
161 | struct drm_device *dev = node->minor->dev; |
162 | drm_i915_private_t *dev_priv = dev->dev_private; | |
05394f39 | 163 | struct drm_i915_gem_object *obj; |
8f2480fb CW |
164 | size_t total_obj_size, total_gtt_size; |
165 | int count, ret; | |
de227ef0 CW |
166 | |
167 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
168 | if (ret) | |
169 | return ret; | |
2017263e | 170 | |
433e12f7 BG |
171 | switch (list) { |
172 | case ACTIVE_LIST: | |
173 | seq_printf(m, "Active:\n"); | |
69dc4987 | 174 | head = &dev_priv->mm.active_list; |
433e12f7 BG |
175 | break; |
176 | case INACTIVE_LIST: | |
a17458fc | 177 | seq_printf(m, "Inactive:\n"); |
433e12f7 BG |
178 | head = &dev_priv->mm.inactive_list; |
179 | break; | |
180 | case FLUSHING_LIST: | |
181 | seq_printf(m, "Flushing:\n"); | |
182 | head = &dev_priv->mm.flushing_list; | |
183 | break; | |
184 | default: | |
de227ef0 CW |
185 | mutex_unlock(&dev->struct_mutex); |
186 | return -EINVAL; | |
2017263e | 187 | } |
2017263e | 188 | |
8f2480fb | 189 | total_obj_size = total_gtt_size = count = 0; |
05394f39 | 190 | list_for_each_entry(obj, head, mm_list) { |
37811fcc | 191 | seq_printf(m, " "); |
05394f39 | 192 | describe_obj(m, obj); |
f4ceda89 | 193 | seq_printf(m, "\n"); |
05394f39 CW |
194 | total_obj_size += obj->base.size; |
195 | total_gtt_size += obj->gtt_space->size; | |
8f2480fb | 196 | count++; |
2017263e | 197 | } |
de227ef0 | 198 | mutex_unlock(&dev->struct_mutex); |
5e118f41 | 199 | |
8f2480fb CW |
200 | seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n", |
201 | count, total_obj_size, total_gtt_size); | |
2017263e BG |
202 | return 0; |
203 | } | |
204 | ||
6299f992 CW |
205 | #define count_objects(list, member) do { \ |
206 | list_for_each_entry(obj, list, member) { \ | |
207 | size += obj->gtt_space->size; \ | |
208 | ++count; \ | |
209 | if (obj->map_and_fenceable) { \ | |
210 | mappable_size += obj->gtt_space->size; \ | |
211 | ++mappable_count; \ | |
212 | } \ | |
213 | } \ | |
0206e353 | 214 | } while (0) |
6299f992 | 215 | |
73aa808f CW |
216 | static int i915_gem_object_info(struct seq_file *m, void* data) |
217 | { | |
218 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
219 | struct drm_device *dev = node->minor->dev; | |
220 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6299f992 CW |
221 | u32 count, mappable_count; |
222 | size_t size, mappable_size; | |
223 | struct drm_i915_gem_object *obj; | |
73aa808f CW |
224 | int ret; |
225 | ||
226 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
227 | if (ret) | |
228 | return ret; | |
229 | ||
6299f992 CW |
230 | seq_printf(m, "%u objects, %zu bytes\n", |
231 | dev_priv->mm.object_count, | |
232 | dev_priv->mm.object_memory); | |
233 | ||
234 | size = count = mappable_size = mappable_count = 0; | |
235 | count_objects(&dev_priv->mm.gtt_list, gtt_list); | |
236 | seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n", | |
237 | count, mappable_count, size, mappable_size); | |
238 | ||
239 | size = count = mappable_size = mappable_count = 0; | |
240 | count_objects(&dev_priv->mm.active_list, mm_list); | |
241 | count_objects(&dev_priv->mm.flushing_list, mm_list); | |
242 | seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n", | |
243 | count, mappable_count, size, mappable_size); | |
244 | ||
6299f992 CW |
245 | size = count = mappable_size = mappable_count = 0; |
246 | count_objects(&dev_priv->mm.inactive_list, mm_list); | |
247 | seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n", | |
248 | count, mappable_count, size, mappable_size); | |
249 | ||
6299f992 CW |
250 | size = count = mappable_size = mappable_count = 0; |
251 | list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) { | |
252 | if (obj->fault_mappable) { | |
253 | size += obj->gtt_space->size; | |
254 | ++count; | |
255 | } | |
256 | if (obj->pin_mappable) { | |
257 | mappable_size += obj->gtt_space->size; | |
258 | ++mappable_count; | |
259 | } | |
260 | } | |
261 | seq_printf(m, "%u pinned mappable objects, %zu bytes\n", | |
262 | mappable_count, mappable_size); | |
263 | seq_printf(m, "%u fault mappable objects, %zu bytes\n", | |
264 | count, size); | |
265 | ||
266 | seq_printf(m, "%zu [%zu] gtt total\n", | |
267 | dev_priv->mm.gtt_total, dev_priv->mm.mappable_gtt_total); | |
73aa808f CW |
268 | |
269 | mutex_unlock(&dev->struct_mutex); | |
270 | ||
271 | return 0; | |
272 | } | |
273 | ||
08c18323 CW |
274 | static int i915_gem_gtt_info(struct seq_file *m, void* data) |
275 | { | |
276 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
277 | struct drm_device *dev = node->minor->dev; | |
1b50247a | 278 | uintptr_t list = (uintptr_t) node->info_ent->data; |
08c18323 CW |
279 | struct drm_i915_private *dev_priv = dev->dev_private; |
280 | struct drm_i915_gem_object *obj; | |
281 | size_t total_obj_size, total_gtt_size; | |
282 | int count, ret; | |
283 | ||
284 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
285 | if (ret) | |
286 | return ret; | |
287 | ||
288 | total_obj_size = total_gtt_size = count = 0; | |
289 | list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) { | |
1b50247a CW |
290 | if (list == PINNED_LIST && obj->pin_count == 0) |
291 | continue; | |
292 | ||
08c18323 CW |
293 | seq_printf(m, " "); |
294 | describe_obj(m, obj); | |
295 | seq_printf(m, "\n"); | |
296 | total_obj_size += obj->base.size; | |
297 | total_gtt_size += obj->gtt_space->size; | |
298 | count++; | |
299 | } | |
300 | ||
301 | mutex_unlock(&dev->struct_mutex); | |
302 | ||
303 | seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n", | |
304 | count, total_obj_size, total_gtt_size); | |
305 | ||
306 | return 0; | |
307 | } | |
308 | ||
4e5359cd SF |
309 | static int i915_gem_pageflip_info(struct seq_file *m, void *data) |
310 | { | |
311 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
312 | struct drm_device *dev = node->minor->dev; | |
313 | unsigned long flags; | |
314 | struct intel_crtc *crtc; | |
315 | ||
316 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { | |
9db4a9c7 JB |
317 | const char pipe = pipe_name(crtc->pipe); |
318 | const char plane = plane_name(crtc->plane); | |
4e5359cd SF |
319 | struct intel_unpin_work *work; |
320 | ||
321 | spin_lock_irqsave(&dev->event_lock, flags); | |
322 | work = crtc->unpin_work; | |
323 | if (work == NULL) { | |
9db4a9c7 | 324 | seq_printf(m, "No flip due on pipe %c (plane %c)\n", |
4e5359cd SF |
325 | pipe, plane); |
326 | } else { | |
327 | if (!work->pending) { | |
9db4a9c7 | 328 | seq_printf(m, "Flip queued on pipe %c (plane %c)\n", |
4e5359cd SF |
329 | pipe, plane); |
330 | } else { | |
9db4a9c7 | 331 | seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n", |
4e5359cd SF |
332 | pipe, plane); |
333 | } | |
334 | if (work->enable_stall_check) | |
335 | seq_printf(m, "Stall check enabled, "); | |
336 | else | |
337 | seq_printf(m, "Stall check waiting for page flip ioctl, "); | |
338 | seq_printf(m, "%d prepares\n", work->pending); | |
339 | ||
340 | if (work->old_fb_obj) { | |
05394f39 CW |
341 | struct drm_i915_gem_object *obj = work->old_fb_obj; |
342 | if (obj) | |
343 | seq_printf(m, "Old framebuffer gtt_offset 0x%08x\n", obj->gtt_offset); | |
4e5359cd SF |
344 | } |
345 | if (work->pending_flip_obj) { | |
05394f39 CW |
346 | struct drm_i915_gem_object *obj = work->pending_flip_obj; |
347 | if (obj) | |
348 | seq_printf(m, "New framebuffer gtt_offset 0x%08x\n", obj->gtt_offset); | |
4e5359cd SF |
349 | } |
350 | } | |
351 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
352 | } | |
353 | ||
354 | return 0; | |
355 | } | |
356 | ||
2017263e BG |
357 | static int i915_gem_request_info(struct seq_file *m, void *data) |
358 | { | |
359 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
360 | struct drm_device *dev = node->minor->dev; | |
361 | drm_i915_private_t *dev_priv = dev->dev_private; | |
362 | struct drm_i915_gem_request *gem_request; | |
c2c347a9 | 363 | int ret, count; |
de227ef0 CW |
364 | |
365 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
366 | if (ret) | |
367 | return ret; | |
2017263e | 368 | |
c2c347a9 | 369 | count = 0; |
1ec14ad3 | 370 | if (!list_empty(&dev_priv->ring[RCS].request_list)) { |
c2c347a9 CW |
371 | seq_printf(m, "Render requests:\n"); |
372 | list_for_each_entry(gem_request, | |
1ec14ad3 | 373 | &dev_priv->ring[RCS].request_list, |
c2c347a9 CW |
374 | list) { |
375 | seq_printf(m, " %d @ %d\n", | |
376 | gem_request->seqno, | |
377 | (int) (jiffies - gem_request->emitted_jiffies)); | |
378 | } | |
379 | count++; | |
380 | } | |
1ec14ad3 | 381 | if (!list_empty(&dev_priv->ring[VCS].request_list)) { |
c2c347a9 CW |
382 | seq_printf(m, "BSD requests:\n"); |
383 | list_for_each_entry(gem_request, | |
1ec14ad3 | 384 | &dev_priv->ring[VCS].request_list, |
c2c347a9 CW |
385 | list) { |
386 | seq_printf(m, " %d @ %d\n", | |
387 | gem_request->seqno, | |
388 | (int) (jiffies - gem_request->emitted_jiffies)); | |
389 | } | |
390 | count++; | |
391 | } | |
1ec14ad3 | 392 | if (!list_empty(&dev_priv->ring[BCS].request_list)) { |
c2c347a9 CW |
393 | seq_printf(m, "BLT requests:\n"); |
394 | list_for_each_entry(gem_request, | |
1ec14ad3 | 395 | &dev_priv->ring[BCS].request_list, |
c2c347a9 CW |
396 | list) { |
397 | seq_printf(m, " %d @ %d\n", | |
398 | gem_request->seqno, | |
399 | (int) (jiffies - gem_request->emitted_jiffies)); | |
400 | } | |
401 | count++; | |
2017263e | 402 | } |
de227ef0 CW |
403 | mutex_unlock(&dev->struct_mutex); |
404 | ||
c2c347a9 CW |
405 | if (count == 0) |
406 | seq_printf(m, "No requests\n"); | |
407 | ||
2017263e BG |
408 | return 0; |
409 | } | |
410 | ||
b2223497 CW |
411 | static void i915_ring_seqno_info(struct seq_file *m, |
412 | struct intel_ring_buffer *ring) | |
413 | { | |
414 | if (ring->get_seqno) { | |
415 | seq_printf(m, "Current sequence (%s): %d\n", | |
416 | ring->name, ring->get_seqno(ring)); | |
b2223497 CW |
417 | } |
418 | } | |
419 | ||
2017263e BG |
420 | static int i915_gem_seqno_info(struct seq_file *m, void *data) |
421 | { | |
422 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
423 | struct drm_device *dev = node->minor->dev; | |
424 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1ec14ad3 | 425 | int ret, i; |
de227ef0 CW |
426 | |
427 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
428 | if (ret) | |
429 | return ret; | |
2017263e | 430 | |
1ec14ad3 CW |
431 | for (i = 0; i < I915_NUM_RINGS; i++) |
432 | i915_ring_seqno_info(m, &dev_priv->ring[i]); | |
de227ef0 CW |
433 | |
434 | mutex_unlock(&dev->struct_mutex); | |
435 | ||
2017263e BG |
436 | return 0; |
437 | } | |
438 | ||
439 | ||
440 | static int i915_interrupt_info(struct seq_file *m, void *data) | |
441 | { | |
442 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
443 | struct drm_device *dev = node->minor->dev; | |
444 | drm_i915_private_t *dev_priv = dev->dev_private; | |
9db4a9c7 | 445 | int ret, i, pipe; |
de227ef0 CW |
446 | |
447 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
448 | if (ret) | |
449 | return ret; | |
2017263e | 450 | |
7e231dbe JB |
451 | if (IS_VALLEYVIEW(dev)) { |
452 | seq_printf(m, "Display IER:\t%08x\n", | |
453 | I915_READ(VLV_IER)); | |
454 | seq_printf(m, "Display IIR:\t%08x\n", | |
455 | I915_READ(VLV_IIR)); | |
456 | seq_printf(m, "Display IIR_RW:\t%08x\n", | |
457 | I915_READ(VLV_IIR_RW)); | |
458 | seq_printf(m, "Display IMR:\t%08x\n", | |
459 | I915_READ(VLV_IMR)); | |
460 | for_each_pipe(pipe) | |
461 | seq_printf(m, "Pipe %c stat:\t%08x\n", | |
462 | pipe_name(pipe), | |
463 | I915_READ(PIPESTAT(pipe))); | |
464 | ||
465 | seq_printf(m, "Master IER:\t%08x\n", | |
466 | I915_READ(VLV_MASTER_IER)); | |
467 | ||
468 | seq_printf(m, "Render IER:\t%08x\n", | |
469 | I915_READ(GTIER)); | |
470 | seq_printf(m, "Render IIR:\t%08x\n", | |
471 | I915_READ(GTIIR)); | |
472 | seq_printf(m, "Render IMR:\t%08x\n", | |
473 | I915_READ(GTIMR)); | |
474 | ||
475 | seq_printf(m, "PM IER:\t\t%08x\n", | |
476 | I915_READ(GEN6_PMIER)); | |
477 | seq_printf(m, "PM IIR:\t\t%08x\n", | |
478 | I915_READ(GEN6_PMIIR)); | |
479 | seq_printf(m, "PM IMR:\t\t%08x\n", | |
480 | I915_READ(GEN6_PMIMR)); | |
481 | ||
482 | seq_printf(m, "Port hotplug:\t%08x\n", | |
483 | I915_READ(PORT_HOTPLUG_EN)); | |
484 | seq_printf(m, "DPFLIPSTAT:\t%08x\n", | |
485 | I915_READ(VLV_DPFLIPSTAT)); | |
486 | seq_printf(m, "DPINVGTT:\t%08x\n", | |
487 | I915_READ(DPINVGTT)); | |
488 | ||
489 | } else if (!HAS_PCH_SPLIT(dev)) { | |
5f6a1695 ZW |
490 | seq_printf(m, "Interrupt enable: %08x\n", |
491 | I915_READ(IER)); | |
492 | seq_printf(m, "Interrupt identity: %08x\n", | |
493 | I915_READ(IIR)); | |
494 | seq_printf(m, "Interrupt mask: %08x\n", | |
495 | I915_READ(IMR)); | |
9db4a9c7 JB |
496 | for_each_pipe(pipe) |
497 | seq_printf(m, "Pipe %c stat: %08x\n", | |
498 | pipe_name(pipe), | |
499 | I915_READ(PIPESTAT(pipe))); | |
5f6a1695 ZW |
500 | } else { |
501 | seq_printf(m, "North Display Interrupt enable: %08x\n", | |
502 | I915_READ(DEIER)); | |
503 | seq_printf(m, "North Display Interrupt identity: %08x\n", | |
504 | I915_READ(DEIIR)); | |
505 | seq_printf(m, "North Display Interrupt mask: %08x\n", | |
506 | I915_READ(DEIMR)); | |
507 | seq_printf(m, "South Display Interrupt enable: %08x\n", | |
508 | I915_READ(SDEIER)); | |
509 | seq_printf(m, "South Display Interrupt identity: %08x\n", | |
510 | I915_READ(SDEIIR)); | |
511 | seq_printf(m, "South Display Interrupt mask: %08x\n", | |
512 | I915_READ(SDEIMR)); | |
513 | seq_printf(m, "Graphics Interrupt enable: %08x\n", | |
514 | I915_READ(GTIER)); | |
515 | seq_printf(m, "Graphics Interrupt identity: %08x\n", | |
516 | I915_READ(GTIIR)); | |
517 | seq_printf(m, "Graphics Interrupt mask: %08x\n", | |
518 | I915_READ(GTIMR)); | |
519 | } | |
2017263e BG |
520 | seq_printf(m, "Interrupts received: %d\n", |
521 | atomic_read(&dev_priv->irq_received)); | |
9862e600 | 522 | for (i = 0; i < I915_NUM_RINGS; i++) { |
da64c6fc | 523 | if (IS_GEN6(dev) || IS_GEN7(dev)) { |
9862e600 CW |
524 | seq_printf(m, "Graphics Interrupt mask (%s): %08x\n", |
525 | dev_priv->ring[i].name, | |
526 | I915_READ_IMR(&dev_priv->ring[i])); | |
527 | } | |
1ec14ad3 | 528 | i915_ring_seqno_info(m, &dev_priv->ring[i]); |
9862e600 | 529 | } |
de227ef0 CW |
530 | mutex_unlock(&dev->struct_mutex); |
531 | ||
2017263e BG |
532 | return 0; |
533 | } | |
534 | ||
a6172a80 CW |
535 | static int i915_gem_fence_regs_info(struct seq_file *m, void *data) |
536 | { | |
537 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
538 | struct drm_device *dev = node->minor->dev; | |
539 | drm_i915_private_t *dev_priv = dev->dev_private; | |
de227ef0 CW |
540 | int i, ret; |
541 | ||
542 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
543 | if (ret) | |
544 | return ret; | |
a6172a80 CW |
545 | |
546 | seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start); | |
547 | seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs); | |
548 | for (i = 0; i < dev_priv->num_fence_regs; i++) { | |
05394f39 | 549 | struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj; |
a6172a80 | 550 | |
c2c347a9 CW |
551 | seq_printf(m, "Fenced object[%2d] = ", i); |
552 | if (obj == NULL) | |
553 | seq_printf(m, "unused"); | |
554 | else | |
05394f39 | 555 | describe_obj(m, obj); |
c2c347a9 | 556 | seq_printf(m, "\n"); |
a6172a80 CW |
557 | } |
558 | ||
05394f39 | 559 | mutex_unlock(&dev->struct_mutex); |
a6172a80 CW |
560 | return 0; |
561 | } | |
562 | ||
2017263e BG |
563 | static int i915_hws_info(struct seq_file *m, void *data) |
564 | { | |
565 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
566 | struct drm_device *dev = node->minor->dev; | |
567 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4066c0ae | 568 | struct intel_ring_buffer *ring; |
311bd68e | 569 | const volatile u32 __iomem *hws; |
4066c0ae CW |
570 | int i; |
571 | ||
1ec14ad3 | 572 | ring = &dev_priv->ring[(uintptr_t)node->info_ent->data]; |
311bd68e | 573 | hws = (volatile u32 __iomem *)ring->status_page.page_addr; |
2017263e BG |
574 | if (hws == NULL) |
575 | return 0; | |
576 | ||
577 | for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) { | |
578 | seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n", | |
579 | i * 4, | |
580 | hws[i], hws[i + 1], hws[i + 2], hws[i + 3]); | |
581 | } | |
582 | return 0; | |
583 | } | |
584 | ||
e5c65260 CW |
585 | static const char *ring_str(int ring) |
586 | { | |
587 | switch (ring) { | |
96154f2f DV |
588 | case RCS: return "render"; |
589 | case VCS: return "bsd"; | |
590 | case BCS: return "blt"; | |
e5c65260 CW |
591 | default: return ""; |
592 | } | |
593 | } | |
594 | ||
9df30794 CW |
595 | static const char *pin_flag(int pinned) |
596 | { | |
597 | if (pinned > 0) | |
598 | return " P"; | |
599 | else if (pinned < 0) | |
600 | return " p"; | |
601 | else | |
602 | return ""; | |
603 | } | |
604 | ||
605 | static const char *tiling_flag(int tiling) | |
606 | { | |
607 | switch (tiling) { | |
608 | default: | |
609 | case I915_TILING_NONE: return ""; | |
610 | case I915_TILING_X: return " X"; | |
611 | case I915_TILING_Y: return " Y"; | |
612 | } | |
613 | } | |
614 | ||
615 | static const char *dirty_flag(int dirty) | |
616 | { | |
617 | return dirty ? " dirty" : ""; | |
618 | } | |
619 | ||
620 | static const char *purgeable_flag(int purgeable) | |
621 | { | |
622 | return purgeable ? " purgeable" : ""; | |
623 | } | |
624 | ||
c724e8a9 CW |
625 | static void print_error_buffers(struct seq_file *m, |
626 | const char *name, | |
627 | struct drm_i915_error_buffer *err, | |
628 | int count) | |
629 | { | |
630 | seq_printf(m, "%s [%d]:\n", name, count); | |
631 | ||
632 | while (count--) { | |
96154f2f | 633 | seq_printf(m, " %08x %8u %04x %04x %08x%s%s%s%s%s%s%s", |
c724e8a9 CW |
634 | err->gtt_offset, |
635 | err->size, | |
636 | err->read_domains, | |
637 | err->write_domain, | |
638 | err->seqno, | |
639 | pin_flag(err->pinned), | |
640 | tiling_flag(err->tiling), | |
641 | dirty_flag(err->dirty), | |
642 | purgeable_flag(err->purgeable), | |
96154f2f | 643 | err->ring != -1 ? " " : "", |
a779e5ab | 644 | ring_str(err->ring), |
93dfb40c | 645 | cache_level_str(err->cache_level)); |
c724e8a9 CW |
646 | |
647 | if (err->name) | |
648 | seq_printf(m, " (name: %d)", err->name); | |
649 | if (err->fence_reg != I915_FENCE_REG_NONE) | |
650 | seq_printf(m, " (fence: %d)", err->fence_reg); | |
651 | ||
652 | seq_printf(m, "\n"); | |
653 | err++; | |
654 | } | |
655 | } | |
656 | ||
d27b1e0e DV |
657 | static void i915_ring_error_state(struct seq_file *m, |
658 | struct drm_device *dev, | |
659 | struct drm_i915_error_state *error, | |
660 | unsigned ring) | |
661 | { | |
ec34a01d | 662 | BUG_ON(ring >= I915_NUM_RINGS); /* shut up confused gcc */ |
d27b1e0e | 663 | seq_printf(m, "%s command stream:\n", ring_str(ring)); |
c1cd90ed DV |
664 | seq_printf(m, " HEAD: 0x%08x\n", error->head[ring]); |
665 | seq_printf(m, " TAIL: 0x%08x\n", error->tail[ring]); | |
d27b1e0e DV |
666 | seq_printf(m, " ACTHD: 0x%08x\n", error->acthd[ring]); |
667 | seq_printf(m, " IPEIR: 0x%08x\n", error->ipeir[ring]); | |
668 | seq_printf(m, " IPEHR: 0x%08x\n", error->ipehr[ring]); | |
669 | seq_printf(m, " INSTDONE: 0x%08x\n", error->instdone[ring]); | |
c1cd90ed DV |
670 | if (ring == RCS && INTEL_INFO(dev)->gen >= 4) { |
671 | seq_printf(m, " INSTDONE1: 0x%08x\n", error->instdone1); | |
672 | seq_printf(m, " BBADDR: 0x%08llx\n", error->bbaddr); | |
d27b1e0e | 673 | } |
c1cd90ed DV |
674 | if (INTEL_INFO(dev)->gen >= 4) |
675 | seq_printf(m, " INSTPS: 0x%08x\n", error->instps[ring]); | |
676 | seq_printf(m, " INSTPM: 0x%08x\n", error->instpm[ring]); | |
9d2f41fa | 677 | seq_printf(m, " FADDR: 0x%08x\n", error->faddr[ring]); |
33f3f518 | 678 | if (INTEL_INFO(dev)->gen >= 6) { |
33f3f518 | 679 | seq_printf(m, " FAULT_REG: 0x%08x\n", error->fault_reg[ring]); |
7e3b8737 DV |
680 | seq_printf(m, " SYNC_0: 0x%08x\n", |
681 | error->semaphore_mboxes[ring][0]); | |
682 | seq_printf(m, " SYNC_1: 0x%08x\n", | |
683 | error->semaphore_mboxes[ring][1]); | |
33f3f518 | 684 | } |
d27b1e0e | 685 | seq_printf(m, " seqno: 0x%08x\n", error->seqno[ring]); |
9574b3fe | 686 | seq_printf(m, " waiting: %s\n", yesno(error->waiting[ring])); |
7e3b8737 DV |
687 | seq_printf(m, " ring->head: 0x%08x\n", error->cpu_ring_head[ring]); |
688 | seq_printf(m, " ring->tail: 0x%08x\n", error->cpu_ring_tail[ring]); | |
d27b1e0e DV |
689 | } |
690 | ||
d5442303 DV |
691 | struct i915_error_state_file_priv { |
692 | struct drm_device *dev; | |
693 | struct drm_i915_error_state *error; | |
694 | }; | |
695 | ||
63eeaf38 JB |
696 | static int i915_error_state(struct seq_file *m, void *unused) |
697 | { | |
d5442303 DV |
698 | struct i915_error_state_file_priv *error_priv = m->private; |
699 | struct drm_device *dev = error_priv->dev; | |
63eeaf38 | 700 | drm_i915_private_t *dev_priv = dev->dev_private; |
d5442303 | 701 | struct drm_i915_error_state *error = error_priv->error; |
b4519513 | 702 | struct intel_ring_buffer *ring; |
52d39a21 | 703 | int i, j, page, offset, elt; |
63eeaf38 | 704 | |
742cbee8 | 705 | if (!error) { |
63eeaf38 | 706 | seq_printf(m, "no error state collected\n"); |
742cbee8 | 707 | return 0; |
63eeaf38 JB |
708 | } |
709 | ||
8a905236 JB |
710 | seq_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec, |
711 | error->time.tv_usec); | |
9df30794 | 712 | seq_printf(m, "PCI ID: 0x%04x\n", dev->pci_device); |
1d8f38f4 | 713 | seq_printf(m, "EIR: 0x%08x\n", error->eir); |
be998e2e | 714 | seq_printf(m, "IER: 0x%08x\n", error->ier); |
1d8f38f4 | 715 | seq_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er); |
9df30794 | 716 | |
bf3301ab | 717 | for (i = 0; i < dev_priv->num_fence_regs; i++) |
748ebc60 CW |
718 | seq_printf(m, " fence[%d] = %08llx\n", i, error->fence[i]); |
719 | ||
33f3f518 | 720 | if (INTEL_INFO(dev)->gen >= 6) { |
d27b1e0e | 721 | seq_printf(m, "ERROR: 0x%08x\n", error->error); |
33f3f518 DV |
722 | seq_printf(m, "DONE_REG: 0x%08x\n", error->done_reg); |
723 | } | |
d27b1e0e | 724 | |
b4519513 CW |
725 | for_each_ring(ring, dev_priv, i) |
726 | i915_ring_error_state(m, dev, error, i); | |
d27b1e0e | 727 | |
c724e8a9 CW |
728 | if (error->active_bo) |
729 | print_error_buffers(m, "Active", | |
730 | error->active_bo, | |
731 | error->active_bo_count); | |
732 | ||
733 | if (error->pinned_bo) | |
734 | print_error_buffers(m, "Pinned", | |
735 | error->pinned_bo, | |
736 | error->pinned_bo_count); | |
9df30794 | 737 | |
52d39a21 CW |
738 | for (i = 0; i < ARRAY_SIZE(error->ring); i++) { |
739 | struct drm_i915_error_object *obj; | |
9df30794 | 740 | |
52d39a21 | 741 | if ((obj = error->ring[i].batchbuffer)) { |
bcfb2e28 CW |
742 | seq_printf(m, "%s --- gtt_offset = 0x%08x\n", |
743 | dev_priv->ring[i].name, | |
744 | obj->gtt_offset); | |
9df30794 CW |
745 | offset = 0; |
746 | for (page = 0; page < obj->page_count; page++) { | |
747 | for (elt = 0; elt < PAGE_SIZE/4; elt++) { | |
748 | seq_printf(m, "%08x : %08x\n", offset, obj->pages[page][elt]); | |
749 | offset += 4; | |
750 | } | |
751 | } | |
752 | } | |
9df30794 | 753 | |
52d39a21 CW |
754 | if (error->ring[i].num_requests) { |
755 | seq_printf(m, "%s --- %d requests\n", | |
756 | dev_priv->ring[i].name, | |
757 | error->ring[i].num_requests); | |
758 | for (j = 0; j < error->ring[i].num_requests; j++) { | |
ee4f42b1 | 759 | seq_printf(m, " seqno 0x%08x, emitted %ld, tail 0x%08x\n", |
52d39a21 | 760 | error->ring[i].requests[j].seqno, |
ee4f42b1 CW |
761 | error->ring[i].requests[j].jiffies, |
762 | error->ring[i].requests[j].tail); | |
52d39a21 CW |
763 | } |
764 | } | |
765 | ||
766 | if ((obj = error->ring[i].ringbuffer)) { | |
e2f973d5 CW |
767 | seq_printf(m, "%s --- ringbuffer = 0x%08x\n", |
768 | dev_priv->ring[i].name, | |
769 | obj->gtt_offset); | |
770 | offset = 0; | |
771 | for (page = 0; page < obj->page_count; page++) { | |
772 | for (elt = 0; elt < PAGE_SIZE/4; elt++) { | |
773 | seq_printf(m, "%08x : %08x\n", | |
774 | offset, | |
775 | obj->pages[page][elt]); | |
776 | offset += 4; | |
777 | } | |
9df30794 CW |
778 | } |
779 | } | |
780 | } | |
63eeaf38 | 781 | |
6ef3d427 CW |
782 | if (error->overlay) |
783 | intel_overlay_print_error_state(m, error->overlay); | |
784 | ||
c4a1d9e4 CW |
785 | if (error->display) |
786 | intel_display_print_error_state(m, dev, error->display); | |
787 | ||
63eeaf38 JB |
788 | return 0; |
789 | } | |
6911a9b8 | 790 | |
d5442303 DV |
791 | static ssize_t |
792 | i915_error_state_write(struct file *filp, | |
793 | const char __user *ubuf, | |
794 | size_t cnt, | |
795 | loff_t *ppos) | |
796 | { | |
797 | struct seq_file *m = filp->private_data; | |
798 | struct i915_error_state_file_priv *error_priv = m->private; | |
799 | struct drm_device *dev = error_priv->dev; | |
800 | ||
801 | DRM_DEBUG_DRIVER("Resetting error state\n"); | |
802 | ||
803 | mutex_lock(&dev->struct_mutex); | |
804 | i915_destroy_error_state(dev); | |
805 | mutex_unlock(&dev->struct_mutex); | |
806 | ||
807 | return cnt; | |
808 | } | |
809 | ||
810 | static int i915_error_state_open(struct inode *inode, struct file *file) | |
811 | { | |
812 | struct drm_device *dev = inode->i_private; | |
813 | drm_i915_private_t *dev_priv = dev->dev_private; | |
814 | struct i915_error_state_file_priv *error_priv; | |
815 | unsigned long flags; | |
816 | ||
817 | error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL); | |
818 | if (!error_priv) | |
819 | return -ENOMEM; | |
820 | ||
821 | error_priv->dev = dev; | |
822 | ||
823 | spin_lock_irqsave(&dev_priv->error_lock, flags); | |
824 | error_priv->error = dev_priv->first_error; | |
825 | if (error_priv->error) | |
826 | kref_get(&error_priv->error->ref); | |
827 | spin_unlock_irqrestore(&dev_priv->error_lock, flags); | |
828 | ||
829 | return single_open(file, i915_error_state, error_priv); | |
830 | } | |
831 | ||
832 | static int i915_error_state_release(struct inode *inode, struct file *file) | |
833 | { | |
834 | struct seq_file *m = file->private_data; | |
835 | struct i915_error_state_file_priv *error_priv = m->private; | |
836 | ||
837 | if (error_priv->error) | |
838 | kref_put(&error_priv->error->ref, i915_error_state_free); | |
839 | kfree(error_priv); | |
840 | ||
841 | return single_release(inode, file); | |
842 | } | |
843 | ||
844 | static const struct file_operations i915_error_state_fops = { | |
845 | .owner = THIS_MODULE, | |
846 | .open = i915_error_state_open, | |
847 | .read = seq_read, | |
848 | .write = i915_error_state_write, | |
849 | .llseek = default_llseek, | |
850 | .release = i915_error_state_release, | |
851 | }; | |
852 | ||
f97108d1 JB |
853 | static int i915_rstdby_delays(struct seq_file *m, void *unused) |
854 | { | |
855 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
856 | struct drm_device *dev = node->minor->dev; | |
857 | drm_i915_private_t *dev_priv = dev->dev_private; | |
616fdb5a BW |
858 | u16 crstanddelay; |
859 | int ret; | |
860 | ||
861 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
862 | if (ret) | |
863 | return ret; | |
864 | ||
865 | crstanddelay = I915_READ16(CRSTANDVID); | |
866 | ||
867 | mutex_unlock(&dev->struct_mutex); | |
f97108d1 JB |
868 | |
869 | seq_printf(m, "w/ctx: %d, w/o ctx: %d\n", (crstanddelay >> 8) & 0x3f, (crstanddelay & 0x3f)); | |
870 | ||
871 | return 0; | |
872 | } | |
873 | ||
874 | static int i915_cur_delayinfo(struct seq_file *m, void *unused) | |
875 | { | |
876 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
877 | struct drm_device *dev = node->minor->dev; | |
878 | drm_i915_private_t *dev_priv = dev->dev_private; | |
d1ebd816 | 879 | int ret; |
3b8d8d91 JB |
880 | |
881 | if (IS_GEN5(dev)) { | |
882 | u16 rgvswctl = I915_READ16(MEMSWCTL); | |
883 | u16 rgvstat = I915_READ16(MEMSTAT_ILK); | |
884 | ||
885 | seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf); | |
886 | seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f); | |
887 | seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >> | |
888 | MEMSTAT_VID_SHIFT); | |
889 | seq_printf(m, "Current P-state: %d\n", | |
890 | (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT); | |
1c70c0ce | 891 | } else if (IS_GEN6(dev) || IS_GEN7(dev)) { |
3b8d8d91 JB |
892 | u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS); |
893 | u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS); | |
894 | u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); | |
ccab5c82 JB |
895 | u32 rpstat; |
896 | u32 rpupei, rpcurup, rpprevup; | |
897 | u32 rpdownei, rpcurdown, rpprevdown; | |
3b8d8d91 JB |
898 | int max_freq; |
899 | ||
900 | /* RPSTAT1 is in the GT power well */ | |
d1ebd816 BW |
901 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
902 | if (ret) | |
903 | return ret; | |
904 | ||
fcca7926 | 905 | gen6_gt_force_wake_get(dev_priv); |
3b8d8d91 | 906 | |
ccab5c82 JB |
907 | rpstat = I915_READ(GEN6_RPSTAT1); |
908 | rpupei = I915_READ(GEN6_RP_CUR_UP_EI); | |
909 | rpcurup = I915_READ(GEN6_RP_CUR_UP); | |
910 | rpprevup = I915_READ(GEN6_RP_PREV_UP); | |
911 | rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI); | |
912 | rpcurdown = I915_READ(GEN6_RP_CUR_DOWN); | |
913 | rpprevdown = I915_READ(GEN6_RP_PREV_DOWN); | |
914 | ||
d1ebd816 BW |
915 | gen6_gt_force_wake_put(dev_priv); |
916 | mutex_unlock(&dev->struct_mutex); | |
917 | ||
3b8d8d91 | 918 | seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status); |
ccab5c82 | 919 | seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat); |
3b8d8d91 JB |
920 | seq_printf(m, "Render p-state ratio: %d\n", |
921 | (gt_perf_status & 0xff00) >> 8); | |
922 | seq_printf(m, "Render p-state VID: %d\n", | |
923 | gt_perf_status & 0xff); | |
924 | seq_printf(m, "Render p-state limit: %d\n", | |
925 | rp_state_limits & 0xff); | |
ccab5c82 | 926 | seq_printf(m, "CAGF: %dMHz\n", ((rpstat & GEN6_CAGF_MASK) >> |
e281fcaa | 927 | GEN6_CAGF_SHIFT) * 50); |
ccab5c82 JB |
928 | seq_printf(m, "RP CUR UP EI: %dus\n", rpupei & |
929 | GEN6_CURICONT_MASK); | |
930 | seq_printf(m, "RP CUR UP: %dus\n", rpcurup & | |
931 | GEN6_CURBSYTAVG_MASK); | |
932 | seq_printf(m, "RP PREV UP: %dus\n", rpprevup & | |
933 | GEN6_CURBSYTAVG_MASK); | |
934 | seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei & | |
935 | GEN6_CURIAVG_MASK); | |
936 | seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown & | |
937 | GEN6_CURBSYTAVG_MASK); | |
938 | seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown & | |
939 | GEN6_CURBSYTAVG_MASK); | |
3b8d8d91 JB |
940 | |
941 | max_freq = (rp_state_cap & 0xff0000) >> 16; | |
942 | seq_printf(m, "Lowest (RPN) frequency: %dMHz\n", | |
e281fcaa | 943 | max_freq * 50); |
3b8d8d91 JB |
944 | |
945 | max_freq = (rp_state_cap & 0xff00) >> 8; | |
946 | seq_printf(m, "Nominal (RP1) frequency: %dMHz\n", | |
e281fcaa | 947 | max_freq * 50); |
3b8d8d91 JB |
948 | |
949 | max_freq = rp_state_cap & 0xff; | |
950 | seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n", | |
e281fcaa | 951 | max_freq * 50); |
3b8d8d91 JB |
952 | } else { |
953 | seq_printf(m, "no P-state info available\n"); | |
954 | } | |
f97108d1 JB |
955 | |
956 | return 0; | |
957 | } | |
958 | ||
959 | static int i915_delayfreq_table(struct seq_file *m, void *unused) | |
960 | { | |
961 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
962 | struct drm_device *dev = node->minor->dev; | |
963 | drm_i915_private_t *dev_priv = dev->dev_private; | |
964 | u32 delayfreq; | |
616fdb5a BW |
965 | int ret, i; |
966 | ||
967 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
968 | if (ret) | |
969 | return ret; | |
f97108d1 JB |
970 | |
971 | for (i = 0; i < 16; i++) { | |
972 | delayfreq = I915_READ(PXVFREQ_BASE + i * 4); | |
7648fa99 JB |
973 | seq_printf(m, "P%02dVIDFREQ: 0x%08x (VID: %d)\n", i, delayfreq, |
974 | (delayfreq & PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT); | |
f97108d1 JB |
975 | } |
976 | ||
616fdb5a BW |
977 | mutex_unlock(&dev->struct_mutex); |
978 | ||
f97108d1 JB |
979 | return 0; |
980 | } | |
981 | ||
982 | static inline int MAP_TO_MV(int map) | |
983 | { | |
984 | return 1250 - (map * 25); | |
985 | } | |
986 | ||
987 | static int i915_inttoext_table(struct seq_file *m, void *unused) | |
988 | { | |
989 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
990 | struct drm_device *dev = node->minor->dev; | |
991 | drm_i915_private_t *dev_priv = dev->dev_private; | |
992 | u32 inttoext; | |
616fdb5a BW |
993 | int ret, i; |
994 | ||
995 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
996 | if (ret) | |
997 | return ret; | |
f97108d1 JB |
998 | |
999 | for (i = 1; i <= 32; i++) { | |
1000 | inttoext = I915_READ(INTTOEXT_BASE_ILK + i * 4); | |
1001 | seq_printf(m, "INTTOEXT%02d: 0x%08x\n", i, inttoext); | |
1002 | } | |
1003 | ||
616fdb5a BW |
1004 | mutex_unlock(&dev->struct_mutex); |
1005 | ||
f97108d1 JB |
1006 | return 0; |
1007 | } | |
1008 | ||
4d85529d | 1009 | static int ironlake_drpc_info(struct seq_file *m) |
f97108d1 JB |
1010 | { |
1011 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1012 | struct drm_device *dev = node->minor->dev; | |
1013 | drm_i915_private_t *dev_priv = dev->dev_private; | |
616fdb5a BW |
1014 | u32 rgvmodectl, rstdbyctl; |
1015 | u16 crstandvid; | |
1016 | int ret; | |
1017 | ||
1018 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1019 | if (ret) | |
1020 | return ret; | |
1021 | ||
1022 | rgvmodectl = I915_READ(MEMMODECTL); | |
1023 | rstdbyctl = I915_READ(RSTDBYCTL); | |
1024 | crstandvid = I915_READ16(CRSTANDVID); | |
1025 | ||
1026 | mutex_unlock(&dev->struct_mutex); | |
f97108d1 JB |
1027 | |
1028 | seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ? | |
1029 | "yes" : "no"); | |
1030 | seq_printf(m, "Boost freq: %d\n", | |
1031 | (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >> | |
1032 | MEMMODE_BOOST_FREQ_SHIFT); | |
1033 | seq_printf(m, "HW control enabled: %s\n", | |
1034 | rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no"); | |
1035 | seq_printf(m, "SW control enabled: %s\n", | |
1036 | rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no"); | |
1037 | seq_printf(m, "Gated voltage change: %s\n", | |
1038 | rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no"); | |
1039 | seq_printf(m, "Starting frequency: P%d\n", | |
1040 | (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT); | |
7648fa99 | 1041 | seq_printf(m, "Max P-state: P%d\n", |
f97108d1 | 1042 | (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT); |
7648fa99 JB |
1043 | seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK)); |
1044 | seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f)); | |
1045 | seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f)); | |
1046 | seq_printf(m, "Render standby enabled: %s\n", | |
1047 | (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes"); | |
88271da3 JB |
1048 | seq_printf(m, "Current RS state: "); |
1049 | switch (rstdbyctl & RSX_STATUS_MASK) { | |
1050 | case RSX_STATUS_ON: | |
1051 | seq_printf(m, "on\n"); | |
1052 | break; | |
1053 | case RSX_STATUS_RC1: | |
1054 | seq_printf(m, "RC1\n"); | |
1055 | break; | |
1056 | case RSX_STATUS_RC1E: | |
1057 | seq_printf(m, "RC1E\n"); | |
1058 | break; | |
1059 | case RSX_STATUS_RS1: | |
1060 | seq_printf(m, "RS1\n"); | |
1061 | break; | |
1062 | case RSX_STATUS_RS2: | |
1063 | seq_printf(m, "RS2 (RC6)\n"); | |
1064 | break; | |
1065 | case RSX_STATUS_RS3: | |
1066 | seq_printf(m, "RC3 (RC6+)\n"); | |
1067 | break; | |
1068 | default: | |
1069 | seq_printf(m, "unknown\n"); | |
1070 | break; | |
1071 | } | |
f97108d1 JB |
1072 | |
1073 | return 0; | |
1074 | } | |
1075 | ||
4d85529d BW |
1076 | static int gen6_drpc_info(struct seq_file *m) |
1077 | { | |
1078 | ||
1079 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1080 | struct drm_device *dev = node->minor->dev; | |
1081 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1082 | u32 rpmodectl1, gt_core_status, rcctl1; | |
93b525dc | 1083 | unsigned forcewake_count; |
4d85529d BW |
1084 | int count=0, ret; |
1085 | ||
1086 | ||
1087 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1088 | if (ret) | |
1089 | return ret; | |
1090 | ||
93b525dc DV |
1091 | spin_lock_irq(&dev_priv->gt_lock); |
1092 | forcewake_count = dev_priv->forcewake_count; | |
1093 | spin_unlock_irq(&dev_priv->gt_lock); | |
1094 | ||
1095 | if (forcewake_count) { | |
1096 | seq_printf(m, "RC information inaccurate because somebody " | |
1097 | "holds a forcewake reference \n"); | |
4d85529d BW |
1098 | } else { |
1099 | /* NB: we cannot use forcewake, else we read the wrong values */ | |
1100 | while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1)) | |
1101 | udelay(10); | |
1102 | seq_printf(m, "RC information accurate: %s\n", yesno(count < 51)); | |
1103 | } | |
1104 | ||
1105 | gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS); | |
1106 | trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4); | |
1107 | ||
1108 | rpmodectl1 = I915_READ(GEN6_RP_CONTROL); | |
1109 | rcctl1 = I915_READ(GEN6_RC_CONTROL); | |
1110 | mutex_unlock(&dev->struct_mutex); | |
1111 | ||
1112 | seq_printf(m, "Video Turbo Mode: %s\n", | |
1113 | yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO)); | |
1114 | seq_printf(m, "HW control enabled: %s\n", | |
1115 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); | |
1116 | seq_printf(m, "SW control enabled: %s\n", | |
1117 | yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) == | |
1118 | GEN6_RP_MEDIA_SW_MODE)); | |
fff24e21 | 1119 | seq_printf(m, "RC1e Enabled: %s\n", |
4d85529d BW |
1120 | yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE)); |
1121 | seq_printf(m, "RC6 Enabled: %s\n", | |
1122 | yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE)); | |
1123 | seq_printf(m, "Deep RC6 Enabled: %s\n", | |
1124 | yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE)); | |
1125 | seq_printf(m, "Deepest RC6 Enabled: %s\n", | |
1126 | yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE)); | |
1127 | seq_printf(m, "Current RC state: "); | |
1128 | switch (gt_core_status & GEN6_RCn_MASK) { | |
1129 | case GEN6_RC0: | |
1130 | if (gt_core_status & GEN6_CORE_CPD_STATE_MASK) | |
1131 | seq_printf(m, "Core Power Down\n"); | |
1132 | else | |
1133 | seq_printf(m, "on\n"); | |
1134 | break; | |
1135 | case GEN6_RC3: | |
1136 | seq_printf(m, "RC3\n"); | |
1137 | break; | |
1138 | case GEN6_RC6: | |
1139 | seq_printf(m, "RC6\n"); | |
1140 | break; | |
1141 | case GEN6_RC7: | |
1142 | seq_printf(m, "RC7\n"); | |
1143 | break; | |
1144 | default: | |
1145 | seq_printf(m, "Unknown\n"); | |
1146 | break; | |
1147 | } | |
1148 | ||
1149 | seq_printf(m, "Core Power Down: %s\n", | |
1150 | yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK)); | |
cce66a28 BW |
1151 | |
1152 | /* Not exactly sure what this is */ | |
1153 | seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n", | |
1154 | I915_READ(GEN6_GT_GFX_RC6_LOCKED)); | |
1155 | seq_printf(m, "RC6 residency since boot: %u\n", | |
1156 | I915_READ(GEN6_GT_GFX_RC6)); | |
1157 | seq_printf(m, "RC6+ residency since boot: %u\n", | |
1158 | I915_READ(GEN6_GT_GFX_RC6p)); | |
1159 | seq_printf(m, "RC6++ residency since boot: %u\n", | |
1160 | I915_READ(GEN6_GT_GFX_RC6pp)); | |
1161 | ||
4d85529d BW |
1162 | return 0; |
1163 | } | |
1164 | ||
1165 | static int i915_drpc_info(struct seq_file *m, void *unused) | |
1166 | { | |
1167 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1168 | struct drm_device *dev = node->minor->dev; | |
1169 | ||
1170 | if (IS_GEN6(dev) || IS_GEN7(dev)) | |
1171 | return gen6_drpc_info(m); | |
1172 | else | |
1173 | return ironlake_drpc_info(m); | |
1174 | } | |
1175 | ||
b5e50c3f JB |
1176 | static int i915_fbc_status(struct seq_file *m, void *unused) |
1177 | { | |
1178 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1179 | struct drm_device *dev = node->minor->dev; | |
b5e50c3f | 1180 | drm_i915_private_t *dev_priv = dev->dev_private; |
b5e50c3f | 1181 | |
ee5382ae | 1182 | if (!I915_HAS_FBC(dev)) { |
b5e50c3f JB |
1183 | seq_printf(m, "FBC unsupported on this chipset\n"); |
1184 | return 0; | |
1185 | } | |
1186 | ||
ee5382ae | 1187 | if (intel_fbc_enabled(dev)) { |
b5e50c3f JB |
1188 | seq_printf(m, "FBC enabled\n"); |
1189 | } else { | |
1190 | seq_printf(m, "FBC disabled: "); | |
1191 | switch (dev_priv->no_fbc_reason) { | |
bed4a673 CW |
1192 | case FBC_NO_OUTPUT: |
1193 | seq_printf(m, "no outputs"); | |
1194 | break; | |
b5e50c3f JB |
1195 | case FBC_STOLEN_TOO_SMALL: |
1196 | seq_printf(m, "not enough stolen memory"); | |
1197 | break; | |
1198 | case FBC_UNSUPPORTED_MODE: | |
1199 | seq_printf(m, "mode not supported"); | |
1200 | break; | |
1201 | case FBC_MODE_TOO_LARGE: | |
1202 | seq_printf(m, "mode too large"); | |
1203 | break; | |
1204 | case FBC_BAD_PLANE: | |
1205 | seq_printf(m, "FBC unsupported on plane"); | |
1206 | break; | |
1207 | case FBC_NOT_TILED: | |
1208 | seq_printf(m, "scanout buffer not tiled"); | |
1209 | break; | |
9c928d16 JB |
1210 | case FBC_MULTIPLE_PIPES: |
1211 | seq_printf(m, "multiple pipes are enabled"); | |
1212 | break; | |
c1a9f047 JB |
1213 | case FBC_MODULE_PARAM: |
1214 | seq_printf(m, "disabled per module param (default off)"); | |
1215 | break; | |
b5e50c3f JB |
1216 | default: |
1217 | seq_printf(m, "unknown reason"); | |
1218 | } | |
1219 | seq_printf(m, "\n"); | |
1220 | } | |
1221 | return 0; | |
1222 | } | |
1223 | ||
4a9bef37 JB |
1224 | static int i915_sr_status(struct seq_file *m, void *unused) |
1225 | { | |
1226 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1227 | struct drm_device *dev = node->minor->dev; | |
1228 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1229 | bool sr_enabled = false; | |
1230 | ||
1398261a | 1231 | if (HAS_PCH_SPLIT(dev)) |
5ba2aaaa | 1232 | sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN; |
a6c45cf0 | 1233 | else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev)) |
4a9bef37 JB |
1234 | sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN; |
1235 | else if (IS_I915GM(dev)) | |
1236 | sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN; | |
1237 | else if (IS_PINEVIEW(dev)) | |
1238 | sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN; | |
1239 | ||
5ba2aaaa CW |
1240 | seq_printf(m, "self-refresh: %s\n", |
1241 | sr_enabled ? "enabled" : "disabled"); | |
4a9bef37 JB |
1242 | |
1243 | return 0; | |
1244 | } | |
1245 | ||
7648fa99 JB |
1246 | static int i915_emon_status(struct seq_file *m, void *unused) |
1247 | { | |
1248 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1249 | struct drm_device *dev = node->minor->dev; | |
1250 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1251 | unsigned long temp, chipset, gfx; | |
de227ef0 CW |
1252 | int ret; |
1253 | ||
582be6b4 CW |
1254 | if (!IS_GEN5(dev)) |
1255 | return -ENODEV; | |
1256 | ||
de227ef0 CW |
1257 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1258 | if (ret) | |
1259 | return ret; | |
7648fa99 JB |
1260 | |
1261 | temp = i915_mch_val(dev_priv); | |
1262 | chipset = i915_chipset_val(dev_priv); | |
1263 | gfx = i915_gfx_val(dev_priv); | |
de227ef0 | 1264 | mutex_unlock(&dev->struct_mutex); |
7648fa99 JB |
1265 | |
1266 | seq_printf(m, "GMCH temp: %ld\n", temp); | |
1267 | seq_printf(m, "Chipset power: %ld\n", chipset); | |
1268 | seq_printf(m, "GFX power: %ld\n", gfx); | |
1269 | seq_printf(m, "Total power: %ld\n", chipset + gfx); | |
1270 | ||
1271 | return 0; | |
1272 | } | |
1273 | ||
23b2f8bb JB |
1274 | static int i915_ring_freq_table(struct seq_file *m, void *unused) |
1275 | { | |
1276 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1277 | struct drm_device *dev = node->minor->dev; | |
1278 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1279 | int ret; | |
1280 | int gpu_freq, ia_freq; | |
1281 | ||
1c70c0ce | 1282 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) { |
23b2f8bb JB |
1283 | seq_printf(m, "unsupported on this chipset\n"); |
1284 | return 0; | |
1285 | } | |
1286 | ||
1287 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1288 | if (ret) | |
1289 | return ret; | |
1290 | ||
1291 | seq_printf(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\n"); | |
1292 | ||
1293 | for (gpu_freq = dev_priv->min_delay; gpu_freq <= dev_priv->max_delay; | |
1294 | gpu_freq++) { | |
1295 | I915_WRITE(GEN6_PCODE_DATA, gpu_freq); | |
1296 | I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | | |
1297 | GEN6_PCODE_READ_MIN_FREQ_TABLE); | |
1298 | if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & | |
1299 | GEN6_PCODE_READY) == 0, 10)) { | |
1300 | DRM_ERROR("pcode read of freq table timed out\n"); | |
1301 | continue; | |
1302 | } | |
1303 | ia_freq = I915_READ(GEN6_PCODE_DATA); | |
1304 | seq_printf(m, "%d\t\t%d\n", gpu_freq * 50, ia_freq * 100); | |
1305 | } | |
1306 | ||
1307 | mutex_unlock(&dev->struct_mutex); | |
1308 | ||
1309 | return 0; | |
1310 | } | |
1311 | ||
7648fa99 JB |
1312 | static int i915_gfxec(struct seq_file *m, void *unused) |
1313 | { | |
1314 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1315 | struct drm_device *dev = node->minor->dev; | |
1316 | drm_i915_private_t *dev_priv = dev->dev_private; | |
616fdb5a BW |
1317 | int ret; |
1318 | ||
1319 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1320 | if (ret) | |
1321 | return ret; | |
7648fa99 JB |
1322 | |
1323 | seq_printf(m, "GFXEC: %ld\n", (unsigned long)I915_READ(0x112f4)); | |
1324 | ||
616fdb5a BW |
1325 | mutex_unlock(&dev->struct_mutex); |
1326 | ||
7648fa99 JB |
1327 | return 0; |
1328 | } | |
1329 | ||
44834a67 CW |
1330 | static int i915_opregion(struct seq_file *m, void *unused) |
1331 | { | |
1332 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1333 | struct drm_device *dev = node->minor->dev; | |
1334 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1335 | struct intel_opregion *opregion = &dev_priv->opregion; | |
0d38f009 | 1336 | void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL); |
44834a67 CW |
1337 | int ret; |
1338 | ||
0d38f009 DV |
1339 | if (data == NULL) |
1340 | return -ENOMEM; | |
1341 | ||
44834a67 CW |
1342 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1343 | if (ret) | |
0d38f009 | 1344 | goto out; |
44834a67 | 1345 | |
0d38f009 DV |
1346 | if (opregion->header) { |
1347 | memcpy_fromio(data, opregion->header, OPREGION_SIZE); | |
1348 | seq_write(m, data, OPREGION_SIZE); | |
1349 | } | |
44834a67 CW |
1350 | |
1351 | mutex_unlock(&dev->struct_mutex); | |
1352 | ||
0d38f009 DV |
1353 | out: |
1354 | kfree(data); | |
44834a67 CW |
1355 | return 0; |
1356 | } | |
1357 | ||
37811fcc CW |
1358 | static int i915_gem_framebuffer_info(struct seq_file *m, void *data) |
1359 | { | |
1360 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1361 | struct drm_device *dev = node->minor->dev; | |
1362 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1363 | struct intel_fbdev *ifbdev; | |
1364 | struct intel_framebuffer *fb; | |
1365 | int ret; | |
1366 | ||
1367 | ret = mutex_lock_interruptible(&dev->mode_config.mutex); | |
1368 | if (ret) | |
1369 | return ret; | |
1370 | ||
1371 | ifbdev = dev_priv->fbdev; | |
1372 | fb = to_intel_framebuffer(ifbdev->helper.fb); | |
1373 | ||
1374 | seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, obj ", | |
1375 | fb->base.width, | |
1376 | fb->base.height, | |
1377 | fb->base.depth, | |
1378 | fb->base.bits_per_pixel); | |
05394f39 | 1379 | describe_obj(m, fb->obj); |
37811fcc CW |
1380 | seq_printf(m, "\n"); |
1381 | ||
1382 | list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) { | |
1383 | if (&fb->base == ifbdev->helper.fb) | |
1384 | continue; | |
1385 | ||
1386 | seq_printf(m, "user size: %d x %d, depth %d, %d bpp, obj ", | |
1387 | fb->base.width, | |
1388 | fb->base.height, | |
1389 | fb->base.depth, | |
1390 | fb->base.bits_per_pixel); | |
05394f39 | 1391 | describe_obj(m, fb->obj); |
37811fcc CW |
1392 | seq_printf(m, "\n"); |
1393 | } | |
1394 | ||
1395 | mutex_unlock(&dev->mode_config.mutex); | |
1396 | ||
1397 | return 0; | |
1398 | } | |
1399 | ||
e76d3630 BW |
1400 | static int i915_context_status(struct seq_file *m, void *unused) |
1401 | { | |
1402 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1403 | struct drm_device *dev = node->minor->dev; | |
1404 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1405 | int ret; | |
1406 | ||
1407 | ret = mutex_lock_interruptible(&dev->mode_config.mutex); | |
1408 | if (ret) | |
1409 | return ret; | |
1410 | ||
dc501fbc BW |
1411 | if (dev_priv->pwrctx) { |
1412 | seq_printf(m, "power context "); | |
1413 | describe_obj(m, dev_priv->pwrctx); | |
1414 | seq_printf(m, "\n"); | |
1415 | } | |
e76d3630 | 1416 | |
dc501fbc BW |
1417 | if (dev_priv->renderctx) { |
1418 | seq_printf(m, "render context "); | |
1419 | describe_obj(m, dev_priv->renderctx); | |
1420 | seq_printf(m, "\n"); | |
1421 | } | |
e76d3630 BW |
1422 | |
1423 | mutex_unlock(&dev->mode_config.mutex); | |
1424 | ||
1425 | return 0; | |
1426 | } | |
1427 | ||
6d794d42 BW |
1428 | static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data) |
1429 | { | |
1430 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1431 | struct drm_device *dev = node->minor->dev; | |
1432 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9f1f46a4 | 1433 | unsigned forcewake_count; |
6d794d42 | 1434 | |
9f1f46a4 DV |
1435 | spin_lock_irq(&dev_priv->gt_lock); |
1436 | forcewake_count = dev_priv->forcewake_count; | |
1437 | spin_unlock_irq(&dev_priv->gt_lock); | |
6d794d42 | 1438 | |
9f1f46a4 | 1439 | seq_printf(m, "forcewake count = %u\n", forcewake_count); |
6d794d42 BW |
1440 | |
1441 | return 0; | |
1442 | } | |
1443 | ||
ea16a3cd DV |
1444 | static const char *swizzle_string(unsigned swizzle) |
1445 | { | |
1446 | switch(swizzle) { | |
1447 | case I915_BIT_6_SWIZZLE_NONE: | |
1448 | return "none"; | |
1449 | case I915_BIT_6_SWIZZLE_9: | |
1450 | return "bit9"; | |
1451 | case I915_BIT_6_SWIZZLE_9_10: | |
1452 | return "bit9/bit10"; | |
1453 | case I915_BIT_6_SWIZZLE_9_11: | |
1454 | return "bit9/bit11"; | |
1455 | case I915_BIT_6_SWIZZLE_9_10_11: | |
1456 | return "bit9/bit10/bit11"; | |
1457 | case I915_BIT_6_SWIZZLE_9_17: | |
1458 | return "bit9/bit17"; | |
1459 | case I915_BIT_6_SWIZZLE_9_10_17: | |
1460 | return "bit9/bit10/bit17"; | |
1461 | case I915_BIT_6_SWIZZLE_UNKNOWN: | |
1462 | return "unkown"; | |
1463 | } | |
1464 | ||
1465 | return "bug"; | |
1466 | } | |
1467 | ||
1468 | static int i915_swizzle_info(struct seq_file *m, void *data) | |
1469 | { | |
1470 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1471 | struct drm_device *dev = node->minor->dev; | |
1472 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1473 | ||
1474 | mutex_lock(&dev->struct_mutex); | |
1475 | seq_printf(m, "bit6 swizzle for X-tiling = %s\n", | |
1476 | swizzle_string(dev_priv->mm.bit_6_swizzle_x)); | |
1477 | seq_printf(m, "bit6 swizzle for Y-tiling = %s\n", | |
1478 | swizzle_string(dev_priv->mm.bit_6_swizzle_y)); | |
1479 | ||
1480 | if (IS_GEN3(dev) || IS_GEN4(dev)) { | |
1481 | seq_printf(m, "DDC = 0x%08x\n", | |
1482 | I915_READ(DCC)); | |
1483 | seq_printf(m, "C0DRB3 = 0x%04x\n", | |
1484 | I915_READ16(C0DRB3)); | |
1485 | seq_printf(m, "C1DRB3 = 0x%04x\n", | |
1486 | I915_READ16(C1DRB3)); | |
3fa7d235 DV |
1487 | } else if (IS_GEN6(dev) || IS_GEN7(dev)) { |
1488 | seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n", | |
1489 | I915_READ(MAD_DIMM_C0)); | |
1490 | seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n", | |
1491 | I915_READ(MAD_DIMM_C1)); | |
1492 | seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n", | |
1493 | I915_READ(MAD_DIMM_C2)); | |
1494 | seq_printf(m, "TILECTL = 0x%08x\n", | |
1495 | I915_READ(TILECTL)); | |
1496 | seq_printf(m, "ARB_MODE = 0x%08x\n", | |
1497 | I915_READ(ARB_MODE)); | |
1498 | seq_printf(m, "DISP_ARB_CTL = 0x%08x\n", | |
1499 | I915_READ(DISP_ARB_CTL)); | |
ea16a3cd DV |
1500 | } |
1501 | mutex_unlock(&dev->struct_mutex); | |
1502 | ||
1503 | return 0; | |
1504 | } | |
1505 | ||
3cf17fc5 DV |
1506 | static int i915_ppgtt_info(struct seq_file *m, void *data) |
1507 | { | |
1508 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1509 | struct drm_device *dev = node->minor->dev; | |
1510 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1511 | struct intel_ring_buffer *ring; | |
1512 | int i, ret; | |
1513 | ||
1514 | ||
1515 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1516 | if (ret) | |
1517 | return ret; | |
1518 | if (INTEL_INFO(dev)->gen == 6) | |
1519 | seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE)); | |
1520 | ||
1521 | for (i = 0; i < I915_NUM_RINGS; i++) { | |
1522 | ring = &dev_priv->ring[i]; | |
1523 | ||
1524 | seq_printf(m, "%s\n", ring->name); | |
1525 | if (INTEL_INFO(dev)->gen == 7) | |
1526 | seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring))); | |
1527 | seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring))); | |
1528 | seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring))); | |
1529 | seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring))); | |
1530 | } | |
1531 | if (dev_priv->mm.aliasing_ppgtt) { | |
1532 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
1533 | ||
1534 | seq_printf(m, "aliasing PPGTT:\n"); | |
1535 | seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset); | |
1536 | } | |
1537 | seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK)); | |
1538 | mutex_unlock(&dev->struct_mutex); | |
1539 | ||
1540 | return 0; | |
1541 | } | |
1542 | ||
57f350b6 JB |
1543 | static int i915_dpio_info(struct seq_file *m, void *data) |
1544 | { | |
1545 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1546 | struct drm_device *dev = node->minor->dev; | |
1547 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1548 | int ret; | |
1549 | ||
1550 | ||
1551 | if (!IS_VALLEYVIEW(dev)) { | |
1552 | seq_printf(m, "unsupported\n"); | |
1553 | return 0; | |
1554 | } | |
1555 | ||
1556 | ret = mutex_lock_interruptible(&dev->mode_config.mutex); | |
1557 | if (ret) | |
1558 | return ret; | |
1559 | ||
1560 | seq_printf(m, "DPIO_CTL: 0x%08x\n", I915_READ(DPIO_CTL)); | |
1561 | ||
1562 | seq_printf(m, "DPIO_DIV_A: 0x%08x\n", | |
1563 | intel_dpio_read(dev_priv, _DPIO_DIV_A)); | |
1564 | seq_printf(m, "DPIO_DIV_B: 0x%08x\n", | |
1565 | intel_dpio_read(dev_priv, _DPIO_DIV_B)); | |
1566 | ||
1567 | seq_printf(m, "DPIO_REFSFR_A: 0x%08x\n", | |
1568 | intel_dpio_read(dev_priv, _DPIO_REFSFR_A)); | |
1569 | seq_printf(m, "DPIO_REFSFR_B: 0x%08x\n", | |
1570 | intel_dpio_read(dev_priv, _DPIO_REFSFR_B)); | |
1571 | ||
1572 | seq_printf(m, "DPIO_CORE_CLK_A: 0x%08x\n", | |
1573 | intel_dpio_read(dev_priv, _DPIO_CORE_CLK_A)); | |
1574 | seq_printf(m, "DPIO_CORE_CLK_B: 0x%08x\n", | |
1575 | intel_dpio_read(dev_priv, _DPIO_CORE_CLK_B)); | |
1576 | ||
1577 | seq_printf(m, "DPIO_LFP_COEFF_A: 0x%08x\n", | |
1578 | intel_dpio_read(dev_priv, _DPIO_LFP_COEFF_A)); | |
1579 | seq_printf(m, "DPIO_LFP_COEFF_B: 0x%08x\n", | |
1580 | intel_dpio_read(dev_priv, _DPIO_LFP_COEFF_B)); | |
1581 | ||
1582 | seq_printf(m, "DPIO_FASTCLK_DISABLE: 0x%08x\n", | |
1583 | intel_dpio_read(dev_priv, DPIO_FASTCLK_DISABLE)); | |
1584 | ||
1585 | mutex_unlock(&dev->mode_config.mutex); | |
1586 | ||
1587 | return 0; | |
1588 | } | |
1589 | ||
f3cd474b CW |
1590 | static ssize_t |
1591 | i915_wedged_read(struct file *filp, | |
1592 | char __user *ubuf, | |
1593 | size_t max, | |
1594 | loff_t *ppos) | |
1595 | { | |
1596 | struct drm_device *dev = filp->private_data; | |
1597 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1598 | char buf[80]; | |
1599 | int len; | |
1600 | ||
0206e353 | 1601 | len = snprintf(buf, sizeof(buf), |
f3cd474b CW |
1602 | "wedged : %d\n", |
1603 | atomic_read(&dev_priv->mm.wedged)); | |
1604 | ||
0206e353 AJ |
1605 | if (len > sizeof(buf)) |
1606 | len = sizeof(buf); | |
f4433a8d | 1607 | |
f3cd474b CW |
1608 | return simple_read_from_buffer(ubuf, max, ppos, buf, len); |
1609 | } | |
1610 | ||
1611 | static ssize_t | |
1612 | i915_wedged_write(struct file *filp, | |
1613 | const char __user *ubuf, | |
1614 | size_t cnt, | |
1615 | loff_t *ppos) | |
1616 | { | |
1617 | struct drm_device *dev = filp->private_data; | |
f3cd474b CW |
1618 | char buf[20]; |
1619 | int val = 1; | |
1620 | ||
1621 | if (cnt > 0) { | |
0206e353 | 1622 | if (cnt > sizeof(buf) - 1) |
f3cd474b CW |
1623 | return -EINVAL; |
1624 | ||
1625 | if (copy_from_user(buf, ubuf, cnt)) | |
1626 | return -EFAULT; | |
1627 | buf[cnt] = 0; | |
1628 | ||
1629 | val = simple_strtoul(buf, NULL, 0); | |
1630 | } | |
1631 | ||
1632 | DRM_INFO("Manually setting wedged to %d\n", val); | |
527f9e90 | 1633 | i915_handle_error(dev, val); |
f3cd474b CW |
1634 | |
1635 | return cnt; | |
1636 | } | |
1637 | ||
1638 | static const struct file_operations i915_wedged_fops = { | |
1639 | .owner = THIS_MODULE, | |
234e3405 | 1640 | .open = simple_open, |
f3cd474b CW |
1641 | .read = i915_wedged_read, |
1642 | .write = i915_wedged_write, | |
6038f373 | 1643 | .llseek = default_llseek, |
f3cd474b CW |
1644 | }; |
1645 | ||
e5eb3d63 DV |
1646 | static ssize_t |
1647 | i915_ring_stop_read(struct file *filp, | |
1648 | char __user *ubuf, | |
1649 | size_t max, | |
1650 | loff_t *ppos) | |
1651 | { | |
1652 | struct drm_device *dev = filp->private_data; | |
1653 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1654 | char buf[20]; | |
1655 | int len; | |
1656 | ||
1657 | len = snprintf(buf, sizeof(buf), | |
1658 | "0x%08x\n", dev_priv->stop_rings); | |
1659 | ||
1660 | if (len > sizeof(buf)) | |
1661 | len = sizeof(buf); | |
1662 | ||
1663 | return simple_read_from_buffer(ubuf, max, ppos, buf, len); | |
1664 | } | |
1665 | ||
1666 | static ssize_t | |
1667 | i915_ring_stop_write(struct file *filp, | |
1668 | const char __user *ubuf, | |
1669 | size_t cnt, | |
1670 | loff_t *ppos) | |
1671 | { | |
1672 | struct drm_device *dev = filp->private_data; | |
1673 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1674 | char buf[20]; | |
1675 | int val = 0; | |
1676 | ||
1677 | if (cnt > 0) { | |
1678 | if (cnt > sizeof(buf) - 1) | |
1679 | return -EINVAL; | |
1680 | ||
1681 | if (copy_from_user(buf, ubuf, cnt)) | |
1682 | return -EFAULT; | |
1683 | buf[cnt] = 0; | |
1684 | ||
1685 | val = simple_strtoul(buf, NULL, 0); | |
1686 | } | |
1687 | ||
1688 | DRM_DEBUG_DRIVER("Stopping rings 0x%08x\n", val); | |
1689 | ||
1690 | mutex_lock(&dev->struct_mutex); | |
1691 | dev_priv->stop_rings = val; | |
1692 | mutex_unlock(&dev->struct_mutex); | |
1693 | ||
1694 | return cnt; | |
1695 | } | |
1696 | ||
1697 | static const struct file_operations i915_ring_stop_fops = { | |
1698 | .owner = THIS_MODULE, | |
1699 | .open = simple_open, | |
1700 | .read = i915_ring_stop_read, | |
1701 | .write = i915_ring_stop_write, | |
1702 | .llseek = default_llseek, | |
1703 | }; | |
d5442303 | 1704 | |
358733e9 JB |
1705 | static ssize_t |
1706 | i915_max_freq_read(struct file *filp, | |
1707 | char __user *ubuf, | |
1708 | size_t max, | |
1709 | loff_t *ppos) | |
1710 | { | |
1711 | struct drm_device *dev = filp->private_data; | |
1712 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1713 | char buf[80]; | |
1714 | int len; | |
1715 | ||
0206e353 | 1716 | len = snprintf(buf, sizeof(buf), |
358733e9 JB |
1717 | "max freq: %d\n", dev_priv->max_delay * 50); |
1718 | ||
0206e353 AJ |
1719 | if (len > sizeof(buf)) |
1720 | len = sizeof(buf); | |
358733e9 JB |
1721 | |
1722 | return simple_read_from_buffer(ubuf, max, ppos, buf, len); | |
1723 | } | |
1724 | ||
1725 | static ssize_t | |
1726 | i915_max_freq_write(struct file *filp, | |
1727 | const char __user *ubuf, | |
1728 | size_t cnt, | |
1729 | loff_t *ppos) | |
1730 | { | |
1731 | struct drm_device *dev = filp->private_data; | |
1732 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1733 | char buf[20]; | |
1734 | int val = 1; | |
1735 | ||
1736 | if (cnt > 0) { | |
0206e353 | 1737 | if (cnt > sizeof(buf) - 1) |
358733e9 JB |
1738 | return -EINVAL; |
1739 | ||
1740 | if (copy_from_user(buf, ubuf, cnt)) | |
1741 | return -EFAULT; | |
1742 | buf[cnt] = 0; | |
1743 | ||
1744 | val = simple_strtoul(buf, NULL, 0); | |
1745 | } | |
1746 | ||
1747 | DRM_DEBUG_DRIVER("Manually setting max freq to %d\n", val); | |
1748 | ||
1749 | /* | |
1750 | * Turbo will still be enabled, but won't go above the set value. | |
1751 | */ | |
1752 | dev_priv->max_delay = val / 50; | |
1753 | ||
1754 | gen6_set_rps(dev, val / 50); | |
1755 | ||
1756 | return cnt; | |
1757 | } | |
1758 | ||
1759 | static const struct file_operations i915_max_freq_fops = { | |
1760 | .owner = THIS_MODULE, | |
234e3405 | 1761 | .open = simple_open, |
358733e9 JB |
1762 | .read = i915_max_freq_read, |
1763 | .write = i915_max_freq_write, | |
1764 | .llseek = default_llseek, | |
1765 | }; | |
1766 | ||
07b7ddd9 JB |
1767 | static ssize_t |
1768 | i915_cache_sharing_read(struct file *filp, | |
1769 | char __user *ubuf, | |
1770 | size_t max, | |
1771 | loff_t *ppos) | |
1772 | { | |
1773 | struct drm_device *dev = filp->private_data; | |
1774 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1775 | char buf[80]; | |
1776 | u32 snpcr; | |
1777 | int len; | |
1778 | ||
1779 | mutex_lock(&dev_priv->dev->struct_mutex); | |
1780 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); | |
1781 | mutex_unlock(&dev_priv->dev->struct_mutex); | |
1782 | ||
0206e353 | 1783 | len = snprintf(buf, sizeof(buf), |
07b7ddd9 JB |
1784 | "%d\n", (snpcr & GEN6_MBC_SNPCR_MASK) >> |
1785 | GEN6_MBC_SNPCR_SHIFT); | |
1786 | ||
0206e353 AJ |
1787 | if (len > sizeof(buf)) |
1788 | len = sizeof(buf); | |
07b7ddd9 JB |
1789 | |
1790 | return simple_read_from_buffer(ubuf, max, ppos, buf, len); | |
1791 | } | |
1792 | ||
1793 | static ssize_t | |
1794 | i915_cache_sharing_write(struct file *filp, | |
1795 | const char __user *ubuf, | |
1796 | size_t cnt, | |
1797 | loff_t *ppos) | |
1798 | { | |
1799 | struct drm_device *dev = filp->private_data; | |
1800 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1801 | char buf[20]; | |
1802 | u32 snpcr; | |
1803 | int val = 1; | |
1804 | ||
1805 | if (cnt > 0) { | |
0206e353 | 1806 | if (cnt > sizeof(buf) - 1) |
07b7ddd9 JB |
1807 | return -EINVAL; |
1808 | ||
1809 | if (copy_from_user(buf, ubuf, cnt)) | |
1810 | return -EFAULT; | |
1811 | buf[cnt] = 0; | |
1812 | ||
1813 | val = simple_strtoul(buf, NULL, 0); | |
1814 | } | |
1815 | ||
1816 | if (val < 0 || val > 3) | |
1817 | return -EINVAL; | |
1818 | ||
1819 | DRM_DEBUG_DRIVER("Manually setting uncore sharing to %d\n", val); | |
1820 | ||
1821 | /* Update the cache sharing policy here as well */ | |
1822 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); | |
1823 | snpcr &= ~GEN6_MBC_SNPCR_MASK; | |
1824 | snpcr |= (val << GEN6_MBC_SNPCR_SHIFT); | |
1825 | I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); | |
1826 | ||
1827 | return cnt; | |
1828 | } | |
1829 | ||
1830 | static const struct file_operations i915_cache_sharing_fops = { | |
1831 | .owner = THIS_MODULE, | |
234e3405 | 1832 | .open = simple_open, |
07b7ddd9 JB |
1833 | .read = i915_cache_sharing_read, |
1834 | .write = i915_cache_sharing_write, | |
1835 | .llseek = default_llseek, | |
1836 | }; | |
1837 | ||
f3cd474b CW |
1838 | /* As the drm_debugfs_init() routines are called before dev->dev_private is |
1839 | * allocated we need to hook into the minor for release. */ | |
1840 | static int | |
1841 | drm_add_fake_info_node(struct drm_minor *minor, | |
1842 | struct dentry *ent, | |
1843 | const void *key) | |
1844 | { | |
1845 | struct drm_info_node *node; | |
1846 | ||
1847 | node = kmalloc(sizeof(struct drm_info_node), GFP_KERNEL); | |
1848 | if (node == NULL) { | |
1849 | debugfs_remove(ent); | |
1850 | return -ENOMEM; | |
1851 | } | |
1852 | ||
1853 | node->minor = minor; | |
1854 | node->dent = ent; | |
1855 | node->info_ent = (void *) key; | |
b3e067c0 MS |
1856 | |
1857 | mutex_lock(&minor->debugfs_lock); | |
1858 | list_add(&node->list, &minor->debugfs_list); | |
1859 | mutex_unlock(&minor->debugfs_lock); | |
f3cd474b CW |
1860 | |
1861 | return 0; | |
1862 | } | |
1863 | ||
6d794d42 BW |
1864 | static int i915_forcewake_open(struct inode *inode, struct file *file) |
1865 | { | |
1866 | struct drm_device *dev = inode->i_private; | |
1867 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1868 | int ret; | |
1869 | ||
075edca4 | 1870 | if (INTEL_INFO(dev)->gen < 6) |
6d794d42 BW |
1871 | return 0; |
1872 | ||
1873 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1874 | if (ret) | |
1875 | return ret; | |
1876 | gen6_gt_force_wake_get(dev_priv); | |
1877 | mutex_unlock(&dev->struct_mutex); | |
1878 | ||
1879 | return 0; | |
1880 | } | |
1881 | ||
c43b5634 | 1882 | static int i915_forcewake_release(struct inode *inode, struct file *file) |
6d794d42 BW |
1883 | { |
1884 | struct drm_device *dev = inode->i_private; | |
1885 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1886 | ||
075edca4 | 1887 | if (INTEL_INFO(dev)->gen < 6) |
6d794d42 BW |
1888 | return 0; |
1889 | ||
1890 | /* | |
1891 | * It's bad that we can potentially hang userspace if struct_mutex gets | |
1892 | * forever stuck. However, if we cannot acquire this lock it means that | |
1893 | * almost certainly the driver has hung, is not unload-able. Therefore | |
1894 | * hanging here is probably a minor inconvenience not to be seen my | |
1895 | * almost every user. | |
1896 | */ | |
1897 | mutex_lock(&dev->struct_mutex); | |
1898 | gen6_gt_force_wake_put(dev_priv); | |
1899 | mutex_unlock(&dev->struct_mutex); | |
1900 | ||
1901 | return 0; | |
1902 | } | |
1903 | ||
1904 | static const struct file_operations i915_forcewake_fops = { | |
1905 | .owner = THIS_MODULE, | |
1906 | .open = i915_forcewake_open, | |
1907 | .release = i915_forcewake_release, | |
1908 | }; | |
1909 | ||
1910 | static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor) | |
1911 | { | |
1912 | struct drm_device *dev = minor->dev; | |
1913 | struct dentry *ent; | |
1914 | ||
1915 | ent = debugfs_create_file("i915_forcewake_user", | |
8eb57294 | 1916 | S_IRUSR, |
6d794d42 BW |
1917 | root, dev, |
1918 | &i915_forcewake_fops); | |
1919 | if (IS_ERR(ent)) | |
1920 | return PTR_ERR(ent); | |
1921 | ||
8eb57294 | 1922 | return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops); |
6d794d42 BW |
1923 | } |
1924 | ||
6a9c308d DV |
1925 | static int i915_debugfs_create(struct dentry *root, |
1926 | struct drm_minor *minor, | |
1927 | const char *name, | |
1928 | const struct file_operations *fops) | |
07b7ddd9 JB |
1929 | { |
1930 | struct drm_device *dev = minor->dev; | |
1931 | struct dentry *ent; | |
1932 | ||
6a9c308d | 1933 | ent = debugfs_create_file(name, |
07b7ddd9 JB |
1934 | S_IRUGO | S_IWUSR, |
1935 | root, dev, | |
6a9c308d | 1936 | fops); |
07b7ddd9 JB |
1937 | if (IS_ERR(ent)) |
1938 | return PTR_ERR(ent); | |
1939 | ||
6a9c308d | 1940 | return drm_add_fake_info_node(minor, ent, fops); |
07b7ddd9 JB |
1941 | } |
1942 | ||
27c202ad | 1943 | static struct drm_info_list i915_debugfs_list[] = { |
311bd68e | 1944 | {"i915_capabilities", i915_capabilities, 0}, |
73aa808f | 1945 | {"i915_gem_objects", i915_gem_object_info, 0}, |
08c18323 | 1946 | {"i915_gem_gtt", i915_gem_gtt_info, 0}, |
1b50247a | 1947 | {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST}, |
433e12f7 BG |
1948 | {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST}, |
1949 | {"i915_gem_flushing", i915_gem_object_list_info, 0, (void *) FLUSHING_LIST}, | |
1950 | {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST}, | |
4e5359cd | 1951 | {"i915_gem_pageflip", i915_gem_pageflip_info, 0}, |
2017263e BG |
1952 | {"i915_gem_request", i915_gem_request_info, 0}, |
1953 | {"i915_gem_seqno", i915_gem_seqno_info, 0}, | |
a6172a80 | 1954 | {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0}, |
2017263e | 1955 | {"i915_gem_interrupt", i915_interrupt_info, 0}, |
1ec14ad3 CW |
1956 | {"i915_gem_hws", i915_hws_info, 0, (void *)RCS}, |
1957 | {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS}, | |
1958 | {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS}, | |
f97108d1 JB |
1959 | {"i915_rstdby_delays", i915_rstdby_delays, 0}, |
1960 | {"i915_cur_delayinfo", i915_cur_delayinfo, 0}, | |
1961 | {"i915_delayfreq_table", i915_delayfreq_table, 0}, | |
1962 | {"i915_inttoext_table", i915_inttoext_table, 0}, | |
1963 | {"i915_drpc_info", i915_drpc_info, 0}, | |
7648fa99 | 1964 | {"i915_emon_status", i915_emon_status, 0}, |
23b2f8bb | 1965 | {"i915_ring_freq_table", i915_ring_freq_table, 0}, |
7648fa99 | 1966 | {"i915_gfxec", i915_gfxec, 0}, |
b5e50c3f | 1967 | {"i915_fbc_status", i915_fbc_status, 0}, |
4a9bef37 | 1968 | {"i915_sr_status", i915_sr_status, 0}, |
44834a67 | 1969 | {"i915_opregion", i915_opregion, 0}, |
37811fcc | 1970 | {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0}, |
e76d3630 | 1971 | {"i915_context_status", i915_context_status, 0}, |
6d794d42 | 1972 | {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0}, |
ea16a3cd | 1973 | {"i915_swizzle_info", i915_swizzle_info, 0}, |
3cf17fc5 | 1974 | {"i915_ppgtt_info", i915_ppgtt_info, 0}, |
57f350b6 | 1975 | {"i915_dpio", i915_dpio_info, 0}, |
2017263e | 1976 | }; |
27c202ad | 1977 | #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list) |
2017263e | 1978 | |
27c202ad | 1979 | int i915_debugfs_init(struct drm_minor *minor) |
2017263e | 1980 | { |
f3cd474b CW |
1981 | int ret; |
1982 | ||
6a9c308d DV |
1983 | ret = i915_debugfs_create(minor->debugfs_root, minor, |
1984 | "i915_wedged", | |
1985 | &i915_wedged_fops); | |
f3cd474b CW |
1986 | if (ret) |
1987 | return ret; | |
1988 | ||
6d794d42 | 1989 | ret = i915_forcewake_create(minor->debugfs_root, minor); |
358733e9 JB |
1990 | if (ret) |
1991 | return ret; | |
6a9c308d DV |
1992 | |
1993 | ret = i915_debugfs_create(minor->debugfs_root, minor, | |
1994 | "i915_max_freq", | |
1995 | &i915_max_freq_fops); | |
07b7ddd9 JB |
1996 | if (ret) |
1997 | return ret; | |
6a9c308d DV |
1998 | |
1999 | ret = i915_debugfs_create(minor->debugfs_root, minor, | |
2000 | "i915_cache_sharing", | |
2001 | &i915_cache_sharing_fops); | |
6d794d42 BW |
2002 | if (ret) |
2003 | return ret; | |
e5eb3d63 DV |
2004 | ret = i915_debugfs_create(minor->debugfs_root, minor, |
2005 | "i915_ring_stop", | |
2006 | &i915_ring_stop_fops); | |
2007 | if (ret) | |
2008 | return ret; | |
6d794d42 | 2009 | |
d5442303 DV |
2010 | ret = i915_debugfs_create(minor->debugfs_root, minor, |
2011 | "i915_error_state", | |
2012 | &i915_error_state_fops); | |
2013 | if (ret) | |
2014 | return ret; | |
2015 | ||
27c202ad BG |
2016 | return drm_debugfs_create_files(i915_debugfs_list, |
2017 | I915_DEBUGFS_ENTRIES, | |
2017263e BG |
2018 | minor->debugfs_root, minor); |
2019 | } | |
2020 | ||
27c202ad | 2021 | void i915_debugfs_cleanup(struct drm_minor *minor) |
2017263e | 2022 | { |
27c202ad BG |
2023 | drm_debugfs_remove_files(i915_debugfs_list, |
2024 | I915_DEBUGFS_ENTRIES, minor); | |
6d794d42 BW |
2025 | drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops, |
2026 | 1, minor); | |
33db679b KH |
2027 | drm_debugfs_remove_files((struct drm_info_list *) &i915_wedged_fops, |
2028 | 1, minor); | |
358733e9 JB |
2029 | drm_debugfs_remove_files((struct drm_info_list *) &i915_max_freq_fops, |
2030 | 1, minor); | |
07b7ddd9 JB |
2031 | drm_debugfs_remove_files((struct drm_info_list *) &i915_cache_sharing_fops, |
2032 | 1, minor); | |
e5eb3d63 DV |
2033 | drm_debugfs_remove_files((struct drm_info_list *) &i915_ring_stop_fops, |
2034 | 1, minor); | |
2017263e BG |
2035 | } |
2036 | ||
2037 | #endif /* CONFIG_DEBUG_FS */ |