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drm/i915: Limit mmio flip RPS boosts
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_debugfs.c
CommitLineData
2017263e
BG		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 *
27 */
28
29#include <linux/seq_file.h>
b2c88f5b 30#include <linux/circ_buf.h>
926321d5 31#include <linux/ctype.h>
f3cd474b 32#include <linux/debugfs.h>
5a0e3ad6 33#include <linux/slab.h>
2d1a8a48 34#include <linux/export.h>
6d2b8885 35#include <linux/list_sort.h>
ec013e7f 36#include <asm/msr-index.h>
760285e7 37#include <drm/drmP.h>
4e5359cd 38#include "intel_drv.h"
e5c65260 39#include "intel_ringbuffer.h"
760285e7 40#include <drm/i915_drm.h>
2017263e
BG		 41#include "i915_drv.h"
42
f13d3f73 43enum {
69dc4987 44 ACTIVE_LIST,
f13d3f73 45 INACTIVE_LIST,
d21d5975 46 PINNED_LIST,
f13d3f73 47};
2017263e 48
70d39fe4
CW		 49static const char *yesno(int v)
50{
51 return v ? "yes" : "no";
52}
53
497666d8
DL		 54/* As the drm_debugfs_init() routines are called before dev->dev_private is
55 * allocated we need to hook into the minor for release. */
56static int
57drm_add_fake_info_node(struct drm_minor *minor,
58 struct dentry *ent,
59 const void *key)
60{
61 struct drm_info_node *node;
62
63 node = kmalloc(sizeof(*node), GFP_KERNEL);
64 if (node == NULL) {
65 debugfs_remove(ent);
66 return -ENOMEM;
67 }
68
69 node->minor = minor;
70 node->dent = ent;
71 node->info_ent = (void *) key;
72
73 mutex_lock(&minor->debugfs_lock);
74 list_add(&node->list, &minor->debugfs_list);
75 mutex_unlock(&minor->debugfs_lock);
76
77 return 0;
78}
79
70d39fe4
CW		 80static int i915_capabilities(struct seq_file *m, void *data)
81{
9f25d007 82 struct drm_info_node *node = m->private;
70d39fe4
CW		 83 struct drm_device *dev = node->minor->dev;
84 const struct intel_device_info *info = INTEL_INFO(dev);
85
86 seq_printf(m, "gen: %d\n", info->gen);
03d00ac5 87 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
79fc46df
DL		 88#define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
89#define SEP_SEMICOLON ;
90 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
91#undef PRINT_FLAG
92#undef SEP_SEMICOLON
70d39fe4
CW		 93
94 return 0;
95}
2017263e 96
05394f39 97static const char *get_pin_flag(struct drm_i915_gem_object *obj)
a6172a80 98{
baaa5cfb 99 if (obj->pin_display)
a6172a80
CW		 100 return "p";
101 else
102 return " ";
103}
104
05394f39 105static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
a6172a80 106{
0206e353
AJ		 107 switch (obj->tiling_mode) {
108 default:
109 case I915_TILING_NONE: return " ";
110 case I915_TILING_X: return "X";
111 case I915_TILING_Y: return "Y";
112 }
a6172a80
CW		 113}
114
1d693bcc
BW		 115static inline const char *get_global_flag(struct drm_i915_gem_object *obj)
116{
aff43766 117 return i915_gem_obj_to_ggtt(obj) ? "g" : " ";
1d693bcc
BW		 118}
119
37811fcc
CW		 120static void
121describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
122{
b4716185
CW		 123 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
124 struct intel_engine_cs *ring;
1d693bcc 125 struct i915_vma *vma;
d7f46fc4 126 int pin_count = 0;
b4716185 127 int i;
d7f46fc4 128
b4716185 129 seq_printf(m, "%pK: %s%s%s%s %8zdKiB %02x %02x [ ",
37811fcc 130 &obj->base,
481a3d43 131 obj->active ? "*" : " ",
37811fcc
CW		 132 get_pin_flag(obj),
133 get_tiling_flag(obj),
1d693bcc 134 get_global_flag(obj),
a05a5862 135 obj->base.size / 1024,
37811fcc 136 obj->base.read_domains,
b4716185
CW		 137 obj->base.write_domain);
138 for_each_ring(ring, dev_priv, i)
139 seq_printf(m, "%x ",
140 i915_gem_request_get_seqno(obj->last_read_req[i]));
141 seq_printf(m, "] %x %x%s%s%s",
97b2a6a1
JH		 142 i915_gem_request_get_seqno(obj->last_write_req),
143 i915_gem_request_get_seqno(obj->last_fenced_req),
0a4cd7c8 144 i915_cache_level_str(to_i915(obj->base.dev), obj->cache_level),
37811fcc
CW		 145 obj->dirty ? " dirty" : "",
146 obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
147 if (obj->base.name)
148 seq_printf(m, " (name: %d)", obj->base.name);
ba0635ff 149 list_for_each_entry(vma, &obj->vma_list, vma_link) {
d7f46fc4
BW		 150 if (vma->pin_count > 0)
151 pin_count++;
ba0635ff
DC		 152 }
153 seq_printf(m, " (pinned x %d)", pin_count);
cc98b413
CW		 154 if (obj->pin_display)
155 seq_printf(m, " (display)");
37811fcc
CW		 156 if (obj->fence_reg != I915_FENCE_REG_NONE)
157 seq_printf(m, " (fence: %d)", obj->fence_reg);
1d693bcc
BW		 158 list_for_each_entry(vma, &obj->vma_list, vma_link) {
159 if (!i915_is_ggtt(vma->vm))
160 seq_puts(m, " (pp");
161 else
162 seq_puts(m, " (g");
440fd528 163 seq_printf(m, "gtt offset: %08llx, size: %08llx, type: %u)",
fe14d5f4
TU		 164 vma->node.start, vma->node.size,
165 vma->ggtt_view.type);
1d693bcc 166 }
c1ad11fc 167 if (obj->stolen)
440fd528 168 seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
30154650 169 if (obj->pin_display || obj->fault_mappable) {
6299f992 170 char s[3], *t = s;
30154650 171 if (obj->pin_display)
6299f992
CW		 172 *t++ = 'p';
173 if (obj->fault_mappable)
174 *t++ = 'f';
175 *t = '\0';
176 seq_printf(m, " (%s mappable)", s);
177 }
b4716185 178 if (obj->last_write_req != NULL)
41c52415 179 seq_printf(m, " (%s)",
b4716185 180 i915_gem_request_get_ring(obj->last_write_req)->name);
d5a81ef1
DV		 181 if (obj->frontbuffer_bits)
182 seq_printf(m, " (frontbuffer: 0x%03x)", obj->frontbuffer_bits);
37811fcc
CW		 183}
184
273497e5 185static void describe_ctx(struct seq_file *m, struct intel_context *ctx)
3ccfd19d 186{
ea0c76f8 187 seq_putc(m, ctx->legacy_hw_ctx.initialized ? 'I' : 'i');
3ccfd19d
BW		 188 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
189 seq_putc(m, ' ');
190}
191
433e12f7 192static int i915_gem_object_list_info(struct seq_file *m, void *data)
2017263e 193{
9f25d007 194 struct drm_info_node *node = m->private;
433e12f7
BG		 195 uintptr_t list = (uintptr_t) node->info_ent->data;
196 struct list_head *head;
2017263e 197 struct drm_device *dev = node->minor->dev;
5cef07e1
BW		 198 struct drm_i915_private *dev_priv = dev->dev_private;
199 struct i915_address_space *vm = &dev_priv->gtt.base;
ca191b13 200 struct i915_vma *vma;
8f2480fb
CW		 201 size_t total_obj_size, total_gtt_size;
202 int count, ret;
de227ef0
CW		 203
204 ret = mutex_lock_interruptible(&dev->struct_mutex);
205 if (ret)
206 return ret;
2017263e 207
ca191b13 208 /* FIXME: the user of this interface might want more than just GGTT */
433e12f7
BG		 209 switch (list) {
210 case ACTIVE_LIST:
267f0c90 211 seq_puts(m, "Active:\n");
5cef07e1 212 head = &vm->active_list;
433e12f7
BG		 213 break;
214 case INACTIVE_LIST:
267f0c90 215 seq_puts(m, "Inactive:\n");
5cef07e1 216 head = &vm->inactive_list;
433e12f7 217 break;
433e12f7 218 default:
de227ef0
CW		 219 mutex_unlock(&dev->struct_mutex);
220 return -EINVAL;
2017263e 221 }
2017263e 222
8f2480fb 223 total_obj_size = total_gtt_size = count = 0;
ca191b13
BW		 224 list_for_each_entry(vma, head, mm_list) {
225 seq_printf(m, " ");
226 describe_obj(m, vma->obj);
227 seq_printf(m, "\n");
228 total_obj_size += vma->obj->base.size;
229 total_gtt_size += vma->node.size;
8f2480fb 230 count++;
2017263e 231 }
de227ef0 232 mutex_unlock(&dev->struct_mutex);
5e118f41 233
8f2480fb
CW		 234 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
235 count, total_obj_size, total_gtt_size);
2017263e
BG		 236 return 0;
237}
238
6d2b8885
CW		 239static int obj_rank_by_stolen(void *priv,
240 struct list_head *A, struct list_head *B)
241{
242 struct drm_i915_gem_object *a =
b25cb2f8 243 container_of(A, struct drm_i915_gem_object, obj_exec_link);
6d2b8885 244 struct drm_i915_gem_object *b =
b25cb2f8 245 container_of(B, struct drm_i915_gem_object, obj_exec_link);
6d2b8885
CW		 246
247 return a->stolen->start - b->stolen->start;
248}
249
250static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
251{
9f25d007 252 struct drm_info_node *node = m->private;
6d2b8885
CW		 253 struct drm_device *dev = node->minor->dev;
254 struct drm_i915_private *dev_priv = dev->dev_private;
255 struct drm_i915_gem_object *obj;
256 size_t total_obj_size, total_gtt_size;
257 LIST_HEAD(stolen);
258 int count, ret;
259
260 ret = mutex_lock_interruptible(&dev->struct_mutex);
261 if (ret)
262 return ret;
263
264 total_obj_size = total_gtt_size = count = 0;
265 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
266 if (obj->stolen == NULL)
267 continue;
268
b25cb2f8 269 list_add(&obj->obj_exec_link, &stolen);
6d2b8885
CW		 270
271 total_obj_size += obj->base.size;
272 total_gtt_size += i915_gem_obj_ggtt_size(obj);
273 count++;
274 }
275 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
276 if (obj->stolen == NULL)
277 continue;
278
b25cb2f8 279 list_add(&obj->obj_exec_link, &stolen);
6d2b8885
CW		 280
281 total_obj_size += obj->base.size;
282 count++;
283 }
284 list_sort(NULL, &stolen, obj_rank_by_stolen);
285 seq_puts(m, "Stolen:\n");
286 while (!list_empty(&stolen)) {
b25cb2f8 287 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
6d2b8885
CW		 288 seq_puts(m, " ");
289 describe_obj(m, obj);
290 seq_putc(m, '\n');
b25cb2f8 291 list_del_init(&obj->obj_exec_link);
6d2b8885
CW		 292 }
293 mutex_unlock(&dev->struct_mutex);
294
295 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
296 count, total_obj_size, total_gtt_size);
297 return 0;
298}
299
6299f992
CW		 300#define count_objects(list, member) do { \
301 list_for_each_entry(obj, list, member) { \
f343c5f6 302 size += i915_gem_obj_ggtt_size(obj); \
6299f992
CW		 303 ++count; \
304 if (obj->map_and_fenceable) { \
f343c5f6 305 mappable_size += i915_gem_obj_ggtt_size(obj); \
6299f992
CW		 306 ++mappable_count; \
307 } \
308 } \
0206e353 309} while (0)
6299f992 310
2db8e9d6 311struct file_stats {
6313c204 312 struct drm_i915_file_private *file_priv;
2db8e9d6 313 int count;
c67a17e9
CW		 314 size_t total, unbound;
315 size_t global, shared;
316 size_t active, inactive;
2db8e9d6
CW		 317};
318
319static int per_file_stats(int id, void *ptr, void *data)
320{
321 struct drm_i915_gem_object *obj = ptr;
322 struct file_stats *stats = data;
6313c204 323 struct i915_vma *vma;
2db8e9d6
CW		 324
325 stats->count++;
326 stats->total += obj->base.size;
327
c67a17e9
CW		 328 if (obj->base.name || obj->base.dma_buf)
329 stats->shared += obj->base.size;
330
6313c204
CW		 331 if (USES_FULL_PPGTT(obj->base.dev)) {
332 list_for_each_entry(vma, &obj->vma_list, vma_link) {
333 struct i915_hw_ppgtt *ppgtt;
334
335 if (!drm_mm_node_allocated(&vma->node))
336 continue;
337
338 if (i915_is_ggtt(vma->vm)) {
339 stats->global += obj->base.size;
340 continue;
341 }
342
343 ppgtt = container_of(vma->vm, struct i915_hw_ppgtt, base);
4d884705 344 if (ppgtt->file_priv != stats->file_priv)
6313c204
CW		 345 continue;
346
41c52415 347 if (obj->active) /* XXX per-vma statistic */
6313c204
CW		 348 stats->active += obj->base.size;
349 else
350 stats->inactive += obj->base.size;
351
352 return 0;
353 }
2db8e9d6 354 } else {
6313c204
CW		 355 if (i915_gem_obj_ggtt_bound(obj)) {
356 stats->global += obj->base.size;
41c52415 357 if (obj->active)
6313c204
CW		 358 stats->active += obj->base.size;
359 else
360 stats->inactive += obj->base.size;
361 return 0;
362 }
2db8e9d6
CW		 363 }
364
6313c204
CW		 365 if (!list_empty(&obj->global_list))
366 stats->unbound += obj->base.size;
367
2db8e9d6
CW		 368 return 0;
369}
370
b0da1b79
CW		 371#define print_file_stats(m, name, stats) do { \
372 if (stats.count) \
373 seq_printf(m, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu global, %zu shared, %zu unbound)\n", \
374 name, \
375 stats.count, \
376 stats.total, \
377 stats.active, \
378 stats.inactive, \
379 stats.global, \
380 stats.shared, \
381 stats.unbound); \
382} while (0)
493018dc
BV		 383
384static void print_batch_pool_stats(struct seq_file *m,
385 struct drm_i915_private *dev_priv)
386{
387 struct drm_i915_gem_object *obj;
388 struct file_stats stats;
06fbca71 389 struct intel_engine_cs *ring;
8d9d5744 390 int i, j;
493018dc
BV		 391
392 memset(&stats, 0, sizeof(stats));
393
06fbca71 394 for_each_ring(ring, dev_priv, i) {
8d9d5744
CW		 395 for (j = 0; j < ARRAY_SIZE(ring->batch_pool.cache_list); j++) {
396 list_for_each_entry(obj,
397 &ring->batch_pool.cache_list[j],
398 batch_pool_link)
399 per_file_stats(0, obj, &stats);
400 }
06fbca71 401 }
493018dc 402
b0da1b79 403 print_file_stats(m, "[k]batch pool", stats);
493018dc
BV		 404}
405
ca191b13
BW		 406#define count_vmas(list, member) do { \
407 list_for_each_entry(vma, list, member) { \
408 size += i915_gem_obj_ggtt_size(vma->obj); \
409 ++count; \
410 if (vma->obj->map_and_fenceable) { \
411 mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
412 ++mappable_count; \
413 } \
414 } \
415} while (0)
416
417static int i915_gem_object_info(struct seq_file *m, void* data)
73aa808f 418{
9f25d007 419 struct drm_info_node *node = m->private;
73aa808f
CW		 420 struct drm_device *dev = node->minor->dev;
421 struct drm_i915_private *dev_priv = dev->dev_private;
b7abb714
CW		 422 u32 count, mappable_count, purgeable_count;
423 size_t size, mappable_size, purgeable_size;
6299f992 424 struct drm_i915_gem_object *obj;
5cef07e1 425 struct i915_address_space *vm = &dev_priv->gtt.base;
2db8e9d6 426 struct drm_file *file;
ca191b13 427 struct i915_vma *vma;
73aa808f
CW		 428 int ret;
429
430 ret = mutex_lock_interruptible(&dev->struct_mutex);
431 if (ret)
432 return ret;
433
6299f992
CW		 434 seq_printf(m, "%u objects, %zu bytes\n",
435 dev_priv->mm.object_count,
436 dev_priv->mm.object_memory);
437
438 size = count = mappable_size = mappable_count = 0;
35c20a60 439 count_objects(&dev_priv->mm.bound_list, global_list);
6299f992
CW		 440 seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n",
441 count, mappable_count, size, mappable_size);
442
443 size = count = mappable_size = mappable_count = 0;
ca191b13 444 count_vmas(&vm->active_list, mm_list);
6299f992
CW		 445 seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n",
446 count, mappable_count, size, mappable_size);
447
6299f992 448 size = count = mappable_size = mappable_count = 0;
ca191b13 449 count_vmas(&vm->inactive_list, mm_list);
6299f992
CW		 450 seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n",
451 count, mappable_count, size, mappable_size);
452
b7abb714 453 size = count = purgeable_size = purgeable_count = 0;
35c20a60 454 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
6c085a72 455 size += obj->base.size, ++count;
b7abb714
CW		 456 if (obj->madv == I915_MADV_DONTNEED)
457 purgeable_size += obj->base.size, ++purgeable_count;
458 }
6c085a72
CW		 459 seq_printf(m, "%u unbound objects, %zu bytes\n", count, size);
460
6299f992 461 size = count = mappable_size = mappable_count = 0;
35c20a60 462 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
6299f992 463 if (obj->fault_mappable) {
f343c5f6 464 size += i915_gem_obj_ggtt_size(obj);
6299f992
CW		 465 ++count;
466 }
30154650 467 if (obj->pin_display) {
f343c5f6 468 mappable_size += i915_gem_obj_ggtt_size(obj);
6299f992
CW		 469 ++mappable_count;
470 }
b7abb714
CW		 471 if (obj->madv == I915_MADV_DONTNEED) {
472 purgeable_size += obj->base.size;
473 ++purgeable_count;
474 }
6299f992 475 }
b7abb714
CW		 476 seq_printf(m, "%u purgeable objects, %zu bytes\n",
477 purgeable_count, purgeable_size);
6299f992
CW		 478 seq_printf(m, "%u pinned mappable objects, %zu bytes\n",
479 mappable_count, mappable_size);
480 seq_printf(m, "%u fault mappable objects, %zu bytes\n",
481 count, size);
482
93d18799 483 seq_printf(m, "%zu [%lu] gtt total\n",
853ba5d2
BW		 484 dev_priv->gtt.base.total,
485 dev_priv->gtt.mappable_end - dev_priv->gtt.base.start);
73aa808f 486
493018dc
BV		 487 seq_putc(m, '\n');
488 print_batch_pool_stats(m, dev_priv);
2db8e9d6
CW		 489 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
490 struct file_stats stats;
3ec2f427 491 struct task_struct *task;
2db8e9d6
CW		 492
493 memset(&stats, 0, sizeof(stats));
6313c204 494 stats.file_priv = file->driver_priv;
5b5ffff0 495 spin_lock(&file->table_lock);
2db8e9d6 496 idr_for_each(&file->object_idr, per_file_stats, &stats);
5b5ffff0 497 spin_unlock(&file->table_lock);
3ec2f427
TH		 498 /*
499 * Although we have a valid reference on file->pid, that does
500 * not guarantee that the task_struct who called get_pid() is
501 * still alive (e.g. get_pid(current) => fork() => exit()).
502 * Therefore, we need to protect this ->comm access using RCU.
503 */
504 rcu_read_lock();
505 task = pid_task(file->pid, PIDTYPE_PID);
493018dc 506 print_file_stats(m, task ? task->comm : "<unknown>", stats);
3ec2f427 507 rcu_read_unlock();
2db8e9d6
CW		 508 }
509
73aa808f
CW		 510 mutex_unlock(&dev->struct_mutex);
511
512 return 0;
513}
514
aee56cff 515static int i915_gem_gtt_info(struct seq_file *m, void *data)
08c18323 516{
9f25d007 517 struct drm_info_node *node = m->private;
08c18323 518 struct drm_device *dev = node->minor->dev;
1b50247a 519 uintptr_t list = (uintptr_t) node->info_ent->data;
08c18323
CW		 520 struct drm_i915_private *dev_priv = dev->dev_private;
521 struct drm_i915_gem_object *obj;
522 size_t total_obj_size, total_gtt_size;
523 int count, ret;
524
525 ret = mutex_lock_interruptible(&dev->struct_mutex);
526 if (ret)
527 return ret;
528
529 total_obj_size = total_gtt_size = count = 0;
35c20a60 530 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
d7f46fc4 531 if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj))
1b50247a
CW		 532 continue;
533
267f0c90 534 seq_puts(m, " ");
08c18323 535 describe_obj(m, obj);
267f0c90 536 seq_putc(m, '\n');
08c18323 537 total_obj_size += obj->base.size;
f343c5f6 538 total_gtt_size += i915_gem_obj_ggtt_size(obj);
08c18323
CW		 539 count++;
540 }
541
542 mutex_unlock(&dev->struct_mutex);
543
544 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
545 count, total_obj_size, total_gtt_size);
546
547 return 0;
548}
549
4e5359cd
SF		 550static int i915_gem_pageflip_info(struct seq_file *m, void *data)
551{
9f25d007 552 struct drm_info_node *node = m->private;
4e5359cd 553 struct drm_device *dev = node->minor->dev;
d6bbafa1 554 struct drm_i915_private *dev_priv = dev->dev_private;
4e5359cd 555 struct intel_crtc *crtc;
8a270ebf
DV		 556 int ret;
557
558 ret = mutex_lock_interruptible(&dev->struct_mutex);
559 if (ret)
560 return ret;
4e5359cd 561
d3fcc808 562 for_each_intel_crtc(dev, crtc) {
9db4a9c7
JB		 563 const char pipe = pipe_name(crtc->pipe);
564 const char plane = plane_name(crtc->plane);
4e5359cd
SF		 565 struct intel_unpin_work *work;
566
5e2d7afc 567 spin_lock_irq(&dev->event_lock);
4e5359cd
SF		 568 work = crtc->unpin_work;
569 if (work == NULL) {
9db4a9c7 570 seq_printf(m, "No flip due on pipe %c (plane %c)\n",
4e5359cd
SF		 571 pipe, plane);
572 } else {
d6bbafa1
CW		 573 u32 addr;
574
e7d841ca 575 if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9db4a9c7 576 seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
4e5359cd
SF		 577 pipe, plane);
578 } else {
9db4a9c7 579 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
4e5359cd
SF		 580 pipe, plane);
581 }
3a8a946e
DV		 582 if (work->flip_queued_req) {
583 struct intel_engine_cs *ring =
584 i915_gem_request_get_ring(work->flip_queued_req);
585
20e28fba 586 seq_printf(m, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n",
3a8a946e 587 ring->name,
f06cc1b9 588 i915_gem_request_get_seqno(work->flip_queued_req),
d6bbafa1 589 dev_priv->next_seqno,
3a8a946e 590 ring->get_seqno(ring, true),
1b5a433a 591 i915_gem_request_completed(work->flip_queued_req, true));
d6bbafa1
CW		 592 } else
593 seq_printf(m, "Flip not associated with any ring\n");
594 seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
595 work->flip_queued_vblank,
596 work->flip_ready_vblank,
1e3feefd 597 drm_crtc_vblank_count(&crtc->base));
4e5359cd 598 if (work->enable_stall_check)
267f0c90 599 seq_puts(m, "Stall check enabled, ");
4e5359cd 600 else
267f0c90 601 seq_puts(m, "Stall check waiting for page flip ioctl, ");
e7d841ca 602 seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
4e5359cd 603
d6bbafa1
CW		 604 if (INTEL_INFO(dev)->gen >= 4)
605 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane)));
606 else
607 addr = I915_READ(DSPADDR(crtc->plane));
608 seq_printf(m, "Current scanout address 0x%08x\n", addr);
609
4e5359cd 610 if (work->pending_flip_obj) {
d6bbafa1
CW		 611 seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset);
612 seq_printf(m, "MMIO update completed? %d\n", addr == work->gtt_offset);
4e5359cd
SF		 613 }
614 }
5e2d7afc 615 spin_unlock_irq(&dev->event_lock);
4e5359cd
SF		 616 }
617
8a270ebf
DV		 618 mutex_unlock(&dev->struct_mutex);
619
4e5359cd
SF		 620 return 0;
621}
622
493018dc
BV		 623static int i915_gem_batch_pool_info(struct seq_file *m, void *data)
624{
625 struct drm_info_node *node = m->private;
626 struct drm_device *dev = node->minor->dev;
627 struct drm_i915_private *dev_priv = dev->dev_private;
628 struct drm_i915_gem_object *obj;
06fbca71 629 struct intel_engine_cs *ring;
8d9d5744
CW		 630 int total = 0;
631 int ret, i, j;
493018dc
BV		 632
633 ret = mutex_lock_interruptible(&dev->struct_mutex);
634 if (ret)
635 return ret;
636
06fbca71 637 for_each_ring(ring, dev_priv, i) {
8d9d5744
CW		 638 for (j = 0; j < ARRAY_SIZE(ring->batch_pool.cache_list); j++) {
639 int count;
640
641 count = 0;
642 list_for_each_entry(obj,
643 &ring->batch_pool.cache_list[j],
644 batch_pool_link)
645 count++;
646 seq_printf(m, "%s cache[%d]: %d objects\n",
647 ring->name, j, count);
648
649 list_for_each_entry(obj,
650 &ring->batch_pool.cache_list[j],
651 batch_pool_link) {
652 seq_puts(m, " ");
653 describe_obj(m, obj);
654 seq_putc(m, '\n');
655 }
656
657 total += count;
06fbca71 658 }
493018dc
BV		 659 }
660
8d9d5744 661 seq_printf(m, "total: %d\n", total);
493018dc
BV		 662
663 mutex_unlock(&dev->struct_mutex);
664
665 return 0;
666}
667
2017263e
BG		 668static int i915_gem_request_info(struct seq_file *m, void *data)
669{
9f25d007 670 struct drm_info_node *node = m->private;
2017263e 671 struct drm_device *dev = node->minor->dev;
e277a1f8 672 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 673 struct intel_engine_cs *ring;
eed29a5b 674 struct drm_i915_gem_request *req;
2d1070b2 675 int ret, any, i;
de227ef0
CW		 676
677 ret = mutex_lock_interruptible(&dev->struct_mutex);
678 if (ret)
679 return ret;
2017263e 680
2d1070b2 681 any = 0;
a2c7f6fd 682 for_each_ring(ring, dev_priv, i) {
2d1070b2
CW		 683 int count;
684
685 count = 0;
eed29a5b 686 list_for_each_entry(req, &ring->request_list, list)
2d1070b2
CW		 687 count++;
688 if (count == 0)
a2c7f6fd
CW		 689 continue;
690
2d1070b2 691 seq_printf(m, "%s requests: %d\n", ring->name, count);
eed29a5b 692 list_for_each_entry(req, &ring->request_list, list) {
2d1070b2
CW		 693 struct task_struct *task;
694
695 rcu_read_lock();
696 task = NULL;
eed29a5b
DV		 697 if (req->pid)
698 task = pid_task(req->pid, PIDTYPE_PID);
2d1070b2 699 seq_printf(m, " %x @ %d: %s [%d]\n",
eed29a5b
DV		 700 req->seqno,
701 (int) (jiffies - req->emitted_jiffies),
2d1070b2
CW		 702 task ? task->comm : "<unknown>",
703 task ? task->pid : -1);
704 rcu_read_unlock();
c2c347a9 705 }
2d1070b2
CW		 706
707 any++;
2017263e 708 }
de227ef0
CW		 709 mutex_unlock(&dev->struct_mutex);
710
2d1070b2 711 if (any == 0)
267f0c90 712 seq_puts(m, "No requests\n");
c2c347a9 713
2017263e
BG		 714 return 0;
715}
716
b2223497 717static void i915_ring_seqno_info(struct seq_file *m,
a4872ba6 718 struct intel_engine_cs *ring)
b2223497
CW		 719{
720 if (ring->get_seqno) {
20e28fba 721 seq_printf(m, "Current sequence (%s): %x\n",
b2eadbc8 722 ring->name, ring->get_seqno(ring, false));
b2223497
CW		 723 }
724}
725
2017263e
BG		 726static int i915_gem_seqno_info(struct seq_file *m, void *data)
727{
9f25d007 728 struct drm_info_node *node = m->private;
2017263e 729 struct drm_device *dev = node->minor->dev;
e277a1f8 730 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 731 struct intel_engine_cs *ring;
1ec14ad3 732 int ret, i;
de227ef0
CW		 733
734 ret = mutex_lock_interruptible(&dev->struct_mutex);
735 if (ret)
736 return ret;
c8c8fb33 737 intel_runtime_pm_get(dev_priv);
2017263e 738
a2c7f6fd
CW		 739 for_each_ring(ring, dev_priv, i)
740 i915_ring_seqno_info(m, ring);
de227ef0 741
c8c8fb33 742 intel_runtime_pm_put(dev_priv);
de227ef0
CW		 743 mutex_unlock(&dev->struct_mutex);
744
2017263e
BG		 745 return 0;
746}
747
748
749static int i915_interrupt_info(struct seq_file *m, void *data)
750{
9f25d007 751 struct drm_info_node *node = m->private;
2017263e 752 struct drm_device *dev = node->minor->dev;
e277a1f8 753 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 754 struct intel_engine_cs *ring;
9db4a9c7 755 int ret, i, pipe;
de227ef0
CW		 756
757 ret = mutex_lock_interruptible(&dev->struct_mutex);
758 if (ret)
759 return ret;
c8c8fb33 760 intel_runtime_pm_get(dev_priv);
2017263e 761
74e1ca8c 762 if (IS_CHERRYVIEW(dev)) {
74e1ca8c
VS		 763 seq_printf(m, "Master Interrupt Control:\t%08x\n",
764 I915_READ(GEN8_MASTER_IRQ));
765
766 seq_printf(m, "Display IER:\t%08x\n",
767 I915_READ(VLV_IER));
768 seq_printf(m, "Display IIR:\t%08x\n",
769 I915_READ(VLV_IIR));
770 seq_printf(m, "Display IIR_RW:\t%08x\n",
771 I915_READ(VLV_IIR_RW));
772 seq_printf(m, "Display IMR:\t%08x\n",
773 I915_READ(VLV_IMR));
055e393f 774 for_each_pipe(dev_priv, pipe)
74e1ca8c
VS		 775 seq_printf(m, "Pipe %c stat:\t%08x\n",
776 pipe_name(pipe),
777 I915_READ(PIPESTAT(pipe)));
778
779 seq_printf(m, "Port hotplug:\t%08x\n",
780 I915_READ(PORT_HOTPLUG_EN));
781 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
782 I915_READ(VLV_DPFLIPSTAT));
783 seq_printf(m, "DPINVGTT:\t%08x\n",
784 I915_READ(DPINVGTT));
785
786 for (i = 0; i < 4; i++) {
787 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
788 i, I915_READ(GEN8_GT_IMR(i)));
789 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
790 i, I915_READ(GEN8_GT_IIR(i)));
791 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
792 i, I915_READ(GEN8_GT_IER(i)));
793 }
794
795 seq_printf(m, "PCU interrupt mask:\t%08x\n",
796 I915_READ(GEN8_PCU_IMR));
797 seq_printf(m, "PCU interrupt identity:\t%08x\n",
798 I915_READ(GEN8_PCU_IIR));
799 seq_printf(m, "PCU interrupt enable:\t%08x\n",
800 I915_READ(GEN8_PCU_IER));
801 } else if (INTEL_INFO(dev)->gen >= 8) {
a123f157
BW		 802 seq_printf(m, "Master Interrupt Control:\t%08x\n",
803 I915_READ(GEN8_MASTER_IRQ));
804
805 for (i = 0; i < 4; i++) {
806 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
807 i, I915_READ(GEN8_GT_IMR(i)));
808 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
809 i, I915_READ(GEN8_GT_IIR(i)));
810 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
811 i, I915_READ(GEN8_GT_IER(i)));
812 }
813
055e393f 814 for_each_pipe(dev_priv, pipe) {
f458ebbc 815 if (!intel_display_power_is_enabled(dev_priv,
22c59960
PZ		 816 POWER_DOMAIN_PIPE(pipe))) {
817 seq_printf(m, "Pipe %c power disabled\n",
818 pipe_name(pipe));
819 continue;
820 }
a123f157 821 seq_printf(m, "Pipe %c IMR:\t%08x\n",
07d27e20
DL		 822 pipe_name(pipe),
823 I915_READ(GEN8_DE_PIPE_IMR(pipe)));
a123f157 824 seq_printf(m, "Pipe %c IIR:\t%08x\n",
07d27e20
DL		 825 pipe_name(pipe),
826 I915_READ(GEN8_DE_PIPE_IIR(pipe)));
a123f157 827 seq_printf(m, "Pipe %c IER:\t%08x\n",
07d27e20
DL		 828 pipe_name(pipe),
829 I915_READ(GEN8_DE_PIPE_IER(pipe)));
a123f157
BW		 830 }
831
832 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
833 I915_READ(GEN8_DE_PORT_IMR));
834 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
835 I915_READ(GEN8_DE_PORT_IIR));
836 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
837 I915_READ(GEN8_DE_PORT_IER));
838
839 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
840 I915_READ(GEN8_DE_MISC_IMR));
841 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
842 I915_READ(GEN8_DE_MISC_IIR));
843 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
844 I915_READ(GEN8_DE_MISC_IER));
845
846 seq_printf(m, "PCU interrupt mask:\t%08x\n",
847 I915_READ(GEN8_PCU_IMR));
848 seq_printf(m, "PCU interrupt identity:\t%08x\n",
849 I915_READ(GEN8_PCU_IIR));
850 seq_printf(m, "PCU interrupt enable:\t%08x\n",
851 I915_READ(GEN8_PCU_IER));
852 } else if (IS_VALLEYVIEW(dev)) {
7e231dbe
JB		 853 seq_printf(m, "Display IER:\t%08x\n",
854 I915_READ(VLV_IER));
855 seq_printf(m, "Display IIR:\t%08x\n",
856 I915_READ(VLV_IIR));
857 seq_printf(m, "Display IIR_RW:\t%08x\n",
858 I915_READ(VLV_IIR_RW));
859 seq_printf(m, "Display IMR:\t%08x\n",
860 I915_READ(VLV_IMR));
055e393f 861 for_each_pipe(dev_priv, pipe)
7e231dbe
JB		 862 seq_printf(m, "Pipe %c stat:\t%08x\n",
863 pipe_name(pipe),
864 I915_READ(PIPESTAT(pipe)));
865
866 seq_printf(m, "Master IER:\t%08x\n",
867 I915_READ(VLV_MASTER_IER));
868
869 seq_printf(m, "Render IER:\t%08x\n",
870 I915_READ(GTIER));
871 seq_printf(m, "Render IIR:\t%08x\n",
872 I915_READ(GTIIR));
873 seq_printf(m, "Render IMR:\t%08x\n",
874 I915_READ(GTIMR));
875
876 seq_printf(m, "PM IER:\t\t%08x\n",
877 I915_READ(GEN6_PMIER));
878 seq_printf(m, "PM IIR:\t\t%08x\n",
879 I915_READ(GEN6_PMIIR));
880 seq_printf(m, "PM IMR:\t\t%08x\n",
881 I915_READ(GEN6_PMIMR));
882
883 seq_printf(m, "Port hotplug:\t%08x\n",
884 I915_READ(PORT_HOTPLUG_EN));
885 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
886 I915_READ(VLV_DPFLIPSTAT));
887 seq_printf(m, "DPINVGTT:\t%08x\n",
888 I915_READ(DPINVGTT));
889
890 } else if (!HAS_PCH_SPLIT(dev)) {
5f6a1695
ZW		 891 seq_printf(m, "Interrupt enable: %08x\n",
892 I915_READ(IER));
893 seq_printf(m, "Interrupt identity: %08x\n",
894 I915_READ(IIR));
895 seq_printf(m, "Interrupt mask: %08x\n",
896 I915_READ(IMR));
055e393f 897 for_each_pipe(dev_priv, pipe)
9db4a9c7
JB		 898 seq_printf(m, "Pipe %c stat: %08x\n",
899 pipe_name(pipe),
900 I915_READ(PIPESTAT(pipe)));
5f6a1695
ZW		 901 } else {
902 seq_printf(m, "North Display Interrupt enable: %08x\n",
903 I915_READ(DEIER));
904 seq_printf(m, "North Display Interrupt identity: %08x\n",
905 I915_READ(DEIIR));
906 seq_printf(m, "North Display Interrupt mask: %08x\n",
907 I915_READ(DEIMR));
908 seq_printf(m, "South Display Interrupt enable: %08x\n",
909 I915_READ(SDEIER));
910 seq_printf(m, "South Display Interrupt identity: %08x\n",
911 I915_READ(SDEIIR));
912 seq_printf(m, "South Display Interrupt mask: %08x\n",
913 I915_READ(SDEIMR));
914 seq_printf(m, "Graphics Interrupt enable: %08x\n",
915 I915_READ(GTIER));
916 seq_printf(m, "Graphics Interrupt identity: %08x\n",
917 I915_READ(GTIIR));
918 seq_printf(m, "Graphics Interrupt mask: %08x\n",
919 I915_READ(GTIMR));
920 }
a2c7f6fd 921 for_each_ring(ring, dev_priv, i) {
a123f157 922 if (INTEL_INFO(dev)->gen >= 6) {
a2c7f6fd
CW		 923 seq_printf(m,
924 "Graphics Interrupt mask (%s): %08x\n",
925 ring->name, I915_READ_IMR(ring));
9862e600 926 }
a2c7f6fd 927 i915_ring_seqno_info(m, ring);
9862e600 928 }
c8c8fb33 929 intel_runtime_pm_put(dev_priv);
de227ef0
CW		 930 mutex_unlock(&dev->struct_mutex);
931
2017263e
BG		 932 return 0;
933}
934
a6172a80
CW		 935static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
936{
9f25d007 937 struct drm_info_node *node = m->private;
a6172a80 938 struct drm_device *dev = node->minor->dev;
e277a1f8 939 struct drm_i915_private *dev_priv = dev->dev_private;
de227ef0
CW		 940 int i, ret;
941
942 ret = mutex_lock_interruptible(&dev->struct_mutex);
943 if (ret)
944 return ret;
a6172a80
CW		 945
946 seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
947 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
948 for (i = 0; i < dev_priv->num_fence_regs; i++) {
05394f39 949 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
a6172a80 950
6c085a72
CW		 951 seq_printf(m, "Fence %d, pin count = %d, object = ",
952 i, dev_priv->fence_regs[i].pin_count);
c2c347a9 953 if (obj == NULL)
267f0c90 954 seq_puts(m, "unused");
c2c347a9 955 else
05394f39 956 describe_obj(m, obj);
267f0c90 957 seq_putc(m, '\n');
a6172a80
CW		 958 }
959
05394f39 960 mutex_unlock(&dev->struct_mutex);
a6172a80
CW		 961 return 0;
962}
963
2017263e
BG		 964static int i915_hws_info(struct seq_file *m, void *data)
965{
9f25d007 966 struct drm_info_node *node = m->private;
2017263e 967 struct drm_device *dev = node->minor->dev;
e277a1f8 968 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 969 struct intel_engine_cs *ring;
1a240d4d 970 const u32 *hws;
4066c0ae
CW		 971 int i;
972
1ec14ad3 973 ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
1a240d4d 974 hws = ring->status_page.page_addr;
2017263e
BG		 975 if (hws == NULL)
976 return 0;
977
978 for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
979 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
980 i * 4,
981 hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
982 }
983 return 0;
984}
985
d5442303
DV		 986static ssize_t
987i915_error_state_write(struct file *filp,
988 const char __user *ubuf,
989 size_t cnt,
990 loff_t *ppos)
991{
edc3d884 992 struct i915_error_state_file_priv *error_priv = filp->private_data;
d5442303 993 struct drm_device *dev = error_priv->dev;
22bcfc6a 994 int ret;
d5442303
DV		 995
996 DRM_DEBUG_DRIVER("Resetting error state\n");
997
22bcfc6a
DV		 998 ret = mutex_lock_interruptible(&dev->struct_mutex);
999 if (ret)
1000 return ret;
1001
d5442303
DV		 1002 i915_destroy_error_state(dev);
1003 mutex_unlock(&dev->struct_mutex);
1004
1005 return cnt;
1006}
1007
1008static int i915_error_state_open(struct inode *inode, struct file *file)
1009{
1010 struct drm_device *dev = inode->i_private;
d5442303 1011 struct i915_error_state_file_priv *error_priv;
d5442303
DV		 1012
1013 error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
1014 if (!error_priv)
1015 return -ENOMEM;
1016
1017 error_priv->dev = dev;
1018
95d5bfb3 1019 i915_error_state_get(dev, error_priv);
d5442303 1020
edc3d884
MK		 1021 file->private_data = error_priv;
1022
1023 return 0;
d5442303
DV		 1024}
1025
1026static int i915_error_state_release(struct inode *inode, struct file *file)
1027{
edc3d884 1028 struct i915_error_state_file_priv *error_priv = file->private_data;
d5442303 1029
95d5bfb3 1030 i915_error_state_put(error_priv);
d5442303
DV		 1031 kfree(error_priv);
1032
edc3d884
MK		 1033 return 0;
1034}
1035
4dc955f7
MK		 1036static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
1037 size_t count, loff_t *pos)
1038{
1039 struct i915_error_state_file_priv *error_priv = file->private_data;
1040 struct drm_i915_error_state_buf error_str;
1041 loff_t tmp_pos = 0;
1042 ssize_t ret_count = 0;
1043 int ret;
1044
0a4cd7c8 1045 ret = i915_error_state_buf_init(&error_str, to_i915(error_priv->dev), count, *pos);
4dc955f7
MK		 1046 if (ret)
1047 return ret;
edc3d884 1048
fc16b48b 1049 ret = i915_error_state_to_str(&error_str, error_priv);
edc3d884
MK		 1050 if (ret)
1051 goto out;
1052
edc3d884
MK		 1053 ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
1054 error_str.buf,
1055 error_str.bytes);
1056
1057 if (ret_count < 0)
1058 ret = ret_count;
1059 else
1060 *pos = error_str.start + ret_count;
1061out:
4dc955f7 1062 i915_error_state_buf_release(&error_str);
edc3d884 1063 return ret ?: ret_count;
d5442303
DV		 1064}
1065
1066static const struct file_operations i915_error_state_fops = {
1067 .owner = THIS_MODULE,
1068 .open = i915_error_state_open,
edc3d884 1069 .read = i915_error_state_read,
d5442303
DV		 1070 .write = i915_error_state_write,
1071 .llseek = default_llseek,
1072 .release = i915_error_state_release,
1073};
1074
647416f9
KC		 1075static int
1076i915_next_seqno_get(void *data, u64 *val)
40633219 1077{
647416f9 1078 struct drm_device *dev = data;
e277a1f8 1079 struct drm_i915_private *dev_priv = dev->dev_private;
40633219
MK		 1080 int ret;
1081
1082 ret = mutex_lock_interruptible(&dev->struct_mutex);
1083 if (ret)
1084 return ret;
1085
647416f9 1086 *val = dev_priv->next_seqno;
40633219
MK		 1087 mutex_unlock(&dev->struct_mutex);
1088
647416f9 1089 return 0;
40633219
MK		 1090}
1091
647416f9
KC		 1092static int
1093i915_next_seqno_set(void *data, u64 val)
1094{
1095 struct drm_device *dev = data;
40633219
MK		 1096 int ret;
1097
40633219
MK		 1098 ret = mutex_lock_interruptible(&dev->struct_mutex);
1099 if (ret)
1100 return ret;
1101
e94fbaa8 1102 ret = i915_gem_set_seqno(dev, val);
40633219
MK		 1103 mutex_unlock(&dev->struct_mutex);
1104
647416f9 1105 return ret;
40633219
MK		 1106}
1107
647416f9
KC		 1108DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
1109 i915_next_seqno_get, i915_next_seqno_set,
3a3b4f98 1110 "0x%llx\n");
40633219 1111
adb4bd12 1112static int i915_frequency_info(struct seq_file *m, void *unused)
f97108d1 1113{
9f25d007 1114 struct drm_info_node *node = m->private;
f97108d1 1115 struct drm_device *dev = node->minor->dev;
e277a1f8 1116 struct drm_i915_private *dev_priv = dev->dev_private;
c8c8fb33
PZ		 1117 int ret = 0;
1118
1119 intel_runtime_pm_get(dev_priv);
3b8d8d91 1120
5c9669ce
TR		 1121 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1122
3b8d8d91
JB		 1123 if (IS_GEN5(dev)) {
1124 u16 rgvswctl = I915_READ16(MEMSWCTL);
1125 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1126
1127 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1128 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1129 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1130 MEMSTAT_VID_SHIFT);
1131 seq_printf(m, "Current P-state: %d\n",
1132 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
daa3afb2 1133 } else if (IS_GEN6(dev) || (IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) ||
60260a5b 1134 IS_BROADWELL(dev) || IS_GEN9(dev)) {
3b8d8d91
JB		 1135 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1136 u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1137 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
0d8f9491 1138 u32 rpmodectl, rpinclimit, rpdeclimit;
8e8c06cd 1139 u32 rpstat, cagf, reqf;
ccab5c82
JB		 1140 u32 rpupei, rpcurup, rpprevup;
1141 u32 rpdownei, rpcurdown, rpprevdown;
9dd3c605 1142 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
3b8d8d91
JB		 1143 int max_freq;
1144
1145 /* RPSTAT1 is in the GT power well */
d1ebd816
BW		 1146 ret = mutex_lock_interruptible(&dev->struct_mutex);
1147 if (ret)
c8c8fb33 1148 goto out;
d1ebd816 1149
59bad947 1150 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
3b8d8d91 1151
8e8c06cd 1152 reqf = I915_READ(GEN6_RPNSWREQ);
60260a5b
AG		 1153 if (IS_GEN9(dev))
1154 reqf >>= 23;
1155 else {
1156 reqf &= ~GEN6_TURBO_DISABLE;
1157 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1158 reqf >>= 24;
1159 else
1160 reqf >>= 25;
1161 }
7c59a9c1 1162 reqf = intel_gpu_freq(dev_priv, reqf);
8e8c06cd 1163
0d8f9491
CW		 1164 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1165 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1166 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1167
ccab5c82
JB		 1168 rpstat = I915_READ(GEN6_RPSTAT1);
1169 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
1170 rpcurup = I915_READ(GEN6_RP_CUR_UP);
1171 rpprevup = I915_READ(GEN6_RP_PREV_UP);
1172 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
1173 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
1174 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
60260a5b
AG		 1175 if (IS_GEN9(dev))
1176 cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
1177 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
f82855d3
BW		 1178 cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1179 else
1180 cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
7c59a9c1 1181 cagf = intel_gpu_freq(dev_priv, cagf);
ccab5c82 1182
59bad947 1183 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
d1ebd816
BW		 1184 mutex_unlock(&dev->struct_mutex);
1185
9dd3c605
PZ		 1186 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1187 pm_ier = I915_READ(GEN6_PMIER);
1188 pm_imr = I915_READ(GEN6_PMIMR);
1189 pm_isr = I915_READ(GEN6_PMISR);
1190 pm_iir = I915_READ(GEN6_PMIIR);
1191 pm_mask = I915_READ(GEN6_PMINTRMSK);
1192 } else {
1193 pm_ier = I915_READ(GEN8_GT_IER(2));
1194 pm_imr = I915_READ(GEN8_GT_IMR(2));
1195 pm_isr = I915_READ(GEN8_GT_ISR(2));
1196 pm_iir = I915_READ(GEN8_GT_IIR(2));
1197 pm_mask = I915_READ(GEN6_PMINTRMSK);
1198 }
0d8f9491 1199 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
9dd3c605 1200 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
3b8d8d91 1201 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
3b8d8d91 1202 seq_printf(m, "Render p-state ratio: %d\n",
60260a5b 1203 (gt_perf_status & (IS_GEN9(dev) ? 0x1ff00 : 0xff00)) >> 8);
3b8d8d91
JB		 1204 seq_printf(m, "Render p-state VID: %d\n",
1205 gt_perf_status & 0xff);
1206 seq_printf(m, "Render p-state limit: %d\n",
1207 rp_state_limits & 0xff);
0d8f9491
CW		 1208 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1209 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1210 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1211 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
8e8c06cd 1212 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
f82855d3 1213 seq_printf(m, "CAGF: %dMHz\n", cagf);
ccab5c82
JB		 1214 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
1215 GEN6_CURICONT_MASK);
1216 seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
1217 GEN6_CURBSYTAVG_MASK);
1218 seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
1219 GEN6_CURBSYTAVG_MASK);
d86ed34a
CW		 1220 seq_printf(m, "Up threshold: %d%%\n",
1221 dev_priv->rps.up_threshold);
1222
ccab5c82
JB		 1223 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
1224 GEN6_CURIAVG_MASK);
1225 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
1226 GEN6_CURBSYTAVG_MASK);
1227 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
1228 GEN6_CURBSYTAVG_MASK);
d86ed34a
CW		 1229 seq_printf(m, "Down threshold: %d%%\n",
1230 dev_priv->rps.down_threshold);
3b8d8d91
JB		 1231
1232 max_freq = (rp_state_cap & 0xff0000) >> 16;
60260a5b 1233 max_freq *= (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1);
3b8d8d91 1234 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
7c59a9c1 1235 intel_gpu_freq(dev_priv, max_freq));
3b8d8d91
JB		 1236
1237 max_freq = (rp_state_cap & 0xff00) >> 8;
60260a5b 1238 max_freq *= (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1);
3b8d8d91 1239 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
7c59a9c1 1240 intel_gpu_freq(dev_priv, max_freq));
3b8d8d91
JB		 1241
1242 max_freq = rp_state_cap & 0xff;
60260a5b 1243 max_freq *= (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1);
3b8d8d91 1244 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
7c59a9c1 1245 intel_gpu_freq(dev_priv, max_freq));
31c77388 1246 seq_printf(m, "Max overclocked frequency: %dMHz\n",
7c59a9c1 1247 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
aed242ff 1248
d86ed34a
CW		 1249 seq_printf(m, "Current freq: %d MHz\n",
1250 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1251 seq_printf(m, "Actual freq: %d MHz\n", cagf);
aed242ff
CW		 1252 seq_printf(m, "Idle freq: %d MHz\n",
1253 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
d86ed34a
CW		 1254 seq_printf(m, "Min freq: %d MHz\n",
1255 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1256 seq_printf(m, "Max freq: %d MHz\n",
1257 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1258 seq_printf(m,
1259 "efficient (RPe) frequency: %d MHz\n",
1260 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
0a073b84 1261 } else if (IS_VALLEYVIEW(dev)) {
03af2045 1262 u32 freq_sts;
0a073b84 1263
259bd5d4 1264 mutex_lock(&dev_priv->rps.hw_lock);
64936258 1265 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
0a073b84
JB		 1266 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1267 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1268
d86ed34a
CW		 1269 seq_printf(m, "actual GPU freq: %d MHz\n",
1270 intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
1271
1272 seq_printf(m, "current GPU freq: %d MHz\n",
1273 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1274
0a073b84 1275 seq_printf(m, "max GPU freq: %d MHz\n",
7c59a9c1 1276 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
0a073b84 1277
0a073b84 1278 seq_printf(m, "min GPU freq: %d MHz\n",
7c59a9c1 1279 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
03af2045 1280
aed242ff
CW		 1281 seq_printf(m, "idle GPU freq: %d MHz\n",
1282 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1283
7c59a9c1
VS		 1284 seq_printf(m,
1285 "efficient (RPe) frequency: %d MHz\n",
1286 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
259bd5d4 1287 mutex_unlock(&dev_priv->rps.hw_lock);
3b8d8d91 1288 } else {
267f0c90 1289 seq_puts(m, "no P-state info available\n");
3b8d8d91 1290 }
f97108d1 1291
c8c8fb33
PZ		 1292out:
1293 intel_runtime_pm_put(dev_priv);
1294 return ret;
f97108d1
JB		 1295}
1296
f654449a
CW		 1297static int i915_hangcheck_info(struct seq_file *m, void *unused)
1298{
1299 struct drm_info_node *node = m->private;
ebbc7546
MK		 1300 struct drm_device *dev = node->minor->dev;
1301 struct drm_i915_private *dev_priv = dev->dev_private;
f654449a 1302 struct intel_engine_cs *ring;
ebbc7546
MK		 1303 u64 acthd[I915_NUM_RINGS];
1304 u32 seqno[I915_NUM_RINGS];
f654449a
CW		 1305 int i;
1306
1307 if (!i915.enable_hangcheck) {
1308 seq_printf(m, "Hangcheck disabled\n");
1309 return 0;
1310 }
1311
ebbc7546
MK		 1312 intel_runtime_pm_get(dev_priv);
1313
1314 for_each_ring(ring, dev_priv, i) {
1315 seqno[i] = ring->get_seqno(ring, false);
1316 acthd[i] = intel_ring_get_active_head(ring);
1317 }
1318
1319 intel_runtime_pm_put(dev_priv);
1320
f654449a
CW		 1321 if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) {
1322 seq_printf(m, "Hangcheck active, fires in %dms\n",
1323 jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires -
1324 jiffies));
1325 } else
1326 seq_printf(m, "Hangcheck inactive\n");
1327
1328 for_each_ring(ring, dev_priv, i) {
1329 seq_printf(m, "%s:\n", ring->name);
1330 seq_printf(m, "\tseqno = %x [current %x]\n",
ebbc7546 1331 ring->hangcheck.seqno, seqno[i]);
f654449a
CW		 1332 seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
1333 (long long)ring->hangcheck.acthd,
ebbc7546 1334 (long long)acthd[i]);
f654449a
CW		 1335 seq_printf(m, "\tmax ACTHD = 0x%08llx\n",
1336 (long long)ring->hangcheck.max_acthd);
ebbc7546
MK		 1337 seq_printf(m, "\tscore = %d\n", ring->hangcheck.score);
1338 seq_printf(m, "\taction = %d\n", ring->hangcheck.action);
f654449a
CW		 1339 }
1340
1341 return 0;
1342}
1343
4d85529d 1344static int ironlake_drpc_info(struct seq_file *m)
f97108d1 1345{
9f25d007 1346 struct drm_info_node *node = m->private;
f97108d1 1347 struct drm_device *dev = node->minor->dev;
e277a1f8 1348 struct drm_i915_private *dev_priv = dev->dev_private;
616fdb5a
BW		 1349 u32 rgvmodectl, rstdbyctl;
1350 u16 crstandvid;
1351 int ret;
1352
1353 ret = mutex_lock_interruptible(&dev->struct_mutex);
1354 if (ret)
1355 return ret;
c8c8fb33 1356 intel_runtime_pm_get(dev_priv);
616fdb5a
BW		 1357
1358 rgvmodectl = I915_READ(MEMMODECTL);
1359 rstdbyctl = I915_READ(RSTDBYCTL);
1360 crstandvid = I915_READ16(CRSTANDVID);
1361
c8c8fb33 1362 intel_runtime_pm_put(dev_priv);
616fdb5a 1363 mutex_unlock(&dev->struct_mutex);
f97108d1
JB		 1364
1365 seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
1366 "yes" : "no");
1367 seq_printf(m, "Boost freq: %d\n",
1368 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1369 MEMMODE_BOOST_FREQ_SHIFT);
1370 seq_printf(m, "HW control enabled: %s\n",
1371 rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");
1372 seq_printf(m, "SW control enabled: %s\n",
1373 rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");
1374 seq_printf(m, "Gated voltage change: %s\n",
1375 rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");
1376 seq_printf(m, "Starting frequency: P%d\n",
1377 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
7648fa99 1378 seq_printf(m, "Max P-state: P%d\n",
f97108d1 1379 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
7648fa99
JB		 1380 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1381 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1382 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1383 seq_printf(m, "Render standby enabled: %s\n",
1384 (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes");
267f0c90 1385 seq_puts(m, "Current RS state: ");
88271da3
JB		 1386 switch (rstdbyctl & RSX_STATUS_MASK) {
1387 case RSX_STATUS_ON:
267f0c90 1388 seq_puts(m, "on\n");
88271da3
JB		 1389 break;
1390 case RSX_STATUS_RC1:
267f0c90 1391 seq_puts(m, "RC1\n");
88271da3
JB		 1392 break;
1393 case RSX_STATUS_RC1E:
267f0c90 1394 seq_puts(m, "RC1E\n");
88271da3
JB		 1395 break;
1396 case RSX_STATUS_RS1:
267f0c90 1397 seq_puts(m, "RS1\n");
88271da3
JB		 1398 break;
1399 case RSX_STATUS_RS2:
267f0c90 1400 seq_puts(m, "RS2 (RC6)\n");
88271da3
JB		 1401 break;
1402 case RSX_STATUS_RS3:
267f0c90 1403 seq_puts(m, "RC3 (RC6+)\n");
88271da3
JB		 1404 break;
1405 default:
267f0c90 1406 seq_puts(m, "unknown\n");
88271da3
JB		 1407 break;
1408 }
f97108d1
JB		 1409
1410 return 0;
1411}
1412
f65367b5 1413static int i915_forcewake_domains(struct seq_file *m, void *data)
669ab5aa 1414{
b2cff0db
CW		 1415 struct drm_info_node *node = m->private;
1416 struct drm_device *dev = node->minor->dev;
1417 struct drm_i915_private *dev_priv = dev->dev_private;
1418 struct intel_uncore_forcewake_domain *fw_domain;
b2cff0db
CW		 1419 int i;
1420
1421 spin_lock_irq(&dev_priv->uncore.lock);
1422 for_each_fw_domain(fw_domain, dev_priv, i) {
1423 seq_printf(m, "%s.wake_count = %u\n",
05a2fb15 1424 intel_uncore_forcewake_domain_to_str(i),
b2cff0db
CW		 1425 fw_domain->wake_count);
1426 }
1427 spin_unlock_irq(&dev_priv->uncore.lock);
669ab5aa 1428
b2cff0db
CW		 1429 return 0;
1430}
1431
1432static int vlv_drpc_info(struct seq_file *m)
1433{
9f25d007 1434 struct drm_info_node *node = m->private;
669ab5aa
D		 1435 struct drm_device *dev = node->minor->dev;
1436 struct drm_i915_private *dev_priv = dev->dev_private;
6b312cd3 1437 u32 rpmodectl1, rcctl1, pw_status;
669ab5aa 1438
d46c0517
ID		 1439 intel_runtime_pm_get(dev_priv);
1440
6b312cd3 1441 pw_status = I915_READ(VLV_GTLC_PW_STATUS);
669ab5aa
D		 1442 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1443 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1444
d46c0517
ID		 1445 intel_runtime_pm_put(dev_priv);
1446
669ab5aa
D		 1447 seq_printf(m, "Video Turbo Mode: %s\n",
1448 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1449 seq_printf(m, "Turbo enabled: %s\n",
1450 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1451 seq_printf(m, "HW control enabled: %s\n",
1452 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1453 seq_printf(m, "SW control enabled: %s\n",
1454 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1455 GEN6_RP_MEDIA_SW_MODE));
1456 seq_printf(m, "RC6 Enabled: %s\n",
1457 yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1458 GEN6_RC_CTL_EI_MODE(1))));
1459 seq_printf(m, "Render Power Well: %s\n",
6b312cd3 1460 (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
669ab5aa 1461 seq_printf(m, "Media Power Well: %s\n",
6b312cd3 1462 (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
669ab5aa 1463
9cc19be5
ID		 1464 seq_printf(m, "Render RC6 residency since boot: %u\n",
1465 I915_READ(VLV_GT_RENDER_RC6));
1466 seq_printf(m, "Media RC6 residency since boot: %u\n",
1467 I915_READ(VLV_GT_MEDIA_RC6));
1468
f65367b5 1469 return i915_forcewake_domains(m, NULL);
669ab5aa
D		 1470}
1471
4d85529d
BW		 1472static int gen6_drpc_info(struct seq_file *m)
1473{
9f25d007 1474 struct drm_info_node *node = m->private;
4d85529d
BW		 1475 struct drm_device *dev = node->minor->dev;
1476 struct drm_i915_private *dev_priv = dev->dev_private;
ecd8faea 1477 u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
93b525dc 1478 unsigned forcewake_count;
aee56cff 1479 int count = 0, ret;
4d85529d
BW		 1480
1481 ret = mutex_lock_interruptible(&dev->struct_mutex);
1482 if (ret)
1483 return ret;
c8c8fb33 1484 intel_runtime_pm_get(dev_priv);
4d85529d 1485
907b28c5 1486 spin_lock_irq(&dev_priv->uncore.lock);
b2cff0db 1487 forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count;
907b28c5 1488 spin_unlock_irq(&dev_priv->uncore.lock);
93b525dc
DV		 1489
1490 if (forcewake_count) {
267f0c90
DL		 1491 seq_puts(m, "RC information inaccurate because somebody "
1492 "holds a forcewake reference \n");
4d85529d
BW		 1493 } else {
1494 /* NB: we cannot use forcewake, else we read the wrong values */
1495 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1496 udelay(10);
1497 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1498 }
1499
1500 gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS);
ed71f1b4 1501 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
4d85529d
BW		 1502
1503 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1504 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1505 mutex_unlock(&dev->struct_mutex);
44cbd338
BW		 1506 mutex_lock(&dev_priv->rps.hw_lock);
1507 sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1508 mutex_unlock(&dev_priv->rps.hw_lock);
4d85529d 1509
c8c8fb33
PZ		 1510 intel_runtime_pm_put(dev_priv);
1511
4d85529d
BW		 1512 seq_printf(m, "Video Turbo Mode: %s\n",
1513 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1514 seq_printf(m, "HW control enabled: %s\n",
1515 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1516 seq_printf(m, "SW control enabled: %s\n",
1517 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1518 GEN6_RP_MEDIA_SW_MODE));
fff24e21 1519 seq_printf(m, "RC1e Enabled: %s\n",
4d85529d
BW		 1520 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1521 seq_printf(m, "RC6 Enabled: %s\n",
1522 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1523 seq_printf(m, "Deep RC6 Enabled: %s\n",
1524 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1525 seq_printf(m, "Deepest RC6 Enabled: %s\n",
1526 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
267f0c90 1527 seq_puts(m, "Current RC state: ");
4d85529d
BW		 1528 switch (gt_core_status & GEN6_RCn_MASK) {
1529 case GEN6_RC0:
1530 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
267f0c90 1531 seq_puts(m, "Core Power Down\n");
4d85529d 1532 else
267f0c90 1533 seq_puts(m, "on\n");
4d85529d
BW		 1534 break;
1535 case GEN6_RC3:
267f0c90 1536 seq_puts(m, "RC3\n");
4d85529d
BW		 1537 break;
1538 case GEN6_RC6:
267f0c90 1539 seq_puts(m, "RC6\n");
4d85529d
BW		 1540 break;
1541 case GEN6_RC7:
267f0c90 1542 seq_puts(m, "RC7\n");
4d85529d
BW		 1543 break;
1544 default:
267f0c90 1545 seq_puts(m, "Unknown\n");
4d85529d
BW		 1546 break;
1547 }
1548
1549 seq_printf(m, "Core Power Down: %s\n",
1550 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
cce66a28
BW		 1551
1552 /* Not exactly sure what this is */
1553 seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1554 I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1555 seq_printf(m, "RC6 residency since boot: %u\n",
1556 I915_READ(GEN6_GT_GFX_RC6));
1557 seq_printf(m, "RC6+ residency since boot: %u\n",
1558 I915_READ(GEN6_GT_GFX_RC6p));
1559 seq_printf(m, "RC6++ residency since boot: %u\n",
1560 I915_READ(GEN6_GT_GFX_RC6pp));
1561
ecd8faea
BW		 1562 seq_printf(m, "RC6 voltage: %dmV\n",
1563 GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1564 seq_printf(m, "RC6+ voltage: %dmV\n",
1565 GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1566 seq_printf(m, "RC6++ voltage: %dmV\n",
1567 GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
4d85529d
BW		 1568 return 0;
1569}
1570
1571static int i915_drpc_info(struct seq_file *m, void *unused)
1572{
9f25d007 1573 struct drm_info_node *node = m->private;
4d85529d
BW		 1574 struct drm_device *dev = node->minor->dev;
1575
669ab5aa
D		 1576 if (IS_VALLEYVIEW(dev))
1577 return vlv_drpc_info(m);
ac66cf4b 1578 else if (INTEL_INFO(dev)->gen >= 6)
4d85529d
BW		 1579 return gen6_drpc_info(m);
1580 else
1581 return ironlake_drpc_info(m);
1582}
1583
b5e50c3f
JB		 1584static int i915_fbc_status(struct seq_file *m, void *unused)
1585{
9f25d007 1586 struct drm_info_node *node = m->private;
b5e50c3f 1587 struct drm_device *dev = node->minor->dev;
e277a1f8 1588 struct drm_i915_private *dev_priv = dev->dev_private;
b5e50c3f 1589
3a77c4c4 1590 if (!HAS_FBC(dev)) {
267f0c90 1591 seq_puts(m, "FBC unsupported on this chipset\n");
b5e50c3f
JB		 1592 return 0;
1593 }
1594
36623ef8
PZ		 1595 intel_runtime_pm_get(dev_priv);
1596
ee5382ae 1597 if (intel_fbc_enabled(dev)) {
267f0c90 1598 seq_puts(m, "FBC enabled\n");
b5e50c3f 1599 } else {
267f0c90 1600 seq_puts(m, "FBC disabled: ");
5c3fe8b0 1601 switch (dev_priv->fbc.no_fbc_reason) {
29ebf90f
CW		 1602 case FBC_OK:
1603 seq_puts(m, "FBC actived, but currently disabled in hardware");
1604 break;
1605 case FBC_UNSUPPORTED:
1606 seq_puts(m, "unsupported by this chipset");
1607 break;
bed4a673 1608 case FBC_NO_OUTPUT:
267f0c90 1609 seq_puts(m, "no outputs");
bed4a673 1610 break;
b5e50c3f 1611 case FBC_STOLEN_TOO_SMALL:
267f0c90 1612 seq_puts(m, "not enough stolen memory");
b5e50c3f
JB		 1613 break;
1614 case FBC_UNSUPPORTED_MODE:
267f0c90 1615 seq_puts(m, "mode not supported");
b5e50c3f
JB		 1616 break;
1617 case FBC_MODE_TOO_LARGE:
267f0c90 1618 seq_puts(m, "mode too large");
b5e50c3f
JB		 1619 break;
1620 case FBC_BAD_PLANE:
267f0c90 1621 seq_puts(m, "FBC unsupported on plane");
b5e50c3f
JB		 1622 break;
1623 case FBC_NOT_TILED:
267f0c90 1624 seq_puts(m, "scanout buffer not tiled");
b5e50c3f 1625 break;
9c928d16 1626 case FBC_MULTIPLE_PIPES:
267f0c90 1627 seq_puts(m, "multiple pipes are enabled");
9c928d16 1628 break;
c1a9f047 1629 case FBC_MODULE_PARAM:
267f0c90 1630 seq_puts(m, "disabled per module param (default off)");
c1a9f047 1631 break;
8a5729a3 1632 case FBC_CHIP_DEFAULT:
267f0c90 1633 seq_puts(m, "disabled per chip default");
8a5729a3 1634 break;
b5e50c3f 1635 default:
267f0c90 1636 seq_puts(m, "unknown reason");
b5e50c3f 1637 }
267f0c90 1638 seq_putc(m, '\n');
b5e50c3f 1639 }
36623ef8
PZ		 1640
1641 intel_runtime_pm_put(dev_priv);
1642
b5e50c3f
JB		 1643 return 0;
1644}
1645
da46f936
RV		 1646static int i915_fbc_fc_get(void *data, u64 *val)
1647{
1648 struct drm_device *dev = data;
1649 struct drm_i915_private *dev_priv = dev->dev_private;
1650
1651 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1652 return -ENODEV;
1653
1654 drm_modeset_lock_all(dev);
1655 *val = dev_priv->fbc.false_color;
1656 drm_modeset_unlock_all(dev);
1657
1658 return 0;
1659}
1660
1661static int i915_fbc_fc_set(void *data, u64 val)
1662{
1663 struct drm_device *dev = data;
1664 struct drm_i915_private *dev_priv = dev->dev_private;
1665 u32 reg;
1666
1667 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1668 return -ENODEV;
1669
1670 drm_modeset_lock_all(dev);
1671
1672 reg = I915_READ(ILK_DPFC_CONTROL);
1673 dev_priv->fbc.false_color = val;
1674
1675 I915_WRITE(ILK_DPFC_CONTROL, val ?
1676 (reg | FBC_CTL_FALSE_COLOR) :
1677 (reg & ~FBC_CTL_FALSE_COLOR));
1678
1679 drm_modeset_unlock_all(dev);
1680 return 0;
1681}
1682
1683DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops,
1684 i915_fbc_fc_get, i915_fbc_fc_set,
1685 "%llu\n");
1686
92d44621
PZ		 1687static int i915_ips_status(struct seq_file *m, void *unused)
1688{
9f25d007 1689 struct drm_info_node *node = m->private;
92d44621
PZ		 1690 struct drm_device *dev = node->minor->dev;
1691 struct drm_i915_private *dev_priv = dev->dev_private;
1692
f5adf94e 1693 if (!HAS_IPS(dev)) {
92d44621
PZ		 1694 seq_puts(m, "not supported\n");
1695 return 0;
1696 }
1697
36623ef8
PZ		 1698 intel_runtime_pm_get(dev_priv);
1699
0eaa53f0
RV		 1700 seq_printf(m, "Enabled by kernel parameter: %s\n",
1701 yesno(i915.enable_ips));
1702
1703 if (INTEL_INFO(dev)->gen >= 8) {
1704 seq_puts(m, "Currently: unknown\n");
1705 } else {
1706 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1707 seq_puts(m, "Currently: enabled\n");
1708 else
1709 seq_puts(m, "Currently: disabled\n");
1710 }
92d44621 1711
36623ef8
PZ		 1712 intel_runtime_pm_put(dev_priv);
1713
92d44621
PZ		 1714 return 0;
1715}
1716
4a9bef37
JB		 1717static int i915_sr_status(struct seq_file *m, void *unused)
1718{
9f25d007 1719 struct drm_info_node *node = m->private;
4a9bef37 1720 struct drm_device *dev = node->minor->dev;
e277a1f8 1721 struct drm_i915_private *dev_priv = dev->dev_private;
4a9bef37
JB		 1722 bool sr_enabled = false;
1723
36623ef8
PZ		 1724 intel_runtime_pm_get(dev_priv);
1725
1398261a 1726 if (HAS_PCH_SPLIT(dev))
5ba2aaaa 1727 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
a6c45cf0 1728 else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))
4a9bef37
JB		 1729 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1730 else if (IS_I915GM(dev))
1731 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1732 else if (IS_PINEVIEW(dev))
1733 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1734
36623ef8
PZ		 1735 intel_runtime_pm_put(dev_priv);
1736
5ba2aaaa
CW		 1737 seq_printf(m, "self-refresh: %s\n",
1738 sr_enabled ? "enabled" : "disabled");
4a9bef37
JB		 1739
1740 return 0;
1741}
1742
7648fa99
JB		 1743static int i915_emon_status(struct seq_file *m, void *unused)
1744{
9f25d007 1745 struct drm_info_node *node = m->private;
7648fa99 1746 struct drm_device *dev = node->minor->dev;
e277a1f8 1747 struct drm_i915_private *dev_priv = dev->dev_private;
7648fa99 1748 unsigned long temp, chipset, gfx;
de227ef0
CW		 1749 int ret;
1750
582be6b4
CW		 1751 if (!IS_GEN5(dev))
1752 return -ENODEV;
1753
de227ef0
CW		 1754 ret = mutex_lock_interruptible(&dev->struct_mutex);
1755 if (ret)
1756 return ret;
7648fa99
JB		 1757
1758 temp = i915_mch_val(dev_priv);
1759 chipset = i915_chipset_val(dev_priv);
1760 gfx = i915_gfx_val(dev_priv);
de227ef0 1761 mutex_unlock(&dev->struct_mutex);
7648fa99
JB		 1762
1763 seq_printf(m, "GMCH temp: %ld\n", temp);
1764 seq_printf(m, "Chipset power: %ld\n", chipset);
1765 seq_printf(m, "GFX power: %ld\n", gfx);
1766 seq_printf(m, "Total power: %ld\n", chipset + gfx);
1767
1768 return 0;
1769}
1770
23b2f8bb
JB		 1771static int i915_ring_freq_table(struct seq_file *m, void *unused)
1772{
9f25d007 1773 struct drm_info_node *node = m->private;
23b2f8bb 1774 struct drm_device *dev = node->minor->dev;
e277a1f8 1775 struct drm_i915_private *dev_priv = dev->dev_private;
5bfa0199 1776 int ret = 0;
23b2f8bb
JB		 1777 int gpu_freq, ia_freq;
1778
1c70c0ce 1779 if (!(IS_GEN6(dev) || IS_GEN7(dev))) {
267f0c90 1780 seq_puts(m, "unsupported on this chipset\n");
23b2f8bb
JB		 1781 return 0;
1782 }
1783
5bfa0199
PZ		 1784 intel_runtime_pm_get(dev_priv);
1785
5c9669ce
TR		 1786 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1787
4fc688ce 1788 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
23b2f8bb 1789 if (ret)
5bfa0199 1790 goto out;
23b2f8bb 1791
267f0c90 1792 seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
23b2f8bb 1793
b39fb297
BW		 1794 for (gpu_freq = dev_priv->rps.min_freq_softlimit;
1795 gpu_freq <= dev_priv->rps.max_freq_softlimit;
23b2f8bb 1796 gpu_freq++) {
42c0526c
BW		 1797 ia_freq = gpu_freq;
1798 sandybridge_pcode_read(dev_priv,
1799 GEN6_PCODE_READ_MIN_FREQ_TABLE,
1800 &ia_freq);
3ebecd07 1801 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
7c59a9c1 1802 intel_gpu_freq(dev_priv, gpu_freq),
3ebecd07
CW		 1803 ((ia_freq >> 0) & 0xff) * 100,
1804 ((ia_freq >> 8) & 0xff) * 100);
23b2f8bb
JB		 1805 }
1806
4fc688ce 1807 mutex_unlock(&dev_priv->rps.hw_lock);
23b2f8bb 1808
5bfa0199
PZ		 1809out:
1810 intel_runtime_pm_put(dev_priv);
1811 return ret;
23b2f8bb
JB		 1812}
1813
44834a67
CW		 1814static int i915_opregion(struct seq_file *m, void *unused)
1815{
9f25d007 1816 struct drm_info_node *node = m->private;
44834a67 1817 struct drm_device *dev = node->minor->dev;
e277a1f8 1818 struct drm_i915_private *dev_priv = dev->dev_private;
44834a67 1819 struct intel_opregion *opregion = &dev_priv->opregion;
0d38f009 1820 void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL);
44834a67
CW		 1821 int ret;
1822
0d38f009
DV		 1823 if (data == NULL)
1824 return -ENOMEM;
1825
44834a67
CW		 1826 ret = mutex_lock_interruptible(&dev->struct_mutex);
1827 if (ret)
0d38f009 1828 goto out;
44834a67 1829
0d38f009
DV		 1830 if (opregion->header) {
1831 memcpy_fromio(data, opregion->header, OPREGION_SIZE);
1832 seq_write(m, data, OPREGION_SIZE);
1833 }
44834a67
CW		 1834
1835 mutex_unlock(&dev->struct_mutex);
1836
0d38f009
DV		 1837out:
1838 kfree(data);
44834a67
CW		 1839 return 0;
1840}
1841
37811fcc
CW		 1842static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1843{
9f25d007 1844 struct drm_info_node *node = m->private;
37811fcc 1845 struct drm_device *dev = node->minor->dev;
4520f53a 1846 struct intel_fbdev *ifbdev = NULL;
37811fcc 1847 struct intel_framebuffer *fb;
37811fcc 1848
4520f53a
DV		 1849#ifdef CONFIG_DRM_I915_FBDEV
1850 struct drm_i915_private *dev_priv = dev->dev_private;
37811fcc
CW		 1851
1852 ifbdev = dev_priv->fbdev;
1853 fb = to_intel_framebuffer(ifbdev->helper.fb);
1854
c1ca506d 1855 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
37811fcc
CW		 1856 fb->base.width,
1857 fb->base.height,
1858 fb->base.depth,
623f9783 1859 fb->base.bits_per_pixel,
c1ca506d 1860 fb->base.modifier[0],
623f9783 1861 atomic_read(&fb->base.refcount.refcount));
05394f39 1862 describe_obj(m, fb->obj);
267f0c90 1863 seq_putc(m, '\n');
4520f53a 1864#endif
37811fcc 1865
4b096ac1 1866 mutex_lock(&dev->mode_config.fb_lock);
37811fcc 1867 list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) {
131a56dc 1868 if (ifbdev && &fb->base == ifbdev->helper.fb)
37811fcc
CW		 1869 continue;
1870
c1ca506d 1871 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
37811fcc
CW		 1872 fb->base.width,
1873 fb->base.height,
1874 fb->base.depth,
623f9783 1875 fb->base.bits_per_pixel,
c1ca506d 1876 fb->base.modifier[0],
623f9783 1877 atomic_read(&fb->base.refcount.refcount));
05394f39 1878 describe_obj(m, fb->obj);
267f0c90 1879 seq_putc(m, '\n');
37811fcc 1880 }
4b096ac1 1881 mutex_unlock(&dev->mode_config.fb_lock);
37811fcc
CW		 1882
1883 return 0;
1884}
1885
c9fe99bd
OM		 1886static void describe_ctx_ringbuf(struct seq_file *m,
1887 struct intel_ringbuffer *ringbuf)
1888{
1889 seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
1890 ringbuf->space, ringbuf->head, ringbuf->tail,
1891 ringbuf->last_retired_head);
1892}
1893
e76d3630
BW		 1894static int i915_context_status(struct seq_file *m, void *unused)
1895{
9f25d007 1896 struct drm_info_node *node = m->private;
e76d3630 1897 struct drm_device *dev = node->minor->dev;
e277a1f8 1898 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 1899 struct intel_engine_cs *ring;
273497e5 1900 struct intel_context *ctx;
a168c293 1901 int ret, i;
e76d3630 1902
f3d28878 1903 ret = mutex_lock_interruptible(&dev->struct_mutex);
e76d3630
BW		 1904 if (ret)
1905 return ret;
1906
a33afea5 1907 list_for_each_entry(ctx, &dev_priv->context_list, link) {
c9fe99bd
OM		 1908 if (!i915.enable_execlists &&
1909 ctx->legacy_hw_ctx.rcs_state == NULL)
b77f6997
CW		 1910 continue;
1911
a33afea5 1912 seq_puts(m, "HW context ");
3ccfd19d 1913 describe_ctx(m, ctx);
c9fe99bd 1914 for_each_ring(ring, dev_priv, i) {
a33afea5 1915 if (ring->default_context == ctx)
c9fe99bd
OM		 1916 seq_printf(m, "(default context %s) ",
1917 ring->name);
1918 }
1919
1920 if (i915.enable_execlists) {
1921 seq_putc(m, '\n');
1922 for_each_ring(ring, dev_priv, i) {
1923 struct drm_i915_gem_object *ctx_obj =
1924 ctx->engine[i].state;
1925 struct intel_ringbuffer *ringbuf =
1926 ctx->engine[i].ringbuf;
1927
1928 seq_printf(m, "%s: ", ring->name);
1929 if (ctx_obj)
1930 describe_obj(m, ctx_obj);
1931 if (ringbuf)
1932 describe_ctx_ringbuf(m, ringbuf);
1933 seq_putc(m, '\n');
1934 }
1935 } else {
1936 describe_obj(m, ctx->legacy_hw_ctx.rcs_state);
1937 }
a33afea5 1938
a33afea5 1939 seq_putc(m, '\n');
a168c293
BW		 1940 }
1941
f3d28878 1942 mutex_unlock(&dev->struct_mutex);
e76d3630
BW		 1943
1944 return 0;
1945}
1946
064ca1d2
TD		 1947static void i915_dump_lrc_obj(struct seq_file *m,
1948 struct intel_engine_cs *ring,
1949 struct drm_i915_gem_object *ctx_obj)
1950{
1951 struct page *page;
1952 uint32_t *reg_state;
1953 int j;
1954 unsigned long ggtt_offset = 0;
1955
1956 if (ctx_obj == NULL) {
1957 seq_printf(m, "Context on %s with no gem object\n",
1958 ring->name);
1959 return;
1960 }
1961
1962 seq_printf(m, "CONTEXT: %s %u\n", ring->name,
1963 intel_execlists_ctx_id(ctx_obj));
1964
1965 if (!i915_gem_obj_ggtt_bound(ctx_obj))
1966 seq_puts(m, "\tNot bound in GGTT\n");
1967 else
1968 ggtt_offset = i915_gem_obj_ggtt_offset(ctx_obj);
1969
1970 if (i915_gem_object_get_pages(ctx_obj)) {
1971 seq_puts(m, "\tFailed to get pages for context object\n");
1972 return;
1973 }
1974
1975 page = i915_gem_object_get_page(ctx_obj, 1);
1976 if (!WARN_ON(page == NULL)) {
1977 reg_state = kmap_atomic(page);
1978
1979 for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
1980 seq_printf(m, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n",
1981 ggtt_offset + 4096 + (j * 4),
1982 reg_state[j], reg_state[j + 1],
1983 reg_state[j + 2], reg_state[j + 3]);
1984 }
1985 kunmap_atomic(reg_state);
1986 }
1987
1988 seq_putc(m, '\n');
1989}
1990
c0ab1ae9
BW		 1991static int i915_dump_lrc(struct seq_file *m, void *unused)
1992{
1993 struct drm_info_node *node = (struct drm_info_node *) m->private;
1994 struct drm_device *dev = node->minor->dev;
1995 struct drm_i915_private *dev_priv = dev->dev_private;
1996 struct intel_engine_cs *ring;
1997 struct intel_context *ctx;
1998 int ret, i;
1999
2000 if (!i915.enable_execlists) {
2001 seq_printf(m, "Logical Ring Contexts are disabled\n");
2002 return 0;
2003 }
2004
2005 ret = mutex_lock_interruptible(&dev->struct_mutex);
2006 if (ret)
2007 return ret;
2008
2009 list_for_each_entry(ctx, &dev_priv->context_list, link) {
2010 for_each_ring(ring, dev_priv, i) {
064ca1d2
TD		 2011 if (ring->default_context != ctx)
2012 i915_dump_lrc_obj(m, ring,
2013 ctx->engine[i].state);
c0ab1ae9
BW		 2014 }
2015 }
2016
2017 mutex_unlock(&dev->struct_mutex);
2018
2019 return 0;
2020}
2021
4ba70e44
OM		 2022static int i915_execlists(struct seq_file *m, void *data)
2023{
2024 struct drm_info_node *node = (struct drm_info_node *)m->private;
2025 struct drm_device *dev = node->minor->dev;
2026 struct drm_i915_private *dev_priv = dev->dev_private;
2027 struct intel_engine_cs *ring;
2028 u32 status_pointer;
2029 u8 read_pointer;
2030 u8 write_pointer;
2031 u32 status;
2032 u32 ctx_id;
2033 struct list_head *cursor;
2034 int ring_id, i;
2035 int ret;
2036
2037 if (!i915.enable_execlists) {
2038 seq_puts(m, "Logical Ring Contexts are disabled\n");
2039 return 0;
2040 }
2041
2042 ret = mutex_lock_interruptible(&dev->struct_mutex);
2043 if (ret)
2044 return ret;
2045
fc0412ec
MT		 2046 intel_runtime_pm_get(dev_priv);
2047
4ba70e44 2048 for_each_ring(ring, dev_priv, ring_id) {
6d3d8274 2049 struct drm_i915_gem_request *head_req = NULL;
4ba70e44
OM		 2050 int count = 0;
2051 unsigned long flags;
2052
2053 seq_printf(m, "%s\n", ring->name);
2054
2055 status = I915_READ(RING_EXECLIST_STATUS(ring));
2056 ctx_id = I915_READ(RING_EXECLIST_STATUS(ring) + 4);
2057 seq_printf(m, "\tExeclist status: 0x%08X, context: %u\n",
2058 status, ctx_id);
2059
2060 status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(ring));
2061 seq_printf(m, "\tStatus pointer: 0x%08X\n", status_pointer);
2062
2063 read_pointer = ring->next_context_status_buffer;
2064 write_pointer = status_pointer & 0x07;
2065 if (read_pointer > write_pointer)
2066 write_pointer += 6;
2067 seq_printf(m, "\tRead pointer: 0x%08X, write pointer 0x%08X\n",
2068 read_pointer, write_pointer);
2069
2070 for (i = 0; i < 6; i++) {
2071 status = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + 8*i);
2072 ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + 8*i + 4);
2073
2074 seq_printf(m, "\tStatus buffer %d: 0x%08X, context: %u\n",
2075 i, status, ctx_id);
2076 }
2077
2078 spin_lock_irqsave(&ring->execlist_lock, flags);
2079 list_for_each(cursor, &ring->execlist_queue)
2080 count++;
2081 head_req = list_first_entry_or_null(&ring->execlist_queue,
6d3d8274 2082 struct drm_i915_gem_request, execlist_link);
4ba70e44
OM		 2083 spin_unlock_irqrestore(&ring->execlist_lock, flags);
2084
2085 seq_printf(m, "\t%d requests in queue\n", count);
2086 if (head_req) {
2087 struct drm_i915_gem_object *ctx_obj;
2088
6d3d8274 2089 ctx_obj = head_req->ctx->engine[ring_id].state;
4ba70e44
OM		 2090 seq_printf(m, "\tHead request id: %u\n",
2091 intel_execlists_ctx_id(ctx_obj));
2092 seq_printf(m, "\tHead request tail: %u\n",
6d3d8274 2093 head_req->tail);
4ba70e44
OM		 2094 }
2095
2096 seq_putc(m, '\n');
2097 }
2098
fc0412ec 2099 intel_runtime_pm_put(dev_priv);
4ba70e44
OM		 2100 mutex_unlock(&dev->struct_mutex);
2101
2102 return 0;
2103}
2104
ea16a3cd
DV		 2105static const char *swizzle_string(unsigned swizzle)
2106{
aee56cff 2107 switch (swizzle) {
ea16a3cd
DV		 2108 case I915_BIT_6_SWIZZLE_NONE:
2109 return "none";
2110 case I915_BIT_6_SWIZZLE_9:
2111 return "bit9";
2112 case I915_BIT_6_SWIZZLE_9_10:
2113 return "bit9/bit10";
2114 case I915_BIT_6_SWIZZLE_9_11:
2115 return "bit9/bit11";
2116 case I915_BIT_6_SWIZZLE_9_10_11:
2117 return "bit9/bit10/bit11";
2118 case I915_BIT_6_SWIZZLE_9_17:
2119 return "bit9/bit17";
2120 case I915_BIT_6_SWIZZLE_9_10_17:
2121 return "bit9/bit10/bit17";
2122 case I915_BIT_6_SWIZZLE_UNKNOWN:
8a168ca7 2123 return "unknown";
ea16a3cd
DV		 2124 }
2125
2126 return "bug";
2127}
2128
2129static int i915_swizzle_info(struct seq_file *m, void *data)
2130{
9f25d007 2131 struct drm_info_node *node = m->private;
ea16a3cd
DV		 2132 struct drm_device *dev = node->minor->dev;
2133 struct drm_i915_private *dev_priv = dev->dev_private;
22bcfc6a
DV		 2134 int ret;
2135
2136 ret = mutex_lock_interruptible(&dev->struct_mutex);
2137 if (ret)
2138 return ret;
c8c8fb33 2139 intel_runtime_pm_get(dev_priv);
ea16a3cd 2140
ea16a3cd
DV		 2141 seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
2142 swizzle_string(dev_priv->mm.bit_6_swizzle_x));
2143 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
2144 swizzle_string(dev_priv->mm.bit_6_swizzle_y));
2145
2146 if (IS_GEN3(dev) || IS_GEN4(dev)) {
2147 seq_printf(m, "DDC = 0x%08x\n",
2148 I915_READ(DCC));
656bfa3a
DV		 2149 seq_printf(m, "DDC2 = 0x%08x\n",
2150 I915_READ(DCC2));
ea16a3cd
DV		 2151 seq_printf(m, "C0DRB3 = 0x%04x\n",
2152 I915_READ16(C0DRB3));
2153 seq_printf(m, "C1DRB3 = 0x%04x\n",
2154 I915_READ16(C1DRB3));
9d3203e1 2155 } else if (INTEL_INFO(dev)->gen >= 6) {
3fa7d235
DV		 2156 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
2157 I915_READ(MAD_DIMM_C0));
2158 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
2159 I915_READ(MAD_DIMM_C1));
2160 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
2161 I915_READ(MAD_DIMM_C2));
2162 seq_printf(m, "TILECTL = 0x%08x\n",
2163 I915_READ(TILECTL));
5907f5fb 2164 if (INTEL_INFO(dev)->gen >= 8)
9d3203e1
BW		 2165 seq_printf(m, "GAMTARBMODE = 0x%08x\n",
2166 I915_READ(GAMTARBMODE));
2167 else
2168 seq_printf(m, "ARB_MODE = 0x%08x\n",
2169 I915_READ(ARB_MODE));
3fa7d235
DV		 2170 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
2171 I915_READ(DISP_ARB_CTL));
ea16a3cd 2172 }
656bfa3a
DV		 2173
2174 if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2175 seq_puts(m, "L-shaped memory detected\n");
2176
c8c8fb33 2177 intel_runtime_pm_put(dev_priv);
ea16a3cd
DV		 2178 mutex_unlock(&dev->struct_mutex);
2179
2180 return 0;
2181}
2182
1c60fef5
BW		 2183static int per_file_ctx(int id, void *ptr, void *data)
2184{
273497e5 2185 struct intel_context *ctx = ptr;
1c60fef5 2186 struct seq_file *m = data;
ae6c4806
DV		 2187 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2188
2189 if (!ppgtt) {
2190 seq_printf(m, " no ppgtt for context %d\n",
2191 ctx->user_handle);
2192 return 0;
2193 }
1c60fef5 2194
f83d6518
OM		 2195 if (i915_gem_context_is_default(ctx))
2196 seq_puts(m, " default context:\n");
2197 else
821d66dd 2198 seq_printf(m, " context %d:\n", ctx->user_handle);
1c60fef5
BW		 2199 ppgtt->debug_dump(ppgtt, m);
2200
2201 return 0;
2202}
2203
77df6772 2204static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev)
3cf17fc5 2205{
3cf17fc5 2206 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2207 struct intel_engine_cs *ring;
77df6772
BW		 2208 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2209 int unused, i;
3cf17fc5 2210
77df6772
BW		 2211 if (!ppgtt)
2212 return;
2213
77df6772
BW		 2214 for_each_ring(ring, dev_priv, unused) {
2215 seq_printf(m, "%s\n", ring->name);
2216 for (i = 0; i < 4; i++) {
2217 u32 offset = 0x270 + i * 8;
2218 u64 pdp = I915_READ(ring->mmio_base + offset + 4);
2219 pdp <<= 32;
2220 pdp |= I915_READ(ring->mmio_base + offset);
a2a5b15c 2221 seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
77df6772
BW		 2222 }
2223 }
2224}
2225
2226static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2227{
2228 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2229 struct intel_engine_cs *ring;
1c60fef5 2230 struct drm_file *file;
77df6772 2231 int i;
3cf17fc5 2232
3cf17fc5
DV		 2233 if (INTEL_INFO(dev)->gen == 6)
2234 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
2235
a2c7f6fd 2236 for_each_ring(ring, dev_priv, i) {
3cf17fc5
DV		 2237 seq_printf(m, "%s\n", ring->name);
2238 if (INTEL_INFO(dev)->gen == 7)
2239 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
2240 seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
2241 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
2242 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring)));
2243 }
2244 if (dev_priv->mm.aliasing_ppgtt) {
2245 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2246
267f0c90 2247 seq_puts(m, "aliasing PPGTT:\n");
7324cc04 2248 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.pd_offset);
1c60fef5 2249
87d60b63 2250 ppgtt->debug_dump(ppgtt, m);
ae6c4806 2251 }
1c60fef5
BW		 2252
2253 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2254 struct drm_i915_file_private *file_priv = file->driver_priv;
1c60fef5 2255
1c60fef5
BW		 2256 seq_printf(m, "proc: %s\n",
2257 get_pid_task(file->pid, PIDTYPE_PID)->comm);
1c60fef5 2258 idr_for_each(&file_priv->context_idr, per_file_ctx, m);
3cf17fc5
DV		 2259 }
2260 seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
77df6772
BW		 2261}
2262
2263static int i915_ppgtt_info(struct seq_file *m, void *data)
2264{
9f25d007 2265 struct drm_info_node *node = m->private;
77df6772 2266 struct drm_device *dev = node->minor->dev;
c8c8fb33 2267 struct drm_i915_private *dev_priv = dev->dev_private;
77df6772
BW		 2268
2269 int ret = mutex_lock_interruptible(&dev->struct_mutex);
2270 if (ret)
2271 return ret;
c8c8fb33 2272 intel_runtime_pm_get(dev_priv);
77df6772
BW		 2273
2274 if (INTEL_INFO(dev)->gen >= 8)
2275 gen8_ppgtt_info(m, dev);
2276 else if (INTEL_INFO(dev)->gen >= 6)
2277 gen6_ppgtt_info(m, dev);
2278
c8c8fb33 2279 intel_runtime_pm_put(dev_priv);
3cf17fc5
DV		 2280 mutex_unlock(&dev->struct_mutex);
2281
2282 return 0;
2283}
2284
1854d5ca
CW		 2285static int i915_rps_boost_info(struct seq_file *m, void *data)
2286{
2287 struct drm_info_node *node = m->private;
2288 struct drm_device *dev = node->minor->dev;
2289 struct drm_i915_private *dev_priv = dev->dev_private;
2290 struct drm_file *file;
2291 int ret;
2292
2293 ret = mutex_lock_interruptible(&dev->struct_mutex);
2294 if (ret)
2295 return ret;
2296
2297 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
2298 if (ret)
2299 goto unlock;
2300
2301 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2302 struct drm_i915_file_private *file_priv = file->driver_priv;
2303 struct task_struct *task;
2304
2305 rcu_read_lock();
2306 task = pid_task(file->pid, PIDTYPE_PID);
2307 seq_printf(m, "%s [%d]: %d boosts%s\n",
2308 task ? task->comm : "<unknown>",
2309 task ? task->pid : -1,
2310 file_priv->rps_boosts,
2311 list_empty(&file_priv->rps_boost) ? "" : ", active");
2312 rcu_read_unlock();
2313 }
a6f766f3 2314 seq_printf(m, "Semaphore boosts: %d\n", dev_priv->rps.semaphores.rps_boosts);
bcafc4e3 2315 seq_printf(m, "MMIO flip boosts: %d\n", dev_priv->rps.mmioflips.rps_boosts);
1854d5ca
CW		 2316 seq_printf(m, "Kernel boosts: %d\n", dev_priv->rps.boosts);
2317
2318 mutex_unlock(&dev_priv->rps.hw_lock);
2319unlock:
2320 mutex_unlock(&dev->struct_mutex);
2321
2322 return ret;
2323}
2324
63573eb7
BW		 2325static int i915_llc(struct seq_file *m, void *data)
2326{
9f25d007 2327 struct drm_info_node *node = m->private;
63573eb7
BW		 2328 struct drm_device *dev = node->minor->dev;
2329 struct drm_i915_private *dev_priv = dev->dev_private;
2330
2331 /* Size calculation for LLC is a bit of a pain. Ignore for now. */
2332 seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
2333 seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size);
2334
2335 return 0;
2336}
2337
e91fd8c6
RV		 2338static int i915_edp_psr_status(struct seq_file *m, void *data)
2339{
2340 struct drm_info_node *node = m->private;
2341 struct drm_device *dev = node->minor->dev;
2342 struct drm_i915_private *dev_priv = dev->dev_private;
a031d709 2343 u32 psrperf = 0;
a6cbdb8e
RV		 2344 u32 stat[3];
2345 enum pipe pipe;
a031d709 2346 bool enabled = false;
e91fd8c6 2347
3553a8ea
DL		 2348 if (!HAS_PSR(dev)) {
2349 seq_puts(m, "PSR not supported\n");
2350 return 0;
2351 }
2352
c8c8fb33
PZ		 2353 intel_runtime_pm_get(dev_priv);
2354
fa128fa6 2355 mutex_lock(&dev_priv->psr.lock);
a031d709
RV		 2356 seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
2357 seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
2807cf69 2358 seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
5755c78f 2359 seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
fa128fa6
DV		 2360 seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
2361 dev_priv->psr.busy_frontbuffer_bits);
2362 seq_printf(m, "Re-enable work scheduled: %s\n",
2363 yesno(work_busy(&dev_priv->psr.work.work)));
e91fd8c6 2364
3553a8ea
DL		 2365 if (HAS_DDI(dev))
2366 enabled = I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
2367 else {
2368 for_each_pipe(dev_priv, pipe) {
2369 stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
2370 VLV_EDP_PSR_CURR_STATE_MASK;
2371 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2372 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2373 enabled = true;
a6cbdb8e
RV		 2374 }
2375 }
2376 seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));
2377
2378 if (!HAS_DDI(dev))
2379 for_each_pipe(dev_priv, pipe) {
2380 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2381 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2382 seq_printf(m, " pipe %c", pipe_name(pipe));
2383 }
2384 seq_puts(m, "\n");
e91fd8c6 2385
a6cbdb8e 2386 /* CHV PSR has no kind of performance counter */
3553a8ea 2387 if (HAS_DDI(dev)) {
a031d709
RV		 2388 psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) &
2389 EDP_PSR_PERF_CNT_MASK;
a6cbdb8e
RV		 2390
2391 seq_printf(m, "Performance_Counter: %u\n", psrperf);
2392 }
fa128fa6 2393 mutex_unlock(&dev_priv->psr.lock);
e91fd8c6 2394
c8c8fb33 2395 intel_runtime_pm_put(dev_priv);
e91fd8c6
RV		 2396 return 0;
2397}
2398
d2e216d0
RV		 2399static int i915_sink_crc(struct seq_file *m, void *data)
2400{
2401 struct drm_info_node *node = m->private;
2402 struct drm_device *dev = node->minor->dev;
2403 struct intel_encoder *encoder;
2404 struct intel_connector *connector;
2405 struct intel_dp *intel_dp = NULL;
2406 int ret;
2407 u8 crc[6];
2408
2409 drm_modeset_lock_all(dev);
aca5e361 2410 for_each_intel_connector(dev, connector) {
d2e216d0
RV		 2411
2412 if (connector->base.dpms != DRM_MODE_DPMS_ON)
2413 continue;
2414
b6ae3c7c
PZ		 2415 if (!connector->base.encoder)
2416 continue;
2417
d2e216d0
RV		 2418 encoder = to_intel_encoder(connector->base.encoder);
2419 if (encoder->type != INTEL_OUTPUT_EDP)
2420 continue;
2421
2422 intel_dp = enc_to_intel_dp(&encoder->base);
2423
2424 ret = intel_dp_sink_crc(intel_dp, crc);
2425 if (ret)
2426 goto out;
2427
2428 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2429 crc[0], crc[1], crc[2],
2430 crc[3], crc[4], crc[5]);
2431 goto out;
2432 }
2433 ret = -ENODEV;
2434out:
2435 drm_modeset_unlock_all(dev);
2436 return ret;
2437}
2438
ec013e7f
JB		 2439static int i915_energy_uJ(struct seq_file *m, void *data)
2440{
2441 struct drm_info_node *node = m->private;
2442 struct drm_device *dev = node->minor->dev;
2443 struct drm_i915_private *dev_priv = dev->dev_private;
2444 u64 power;
2445 u32 units;
2446
2447 if (INTEL_INFO(dev)->gen < 6)
2448 return -ENODEV;
2449
36623ef8
PZ		 2450 intel_runtime_pm_get(dev_priv);
2451
ec013e7f
JB		 2452 rdmsrl(MSR_RAPL_POWER_UNIT, power);
2453 power = (power & 0x1f00) >> 8;
2454 units = 1000000 / (1 << power); /* convert to uJ */
2455 power = I915_READ(MCH_SECP_NRG_STTS);
2456 power *= units;
2457
36623ef8
PZ		 2458 intel_runtime_pm_put(dev_priv);
2459
ec013e7f 2460 seq_printf(m, "%llu", (long long unsigned)power);
371db66a
PZ		 2461
2462 return 0;
2463}
2464
2465static int i915_pc8_status(struct seq_file *m, void *unused)
2466{
9f25d007 2467 struct drm_info_node *node = m->private;
371db66a
PZ		 2468 struct drm_device *dev = node->minor->dev;
2469 struct drm_i915_private *dev_priv = dev->dev_private;
2470
85b8d5c2 2471 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
371db66a
PZ		 2472 seq_puts(m, "not supported\n");
2473 return 0;
2474 }
2475
86c4ec0d 2476 seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy));
371db66a 2477 seq_printf(m, "IRQs disabled: %s\n",
9df7575f 2478 yesno(!intel_irqs_enabled(dev_priv)));
371db66a 2479
ec013e7f
JB		 2480 return 0;
2481}
2482
1da51581
ID		 2483static const char *power_domain_str(enum intel_display_power_domain domain)
2484{
2485 switch (domain) {
2486 case POWER_DOMAIN_PIPE_A:
2487 return "PIPE_A";
2488 case POWER_DOMAIN_PIPE_B:
2489 return "PIPE_B";
2490 case POWER_DOMAIN_PIPE_C:
2491 return "PIPE_C";
2492 case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
2493 return "PIPE_A_PANEL_FITTER";
2494 case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
2495 return "PIPE_B_PANEL_FITTER";
2496 case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
2497 return "PIPE_C_PANEL_FITTER";
2498 case POWER_DOMAIN_TRANSCODER_A:
2499 return "TRANSCODER_A";
2500 case POWER_DOMAIN_TRANSCODER_B:
2501 return "TRANSCODER_B";
2502 case POWER_DOMAIN_TRANSCODER_C:
2503 return "TRANSCODER_C";
2504 case POWER_DOMAIN_TRANSCODER_EDP:
2505 return "TRANSCODER_EDP";
319be8ae
ID		 2506 case POWER_DOMAIN_PORT_DDI_A_2_LANES:
2507 return "PORT_DDI_A_2_LANES";
2508 case POWER_DOMAIN_PORT_DDI_A_4_LANES:
2509 return "PORT_DDI_A_4_LANES";
2510 case POWER_DOMAIN_PORT_DDI_B_2_LANES:
2511 return "PORT_DDI_B_2_LANES";
2512 case POWER_DOMAIN_PORT_DDI_B_4_LANES:
2513 return "PORT_DDI_B_4_LANES";
2514 case POWER_DOMAIN_PORT_DDI_C_2_LANES:
2515 return "PORT_DDI_C_2_LANES";
2516 case POWER_DOMAIN_PORT_DDI_C_4_LANES:
2517 return "PORT_DDI_C_4_LANES";
2518 case POWER_DOMAIN_PORT_DDI_D_2_LANES:
2519 return "PORT_DDI_D_2_LANES";
2520 case POWER_DOMAIN_PORT_DDI_D_4_LANES:
2521 return "PORT_DDI_D_4_LANES";
2522 case POWER_DOMAIN_PORT_DSI:
2523 return "PORT_DSI";
2524 case POWER_DOMAIN_PORT_CRT:
2525 return "PORT_CRT";
2526 case POWER_DOMAIN_PORT_OTHER:
2527 return "PORT_OTHER";
1da51581
ID		 2528 case POWER_DOMAIN_VGA:
2529 return "VGA";
2530 case POWER_DOMAIN_AUDIO:
2531 return "AUDIO";
bd2bb1b9
PZ		 2532 case POWER_DOMAIN_PLLS:
2533 return "PLLS";
1407121a
S		 2534 case POWER_DOMAIN_AUX_A:
2535 return "AUX_A";
2536 case POWER_DOMAIN_AUX_B:
2537 return "AUX_B";
2538 case POWER_DOMAIN_AUX_C:
2539 return "AUX_C";
2540 case POWER_DOMAIN_AUX_D:
2541 return "AUX_D";
1da51581
ID		 2542 case POWER_DOMAIN_INIT:
2543 return "INIT";
2544 default:
5f77eeb0 2545 MISSING_CASE(domain);
1da51581
ID		 2546 return "?";
2547 }
2548}
2549
2550static int i915_power_domain_info(struct seq_file *m, void *unused)
2551{
9f25d007 2552 struct drm_info_node *node = m->private;
1da51581
ID		 2553 struct drm_device *dev = node->minor->dev;
2554 struct drm_i915_private *dev_priv = dev->dev_private;
2555 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2556 int i;
2557
2558 mutex_lock(&power_domains->lock);
2559
2560 seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2561 for (i = 0; i < power_domains->power_well_count; i++) {
2562 struct i915_power_well *power_well;
2563 enum intel_display_power_domain power_domain;
2564
2565 power_well = &power_domains->power_wells[i];
2566 seq_printf(m, "%-25s %d\n", power_well->name,
2567 power_well->count);
2568
2569 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
2570 power_domain++) {
2571 if (!(BIT(power_domain) & power_well->domains))
2572 continue;
2573
2574 seq_printf(m, " %-23s %d\n",
2575 power_domain_str(power_domain),
2576 power_domains->domain_use_count[power_domain]);
2577 }
2578 }
2579
2580 mutex_unlock(&power_domains->lock);
2581
2582 return 0;
2583}
2584
53f5e3ca
JB		 2585static void intel_seq_print_mode(struct seq_file *m, int tabs,
2586 struct drm_display_mode *mode)
2587{
2588 int i;
2589
2590 for (i = 0; i < tabs; i++)
2591 seq_putc(m, '\t');
2592
2593 seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2594 mode->base.id, mode->name,
2595 mode->vrefresh, mode->clock,
2596 mode->hdisplay, mode->hsync_start,
2597 mode->hsync_end, mode->htotal,
2598 mode->vdisplay, mode->vsync_start,
2599 mode->vsync_end, mode->vtotal,
2600 mode->type, mode->flags);
2601}
2602
2603static void intel_encoder_info(struct seq_file *m,
2604 struct intel_crtc *intel_crtc,
2605 struct intel_encoder *intel_encoder)
2606{
9f25d007 2607 struct drm_info_node *node = m->private;
53f5e3ca
JB		 2608 struct drm_device *dev = node->minor->dev;
2609 struct drm_crtc *crtc = &intel_crtc->base;
2610 struct intel_connector *intel_connector;
2611 struct drm_encoder *encoder;
2612
2613 encoder = &intel_encoder->base;
2614 seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
8e329a03 2615 encoder->base.id, encoder->name);
53f5e3ca
JB		 2616 for_each_connector_on_encoder(dev, encoder, intel_connector) {
2617 struct drm_connector *connector = &intel_connector->base;
2618 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2619 connector->base.id,
c23cc417 2620 connector->name,
53f5e3ca
JB		 2621 drm_get_connector_status_name(connector->status));
2622 if (connector->status == connector_status_connected) {
2623 struct drm_display_mode *mode = &crtc->mode;
2624 seq_printf(m, ", mode:\n");
2625 intel_seq_print_mode(m, 2, mode);
2626 } else {
2627 seq_putc(m, '\n');
2628 }
2629 }
2630}
2631
2632static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2633{
9f25d007 2634 struct drm_info_node *node = m->private;
53f5e3ca
JB		 2635 struct drm_device *dev = node->minor->dev;
2636 struct drm_crtc *crtc = &intel_crtc->base;
2637 struct intel_encoder *intel_encoder;
2638
5aa8a937
MR		 2639 if (crtc->primary->fb)
2640 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2641 crtc->primary->fb->base.id, crtc->x, crtc->y,
2642 crtc->primary->fb->width, crtc->primary->fb->height);
2643 else
2644 seq_puts(m, "\tprimary plane disabled\n");
53f5e3ca
JB		 2645 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2646 intel_encoder_info(m, intel_crtc, intel_encoder);
2647}
2648
2649static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2650{
2651 struct drm_display_mode *mode = panel->fixed_mode;
2652
2653 seq_printf(m, "\tfixed mode:\n");
2654 intel_seq_print_mode(m, 2, mode);
2655}
2656
2657static void intel_dp_info(struct seq_file *m,
2658 struct intel_connector *intel_connector)
2659{
2660 struct intel_encoder *intel_encoder = intel_connector->encoder;
2661 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2662
2663 seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2664 seq_printf(m, "\taudio support: %s\n", intel_dp->has_audio ? "yes" :
2665 "no");
2666 if (intel_encoder->type == INTEL_OUTPUT_EDP)
2667 intel_panel_info(m, &intel_connector->panel);
2668}
2669
2670static void intel_hdmi_info(struct seq_file *m,
2671 struct intel_connector *intel_connector)
2672{
2673 struct intel_encoder *intel_encoder = intel_connector->encoder;
2674 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2675
2676 seq_printf(m, "\taudio support: %s\n", intel_hdmi->has_audio ? "yes" :
2677 "no");
2678}
2679
2680static void intel_lvds_info(struct seq_file *m,
2681 struct intel_connector *intel_connector)
2682{
2683 intel_panel_info(m, &intel_connector->panel);
2684}
2685
2686static void intel_connector_info(struct seq_file *m,
2687 struct drm_connector *connector)
2688{
2689 struct intel_connector *intel_connector = to_intel_connector(connector);
2690 struct intel_encoder *intel_encoder = intel_connector->encoder;
f103fc7d 2691 struct drm_display_mode *mode;
53f5e3ca
JB		 2692
2693 seq_printf(m, "connector %d: type %s, status: %s\n",
c23cc417 2694 connector->base.id, connector->name,
53f5e3ca
JB		 2695 drm_get_connector_status_name(connector->status));
2696 if (connector->status == connector_status_connected) {
2697 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2698 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2699 connector->display_info.width_mm,
2700 connector->display_info.height_mm);
2701 seq_printf(m, "\tsubpixel order: %s\n",
2702 drm_get_subpixel_order_name(connector->display_info.subpixel_order));
2703 seq_printf(m, "\tCEA rev: %d\n",
2704 connector->display_info.cea_rev);
2705 }
36cd7444
DA		 2706 if (intel_encoder) {
2707 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2708 intel_encoder->type == INTEL_OUTPUT_EDP)
2709 intel_dp_info(m, intel_connector);
2710 else if (intel_encoder->type == INTEL_OUTPUT_HDMI)
2711 intel_hdmi_info(m, intel_connector);
2712 else if (intel_encoder->type == INTEL_OUTPUT_LVDS)
2713 intel_lvds_info(m, intel_connector);
2714 }
53f5e3ca 2715
f103fc7d
JB		 2716 seq_printf(m, "\tmodes:\n");
2717 list_for_each_entry(mode, &connector->modes, head)
2718 intel_seq_print_mode(m, 2, mode);
53f5e3ca
JB		 2719}
2720
065f2ec2
CW		 2721static bool cursor_active(struct drm_device *dev, int pipe)
2722{
2723 struct drm_i915_private *dev_priv = dev->dev_private;
2724 u32 state;
2725
2726 if (IS_845G(dev) || IS_I865G(dev))
2727 state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
065f2ec2 2728 else
5efb3e28 2729 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
065f2ec2
CW		 2730
2731 return state;
2732}
2733
2734static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y)
2735{
2736 struct drm_i915_private *dev_priv = dev->dev_private;
2737 u32 pos;
2738
5efb3e28 2739 pos = I915_READ(CURPOS(pipe));
065f2ec2
CW		 2740
2741 *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
2742 if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
2743 *x = -*x;
2744
2745 *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
2746 if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
2747 *y = -*y;
2748
2749 return cursor_active(dev, pipe);
2750}
2751
53f5e3ca
JB		 2752static int i915_display_info(struct seq_file *m, void *unused)
2753{
9f25d007 2754 struct drm_info_node *node = m->private;
53f5e3ca 2755 struct drm_device *dev = node->minor->dev;
b0e5ddf3 2756 struct drm_i915_private *dev_priv = dev->dev_private;
065f2ec2 2757 struct intel_crtc *crtc;
53f5e3ca
JB		 2758 struct drm_connector *connector;
2759
b0e5ddf3 2760 intel_runtime_pm_get(dev_priv);
53f5e3ca
JB		 2761 drm_modeset_lock_all(dev);
2762 seq_printf(m, "CRTC info\n");
2763 seq_printf(m, "---------\n");
d3fcc808 2764 for_each_intel_crtc(dev, crtc) {
065f2ec2
CW		 2765 bool active;
2766 int x, y;
53f5e3ca 2767
57127efa 2768 seq_printf(m, "CRTC %d: pipe: %c, active=%s (size=%dx%d)\n",
065f2ec2 2769 crtc->base.base.id, pipe_name(crtc->pipe),
6e3c9717
ACO		 2770 yesno(crtc->active), crtc->config->pipe_src_w,
2771 crtc->config->pipe_src_h);
a23dc658 2772 if (crtc->active) {
065f2ec2
CW		 2773 intel_crtc_info(m, crtc);
2774
a23dc658 2775 active = cursor_position(dev, crtc->pipe, &x, &y);
57127efa 2776 seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
4b0e333e 2777 yesno(crtc->cursor_base),
3dd512fb
MR		 2778 x, y, crtc->base.cursor->state->crtc_w,
2779 crtc->base.cursor->state->crtc_h,
57127efa 2780 crtc->cursor_addr, yesno(active));
a23dc658 2781 }
cace841c
DV		 2782
2783 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
2784 yesno(!crtc->cpu_fifo_underrun_disabled),
2785 yesno(!crtc->pch_fifo_underrun_disabled));
53f5e3ca
JB		 2786 }
2787
2788 seq_printf(m, "\n");
2789 seq_printf(m, "Connector info\n");
2790 seq_printf(m, "--------------\n");
2791 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2792 intel_connector_info(m, connector);
2793 }
2794 drm_modeset_unlock_all(dev);
b0e5ddf3 2795 intel_runtime_pm_put(dev_priv);
53f5e3ca
JB		 2796
2797 return 0;
2798}
2799
e04934cf
BW		 2800static int i915_semaphore_status(struct seq_file *m, void *unused)
2801{
2802 struct drm_info_node *node = (struct drm_info_node *) m->private;
2803 struct drm_device *dev = node->minor->dev;
2804 struct drm_i915_private *dev_priv = dev->dev_private;
2805 struct intel_engine_cs *ring;
2806 int num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
2807 int i, j, ret;
2808
2809 if (!i915_semaphore_is_enabled(dev)) {
2810 seq_puts(m, "Semaphores are disabled\n");
2811 return 0;
2812 }
2813
2814 ret = mutex_lock_interruptible(&dev->struct_mutex);
2815 if (ret)
2816 return ret;
03872064 2817 intel_runtime_pm_get(dev_priv);
e04934cf
BW		 2818
2819 if (IS_BROADWELL(dev)) {
2820 struct page *page;
2821 uint64_t *seqno;
2822
2823 page = i915_gem_object_get_page(dev_priv->semaphore_obj, 0);
2824
2825 seqno = (uint64_t *)kmap_atomic(page);
2826 for_each_ring(ring, dev_priv, i) {
2827 uint64_t offset;
2828
2829 seq_printf(m, "%s\n", ring->name);
2830
2831 seq_puts(m, " Last signal:");
2832 for (j = 0; j < num_rings; j++) {
2833 offset = i * I915_NUM_RINGS + j;
2834 seq_printf(m, "0x%08llx (0x%02llx) ",
2835 seqno[offset], offset * 8);
2836 }
2837 seq_putc(m, '\n');
2838
2839 seq_puts(m, " Last wait: ");
2840 for (j = 0; j < num_rings; j++) {
2841 offset = i + (j * I915_NUM_RINGS);
2842 seq_printf(m, "0x%08llx (0x%02llx) ",
2843 seqno[offset], offset * 8);
2844 }
2845 seq_putc(m, '\n');
2846
2847 }
2848 kunmap_atomic(seqno);
2849 } else {
2850 seq_puts(m, " Last signal:");
2851 for_each_ring(ring, dev_priv, i)
2852 for (j = 0; j < num_rings; j++)
2853 seq_printf(m, "0x%08x\n",
2854 I915_READ(ring->semaphore.mbox.signal[j]));
2855 seq_putc(m, '\n');
2856 }
2857
2858 seq_puts(m, "\nSync seqno:\n");
2859 for_each_ring(ring, dev_priv, i) {
2860 for (j = 0; j < num_rings; j++) {
2861 seq_printf(m, " 0x%08x ", ring->semaphore.sync_seqno[j]);
2862 }
2863 seq_putc(m, '\n');
2864 }
2865 seq_putc(m, '\n');
2866
03872064 2867 intel_runtime_pm_put(dev_priv);
e04934cf
BW		 2868 mutex_unlock(&dev->struct_mutex);
2869 return 0;
2870}
2871
728e29d7
DV		 2872static int i915_shared_dplls_info(struct seq_file *m, void *unused)
2873{
2874 struct drm_info_node *node = (struct drm_info_node *) m->private;
2875 struct drm_device *dev = node->minor->dev;
2876 struct drm_i915_private *dev_priv = dev->dev_private;
2877 int i;
2878
2879 drm_modeset_lock_all(dev);
2880 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
2881 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
2882
2883 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
1e6f2ddc 2884 seq_printf(m, " crtc_mask: 0x%08x, active: %d, on: %s\n",
3e369b76 2885 pll->config.crtc_mask, pll->active, yesno(pll->on));
728e29d7 2886 seq_printf(m, " tracked hardware state:\n");
3e369b76
ACO		 2887 seq_printf(m, " dpll: 0x%08x\n", pll->config.hw_state.dpll);
2888 seq_printf(m, " dpll_md: 0x%08x\n",
2889 pll->config.hw_state.dpll_md);
2890 seq_printf(m, " fp0: 0x%08x\n", pll->config.hw_state.fp0);
2891 seq_printf(m, " fp1: 0x%08x\n", pll->config.hw_state.fp1);
2892 seq_printf(m, " wrpll: 0x%08x\n", pll->config.hw_state.wrpll);
728e29d7
DV		 2893 }
2894 drm_modeset_unlock_all(dev);
2895
2896 return 0;
2897}
2898
1ed1ef9d 2899static int i915_wa_registers(struct seq_file *m, void *unused)
888b5995
AS		 2900{
2901 int i;
2902 int ret;
2903 struct drm_info_node *node = (struct drm_info_node *) m->private;
2904 struct drm_device *dev = node->minor->dev;
2905 struct drm_i915_private *dev_priv = dev->dev_private;
2906
888b5995
AS		 2907 ret = mutex_lock_interruptible(&dev->struct_mutex);
2908 if (ret)
2909 return ret;
2910
2911 intel_runtime_pm_get(dev_priv);
2912
7225342a
MK		 2913 seq_printf(m, "Workarounds applied: %d\n", dev_priv->workarounds.count);
2914 for (i = 0; i < dev_priv->workarounds.count; ++i) {
2fa60f6d
MK		 2915 u32 addr, mask, value, read;
2916 bool ok;
888b5995 2917
7225342a
MK		 2918 addr = dev_priv->workarounds.reg[i].addr;
2919 mask = dev_priv->workarounds.reg[i].mask;
2fa60f6d
MK		 2920 value = dev_priv->workarounds.reg[i].value;
2921 read = I915_READ(addr);
2922 ok = (value & mask) == (read & mask);
2923 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
2924 addr, value, mask, read, ok ? "OK" : "FAIL");
888b5995
AS		 2925 }
2926
2927 intel_runtime_pm_put(dev_priv);
2928 mutex_unlock(&dev->struct_mutex);
2929
2930 return 0;
2931}
2932
c5511e44
DL		 2933static int i915_ddb_info(struct seq_file *m, void *unused)
2934{
2935 struct drm_info_node *node = m->private;
2936 struct drm_device *dev = node->minor->dev;
2937 struct drm_i915_private *dev_priv = dev->dev_private;
2938 struct skl_ddb_allocation *ddb;
2939 struct skl_ddb_entry *entry;
2940 enum pipe pipe;
2941 int plane;
2942
2fcffe19
DL		 2943 if (INTEL_INFO(dev)->gen < 9)
2944 return 0;
2945
c5511e44
DL		 2946 drm_modeset_lock_all(dev);
2947
2948 ddb = &dev_priv->wm.skl_hw.ddb;
2949
2950 seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
2951
2952 for_each_pipe(dev_priv, pipe) {
2953 seq_printf(m, "Pipe %c\n", pipe_name(pipe));
2954
dd740780 2955 for_each_plane(dev_priv, pipe, plane) {
c5511e44
DL		 2956 entry = &ddb->plane[pipe][plane];
2957 seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane + 1,
2958 entry->start, entry->end,
2959 skl_ddb_entry_size(entry));
2960 }
2961
2962 entry = &ddb->cursor[pipe];
2963 seq_printf(m, " %-13s%8u%8u%8u\n", "Cursor", entry->start,
2964 entry->end, skl_ddb_entry_size(entry));
2965 }
2966
2967 drm_modeset_unlock_all(dev);
2968
2969 return 0;
2970}
2971
a54746e3
VK		 2972static void drrs_status_per_crtc(struct seq_file *m,
2973 struct drm_device *dev, struct intel_crtc *intel_crtc)
2974{
2975 struct intel_encoder *intel_encoder;
2976 struct drm_i915_private *dev_priv = dev->dev_private;
2977 struct i915_drrs *drrs = &dev_priv->drrs;
2978 int vrefresh = 0;
2979
2980 for_each_encoder_on_crtc(dev, &intel_crtc->base, intel_encoder) {
2981 /* Encoder connected on this CRTC */
2982 switch (intel_encoder->type) {
2983 case INTEL_OUTPUT_EDP:
2984 seq_puts(m, "eDP:\n");
2985 break;
2986 case INTEL_OUTPUT_DSI:
2987 seq_puts(m, "DSI:\n");
2988 break;
2989 case INTEL_OUTPUT_HDMI:
2990 seq_puts(m, "HDMI:\n");
2991 break;
2992 case INTEL_OUTPUT_DISPLAYPORT:
2993 seq_puts(m, "DP:\n");
2994 break;
2995 default:
2996 seq_printf(m, "Other encoder (id=%d).\n",
2997 intel_encoder->type);
2998 return;
2999 }
3000 }
3001
3002 if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT)
3003 seq_puts(m, "\tVBT: DRRS_type: Static");
3004 else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT)
3005 seq_puts(m, "\tVBT: DRRS_type: Seamless");
3006 else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED)
3007 seq_puts(m, "\tVBT: DRRS_type: None");
3008 else
3009 seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value");
3010
3011 seq_puts(m, "\n\n");
3012
3013 if (intel_crtc->config->has_drrs) {
3014 struct intel_panel *panel;
3015
3016 mutex_lock(&drrs->mutex);
3017 /* DRRS Supported */
3018 seq_puts(m, "\tDRRS Supported: Yes\n");
3019
3020 /* disable_drrs() will make drrs->dp NULL */
3021 if (!drrs->dp) {
3022 seq_puts(m, "Idleness DRRS: Disabled");
3023 mutex_unlock(&drrs->mutex);
3024 return;
3025 }
3026
3027 panel = &drrs->dp->attached_connector->panel;
3028 seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X",
3029 drrs->busy_frontbuffer_bits);
3030
3031 seq_puts(m, "\n\t\t");
3032 if (drrs->refresh_rate_type == DRRS_HIGH_RR) {
3033 seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n");
3034 vrefresh = panel->fixed_mode->vrefresh;
3035 } else if (drrs->refresh_rate_type == DRRS_LOW_RR) {
3036 seq_puts(m, "DRRS_State: DRRS_LOW_RR\n");
3037 vrefresh = panel->downclock_mode->vrefresh;
3038 } else {
3039 seq_printf(m, "DRRS_State: Unknown(%d)\n",
3040 drrs->refresh_rate_type);
3041 mutex_unlock(&drrs->mutex);
3042 return;
3043 }
3044 seq_printf(m, "\t\tVrefresh: %d", vrefresh);
3045
3046 seq_puts(m, "\n\t\t");
3047 mutex_unlock(&drrs->mutex);
3048 } else {
3049 /* DRRS not supported. Print the VBT parameter*/
3050 seq_puts(m, "\tDRRS Supported : No");
3051 }
3052 seq_puts(m, "\n");
3053}
3054
3055static int i915_drrs_status(struct seq_file *m, void *unused)
3056{
3057 struct drm_info_node *node = m->private;
3058 struct drm_device *dev = node->minor->dev;
3059 struct intel_crtc *intel_crtc;
3060 int active_crtc_cnt = 0;
3061
3062 for_each_intel_crtc(dev, intel_crtc) {
3063 drm_modeset_lock(&intel_crtc->base.mutex, NULL);
3064
3065 if (intel_crtc->active) {
3066 active_crtc_cnt++;
3067 seq_printf(m, "\nCRTC %d: ", active_crtc_cnt);
3068
3069 drrs_status_per_crtc(m, dev, intel_crtc);
3070 }
3071
3072 drm_modeset_unlock(&intel_crtc->base.mutex);
3073 }
3074
3075 if (!active_crtc_cnt)
3076 seq_puts(m, "No active crtc found\n");
3077
3078 return 0;
3079}
3080
07144428
DL		 3081struct pipe_crc_info {
3082 const char *name;
3083 struct drm_device *dev;
3084 enum pipe pipe;
3085};
3086
11bed958
DA		 3087static int i915_dp_mst_info(struct seq_file *m, void *unused)
3088{
3089 struct drm_info_node *node = (struct drm_info_node *) m->private;
3090 struct drm_device *dev = node->minor->dev;
3091 struct drm_encoder *encoder;
3092 struct intel_encoder *intel_encoder;
3093 struct intel_digital_port *intel_dig_port;
3094 drm_modeset_lock_all(dev);
3095 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3096 intel_encoder = to_intel_encoder(encoder);
3097 if (intel_encoder->type != INTEL_OUTPUT_DISPLAYPORT)
3098 continue;
3099 intel_dig_port = enc_to_dig_port(encoder);
3100 if (!intel_dig_port->dp.can_mst)
3101 continue;
3102
3103 drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr);
3104 }
3105 drm_modeset_unlock_all(dev);
3106 return 0;
3107}
3108
07144428
DL		 3109static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
3110{
be5c7a90
DL		 3111 struct pipe_crc_info *info = inode->i_private;
3112 struct drm_i915_private *dev_priv = info->dev->dev_private;
3113 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3114
7eb1c496
DV		 3115 if (info->pipe >= INTEL_INFO(info->dev)->num_pipes)
3116 return -ENODEV;
3117
d538bbdf
DL		 3118 spin_lock_irq(&pipe_crc->lock);
3119
3120 if (pipe_crc->opened) {
3121 spin_unlock_irq(&pipe_crc->lock);
be5c7a90
DL		 3122 return -EBUSY; /* already open */
3123 }
3124
d538bbdf 3125 pipe_crc->opened = true;
07144428
DL		 3126 filep->private_data = inode->i_private;
3127
d538bbdf
DL		 3128 spin_unlock_irq(&pipe_crc->lock);
3129
07144428
DL		 3130 return 0;
3131}
3132
3133static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
3134{
be5c7a90
DL		 3135 struct pipe_crc_info *info = inode->i_private;
3136 struct drm_i915_private *dev_priv = info->dev->dev_private;
3137 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3138
d538bbdf
DL		 3139 spin_lock_irq(&pipe_crc->lock);
3140 pipe_crc->opened = false;
3141 spin_unlock_irq(&pipe_crc->lock);
be5c7a90 3142
07144428
DL		 3143 return 0;
3144}
3145
3146/* (6 fields, 8 chars each, space separated (5) + '\n') */
3147#define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
3148/* account for \'0' */
3149#define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1)
3150
3151static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
8bf1e9f1 3152{
d538bbdf
DL		 3153 assert_spin_locked(&pipe_crc->lock);
3154 return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3155 INTEL_PIPE_CRC_ENTRIES_NR);
07144428
DL		 3156}
3157
3158static ssize_t
3159i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
3160 loff_t *pos)
3161{
3162 struct pipe_crc_info *info = filep->private_data;
3163 struct drm_device *dev = info->dev;
3164 struct drm_i915_private *dev_priv = dev->dev_private;
3165 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3166 char buf[PIPE_CRC_BUFFER_LEN];
9ad6d99f 3167 int n_entries;
07144428
DL		 3168 ssize_t bytes_read;
3169
3170 /*
3171 * Don't allow user space to provide buffers not big enough to hold
3172 * a line of data.
3173 */
3174 if (count < PIPE_CRC_LINE_LEN)
3175 return -EINVAL;
3176
3177 if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
8bf1e9f1 3178 return 0;
07144428
DL		 3179
3180 /* nothing to read */
d538bbdf 3181 spin_lock_irq(&pipe_crc->lock);
07144428 3182 while (pipe_crc_data_count(pipe_crc) == 0) {
d538bbdf
DL		 3183 int ret;
3184
3185 if (filep->f_flags & O_NONBLOCK) {
3186 spin_unlock_irq(&pipe_crc->lock);
07144428 3187 return -EAGAIN;
d538bbdf 3188 }
07144428 3189
d538bbdf
DL		 3190 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
3191 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
3192 if (ret) {
3193 spin_unlock_irq(&pipe_crc->lock);
3194 return ret;
3195 }
8bf1e9f1
SH		 3196 }
3197
07144428 3198 /* We now have one or more entries to read */
9ad6d99f 3199 n_entries = count / PIPE_CRC_LINE_LEN;
d538bbdf 3200
07144428 3201 bytes_read = 0;
9ad6d99f
VS		 3202 while (n_entries > 0) {
3203 struct intel_pipe_crc_entry *entry =
3204 &pipe_crc->entries[pipe_crc->tail];
07144428 3205 int ret;
8bf1e9f1 3206
9ad6d99f
VS		 3207 if (CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3208 INTEL_PIPE_CRC_ENTRIES_NR) < 1)
3209 break;
3210
3211 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
3212 pipe_crc->tail = (pipe_crc->tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
3213
07144428
DL		 3214 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
3215 "%8u %8x %8x %8x %8x %8x\n",
3216 entry->frame, entry->crc[0],
3217 entry->crc[1], entry->crc[2],
3218 entry->crc[3], entry->crc[4]);
3219
9ad6d99f
VS		 3220 spin_unlock_irq(&pipe_crc->lock);
3221
3222 ret = copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN);
07144428
DL		 3223 if (ret == PIPE_CRC_LINE_LEN)
3224 return -EFAULT;
b2c88f5b 3225
9ad6d99f
VS		 3226 user_buf += PIPE_CRC_LINE_LEN;
3227 n_entries--;
3228
3229 spin_lock_irq(&pipe_crc->lock);
3230 }
8bf1e9f1 3231
d538bbdf
DL		 3232 spin_unlock_irq(&pipe_crc->lock);
3233
07144428
DL		 3234 return bytes_read;
3235}
3236
3237static const struct file_operations i915_pipe_crc_fops = {
3238 .owner = THIS_MODULE,
3239 .open = i915_pipe_crc_open,
3240 .read = i915_pipe_crc_read,
3241 .release = i915_pipe_crc_release,
3242};
3243
3244static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
3245 {
3246 .name = "i915_pipe_A_crc",
3247 .pipe = PIPE_A,
3248 },
3249 {
3250 .name = "i915_pipe_B_crc",
3251 .pipe = PIPE_B,
3252 },
3253 {
3254 .name = "i915_pipe_C_crc",
3255 .pipe = PIPE_C,
3256 },
3257};
3258
3259static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
3260 enum pipe pipe)
3261{
3262 struct drm_device *dev = minor->dev;
3263 struct dentry *ent;
3264 struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
3265
3266 info->dev = dev;
3267 ent = debugfs_create_file(info->name, S_IRUGO, root, info,
3268 &i915_pipe_crc_fops);
f3c5fe97
WY		 3269 if (!ent)
3270 return -ENOMEM;
07144428
DL		 3271
3272 return drm_add_fake_info_node(minor, ent, info);
8bf1e9f1
SH		 3273}
3274
e8dfcf78 3275static const char * const pipe_crc_sources[] = {
926321d5
DV		 3276 "none",
3277 "plane1",
3278 "plane2",
3279 "pf",
5b3a856b 3280 "pipe",
3d099a05
DV		 3281 "TV",
3282 "DP-B",
3283 "DP-C",
3284 "DP-D",
46a19188 3285 "auto",
926321d5
DV		 3286};
3287
3288static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
3289{
3290 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
3291 return pipe_crc_sources[source];
3292}
3293
bd9db02f 3294static int display_crc_ctl_show(struct seq_file *m, void *data)
926321d5
DV		 3295{
3296 struct drm_device *dev = m->private;
3297 struct drm_i915_private *dev_priv = dev->dev_private;
3298 int i;
3299
3300 for (i = 0; i < I915_MAX_PIPES; i++)
3301 seq_printf(m, "%c %s\n", pipe_name(i),
3302 pipe_crc_source_name(dev_priv->pipe_crc[i].source));
3303
3304 return 0;
3305}
3306
bd9db02f 3307static int display_crc_ctl_open(struct inode *inode, struct file *file)
926321d5
DV		 3308{
3309 struct drm_device *dev = inode->i_private;
3310
bd9db02f 3311 return single_open(file, display_crc_ctl_show, dev);
926321d5
DV		 3312}
3313
46a19188 3314static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
52f843f6
DV		 3315 uint32_t *val)
3316{
46a19188
DV		 3317 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3318 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3319
3320 switch (*source) {
52f843f6
DV		 3321 case INTEL_PIPE_CRC_SOURCE_PIPE:
3322 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
3323 break;
3324 case INTEL_PIPE_CRC_SOURCE_NONE:
3325 *val = 0;
3326 break;
3327 default:
3328 return -EINVAL;
3329 }
3330
3331 return 0;
3332}
3333
46a19188
DV		 3334static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe,
3335 enum intel_pipe_crc_source *source)
3336{
3337 struct intel_encoder *encoder;
3338 struct intel_crtc *crtc;
26756809 3339 struct intel_digital_port *dig_port;
46a19188
DV		 3340 int ret = 0;
3341
3342 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3343
6e9f798d 3344 drm_modeset_lock_all(dev);
b2784e15 3345 for_each_intel_encoder(dev, encoder) {
46a19188
DV		 3346 if (!encoder->base.crtc)
3347 continue;
3348
3349 crtc = to_intel_crtc(encoder->base.crtc);
3350
3351 if (crtc->pipe != pipe)
3352 continue;
3353
3354 switch (encoder->type) {
3355 case INTEL_OUTPUT_TVOUT:
3356 *source = INTEL_PIPE_CRC_SOURCE_TV;
3357 break;
3358 case INTEL_OUTPUT_DISPLAYPORT:
3359 case INTEL_OUTPUT_EDP:
26756809
DV		 3360 dig_port = enc_to_dig_port(&encoder->base);
3361 switch (dig_port->port) {
3362 case PORT_B:
3363 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
3364 break;
3365 case PORT_C:
3366 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
3367 break;
3368 case PORT_D:
3369 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
3370 break;
3371 default:
3372 WARN(1, "nonexisting DP port %c\n",
3373 port_name(dig_port->port));
3374 break;
3375 }
46a19188 3376 break;
6847d71b
PZ		 3377 default:
3378 break;
46a19188
DV		 3379 }
3380 }
6e9f798d 3381 drm_modeset_unlock_all(dev);
46a19188
DV		 3382
3383 return ret;
3384}
3385
3386static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
3387 enum pipe pipe,
3388 enum intel_pipe_crc_source *source,
7ac0129b
DV		 3389 uint32_t *val)
3390{
8d2f24ca
DV		 3391 struct drm_i915_private *dev_priv = dev->dev_private;
3392 bool need_stable_symbols = false;
3393
46a19188
DV		 3394 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3395 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3396 if (ret)
3397 return ret;
3398 }
3399
3400 switch (*source) {
7ac0129b
DV		 3401 case INTEL_PIPE_CRC_SOURCE_PIPE:
3402 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
3403 break;
3404 case INTEL_PIPE_CRC_SOURCE_DP_B:
3405 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
8d2f24ca 3406 need_stable_symbols = true;
7ac0129b
DV		 3407 break;
3408 case INTEL_PIPE_CRC_SOURCE_DP_C:
3409 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
8d2f24ca 3410 need_stable_symbols = true;
7ac0129b 3411 break;
2be57922
VS		 3412 case INTEL_PIPE_CRC_SOURCE_DP_D:
3413 if (!IS_CHERRYVIEW(dev))
3414 return -EINVAL;
3415 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV;
3416 need_stable_symbols = true;
3417 break;
7ac0129b
DV		 3418 case INTEL_PIPE_CRC_SOURCE_NONE:
3419 *val = 0;
3420 break;
3421 default:
3422 return -EINVAL;
3423 }
3424
8d2f24ca
DV		 3425 /*
3426 * When the pipe CRC tap point is after the transcoders we need
3427 * to tweak symbol-level features to produce a deterministic series of
3428 * symbols for a given frame. We need to reset those features only once
3429 * a frame (instead of every nth symbol):
3430 * - DC-balance: used to ensure a better clock recovery from the data
3431 * link (SDVO)
3432 * - DisplayPort scrambling: used for EMI reduction
3433 */
3434 if (need_stable_symbols) {
3435 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3436
8d2f24ca 3437 tmp |= DC_BALANCE_RESET_VLV;
eb736679
VS		 3438 switch (pipe) {
3439 case PIPE_A:
8d2f24ca 3440 tmp |= PIPE_A_SCRAMBLE_RESET;
eb736679
VS		 3441 break;
3442 case PIPE_B:
8d2f24ca 3443 tmp |= PIPE_B_SCRAMBLE_RESET;
eb736679
VS		 3444 break;
3445 case PIPE_C:
3446 tmp |= PIPE_C_SCRAMBLE_RESET;
3447 break;
3448 default:
3449 return -EINVAL;
3450 }
8d2f24ca
DV		 3451 I915_WRITE(PORT_DFT2_G4X, tmp);
3452 }
3453
7ac0129b
DV		 3454 return 0;
3455}
3456
4b79ebf7 3457static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
46a19188
DV		 3458 enum pipe pipe,
3459 enum intel_pipe_crc_source *source,
4b79ebf7
DV		 3460 uint32_t *val)
3461{
84093603
DV		 3462 struct drm_i915_private *dev_priv = dev->dev_private;
3463 bool need_stable_symbols = false;
3464
46a19188
DV		 3465 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3466 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3467 if (ret)
3468 return ret;
3469 }
3470
3471 switch (*source) {
4b79ebf7
DV		 3472 case INTEL_PIPE_CRC_SOURCE_PIPE:
3473 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
3474 break;
3475 case INTEL_PIPE_CRC_SOURCE_TV:
3476 if (!SUPPORTS_TV(dev))
3477 return -EINVAL;
3478 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
3479 break;
3480 case INTEL_PIPE_CRC_SOURCE_DP_B:
3481 if (!IS_G4X(dev))
3482 return -EINVAL;
3483 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
84093603 3484 need_stable_symbols = true;
4b79ebf7
DV		 3485 break;
3486 case INTEL_PIPE_CRC_SOURCE_DP_C:
3487 if (!IS_G4X(dev))
3488 return -EINVAL;
3489 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
84093603 3490 need_stable_symbols = true;
4b79ebf7
DV		 3491 break;
3492 case INTEL_PIPE_CRC_SOURCE_DP_D:
3493 if (!IS_G4X(dev))
3494 return -EINVAL;
3495 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
84093603 3496 need_stable_symbols = true;
4b79ebf7
DV		 3497 break;
3498 case INTEL_PIPE_CRC_SOURCE_NONE:
3499 *val = 0;
3500 break;
3501 default:
3502 return -EINVAL;
3503 }
3504
84093603
DV		 3505 /*
3506 * When the pipe CRC tap point is after the transcoders we need
3507 * to tweak symbol-level features to produce a deterministic series of
3508 * symbols for a given frame. We need to reset those features only once
3509 * a frame (instead of every nth symbol):
3510 * - DC-balance: used to ensure a better clock recovery from the data
3511 * link (SDVO)
3512 * - DisplayPort scrambling: used for EMI reduction
3513 */
3514 if (need_stable_symbols) {
3515 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3516
3517 WARN_ON(!IS_G4X(dev));
3518
3519 I915_WRITE(PORT_DFT_I9XX,
3520 I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
3521
3522 if (pipe == PIPE_A)
3523 tmp |= PIPE_A_SCRAMBLE_RESET;
3524 else
3525 tmp |= PIPE_B_SCRAMBLE_RESET;
3526
3527 I915_WRITE(PORT_DFT2_G4X, tmp);
3528 }
3529
4b79ebf7
DV		 3530 return 0;
3531}
3532
8d2f24ca
DV		 3533static void vlv_undo_pipe_scramble_reset(struct drm_device *dev,
3534 enum pipe pipe)
3535{
3536 struct drm_i915_private *dev_priv = dev->dev_private;
3537 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3538
eb736679
VS		 3539 switch (pipe) {
3540 case PIPE_A:
8d2f24ca 3541 tmp &= ~PIPE_A_SCRAMBLE_RESET;
eb736679
VS		 3542 break;
3543 case PIPE_B:
8d2f24ca 3544 tmp &= ~PIPE_B_SCRAMBLE_RESET;
eb736679
VS		 3545 break;
3546 case PIPE_C:
3547 tmp &= ~PIPE_C_SCRAMBLE_RESET;
3548 break;
3549 default:
3550 return;
3551 }
8d2f24ca
DV		 3552 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
3553 tmp &= ~DC_BALANCE_RESET_VLV;
3554 I915_WRITE(PORT_DFT2_G4X, tmp);
3555
3556}
3557
84093603
DV		 3558static void g4x_undo_pipe_scramble_reset(struct drm_device *dev,
3559 enum pipe pipe)
3560{
3561 struct drm_i915_private *dev_priv = dev->dev_private;
3562 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3563
3564 if (pipe == PIPE_A)
3565 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3566 else
3567 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3568 I915_WRITE(PORT_DFT2_G4X, tmp);
3569
3570 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
3571 I915_WRITE(PORT_DFT_I9XX,
3572 I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
3573 }
3574}
3575
46a19188 3576static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
5b3a856b
DV		 3577 uint32_t *val)
3578{
46a19188
DV		 3579 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3580 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3581
3582 switch (*source) {
5b3a856b
DV		 3583 case INTEL_PIPE_CRC_SOURCE_PLANE1:
3584 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
3585 break;
3586 case INTEL_PIPE_CRC_SOURCE_PLANE2:
3587 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
3588 break;
5b3a856b
DV		 3589 case INTEL_PIPE_CRC_SOURCE_PIPE:
3590 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
3591 break;
3d099a05 3592 case INTEL_PIPE_CRC_SOURCE_NONE:
5b3a856b
DV		 3593 *val = 0;
3594 break;
3d099a05
DV		 3595 default:
3596 return -EINVAL;
5b3a856b
DV		 3597 }
3598
3599 return 0;
3600}
3601
fabf6e51
DV		 3602static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device *dev)
3603{
3604 struct drm_i915_private *dev_priv = dev->dev_private;
3605 struct intel_crtc *crtc =
3606 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
3607
3608 drm_modeset_lock_all(dev);
3609 /*
3610 * If we use the eDP transcoder we need to make sure that we don't
3611 * bypass the pfit, since otherwise the pipe CRC source won't work. Only
3612 * relevant on hsw with pipe A when using the always-on power well
3613 * routing.
3614 */
6e3c9717
ACO		 3615 if (crtc->config->cpu_transcoder == TRANSCODER_EDP &&
3616 !crtc->config->pch_pfit.enabled) {
3617 crtc->config->pch_pfit.force_thru = true;
fabf6e51
DV		 3618
3619 intel_display_power_get(dev_priv,
3620 POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A));
3621
ce22dba9 3622 intel_crtc_reset(crtc);
fabf6e51
DV		 3623 }
3624 drm_modeset_unlock_all(dev);
3625}
3626
3627static void hsw_undo_trans_edp_pipe_A_crc_wa(struct drm_device *dev)
3628{
3629 struct drm_i915_private *dev_priv = dev->dev_private;
3630 struct intel_crtc *crtc =
3631 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
3632
3633 drm_modeset_lock_all(dev);
3634 /*
3635 * If we use the eDP transcoder we need to make sure that we don't
3636 * bypass the pfit, since otherwise the pipe CRC source won't work. Only
3637 * relevant on hsw with pipe A when using the always-on power well
3638 * routing.
3639 */
6e3c9717
ACO		 3640 if (crtc->config->pch_pfit.force_thru) {
3641 crtc->config->pch_pfit.force_thru = false;
fabf6e51 3642
ce22dba9 3643 intel_crtc_reset(crtc);
fabf6e51
DV		 3644
3645 intel_display_power_put(dev_priv,
3646 POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A));
3647 }
3648 drm_modeset_unlock_all(dev);
3649}
3650
3651static int ivb_pipe_crc_ctl_reg(struct drm_device *dev,
3652 enum pipe pipe,
3653 enum intel_pipe_crc_source *source,
5b3a856b
DV		 3654 uint32_t *val)
3655{
46a19188
DV		 3656 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3657 *source = INTEL_PIPE_CRC_SOURCE_PF;
3658
3659 switch (*source) {
5b3a856b
DV		 3660 case INTEL_PIPE_CRC_SOURCE_PLANE1:
3661 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
3662 break;
3663 case INTEL_PIPE_CRC_SOURCE_PLANE2:
3664 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
3665 break;
3666 case INTEL_PIPE_CRC_SOURCE_PF:
fabf6e51
DV		 3667 if (IS_HASWELL(dev) && pipe == PIPE_A)
3668 hsw_trans_edp_pipe_A_crc_wa(dev);
3669
5b3a856b
DV		 3670 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
3671 break;
3d099a05 3672 case INTEL_PIPE_CRC_SOURCE_NONE:
5b3a856b
DV		 3673 *val = 0;
3674 break;
3d099a05
DV		 3675 default:
3676 return -EINVAL;
5b3a856b
DV		 3677 }
3678
3679 return 0;
3680}
3681
926321d5
DV		 3682static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
3683 enum intel_pipe_crc_source source)
3684{
3685 struct drm_i915_private *dev_priv = dev->dev_private;
cc3da175 3686 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
8c740dce
PZ		 3687 struct intel_crtc *crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev,
3688 pipe));
432f3342 3689 u32 val = 0; /* shut up gcc */
5b3a856b 3690 int ret;
926321d5 3691
cc3da175
DL		 3692 if (pipe_crc->source == source)
3693 return 0;
3694
ae676fcd
DL		 3695 /* forbid changing the source without going back to 'none' */
3696 if (pipe_crc->source && source)
3697 return -EINVAL;
3698
9d8b0588
DV		 3699 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PIPE(pipe))) {
3700 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
3701 return -EIO;
3702 }
3703
52f843f6 3704 if (IS_GEN2(dev))
46a19188 3705 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
52f843f6 3706 else if (INTEL_INFO(dev)->gen < 5)
46a19188 3707 ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
7ac0129b 3708 else if (IS_VALLEYVIEW(dev))
fabf6e51 3709 ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val);
4b79ebf7 3710 else if (IS_GEN5(dev) || IS_GEN6(dev))
46a19188 3711 ret = ilk_pipe_crc_ctl_reg(&source, &val);
5b3a856b 3712 else
fabf6e51 3713 ret = ivb_pipe_crc_ctl_reg(dev, pipe, &source, &val);
5b3a856b
DV		 3714
3715 if (ret != 0)
3716 return ret;
3717
4b584369
DL		 3718 /* none -> real source transition */
3719 if (source) {
4252fbc3
VS		 3720 struct intel_pipe_crc_entry *entries;
3721
7cd6ccff
DL		 3722 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
3723 pipe_name(pipe), pipe_crc_source_name(source));
3724
3cf54b34
VS		 3725 entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR,
3726 sizeof(pipe_crc->entries[0]),
4252fbc3
VS		 3727 GFP_KERNEL);
3728 if (!entries)
e5f75aca
DL		 3729 return -ENOMEM;
3730
8c740dce
PZ		 3731 /*
3732 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
3733 * enabled and disabled dynamically based on package C states,
3734 * user space can't make reliable use of the CRCs, so let's just
3735 * completely disable it.
3736 */
3737 hsw_disable_ips(crtc);
3738
d538bbdf 3739 spin_lock_irq(&pipe_crc->lock);
64387b61 3740 kfree(pipe_crc->entries);
4252fbc3 3741 pipe_crc->entries = entries;
d538bbdf
DL		 3742 pipe_crc->head = 0;
3743 pipe_crc->tail = 0;
3744 spin_unlock_irq(&pipe_crc->lock);
4b584369
DL		 3745 }
3746
cc3da175 3747 pipe_crc->source = source;
926321d5 3748
926321d5
DV		 3749 I915_WRITE(PIPE_CRC_CTL(pipe), val);
3750 POSTING_READ(PIPE_CRC_CTL(pipe));
3751
e5f75aca
DL		 3752 /* real source -> none transition */
3753 if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
d538bbdf 3754 struct intel_pipe_crc_entry *entries;
a33d7105
DV		 3755 struct intel_crtc *crtc =
3756 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
d538bbdf 3757
7cd6ccff
DL		 3758 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
3759 pipe_name(pipe));
3760
a33d7105
DV		 3761 drm_modeset_lock(&crtc->base.mutex, NULL);
3762 if (crtc->active)
3763 intel_wait_for_vblank(dev, pipe);
3764 drm_modeset_unlock(&crtc->base.mutex);
bcf17ab2 3765
d538bbdf
DL		 3766 spin_lock_irq(&pipe_crc->lock);
3767 entries = pipe_crc->entries;
e5f75aca 3768 pipe_crc->entries = NULL;
9ad6d99f
VS		 3769 pipe_crc->head = 0;
3770 pipe_crc->tail = 0;
d538bbdf
DL		 3771 spin_unlock_irq(&pipe_crc->lock);
3772
3773 kfree(entries);
84093603
DV		 3774
3775 if (IS_G4X(dev))
3776 g4x_undo_pipe_scramble_reset(dev, pipe);
8d2f24ca
DV		 3777 else if (IS_VALLEYVIEW(dev))
3778 vlv_undo_pipe_scramble_reset(dev, pipe);
fabf6e51
DV		 3779 else if (IS_HASWELL(dev) && pipe == PIPE_A)
3780 hsw_undo_trans_edp_pipe_A_crc_wa(dev);
8c740dce
PZ		 3781
3782 hsw_enable_ips(crtc);
e5f75aca
DL		 3783 }
3784
926321d5
DV		 3785 return 0;
3786}
3787
3788/*
3789 * Parse pipe CRC command strings:
b94dec87
DL		 3790 * command: wsp* object wsp+ name wsp+ source wsp*
3791 * object: 'pipe'
3792 * name: (A | B | C)
926321d5
DV		 3793 * source: (none | plane1 | plane2 | pf)
3794 * wsp: (#0x20 | #0x9 | #0xA)+
3795 *
3796 * eg.:
b94dec87
DL		 3797 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A
3798 * "pipe A none" -> Stop CRC
926321d5 3799 */
bd9db02f 3800static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
926321d5
DV		 3801{
3802 int n_words = 0;
3803
3804 while (*buf) {
3805 char *end;
3806
3807 /* skip leading white space */
3808 buf = skip_spaces(buf);
3809 if (!*buf)
3810 break; /* end of buffer */
3811
3812 /* find end of word */
3813 for (end = buf; *end && !isspace(*end); end++)
3814 ;
3815
3816 if (n_words == max_words) {
3817 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
3818 max_words);
3819 return -EINVAL; /* ran out of words[] before bytes */
3820 }
3821
3822 if (*end)
3823 *end++ = '\0';
3824 words[n_words++] = buf;
3825 buf = end;
3826 }
3827
3828 return n_words;
3829}
3830
b94dec87
DL		 3831enum intel_pipe_crc_object {
3832 PIPE_CRC_OBJECT_PIPE,
3833};
3834
e8dfcf78 3835static const char * const pipe_crc_objects[] = {
b94dec87
DL		 3836 "pipe",
3837};
3838
3839static int
bd9db02f 3840display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
b94dec87
DL		 3841{
3842 int i;
3843
3844 for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
3845 if (!strcmp(buf, pipe_crc_objects[i])) {
bd9db02f 3846 *o = i;
b94dec87
DL		 3847 return 0;
3848 }
3849
3850 return -EINVAL;
3851}
3852
bd9db02f 3853static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
926321d5
DV		 3854{
3855 const char name = buf[0];
3856
3857 if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
3858 return -EINVAL;
3859
3860 *pipe = name - 'A';
3861
3862 return 0;
3863}
3864
3865static int
bd9db02f 3866display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
926321d5
DV		 3867{
3868 int i;
3869
3870 for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
3871 if (!strcmp(buf, pipe_crc_sources[i])) {
bd9db02f 3872 *s = i;
926321d5
DV		 3873 return 0;
3874 }
3875
3876 return -EINVAL;
3877}
3878
bd9db02f 3879static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len)
926321d5 3880{
b94dec87 3881#define N_WORDS 3
926321d5 3882 int n_words;
b94dec87 3883 char *words[N_WORDS];
926321d5 3884 enum pipe pipe;
b94dec87 3885 enum intel_pipe_crc_object object;
926321d5
DV		 3886 enum intel_pipe_crc_source source;
3887
bd9db02f 3888 n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
b94dec87
DL		 3889 if (n_words != N_WORDS) {
3890 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
3891 N_WORDS);
3892 return -EINVAL;
3893 }
3894
bd9db02f 3895 if (display_crc_ctl_parse_object(words[0], &object) < 0) {
b94dec87 3896 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
926321d5
DV		 3897 return -EINVAL;
3898 }
3899
bd9db02f 3900 if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
b94dec87 3901 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
926321d5
DV		 3902 return -EINVAL;
3903 }
3904
bd9db02f 3905 if (display_crc_ctl_parse_source(words[2], &source) < 0) {
b94dec87 3906 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
926321d5
DV		 3907 return -EINVAL;
3908 }
3909
3910 return pipe_crc_set_source(dev, pipe, source);
3911}
3912
bd9db02f
DL		 3913static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
3914 size_t len, loff_t *offp)
926321d5
DV		 3915{
3916 struct seq_file *m = file->private_data;
3917 struct drm_device *dev = m->private;
3918 char *tmpbuf;
3919 int ret;
3920
3921 if (len == 0)
3922 return 0;
3923
3924 if (len > PAGE_SIZE - 1) {
3925 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
3926 PAGE_SIZE);
3927 return -E2BIG;
3928 }
3929
3930 tmpbuf = kmalloc(len + 1, GFP_KERNEL);
3931 if (!tmpbuf)
3932 return -ENOMEM;
3933
3934 if (copy_from_user(tmpbuf, ubuf, len)) {
3935 ret = -EFAULT;
3936 goto out;
3937 }
3938 tmpbuf[len] = '\0';
3939
bd9db02f 3940 ret = display_crc_ctl_parse(dev, tmpbuf, len);
926321d5
DV		 3941
3942out:
3943 kfree(tmpbuf);
3944 if (ret < 0)
3945 return ret;
3946
3947 *offp += len;
3948 return len;
3949}
3950
bd9db02f 3951static const struct file_operations i915_display_crc_ctl_fops = {
926321d5 3952 .owner = THIS_MODULE,
bd9db02f 3953 .open = display_crc_ctl_open,
926321d5
DV		 3954 .read = seq_read,
3955 .llseek = seq_lseek,
3956 .release = single_release,
bd9db02f 3957 .write = display_crc_ctl_write
926321d5
DV		 3958};
3959
eb3394fa
TP		 3960static ssize_t i915_displayport_test_active_write(struct file *file,
3961 const char __user *ubuf,
3962 size_t len, loff_t *offp)
3963{
3964 char *input_buffer;
3965 int status = 0;
3966 struct seq_file *m;
3967 struct drm_device *dev;
3968 struct drm_connector *connector;
3969 struct list_head *connector_list;
3970 struct intel_dp *intel_dp;
3971 int val = 0;
3972
3973 m = file->private_data;
3974 if (!m) {
3975 status = -ENODEV;
3976 return status;
3977 }
3978 dev = m->private;
3979
3980 if (!dev) {
3981 status = -ENODEV;
3982 return status;
3983 }
3984 connector_list = &dev->mode_config.connector_list;
3985
3986 if (len == 0)
3987 return 0;
3988
3989 input_buffer = kmalloc(len + 1, GFP_KERNEL);
3990 if (!input_buffer)
3991 return -ENOMEM;
3992
3993 if (copy_from_user(input_buffer, ubuf, len)) {
3994 status = -EFAULT;
3995 goto out;
3996 }
3997
3998 input_buffer[len] = '\0';
3999 DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len);
4000
4001 list_for_each_entry(connector, connector_list, head) {
4002
4003 if (connector->connector_type !=
4004 DRM_MODE_CONNECTOR_DisplayPort)
4005 continue;
4006
4007 if (connector->connector_type ==
4008 DRM_MODE_CONNECTOR_DisplayPort &&
4009 connector->status == connector_status_connected &&
4010 connector->encoder != NULL) {
4011 intel_dp = enc_to_intel_dp(connector->encoder);
4012 status = kstrtoint(input_buffer, 10, &val);
4013 if (status < 0)
4014 goto out;
4015 DRM_DEBUG_DRIVER("Got %d for test active\n", val);
4016 /* To prevent erroneous activation of the compliance
4017 * testing code, only accept an actual value of 1 here
4018 */
4019 if (val == 1)
4020 intel_dp->compliance_test_active = 1;
4021 else
4022 intel_dp->compliance_test_active = 0;
4023 }
4024 }
4025out:
4026 kfree(input_buffer);
4027 if (status < 0)
4028 return status;
4029
4030 *offp += len;
4031 return len;
4032}
4033
4034static int i915_displayport_test_active_show(struct seq_file *m, void *data)
4035{
4036 struct drm_device *dev = m->private;
4037 struct drm_connector *connector;
4038 struct list_head *connector_list = &dev->mode_config.connector_list;
4039 struct intel_dp *intel_dp;
4040
4041 if (!dev)
4042 return -ENODEV;
4043
4044 list_for_each_entry(connector, connector_list, head) {
4045
4046 if (connector->connector_type !=
4047 DRM_MODE_CONNECTOR_DisplayPort)
4048 continue;
4049
4050 if (connector->status == connector_status_connected &&
4051 connector->encoder != NULL) {
4052 intel_dp = enc_to_intel_dp(connector->encoder);
4053 if (intel_dp->compliance_test_active)
4054 seq_puts(m, "1");
4055 else
4056 seq_puts(m, "0");
4057 } else
4058 seq_puts(m, "0");
4059 }
4060
4061 return 0;
4062}
4063
4064static int i915_displayport_test_active_open(struct inode *inode,
4065 struct file *file)
4066{
4067 struct drm_device *dev = inode->i_private;
4068
4069 return single_open(file, i915_displayport_test_active_show, dev);
4070}
4071
4072static const struct file_operations i915_displayport_test_active_fops = {
4073 .owner = THIS_MODULE,
4074 .open = i915_displayport_test_active_open,
4075 .read = seq_read,
4076 .llseek = seq_lseek,
4077 .release = single_release,
4078 .write = i915_displayport_test_active_write
4079};
4080
4081static int i915_displayport_test_data_show(struct seq_file *m, void *data)
4082{
4083 struct drm_device *dev = m->private;
4084 struct drm_connector *connector;
4085 struct list_head *connector_list = &dev->mode_config.connector_list;
4086 struct intel_dp *intel_dp;
4087
4088 if (!dev)
4089 return -ENODEV;
4090
4091 list_for_each_entry(connector, connector_list, head) {
4092
4093 if (connector->connector_type !=
4094 DRM_MODE_CONNECTOR_DisplayPort)
4095 continue;
4096
4097 if (connector->status == connector_status_connected &&
4098 connector->encoder != NULL) {
4099 intel_dp = enc_to_intel_dp(connector->encoder);
4100 seq_printf(m, "%lx", intel_dp->compliance_test_data);
4101 } else
4102 seq_puts(m, "0");
4103 }
4104
4105 return 0;
4106}
4107static int i915_displayport_test_data_open(struct inode *inode,
4108 struct file *file)
4109{
4110 struct drm_device *dev = inode->i_private;
4111
4112 return single_open(file, i915_displayport_test_data_show, dev);
4113}
4114
4115static const struct file_operations i915_displayport_test_data_fops = {
4116 .owner = THIS_MODULE,
4117 .open = i915_displayport_test_data_open,
4118 .read = seq_read,
4119 .llseek = seq_lseek,
4120 .release = single_release
4121};
4122
4123static int i915_displayport_test_type_show(struct seq_file *m, void *data)
4124{
4125 struct drm_device *dev = m->private;
4126 struct drm_connector *connector;
4127 struct list_head *connector_list = &dev->mode_config.connector_list;
4128 struct intel_dp *intel_dp;
4129
4130 if (!dev)
4131 return -ENODEV;
4132
4133 list_for_each_entry(connector, connector_list, head) {
4134
4135 if (connector->connector_type !=
4136 DRM_MODE_CONNECTOR_DisplayPort)
4137 continue;
4138
4139 if (connector->status == connector_status_connected &&
4140 connector->encoder != NULL) {
4141 intel_dp = enc_to_intel_dp(connector->encoder);
4142 seq_printf(m, "%02lx", intel_dp->compliance_test_type);
4143 } else
4144 seq_puts(m, "0");
4145 }
4146
4147 return 0;
4148}
4149
4150static int i915_displayport_test_type_open(struct inode *inode,
4151 struct file *file)
4152{
4153 struct drm_device *dev = inode->i_private;
4154
4155 return single_open(file, i915_displayport_test_type_show, dev);
4156}
4157
4158static const struct file_operations i915_displayport_test_type_fops = {
4159 .owner = THIS_MODULE,
4160 .open = i915_displayport_test_type_open,
4161 .read = seq_read,
4162 .llseek = seq_lseek,
4163 .release = single_release
4164};
4165
97e94b22 4166static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
369a1342
VS		 4167{
4168 struct drm_device *dev = m->private;
546c81fd 4169 int num_levels = ilk_wm_max_level(dev) + 1;
369a1342
VS		 4170 int level;
4171
4172 drm_modeset_lock_all(dev);
4173
4174 for (level = 0; level < num_levels; level++) {
4175 unsigned int latency = wm[level];
4176
97e94b22
DL		 4177 /*
4178 * - WM1+ latency values in 0.5us units
4179 * - latencies are in us on gen9
4180 */
4181 if (INTEL_INFO(dev)->gen >= 9)
4182 latency *= 10;
4183 else if (level > 0)
369a1342
VS		 4184 latency *= 5;
4185
4186 seq_printf(m, "WM%d %u (%u.%u usec)\n",
97e94b22 4187 level, wm[level], latency / 10, latency % 10);
369a1342
VS		 4188 }
4189
4190 drm_modeset_unlock_all(dev);
4191}
4192
4193static int pri_wm_latency_show(struct seq_file *m, void *data)
4194{
4195 struct drm_device *dev = m->private;
97e94b22
DL		 4196 struct drm_i915_private *dev_priv = dev->dev_private;
4197 const uint16_t *latencies;
4198
4199 if (INTEL_INFO(dev)->gen >= 9)
4200 latencies = dev_priv->wm.skl_latency;
4201 else
4202 latencies = to_i915(dev)->wm.pri_latency;
369a1342 4203
97e94b22 4204 wm_latency_show(m, latencies);
369a1342
VS		 4205
4206 return 0;
4207}
4208
4209static int spr_wm_latency_show(struct seq_file *m, void *data)
4210{
4211 struct drm_device *dev = m->private;
97e94b22
DL		 4212 struct drm_i915_private *dev_priv = dev->dev_private;
4213 const uint16_t *latencies;
4214
4215 if (INTEL_INFO(dev)->gen >= 9)
4216 latencies = dev_priv->wm.skl_latency;
4217 else
4218 latencies = to_i915(dev)->wm.spr_latency;
369a1342 4219
97e94b22 4220 wm_latency_show(m, latencies);
369a1342
VS		 4221
4222 return 0;
4223}
4224
4225static int cur_wm_latency_show(struct seq_file *m, void *data)
4226{
4227 struct drm_device *dev = m->private;
97e94b22
DL		 4228 struct drm_i915_private *dev_priv = dev->dev_private;
4229 const uint16_t *latencies;
4230
4231 if (INTEL_INFO(dev)->gen >= 9)
4232 latencies = dev_priv->wm.skl_latency;
4233 else
4234 latencies = to_i915(dev)->wm.cur_latency;
369a1342 4235
97e94b22 4236 wm_latency_show(m, latencies);
369a1342
VS		 4237
4238 return 0;
4239}
4240
4241static int pri_wm_latency_open(struct inode *inode, struct file *file)
4242{
4243 struct drm_device *dev = inode->i_private;
4244
9ad0257c 4245 if (HAS_GMCH_DISPLAY(dev))
369a1342
VS		 4246 return -ENODEV;
4247
4248 return single_open(file, pri_wm_latency_show, dev);
4249}
4250
4251static int spr_wm_latency_open(struct inode *inode, struct file *file)
4252{
4253 struct drm_device *dev = inode->i_private;
4254
9ad0257c 4255 if (HAS_GMCH_DISPLAY(dev))
369a1342
VS		 4256 return -ENODEV;
4257
4258 return single_open(file, spr_wm_latency_show, dev);
4259}
4260
4261static int cur_wm_latency_open(struct inode *inode, struct file *file)
4262{
4263 struct drm_device *dev = inode->i_private;
4264
9ad0257c 4265 if (HAS_GMCH_DISPLAY(dev))
369a1342
VS		 4266 return -ENODEV;
4267
4268 return single_open(file, cur_wm_latency_show, dev);
4269}
4270
4271static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
97e94b22 4272 size_t len, loff_t *offp, uint16_t wm[8])
369a1342
VS		 4273{
4274 struct seq_file *m = file->private_data;
4275 struct drm_device *dev = m->private;
97e94b22 4276 uint16_t new[8] = { 0 };
546c81fd 4277 int num_levels = ilk_wm_max_level(dev) + 1;
369a1342
VS		 4278 int level;
4279 int ret;
4280 char tmp[32];
4281
4282 if (len >= sizeof(tmp))
4283 return -EINVAL;
4284
4285 if (copy_from_user(tmp, ubuf, len))
4286 return -EFAULT;
4287
4288 tmp[len] = '\0';
4289
97e94b22
DL		 4290 ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
4291 &new[0], &new[1], &new[2], &new[3],
4292 &new[4], &new[5], &new[6], &new[7]);
369a1342
VS		 4293 if (ret != num_levels)
4294 return -EINVAL;
4295
4296 drm_modeset_lock_all(dev);
4297
4298 for (level = 0; level < num_levels; level++)
4299 wm[level] = new[level];
4300
4301 drm_modeset_unlock_all(dev);
4302
4303 return len;
4304}
4305
4306
4307static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
4308 size_t len, loff_t *offp)
4309{
4310 struct seq_file *m = file->private_data;
4311 struct drm_device *dev = m->private;
97e94b22
DL		 4312 struct drm_i915_private *dev_priv = dev->dev_private;
4313 uint16_t *latencies;
369a1342 4314
97e94b22
DL		 4315 if (INTEL_INFO(dev)->gen >= 9)
4316 latencies = dev_priv->wm.skl_latency;
4317 else
4318 latencies = to_i915(dev)->wm.pri_latency;
4319
4320 return wm_latency_write(file, ubuf, len, offp, latencies);
369a1342
VS		 4321}
4322
4323static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
4324 size_t len, loff_t *offp)
4325{
4326 struct seq_file *m = file->private_data;
4327 struct drm_device *dev = m->private;
97e94b22
DL		 4328 struct drm_i915_private *dev_priv = dev->dev_private;
4329 uint16_t *latencies;
369a1342 4330
97e94b22
DL		 4331 if (INTEL_INFO(dev)->gen >= 9)
4332 latencies = dev_priv->wm.skl_latency;
4333 else
4334 latencies = to_i915(dev)->wm.spr_latency;
4335
4336 return wm_latency_write(file, ubuf, len, offp, latencies);
369a1342
VS		 4337}
4338
4339static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
4340 size_t len, loff_t *offp)
4341{
4342 struct seq_file *m = file->private_data;
4343 struct drm_device *dev = m->private;
97e94b22
DL		 4344 struct drm_i915_private *dev_priv = dev->dev_private;
4345 uint16_t *latencies;
4346
4347 if (INTEL_INFO(dev)->gen >= 9)
4348 latencies = dev_priv->wm.skl_latency;
4349 else
4350 latencies = to_i915(dev)->wm.cur_latency;
369a1342 4351
97e94b22 4352 return wm_latency_write(file, ubuf, len, offp, latencies);
369a1342
VS		 4353}
4354
4355static const struct file_operations i915_pri_wm_latency_fops = {
4356 .owner = THIS_MODULE,
4357 .open = pri_wm_latency_open,
4358 .read = seq_read,
4359 .llseek = seq_lseek,
4360 .release = single_release,
4361 .write = pri_wm_latency_write
4362};
4363
4364static const struct file_operations i915_spr_wm_latency_fops = {
4365 .owner = THIS_MODULE,
4366 .open = spr_wm_latency_open,
4367 .read = seq_read,
4368 .llseek = seq_lseek,
4369 .release = single_release,
4370 .write = spr_wm_latency_write
4371};
4372
4373static const struct file_operations i915_cur_wm_latency_fops = {
4374 .owner = THIS_MODULE,
4375 .open = cur_wm_latency_open,
4376 .read = seq_read,
4377 .llseek = seq_lseek,
4378 .release = single_release,
4379 .write = cur_wm_latency_write
4380};
4381
647416f9
KC		 4382static int
4383i915_wedged_get(void *data, u64 *val)
f3cd474b 4384{
647416f9 4385 struct drm_device *dev = data;
e277a1f8 4386 struct drm_i915_private *dev_priv = dev->dev_private;
f3cd474b 4387
647416f9 4388 *val = atomic_read(&dev_priv->gpu_error.reset_counter);
f3cd474b 4389
647416f9 4390 return 0;
f3cd474b
CW		 4391}
4392
647416f9
KC		 4393static int
4394i915_wedged_set(void *data, u64 val)
f3cd474b 4395{
647416f9 4396 struct drm_device *dev = data;
d46c0517
ID		 4397 struct drm_i915_private *dev_priv = dev->dev_private;
4398
b8d24a06
MK		 4399 /*
4400 * There is no safeguard against this debugfs entry colliding
4401 * with the hangcheck calling same i915_handle_error() in
4402 * parallel, causing an explosion. For now we assume that the
4403 * test harness is responsible enough not to inject gpu hangs
4404 * while it is writing to 'i915_wedged'
4405 */
4406
4407 if (i915_reset_in_progress(&dev_priv->gpu_error))
4408 return -EAGAIN;
4409
d46c0517 4410 intel_runtime_pm_get(dev_priv);
f3cd474b 4411
58174462
MK		 4412 i915_handle_error(dev, val,
4413 "Manually setting wedged to %llu", val);
d46c0517
ID		 4414
4415 intel_runtime_pm_put(dev_priv);
4416
647416f9 4417 return 0;
f3cd474b
CW		 4418}
4419
647416f9
KC		 4420DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
4421 i915_wedged_get, i915_wedged_set,
3a3b4f98 4422 "%llu\n");
f3cd474b 4423
647416f9
KC		 4424static int
4425i915_ring_stop_get(void *data, u64 *val)
e5eb3d63 4426{
647416f9 4427 struct drm_device *dev = data;
e277a1f8 4428 struct drm_i915_private *dev_priv = dev->dev_private;
e5eb3d63 4429
647416f9 4430 *val = dev_priv->gpu_error.stop_rings;
e5eb3d63 4431
647416f9 4432 return 0;
e5eb3d63
DV		 4433}
4434
647416f9
KC		 4435static int
4436i915_ring_stop_set(void *data, u64 val)
e5eb3d63 4437{
647416f9 4438 struct drm_device *dev = data;
e5eb3d63 4439 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 4440 int ret;
e5eb3d63 4441
647416f9 4442 DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val);
e5eb3d63 4443
22bcfc6a
DV		 4444 ret = mutex_lock_interruptible(&dev->struct_mutex);
4445 if (ret)
4446 return ret;
4447
99584db3 4448 dev_priv->gpu_error.stop_rings = val;
e5eb3d63
DV		 4449 mutex_unlock(&dev->struct_mutex);
4450
647416f9 4451 return 0;
e5eb3d63
DV		 4452}
4453
647416f9
KC		 4454DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops,
4455 i915_ring_stop_get, i915_ring_stop_set,
4456 "0x%08llx\n");
d5442303 4457
094f9a54
CW		 4458static int
4459i915_ring_missed_irq_get(void *data, u64 *val)
4460{
4461 struct drm_device *dev = data;
4462 struct drm_i915_private *dev_priv = dev->dev_private;
4463
4464 *val = dev_priv->gpu_error.missed_irq_rings;
4465 return 0;
4466}
4467
4468static int
4469i915_ring_missed_irq_set(void *data, u64 val)
4470{
4471 struct drm_device *dev = data;
4472 struct drm_i915_private *dev_priv = dev->dev_private;
4473 int ret;
4474
4475 /* Lock against concurrent debugfs callers */
4476 ret = mutex_lock_interruptible(&dev->struct_mutex);
4477 if (ret)
4478 return ret;
4479 dev_priv->gpu_error.missed_irq_rings = val;
4480 mutex_unlock(&dev->struct_mutex);
4481
4482 return 0;
4483}
4484
4485DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
4486 i915_ring_missed_irq_get, i915_ring_missed_irq_set,
4487 "0x%08llx\n");
4488
4489static int
4490i915_ring_test_irq_get(void *data, u64 *val)
4491{
4492 struct drm_device *dev = data;
4493 struct drm_i915_private *dev_priv = dev->dev_private;
4494
4495 *val = dev_priv->gpu_error.test_irq_rings;
4496
4497 return 0;
4498}
4499
4500static int
4501i915_ring_test_irq_set(void *data, u64 val)
4502{
4503 struct drm_device *dev = data;
4504 struct drm_i915_private *dev_priv = dev->dev_private;
4505 int ret;
4506
4507 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
4508
4509 /* Lock against concurrent debugfs callers */
4510 ret = mutex_lock_interruptible(&dev->struct_mutex);
4511 if (ret)
4512 return ret;
4513
4514 dev_priv->gpu_error.test_irq_rings = val;
4515 mutex_unlock(&dev->struct_mutex);
4516
4517 return 0;
4518}
4519
4520DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
4521 i915_ring_test_irq_get, i915_ring_test_irq_set,
4522 "0x%08llx\n");
4523
dd624afd
CW		 4524#define DROP_UNBOUND 0x1
4525#define DROP_BOUND 0x2
4526#define DROP_RETIRE 0x4
4527#define DROP_ACTIVE 0x8
4528#define DROP_ALL (DROP_UNBOUND | \
4529 DROP_BOUND | \
4530 DROP_RETIRE | \
4531 DROP_ACTIVE)
647416f9
KC		 4532static int
4533i915_drop_caches_get(void *data, u64 *val)
dd624afd 4534{
647416f9 4535 *val = DROP_ALL;
dd624afd 4536
647416f9 4537 return 0;
dd624afd
CW		 4538}
4539
647416f9
KC		 4540static int
4541i915_drop_caches_set(void *data, u64 val)
dd624afd 4542{
647416f9 4543 struct drm_device *dev = data;
dd624afd 4544 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 4545 int ret;
dd624afd 4546
2f9fe5ff 4547 DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
dd624afd
CW		 4548
4549 /* No need to check and wait for gpu resets, only libdrm auto-restarts
4550 * on ioctls on -EAGAIN. */
4551 ret = mutex_lock_interruptible(&dev->struct_mutex);
4552 if (ret)
4553 return ret;
4554
4555 if (val & DROP_ACTIVE) {
4556 ret = i915_gpu_idle(dev);
4557 if (ret)
4558 goto unlock;
4559 }
4560
4561 if (val & (DROP_RETIRE | DROP_ACTIVE))
4562 i915_gem_retire_requests(dev);
4563
21ab4e74
CW		 4564 if (val & DROP_BOUND)
4565 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND);
4ad72b7f 4566
21ab4e74
CW		 4567 if (val & DROP_UNBOUND)
4568 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND);
dd624afd
CW		 4569
4570unlock:
4571 mutex_unlock(&dev->struct_mutex);
4572
647416f9 4573 return ret;
dd624afd
CW		 4574}
4575
647416f9
KC		 4576DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
4577 i915_drop_caches_get, i915_drop_caches_set,
4578 "0x%08llx\n");
dd624afd 4579
647416f9
KC		 4580static int
4581i915_max_freq_get(void *data, u64 *val)
358733e9 4582{
647416f9 4583 struct drm_device *dev = data;
e277a1f8 4584 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 4585 int ret;
004777cb 4586
daa3afb2 4587 if (INTEL_INFO(dev)->gen < 6)
004777cb
DV		 4588 return -ENODEV;
4589
5c9669ce
TR		 4590 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4591
4fc688ce 4592 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 4593 if (ret)
4594 return ret;
358733e9 4595
7c59a9c1 4596 *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
4fc688ce 4597 mutex_unlock(&dev_priv->rps.hw_lock);
358733e9 4598
647416f9 4599 return 0;
358733e9
JB		 4600}
4601
647416f9
KC		 4602static int
4603i915_max_freq_set(void *data, u64 val)
358733e9 4604{
647416f9 4605 struct drm_device *dev = data;
358733e9 4606 struct drm_i915_private *dev_priv = dev->dev_private;
bc4d91f6 4607 u32 hw_max, hw_min;
647416f9 4608 int ret;
004777cb 4609
daa3afb2 4610 if (INTEL_INFO(dev)->gen < 6)
004777cb 4611 return -ENODEV;
358733e9 4612
5c9669ce
TR		 4613 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4614
647416f9 4615 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
358733e9 4616
4fc688ce 4617 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 4618 if (ret)
4619 return ret;
4620
358733e9
JB		 4621 /*
4622 * Turbo will still be enabled, but won't go above the set value.
4623 */
bc4d91f6 4624 val = intel_freq_opcode(dev_priv, val);
dd0a1aa1 4625
bc4d91f6
AG		 4626 hw_max = dev_priv->rps.max_freq;
4627 hw_min = dev_priv->rps.min_freq;
dd0a1aa1 4628
b39fb297 4629 if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
dd0a1aa1
JM		 4630 mutex_unlock(&dev_priv->rps.hw_lock);
4631 return -EINVAL;
0a073b84
JB		 4632 }
4633
b39fb297 4634 dev_priv->rps.max_freq_softlimit = val;
dd0a1aa1 4635
ffe02b40 4636 intel_set_rps(dev, val);
dd0a1aa1 4637
4fc688ce 4638 mutex_unlock(&dev_priv->rps.hw_lock);
358733e9 4639
647416f9 4640 return 0;
358733e9
JB		 4641}
4642
647416f9
KC		 4643DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
4644 i915_max_freq_get, i915_max_freq_set,
3a3b4f98 4645 "%llu\n");
358733e9 4646
647416f9
KC		 4647static int
4648i915_min_freq_get(void *data, u64 *val)
1523c310 4649{
647416f9 4650 struct drm_device *dev = data;
e277a1f8 4651 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 4652 int ret;
004777cb 4653
daa3afb2 4654 if (INTEL_INFO(dev)->gen < 6)
004777cb
DV		 4655 return -ENODEV;
4656
5c9669ce
TR		 4657 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4658
4fc688ce 4659 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 4660 if (ret)
4661 return ret;
1523c310 4662
7c59a9c1 4663 *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
4fc688ce 4664 mutex_unlock(&dev_priv->rps.hw_lock);
1523c310 4665
647416f9 4666 return 0;
1523c310
JB		 4667}
4668
647416f9
KC		 4669static int
4670i915_min_freq_set(void *data, u64 val)
1523c310 4671{
647416f9 4672 struct drm_device *dev = data;
1523c310 4673 struct drm_i915_private *dev_priv = dev->dev_private;
bc4d91f6 4674 u32 hw_max, hw_min;
647416f9 4675 int ret;
004777cb 4676
daa3afb2 4677 if (INTEL_INFO(dev)->gen < 6)
004777cb 4678 return -ENODEV;
1523c310 4679
5c9669ce
TR		 4680 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4681
647416f9 4682 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
1523c310 4683
4fc688ce 4684 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 4685 if (ret)
4686 return ret;
4687
1523c310
JB		 4688 /*
4689 * Turbo will still be enabled, but won't go below the set value.
4690 */
bc4d91f6 4691 val = intel_freq_opcode(dev_priv, val);
dd0a1aa1 4692
bc4d91f6
AG		 4693 hw_max = dev_priv->rps.max_freq;
4694 hw_min = dev_priv->rps.min_freq;
dd0a1aa1 4695
b39fb297 4696 if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
dd0a1aa1
JM		 4697 mutex_unlock(&dev_priv->rps.hw_lock);
4698 return -EINVAL;
0a073b84 4699 }
dd0a1aa1 4700
b39fb297 4701 dev_priv->rps.min_freq_softlimit = val;
dd0a1aa1 4702
ffe02b40 4703 intel_set_rps(dev, val);
dd0a1aa1 4704
4fc688ce 4705 mutex_unlock(&dev_priv->rps.hw_lock);
1523c310 4706
647416f9 4707 return 0;
1523c310
JB		 4708}
4709
647416f9
KC		 4710DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
4711 i915_min_freq_get, i915_min_freq_set,
3a3b4f98 4712 "%llu\n");
1523c310 4713
647416f9
KC		 4714static int
4715i915_cache_sharing_get(void *data, u64 *val)
07b7ddd9 4716{
647416f9 4717 struct drm_device *dev = data;
e277a1f8 4718 struct drm_i915_private *dev_priv = dev->dev_private;
07b7ddd9 4719 u32 snpcr;
647416f9 4720 int ret;
07b7ddd9 4721
004777cb
DV		 4722 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
4723 return -ENODEV;
4724
22bcfc6a
DV		 4725 ret = mutex_lock_interruptible(&dev->struct_mutex);
4726 if (ret)
4727 return ret;
c8c8fb33 4728 intel_runtime_pm_get(dev_priv);
22bcfc6a 4729
07b7ddd9 4730 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
c8c8fb33
PZ		 4731
4732 intel_runtime_pm_put(dev_priv);
07b7ddd9
JB		 4733 mutex_unlock(&dev_priv->dev->struct_mutex);
4734
647416f9 4735 *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
07b7ddd9 4736
647416f9 4737 return 0;
07b7ddd9
JB		 4738}
4739
647416f9
KC		 4740static int
4741i915_cache_sharing_set(void *data, u64 val)
07b7ddd9 4742{
647416f9 4743 struct drm_device *dev = data;
07b7ddd9 4744 struct drm_i915_private *dev_priv = dev->dev_private;
07b7ddd9 4745 u32 snpcr;
07b7ddd9 4746
004777cb
DV		 4747 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
4748 return -ENODEV;
4749
647416f9 4750 if (val > 3)
07b7ddd9
JB		 4751 return -EINVAL;
4752
c8c8fb33 4753 intel_runtime_pm_get(dev_priv);
647416f9 4754 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
07b7ddd9
JB		 4755
4756 /* Update the cache sharing policy here as well */
4757 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4758 snpcr &= ~GEN6_MBC_SNPCR_MASK;
4759 snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
4760 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
4761
c8c8fb33 4762 intel_runtime_pm_put(dev_priv);
647416f9 4763 return 0;
07b7ddd9
JB		 4764}
4765
647416f9
KC		 4766DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
4767 i915_cache_sharing_get, i915_cache_sharing_set,
4768 "%llu\n");
07b7ddd9 4769
5d39525a
JM		 4770struct sseu_dev_status {
4771 unsigned int slice_total;
4772 unsigned int subslice_total;
4773 unsigned int subslice_per_slice;
4774 unsigned int eu_total;
4775 unsigned int eu_per_subslice;
4776};
4777
4778static void cherryview_sseu_device_status(struct drm_device *dev,
4779 struct sseu_dev_status *stat)
4780{
4781 struct drm_i915_private *dev_priv = dev->dev_private;
4782 const int ss_max = 2;
4783 int ss;
4784 u32 sig1[ss_max], sig2[ss_max];
4785
4786 sig1[0] = I915_READ(CHV_POWER_SS0_SIG1);
4787 sig1[1] = I915_READ(CHV_POWER_SS1_SIG1);
4788 sig2[0] = I915_READ(CHV_POWER_SS0_SIG2);
4789 sig2[1] = I915_READ(CHV_POWER_SS1_SIG2);
4790
4791 for (ss = 0; ss < ss_max; ss++) {
4792 unsigned int eu_cnt;
4793
4794 if (sig1[ss] & CHV_SS_PG_ENABLE)
4795 /* skip disabled subslice */
4796 continue;
4797
4798 stat->slice_total = 1;
4799 stat->subslice_per_slice++;
4800 eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
4801 ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
4802 ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
4803 ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2);
4804 stat->eu_total += eu_cnt;
4805 stat->eu_per_subslice = max(stat->eu_per_subslice, eu_cnt);
4806 }
4807 stat->subslice_total = stat->subslice_per_slice;
4808}
4809
4810static void gen9_sseu_device_status(struct drm_device *dev,
4811 struct sseu_dev_status *stat)
4812{
4813 struct drm_i915_private *dev_priv = dev->dev_private;
1c046bc1 4814 int s_max = 3, ss_max = 4;
5d39525a
JM		 4815 int s, ss;
4816 u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
4817
1c046bc1
JM		 4818 /* BXT has a single slice and at most 3 subslices. */
4819 if (IS_BROXTON(dev)) {
4820 s_max = 1;
4821 ss_max = 3;
4822 }
4823
4824 for (s = 0; s < s_max; s++) {
4825 s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s));
4826 eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s));
4827 eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s));
4828 }
4829
5d39525a
JM		 4830 eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
4831 GEN9_PGCTL_SSA_EU19_ACK |
4832 GEN9_PGCTL_SSA_EU210_ACK |
4833 GEN9_PGCTL_SSA_EU311_ACK;
4834 eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
4835 GEN9_PGCTL_SSB_EU19_ACK |
4836 GEN9_PGCTL_SSB_EU210_ACK |
4837 GEN9_PGCTL_SSB_EU311_ACK;
4838
4839 for (s = 0; s < s_max; s++) {
1c046bc1
JM		 4840 unsigned int ss_cnt = 0;
4841
5d39525a
JM		 4842 if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
4843 /* skip disabled slice */
4844 continue;
4845
4846 stat->slice_total++;
1c046bc1
JM		 4847
4848 if (IS_SKYLAKE(dev))
4849 ss_cnt = INTEL_INFO(dev)->subslice_per_slice;
4850
5d39525a
JM		 4851 for (ss = 0; ss < ss_max; ss++) {
4852 unsigned int eu_cnt;
4853
1c046bc1
JM		 4854 if (IS_BROXTON(dev) &&
4855 !(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
4856 /* skip disabled subslice */
4857 continue;
4858
4859 if (IS_BROXTON(dev))
4860 ss_cnt++;
4861
5d39525a
JM		 4862 eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
4863 eu_mask[ss%2]);
4864 stat->eu_total += eu_cnt;
4865 stat->eu_per_subslice = max(stat->eu_per_subslice,
4866 eu_cnt);
4867 }
1c046bc1
JM		 4868
4869 stat->subslice_total += ss_cnt;
4870 stat->subslice_per_slice = max(stat->subslice_per_slice,
4871 ss_cnt);
5d39525a
JM		 4872 }
4873}
4874
3873218f
JM		 4875static int i915_sseu_status(struct seq_file *m, void *unused)
4876{
4877 struct drm_info_node *node = (struct drm_info_node *) m->private;
4878 struct drm_device *dev = node->minor->dev;
5d39525a 4879 struct sseu_dev_status stat;
3873218f 4880
5575f03a 4881 if ((INTEL_INFO(dev)->gen < 8) || IS_BROADWELL(dev))
3873218f
JM		 4882 return -ENODEV;
4883
4884 seq_puts(m, "SSEU Device Info\n");
4885 seq_printf(m, " Available Slice Total: %u\n",
4886 INTEL_INFO(dev)->slice_total);
4887 seq_printf(m, " Available Subslice Total: %u\n",
4888 INTEL_INFO(dev)->subslice_total);
4889 seq_printf(m, " Available Subslice Per Slice: %u\n",
4890 INTEL_INFO(dev)->subslice_per_slice);
4891 seq_printf(m, " Available EU Total: %u\n",
4892 INTEL_INFO(dev)->eu_total);
4893 seq_printf(m, " Available EU Per Subslice: %u\n",
4894 INTEL_INFO(dev)->eu_per_subslice);
4895 seq_printf(m, " Has Slice Power Gating: %s\n",
4896 yesno(INTEL_INFO(dev)->has_slice_pg));
4897 seq_printf(m, " Has Subslice Power Gating: %s\n",
4898 yesno(INTEL_INFO(dev)->has_subslice_pg));
4899 seq_printf(m, " Has EU Power Gating: %s\n",
4900 yesno(INTEL_INFO(dev)->has_eu_pg));
4901
7f992aba 4902 seq_puts(m, "SSEU Device Status\n");
5d39525a 4903 memset(&stat, 0, sizeof(stat));
5575f03a 4904 if (IS_CHERRYVIEW(dev)) {
5d39525a 4905 cherryview_sseu_device_status(dev, &stat);
1c046bc1 4906 } else if (INTEL_INFO(dev)->gen >= 9) {
5d39525a 4907 gen9_sseu_device_status(dev, &stat);
7f992aba 4908 }
5d39525a
JM		 4909 seq_printf(m, " Enabled Slice Total: %u\n",
4910 stat.slice_total);
4911 seq_printf(m, " Enabled Subslice Total: %u\n",
4912 stat.subslice_total);
4913 seq_printf(m, " Enabled Subslice Per Slice: %u\n",
4914 stat.subslice_per_slice);
4915 seq_printf(m, " Enabled EU Total: %u\n",
4916 stat.eu_total);
4917 seq_printf(m, " Enabled EU Per Subslice: %u\n",
4918 stat.eu_per_subslice);
7f992aba 4919
3873218f
JM		 4920 return 0;
4921}
4922
6d794d42
BW		 4923static int i915_forcewake_open(struct inode *inode, struct file *file)
4924{
4925 struct drm_device *dev = inode->i_private;
4926 struct drm_i915_private *dev_priv = dev->dev_private;
6d794d42 4927
075edca4 4928 if (INTEL_INFO(dev)->gen < 6)
6d794d42
BW		 4929 return 0;
4930
6daccb0b 4931 intel_runtime_pm_get(dev_priv);
59bad947 4932 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6d794d42
BW		 4933
4934 return 0;
4935}
4936
c43b5634 4937static int i915_forcewake_release(struct inode *inode, struct file *file)
6d794d42
BW		 4938{
4939 struct drm_device *dev = inode->i_private;
4940 struct drm_i915_private *dev_priv = dev->dev_private;
4941
075edca4 4942 if (INTEL_INFO(dev)->gen < 6)
6d794d42
BW		 4943 return 0;
4944
59bad947 4945 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6daccb0b 4946 intel_runtime_pm_put(dev_priv);
6d794d42
BW		 4947
4948 return 0;
4949}
4950
4951static const struct file_operations i915_forcewake_fops = {
4952 .owner = THIS_MODULE,
4953 .open = i915_forcewake_open,
4954 .release = i915_forcewake_release,
4955};
4956
4957static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
4958{
4959 struct drm_device *dev = minor->dev;
4960 struct dentry *ent;
4961
4962 ent = debugfs_create_file("i915_forcewake_user",
8eb57294 4963 S_IRUSR,
6d794d42
BW		 4964 root, dev,
4965 &i915_forcewake_fops);
f3c5fe97
WY		 4966 if (!ent)
4967 return -ENOMEM;
6d794d42 4968
8eb57294 4969 return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
6d794d42
BW		 4970}
4971
6a9c308d
DV		 4972static int i915_debugfs_create(struct dentry *root,
4973 struct drm_minor *minor,
4974 const char *name,
4975 const struct file_operations *fops)
07b7ddd9
JB		 4976{
4977 struct drm_device *dev = minor->dev;
4978 struct dentry *ent;
4979
6a9c308d 4980 ent = debugfs_create_file(name,
07b7ddd9
JB		 4981 S_IRUGO | S_IWUSR,
4982 root, dev,
6a9c308d 4983 fops);
f3c5fe97
WY		 4984 if (!ent)
4985 return -ENOMEM;
07b7ddd9 4986
6a9c308d 4987 return drm_add_fake_info_node(minor, ent, fops);
07b7ddd9
JB		 4988}
4989
06c5bf8c 4990static const struct drm_info_list i915_debugfs_list[] = {
311bd68e 4991 {"i915_capabilities", i915_capabilities, 0},
73aa808f 4992 {"i915_gem_objects", i915_gem_object_info, 0},
08c18323 4993 {"i915_gem_gtt", i915_gem_gtt_info, 0},
1b50247a 4994 {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
433e12f7 4995 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
433e12f7 4996 {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
6d2b8885 4997 {"i915_gem_stolen", i915_gem_stolen_list_info },
4e5359cd 4998 {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
2017263e
BG		 4999 {"i915_gem_request", i915_gem_request_info, 0},
5000 {"i915_gem_seqno", i915_gem_seqno_info, 0},
a6172a80 5001 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
2017263e 5002 {"i915_gem_interrupt", i915_interrupt_info, 0},
1ec14ad3
CW		 5003 {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
5004 {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
5005 {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
9010ebfd 5006 {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
493018dc 5007 {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0},
adb4bd12 5008 {"i915_frequency_info", i915_frequency_info, 0},
f654449a 5009 {"i915_hangcheck_info", i915_hangcheck_info, 0},
f97108d1 5010 {"i915_drpc_info", i915_drpc_info, 0},
7648fa99 5011 {"i915_emon_status", i915_emon_status, 0},
23b2f8bb 5012 {"i915_ring_freq_table", i915_ring_freq_table, 0},
b5e50c3f 5013 {"i915_fbc_status", i915_fbc_status, 0},
92d44621 5014 {"i915_ips_status", i915_ips_status, 0},
4a9bef37 5015 {"i915_sr_status", i915_sr_status, 0},
44834a67 5016 {"i915_opregion", i915_opregion, 0},
37811fcc 5017 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
e76d3630 5018 {"i915_context_status", i915_context_status, 0},
c0ab1ae9 5019 {"i915_dump_lrc", i915_dump_lrc, 0},
4ba70e44 5020 {"i915_execlists", i915_execlists, 0},
f65367b5 5021 {"i915_forcewake_domains", i915_forcewake_domains, 0},
ea16a3cd 5022 {"i915_swizzle_info", i915_swizzle_info, 0},
3cf17fc5 5023 {"i915_ppgtt_info", i915_ppgtt_info, 0},
63573eb7 5024 {"i915_llc", i915_llc, 0},
e91fd8c6 5025 {"i915_edp_psr_status", i915_edp_psr_status, 0},
d2e216d0 5026 {"i915_sink_crc_eDP1", i915_sink_crc, 0},
ec013e7f 5027 {"i915_energy_uJ", i915_energy_uJ, 0},
371db66a 5028 {"i915_pc8_status", i915_pc8_status, 0},
1da51581 5029 {"i915_power_domain_info", i915_power_domain_info, 0},
53f5e3ca 5030 {"i915_display_info", i915_display_info, 0},
e04934cf 5031 {"i915_semaphore_status", i915_semaphore_status, 0},
728e29d7 5032 {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
11bed958 5033 {"i915_dp_mst_info", i915_dp_mst_info, 0},
1ed1ef9d 5034 {"i915_wa_registers", i915_wa_registers, 0},
c5511e44 5035 {"i915_ddb_info", i915_ddb_info, 0},
3873218f 5036 {"i915_sseu_status", i915_sseu_status, 0},
a54746e3 5037 {"i915_drrs_status", i915_drrs_status, 0},
1854d5ca 5038 {"i915_rps_boost_info", i915_rps_boost_info, 0},
2017263e 5039};
27c202ad 5040#define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
2017263e 5041
06c5bf8c 5042static const struct i915_debugfs_files {
34b9674c
DV		 5043 const char *name;
5044 const struct file_operations *fops;
5045} i915_debugfs_files[] = {
5046 {"i915_wedged", &i915_wedged_fops},
5047 {"i915_max_freq", &i915_max_freq_fops},
5048 {"i915_min_freq", &i915_min_freq_fops},
5049 {"i915_cache_sharing", &i915_cache_sharing_fops},
5050 {"i915_ring_stop", &i915_ring_stop_fops},
094f9a54
CW		 5051 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
5052 {"i915_ring_test_irq", &i915_ring_test_irq_fops},
34b9674c
DV		 5053 {"i915_gem_drop_caches", &i915_drop_caches_fops},
5054 {"i915_error_state", &i915_error_state_fops},
5055 {"i915_next_seqno", &i915_next_seqno_fops},
bd9db02f 5056 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
369a1342
VS		 5057 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
5058 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
5059 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
da46f936 5060 {"i915_fbc_false_color", &i915_fbc_fc_fops},
eb3394fa
TP		 5061 {"i915_dp_test_data", &i915_displayport_test_data_fops},
5062 {"i915_dp_test_type", &i915_displayport_test_type_fops},
5063 {"i915_dp_test_active", &i915_displayport_test_active_fops}
34b9674c
DV		 5064};
5065
07144428
DL		 5066void intel_display_crc_init(struct drm_device *dev)
5067{
5068 struct drm_i915_private *dev_priv = dev->dev_private;
b378360e 5069 enum pipe pipe;
07144428 5070
055e393f 5071 for_each_pipe(dev_priv, pipe) {
b378360e 5072 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
07144428 5073
d538bbdf
DL		 5074 pipe_crc->opened = false;
5075 spin_lock_init(&pipe_crc->lock);
07144428
DL		 5076 init_waitqueue_head(&pipe_crc->wq);
5077 }
5078}
5079
27c202ad 5080int i915_debugfs_init(struct drm_minor *minor)
2017263e 5081{
34b9674c 5082 int ret, i;
f3cd474b 5083
6d794d42 5084 ret = i915_forcewake_create(minor->debugfs_root, minor);
358733e9
JB		 5085 if (ret)
5086 return ret;
6a9c308d 5087
07144428
DL		 5088 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5089 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
5090 if (ret)
5091 return ret;
5092 }
5093
34b9674c
DV		 5094 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5095 ret = i915_debugfs_create(minor->debugfs_root, minor,
5096 i915_debugfs_files[i].name,
5097 i915_debugfs_files[i].fops);
5098 if (ret)
5099 return ret;
5100 }
40633219 5101
27c202ad
BG		 5102 return drm_debugfs_create_files(i915_debugfs_list,
5103 I915_DEBUGFS_ENTRIES,
2017263e
BG		 5104 minor->debugfs_root, minor);
5105}
5106
27c202ad 5107void i915_debugfs_cleanup(struct drm_minor *minor)
2017263e 5108{
34b9674c
DV		 5109 int i;
5110
27c202ad
BG		 5111 drm_debugfs_remove_files(i915_debugfs_list,
5112 I915_DEBUGFS_ENTRIES, minor);
07144428 5113
6d794d42
BW		 5114 drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
5115 1, minor);
07144428 5116
e309a997 5117 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
07144428
DL		 5118 struct drm_info_list *info_list =
5119 (struct drm_info_list *)&i915_pipe_crc_data[i];
5120
5121 drm_debugfs_remove_files(info_list, 1, minor);
5122 }
5123
34b9674c
DV		 5124 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5125 struct drm_info_list *info_list =
5126 (struct drm_info_list *) i915_debugfs_files[i].fops;
5127
5128 drm_debugfs_remove_files(info_list, 1, minor);
5129 }
2017263e 5130}
aa7471d2
JN		 5131
5132struct dpcd_block {
5133 /* DPCD dump start address. */
5134 unsigned int offset;
5135 /* DPCD dump end address, inclusive. If unset, .size will be used. */
5136 unsigned int end;
5137 /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */
5138 size_t size;
5139 /* Only valid for eDP. */
5140 bool edp;
5141};
5142
5143static const struct dpcd_block i915_dpcd_debug[] = {
5144 { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE },
5145 { .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS },
5146 { .offset = DP_DOWNSTREAM_PORT_0, .size = 16 },
5147 { .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET },
5148 { .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 },
5149 { .offset = DP_SET_POWER },
5150 { .offset = DP_EDP_DPCD_REV },
5151 { .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 },
5152 { .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB },
5153 { .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET },
5154};
5155
5156static int i915_dpcd_show(struct seq_file *m, void *data)
5157{
5158 struct drm_connector *connector = m->private;
5159 struct intel_dp *intel_dp =
5160 enc_to_intel_dp(&intel_attached_encoder(connector)->base);
5161 uint8_t buf[16];
5162 ssize_t err;
5163 int i;
5164
5c1a8875
MK		 5165 if (connector->status != connector_status_connected)
5166 return -ENODEV;
5167
aa7471d2
JN		 5168 for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) {
5169 const struct dpcd_block *b = &i915_dpcd_debug[i];
5170 size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1);
5171
5172 if (b->edp &&
5173 connector->connector_type != DRM_MODE_CONNECTOR_eDP)
5174 continue;
5175
5176 /* low tech for now */
5177 if (WARN_ON(size > sizeof(buf)))
5178 continue;
5179
5180 err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size);
5181 if (err <= 0) {
5182 DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n",
5183 size, b->offset, err);
5184 continue;
5185 }
5186
5187 seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf);
b3f9d7d7 5188 }
aa7471d2
JN		 5189
5190 return 0;
5191}
5192
5193static int i915_dpcd_open(struct inode *inode, struct file *file)
5194{
5195 return single_open(file, i915_dpcd_show, inode->i_private);
5196}
5197
5198static const struct file_operations i915_dpcd_fops = {
5199 .owner = THIS_MODULE,
5200 .open = i915_dpcd_open,
5201 .read = seq_read,
5202 .llseek = seq_lseek,
5203 .release = single_release,
5204};
5205
5206/**
5207 * i915_debugfs_connector_add - add i915 specific connector debugfs files
5208 * @connector: pointer to a registered drm_connector
5209 *
5210 * Cleanup will be done by drm_connector_unregister() through a call to
5211 * drm_debugfs_connector_remove().
5212 *
5213 * Returns 0 on success, negative error codes on error.
5214 */
5215int i915_debugfs_connector_add(struct drm_connector *connector)
5216{
5217 struct dentry *root = connector->debugfs_entry;
5218
5219 /* The connector must have been registered beforehands. */
5220 if (!root)
5221 return -ENODEV;
5222
5223 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
5224 connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5225 debugfs_create_file("i915_dpcd", S_IRUGO, root, connector,
5226 &i915_dpcd_fops);
5227
5228 return 0;
5229}
Linux kernel - Deliverables
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