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drm/i915: introduce for_each_engine_id()
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_debugfs.c
CommitLineData
2017263e
BG		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 *
27 */
28
29#include <linux/seq_file.h>
b2c88f5b 30#include <linux/circ_buf.h>
926321d5 31#include <linux/ctype.h>
f3cd474b 32#include <linux/debugfs.h>
5a0e3ad6 33#include <linux/slab.h>
2d1a8a48 34#include <linux/export.h>
6d2b8885 35#include <linux/list_sort.h>
ec013e7f 36#include <asm/msr-index.h>
760285e7 37#include <drm/drmP.h>
4e5359cd 38#include "intel_drv.h"
e5c65260 39#include "intel_ringbuffer.h"
760285e7 40#include <drm/i915_drm.h>
2017263e
BG		 41#include "i915_drv.h"
42
f13d3f73 43enum {
69dc4987 44 ACTIVE_LIST,
f13d3f73 45 INACTIVE_LIST,
d21d5975 46 PINNED_LIST,
f13d3f73 47};
2017263e 48
497666d8
DL		 49/* As the drm_debugfs_init() routines are called before dev->dev_private is
50 * allocated we need to hook into the minor for release. */
51static int
52drm_add_fake_info_node(struct drm_minor *minor,
53 struct dentry *ent,
54 const void *key)
55{
56 struct drm_info_node *node;
57
58 node = kmalloc(sizeof(*node), GFP_KERNEL);
59 if (node == NULL) {
60 debugfs_remove(ent);
61 return -ENOMEM;
62 }
63
64 node->minor = minor;
65 node->dent = ent;
66 node->info_ent = (void *) key;
67
68 mutex_lock(&minor->debugfs_lock);
69 list_add(&node->list, &minor->debugfs_list);
70 mutex_unlock(&minor->debugfs_lock);
71
72 return 0;
73}
74
70d39fe4
CW		 75static int i915_capabilities(struct seq_file *m, void *data)
76{
9f25d007 77 struct drm_info_node *node = m->private;
70d39fe4
CW		 78 struct drm_device *dev = node->minor->dev;
79 const struct intel_device_info *info = INTEL_INFO(dev);
80
81 seq_printf(m, "gen: %d\n", info->gen);
03d00ac5 82 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
79fc46df
DL		 83#define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
84#define SEP_SEMICOLON ;
85 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
86#undef PRINT_FLAG
87#undef SEP_SEMICOLON
70d39fe4
CW		 88
89 return 0;
90}
2017263e 91
05394f39 92static const char *get_pin_flag(struct drm_i915_gem_object *obj)
a6172a80 93{
baaa5cfb 94 if (obj->pin_display)
a6172a80
CW		 95 return "p";
96 else
97 return " ";
98}
99
05394f39 100static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
a6172a80 101{
0206e353
AJ		 102 switch (obj->tiling_mode) {
103 default:
104 case I915_TILING_NONE: return " ";
105 case I915_TILING_X: return "X";
106 case I915_TILING_Y: return "Y";
107 }
a6172a80
CW		 108}
109
1d693bcc
BW		 110static inline const char *get_global_flag(struct drm_i915_gem_object *obj)
111{
aff43766 112 return i915_gem_obj_to_ggtt(obj) ? "g" : " ";
1d693bcc
BW		 113}
114
ca1543be
TU		 115static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj)
116{
117 u64 size = 0;
118 struct i915_vma *vma;
119
1c7f4bca 120 list_for_each_entry(vma, &obj->vma_list, obj_link) {
596c5923 121 if (vma->is_ggtt && drm_mm_node_allocated(&vma->node))
ca1543be
TU		 122 size += vma->node.size;
123 }
124
125 return size;
126}
127
37811fcc
CW		 128static void
129describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
130{
b4716185 131 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
e2f80391 132 struct intel_engine_cs *engine;
1d693bcc 133 struct i915_vma *vma;
d7f46fc4 134 int pin_count = 0;
c3232b18 135 enum intel_engine_id id;
d7f46fc4 136
b4716185 137 seq_printf(m, "%pK: %s%s%s%s %8zdKiB %02x %02x [ ",
37811fcc 138 &obj->base,
481a3d43 139 obj->active ? "*" : " ",
37811fcc
CW		 140 get_pin_flag(obj),
141 get_tiling_flag(obj),
1d693bcc 142 get_global_flag(obj),
a05a5862 143 obj->base.size / 1024,
37811fcc 144 obj->base.read_domains,
b4716185 145 obj->base.write_domain);
c3232b18 146 for_each_engine_id(engine, dev_priv, id)
b4716185 147 seq_printf(m, "%x ",
c3232b18 148 i915_gem_request_get_seqno(obj->last_read_req[id]));
b4716185 149 seq_printf(m, "] %x %x%s%s%s",
97b2a6a1
JH		 150 i915_gem_request_get_seqno(obj->last_write_req),
151 i915_gem_request_get_seqno(obj->last_fenced_req),
0a4cd7c8 152 i915_cache_level_str(to_i915(obj->base.dev), obj->cache_level),
37811fcc
CW		 153 obj->dirty ? " dirty" : "",
154 obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
155 if (obj->base.name)
156 seq_printf(m, " (name: %d)", obj->base.name);
1c7f4bca 157 list_for_each_entry(vma, &obj->vma_list, obj_link) {
d7f46fc4
BW		 158 if (vma->pin_count > 0)
159 pin_count++;
ba0635ff
DC		 160 }
161 seq_printf(m, " (pinned x %d)", pin_count);
cc98b413
CW		 162 if (obj->pin_display)
163 seq_printf(m, " (display)");
37811fcc
CW		 164 if (obj->fence_reg != I915_FENCE_REG_NONE)
165 seq_printf(m, " (fence: %d)", obj->fence_reg);
1c7f4bca 166 list_for_each_entry(vma, &obj->vma_list, obj_link) {
8d2fdc3f 167 seq_printf(m, " (%sgtt offset: %08llx, size: %08llx",
596c5923 168 vma->is_ggtt ? "g" : "pp",
8d2fdc3f 169 vma->node.start, vma->node.size);
596c5923
CW		 170 if (vma->is_ggtt)
171 seq_printf(m, ", type: %u", vma->ggtt_view.type);
172 seq_puts(m, ")");
1d693bcc 173 }
c1ad11fc 174 if (obj->stolen)
440fd528 175 seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
30154650 176 if (obj->pin_display || obj->fault_mappable) {
6299f992 177 char s[3], *t = s;
30154650 178 if (obj->pin_display)
6299f992
CW		 179 *t++ = 'p';
180 if (obj->fault_mappable)
181 *t++ = 'f';
182 *t = '\0';
183 seq_printf(m, " (%s mappable)", s);
184 }
b4716185 185 if (obj->last_write_req != NULL)
41c52415 186 seq_printf(m, " (%s)",
666796da 187 i915_gem_request_get_engine(obj->last_write_req)->name);
d5a81ef1
DV		 188 if (obj->frontbuffer_bits)
189 seq_printf(m, " (frontbuffer: 0x%03x)", obj->frontbuffer_bits);
37811fcc
CW		 190}
191
273497e5 192static void describe_ctx(struct seq_file *m, struct intel_context *ctx)
3ccfd19d 193{
ea0c76f8 194 seq_putc(m, ctx->legacy_hw_ctx.initialized ? 'I' : 'i');
3ccfd19d
BW		 195 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
196 seq_putc(m, ' ');
197}
198
433e12f7 199static int i915_gem_object_list_info(struct seq_file *m, void *data)
2017263e 200{
9f25d007 201 struct drm_info_node *node = m->private;
433e12f7
BG		 202 uintptr_t list = (uintptr_t) node->info_ent->data;
203 struct list_head *head;
2017263e 204 struct drm_device *dev = node->minor->dev;
5cef07e1 205 struct drm_i915_private *dev_priv = dev->dev_private;
62106b4f 206 struct i915_address_space *vm = &dev_priv->ggtt.base;
ca191b13 207 struct i915_vma *vma;
c44ef60e 208 u64 total_obj_size, total_gtt_size;
8f2480fb 209 int count, ret;
de227ef0
CW		 210
211 ret = mutex_lock_interruptible(&dev->struct_mutex);
212 if (ret)
213 return ret;
2017263e 214
ca191b13 215 /* FIXME: the user of this interface might want more than just GGTT */
433e12f7
BG		 216 switch (list) {
217 case ACTIVE_LIST:
267f0c90 218 seq_puts(m, "Active:\n");
5cef07e1 219 head = &vm->active_list;
433e12f7
BG		 220 break;
221 case INACTIVE_LIST:
267f0c90 222 seq_puts(m, "Inactive:\n");
5cef07e1 223 head = &vm->inactive_list;
433e12f7 224 break;
433e12f7 225 default:
de227ef0
CW		 226 mutex_unlock(&dev->struct_mutex);
227 return -EINVAL;
2017263e 228 }
2017263e 229
8f2480fb 230 total_obj_size = total_gtt_size = count = 0;
1c7f4bca 231 list_for_each_entry(vma, head, vm_link) {
ca191b13
BW		 232 seq_printf(m, " ");
233 describe_obj(m, vma->obj);
234 seq_printf(m, "\n");
235 total_obj_size += vma->obj->base.size;
236 total_gtt_size += vma->node.size;
8f2480fb 237 count++;
2017263e 238 }
de227ef0 239 mutex_unlock(&dev->struct_mutex);
5e118f41 240
c44ef60e 241 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
8f2480fb 242 count, total_obj_size, total_gtt_size);
2017263e
BG		 243 return 0;
244}
245
6d2b8885
CW		 246static int obj_rank_by_stolen(void *priv,
247 struct list_head *A, struct list_head *B)
248{
249 struct drm_i915_gem_object *a =
b25cb2f8 250 container_of(A, struct drm_i915_gem_object, obj_exec_link);
6d2b8885 251 struct drm_i915_gem_object *b =
b25cb2f8 252 container_of(B, struct drm_i915_gem_object, obj_exec_link);
6d2b8885 253
2d05fa16
RV		 254 if (a->stolen->start < b->stolen->start)
255 return -1;
256 if (a->stolen->start > b->stolen->start)
257 return 1;
258 return 0;
6d2b8885
CW		 259}
260
261static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
262{
9f25d007 263 struct drm_info_node *node = m->private;
6d2b8885
CW		 264 struct drm_device *dev = node->minor->dev;
265 struct drm_i915_private *dev_priv = dev->dev_private;
266 struct drm_i915_gem_object *obj;
c44ef60e 267 u64 total_obj_size, total_gtt_size;
6d2b8885
CW		 268 LIST_HEAD(stolen);
269 int count, ret;
270
271 ret = mutex_lock_interruptible(&dev->struct_mutex);
272 if (ret)
273 return ret;
274
275 total_obj_size = total_gtt_size = count = 0;
276 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
277 if (obj->stolen == NULL)
278 continue;
279
b25cb2f8 280 list_add(&obj->obj_exec_link, &stolen);
6d2b8885
CW		 281
282 total_obj_size += obj->base.size;
ca1543be 283 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
6d2b8885
CW		 284 count++;
285 }
286 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
287 if (obj->stolen == NULL)
288 continue;
289
b25cb2f8 290 list_add(&obj->obj_exec_link, &stolen);
6d2b8885
CW		 291
292 total_obj_size += obj->base.size;
293 count++;
294 }
295 list_sort(NULL, &stolen, obj_rank_by_stolen);
296 seq_puts(m, "Stolen:\n");
297 while (!list_empty(&stolen)) {
b25cb2f8 298 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
6d2b8885
CW		 299 seq_puts(m, " ");
300 describe_obj(m, obj);
301 seq_putc(m, '\n');
b25cb2f8 302 list_del_init(&obj->obj_exec_link);
6d2b8885
CW		 303 }
304 mutex_unlock(&dev->struct_mutex);
305
c44ef60e 306 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
6d2b8885
CW		 307 count, total_obj_size, total_gtt_size);
308 return 0;
309}
310
6299f992
CW		 311#define count_objects(list, member) do { \
312 list_for_each_entry(obj, list, member) { \
ca1543be 313 size += i915_gem_obj_total_ggtt_size(obj); \
6299f992
CW		 314 ++count; \
315 if (obj->map_and_fenceable) { \
f343c5f6 316 mappable_size += i915_gem_obj_ggtt_size(obj); \
6299f992
CW		 317 ++mappable_count; \
318 } \
319 } \
0206e353 320} while (0)
6299f992 321
2db8e9d6 322struct file_stats {
6313c204 323 struct drm_i915_file_private *file_priv;
c44ef60e
MK		 324 unsigned long count;
325 u64 total, unbound;
326 u64 global, shared;
327 u64 active, inactive;
2db8e9d6
CW		 328};
329
330static int per_file_stats(int id, void *ptr, void *data)
331{
332 struct drm_i915_gem_object *obj = ptr;
333 struct file_stats *stats = data;
6313c204 334 struct i915_vma *vma;
2db8e9d6
CW		 335
336 stats->count++;
337 stats->total += obj->base.size;
338
c67a17e9
CW		 339 if (obj->base.name || obj->base.dma_buf)
340 stats->shared += obj->base.size;
341
6313c204 342 if (USES_FULL_PPGTT(obj->base.dev)) {
1c7f4bca 343 list_for_each_entry(vma, &obj->vma_list, obj_link) {
6313c204
CW		 344 struct i915_hw_ppgtt *ppgtt;
345
346 if (!drm_mm_node_allocated(&vma->node))
347 continue;
348
596c5923 349 if (vma->is_ggtt) {
6313c204
CW		 350 stats->global += obj->base.size;
351 continue;
352 }
353
354 ppgtt = container_of(vma->vm, struct i915_hw_ppgtt, base);
4d884705 355 if (ppgtt->file_priv != stats->file_priv)
6313c204
CW		 356 continue;
357
41c52415 358 if (obj->active) /* XXX per-vma statistic */
6313c204
CW		 359 stats->active += obj->base.size;
360 else
361 stats->inactive += obj->base.size;
362
363 return 0;
364 }
2db8e9d6 365 } else {
6313c204
CW		 366 if (i915_gem_obj_ggtt_bound(obj)) {
367 stats->global += obj->base.size;
41c52415 368 if (obj->active)
6313c204
CW		 369 stats->active += obj->base.size;
370 else
371 stats->inactive += obj->base.size;
372 return 0;
373 }
2db8e9d6
CW		 374 }
375
6313c204
CW		 376 if (!list_empty(&obj->global_list))
377 stats->unbound += obj->base.size;
378
2db8e9d6
CW		 379 return 0;
380}
381
b0da1b79
CW		 382#define print_file_stats(m, name, stats) do { \
383 if (stats.count) \
c44ef60e 384 seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \
b0da1b79
CW		 385 name, \
386 stats.count, \
387 stats.total, \
388 stats.active, \
389 stats.inactive, \
390 stats.global, \
391 stats.shared, \
392 stats.unbound); \
393} while (0)
493018dc
BV		 394
395static void print_batch_pool_stats(struct seq_file *m,
396 struct drm_i915_private *dev_priv)
397{
398 struct drm_i915_gem_object *obj;
399 struct file_stats stats;
e2f80391 400 struct intel_engine_cs *engine;
8d9d5744 401 int i, j;
493018dc
BV		 402
403 memset(&stats, 0, sizeof(stats));
404
666796da 405 for_each_engine(engine, dev_priv, i) {
e2f80391 406 for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
8d9d5744 407 list_for_each_entry(obj,
e2f80391 408 &engine->batch_pool.cache_list[j],
8d9d5744
CW		 409 batch_pool_link)
410 per_file_stats(0, obj, &stats);
411 }
06fbca71 412 }
493018dc 413
b0da1b79 414 print_file_stats(m, "[k]batch pool", stats);
493018dc
BV		 415}
416
ca191b13
BW		 417#define count_vmas(list, member) do { \
418 list_for_each_entry(vma, list, member) { \
ca1543be 419 size += i915_gem_obj_total_ggtt_size(vma->obj); \
ca191b13
BW		 420 ++count; \
421 if (vma->obj->map_and_fenceable) { \
422 mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
423 ++mappable_count; \
424 } \
425 } \
426} while (0)
427
428static int i915_gem_object_info(struct seq_file *m, void* data)
73aa808f 429{
9f25d007 430 struct drm_info_node *node = m->private;
73aa808f
CW		 431 struct drm_device *dev = node->minor->dev;
432 struct drm_i915_private *dev_priv = dev->dev_private;
b7abb714 433 u32 count, mappable_count, purgeable_count;
c44ef60e 434 u64 size, mappable_size, purgeable_size;
6299f992 435 struct drm_i915_gem_object *obj;
62106b4f 436 struct i915_address_space *vm = &dev_priv->ggtt.base;
2db8e9d6 437 struct drm_file *file;
ca191b13 438 struct i915_vma *vma;
73aa808f
CW		 439 int ret;
440
441 ret = mutex_lock_interruptible(&dev->struct_mutex);
442 if (ret)
443 return ret;
444
6299f992
CW		 445 seq_printf(m, "%u objects, %zu bytes\n",
446 dev_priv->mm.object_count,
447 dev_priv->mm.object_memory);
448
449 size = count = mappable_size = mappable_count = 0;
35c20a60 450 count_objects(&dev_priv->mm.bound_list, global_list);
c44ef60e 451 seq_printf(m, "%u [%u] objects, %llu [%llu] bytes in gtt\n",
6299f992
CW		 452 count, mappable_count, size, mappable_size);
453
454 size = count = mappable_size = mappable_count = 0;
1c7f4bca 455 count_vmas(&vm->active_list, vm_link);
c44ef60e 456 seq_printf(m, " %u [%u] active objects, %llu [%llu] bytes\n",
6299f992
CW		 457 count, mappable_count, size, mappable_size);
458
6299f992 459 size = count = mappable_size = mappable_count = 0;
1c7f4bca 460 count_vmas(&vm->inactive_list, vm_link);
c44ef60e 461 seq_printf(m, " %u [%u] inactive objects, %llu [%llu] bytes\n",
6299f992
CW		 462 count, mappable_count, size, mappable_size);
463
b7abb714 464 size = count = purgeable_size = purgeable_count = 0;
35c20a60 465 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
6c085a72 466 size += obj->base.size, ++count;
b7abb714
CW		 467 if (obj->madv == I915_MADV_DONTNEED)
468 purgeable_size += obj->base.size, ++purgeable_count;
469 }
c44ef60e 470 seq_printf(m, "%u unbound objects, %llu bytes\n", count, size);
6c085a72 471
6299f992 472 size = count = mappable_size = mappable_count = 0;
35c20a60 473 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
6299f992 474 if (obj->fault_mappable) {
f343c5f6 475 size += i915_gem_obj_ggtt_size(obj);
6299f992
CW		 476 ++count;
477 }
30154650 478 if (obj->pin_display) {
f343c5f6 479 mappable_size += i915_gem_obj_ggtt_size(obj);
6299f992
CW		 480 ++mappable_count;
481 }
b7abb714
CW		 482 if (obj->madv == I915_MADV_DONTNEED) {
483 purgeable_size += obj->base.size;
484 ++purgeable_count;
485 }
6299f992 486 }
c44ef60e 487 seq_printf(m, "%u purgeable objects, %llu bytes\n",
b7abb714 488 purgeable_count, purgeable_size);
c44ef60e 489 seq_printf(m, "%u pinned mappable objects, %llu bytes\n",
6299f992 490 mappable_count, mappable_size);
c44ef60e 491 seq_printf(m, "%u fault mappable objects, %llu bytes\n",
6299f992
CW		 492 count, size);
493
c44ef60e 494 seq_printf(m, "%llu [%llu] gtt total\n",
62106b4f
JL		 495 dev_priv->ggtt.base.total,
496 (u64)dev_priv->ggtt.mappable_end - dev_priv->ggtt.base.start);
73aa808f 497
493018dc
BV		 498 seq_putc(m, '\n');
499 print_batch_pool_stats(m, dev_priv);
2db8e9d6
CW		 500 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
501 struct file_stats stats;
3ec2f427 502 struct task_struct *task;
2db8e9d6
CW		 503
504 memset(&stats, 0, sizeof(stats));
6313c204 505 stats.file_priv = file->driver_priv;
5b5ffff0 506 spin_lock(&file->table_lock);
2db8e9d6 507 idr_for_each(&file->object_idr, per_file_stats, &stats);
5b5ffff0 508 spin_unlock(&file->table_lock);
3ec2f427
TH		 509 /*
510 * Although we have a valid reference on file->pid, that does
511 * not guarantee that the task_struct who called get_pid() is
512 * still alive (e.g. get_pid(current) => fork() => exit()).
513 * Therefore, we need to protect this ->comm access using RCU.
514 */
515 rcu_read_lock();
516 task = pid_task(file->pid, PIDTYPE_PID);
493018dc 517 print_file_stats(m, task ? task->comm : "<unknown>", stats);
3ec2f427 518 rcu_read_unlock();
2db8e9d6
CW		 519 }
520
73aa808f
CW		 521 mutex_unlock(&dev->struct_mutex);
522
523 return 0;
524}
525
aee56cff 526static int i915_gem_gtt_info(struct seq_file *m, void *data)
08c18323 527{
9f25d007 528 struct drm_info_node *node = m->private;
08c18323 529 struct drm_device *dev = node->minor->dev;
1b50247a 530 uintptr_t list = (uintptr_t) node->info_ent->data;
08c18323
CW		 531 struct drm_i915_private *dev_priv = dev->dev_private;
532 struct drm_i915_gem_object *obj;
c44ef60e 533 u64 total_obj_size, total_gtt_size;
08c18323
CW		 534 int count, ret;
535
536 ret = mutex_lock_interruptible(&dev->struct_mutex);
537 if (ret)
538 return ret;
539
540 total_obj_size = total_gtt_size = count = 0;
35c20a60 541 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
d7f46fc4 542 if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj))
1b50247a
CW		 543 continue;
544
267f0c90 545 seq_puts(m, " ");
08c18323 546 describe_obj(m, obj);
267f0c90 547 seq_putc(m, '\n');
08c18323 548 total_obj_size += obj->base.size;
ca1543be 549 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
08c18323
CW		 550 count++;
551 }
552
553 mutex_unlock(&dev->struct_mutex);
554
c44ef60e 555 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
08c18323
CW		 556 count, total_obj_size, total_gtt_size);
557
558 return 0;
559}
560
4e5359cd
SF		 561static int i915_gem_pageflip_info(struct seq_file *m, void *data)
562{
9f25d007 563 struct drm_info_node *node = m->private;
4e5359cd 564 struct drm_device *dev = node->minor->dev;
d6bbafa1 565 struct drm_i915_private *dev_priv = dev->dev_private;
4e5359cd 566 struct intel_crtc *crtc;
8a270ebf
DV		 567 int ret;
568
569 ret = mutex_lock_interruptible(&dev->struct_mutex);
570 if (ret)
571 return ret;
4e5359cd 572
d3fcc808 573 for_each_intel_crtc(dev, crtc) {
9db4a9c7
JB		 574 const char pipe = pipe_name(crtc->pipe);
575 const char plane = plane_name(crtc->plane);
4e5359cd
SF		 576 struct intel_unpin_work *work;
577
5e2d7afc 578 spin_lock_irq(&dev->event_lock);
4e5359cd
SF		 579 work = crtc->unpin_work;
580 if (work == NULL) {
9db4a9c7 581 seq_printf(m, "No flip due on pipe %c (plane %c)\n",
4e5359cd
SF		 582 pipe, plane);
583 } else {
d6bbafa1
CW		 584 u32 addr;
585
e7d841ca 586 if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9db4a9c7 587 seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
4e5359cd
SF		 588 pipe, plane);
589 } else {
9db4a9c7 590 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
4e5359cd
SF		 591 pipe, plane);
592 }
3a8a946e 593 if (work->flip_queued_req) {
666796da 594 struct intel_engine_cs *engine = i915_gem_request_get_engine(work->flip_queued_req);
3a8a946e 595
20e28fba 596 seq_printf(m, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n",
e2f80391 597 engine->name,
f06cc1b9 598 i915_gem_request_get_seqno(work->flip_queued_req),
d6bbafa1 599 dev_priv->next_seqno,
e2f80391 600 engine->get_seqno(engine, true),
1b5a433a 601 i915_gem_request_completed(work->flip_queued_req, true));
d6bbafa1
CW		 602 } else
603 seq_printf(m, "Flip not associated with any ring\n");
604 seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
605 work->flip_queued_vblank,
606 work->flip_ready_vblank,
1e3feefd 607 drm_crtc_vblank_count(&crtc->base));
4e5359cd 608 if (work->enable_stall_check)
267f0c90 609 seq_puts(m, "Stall check enabled, ");
4e5359cd 610 else
267f0c90 611 seq_puts(m, "Stall check waiting for page flip ioctl, ");
e7d841ca 612 seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
4e5359cd 613
d6bbafa1
CW		 614 if (INTEL_INFO(dev)->gen >= 4)
615 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane)));
616 else
617 addr = I915_READ(DSPADDR(crtc->plane));
618 seq_printf(m, "Current scanout address 0x%08x\n", addr);
619
4e5359cd 620 if (work->pending_flip_obj) {
d6bbafa1
CW		 621 seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset);
622 seq_printf(m, "MMIO update completed? %d\n", addr == work->gtt_offset);
4e5359cd
SF		 623 }
624 }
5e2d7afc 625 spin_unlock_irq(&dev->event_lock);
4e5359cd
SF		 626 }
627
8a270ebf
DV		 628 mutex_unlock(&dev->struct_mutex);
629
4e5359cd
SF		 630 return 0;
631}
632
493018dc
BV		 633static int i915_gem_batch_pool_info(struct seq_file *m, void *data)
634{
635 struct drm_info_node *node = m->private;
636 struct drm_device *dev = node->minor->dev;
637 struct drm_i915_private *dev_priv = dev->dev_private;
638 struct drm_i915_gem_object *obj;
e2f80391 639 struct intel_engine_cs *engine;
8d9d5744
CW		 640 int total = 0;
641 int ret, i, j;
493018dc
BV		 642
643 ret = mutex_lock_interruptible(&dev->struct_mutex);
644 if (ret)
645 return ret;
646
666796da 647 for_each_engine(engine, dev_priv, i) {
e2f80391 648 for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
8d9d5744
CW		 649 int count;
650
651 count = 0;
652 list_for_each_entry(obj,
e2f80391 653 &engine->batch_pool.cache_list[j],
8d9d5744
CW		 654 batch_pool_link)
655 count++;
656 seq_printf(m, "%s cache[%d]: %d objects\n",
e2f80391 657 engine->name, j, count);
8d9d5744
CW		 658
659 list_for_each_entry(obj,
e2f80391 660 &engine->batch_pool.cache_list[j],
8d9d5744
CW		 661 batch_pool_link) {
662 seq_puts(m, " ");
663 describe_obj(m, obj);
664 seq_putc(m, '\n');
665 }
666
667 total += count;
06fbca71 668 }
493018dc
BV		 669 }
670
8d9d5744 671 seq_printf(m, "total: %d\n", total);
493018dc
BV		 672
673 mutex_unlock(&dev->struct_mutex);
674
675 return 0;
676}
677
2017263e
BG		 678static int i915_gem_request_info(struct seq_file *m, void *data)
679{
9f25d007 680 struct drm_info_node *node = m->private;
2017263e 681 struct drm_device *dev = node->minor->dev;
e277a1f8 682 struct drm_i915_private *dev_priv = dev->dev_private;
e2f80391 683 struct intel_engine_cs *engine;
eed29a5b 684 struct drm_i915_gem_request *req;
2d1070b2 685 int ret, any, i;
de227ef0
CW		 686
687 ret = mutex_lock_interruptible(&dev->struct_mutex);
688 if (ret)
689 return ret;
2017263e 690
2d1070b2 691 any = 0;
666796da 692 for_each_engine(engine, dev_priv, i) {
2d1070b2
CW		 693 int count;
694
695 count = 0;
e2f80391 696 list_for_each_entry(req, &engine->request_list, list)
2d1070b2
CW		 697 count++;
698 if (count == 0)
a2c7f6fd
CW		 699 continue;
700
e2f80391
TU		 701 seq_printf(m, "%s requests: %d\n", engine->name, count);
702 list_for_each_entry(req, &engine->request_list, list) {
2d1070b2
CW		 703 struct task_struct *task;
704
705 rcu_read_lock();
706 task = NULL;
eed29a5b
DV		 707 if (req->pid)
708 task = pid_task(req->pid, PIDTYPE_PID);
2d1070b2 709 seq_printf(m, " %x @ %d: %s [%d]\n",
eed29a5b
DV		 710 req->seqno,
711 (int) (jiffies - req->emitted_jiffies),
2d1070b2
CW		 712 task ? task->comm : "<unknown>",
713 task ? task->pid : -1);
714 rcu_read_unlock();
c2c347a9 715 }
2d1070b2
CW		 716
717 any++;
2017263e 718 }
de227ef0
CW		 719 mutex_unlock(&dev->struct_mutex);
720
2d1070b2 721 if (any == 0)
267f0c90 722 seq_puts(m, "No requests\n");
c2c347a9 723
2017263e
BG		 724 return 0;
725}
726
b2223497 727static void i915_ring_seqno_info(struct seq_file *m,
0bc40be8 728 struct intel_engine_cs *engine)
b2223497 729{
0bc40be8 730 if (engine->get_seqno) {
20e28fba 731 seq_printf(m, "Current sequence (%s): %x\n",
0bc40be8 732 engine->name, engine->get_seqno(engine, false));
b2223497
CW		 733 }
734}
735
2017263e
BG		 736static int i915_gem_seqno_info(struct seq_file *m, void *data)
737{
9f25d007 738 struct drm_info_node *node = m->private;
2017263e 739 struct drm_device *dev = node->minor->dev;
e277a1f8 740 struct drm_i915_private *dev_priv = dev->dev_private;
e2f80391 741 struct intel_engine_cs *engine;
1ec14ad3 742 int ret, i;
de227ef0
CW		 743
744 ret = mutex_lock_interruptible(&dev->struct_mutex);
745 if (ret)
746 return ret;
c8c8fb33 747 intel_runtime_pm_get(dev_priv);
2017263e 748
666796da 749 for_each_engine(engine, dev_priv, i)
e2f80391 750 i915_ring_seqno_info(m, engine);
de227ef0 751
c8c8fb33 752 intel_runtime_pm_put(dev_priv);
de227ef0
CW		 753 mutex_unlock(&dev->struct_mutex);
754
2017263e
BG		 755 return 0;
756}
757
758
759static int i915_interrupt_info(struct seq_file *m, void *data)
760{
9f25d007 761 struct drm_info_node *node = m->private;
2017263e 762 struct drm_device *dev = node->minor->dev;
e277a1f8 763 struct drm_i915_private *dev_priv = dev->dev_private;
e2f80391 764 struct intel_engine_cs *engine;
9db4a9c7 765 int ret, i, pipe;
de227ef0
CW		 766
767 ret = mutex_lock_interruptible(&dev->struct_mutex);
768 if (ret)
769 return ret;
c8c8fb33 770 intel_runtime_pm_get(dev_priv);
2017263e 771
74e1ca8c 772 if (IS_CHERRYVIEW(dev)) {
74e1ca8c
VS		 773 seq_printf(m, "Master Interrupt Control:\t%08x\n",
774 I915_READ(GEN8_MASTER_IRQ));
775
776 seq_printf(m, "Display IER:\t%08x\n",
777 I915_READ(VLV_IER));
778 seq_printf(m, "Display IIR:\t%08x\n",
779 I915_READ(VLV_IIR));
780 seq_printf(m, "Display IIR_RW:\t%08x\n",
781 I915_READ(VLV_IIR_RW));
782 seq_printf(m, "Display IMR:\t%08x\n",
783 I915_READ(VLV_IMR));
055e393f 784 for_each_pipe(dev_priv, pipe)
74e1ca8c
VS		 785 seq_printf(m, "Pipe %c stat:\t%08x\n",
786 pipe_name(pipe),
787 I915_READ(PIPESTAT(pipe)));
788
789 seq_printf(m, "Port hotplug:\t%08x\n",
790 I915_READ(PORT_HOTPLUG_EN));
791 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
792 I915_READ(VLV_DPFLIPSTAT));
793 seq_printf(m, "DPINVGTT:\t%08x\n",
794 I915_READ(DPINVGTT));
795
796 for (i = 0; i < 4; i++) {
797 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
798 i, I915_READ(GEN8_GT_IMR(i)));
799 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
800 i, I915_READ(GEN8_GT_IIR(i)));
801 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
802 i, I915_READ(GEN8_GT_IER(i)));
803 }
804
805 seq_printf(m, "PCU interrupt mask:\t%08x\n",
806 I915_READ(GEN8_PCU_IMR));
807 seq_printf(m, "PCU interrupt identity:\t%08x\n",
808 I915_READ(GEN8_PCU_IIR));
809 seq_printf(m, "PCU interrupt enable:\t%08x\n",
810 I915_READ(GEN8_PCU_IER));
811 } else if (INTEL_INFO(dev)->gen >= 8) {
a123f157
BW		 812 seq_printf(m, "Master Interrupt Control:\t%08x\n",
813 I915_READ(GEN8_MASTER_IRQ));
814
815 for (i = 0; i < 4; i++) {
816 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
817 i, I915_READ(GEN8_GT_IMR(i)));
818 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
819 i, I915_READ(GEN8_GT_IIR(i)));
820 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
821 i, I915_READ(GEN8_GT_IER(i)));
822 }
823
055e393f 824 for_each_pipe(dev_priv, pipe) {
e129649b
ID		 825 enum intel_display_power_domain power_domain;
826
827 power_domain = POWER_DOMAIN_PIPE(pipe);
828 if (!intel_display_power_get_if_enabled(dev_priv,
829 power_domain)) {
22c59960
PZ		 830 seq_printf(m, "Pipe %c power disabled\n",
831 pipe_name(pipe));
832 continue;
833 }
a123f157 834 seq_printf(m, "Pipe %c IMR:\t%08x\n",
07d27e20
DL		 835 pipe_name(pipe),
836 I915_READ(GEN8_DE_PIPE_IMR(pipe)));
a123f157 837 seq_printf(m, "Pipe %c IIR:\t%08x\n",
07d27e20
DL		 838 pipe_name(pipe),
839 I915_READ(GEN8_DE_PIPE_IIR(pipe)));
a123f157 840 seq_printf(m, "Pipe %c IER:\t%08x\n",
07d27e20
DL		 841 pipe_name(pipe),
842 I915_READ(GEN8_DE_PIPE_IER(pipe)));
e129649b
ID		 843
844 intel_display_power_put(dev_priv, power_domain);
a123f157
BW		 845 }
846
847 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
848 I915_READ(GEN8_DE_PORT_IMR));
849 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
850 I915_READ(GEN8_DE_PORT_IIR));
851 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
852 I915_READ(GEN8_DE_PORT_IER));
853
854 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
855 I915_READ(GEN8_DE_MISC_IMR));
856 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
857 I915_READ(GEN8_DE_MISC_IIR));
858 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
859 I915_READ(GEN8_DE_MISC_IER));
860
861 seq_printf(m, "PCU interrupt mask:\t%08x\n",
862 I915_READ(GEN8_PCU_IMR));
863 seq_printf(m, "PCU interrupt identity:\t%08x\n",
864 I915_READ(GEN8_PCU_IIR));
865 seq_printf(m, "PCU interrupt enable:\t%08x\n",
866 I915_READ(GEN8_PCU_IER));
867 } else if (IS_VALLEYVIEW(dev)) {
7e231dbe
JB		 868 seq_printf(m, "Display IER:\t%08x\n",
869 I915_READ(VLV_IER));
870 seq_printf(m, "Display IIR:\t%08x\n",
871 I915_READ(VLV_IIR));
872 seq_printf(m, "Display IIR_RW:\t%08x\n",
873 I915_READ(VLV_IIR_RW));
874 seq_printf(m, "Display IMR:\t%08x\n",
875 I915_READ(VLV_IMR));
055e393f 876 for_each_pipe(dev_priv, pipe)
7e231dbe
JB		 877 seq_printf(m, "Pipe %c stat:\t%08x\n",
878 pipe_name(pipe),
879 I915_READ(PIPESTAT(pipe)));
880
881 seq_printf(m, "Master IER:\t%08x\n",
882 I915_READ(VLV_MASTER_IER));
883
884 seq_printf(m, "Render IER:\t%08x\n",
885 I915_READ(GTIER));
886 seq_printf(m, "Render IIR:\t%08x\n",
887 I915_READ(GTIIR));
888 seq_printf(m, "Render IMR:\t%08x\n",
889 I915_READ(GTIMR));
890
891 seq_printf(m, "PM IER:\t\t%08x\n",
892 I915_READ(GEN6_PMIER));
893 seq_printf(m, "PM IIR:\t\t%08x\n",
894 I915_READ(GEN6_PMIIR));
895 seq_printf(m, "PM IMR:\t\t%08x\n",
896 I915_READ(GEN6_PMIMR));
897
898 seq_printf(m, "Port hotplug:\t%08x\n",
899 I915_READ(PORT_HOTPLUG_EN));
900 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
901 I915_READ(VLV_DPFLIPSTAT));
902 seq_printf(m, "DPINVGTT:\t%08x\n",
903 I915_READ(DPINVGTT));
904
905 } else if (!HAS_PCH_SPLIT(dev)) {
5f6a1695
ZW		 906 seq_printf(m, "Interrupt enable: %08x\n",
907 I915_READ(IER));
908 seq_printf(m, "Interrupt identity: %08x\n",
909 I915_READ(IIR));
910 seq_printf(m, "Interrupt mask: %08x\n",
911 I915_READ(IMR));
055e393f 912 for_each_pipe(dev_priv, pipe)
9db4a9c7
JB		 913 seq_printf(m, "Pipe %c stat: %08x\n",
914 pipe_name(pipe),
915 I915_READ(PIPESTAT(pipe)));
5f6a1695
ZW		 916 } else {
917 seq_printf(m, "North Display Interrupt enable: %08x\n",
918 I915_READ(DEIER));
919 seq_printf(m, "North Display Interrupt identity: %08x\n",
920 I915_READ(DEIIR));
921 seq_printf(m, "North Display Interrupt mask: %08x\n",
922 I915_READ(DEIMR));
923 seq_printf(m, "South Display Interrupt enable: %08x\n",
924 I915_READ(SDEIER));
925 seq_printf(m, "South Display Interrupt identity: %08x\n",
926 I915_READ(SDEIIR));
927 seq_printf(m, "South Display Interrupt mask: %08x\n",
928 I915_READ(SDEIMR));
929 seq_printf(m, "Graphics Interrupt enable: %08x\n",
930 I915_READ(GTIER));
931 seq_printf(m, "Graphics Interrupt identity: %08x\n",
932 I915_READ(GTIIR));
933 seq_printf(m, "Graphics Interrupt mask: %08x\n",
934 I915_READ(GTIMR));
935 }
666796da 936 for_each_engine(engine, dev_priv, i) {
a123f157 937 if (INTEL_INFO(dev)->gen >= 6) {
a2c7f6fd
CW		 938 seq_printf(m,
939 "Graphics Interrupt mask (%s): %08x\n",
e2f80391 940 engine->name, I915_READ_IMR(engine));
9862e600 941 }
e2f80391 942 i915_ring_seqno_info(m, engine);
9862e600 943 }
c8c8fb33 944 intel_runtime_pm_put(dev_priv);
de227ef0
CW		 945 mutex_unlock(&dev->struct_mutex);
946
2017263e
BG		 947 return 0;
948}
949
a6172a80
CW		 950static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
951{
9f25d007 952 struct drm_info_node *node = m->private;
a6172a80 953 struct drm_device *dev = node->minor->dev;
e277a1f8 954 struct drm_i915_private *dev_priv = dev->dev_private;
de227ef0
CW		 955 int i, ret;
956
957 ret = mutex_lock_interruptible(&dev->struct_mutex);
958 if (ret)
959 return ret;
a6172a80 960
a6172a80
CW		 961 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
962 for (i = 0; i < dev_priv->num_fence_regs; i++) {
05394f39 963 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
a6172a80 964
6c085a72
CW		 965 seq_printf(m, "Fence %d, pin count = %d, object = ",
966 i, dev_priv->fence_regs[i].pin_count);
c2c347a9 967 if (obj == NULL)
267f0c90 968 seq_puts(m, "unused");
c2c347a9 969 else
05394f39 970 describe_obj(m, obj);
267f0c90 971 seq_putc(m, '\n');
a6172a80
CW		 972 }
973
05394f39 974 mutex_unlock(&dev->struct_mutex);
a6172a80
CW		 975 return 0;
976}
977
2017263e
BG		 978static int i915_hws_info(struct seq_file *m, void *data)
979{
9f25d007 980 struct drm_info_node *node = m->private;
2017263e 981 struct drm_device *dev = node->minor->dev;
e277a1f8 982 struct drm_i915_private *dev_priv = dev->dev_private;
e2f80391 983 struct intel_engine_cs *engine;
1a240d4d 984 const u32 *hws;
4066c0ae
CW		 985 int i;
986
4a570db5 987 engine = &dev_priv->engine[(uintptr_t)node->info_ent->data];
e2f80391 988 hws = engine->status_page.page_addr;
2017263e
BG		 989 if (hws == NULL)
990 return 0;
991
992 for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
993 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
994 i * 4,
995 hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
996 }
997 return 0;
998}
999
d5442303
DV		 1000static ssize_t
1001i915_error_state_write(struct file *filp,
1002 const char __user *ubuf,
1003 size_t cnt,
1004 loff_t *ppos)
1005{
edc3d884 1006 struct i915_error_state_file_priv *error_priv = filp->private_data;
d5442303 1007 struct drm_device *dev = error_priv->dev;
22bcfc6a 1008 int ret;
d5442303
DV		 1009
1010 DRM_DEBUG_DRIVER("Resetting error state\n");
1011
22bcfc6a
DV		 1012 ret = mutex_lock_interruptible(&dev->struct_mutex);
1013 if (ret)
1014 return ret;
1015
d5442303
DV		 1016 i915_destroy_error_state(dev);
1017 mutex_unlock(&dev->struct_mutex);
1018
1019 return cnt;
1020}
1021
1022static int i915_error_state_open(struct inode *inode, struct file *file)
1023{
1024 struct drm_device *dev = inode->i_private;
d5442303 1025 struct i915_error_state_file_priv *error_priv;
d5442303
DV		 1026
1027 error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
1028 if (!error_priv)
1029 return -ENOMEM;
1030
1031 error_priv->dev = dev;
1032
95d5bfb3 1033 i915_error_state_get(dev, error_priv);
d5442303 1034
edc3d884
MK		 1035 file->private_data = error_priv;
1036
1037 return 0;
d5442303
DV		 1038}
1039
1040static int i915_error_state_release(struct inode *inode, struct file *file)
1041{
edc3d884 1042 struct i915_error_state_file_priv *error_priv = file->private_data;
d5442303 1043
95d5bfb3 1044 i915_error_state_put(error_priv);
d5442303
DV		 1045 kfree(error_priv);
1046
edc3d884
MK		 1047 return 0;
1048}
1049
4dc955f7
MK		 1050static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
1051 size_t count, loff_t *pos)
1052{
1053 struct i915_error_state_file_priv *error_priv = file->private_data;
1054 struct drm_i915_error_state_buf error_str;
1055 loff_t tmp_pos = 0;
1056 ssize_t ret_count = 0;
1057 int ret;
1058
0a4cd7c8 1059 ret = i915_error_state_buf_init(&error_str, to_i915(error_priv->dev), count, *pos);
4dc955f7
MK		 1060 if (ret)
1061 return ret;
edc3d884 1062
fc16b48b 1063 ret = i915_error_state_to_str(&error_str, error_priv);
edc3d884
MK		 1064 if (ret)
1065 goto out;
1066
edc3d884
MK		 1067 ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
1068 error_str.buf,
1069 error_str.bytes);
1070
1071 if (ret_count < 0)
1072 ret = ret_count;
1073 else
1074 *pos = error_str.start + ret_count;
1075out:
4dc955f7 1076 i915_error_state_buf_release(&error_str);
edc3d884 1077 return ret ?: ret_count;
d5442303
DV		 1078}
1079
1080static const struct file_operations i915_error_state_fops = {
1081 .owner = THIS_MODULE,
1082 .open = i915_error_state_open,
edc3d884 1083 .read = i915_error_state_read,
d5442303
DV		 1084 .write = i915_error_state_write,
1085 .llseek = default_llseek,
1086 .release = i915_error_state_release,
1087};
1088
647416f9
KC		 1089static int
1090i915_next_seqno_get(void *data, u64 *val)
40633219 1091{
647416f9 1092 struct drm_device *dev = data;
e277a1f8 1093 struct drm_i915_private *dev_priv = dev->dev_private;
40633219
MK		 1094 int ret;
1095
1096 ret = mutex_lock_interruptible(&dev->struct_mutex);
1097 if (ret)
1098 return ret;
1099
647416f9 1100 *val = dev_priv->next_seqno;
40633219
MK		 1101 mutex_unlock(&dev->struct_mutex);
1102
647416f9 1103 return 0;
40633219
MK		 1104}
1105
647416f9
KC		 1106static int
1107i915_next_seqno_set(void *data, u64 val)
1108{
1109 struct drm_device *dev = data;
40633219
MK		 1110 int ret;
1111
40633219
MK		 1112 ret = mutex_lock_interruptible(&dev->struct_mutex);
1113 if (ret)
1114 return ret;
1115
e94fbaa8 1116 ret = i915_gem_set_seqno(dev, val);
40633219
MK		 1117 mutex_unlock(&dev->struct_mutex);
1118
647416f9 1119 return ret;
40633219
MK		 1120}
1121
647416f9
KC		 1122DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
1123 i915_next_seqno_get, i915_next_seqno_set,
3a3b4f98 1124 "0x%llx\n");
40633219 1125
adb4bd12 1126static int i915_frequency_info(struct seq_file *m, void *unused)
f97108d1 1127{
9f25d007 1128 struct drm_info_node *node = m->private;
f97108d1 1129 struct drm_device *dev = node->minor->dev;
e277a1f8 1130 struct drm_i915_private *dev_priv = dev->dev_private;
c8c8fb33
PZ		 1131 int ret = 0;
1132
1133 intel_runtime_pm_get(dev_priv);
3b8d8d91 1134
5c9669ce
TR		 1135 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1136
3b8d8d91
JB		 1137 if (IS_GEN5(dev)) {
1138 u16 rgvswctl = I915_READ16(MEMSWCTL);
1139 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1140
1141 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1142 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1143 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1144 MEMSTAT_VID_SHIFT);
1145 seq_printf(m, "Current P-state: %d\n",
1146 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
666a4537
WB		 1147 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1148 u32 freq_sts;
1149
1150 mutex_lock(&dev_priv->rps.hw_lock);
1151 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
1152 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1153 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1154
1155 seq_printf(m, "actual GPU freq: %d MHz\n",
1156 intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
1157
1158 seq_printf(m, "current GPU freq: %d MHz\n",
1159 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1160
1161 seq_printf(m, "max GPU freq: %d MHz\n",
1162 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1163
1164 seq_printf(m, "min GPU freq: %d MHz\n",
1165 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1166
1167 seq_printf(m, "idle GPU freq: %d MHz\n",
1168 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1169
1170 seq_printf(m,
1171 "efficient (RPe) frequency: %d MHz\n",
1172 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1173 mutex_unlock(&dev_priv->rps.hw_lock);
1174 } else if (INTEL_INFO(dev)->gen >= 6) {
35040562
BP		 1175 u32 rp_state_limits;
1176 u32 gt_perf_status;
1177 u32 rp_state_cap;
0d8f9491 1178 u32 rpmodectl, rpinclimit, rpdeclimit;
8e8c06cd 1179 u32 rpstat, cagf, reqf;
ccab5c82
JB		 1180 u32 rpupei, rpcurup, rpprevup;
1181 u32 rpdownei, rpcurdown, rpprevdown;
9dd3c605 1182 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
3b8d8d91
JB		 1183 int max_freq;
1184
35040562
BP		 1185 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1186 if (IS_BROXTON(dev)) {
1187 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
1188 gt_perf_status = I915_READ(BXT_GT_PERF_STATUS);
1189 } else {
1190 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
1191 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1192 }
1193
3b8d8d91 1194 /* RPSTAT1 is in the GT power well */
d1ebd816
BW		 1195 ret = mutex_lock_interruptible(&dev->struct_mutex);
1196 if (ret)
c8c8fb33 1197 goto out;
d1ebd816 1198
59bad947 1199 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
3b8d8d91 1200
8e8c06cd 1201 reqf = I915_READ(GEN6_RPNSWREQ);
60260a5b
AG		 1202 if (IS_GEN9(dev))
1203 reqf >>= 23;
1204 else {
1205 reqf &= ~GEN6_TURBO_DISABLE;
1206 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1207 reqf >>= 24;
1208 else
1209 reqf >>= 25;
1210 }
7c59a9c1 1211 reqf = intel_gpu_freq(dev_priv, reqf);
8e8c06cd 1212
0d8f9491
CW		 1213 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1214 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1215 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1216
ccab5c82
JB		 1217 rpstat = I915_READ(GEN6_RPSTAT1);
1218 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
1219 rpcurup = I915_READ(GEN6_RP_CUR_UP);
1220 rpprevup = I915_READ(GEN6_RP_PREV_UP);
1221 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
1222 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
1223 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
60260a5b
AG		 1224 if (IS_GEN9(dev))
1225 cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
1226 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
f82855d3
BW		 1227 cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1228 else
1229 cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
7c59a9c1 1230 cagf = intel_gpu_freq(dev_priv, cagf);
ccab5c82 1231
59bad947 1232 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
d1ebd816
BW		 1233 mutex_unlock(&dev->struct_mutex);
1234
9dd3c605
PZ		 1235 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1236 pm_ier = I915_READ(GEN6_PMIER);
1237 pm_imr = I915_READ(GEN6_PMIMR);
1238 pm_isr = I915_READ(GEN6_PMISR);
1239 pm_iir = I915_READ(GEN6_PMIIR);
1240 pm_mask = I915_READ(GEN6_PMINTRMSK);
1241 } else {
1242 pm_ier = I915_READ(GEN8_GT_IER(2));
1243 pm_imr = I915_READ(GEN8_GT_IMR(2));
1244 pm_isr = I915_READ(GEN8_GT_ISR(2));
1245 pm_iir = I915_READ(GEN8_GT_IIR(2));
1246 pm_mask = I915_READ(GEN6_PMINTRMSK);
1247 }
0d8f9491 1248 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
9dd3c605 1249 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
3b8d8d91 1250 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
3b8d8d91 1251 seq_printf(m, "Render p-state ratio: %d\n",
60260a5b 1252 (gt_perf_status & (IS_GEN9(dev) ? 0x1ff00 : 0xff00)) >> 8);
3b8d8d91
JB		 1253 seq_printf(m, "Render p-state VID: %d\n",
1254 gt_perf_status & 0xff);
1255 seq_printf(m, "Render p-state limit: %d\n",
1256 rp_state_limits & 0xff);
0d8f9491
CW		 1257 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1258 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1259 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1260 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
8e8c06cd 1261 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
f82855d3 1262 seq_printf(m, "CAGF: %dMHz\n", cagf);
ccab5c82
JB		 1263 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
1264 GEN6_CURICONT_MASK);
1265 seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
1266 GEN6_CURBSYTAVG_MASK);
1267 seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
1268 GEN6_CURBSYTAVG_MASK);
d86ed34a
CW		 1269 seq_printf(m, "Up threshold: %d%%\n",
1270 dev_priv->rps.up_threshold);
1271
ccab5c82
JB		 1272 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
1273 GEN6_CURIAVG_MASK);
1274 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
1275 GEN6_CURBSYTAVG_MASK);
1276 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
1277 GEN6_CURBSYTAVG_MASK);
d86ed34a
CW		 1278 seq_printf(m, "Down threshold: %d%%\n",
1279 dev_priv->rps.down_threshold);
3b8d8d91 1280
35040562
BP		 1281 max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 0 :
1282 rp_state_cap >> 16) & 0xff;
ef11bdb3
RV		 1283 max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1284 GEN9_FREQ_SCALER : 1);
3b8d8d91 1285 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
7c59a9c1 1286 intel_gpu_freq(dev_priv, max_freq));
3b8d8d91
JB		 1287
1288 max_freq = (rp_state_cap & 0xff00) >> 8;
ef11bdb3
RV		 1289 max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1290 GEN9_FREQ_SCALER : 1);
3b8d8d91 1291 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
7c59a9c1 1292 intel_gpu_freq(dev_priv, max_freq));
3b8d8d91 1293
35040562
BP		 1294 max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 16 :
1295 rp_state_cap >> 0) & 0xff;
ef11bdb3
RV		 1296 max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1297 GEN9_FREQ_SCALER : 1);
3b8d8d91 1298 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
7c59a9c1 1299 intel_gpu_freq(dev_priv, max_freq));
31c77388 1300 seq_printf(m, "Max overclocked frequency: %dMHz\n",
7c59a9c1 1301 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
aed242ff 1302
d86ed34a
CW		 1303 seq_printf(m, "Current freq: %d MHz\n",
1304 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1305 seq_printf(m, "Actual freq: %d MHz\n", cagf);
aed242ff
CW		 1306 seq_printf(m, "Idle freq: %d MHz\n",
1307 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
d86ed34a
CW		 1308 seq_printf(m, "Min freq: %d MHz\n",
1309 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1310 seq_printf(m, "Max freq: %d MHz\n",
1311 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1312 seq_printf(m,
1313 "efficient (RPe) frequency: %d MHz\n",
1314 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
3b8d8d91 1315 } else {
267f0c90 1316 seq_puts(m, "no P-state info available\n");
3b8d8d91 1317 }
f97108d1 1318
1170f28c
MK		 1319 seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk_freq);
1320 seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq);
1321 seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq);
1322
c8c8fb33
PZ		 1323out:
1324 intel_runtime_pm_put(dev_priv);
1325 return ret;
f97108d1
JB		 1326}
1327
f654449a
CW		 1328static int i915_hangcheck_info(struct seq_file *m, void *unused)
1329{
1330 struct drm_info_node *node = m->private;
ebbc7546
MK		 1331 struct drm_device *dev = node->minor->dev;
1332 struct drm_i915_private *dev_priv = dev->dev_private;
e2f80391 1333 struct intel_engine_cs *engine;
666796da
TU		 1334 u64 acthd[I915_NUM_ENGINES];
1335 u32 seqno[I915_NUM_ENGINES];
61642ff0 1336 u32 instdone[I915_NUM_INSTDONE_REG];
c3232b18
DG		 1337 enum intel_engine_id id;
1338 int j;
f654449a
CW		 1339
1340 if (!i915.enable_hangcheck) {
1341 seq_printf(m, "Hangcheck disabled\n");
1342 return 0;
1343 }
1344
ebbc7546
MK		 1345 intel_runtime_pm_get(dev_priv);
1346
c3232b18
DG		 1347 for_each_engine_id(engine, dev_priv, id) {
1348 seqno[id] = engine->get_seqno(engine, false);
1349 acthd[id] = intel_ring_get_active_head(engine);
ebbc7546
MK		 1350 }
1351
61642ff0
MK		 1352 i915_get_extra_instdone(dev, instdone);
1353
ebbc7546
MK		 1354 intel_runtime_pm_put(dev_priv);
1355
f654449a
CW		 1356 if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) {
1357 seq_printf(m, "Hangcheck active, fires in %dms\n",
1358 jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires -
1359 jiffies));
1360 } else
1361 seq_printf(m, "Hangcheck inactive\n");
1362
c3232b18 1363 for_each_engine_id(engine, dev_priv, id) {
e2f80391 1364 seq_printf(m, "%s:\n", engine->name);
f654449a 1365 seq_printf(m, "\tseqno = %x [current %x]\n",
c3232b18 1366 engine->hangcheck.seqno, seqno[id]);
f654449a 1367 seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
e2f80391 1368 (long long)engine->hangcheck.acthd,
c3232b18 1369 (long long)acthd[id]);
e2f80391
TU		 1370 seq_printf(m, "\tscore = %d\n", engine->hangcheck.score);
1371 seq_printf(m, "\taction = %d\n", engine->hangcheck.action);
61642ff0 1372
e2f80391 1373 if (engine->id == RCS) {
61642ff0
MK		 1374 seq_puts(m, "\tinstdone read =");
1375
1376 for (j = 0; j < I915_NUM_INSTDONE_REG; j++)
1377 seq_printf(m, " 0x%08x", instdone[j]);
1378
1379 seq_puts(m, "\n\tinstdone accu =");
1380
1381 for (j = 0; j < I915_NUM_INSTDONE_REG; j++)
1382 seq_printf(m, " 0x%08x",
e2f80391 1383 engine->hangcheck.instdone[j]);
61642ff0
MK		 1384
1385 seq_puts(m, "\n");
1386 }
f654449a
CW		 1387 }
1388
1389 return 0;
1390}
1391
4d85529d 1392static int ironlake_drpc_info(struct seq_file *m)
f97108d1 1393{
9f25d007 1394 struct drm_info_node *node = m->private;
f97108d1 1395 struct drm_device *dev = node->minor->dev;
e277a1f8 1396 struct drm_i915_private *dev_priv = dev->dev_private;
616fdb5a
BW		 1397 u32 rgvmodectl, rstdbyctl;
1398 u16 crstandvid;
1399 int ret;
1400
1401 ret = mutex_lock_interruptible(&dev->struct_mutex);
1402 if (ret)
1403 return ret;
c8c8fb33 1404 intel_runtime_pm_get(dev_priv);
616fdb5a
BW		 1405
1406 rgvmodectl = I915_READ(MEMMODECTL);
1407 rstdbyctl = I915_READ(RSTDBYCTL);
1408 crstandvid = I915_READ16(CRSTANDVID);
1409
c8c8fb33 1410 intel_runtime_pm_put(dev_priv);
616fdb5a 1411 mutex_unlock(&dev->struct_mutex);
f97108d1 1412
742f491d 1413 seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN));
f97108d1
JB		 1414 seq_printf(m, "Boost freq: %d\n",
1415 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1416 MEMMODE_BOOST_FREQ_SHIFT);
1417 seq_printf(m, "HW control enabled: %s\n",
742f491d 1418 yesno(rgvmodectl & MEMMODE_HWIDLE_EN));
f97108d1 1419 seq_printf(m, "SW control enabled: %s\n",
742f491d 1420 yesno(rgvmodectl & MEMMODE_SWMODE_EN));
f97108d1 1421 seq_printf(m, "Gated voltage change: %s\n",
742f491d 1422 yesno(rgvmodectl & MEMMODE_RCLK_GATE));
f97108d1
JB		 1423 seq_printf(m, "Starting frequency: P%d\n",
1424 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
7648fa99 1425 seq_printf(m, "Max P-state: P%d\n",
f97108d1 1426 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
7648fa99
JB		 1427 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1428 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1429 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1430 seq_printf(m, "Render standby enabled: %s\n",
742f491d 1431 yesno(!(rstdbyctl & RCX_SW_EXIT)));
267f0c90 1432 seq_puts(m, "Current RS state: ");
88271da3
JB		 1433 switch (rstdbyctl & RSX_STATUS_MASK) {
1434 case RSX_STATUS_ON:
267f0c90 1435 seq_puts(m, "on\n");
88271da3
JB		 1436 break;
1437 case RSX_STATUS_RC1:
267f0c90 1438 seq_puts(m, "RC1\n");
88271da3
JB		 1439 break;
1440 case RSX_STATUS_RC1E:
267f0c90 1441 seq_puts(m, "RC1E\n");
88271da3
JB		 1442 break;
1443 case RSX_STATUS_RS1:
267f0c90 1444 seq_puts(m, "RS1\n");
88271da3
JB		 1445 break;
1446 case RSX_STATUS_RS2:
267f0c90 1447 seq_puts(m, "RS2 (RC6)\n");
88271da3
JB		 1448 break;
1449 case RSX_STATUS_RS3:
267f0c90 1450 seq_puts(m, "RC3 (RC6+)\n");
88271da3
JB		 1451 break;
1452 default:
267f0c90 1453 seq_puts(m, "unknown\n");
88271da3
JB		 1454 break;
1455 }
f97108d1
JB		 1456
1457 return 0;
1458}
1459
f65367b5 1460static int i915_forcewake_domains(struct seq_file *m, void *data)
669ab5aa 1461{
b2cff0db
CW		 1462 struct drm_info_node *node = m->private;
1463 struct drm_device *dev = node->minor->dev;
1464 struct drm_i915_private *dev_priv = dev->dev_private;
1465 struct intel_uncore_forcewake_domain *fw_domain;
b2cff0db
CW		 1466 int i;
1467
1468 spin_lock_irq(&dev_priv->uncore.lock);
1469 for_each_fw_domain(fw_domain, dev_priv, i) {
1470 seq_printf(m, "%s.wake_count = %u\n",
05a2fb15 1471 intel_uncore_forcewake_domain_to_str(i),
b2cff0db
CW		 1472 fw_domain->wake_count);
1473 }
1474 spin_unlock_irq(&dev_priv->uncore.lock);
669ab5aa 1475
b2cff0db
CW		 1476 return 0;
1477}
1478
1479static int vlv_drpc_info(struct seq_file *m)
1480{
9f25d007 1481 struct drm_info_node *node = m->private;
669ab5aa
D		 1482 struct drm_device *dev = node->minor->dev;
1483 struct drm_i915_private *dev_priv = dev->dev_private;
6b312cd3 1484 u32 rpmodectl1, rcctl1, pw_status;
669ab5aa 1485
d46c0517
ID		 1486 intel_runtime_pm_get(dev_priv);
1487
6b312cd3 1488 pw_status = I915_READ(VLV_GTLC_PW_STATUS);
669ab5aa
D		 1489 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1490 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1491
d46c0517
ID		 1492 intel_runtime_pm_put(dev_priv);
1493
669ab5aa
D		 1494 seq_printf(m, "Video Turbo Mode: %s\n",
1495 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1496 seq_printf(m, "Turbo enabled: %s\n",
1497 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1498 seq_printf(m, "HW control enabled: %s\n",
1499 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1500 seq_printf(m, "SW control enabled: %s\n",
1501 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1502 GEN6_RP_MEDIA_SW_MODE));
1503 seq_printf(m, "RC6 Enabled: %s\n",
1504 yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1505 GEN6_RC_CTL_EI_MODE(1))));
1506 seq_printf(m, "Render Power Well: %s\n",
6b312cd3 1507 (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
669ab5aa 1508 seq_printf(m, "Media Power Well: %s\n",
6b312cd3 1509 (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
669ab5aa 1510
9cc19be5
ID		 1511 seq_printf(m, "Render RC6 residency since boot: %u\n",
1512 I915_READ(VLV_GT_RENDER_RC6));
1513 seq_printf(m, "Media RC6 residency since boot: %u\n",
1514 I915_READ(VLV_GT_MEDIA_RC6));
1515
f65367b5 1516 return i915_forcewake_domains(m, NULL);
669ab5aa
D		 1517}
1518
4d85529d
BW		 1519static int gen6_drpc_info(struct seq_file *m)
1520{
9f25d007 1521 struct drm_info_node *node = m->private;
4d85529d
BW		 1522 struct drm_device *dev = node->minor->dev;
1523 struct drm_i915_private *dev_priv = dev->dev_private;
ecd8faea 1524 u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
93b525dc 1525 unsigned forcewake_count;
aee56cff 1526 int count = 0, ret;
4d85529d
BW		 1527
1528 ret = mutex_lock_interruptible(&dev->struct_mutex);
1529 if (ret)
1530 return ret;
c8c8fb33 1531 intel_runtime_pm_get(dev_priv);
4d85529d 1532
907b28c5 1533 spin_lock_irq(&dev_priv->uncore.lock);
b2cff0db 1534 forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count;
907b28c5 1535 spin_unlock_irq(&dev_priv->uncore.lock);
93b525dc
DV		 1536
1537 if (forcewake_count) {
267f0c90
DL		 1538 seq_puts(m, "RC information inaccurate because somebody "
1539 "holds a forcewake reference \n");
4d85529d
BW		 1540 } else {
1541 /* NB: we cannot use forcewake, else we read the wrong values */
1542 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1543 udelay(10);
1544 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1545 }
1546
75aa3f63 1547 gt_core_status = I915_READ_FW(GEN6_GT_CORE_STATUS);
ed71f1b4 1548 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
4d85529d
BW		 1549
1550 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1551 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1552 mutex_unlock(&dev->struct_mutex);
44cbd338
BW		 1553 mutex_lock(&dev_priv->rps.hw_lock);
1554 sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1555 mutex_unlock(&dev_priv->rps.hw_lock);
4d85529d 1556
c8c8fb33
PZ		 1557 intel_runtime_pm_put(dev_priv);
1558
4d85529d
BW		 1559 seq_printf(m, "Video Turbo Mode: %s\n",
1560 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1561 seq_printf(m, "HW control enabled: %s\n",
1562 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1563 seq_printf(m, "SW control enabled: %s\n",
1564 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1565 GEN6_RP_MEDIA_SW_MODE));
fff24e21 1566 seq_printf(m, "RC1e Enabled: %s\n",
4d85529d
BW		 1567 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1568 seq_printf(m, "RC6 Enabled: %s\n",
1569 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1570 seq_printf(m, "Deep RC6 Enabled: %s\n",
1571 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1572 seq_printf(m, "Deepest RC6 Enabled: %s\n",
1573 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
267f0c90 1574 seq_puts(m, "Current RC state: ");
4d85529d
BW		 1575 switch (gt_core_status & GEN6_RCn_MASK) {
1576 case GEN6_RC0:
1577 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
267f0c90 1578 seq_puts(m, "Core Power Down\n");
4d85529d 1579 else
267f0c90 1580 seq_puts(m, "on\n");
4d85529d
BW		 1581 break;
1582 case GEN6_RC3:
267f0c90 1583 seq_puts(m, "RC3\n");
4d85529d
BW		 1584 break;
1585 case GEN6_RC6:
267f0c90 1586 seq_puts(m, "RC6\n");
4d85529d
BW		 1587 break;
1588 case GEN6_RC7:
267f0c90 1589 seq_puts(m, "RC7\n");
4d85529d
BW		 1590 break;
1591 default:
267f0c90 1592 seq_puts(m, "Unknown\n");
4d85529d
BW		 1593 break;
1594 }
1595
1596 seq_printf(m, "Core Power Down: %s\n",
1597 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
cce66a28
BW		 1598
1599 /* Not exactly sure what this is */
1600 seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1601 I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1602 seq_printf(m, "RC6 residency since boot: %u\n",
1603 I915_READ(GEN6_GT_GFX_RC6));
1604 seq_printf(m, "RC6+ residency since boot: %u\n",
1605 I915_READ(GEN6_GT_GFX_RC6p));
1606 seq_printf(m, "RC6++ residency since boot: %u\n",
1607 I915_READ(GEN6_GT_GFX_RC6pp));
1608
ecd8faea
BW		 1609 seq_printf(m, "RC6 voltage: %dmV\n",
1610 GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1611 seq_printf(m, "RC6+ voltage: %dmV\n",
1612 GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1613 seq_printf(m, "RC6++ voltage: %dmV\n",
1614 GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
4d85529d
BW		 1615 return 0;
1616}
1617
1618static int i915_drpc_info(struct seq_file *m, void *unused)
1619{
9f25d007 1620 struct drm_info_node *node = m->private;
4d85529d
BW		 1621 struct drm_device *dev = node->minor->dev;
1622
666a4537 1623 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
669ab5aa 1624 return vlv_drpc_info(m);
ac66cf4b 1625 else if (INTEL_INFO(dev)->gen >= 6)
4d85529d
BW		 1626 return gen6_drpc_info(m);
1627 else
1628 return ironlake_drpc_info(m);
1629}
1630
9a851789
DV		 1631static int i915_frontbuffer_tracking(struct seq_file *m, void *unused)
1632{
1633 struct drm_info_node *node = m->private;
1634 struct drm_device *dev = node->minor->dev;
1635 struct drm_i915_private *dev_priv = dev->dev_private;
1636
1637 seq_printf(m, "FB tracking busy bits: 0x%08x\n",
1638 dev_priv->fb_tracking.busy_bits);
1639
1640 seq_printf(m, "FB tracking flip bits: 0x%08x\n",
1641 dev_priv->fb_tracking.flip_bits);
1642
1643 return 0;
1644}
1645
b5e50c3f
JB		 1646static int i915_fbc_status(struct seq_file *m, void *unused)
1647{
9f25d007 1648 struct drm_info_node *node = m->private;
b5e50c3f 1649 struct drm_device *dev = node->minor->dev;
e277a1f8 1650 struct drm_i915_private *dev_priv = dev->dev_private;
b5e50c3f 1651
3a77c4c4 1652 if (!HAS_FBC(dev)) {
267f0c90 1653 seq_puts(m, "FBC unsupported on this chipset\n");
b5e50c3f
JB		 1654 return 0;
1655 }
1656
36623ef8 1657 intel_runtime_pm_get(dev_priv);
25ad93fd 1658 mutex_lock(&dev_priv->fbc.lock);
36623ef8 1659
0e631adc 1660 if (intel_fbc_is_active(dev_priv))
267f0c90 1661 seq_puts(m, "FBC enabled\n");
2e8144a5
PZ		 1662 else
1663 seq_printf(m, "FBC disabled: %s\n",
bf6189c6 1664 dev_priv->fbc.no_fbc_reason);
36623ef8 1665
31b9df10
PZ		 1666 if (INTEL_INFO(dev_priv)->gen >= 7)
1667 seq_printf(m, "Compressing: %s\n",
1668 yesno(I915_READ(FBC_STATUS2) &
1669 FBC_COMPRESSION_MASK));
1670
25ad93fd 1671 mutex_unlock(&dev_priv->fbc.lock);
36623ef8
PZ		 1672 intel_runtime_pm_put(dev_priv);
1673
b5e50c3f
JB		 1674 return 0;
1675}
1676
da46f936
RV		 1677static int i915_fbc_fc_get(void *data, u64 *val)
1678{
1679 struct drm_device *dev = data;
1680 struct drm_i915_private *dev_priv = dev->dev_private;
1681
1682 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1683 return -ENODEV;
1684
da46f936 1685 *val = dev_priv->fbc.false_color;
da46f936
RV		 1686
1687 return 0;
1688}
1689
1690static int i915_fbc_fc_set(void *data, u64 val)
1691{
1692 struct drm_device *dev = data;
1693 struct drm_i915_private *dev_priv = dev->dev_private;
1694 u32 reg;
1695
1696 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1697 return -ENODEV;
1698
25ad93fd 1699 mutex_lock(&dev_priv->fbc.lock);
da46f936
RV		 1700
1701 reg = I915_READ(ILK_DPFC_CONTROL);
1702 dev_priv->fbc.false_color = val;
1703
1704 I915_WRITE(ILK_DPFC_CONTROL, val ?
1705 (reg | FBC_CTL_FALSE_COLOR) :
1706 (reg & ~FBC_CTL_FALSE_COLOR));
1707
25ad93fd 1708 mutex_unlock(&dev_priv->fbc.lock);
da46f936
RV		 1709 return 0;
1710}
1711
1712DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops,
1713 i915_fbc_fc_get, i915_fbc_fc_set,
1714 "%llu\n");
1715
92d44621
PZ		 1716static int i915_ips_status(struct seq_file *m, void *unused)
1717{
9f25d007 1718 struct drm_info_node *node = m->private;
92d44621
PZ		 1719 struct drm_device *dev = node->minor->dev;
1720 struct drm_i915_private *dev_priv = dev->dev_private;
1721
f5adf94e 1722 if (!HAS_IPS(dev)) {
92d44621
PZ		 1723 seq_puts(m, "not supported\n");
1724 return 0;
1725 }
1726
36623ef8
PZ		 1727 intel_runtime_pm_get(dev_priv);
1728
0eaa53f0
RV		 1729 seq_printf(m, "Enabled by kernel parameter: %s\n",
1730 yesno(i915.enable_ips));
1731
1732 if (INTEL_INFO(dev)->gen >= 8) {
1733 seq_puts(m, "Currently: unknown\n");
1734 } else {
1735 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1736 seq_puts(m, "Currently: enabled\n");
1737 else
1738 seq_puts(m, "Currently: disabled\n");
1739 }
92d44621 1740
36623ef8
PZ		 1741 intel_runtime_pm_put(dev_priv);
1742
92d44621
PZ		 1743 return 0;
1744}
1745
4a9bef37
JB		 1746static int i915_sr_status(struct seq_file *m, void *unused)
1747{
9f25d007 1748 struct drm_info_node *node = m->private;
4a9bef37 1749 struct drm_device *dev = node->minor->dev;
e277a1f8 1750 struct drm_i915_private *dev_priv = dev->dev_private;
4a9bef37
JB		 1751 bool sr_enabled = false;
1752
36623ef8
PZ		 1753 intel_runtime_pm_get(dev_priv);
1754
1398261a 1755 if (HAS_PCH_SPLIT(dev))
5ba2aaaa 1756 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
77b64555
ACO		 1757 else if (IS_CRESTLINE(dev) || IS_G4X(dev) ||
1758 IS_I945G(dev) || IS_I945GM(dev))
4a9bef37
JB		 1759 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1760 else if (IS_I915GM(dev))
1761 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1762 else if (IS_PINEVIEW(dev))
1763 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
666a4537 1764 else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
77b64555 1765 sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
4a9bef37 1766
36623ef8
PZ		 1767 intel_runtime_pm_put(dev_priv);
1768
5ba2aaaa
CW		 1769 seq_printf(m, "self-refresh: %s\n",
1770 sr_enabled ? "enabled" : "disabled");
4a9bef37
JB		 1771
1772 return 0;
1773}
1774
7648fa99
JB		 1775static int i915_emon_status(struct seq_file *m, void *unused)
1776{
9f25d007 1777 struct drm_info_node *node = m->private;
7648fa99 1778 struct drm_device *dev = node->minor->dev;
e277a1f8 1779 struct drm_i915_private *dev_priv = dev->dev_private;
7648fa99 1780 unsigned long temp, chipset, gfx;
de227ef0
CW		 1781 int ret;
1782
582be6b4
CW		 1783 if (!IS_GEN5(dev))
1784 return -ENODEV;
1785
de227ef0
CW		 1786 ret = mutex_lock_interruptible(&dev->struct_mutex);
1787 if (ret)
1788 return ret;
7648fa99
JB		 1789
1790 temp = i915_mch_val(dev_priv);
1791 chipset = i915_chipset_val(dev_priv);
1792 gfx = i915_gfx_val(dev_priv);
de227ef0 1793 mutex_unlock(&dev->struct_mutex);
7648fa99
JB		 1794
1795 seq_printf(m, "GMCH temp: %ld\n", temp);
1796 seq_printf(m, "Chipset power: %ld\n", chipset);
1797 seq_printf(m, "GFX power: %ld\n", gfx);
1798 seq_printf(m, "Total power: %ld\n", chipset + gfx);
1799
1800 return 0;
1801}
1802
23b2f8bb
JB		 1803static int i915_ring_freq_table(struct seq_file *m, void *unused)
1804{
9f25d007 1805 struct drm_info_node *node = m->private;
23b2f8bb 1806 struct drm_device *dev = node->minor->dev;
e277a1f8 1807 struct drm_i915_private *dev_priv = dev->dev_private;
5bfa0199 1808 int ret = 0;
23b2f8bb 1809 int gpu_freq, ia_freq;
f936ec34 1810 unsigned int max_gpu_freq, min_gpu_freq;
23b2f8bb 1811
97d3308a 1812 if (!HAS_CORE_RING_FREQ(dev)) {
267f0c90 1813 seq_puts(m, "unsupported on this chipset\n");
23b2f8bb
JB		 1814 return 0;
1815 }
1816
5bfa0199
PZ		 1817 intel_runtime_pm_get(dev_priv);
1818
5c9669ce
TR		 1819 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1820
4fc688ce 1821 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
23b2f8bb 1822 if (ret)
5bfa0199 1823 goto out;
23b2f8bb 1824
ef11bdb3 1825 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
f936ec34
AG		 1826 /* Convert GT frequency to 50 HZ units */
1827 min_gpu_freq =
1828 dev_priv->rps.min_freq_softlimit / GEN9_FREQ_SCALER;
1829 max_gpu_freq =
1830 dev_priv->rps.max_freq_softlimit / GEN9_FREQ_SCALER;
1831 } else {
1832 min_gpu_freq = dev_priv->rps.min_freq_softlimit;
1833 max_gpu_freq = dev_priv->rps.max_freq_softlimit;
1834 }
1835
267f0c90 1836 seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
23b2f8bb 1837
f936ec34 1838 for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
42c0526c
BW		 1839 ia_freq = gpu_freq;
1840 sandybridge_pcode_read(dev_priv,
1841 GEN6_PCODE_READ_MIN_FREQ_TABLE,
1842 &ia_freq);
3ebecd07 1843 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
f936ec34 1844 intel_gpu_freq(dev_priv, (gpu_freq *
ef11bdb3
RV		 1845 (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1846 GEN9_FREQ_SCALER : 1))),
3ebecd07
CW		 1847 ((ia_freq >> 0) & 0xff) * 100,
1848 ((ia_freq >> 8) & 0xff) * 100);
23b2f8bb
JB		 1849 }
1850
4fc688ce 1851 mutex_unlock(&dev_priv->rps.hw_lock);
23b2f8bb 1852
5bfa0199
PZ		 1853out:
1854 intel_runtime_pm_put(dev_priv);
1855 return ret;
23b2f8bb
JB		 1856}
1857
44834a67
CW		 1858static int i915_opregion(struct seq_file *m, void *unused)
1859{
9f25d007 1860 struct drm_info_node *node = m->private;
44834a67 1861 struct drm_device *dev = node->minor->dev;
e277a1f8 1862 struct drm_i915_private *dev_priv = dev->dev_private;
44834a67
CW		 1863 struct intel_opregion *opregion = &dev_priv->opregion;
1864 int ret;
1865
1866 ret = mutex_lock_interruptible(&dev->struct_mutex);
1867 if (ret)
0d38f009 1868 goto out;
44834a67 1869
2455a8e4
JN		 1870 if (opregion->header)
1871 seq_write(m, opregion->header, OPREGION_SIZE);
44834a67
CW		 1872
1873 mutex_unlock(&dev->struct_mutex);
1874
0d38f009 1875out:
44834a67
CW		 1876 return 0;
1877}
1878
ada8f955
JN		 1879static int i915_vbt(struct seq_file *m, void *unused)
1880{
1881 struct drm_info_node *node = m->private;
1882 struct drm_device *dev = node->minor->dev;
1883 struct drm_i915_private *dev_priv = dev->dev_private;
1884 struct intel_opregion *opregion = &dev_priv->opregion;
1885
1886 if (opregion->vbt)
1887 seq_write(m, opregion->vbt, opregion->vbt_size);
1888
1889 return 0;
1890}
1891
37811fcc
CW		 1892static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1893{
9f25d007 1894 struct drm_info_node *node = m->private;
37811fcc 1895 struct drm_device *dev = node->minor->dev;
b13b8402 1896 struct intel_framebuffer *fbdev_fb = NULL;
3a58ee10 1897 struct drm_framebuffer *drm_fb;
37811fcc 1898
0695726e 1899#ifdef CONFIG_DRM_FBDEV_EMULATION
b13b8402
NS		 1900 if (to_i915(dev)->fbdev) {
1901 fbdev_fb = to_intel_framebuffer(to_i915(dev)->fbdev->helper.fb);
1902
1903 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1904 fbdev_fb->base.width,
1905 fbdev_fb->base.height,
1906 fbdev_fb->base.depth,
1907 fbdev_fb->base.bits_per_pixel,
1908 fbdev_fb->base.modifier[0],
1909 atomic_read(&fbdev_fb->base.refcount.refcount));
1910 describe_obj(m, fbdev_fb->obj);
1911 seq_putc(m, '\n');
1912 }
4520f53a 1913#endif
37811fcc 1914
4b096ac1 1915 mutex_lock(&dev->mode_config.fb_lock);
3a58ee10 1916 drm_for_each_fb(drm_fb, dev) {
b13b8402
NS		 1917 struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb);
1918 if (fb == fbdev_fb)
37811fcc
CW		 1919 continue;
1920
c1ca506d 1921 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
37811fcc
CW		 1922 fb->base.width,
1923 fb->base.height,
1924 fb->base.depth,
623f9783 1925 fb->base.bits_per_pixel,
c1ca506d 1926 fb->base.modifier[0],
623f9783 1927 atomic_read(&fb->base.refcount.refcount));
05394f39 1928 describe_obj(m, fb->obj);
267f0c90 1929 seq_putc(m, '\n');
37811fcc 1930 }
4b096ac1 1931 mutex_unlock(&dev->mode_config.fb_lock);
37811fcc
CW		 1932
1933 return 0;
1934}
1935
c9fe99bd
OM		 1936static void describe_ctx_ringbuf(struct seq_file *m,
1937 struct intel_ringbuffer *ringbuf)
1938{
1939 seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
1940 ringbuf->space, ringbuf->head, ringbuf->tail,
1941 ringbuf->last_retired_head);
1942}
1943
e76d3630
BW		 1944static int i915_context_status(struct seq_file *m, void *unused)
1945{
9f25d007 1946 struct drm_info_node *node = m->private;
e76d3630 1947 struct drm_device *dev = node->minor->dev;
e277a1f8 1948 struct drm_i915_private *dev_priv = dev->dev_private;
e2f80391 1949 struct intel_engine_cs *engine;
273497e5 1950 struct intel_context *ctx;
c3232b18
DG		 1951 enum intel_engine_id id;
1952 int ret;
e76d3630 1953
f3d28878 1954 ret = mutex_lock_interruptible(&dev->struct_mutex);
e76d3630
BW		 1955 if (ret)
1956 return ret;
1957
a33afea5 1958 list_for_each_entry(ctx, &dev_priv->context_list, link) {
c9fe99bd
OM		 1959 if (!i915.enable_execlists &&
1960 ctx->legacy_hw_ctx.rcs_state == NULL)
b77f6997
CW		 1961 continue;
1962
a33afea5 1963 seq_puts(m, "HW context ");
3ccfd19d 1964 describe_ctx(m, ctx);
e28e404c
DG		 1965 if (ctx == dev_priv->kernel_context)
1966 seq_printf(m, "(kernel context) ");
c9fe99bd
OM		 1967
1968 if (i915.enable_execlists) {
1969 seq_putc(m, '\n');
c3232b18 1970 for_each_engine_id(engine, dev_priv, id) {
c9fe99bd 1971 struct drm_i915_gem_object *ctx_obj =
c3232b18 1972 ctx->engine[id].state;
c9fe99bd 1973 struct intel_ringbuffer *ringbuf =
c3232b18 1974 ctx->engine[id].ringbuf;
c9fe99bd 1975
e2f80391 1976 seq_printf(m, "%s: ", engine->name);
c9fe99bd
OM		 1977 if (ctx_obj)
1978 describe_obj(m, ctx_obj);
1979 if (ringbuf)
1980 describe_ctx_ringbuf(m, ringbuf);
1981 seq_putc(m, '\n');
1982 }
1983 } else {
1984 describe_obj(m, ctx->legacy_hw_ctx.rcs_state);
1985 }
a33afea5 1986
a33afea5 1987 seq_putc(m, '\n');
a168c293
BW		 1988 }
1989
f3d28878 1990 mutex_unlock(&dev->struct_mutex);
e76d3630
BW		 1991
1992 return 0;
1993}
1994
064ca1d2 1995static void i915_dump_lrc_obj(struct seq_file *m,
ca82580c 1996 struct intel_context *ctx,
0bc40be8 1997 struct intel_engine_cs *engine)
064ca1d2
TD		 1998{
1999 struct page *page;
2000 uint32_t *reg_state;
2001 int j;
0bc40be8 2002 struct drm_i915_gem_object *ctx_obj = ctx->engine[engine->id].state;
064ca1d2
TD		 2003 unsigned long ggtt_offset = 0;
2004
2005 if (ctx_obj == NULL) {
2006 seq_printf(m, "Context on %s with no gem object\n",
0bc40be8 2007 engine->name);
064ca1d2
TD		 2008 return;
2009 }
2010
0bc40be8
TU		 2011 seq_printf(m, "CONTEXT: %s %u\n", engine->name,
2012 intel_execlists_ctx_id(ctx, engine));
064ca1d2
TD		 2013
2014 if (!i915_gem_obj_ggtt_bound(ctx_obj))
2015 seq_puts(m, "\tNot bound in GGTT\n");
2016 else
2017 ggtt_offset = i915_gem_obj_ggtt_offset(ctx_obj);
2018
2019 if (i915_gem_object_get_pages(ctx_obj)) {
2020 seq_puts(m, "\tFailed to get pages for context object\n");
2021 return;
2022 }
2023
d1675198 2024 page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN);
064ca1d2
TD		 2025 if (!WARN_ON(page == NULL)) {
2026 reg_state = kmap_atomic(page);
2027
2028 for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
2029 seq_printf(m, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n",
2030 ggtt_offset + 4096 + (j * 4),
2031 reg_state[j], reg_state[j + 1],
2032 reg_state[j + 2], reg_state[j + 3]);
2033 }
2034 kunmap_atomic(reg_state);
2035 }
2036
2037 seq_putc(m, '\n');
2038}
2039
c0ab1ae9
BW		 2040static int i915_dump_lrc(struct seq_file *m, void *unused)
2041{
2042 struct drm_info_node *node = (struct drm_info_node *) m->private;
2043 struct drm_device *dev = node->minor->dev;
2044 struct drm_i915_private *dev_priv = dev->dev_private;
e2f80391 2045 struct intel_engine_cs *engine;
c0ab1ae9
BW		 2046 struct intel_context *ctx;
2047 int ret, i;
2048
2049 if (!i915.enable_execlists) {
2050 seq_printf(m, "Logical Ring Contexts are disabled\n");
2051 return 0;
2052 }
2053
2054 ret = mutex_lock_interruptible(&dev->struct_mutex);
2055 if (ret)
2056 return ret;
2057
e28e404c
DG		 2058 list_for_each_entry(ctx, &dev_priv->context_list, link)
2059 if (ctx != dev_priv->kernel_context)
666796da 2060 for_each_engine(engine, dev_priv, i)
e2f80391 2061 i915_dump_lrc_obj(m, ctx, engine);
c0ab1ae9
BW		 2062
2063 mutex_unlock(&dev->struct_mutex);
2064
2065 return 0;
2066}
2067
4ba70e44
OM		 2068static int i915_execlists(struct seq_file *m, void *data)
2069{
2070 struct drm_info_node *node = (struct drm_info_node *)m->private;
2071 struct drm_device *dev = node->minor->dev;
2072 struct drm_i915_private *dev_priv = dev->dev_private;
e2f80391 2073 struct intel_engine_cs *engine;
4ba70e44
OM		 2074 u32 status_pointer;
2075 u8 read_pointer;
2076 u8 write_pointer;
2077 u32 status;
2078 u32 ctx_id;
2079 struct list_head *cursor;
2080 int ring_id, i;
2081 int ret;
2082
2083 if (!i915.enable_execlists) {
2084 seq_puts(m, "Logical Ring Contexts are disabled\n");
2085 return 0;
2086 }
2087
2088 ret = mutex_lock_interruptible(&dev->struct_mutex);
2089 if (ret)
2090 return ret;
2091
fc0412ec
MT		 2092 intel_runtime_pm_get(dev_priv);
2093
666796da 2094 for_each_engine(engine, dev_priv, ring_id) {
6d3d8274 2095 struct drm_i915_gem_request *head_req = NULL;
4ba70e44
OM		 2096 int count = 0;
2097 unsigned long flags;
2098
e2f80391 2099 seq_printf(m, "%s\n", engine->name);
4ba70e44 2100
e2f80391
TU		 2101 status = I915_READ(RING_EXECLIST_STATUS_LO(engine));
2102 ctx_id = I915_READ(RING_EXECLIST_STATUS_HI(engine));
4ba70e44
OM		 2103 seq_printf(m, "\tExeclist status: 0x%08X, context: %u\n",
2104 status, ctx_id);
2105
e2f80391 2106 status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(engine));
4ba70e44
OM		 2107 seq_printf(m, "\tStatus pointer: 0x%08X\n", status_pointer);
2108
e2f80391 2109 read_pointer = engine->next_context_status_buffer;
5590a5f0 2110 write_pointer = GEN8_CSB_WRITE_PTR(status_pointer);
4ba70e44 2111 if (read_pointer > write_pointer)
5590a5f0 2112 write_pointer += GEN8_CSB_ENTRIES;
4ba70e44
OM		 2113 seq_printf(m, "\tRead pointer: 0x%08X, write pointer 0x%08X\n",
2114 read_pointer, write_pointer);
2115
5590a5f0 2116 for (i = 0; i < GEN8_CSB_ENTRIES; i++) {
e2f80391
TU		 2117 status = I915_READ(RING_CONTEXT_STATUS_BUF_LO(engine, i));
2118 ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF_HI(engine, i));
4ba70e44
OM		 2119
2120 seq_printf(m, "\tStatus buffer %d: 0x%08X, context: %u\n",
2121 i, status, ctx_id);
2122 }
2123
e2f80391
TU		 2124 spin_lock_irqsave(&engine->execlist_lock, flags);
2125 list_for_each(cursor, &engine->execlist_queue)
4ba70e44 2126 count++;
e2f80391
TU		 2127 head_req = list_first_entry_or_null(&engine->execlist_queue,
2128 struct drm_i915_gem_request,
2129 execlist_link);
2130 spin_unlock_irqrestore(&engine->execlist_lock, flags);
4ba70e44
OM		 2131
2132 seq_printf(m, "\t%d requests in queue\n", count);
2133 if (head_req) {
4ba70e44 2134 seq_printf(m, "\tHead request id: %u\n",
e2f80391 2135 intel_execlists_ctx_id(head_req->ctx, engine));
4ba70e44 2136 seq_printf(m, "\tHead request tail: %u\n",
6d3d8274 2137 head_req->tail);
4ba70e44
OM		 2138 }
2139
2140 seq_putc(m, '\n');
2141 }
2142
fc0412ec 2143 intel_runtime_pm_put(dev_priv);
4ba70e44
OM		 2144 mutex_unlock(&dev->struct_mutex);
2145
2146 return 0;
2147}
2148
ea16a3cd
DV		 2149static const char *swizzle_string(unsigned swizzle)
2150{
aee56cff 2151 switch (swizzle) {
ea16a3cd
DV		 2152 case I915_BIT_6_SWIZZLE_NONE:
2153 return "none";
2154 case I915_BIT_6_SWIZZLE_9:
2155 return "bit9";
2156 case I915_BIT_6_SWIZZLE_9_10:
2157 return "bit9/bit10";
2158 case I915_BIT_6_SWIZZLE_9_11:
2159 return "bit9/bit11";
2160 case I915_BIT_6_SWIZZLE_9_10_11:
2161 return "bit9/bit10/bit11";
2162 case I915_BIT_6_SWIZZLE_9_17:
2163 return "bit9/bit17";
2164 case I915_BIT_6_SWIZZLE_9_10_17:
2165 return "bit9/bit10/bit17";
2166 case I915_BIT_6_SWIZZLE_UNKNOWN:
8a168ca7 2167 return "unknown";
ea16a3cd
DV		 2168 }
2169
2170 return "bug";
2171}
2172
2173static int i915_swizzle_info(struct seq_file *m, void *data)
2174{
9f25d007 2175 struct drm_info_node *node = m->private;
ea16a3cd
DV		 2176 struct drm_device *dev = node->minor->dev;
2177 struct drm_i915_private *dev_priv = dev->dev_private;
22bcfc6a
DV		 2178 int ret;
2179
2180 ret = mutex_lock_interruptible(&dev->struct_mutex);
2181 if (ret)
2182 return ret;
c8c8fb33 2183 intel_runtime_pm_get(dev_priv);
ea16a3cd 2184
ea16a3cd
DV		 2185 seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
2186 swizzle_string(dev_priv->mm.bit_6_swizzle_x));
2187 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
2188 swizzle_string(dev_priv->mm.bit_6_swizzle_y));
2189
2190 if (IS_GEN3(dev) || IS_GEN4(dev)) {
2191 seq_printf(m, "DDC = 0x%08x\n",
2192 I915_READ(DCC));
656bfa3a
DV		 2193 seq_printf(m, "DDC2 = 0x%08x\n",
2194 I915_READ(DCC2));
ea16a3cd
DV		 2195 seq_printf(m, "C0DRB3 = 0x%04x\n",
2196 I915_READ16(C0DRB3));
2197 seq_printf(m, "C1DRB3 = 0x%04x\n",
2198 I915_READ16(C1DRB3));
9d3203e1 2199 } else if (INTEL_INFO(dev)->gen >= 6) {
3fa7d235
DV		 2200 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
2201 I915_READ(MAD_DIMM_C0));
2202 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
2203 I915_READ(MAD_DIMM_C1));
2204 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
2205 I915_READ(MAD_DIMM_C2));
2206 seq_printf(m, "TILECTL = 0x%08x\n",
2207 I915_READ(TILECTL));
5907f5fb 2208 if (INTEL_INFO(dev)->gen >= 8)
9d3203e1
BW		 2209 seq_printf(m, "GAMTARBMODE = 0x%08x\n",
2210 I915_READ(GAMTARBMODE));
2211 else
2212 seq_printf(m, "ARB_MODE = 0x%08x\n",
2213 I915_READ(ARB_MODE));
3fa7d235
DV		 2214 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
2215 I915_READ(DISP_ARB_CTL));
ea16a3cd 2216 }
656bfa3a
DV		 2217
2218 if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2219 seq_puts(m, "L-shaped memory detected\n");
2220
c8c8fb33 2221 intel_runtime_pm_put(dev_priv);
ea16a3cd
DV		 2222 mutex_unlock(&dev->struct_mutex);
2223
2224 return 0;
2225}
2226
1c60fef5
BW		 2227static int per_file_ctx(int id, void *ptr, void *data)
2228{
273497e5 2229 struct intel_context *ctx = ptr;
1c60fef5 2230 struct seq_file *m = data;
ae6c4806
DV		 2231 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2232
2233 if (!ppgtt) {
2234 seq_printf(m, " no ppgtt for context %d\n",
2235 ctx->user_handle);
2236 return 0;
2237 }
1c60fef5 2238
f83d6518
OM		 2239 if (i915_gem_context_is_default(ctx))
2240 seq_puts(m, " default context:\n");
2241 else
821d66dd 2242 seq_printf(m, " context %d:\n", ctx->user_handle);
1c60fef5
BW		 2243 ppgtt->debug_dump(ppgtt, m);
2244
2245 return 0;
2246}
2247
77df6772 2248static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev)
3cf17fc5 2249{
3cf17fc5 2250 struct drm_i915_private *dev_priv = dev->dev_private;
e2f80391 2251 struct intel_engine_cs *engine;
77df6772
BW		 2252 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2253 int unused, i;
3cf17fc5 2254
77df6772
BW		 2255 if (!ppgtt)
2256 return;
2257
666796da 2258 for_each_engine(engine, dev_priv, unused) {
e2f80391 2259 seq_printf(m, "%s\n", engine->name);
77df6772 2260 for (i = 0; i < 4; i++) {
e2f80391 2261 u64 pdp = I915_READ(GEN8_RING_PDP_UDW(engine, i));
77df6772 2262 pdp <<= 32;
e2f80391 2263 pdp |= I915_READ(GEN8_RING_PDP_LDW(engine, i));
a2a5b15c 2264 seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
77df6772
BW		 2265 }
2266 }
2267}
2268
2269static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2270{
2271 struct drm_i915_private *dev_priv = dev->dev_private;
e2f80391 2272 struct intel_engine_cs *engine;
77df6772 2273 int i;
3cf17fc5 2274
3cf17fc5
DV		 2275 if (INTEL_INFO(dev)->gen == 6)
2276 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
2277
666796da 2278 for_each_engine(engine, dev_priv, i) {
e2f80391 2279 seq_printf(m, "%s\n", engine->name);
3cf17fc5 2280 if (INTEL_INFO(dev)->gen == 7)
e2f80391
TU		 2281 seq_printf(m, "GFX_MODE: 0x%08x\n",
2282 I915_READ(RING_MODE_GEN7(engine)));
2283 seq_printf(m, "PP_DIR_BASE: 0x%08x\n",
2284 I915_READ(RING_PP_DIR_BASE(engine)));
2285 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n",
2286 I915_READ(RING_PP_DIR_BASE_READ(engine)));
2287 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n",
2288 I915_READ(RING_PP_DIR_DCLV(engine)));
3cf17fc5
DV		 2289 }
2290 if (dev_priv->mm.aliasing_ppgtt) {
2291 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2292
267f0c90 2293 seq_puts(m, "aliasing PPGTT:\n");
44159ddb 2294 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.base.ggtt_offset);
1c60fef5 2295
87d60b63 2296 ppgtt->debug_dump(ppgtt, m);
ae6c4806 2297 }
1c60fef5 2298
3cf17fc5 2299 seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
77df6772
BW		 2300}
2301
2302static int i915_ppgtt_info(struct seq_file *m, void *data)
2303{
9f25d007 2304 struct drm_info_node *node = m->private;
77df6772 2305 struct drm_device *dev = node->minor->dev;
c8c8fb33 2306 struct drm_i915_private *dev_priv = dev->dev_private;
ea91e401 2307 struct drm_file *file;
77df6772
BW		 2308
2309 int ret = mutex_lock_interruptible(&dev->struct_mutex);
2310 if (ret)
2311 return ret;
c8c8fb33 2312 intel_runtime_pm_get(dev_priv);
77df6772
BW		 2313
2314 if (INTEL_INFO(dev)->gen >= 8)
2315 gen8_ppgtt_info(m, dev);
2316 else if (INTEL_INFO(dev)->gen >= 6)
2317 gen6_ppgtt_info(m, dev);
2318
ea91e401
MT		 2319 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2320 struct drm_i915_file_private *file_priv = file->driver_priv;
7cb5dff8 2321 struct task_struct *task;
ea91e401 2322
7cb5dff8 2323 task = get_pid_task(file->pid, PIDTYPE_PID);
06812760
DC		 2324 if (!task) {
2325 ret = -ESRCH;
2326 goto out_put;
2327 }
7cb5dff8
GT		 2328 seq_printf(m, "\nproc: %s\n", task->comm);
2329 put_task_struct(task);
ea91e401
MT		 2330 idr_for_each(&file_priv->context_idr, per_file_ctx,
2331 (void *)(unsigned long)m);
2332 }
2333
06812760 2334out_put:
c8c8fb33 2335 intel_runtime_pm_put(dev_priv);
3cf17fc5
DV		 2336 mutex_unlock(&dev->struct_mutex);
2337
06812760 2338 return ret;
3cf17fc5
DV		 2339}
2340
f5a4c67d
CW		 2341static int count_irq_waiters(struct drm_i915_private *i915)
2342{
e2f80391 2343 struct intel_engine_cs *engine;
f5a4c67d
CW		 2344 int count = 0;
2345 int i;
2346
666796da 2347 for_each_engine(engine, i915, i)
e2f80391 2348 count += engine->irq_refcount;
f5a4c67d
CW		 2349
2350 return count;
2351}
2352
1854d5ca
CW		 2353static int i915_rps_boost_info(struct seq_file *m, void *data)
2354{
2355 struct drm_info_node *node = m->private;
2356 struct drm_device *dev = node->minor->dev;
2357 struct drm_i915_private *dev_priv = dev->dev_private;
2358 struct drm_file *file;
1854d5ca 2359
f5a4c67d
CW		 2360 seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled);
2361 seq_printf(m, "GPU busy? %d\n", dev_priv->mm.busy);
2362 seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv));
2363 seq_printf(m, "Frequency requested %d; min hard:%d, soft:%d; max soft:%d, hard:%d\n",
2364 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
2365 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2366 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit),
2367 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit),
2368 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
8d3afd7d 2369 spin_lock(&dev_priv->rps.client_lock);
1854d5ca
CW		 2370 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2371 struct drm_i915_file_private *file_priv = file->driver_priv;
2372 struct task_struct *task;
2373
2374 rcu_read_lock();
2375 task = pid_task(file->pid, PIDTYPE_PID);
2376 seq_printf(m, "%s [%d]: %d boosts%s\n",
2377 task ? task->comm : "<unknown>",
2378 task ? task->pid : -1,
2e1b8730
CW		 2379 file_priv->rps.boosts,
2380 list_empty(&file_priv->rps.link) ? "" : ", active");
1854d5ca
CW		 2381 rcu_read_unlock();
2382 }
2e1b8730
CW		 2383 seq_printf(m, "Semaphore boosts: %d%s\n",
2384 dev_priv->rps.semaphores.boosts,
2385 list_empty(&dev_priv->rps.semaphores.link) ? "" : ", active");
2386 seq_printf(m, "MMIO flip boosts: %d%s\n",
2387 dev_priv->rps.mmioflips.boosts,
2388 list_empty(&dev_priv->rps.mmioflips.link) ? "" : ", active");
1854d5ca 2389 seq_printf(m, "Kernel boosts: %d\n", dev_priv->rps.boosts);
8d3afd7d 2390 spin_unlock(&dev_priv->rps.client_lock);
1854d5ca 2391
8d3afd7d 2392 return 0;
1854d5ca
CW		 2393}
2394
63573eb7
BW		 2395static int i915_llc(struct seq_file *m, void *data)
2396{
9f25d007 2397 struct drm_info_node *node = m->private;
63573eb7
BW		 2398 struct drm_device *dev = node->minor->dev;
2399 struct drm_i915_private *dev_priv = dev->dev_private;
2400
2401 /* Size calculation for LLC is a bit of a pain. Ignore for now. */
2402 seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
2403 seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size);
2404
2405 return 0;
2406}
2407
fdf5d357
AD		 2408static int i915_guc_load_status_info(struct seq_file *m, void *data)
2409{
2410 struct drm_info_node *node = m->private;
2411 struct drm_i915_private *dev_priv = node->minor->dev->dev_private;
2412 struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
2413 u32 tmp, i;
2414
2415 if (!HAS_GUC_UCODE(dev_priv->dev))
2416 return 0;
2417
2418 seq_printf(m, "GuC firmware status:\n");
2419 seq_printf(m, "\tpath: %s\n",
2420 guc_fw->guc_fw_path);
2421 seq_printf(m, "\tfetch: %s\n",
2422 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
2423 seq_printf(m, "\tload: %s\n",
2424 intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
2425 seq_printf(m, "\tversion wanted: %d.%d\n",
2426 guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
2427 seq_printf(m, "\tversion found: %d.%d\n",
2428 guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found);
feda33ef
AD		 2429 seq_printf(m, "\theader: offset is %d; size = %d\n",
2430 guc_fw->header_offset, guc_fw->header_size);
2431 seq_printf(m, "\tuCode: offset is %d; size = %d\n",
2432 guc_fw->ucode_offset, guc_fw->ucode_size);
2433 seq_printf(m, "\tRSA: offset is %d; size = %d\n",
2434 guc_fw->rsa_offset, guc_fw->rsa_size);
fdf5d357
AD		 2435
2436 tmp = I915_READ(GUC_STATUS);
2437
2438 seq_printf(m, "\nGuC status 0x%08x:\n", tmp);
2439 seq_printf(m, "\tBootrom status = 0x%x\n",
2440 (tmp & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT);
2441 seq_printf(m, "\tuKernel status = 0x%x\n",
2442 (tmp & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT);
2443 seq_printf(m, "\tMIA Core status = 0x%x\n",
2444 (tmp & GS_MIA_MASK) >> GS_MIA_SHIFT);
2445 seq_puts(m, "\nScratch registers:\n");
2446 for (i = 0; i < 16; i++)
2447 seq_printf(m, "\t%2d: \t0x%x\n", i, I915_READ(SOFT_SCRATCH(i)));
2448
2449 return 0;
2450}
2451
8b417c26
DG		 2452static void i915_guc_client_info(struct seq_file *m,
2453 struct drm_i915_private *dev_priv,
2454 struct i915_guc_client *client)
2455{
e2f80391 2456 struct intel_engine_cs *engine;
8b417c26
DG		 2457 uint64_t tot = 0;
2458 uint32_t i;
2459
2460 seq_printf(m, "\tPriority %d, GuC ctx index: %u, PD offset 0x%x\n",
2461 client->priority, client->ctx_index, client->proc_desc_offset);
2462 seq_printf(m, "\tDoorbell id %d, offset: 0x%x, cookie 0x%x\n",
2463 client->doorbell_id, client->doorbell_offset, client->cookie);
2464 seq_printf(m, "\tWQ size %d, offset: 0x%x, tail %d\n",
2465 client->wq_size, client->wq_offset, client->wq_tail);
2466
2467 seq_printf(m, "\tFailed to queue: %u\n", client->q_fail);
2468 seq_printf(m, "\tFailed doorbell: %u\n", client->b_fail);
2469 seq_printf(m, "\tLast submission result: %d\n", client->retcode);
2470
666796da 2471 for_each_engine(engine, dev_priv, i) {
8b417c26 2472 seq_printf(m, "\tSubmissions: %llu %s\n",
e2f80391
TU		 2473 client->submissions[engine->guc_id],
2474 engine->name);
2475 tot += client->submissions[engine->guc_id];
8b417c26
DG		 2476 }
2477 seq_printf(m, "\tTotal: %llu\n", tot);
2478}
2479
2480static int i915_guc_info(struct seq_file *m, void *data)
2481{
2482 struct drm_info_node *node = m->private;
2483 struct drm_device *dev = node->minor->dev;
2484 struct drm_i915_private *dev_priv = dev->dev_private;
2485 struct intel_guc guc;
0a0b457f 2486 struct i915_guc_client client = {};
e2f80391 2487 struct intel_engine_cs *engine;
117897f4 2488 enum intel_engine_id i;
8b417c26
DG		 2489 u64 total = 0;
2490
2491 if (!HAS_GUC_SCHED(dev_priv->dev))
2492 return 0;
2493
5a843307
AD		 2494 if (mutex_lock_interruptible(&dev->struct_mutex))
2495 return 0;
2496
8b417c26 2497 /* Take a local copy of the GuC data, so we can dump it at leisure */
8b417c26 2498 guc = dev_priv->guc;
5a843307 2499 if (guc.execbuf_client)
8b417c26 2500 client = *guc.execbuf_client;
5a843307
AD		 2501
2502 mutex_unlock(&dev->struct_mutex);
8b417c26
DG		 2503
2504 seq_printf(m, "GuC total action count: %llu\n", guc.action_count);
2505 seq_printf(m, "GuC action failure count: %u\n", guc.action_fail);
2506 seq_printf(m, "GuC last action command: 0x%x\n", guc.action_cmd);
2507 seq_printf(m, "GuC last action status: 0x%x\n", guc.action_status);
2508 seq_printf(m, "GuC last action error code: %d\n", guc.action_err);
2509
2510 seq_printf(m, "\nGuC submissions:\n");
666796da 2511 for_each_engine(engine, dev_priv, i) {
397097b0 2512 seq_printf(m, "\t%-24s: %10llu, last seqno 0x%08x\n",
e2f80391
TU		 2513 engine->name, guc.submissions[engine->guc_id],
2514 guc.last_seqno[engine->guc_id]);
2515 total += guc.submissions[engine->guc_id];
8b417c26
DG		 2516 }
2517 seq_printf(m, "\t%s: %llu\n", "Total", total);
2518
2519 seq_printf(m, "\nGuC execbuf client @ %p:\n", guc.execbuf_client);
2520 i915_guc_client_info(m, dev_priv, &client);
2521
2522 /* Add more as required ... */
2523
2524 return 0;
2525}
2526
4c7e77fc
AD		 2527static int i915_guc_log_dump(struct seq_file *m, void *data)
2528{
2529 struct drm_info_node *node = m->private;
2530 struct drm_device *dev = node->minor->dev;
2531 struct drm_i915_private *dev_priv = dev->dev_private;
2532 struct drm_i915_gem_object *log_obj = dev_priv->guc.log_obj;
2533 u32 *log;
2534 int i = 0, pg;
2535
2536 if (!log_obj)
2537 return 0;
2538
2539 for (pg = 0; pg < log_obj->base.size / PAGE_SIZE; pg++) {
2540 log = kmap_atomic(i915_gem_object_get_page(log_obj, pg));
2541
2542 for (i = 0; i < PAGE_SIZE / sizeof(u32); i += 4)
2543 seq_printf(m, "0x%08x 0x%08x 0x%08x 0x%08x\n",
2544 *(log + i), *(log + i + 1),
2545 *(log + i + 2), *(log + i + 3));
2546
2547 kunmap_atomic(log);
2548 }
2549
2550 seq_putc(m, '\n');
2551
2552 return 0;
2553}
2554
e91fd8c6
RV		 2555static int i915_edp_psr_status(struct seq_file *m, void *data)
2556{
2557 struct drm_info_node *node = m->private;
2558 struct drm_device *dev = node->minor->dev;
2559 struct drm_i915_private *dev_priv = dev->dev_private;
a031d709 2560 u32 psrperf = 0;
a6cbdb8e
RV		 2561 u32 stat[3];
2562 enum pipe pipe;
a031d709 2563 bool enabled = false;
e91fd8c6 2564
3553a8ea
DL		 2565 if (!HAS_PSR(dev)) {
2566 seq_puts(m, "PSR not supported\n");
2567 return 0;
2568 }
2569
c8c8fb33
PZ		 2570 intel_runtime_pm_get(dev_priv);
2571
fa128fa6 2572 mutex_lock(&dev_priv->psr.lock);
a031d709
RV		 2573 seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
2574 seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
2807cf69 2575 seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
5755c78f 2576 seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
fa128fa6
DV		 2577 seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
2578 dev_priv->psr.busy_frontbuffer_bits);
2579 seq_printf(m, "Re-enable work scheduled: %s\n",
2580 yesno(work_busy(&dev_priv->psr.work.work)));
e91fd8c6 2581
3553a8ea 2582 if (HAS_DDI(dev))
443a389f 2583 enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
3553a8ea
DL		 2584 else {
2585 for_each_pipe(dev_priv, pipe) {
2586 stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
2587 VLV_EDP_PSR_CURR_STATE_MASK;
2588 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2589 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2590 enabled = true;
a6cbdb8e
RV		 2591 }
2592 }
60e5ffe3
RV		 2593
2594 seq_printf(m, "Main link in standby mode: %s\n",
2595 yesno(dev_priv->psr.link_standby));
2596
a6cbdb8e
RV		 2597 seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));
2598
2599 if (!HAS_DDI(dev))
2600 for_each_pipe(dev_priv, pipe) {
2601 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2602 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2603 seq_printf(m, " pipe %c", pipe_name(pipe));
2604 }
2605 seq_puts(m, "\n");
e91fd8c6 2606
05eec3c2
RV		 2607 /*
2608 * VLV/CHV PSR has no kind of performance counter
2609 * SKL+ Perf counter is reset to 0 everytime DC state is entered
2610 */
2611 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
443a389f 2612 psrperf = I915_READ(EDP_PSR_PERF_CNT) &
a031d709 2613 EDP_PSR_PERF_CNT_MASK;
a6cbdb8e
RV		 2614
2615 seq_printf(m, "Performance_Counter: %u\n", psrperf);
2616 }
fa128fa6 2617 mutex_unlock(&dev_priv->psr.lock);
e91fd8c6 2618
c8c8fb33 2619 intel_runtime_pm_put(dev_priv);
e91fd8c6
RV		 2620 return 0;
2621}
2622
d2e216d0
RV		 2623static int i915_sink_crc(struct seq_file *m, void *data)
2624{
2625 struct drm_info_node *node = m->private;
2626 struct drm_device *dev = node->minor->dev;
2627 struct intel_encoder *encoder;
2628 struct intel_connector *connector;
2629 struct intel_dp *intel_dp = NULL;
2630 int ret;
2631 u8 crc[6];
2632
2633 drm_modeset_lock_all(dev);
aca5e361 2634 for_each_intel_connector(dev, connector) {
d2e216d0
RV		 2635
2636 if (connector->base.dpms != DRM_MODE_DPMS_ON)
2637 continue;
2638
b6ae3c7c
PZ		 2639 if (!connector->base.encoder)
2640 continue;
2641
d2e216d0
RV		 2642 encoder = to_intel_encoder(connector->base.encoder);
2643 if (encoder->type != INTEL_OUTPUT_EDP)
2644 continue;
2645
2646 intel_dp = enc_to_intel_dp(&encoder->base);
2647
2648 ret = intel_dp_sink_crc(intel_dp, crc);
2649 if (ret)
2650 goto out;
2651
2652 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2653 crc[0], crc[1], crc[2],
2654 crc[3], crc[4], crc[5]);
2655 goto out;
2656 }
2657 ret = -ENODEV;
2658out:
2659 drm_modeset_unlock_all(dev);
2660 return ret;
2661}
2662
ec013e7f
JB		 2663static int i915_energy_uJ(struct seq_file *m, void *data)
2664{
2665 struct drm_info_node *node = m->private;
2666 struct drm_device *dev = node->minor->dev;
2667 struct drm_i915_private *dev_priv = dev->dev_private;
2668 u64 power;
2669 u32 units;
2670
2671 if (INTEL_INFO(dev)->gen < 6)
2672 return -ENODEV;
2673
36623ef8
PZ		 2674 intel_runtime_pm_get(dev_priv);
2675
ec013e7f
JB		 2676 rdmsrl(MSR_RAPL_POWER_UNIT, power);
2677 power = (power & 0x1f00) >> 8;
2678 units = 1000000 / (1 << power); /* convert to uJ */
2679 power = I915_READ(MCH_SECP_NRG_STTS);
2680 power *= units;
2681
36623ef8
PZ		 2682 intel_runtime_pm_put(dev_priv);
2683
ec013e7f 2684 seq_printf(m, "%llu", (long long unsigned)power);
371db66a
PZ		 2685
2686 return 0;
2687}
2688
6455c870 2689static int i915_runtime_pm_status(struct seq_file *m, void *unused)
371db66a 2690{
9f25d007 2691 struct drm_info_node *node = m->private;
371db66a
PZ		 2692 struct drm_device *dev = node->minor->dev;
2693 struct drm_i915_private *dev_priv = dev->dev_private;
2694
6455c870 2695 if (!HAS_RUNTIME_PM(dev)) {
371db66a
PZ		 2696 seq_puts(m, "not supported\n");
2697 return 0;
2698 }
2699
86c4ec0d 2700 seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy));
371db66a 2701 seq_printf(m, "IRQs disabled: %s\n",
9df7575f 2702 yesno(!intel_irqs_enabled(dev_priv)));
0d804184 2703#ifdef CONFIG_PM
a6aaec8b
DL		 2704 seq_printf(m, "Usage count: %d\n",
2705 atomic_read(&dev->dev->power.usage_count));
0d804184
CW		 2706#else
2707 seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n");
2708#endif
371db66a 2709
ec013e7f
JB		 2710 return 0;
2711}
2712
1da51581
ID		 2713static int i915_power_domain_info(struct seq_file *m, void *unused)
2714{
9f25d007 2715 struct drm_info_node *node = m->private;
1da51581
ID		 2716 struct drm_device *dev = node->minor->dev;
2717 struct drm_i915_private *dev_priv = dev->dev_private;
2718 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2719 int i;
2720
2721 mutex_lock(&power_domains->lock);
2722
2723 seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2724 for (i = 0; i < power_domains->power_well_count; i++) {
2725 struct i915_power_well *power_well;
2726 enum intel_display_power_domain power_domain;
2727
2728 power_well = &power_domains->power_wells[i];
2729 seq_printf(m, "%-25s %d\n", power_well->name,
2730 power_well->count);
2731
2732 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
2733 power_domain++) {
2734 if (!(BIT(power_domain) & power_well->domains))
2735 continue;
2736
2737 seq_printf(m, " %-23s %d\n",
9895ad03 2738 intel_display_power_domain_str(power_domain),
1da51581
ID		 2739 power_domains->domain_use_count[power_domain]);
2740 }
2741 }
2742
2743 mutex_unlock(&power_domains->lock);
2744
2745 return 0;
2746}
2747
b7cec66d
DL		 2748static int i915_dmc_info(struct seq_file *m, void *unused)
2749{
2750 struct drm_info_node *node = m->private;
2751 struct drm_device *dev = node->minor->dev;
2752 struct drm_i915_private *dev_priv = dev->dev_private;
2753 struct intel_csr *csr;
2754
2755 if (!HAS_CSR(dev)) {
2756 seq_puts(m, "not supported\n");
2757 return 0;
2758 }
2759
2760 csr = &dev_priv->csr;
2761
6fb403de
MK		 2762 intel_runtime_pm_get(dev_priv);
2763
b7cec66d
DL		 2764 seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload != NULL));
2765 seq_printf(m, "path: %s\n", csr->fw_path);
2766
2767 if (!csr->dmc_payload)
6fb403de 2768 goto out;
b7cec66d
DL		 2769
2770 seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
2771 CSR_VERSION_MINOR(csr->version));
2772
8337206d
DL		 2773 if (IS_SKYLAKE(dev) && csr->version >= CSR_VERSION(1, 6)) {
2774 seq_printf(m, "DC3 -> DC5 count: %d\n",
2775 I915_READ(SKL_CSR_DC3_DC5_COUNT));
2776 seq_printf(m, "DC5 -> DC6 count: %d\n",
2777 I915_READ(SKL_CSR_DC5_DC6_COUNT));
16e11b99
MK		 2778 } else if (IS_BROXTON(dev) && csr->version >= CSR_VERSION(1, 4)) {
2779 seq_printf(m, "DC3 -> DC5 count: %d\n",
2780 I915_READ(BXT_CSR_DC3_DC5_COUNT));
8337206d
DL		 2781 }
2782
6fb403de
MK		 2783out:
2784 seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0)));
2785 seq_printf(m, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE));
2786 seq_printf(m, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL));
2787
8337206d
DL		 2788 intel_runtime_pm_put(dev_priv);
2789
b7cec66d
DL		 2790 return 0;
2791}
2792
53f5e3ca
JB		 2793static void intel_seq_print_mode(struct seq_file *m, int tabs,
2794 struct drm_display_mode *mode)
2795{
2796 int i;
2797
2798 for (i = 0; i < tabs; i++)
2799 seq_putc(m, '\t');
2800
2801 seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2802 mode->base.id, mode->name,
2803 mode->vrefresh, mode->clock,
2804 mode->hdisplay, mode->hsync_start,
2805 mode->hsync_end, mode->htotal,
2806 mode->vdisplay, mode->vsync_start,
2807 mode->vsync_end, mode->vtotal,
2808 mode->type, mode->flags);
2809}
2810
2811static void intel_encoder_info(struct seq_file *m,
2812 struct intel_crtc *intel_crtc,
2813 struct intel_encoder *intel_encoder)
2814{
9f25d007 2815 struct drm_info_node *node = m->private;
53f5e3ca
JB		 2816 struct drm_device *dev = node->minor->dev;
2817 struct drm_crtc *crtc = &intel_crtc->base;
2818 struct intel_connector *intel_connector;
2819 struct drm_encoder *encoder;
2820
2821 encoder = &intel_encoder->base;
2822 seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
8e329a03 2823 encoder->base.id, encoder->name);
53f5e3ca
JB		 2824 for_each_connector_on_encoder(dev, encoder, intel_connector) {
2825 struct drm_connector *connector = &intel_connector->base;
2826 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2827 connector->base.id,
c23cc417 2828 connector->name,
53f5e3ca
JB		 2829 drm_get_connector_status_name(connector->status));
2830 if (connector->status == connector_status_connected) {
2831 struct drm_display_mode *mode = &crtc->mode;
2832 seq_printf(m, ", mode:\n");
2833 intel_seq_print_mode(m, 2, mode);
2834 } else {
2835 seq_putc(m, '\n');
2836 }
2837 }
2838}
2839
2840static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2841{
9f25d007 2842 struct drm_info_node *node = m->private;
53f5e3ca
JB		 2843 struct drm_device *dev = node->minor->dev;
2844 struct drm_crtc *crtc = &intel_crtc->base;
2845 struct intel_encoder *intel_encoder;
23a48d53
ML		 2846 struct drm_plane_state *plane_state = crtc->primary->state;
2847 struct drm_framebuffer *fb = plane_state->fb;
53f5e3ca 2848
23a48d53 2849 if (fb)
5aa8a937 2850 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
23a48d53
ML		 2851 fb->base.id, plane_state->src_x >> 16,
2852 plane_state->src_y >> 16, fb->width, fb->height);
5aa8a937
MR		 2853 else
2854 seq_puts(m, "\tprimary plane disabled\n");
53f5e3ca
JB		 2855 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2856 intel_encoder_info(m, intel_crtc, intel_encoder);
2857}
2858
2859static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2860{
2861 struct drm_display_mode *mode = panel->fixed_mode;
2862
2863 seq_printf(m, "\tfixed mode:\n");
2864 intel_seq_print_mode(m, 2, mode);
2865}
2866
2867static void intel_dp_info(struct seq_file *m,
2868 struct intel_connector *intel_connector)
2869{
2870 struct intel_encoder *intel_encoder = intel_connector->encoder;
2871 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2872
2873 seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
742f491d 2874 seq_printf(m, "\taudio support: %s\n", yesno(intel_dp->has_audio));
53f5e3ca
JB		 2875 if (intel_encoder->type == INTEL_OUTPUT_EDP)
2876 intel_panel_info(m, &intel_connector->panel);
2877}
2878
3d52ccf5
LY		 2879static void intel_dp_mst_info(struct seq_file *m,
2880 struct intel_connector *intel_connector)
2881{
2882 struct intel_encoder *intel_encoder = intel_connector->encoder;
2883 struct intel_dp_mst_encoder *intel_mst =
2884 enc_to_mst(&intel_encoder->base);
2885 struct intel_digital_port *intel_dig_port = intel_mst->primary;
2886 struct intel_dp *intel_dp = &intel_dig_port->dp;
2887 bool has_audio = drm_dp_mst_port_has_audio(&intel_dp->mst_mgr,
2888 intel_connector->port);
2889
2890 seq_printf(m, "\taudio support: %s\n", yesno(has_audio));
2891}
2892
53f5e3ca
JB		 2893static void intel_hdmi_info(struct seq_file *m,
2894 struct intel_connector *intel_connector)
2895{
2896 struct intel_encoder *intel_encoder = intel_connector->encoder;
2897 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2898
742f491d 2899 seq_printf(m, "\taudio support: %s\n", yesno(intel_hdmi->has_audio));
53f5e3ca
JB		 2900}
2901
2902static void intel_lvds_info(struct seq_file *m,
2903 struct intel_connector *intel_connector)
2904{
2905 intel_panel_info(m, &intel_connector->panel);
2906}
2907
2908static void intel_connector_info(struct seq_file *m,
2909 struct drm_connector *connector)
2910{
2911 struct intel_connector *intel_connector = to_intel_connector(connector);
2912 struct intel_encoder *intel_encoder = intel_connector->encoder;
f103fc7d 2913 struct drm_display_mode *mode;
53f5e3ca
JB		 2914
2915 seq_printf(m, "connector %d: type %s, status: %s\n",
c23cc417 2916 connector->base.id, connector->name,
53f5e3ca
JB		 2917 drm_get_connector_status_name(connector->status));
2918 if (connector->status == connector_status_connected) {
2919 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2920 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2921 connector->display_info.width_mm,
2922 connector->display_info.height_mm);
2923 seq_printf(m, "\tsubpixel order: %s\n",
2924 drm_get_subpixel_order_name(connector->display_info.subpixel_order));
2925 seq_printf(m, "\tCEA rev: %d\n",
2926 connector->display_info.cea_rev);
2927 }
36cd7444
DA		 2928 if (intel_encoder) {
2929 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2930 intel_encoder->type == INTEL_OUTPUT_EDP)
2931 intel_dp_info(m, intel_connector);
2932 else if (intel_encoder->type == INTEL_OUTPUT_HDMI)
2933 intel_hdmi_info(m, intel_connector);
2934 else if (intel_encoder->type == INTEL_OUTPUT_LVDS)
2935 intel_lvds_info(m, intel_connector);
3d52ccf5
LY		 2936 else if (intel_encoder->type == INTEL_OUTPUT_DP_MST)
2937 intel_dp_mst_info(m, intel_connector);
36cd7444 2938 }
53f5e3ca 2939
f103fc7d
JB		 2940 seq_printf(m, "\tmodes:\n");
2941 list_for_each_entry(mode, &connector->modes, head)
2942 intel_seq_print_mode(m, 2, mode);
53f5e3ca
JB		 2943}
2944
065f2ec2
CW		 2945static bool cursor_active(struct drm_device *dev, int pipe)
2946{
2947 struct drm_i915_private *dev_priv = dev->dev_private;
2948 u32 state;
2949
2950 if (IS_845G(dev) || IS_I865G(dev))
0b87c24e 2951 state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
065f2ec2 2952 else
5efb3e28 2953 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
065f2ec2
CW		 2954
2955 return state;
2956}
2957
2958static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y)
2959{
2960 struct drm_i915_private *dev_priv = dev->dev_private;
2961 u32 pos;
2962
5efb3e28 2963 pos = I915_READ(CURPOS(pipe));
065f2ec2
CW		 2964
2965 *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
2966 if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
2967 *x = -*x;
2968
2969 *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
2970 if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
2971 *y = -*y;
2972
2973 return cursor_active(dev, pipe);
2974}
2975
3abc4e09
RF		 2976static const char *plane_type(enum drm_plane_type type)
2977{
2978 switch (type) {
2979 case DRM_PLANE_TYPE_OVERLAY:
2980 return "OVL";
2981 case DRM_PLANE_TYPE_PRIMARY:
2982 return "PRI";
2983 case DRM_PLANE_TYPE_CURSOR:
2984 return "CUR";
2985 /*
2986 * Deliberately omitting default: to generate compiler warnings
2987 * when a new drm_plane_type gets added.
2988 */
2989 }
2990
2991 return "unknown";
2992}
2993
2994static const char *plane_rotation(unsigned int rotation)
2995{
2996 static char buf[48];
2997 /*
2998 * According to doc only one DRM_ROTATE_ is allowed but this
2999 * will print them all to visualize if the values are misused
3000 */
3001 snprintf(buf, sizeof(buf),
3002 "%s%s%s%s%s%s(0x%08x)",
3003 (rotation & BIT(DRM_ROTATE_0)) ? "0 " : "",
3004 (rotation & BIT(DRM_ROTATE_90)) ? "90 " : "",
3005 (rotation & BIT(DRM_ROTATE_180)) ? "180 " : "",
3006 (rotation & BIT(DRM_ROTATE_270)) ? "270 " : "",
3007 (rotation & BIT(DRM_REFLECT_X)) ? "FLIPX " : "",
3008 (rotation & BIT(DRM_REFLECT_Y)) ? "FLIPY " : "",
3009 rotation);
3010
3011 return buf;
3012}
3013
3014static void intel_plane_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3015{
3016 struct drm_info_node *node = m->private;
3017 struct drm_device *dev = node->minor->dev;
3018 struct intel_plane *intel_plane;
3019
3020 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3021 struct drm_plane_state *state;
3022 struct drm_plane *plane = &intel_plane->base;
3023
3024 if (!plane->state) {
3025 seq_puts(m, "plane->state is NULL!\n");
3026 continue;
3027 }
3028
3029 state = plane->state;
3030
3031 seq_printf(m, "\t--Plane id %d: type=%s, crtc_pos=%4dx%4d, crtc_size=%4dx%4d, src_pos=%d.%04ux%d.%04u, src_size=%d.%04ux%d.%04u, format=%s, rotation=%s\n",
3032 plane->base.id,
3033 plane_type(intel_plane->base.type),
3034 state->crtc_x, state->crtc_y,
3035 state->crtc_w, state->crtc_h,
3036 (state->src_x >> 16),
3037 ((state->src_x & 0xffff) * 15625) >> 10,
3038 (state->src_y >> 16),
3039 ((state->src_y & 0xffff) * 15625) >> 10,
3040 (state->src_w >> 16),
3041 ((state->src_w & 0xffff) * 15625) >> 10,
3042 (state->src_h >> 16),
3043 ((state->src_h & 0xffff) * 15625) >> 10,
3044 state->fb ? drm_get_format_name(state->fb->pixel_format) : "N/A",
3045 plane_rotation(state->rotation));
3046 }
3047}
3048
3049static void intel_scaler_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3050{
3051 struct intel_crtc_state *pipe_config;
3052 int num_scalers = intel_crtc->num_scalers;
3053 int i;
3054
3055 pipe_config = to_intel_crtc_state(intel_crtc->base.state);
3056
3057 /* Not all platformas have a scaler */
3058 if (num_scalers) {
3059 seq_printf(m, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d",
3060 num_scalers,
3061 pipe_config->scaler_state.scaler_users,
3062 pipe_config->scaler_state.scaler_id);
3063
3064 for (i = 0; i < SKL_NUM_SCALERS; i++) {
3065 struct intel_scaler *sc =
3066 &pipe_config->scaler_state.scalers[i];
3067
3068 seq_printf(m, ", scalers[%d]: use=%s, mode=%x",
3069 i, yesno(sc->in_use), sc->mode);
3070 }
3071 seq_puts(m, "\n");
3072 } else {
3073 seq_puts(m, "\tNo scalers available on this platform\n");
3074 }
3075}
3076
53f5e3ca
JB		 3077static int i915_display_info(struct seq_file *m, void *unused)
3078{
9f25d007 3079 struct drm_info_node *node = m->private;
53f5e3ca 3080 struct drm_device *dev = node->minor->dev;
b0e5ddf3 3081 struct drm_i915_private *dev_priv = dev->dev_private;
065f2ec2 3082 struct intel_crtc *crtc;
53f5e3ca
JB		 3083 struct drm_connector *connector;
3084
b0e5ddf3 3085 intel_runtime_pm_get(dev_priv);
53f5e3ca
JB		 3086 drm_modeset_lock_all(dev);
3087 seq_printf(m, "CRTC info\n");
3088 seq_printf(m, "---------\n");
d3fcc808 3089 for_each_intel_crtc(dev, crtc) {
065f2ec2 3090 bool active;
f77076c9 3091 struct intel_crtc_state *pipe_config;
065f2ec2 3092 int x, y;
53f5e3ca 3093
f77076c9
ML		 3094 pipe_config = to_intel_crtc_state(crtc->base.state);
3095
3abc4e09 3096 seq_printf(m, "CRTC %d: pipe: %c, active=%s, (size=%dx%d), dither=%s, bpp=%d\n",
065f2ec2 3097 crtc->base.base.id, pipe_name(crtc->pipe),
f77076c9 3098 yesno(pipe_config->base.active),
3abc4e09
RF		 3099 pipe_config->pipe_src_w, pipe_config->pipe_src_h,
3100 yesno(pipe_config->dither), pipe_config->pipe_bpp);
3101
f77076c9 3102 if (pipe_config->base.active) {
065f2ec2
CW		 3103 intel_crtc_info(m, crtc);
3104
a23dc658 3105 active = cursor_position(dev, crtc->pipe, &x, &y);
57127efa 3106 seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
4b0e333e 3107 yesno(crtc->cursor_base),
3dd512fb
MR		 3108 x, y, crtc->base.cursor->state->crtc_w,
3109 crtc->base.cursor->state->crtc_h,
57127efa 3110 crtc->cursor_addr, yesno(active));
3abc4e09
RF		 3111 intel_scaler_info(m, crtc);
3112 intel_plane_info(m, crtc);
a23dc658 3113 }
cace841c
DV		 3114
3115 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
3116 yesno(!crtc->cpu_fifo_underrun_disabled),
3117 yesno(!crtc->pch_fifo_underrun_disabled));
53f5e3ca
JB		 3118 }
3119
3120 seq_printf(m, "\n");
3121 seq_printf(m, "Connector info\n");
3122 seq_printf(m, "--------------\n");
3123 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3124 intel_connector_info(m, connector);
3125 }
3126 drm_modeset_unlock_all(dev);
b0e5ddf3 3127 intel_runtime_pm_put(dev_priv);
53f5e3ca
JB		 3128
3129 return 0;
3130}
3131
e04934cf
BW		 3132static int i915_semaphore_status(struct seq_file *m, void *unused)
3133{
3134 struct drm_info_node *node = (struct drm_info_node *) m->private;
3135 struct drm_device *dev = node->minor->dev;
3136 struct drm_i915_private *dev_priv = dev->dev_private;
e2f80391 3137 struct intel_engine_cs *engine;
e04934cf 3138 int num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
c3232b18
DG		 3139 enum intel_engine_id id;
3140 int j, ret;
e04934cf
BW		 3141
3142 if (!i915_semaphore_is_enabled(dev)) {
3143 seq_puts(m, "Semaphores are disabled\n");
3144 return 0;
3145 }
3146
3147 ret = mutex_lock_interruptible(&dev->struct_mutex);
3148 if (ret)
3149 return ret;
03872064 3150 intel_runtime_pm_get(dev_priv);
e04934cf
BW		 3151
3152 if (IS_BROADWELL(dev)) {
3153 struct page *page;
3154 uint64_t *seqno;
3155
3156 page = i915_gem_object_get_page(dev_priv->semaphore_obj, 0);
3157
3158 seqno = (uint64_t *)kmap_atomic(page);
c3232b18 3159 for_each_engine_id(engine, dev_priv, id) {
e04934cf
BW		 3160 uint64_t offset;
3161
e2f80391 3162 seq_printf(m, "%s\n", engine->name);
e04934cf
BW		 3163
3164 seq_puts(m, " Last signal:");
3165 for (j = 0; j < num_rings; j++) {
c3232b18 3166 offset = id * I915_NUM_ENGINES + j;
e04934cf
BW		 3167 seq_printf(m, "0x%08llx (0x%02llx) ",
3168 seqno[offset], offset * 8);
3169 }
3170 seq_putc(m, '\n');
3171
3172 seq_puts(m, " Last wait: ");
3173 for (j = 0; j < num_rings; j++) {
c3232b18 3174 offset = id + (j * I915_NUM_ENGINES);
e04934cf
BW		 3175 seq_printf(m, "0x%08llx (0x%02llx) ",
3176 seqno[offset], offset * 8);
3177 }
3178 seq_putc(m, '\n');
3179
3180 }
3181 kunmap_atomic(seqno);
3182 } else {
3183 seq_puts(m, " Last signal:");
c3232b18 3184 for_each_engine(engine, dev_priv, id)
e04934cf
BW		 3185 for (j = 0; j < num_rings; j++)
3186 seq_printf(m, "0x%08x\n",
e2f80391 3187 I915_READ(engine->semaphore.mbox.signal[j]));
e04934cf
BW		 3188 seq_putc(m, '\n');
3189 }
3190
3191 seq_puts(m, "\nSync seqno:\n");
c3232b18 3192 for_each_engine(engine, dev_priv, id) {
e04934cf 3193 for (j = 0; j < num_rings; j++) {
e2f80391
TU		 3194 seq_printf(m, " 0x%08x ",
3195 engine->semaphore.sync_seqno[j]);
e04934cf
BW		 3196 }
3197 seq_putc(m, '\n');
3198 }
3199 seq_putc(m, '\n');
3200
03872064 3201 intel_runtime_pm_put(dev_priv);
e04934cf
BW		 3202 mutex_unlock(&dev->struct_mutex);
3203 return 0;
3204}
3205
728e29d7
DV		 3206static int i915_shared_dplls_info(struct seq_file *m, void *unused)
3207{
3208 struct drm_info_node *node = (struct drm_info_node *) m->private;
3209 struct drm_device *dev = node->minor->dev;
3210 struct drm_i915_private *dev_priv = dev->dev_private;
3211 int i;
3212
3213 drm_modeset_lock_all(dev);
3214 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3215 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
3216
3217 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
2dd66ebd
ML		 3218 seq_printf(m, " crtc_mask: 0x%08x, active: 0x%x, on: %s\n",
3219 pll->config.crtc_mask, pll->active_mask, yesno(pll->on));
728e29d7 3220 seq_printf(m, " tracked hardware state:\n");
3e369b76
ACO		 3221 seq_printf(m, " dpll: 0x%08x\n", pll->config.hw_state.dpll);
3222 seq_printf(m, " dpll_md: 0x%08x\n",
3223 pll->config.hw_state.dpll_md);
3224 seq_printf(m, " fp0: 0x%08x\n", pll->config.hw_state.fp0);
3225 seq_printf(m, " fp1: 0x%08x\n", pll->config.hw_state.fp1);
3226 seq_printf(m, " wrpll: 0x%08x\n", pll->config.hw_state.wrpll);
728e29d7
DV		 3227 }
3228 drm_modeset_unlock_all(dev);
3229
3230 return 0;
3231}
3232
1ed1ef9d 3233static int i915_wa_registers(struct seq_file *m, void *unused)
888b5995
AS		 3234{
3235 int i;
3236 int ret;
e2f80391 3237 struct intel_engine_cs *engine;
888b5995
AS		 3238 struct drm_info_node *node = (struct drm_info_node *) m->private;
3239 struct drm_device *dev = node->minor->dev;
3240 struct drm_i915_private *dev_priv = dev->dev_private;
33136b06 3241 struct i915_workarounds *workarounds = &dev_priv->workarounds;
c3232b18 3242 enum intel_engine_id id;
888b5995 3243
888b5995
AS		 3244 ret = mutex_lock_interruptible(&dev->struct_mutex);
3245 if (ret)
3246 return ret;
3247
3248 intel_runtime_pm_get(dev_priv);
3249
33136b06 3250 seq_printf(m, "Workarounds applied: %d\n", workarounds->count);
c3232b18 3251 for_each_engine_id(engine, dev_priv, id)
33136b06 3252 seq_printf(m, "HW whitelist count for %s: %d\n",
c3232b18 3253 engine->name, workarounds->hw_whitelist_count[id]);
33136b06 3254 for (i = 0; i < workarounds->count; ++i) {
f0f59a00
VS		 3255 i915_reg_t addr;
3256 u32 mask, value, read;
2fa60f6d 3257 bool ok;
888b5995 3258
33136b06
AS		 3259 addr = workarounds->reg[i].addr;
3260 mask = workarounds->reg[i].mask;
3261 value = workarounds->reg[i].value;
2fa60f6d
MK		 3262 read = I915_READ(addr);
3263 ok = (value & mask) == (read & mask);
3264 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
f0f59a00 3265 i915_mmio_reg_offset(addr), value, mask, read, ok ? "OK" : "FAIL");
888b5995
AS		 3266 }
3267
3268 intel_runtime_pm_put(dev_priv);
3269 mutex_unlock(&dev->struct_mutex);
3270
3271 return 0;
3272}
3273
c5511e44
DL		 3274static int i915_ddb_info(struct seq_file *m, void *unused)
3275{
3276 struct drm_info_node *node = m->private;
3277 struct drm_device *dev = node->minor->dev;
3278 struct drm_i915_private *dev_priv = dev->dev_private;
3279 struct skl_ddb_allocation *ddb;
3280 struct skl_ddb_entry *entry;
3281 enum pipe pipe;
3282 int plane;
3283
2fcffe19
DL		 3284 if (INTEL_INFO(dev)->gen < 9)
3285 return 0;
3286
c5511e44
DL		 3287 drm_modeset_lock_all(dev);
3288
3289 ddb = &dev_priv->wm.skl_hw.ddb;
3290
3291 seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
3292
3293 for_each_pipe(dev_priv, pipe) {
3294 seq_printf(m, "Pipe %c\n", pipe_name(pipe));
3295
dd740780 3296 for_each_plane(dev_priv, pipe, plane) {
c5511e44
DL		 3297 entry = &ddb->plane[pipe][plane];
3298 seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane + 1,
3299 entry->start, entry->end,
3300 skl_ddb_entry_size(entry));
3301 }
3302
4969d33e 3303 entry = &ddb->plane[pipe][PLANE_CURSOR];
c5511e44
DL		 3304 seq_printf(m, " %-13s%8u%8u%8u\n", "Cursor", entry->start,
3305 entry->end, skl_ddb_entry_size(entry));
3306 }
3307
3308 drm_modeset_unlock_all(dev);
3309
3310 return 0;
3311}
3312
a54746e3
VK		 3313static void drrs_status_per_crtc(struct seq_file *m,
3314 struct drm_device *dev, struct intel_crtc *intel_crtc)
3315{
3316 struct intel_encoder *intel_encoder;
3317 struct drm_i915_private *dev_priv = dev->dev_private;
3318 struct i915_drrs *drrs = &dev_priv->drrs;
3319 int vrefresh = 0;
3320
3321 for_each_encoder_on_crtc(dev, &intel_crtc->base, intel_encoder) {
3322 /* Encoder connected on this CRTC */
3323 switch (intel_encoder->type) {
3324 case INTEL_OUTPUT_EDP:
3325 seq_puts(m, "eDP:\n");
3326 break;
3327 case INTEL_OUTPUT_DSI:
3328 seq_puts(m, "DSI:\n");
3329 break;
3330 case INTEL_OUTPUT_HDMI:
3331 seq_puts(m, "HDMI:\n");
3332 break;
3333 case INTEL_OUTPUT_DISPLAYPORT:
3334 seq_puts(m, "DP:\n");
3335 break;
3336 default:
3337 seq_printf(m, "Other encoder (id=%d).\n",
3338 intel_encoder->type);
3339 return;
3340 }
3341 }
3342
3343 if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT)
3344 seq_puts(m, "\tVBT: DRRS_type: Static");
3345 else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT)
3346 seq_puts(m, "\tVBT: DRRS_type: Seamless");
3347 else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED)
3348 seq_puts(m, "\tVBT: DRRS_type: None");
3349 else
3350 seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value");
3351
3352 seq_puts(m, "\n\n");
3353
f77076c9 3354 if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) {
a54746e3
VK		 3355 struct intel_panel *panel;
3356
3357 mutex_lock(&drrs->mutex);
3358 /* DRRS Supported */
3359 seq_puts(m, "\tDRRS Supported: Yes\n");
3360
3361 /* disable_drrs() will make drrs->dp NULL */
3362 if (!drrs->dp) {
3363 seq_puts(m, "Idleness DRRS: Disabled");
3364 mutex_unlock(&drrs->mutex);
3365 return;
3366 }
3367
3368 panel = &drrs->dp->attached_connector->panel;
3369 seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X",
3370 drrs->busy_frontbuffer_bits);
3371
3372 seq_puts(m, "\n\t\t");
3373 if (drrs->refresh_rate_type == DRRS_HIGH_RR) {
3374 seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n");
3375 vrefresh = panel->fixed_mode->vrefresh;
3376 } else if (drrs->refresh_rate_type == DRRS_LOW_RR) {
3377 seq_puts(m, "DRRS_State: DRRS_LOW_RR\n");
3378 vrefresh = panel->downclock_mode->vrefresh;
3379 } else {
3380 seq_printf(m, "DRRS_State: Unknown(%d)\n",
3381 drrs->refresh_rate_type);
3382 mutex_unlock(&drrs->mutex);
3383 return;
3384 }
3385 seq_printf(m, "\t\tVrefresh: %d", vrefresh);
3386
3387 seq_puts(m, "\n\t\t");
3388 mutex_unlock(&drrs->mutex);
3389 } else {
3390 /* DRRS not supported. Print the VBT parameter*/
3391 seq_puts(m, "\tDRRS Supported : No");
3392 }
3393 seq_puts(m, "\n");
3394}
3395
3396static int i915_drrs_status(struct seq_file *m, void *unused)
3397{
3398 struct drm_info_node *node = m->private;
3399 struct drm_device *dev = node->minor->dev;
3400 struct intel_crtc *intel_crtc;
3401 int active_crtc_cnt = 0;
3402
3403 for_each_intel_crtc(dev, intel_crtc) {
3404 drm_modeset_lock(&intel_crtc->base.mutex, NULL);
3405
f77076c9 3406 if (intel_crtc->base.state->active) {
a54746e3
VK		 3407 active_crtc_cnt++;
3408 seq_printf(m, "\nCRTC %d: ", active_crtc_cnt);
3409
3410 drrs_status_per_crtc(m, dev, intel_crtc);
3411 }
3412
3413 drm_modeset_unlock(&intel_crtc->base.mutex);
3414 }
3415
3416 if (!active_crtc_cnt)
3417 seq_puts(m, "No active crtc found\n");
3418
3419 return 0;
3420}
3421
07144428
DL		 3422struct pipe_crc_info {
3423 const char *name;
3424 struct drm_device *dev;
3425 enum pipe pipe;
3426};
3427
11bed958
DA		 3428static int i915_dp_mst_info(struct seq_file *m, void *unused)
3429{
3430 struct drm_info_node *node = (struct drm_info_node *) m->private;
3431 struct drm_device *dev = node->minor->dev;
3432 struct drm_encoder *encoder;
3433 struct intel_encoder *intel_encoder;
3434 struct intel_digital_port *intel_dig_port;
3435 drm_modeset_lock_all(dev);
3436 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3437 intel_encoder = to_intel_encoder(encoder);
3438 if (intel_encoder->type != INTEL_OUTPUT_DISPLAYPORT)
3439 continue;
3440 intel_dig_port = enc_to_dig_port(encoder);
3441 if (!intel_dig_port->dp.can_mst)
3442 continue;
3443
3444 drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr);
3445 }
3446 drm_modeset_unlock_all(dev);
3447 return 0;
3448}
3449
07144428
DL		 3450static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
3451{
be5c7a90
DL		 3452 struct pipe_crc_info *info = inode->i_private;
3453 struct drm_i915_private *dev_priv = info->dev->dev_private;
3454 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3455
7eb1c496
DV		 3456 if (info->pipe >= INTEL_INFO(info->dev)->num_pipes)
3457 return -ENODEV;
3458
d538bbdf
DL		 3459 spin_lock_irq(&pipe_crc->lock);
3460
3461 if (pipe_crc->opened) {
3462 spin_unlock_irq(&pipe_crc->lock);
be5c7a90
DL		 3463 return -EBUSY; /* already open */
3464 }
3465
d538bbdf 3466 pipe_crc->opened = true;
07144428
DL		 3467 filep->private_data = inode->i_private;
3468
d538bbdf
DL		 3469 spin_unlock_irq(&pipe_crc->lock);
3470
07144428
DL		 3471 return 0;
3472}
3473
3474static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
3475{
be5c7a90
DL		 3476 struct pipe_crc_info *info = inode->i_private;
3477 struct drm_i915_private *dev_priv = info->dev->dev_private;
3478 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3479
d538bbdf
DL		 3480 spin_lock_irq(&pipe_crc->lock);
3481 pipe_crc->opened = false;
3482 spin_unlock_irq(&pipe_crc->lock);
be5c7a90 3483
07144428
DL		 3484 return 0;
3485}
3486
3487/* (6 fields, 8 chars each, space separated (5) + '\n') */
3488#define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
3489/* account for \'0' */
3490#define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1)
3491
3492static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
8bf1e9f1 3493{
d538bbdf
DL		 3494 assert_spin_locked(&pipe_crc->lock);
3495 return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3496 INTEL_PIPE_CRC_ENTRIES_NR);
07144428
DL		 3497}
3498
3499static ssize_t
3500i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
3501 loff_t *pos)
3502{
3503 struct pipe_crc_info *info = filep->private_data;
3504 struct drm_device *dev = info->dev;
3505 struct drm_i915_private *dev_priv = dev->dev_private;
3506 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3507 char buf[PIPE_CRC_BUFFER_LEN];
9ad6d99f 3508 int n_entries;
07144428
DL		 3509 ssize_t bytes_read;
3510
3511 /*
3512 * Don't allow user space to provide buffers not big enough to hold
3513 * a line of data.
3514 */
3515 if (count < PIPE_CRC_LINE_LEN)
3516 return -EINVAL;
3517
3518 if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
8bf1e9f1 3519 return 0;
07144428
DL		 3520
3521 /* nothing to read */
d538bbdf 3522 spin_lock_irq(&pipe_crc->lock);
07144428 3523 while (pipe_crc_data_count(pipe_crc) == 0) {
d538bbdf
DL		 3524 int ret;
3525
3526 if (filep->f_flags & O_NONBLOCK) {
3527 spin_unlock_irq(&pipe_crc->lock);
07144428 3528 return -EAGAIN;
d538bbdf 3529 }
07144428 3530
d538bbdf
DL		 3531 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
3532 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
3533 if (ret) {
3534 spin_unlock_irq(&pipe_crc->lock);
3535 return ret;
3536 }
8bf1e9f1
SH		 3537 }
3538
07144428 3539 /* We now have one or more entries to read */
9ad6d99f 3540 n_entries = count / PIPE_CRC_LINE_LEN;
d538bbdf 3541
07144428 3542 bytes_read = 0;
9ad6d99f
VS		 3543 while (n_entries > 0) {
3544 struct intel_pipe_crc_entry *entry =
3545 &pipe_crc->entries[pipe_crc->tail];
07144428 3546 int ret;
8bf1e9f1 3547
9ad6d99f
VS		 3548 if (CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3549 INTEL_PIPE_CRC_ENTRIES_NR) < 1)
3550 break;
3551
3552 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
3553 pipe_crc->tail = (pipe_crc->tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
3554
07144428
DL		 3555 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
3556 "%8u %8x %8x %8x %8x %8x\n",
3557 entry->frame, entry->crc[0],
3558 entry->crc[1], entry->crc[2],
3559 entry->crc[3], entry->crc[4]);
3560
9ad6d99f
VS		 3561 spin_unlock_irq(&pipe_crc->lock);
3562
3563 ret = copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN);
07144428
DL		 3564 if (ret == PIPE_CRC_LINE_LEN)
3565 return -EFAULT;
b2c88f5b 3566
9ad6d99f
VS		 3567 user_buf += PIPE_CRC_LINE_LEN;
3568 n_entries--;
3569
3570 spin_lock_irq(&pipe_crc->lock);
3571 }
8bf1e9f1 3572
d538bbdf
DL		 3573 spin_unlock_irq(&pipe_crc->lock);
3574
07144428
DL		 3575 return bytes_read;
3576}
3577
3578static const struct file_operations i915_pipe_crc_fops = {
3579 .owner = THIS_MODULE,
3580 .open = i915_pipe_crc_open,
3581 .read = i915_pipe_crc_read,
3582 .release = i915_pipe_crc_release,
3583};
3584
3585static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
3586 {
3587 .name = "i915_pipe_A_crc",
3588 .pipe = PIPE_A,
3589 },
3590 {
3591 .name = "i915_pipe_B_crc",
3592 .pipe = PIPE_B,
3593 },
3594 {
3595 .name = "i915_pipe_C_crc",
3596 .pipe = PIPE_C,
3597 },
3598};
3599
3600static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
3601 enum pipe pipe)
3602{
3603 struct drm_device *dev = minor->dev;
3604 struct dentry *ent;
3605 struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
3606
3607 info->dev = dev;
3608 ent = debugfs_create_file(info->name, S_IRUGO, root, info,
3609 &i915_pipe_crc_fops);
f3c5fe97
WY		 3610 if (!ent)
3611 return -ENOMEM;
07144428
DL		 3612
3613 return drm_add_fake_info_node(minor, ent, info);
8bf1e9f1
SH		 3614}
3615
e8dfcf78 3616static const char * const pipe_crc_sources[] = {
926321d5
DV		 3617 "none",
3618 "plane1",
3619 "plane2",
3620 "pf",
5b3a856b 3621 "pipe",
3d099a05
DV		 3622 "TV",
3623 "DP-B",
3624 "DP-C",
3625 "DP-D",
46a19188 3626 "auto",
926321d5
DV		 3627};
3628
3629static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
3630{
3631 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
3632 return pipe_crc_sources[source];
3633}
3634
bd9db02f 3635static int display_crc_ctl_show(struct seq_file *m, void *data)
926321d5
DV		 3636{
3637 struct drm_device *dev = m->private;
3638 struct drm_i915_private *dev_priv = dev->dev_private;
3639 int i;
3640
3641 for (i = 0; i < I915_MAX_PIPES; i++)
3642 seq_printf(m, "%c %s\n", pipe_name(i),
3643 pipe_crc_source_name(dev_priv->pipe_crc[i].source));
3644
3645 return 0;
3646}
3647
bd9db02f 3648static int display_crc_ctl_open(struct inode *inode, struct file *file)
926321d5
DV		 3649{
3650 struct drm_device *dev = inode->i_private;
3651
bd9db02f 3652 return single_open(file, display_crc_ctl_show, dev);
926321d5
DV		 3653}
3654
46a19188 3655static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
52f843f6
DV		 3656 uint32_t *val)
3657{
46a19188
DV		 3658 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3659 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3660
3661 switch (*source) {
52f843f6
DV		 3662 case INTEL_PIPE_CRC_SOURCE_PIPE:
3663 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
3664 break;
3665 case INTEL_PIPE_CRC_SOURCE_NONE:
3666 *val = 0;
3667 break;
3668 default:
3669 return -EINVAL;
3670 }
3671
3672 return 0;
3673}
3674
46a19188
DV		 3675static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe,
3676 enum intel_pipe_crc_source *source)
3677{
3678 struct intel_encoder *encoder;
3679 struct intel_crtc *crtc;
26756809 3680 struct intel_digital_port *dig_port;
46a19188
DV		 3681 int ret = 0;
3682
3683 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3684
6e9f798d 3685 drm_modeset_lock_all(dev);
b2784e15 3686 for_each_intel_encoder(dev, encoder) {
46a19188
DV		 3687 if (!encoder->base.crtc)
3688 continue;
3689
3690 crtc = to_intel_crtc(encoder->base.crtc);
3691
3692 if (crtc->pipe != pipe)
3693 continue;
3694
3695 switch (encoder->type) {
3696 case INTEL_OUTPUT_TVOUT:
3697 *source = INTEL_PIPE_CRC_SOURCE_TV;
3698 break;
3699 case INTEL_OUTPUT_DISPLAYPORT:
3700 case INTEL_OUTPUT_EDP:
26756809
DV		 3701 dig_port = enc_to_dig_port(&encoder->base);
3702 switch (dig_port->port) {
3703 case PORT_B:
3704 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
3705 break;
3706 case PORT_C:
3707 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
3708 break;
3709 case PORT_D:
3710 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
3711 break;
3712 default:
3713 WARN(1, "nonexisting DP port %c\n",
3714 port_name(dig_port->port));
3715 break;
3716 }
46a19188 3717 break;
6847d71b
PZ		 3718 default:
3719 break;
46a19188
DV		 3720 }
3721 }
6e9f798d 3722 drm_modeset_unlock_all(dev);
46a19188
DV		 3723
3724 return ret;
3725}
3726
3727static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
3728 enum pipe pipe,
3729 enum intel_pipe_crc_source *source,
7ac0129b
DV		 3730 uint32_t *val)
3731{
8d2f24ca
DV		 3732 struct drm_i915_private *dev_priv = dev->dev_private;
3733 bool need_stable_symbols = false;
3734
46a19188
DV		 3735 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3736 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3737 if (ret)
3738 return ret;
3739 }
3740
3741 switch (*source) {
7ac0129b
DV		 3742 case INTEL_PIPE_CRC_SOURCE_PIPE:
3743 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
3744 break;
3745 case INTEL_PIPE_CRC_SOURCE_DP_B:
3746 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
8d2f24ca 3747 need_stable_symbols = true;
7ac0129b
DV		 3748 break;
3749 case INTEL_PIPE_CRC_SOURCE_DP_C:
3750 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
8d2f24ca 3751 need_stable_symbols = true;
7ac0129b 3752 break;
2be57922
VS		 3753 case INTEL_PIPE_CRC_SOURCE_DP_D:
3754 if (!IS_CHERRYVIEW(dev))
3755 return -EINVAL;
3756 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV;
3757 need_stable_symbols = true;
3758 break;
7ac0129b
DV		 3759 case INTEL_PIPE_CRC_SOURCE_NONE:
3760 *val = 0;
3761 break;
3762 default:
3763 return -EINVAL;
3764 }
3765
8d2f24ca
DV		 3766 /*
3767 * When the pipe CRC tap point is after the transcoders we need
3768 * to tweak symbol-level features to produce a deterministic series of
3769 * symbols for a given frame. We need to reset those features only once
3770 * a frame (instead of every nth symbol):
3771 * - DC-balance: used to ensure a better clock recovery from the data
3772 * link (SDVO)
3773 * - DisplayPort scrambling: used for EMI reduction
3774 */
3775 if (need_stable_symbols) {
3776 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3777
8d2f24ca 3778 tmp |= DC_BALANCE_RESET_VLV;
eb736679
VS		 3779 switch (pipe) {
3780 case PIPE_A:
8d2f24ca 3781 tmp |= PIPE_A_SCRAMBLE_RESET;
eb736679
VS		 3782 break;
3783 case PIPE_B:
8d2f24ca 3784 tmp |= PIPE_B_SCRAMBLE_RESET;
eb736679
VS		 3785 break;
3786 case PIPE_C:
3787 tmp |= PIPE_C_SCRAMBLE_RESET;
3788 break;
3789 default:
3790 return -EINVAL;
3791 }
8d2f24ca
DV		 3792 I915_WRITE(PORT_DFT2_G4X, tmp);
3793 }
3794
7ac0129b
DV		 3795 return 0;
3796}
3797
4b79ebf7 3798static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
46a19188
DV		 3799 enum pipe pipe,
3800 enum intel_pipe_crc_source *source,
4b79ebf7
DV		 3801 uint32_t *val)
3802{
84093603
DV		 3803 struct drm_i915_private *dev_priv = dev->dev_private;
3804 bool need_stable_symbols = false;
3805
46a19188
DV		 3806 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3807 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3808 if (ret)
3809 return ret;
3810 }
3811
3812 switch (*source) {
4b79ebf7
DV		 3813 case INTEL_PIPE_CRC_SOURCE_PIPE:
3814 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
3815 break;
3816 case INTEL_PIPE_CRC_SOURCE_TV:
3817 if (!SUPPORTS_TV(dev))
3818 return -EINVAL;
3819 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
3820 break;
3821 case INTEL_PIPE_CRC_SOURCE_DP_B:
3822 if (!IS_G4X(dev))
3823 return -EINVAL;
3824 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
84093603 3825 need_stable_symbols = true;
4b79ebf7
DV		 3826 break;
3827 case INTEL_PIPE_CRC_SOURCE_DP_C:
3828 if (!IS_G4X(dev))
3829 return -EINVAL;
3830 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
84093603 3831 need_stable_symbols = true;
4b79ebf7
DV		 3832 break;
3833 case INTEL_PIPE_CRC_SOURCE_DP_D:
3834 if (!IS_G4X(dev))
3835 return -EINVAL;
3836 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
84093603 3837 need_stable_symbols = true;
4b79ebf7
DV		 3838 break;
3839 case INTEL_PIPE_CRC_SOURCE_NONE:
3840 *val = 0;
3841 break;
3842 default:
3843 return -EINVAL;
3844 }
3845
84093603
DV		 3846 /*
3847 * When the pipe CRC tap point is after the transcoders we need
3848 * to tweak symbol-level features to produce a deterministic series of
3849 * symbols for a given frame. We need to reset those features only once
3850 * a frame (instead of every nth symbol):
3851 * - DC-balance: used to ensure a better clock recovery from the data
3852 * link (SDVO)
3853 * - DisplayPort scrambling: used for EMI reduction
3854 */
3855 if (need_stable_symbols) {
3856 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3857
3858 WARN_ON(!IS_G4X(dev));
3859
3860 I915_WRITE(PORT_DFT_I9XX,
3861 I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
3862
3863 if (pipe == PIPE_A)
3864 tmp |= PIPE_A_SCRAMBLE_RESET;
3865 else
3866 tmp |= PIPE_B_SCRAMBLE_RESET;
3867
3868 I915_WRITE(PORT_DFT2_G4X, tmp);
3869 }
3870
4b79ebf7
DV		 3871 return 0;
3872}
3873
8d2f24ca
DV		 3874static void vlv_undo_pipe_scramble_reset(struct drm_device *dev,
3875 enum pipe pipe)
3876{
3877 struct drm_i915_private *dev_priv = dev->dev_private;
3878 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3879
eb736679
VS		 3880 switch (pipe) {
3881 case PIPE_A:
8d2f24ca 3882 tmp &= ~PIPE_A_SCRAMBLE_RESET;
eb736679
VS		 3883 break;
3884 case PIPE_B:
8d2f24ca 3885 tmp &= ~PIPE_B_SCRAMBLE_RESET;
eb736679
VS		 3886 break;
3887 case PIPE_C:
3888 tmp &= ~PIPE_C_SCRAMBLE_RESET;
3889 break;
3890 default:
3891 return;
3892 }
8d2f24ca
DV		 3893 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
3894 tmp &= ~DC_BALANCE_RESET_VLV;
3895 I915_WRITE(PORT_DFT2_G4X, tmp);
3896
3897}
3898
84093603
DV		 3899static void g4x_undo_pipe_scramble_reset(struct drm_device *dev,
3900 enum pipe pipe)
3901{
3902 struct drm_i915_private *dev_priv = dev->dev_private;
3903 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3904
3905 if (pipe == PIPE_A)
3906 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3907 else
3908 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3909 I915_WRITE(PORT_DFT2_G4X, tmp);
3910
3911 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
3912 I915_WRITE(PORT_DFT_I9XX,
3913 I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
3914 }
3915}
3916
46a19188 3917static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
5b3a856b
DV		 3918 uint32_t *val)
3919{
46a19188
DV		 3920 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3921 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3922
3923 switch (*source) {
5b3a856b
DV		 3924 case INTEL_PIPE_CRC_SOURCE_PLANE1:
3925 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
3926 break;
3927 case INTEL_PIPE_CRC_SOURCE_PLANE2:
3928 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
3929 break;
5b3a856b
DV		 3930 case INTEL_PIPE_CRC_SOURCE_PIPE:
3931 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
3932 break;
3d099a05 3933 case INTEL_PIPE_CRC_SOURCE_NONE:
5b3a856b
DV		 3934 *val = 0;
3935 break;
3d099a05
DV		 3936 default:
3937 return -EINVAL;
5b3a856b
DV		 3938 }
3939
3940 return 0;
3941}
3942
c4e2d043 3943static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device *dev, bool enable)
fabf6e51
DV		 3944{
3945 struct drm_i915_private *dev_priv = dev->dev_private;
3946 struct intel_crtc *crtc =
3947 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
f77076c9 3948 struct intel_crtc_state *pipe_config;
c4e2d043
ML		 3949 struct drm_atomic_state *state;
3950 int ret = 0;
fabf6e51
DV		 3951
3952 drm_modeset_lock_all(dev);
c4e2d043
ML		 3953 state = drm_atomic_state_alloc(dev);
3954 if (!state) {
3955 ret = -ENOMEM;
3956 goto out;
fabf6e51 3957 }
fabf6e51 3958
c4e2d043
ML		 3959 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(&crtc->base);
3960 pipe_config = intel_atomic_get_crtc_state(state, crtc);
3961 if (IS_ERR(pipe_config)) {
3962 ret = PTR_ERR(pipe_config);
3963 goto out;
3964 }
fabf6e51 3965
c4e2d043
ML		 3966 pipe_config->pch_pfit.force_thru = enable;
3967 if (pipe_config->cpu_transcoder == TRANSCODER_EDP &&
3968 pipe_config->pch_pfit.enabled != enable)
3969 pipe_config->base.connectors_changed = true;
1b509259 3970
c4e2d043
ML		 3971 ret = drm_atomic_commit(state);
3972out:
fabf6e51 3973 drm_modeset_unlock_all(dev);
c4e2d043
ML		 3974 WARN(ret, "Toggling workaround to %i returns %i\n", enable, ret);
3975 if (ret)
3976 drm_atomic_state_free(state);
fabf6e51
DV		 3977}
3978
3979static int ivb_pipe_crc_ctl_reg(struct drm_device *dev,
3980 enum pipe pipe,
3981 enum intel_pipe_crc_source *source,
5b3a856b
DV		 3982 uint32_t *val)
3983{
46a19188
DV		 3984 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3985 *source = INTEL_PIPE_CRC_SOURCE_PF;
3986
3987 switch (*source) {
5b3a856b
DV		 3988 case INTEL_PIPE_CRC_SOURCE_PLANE1:
3989 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
3990 break;
3991 case INTEL_PIPE_CRC_SOURCE_PLANE2:
3992 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
3993 break;
3994 case INTEL_PIPE_CRC_SOURCE_PF:
fabf6e51 3995 if (IS_HASWELL(dev) && pipe == PIPE_A)
c4e2d043 3996 hsw_trans_edp_pipe_A_crc_wa(dev, true);
fabf6e51 3997
5b3a856b
DV		 3998 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
3999 break;
3d099a05 4000 case INTEL_PIPE_CRC_SOURCE_NONE:
5b3a856b
DV		 4001 *val = 0;
4002 break;
3d099a05
DV		 4003 default:
4004 return -EINVAL;
5b3a856b
DV		 4005 }
4006
4007 return 0;
4008}
4009
926321d5
DV		 4010static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
4011 enum intel_pipe_crc_source source)
4012{
4013 struct drm_i915_private *dev_priv = dev->dev_private;
cc3da175 4014 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
8c740dce
PZ		 4015 struct intel_crtc *crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev,
4016 pipe));
e129649b 4017 enum intel_display_power_domain power_domain;
432f3342 4018 u32 val = 0; /* shut up gcc */
5b3a856b 4019 int ret;
926321d5 4020
cc3da175
DL		 4021 if (pipe_crc->source == source)
4022 return 0;
4023
ae676fcd
DL		 4024 /* forbid changing the source without going back to 'none' */
4025 if (pipe_crc->source && source)
4026 return -EINVAL;
4027
e129649b
ID		 4028 power_domain = POWER_DOMAIN_PIPE(pipe);
4029 if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) {
9d8b0588
DV		 4030 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
4031 return -EIO;
4032 }
4033
52f843f6 4034 if (IS_GEN2(dev))
46a19188 4035 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
52f843f6 4036 else if (INTEL_INFO(dev)->gen < 5)
46a19188 4037 ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
666a4537 4038 else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
fabf6e51 4039 ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val);
4b79ebf7 4040 else if (IS_GEN5(dev) || IS_GEN6(dev))
46a19188 4041 ret = ilk_pipe_crc_ctl_reg(&source, &val);
5b3a856b 4042 else
fabf6e51 4043 ret = ivb_pipe_crc_ctl_reg(dev, pipe, &source, &val);
5b3a856b
DV		 4044
4045 if (ret != 0)
e129649b 4046 goto out;
5b3a856b 4047
4b584369
DL		 4048 /* none -> real source transition */
4049 if (source) {
4252fbc3
VS		 4050 struct intel_pipe_crc_entry *entries;
4051
7cd6ccff
DL		 4052 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
4053 pipe_name(pipe), pipe_crc_source_name(source));
4054
3cf54b34
VS		 4055 entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR,
4056 sizeof(pipe_crc->entries[0]),
4252fbc3 4057 GFP_KERNEL);
e129649b
ID		 4058 if (!entries) {
4059 ret = -ENOMEM;
4060 goto out;
4061 }
e5f75aca 4062
8c740dce
PZ		 4063 /*
4064 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
4065 * enabled and disabled dynamically based on package C states,
4066 * user space can't make reliable use of the CRCs, so let's just
4067 * completely disable it.
4068 */
4069 hsw_disable_ips(crtc);
4070
d538bbdf 4071 spin_lock_irq(&pipe_crc->lock);
64387b61 4072 kfree(pipe_crc->entries);
4252fbc3 4073 pipe_crc->entries = entries;
d538bbdf
DL		 4074 pipe_crc->head = 0;
4075 pipe_crc->tail = 0;
4076 spin_unlock_irq(&pipe_crc->lock);
4b584369
DL		 4077 }
4078
cc3da175 4079 pipe_crc->source = source;
926321d5 4080
926321d5
DV		 4081 I915_WRITE(PIPE_CRC_CTL(pipe), val);
4082 POSTING_READ(PIPE_CRC_CTL(pipe));
4083
e5f75aca
DL		 4084 /* real source -> none transition */
4085 if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
d538bbdf 4086 struct intel_pipe_crc_entry *entries;
a33d7105
DV		 4087 struct intel_crtc *crtc =
4088 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
d538bbdf 4089
7cd6ccff
DL		 4090 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
4091 pipe_name(pipe));
4092
a33d7105 4093 drm_modeset_lock(&crtc->base.mutex, NULL);
f77076c9 4094 if (crtc->base.state->active)
a33d7105
DV		 4095 intel_wait_for_vblank(dev, pipe);
4096 drm_modeset_unlock(&crtc->base.mutex);
bcf17ab2 4097
d538bbdf
DL		 4098 spin_lock_irq(&pipe_crc->lock);
4099 entries = pipe_crc->entries;
e5f75aca 4100 pipe_crc->entries = NULL;
9ad6d99f
VS		 4101 pipe_crc->head = 0;
4102 pipe_crc->tail = 0;
d538bbdf
DL		 4103 spin_unlock_irq(&pipe_crc->lock);
4104
4105 kfree(entries);
84093603
DV		 4106
4107 if (IS_G4X(dev))
4108 g4x_undo_pipe_scramble_reset(dev, pipe);
666a4537 4109 else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
8d2f24ca 4110 vlv_undo_pipe_scramble_reset(dev, pipe);
fabf6e51 4111 else if (IS_HASWELL(dev) && pipe == PIPE_A)
c4e2d043 4112 hsw_trans_edp_pipe_A_crc_wa(dev, false);
8c740dce
PZ		 4113
4114 hsw_enable_ips(crtc);
e5f75aca
DL		 4115 }
4116
e129649b
ID		 4117 ret = 0;
4118
4119out:
4120 intel_display_power_put(dev_priv, power_domain);
4121
4122 return ret;
926321d5
DV		 4123}
4124
4125/*
4126 * Parse pipe CRC command strings:
b94dec87
DL		 4127 * command: wsp* object wsp+ name wsp+ source wsp*
4128 * object: 'pipe'
4129 * name: (A | B | C)
926321d5
DV		 4130 * source: (none | plane1 | plane2 | pf)
4131 * wsp: (#0x20 | #0x9 | #0xA)+
4132 *
4133 * eg.:
b94dec87
DL		 4134 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A
4135 * "pipe A none" -> Stop CRC
926321d5 4136 */
bd9db02f 4137static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
926321d5
DV		 4138{
4139 int n_words = 0;
4140
4141 while (*buf) {
4142 char *end;
4143
4144 /* skip leading white space */
4145 buf = skip_spaces(buf);
4146 if (!*buf)
4147 break; /* end of buffer */
4148
4149 /* find end of word */
4150 for (end = buf; *end && !isspace(*end); end++)
4151 ;
4152
4153 if (n_words == max_words) {
4154 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
4155 max_words);
4156 return -EINVAL; /* ran out of words[] before bytes */
4157 }
4158
4159 if (*end)
4160 *end++ = '\0';
4161 words[n_words++] = buf;
4162 buf = end;
4163 }
4164
4165 return n_words;
4166}
4167
b94dec87
DL		 4168enum intel_pipe_crc_object {
4169 PIPE_CRC_OBJECT_PIPE,
4170};
4171
e8dfcf78 4172static const char * const pipe_crc_objects[] = {
b94dec87
DL		 4173 "pipe",
4174};
4175
4176static int
bd9db02f 4177display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
b94dec87
DL		 4178{
4179 int i;
4180
4181 for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
4182 if (!strcmp(buf, pipe_crc_objects[i])) {
bd9db02f 4183 *o = i;
b94dec87
DL		 4184 return 0;
4185 }
4186
4187 return -EINVAL;
4188}
4189
bd9db02f 4190static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
926321d5
DV		 4191{
4192 const char name = buf[0];
4193
4194 if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
4195 return -EINVAL;
4196
4197 *pipe = name - 'A';
4198
4199 return 0;
4200}
4201
4202static int
bd9db02f 4203display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
926321d5
DV		 4204{
4205 int i;
4206
4207 for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
4208 if (!strcmp(buf, pipe_crc_sources[i])) {
bd9db02f 4209 *s = i;
926321d5
DV		 4210 return 0;
4211 }
4212
4213 return -EINVAL;
4214}
4215
bd9db02f 4216static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len)
926321d5 4217{
b94dec87 4218#define N_WORDS 3
926321d5 4219 int n_words;
b94dec87 4220 char *words[N_WORDS];
926321d5 4221 enum pipe pipe;
b94dec87 4222 enum intel_pipe_crc_object object;
926321d5
DV		 4223 enum intel_pipe_crc_source source;
4224
bd9db02f 4225 n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
b94dec87
DL		 4226 if (n_words != N_WORDS) {
4227 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
4228 N_WORDS);
4229 return -EINVAL;
4230 }
4231
bd9db02f 4232 if (display_crc_ctl_parse_object(words[0], &object) < 0) {
b94dec87 4233 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
926321d5
DV		 4234 return -EINVAL;
4235 }
4236
bd9db02f 4237 if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
b94dec87 4238 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
926321d5
DV		 4239 return -EINVAL;
4240 }
4241
bd9db02f 4242 if (display_crc_ctl_parse_source(words[2], &source) < 0) {
b94dec87 4243 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
926321d5
DV		 4244 return -EINVAL;
4245 }
4246
4247 return pipe_crc_set_source(dev, pipe, source);
4248}
4249
bd9db02f
DL		 4250static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
4251 size_t len, loff_t *offp)
926321d5
DV		 4252{
4253 struct seq_file *m = file->private_data;
4254 struct drm_device *dev = m->private;
4255 char *tmpbuf;
4256 int ret;
4257
4258 if (len == 0)
4259 return 0;
4260
4261 if (len > PAGE_SIZE - 1) {
4262 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
4263 PAGE_SIZE);
4264 return -E2BIG;
4265 }
4266
4267 tmpbuf = kmalloc(len + 1, GFP_KERNEL);
4268 if (!tmpbuf)
4269 return -ENOMEM;
4270
4271 if (copy_from_user(tmpbuf, ubuf, len)) {
4272 ret = -EFAULT;
4273 goto out;
4274 }
4275 tmpbuf[len] = '\0';
4276
bd9db02f 4277 ret = display_crc_ctl_parse(dev, tmpbuf, len);
926321d5
DV		 4278
4279out:
4280 kfree(tmpbuf);
4281 if (ret < 0)
4282 return ret;
4283
4284 *offp += len;
4285 return len;
4286}
4287
bd9db02f 4288static const struct file_operations i915_display_crc_ctl_fops = {
926321d5 4289 .owner = THIS_MODULE,
bd9db02f 4290 .open = display_crc_ctl_open,
926321d5
DV		 4291 .read = seq_read,
4292 .llseek = seq_lseek,
4293 .release = single_release,
bd9db02f 4294 .write = display_crc_ctl_write
926321d5
DV		 4295};
4296
eb3394fa
TP		 4297static ssize_t i915_displayport_test_active_write(struct file *file,
4298 const char __user *ubuf,
4299 size_t len, loff_t *offp)
4300{
4301 char *input_buffer;
4302 int status = 0;
eb3394fa
TP		 4303 struct drm_device *dev;
4304 struct drm_connector *connector;
4305 struct list_head *connector_list;
4306 struct intel_dp *intel_dp;
4307 int val = 0;
4308
9aaffa34 4309 dev = ((struct seq_file *)file->private_data)->private;
eb3394fa 4310
eb3394fa
TP		 4311 connector_list = &dev->mode_config.connector_list;
4312
4313 if (len == 0)
4314 return 0;
4315
4316 input_buffer = kmalloc(len + 1, GFP_KERNEL);
4317 if (!input_buffer)
4318 return -ENOMEM;
4319
4320 if (copy_from_user(input_buffer, ubuf, len)) {
4321 status = -EFAULT;
4322 goto out;
4323 }
4324
4325 input_buffer[len] = '\0';
4326 DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len);
4327
4328 list_for_each_entry(connector, connector_list, head) {
4329
4330 if (connector->connector_type !=
4331 DRM_MODE_CONNECTOR_DisplayPort)
4332 continue;
4333
b8bb08ec 4334 if (connector->status == connector_status_connected &&
eb3394fa
TP		 4335 connector->encoder != NULL) {
4336 intel_dp = enc_to_intel_dp(connector->encoder);
4337 status = kstrtoint(input_buffer, 10, &val);
4338 if (status < 0)
4339 goto out;
4340 DRM_DEBUG_DRIVER("Got %d for test active\n", val);
4341 /* To prevent erroneous activation of the compliance
4342 * testing code, only accept an actual value of 1 here
4343 */
4344 if (val == 1)
4345 intel_dp->compliance_test_active = 1;
4346 else
4347 intel_dp->compliance_test_active = 0;
4348 }
4349 }
4350out:
4351 kfree(input_buffer);
4352 if (status < 0)
4353 return status;
4354
4355 *offp += len;
4356 return len;
4357}
4358
4359static int i915_displayport_test_active_show(struct seq_file *m, void *data)
4360{
4361 struct drm_device *dev = m->private;
4362 struct drm_connector *connector;
4363 struct list_head *connector_list = &dev->mode_config.connector_list;
4364 struct intel_dp *intel_dp;
4365
eb3394fa
TP		 4366 list_for_each_entry(connector, connector_list, head) {
4367
4368 if (connector->connector_type !=
4369 DRM_MODE_CONNECTOR_DisplayPort)
4370 continue;
4371
4372 if (connector->status == connector_status_connected &&
4373 connector->encoder != NULL) {
4374 intel_dp = enc_to_intel_dp(connector->encoder);
4375 if (intel_dp->compliance_test_active)
4376 seq_puts(m, "1");
4377 else
4378 seq_puts(m, "0");
4379 } else
4380 seq_puts(m, "0");
4381 }
4382
4383 return 0;
4384}
4385
4386static int i915_displayport_test_active_open(struct inode *inode,
4387 struct file *file)
4388{
4389 struct drm_device *dev = inode->i_private;
4390
4391 return single_open(file, i915_displayport_test_active_show, dev);
4392}
4393
4394static const struct file_operations i915_displayport_test_active_fops = {
4395 .owner = THIS_MODULE,
4396 .open = i915_displayport_test_active_open,
4397 .read = seq_read,
4398 .llseek = seq_lseek,
4399 .release = single_release,
4400 .write = i915_displayport_test_active_write
4401};
4402
4403static int i915_displayport_test_data_show(struct seq_file *m, void *data)
4404{
4405 struct drm_device *dev = m->private;
4406 struct drm_connector *connector;
4407 struct list_head *connector_list = &dev->mode_config.connector_list;
4408 struct intel_dp *intel_dp;
4409
eb3394fa
TP		 4410 list_for_each_entry(connector, connector_list, head) {
4411
4412 if (connector->connector_type !=
4413 DRM_MODE_CONNECTOR_DisplayPort)
4414 continue;
4415
4416 if (connector->status == connector_status_connected &&
4417 connector->encoder != NULL) {
4418 intel_dp = enc_to_intel_dp(connector->encoder);
4419 seq_printf(m, "%lx", intel_dp->compliance_test_data);
4420 } else
4421 seq_puts(m, "0");
4422 }
4423
4424 return 0;
4425}
4426static int i915_displayport_test_data_open(struct inode *inode,
4427 struct file *file)
4428{
4429 struct drm_device *dev = inode->i_private;
4430
4431 return single_open(file, i915_displayport_test_data_show, dev);
4432}
4433
4434static const struct file_operations i915_displayport_test_data_fops = {
4435 .owner = THIS_MODULE,
4436 .open = i915_displayport_test_data_open,
4437 .read = seq_read,
4438 .llseek = seq_lseek,
4439 .release = single_release
4440};
4441
4442static int i915_displayport_test_type_show(struct seq_file *m, void *data)
4443{
4444 struct drm_device *dev = m->private;
4445 struct drm_connector *connector;
4446 struct list_head *connector_list = &dev->mode_config.connector_list;
4447 struct intel_dp *intel_dp;
4448
eb3394fa
TP		 4449 list_for_each_entry(connector, connector_list, head) {
4450
4451 if (connector->connector_type !=
4452 DRM_MODE_CONNECTOR_DisplayPort)
4453 continue;
4454
4455 if (connector->status == connector_status_connected &&
4456 connector->encoder != NULL) {
4457 intel_dp = enc_to_intel_dp(connector->encoder);
4458 seq_printf(m, "%02lx", intel_dp->compliance_test_type);
4459 } else
4460 seq_puts(m, "0");
4461 }
4462
4463 return 0;
4464}
4465
4466static int i915_displayport_test_type_open(struct inode *inode,
4467 struct file *file)
4468{
4469 struct drm_device *dev = inode->i_private;
4470
4471 return single_open(file, i915_displayport_test_type_show, dev);
4472}
4473
4474static const struct file_operations i915_displayport_test_type_fops = {
4475 .owner = THIS_MODULE,
4476 .open = i915_displayport_test_type_open,
4477 .read = seq_read,
4478 .llseek = seq_lseek,
4479 .release = single_release
4480};
4481
97e94b22 4482static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
369a1342
VS		 4483{
4484 struct drm_device *dev = m->private;
369a1342 4485 int level;
de38b95c
VS		 4486 int num_levels;
4487
4488 if (IS_CHERRYVIEW(dev))
4489 num_levels = 3;
4490 else if (IS_VALLEYVIEW(dev))
4491 num_levels = 1;
4492 else
4493 num_levels = ilk_wm_max_level(dev) + 1;
369a1342
VS		 4494
4495 drm_modeset_lock_all(dev);
4496
4497 for (level = 0; level < num_levels; level++) {
4498 unsigned int latency = wm[level];
4499
97e94b22
DL		 4500 /*
4501 * - WM1+ latency values in 0.5us units
de38b95c 4502 * - latencies are in us on gen9/vlv/chv
97e94b22 4503 */
666a4537
WB		 4504 if (INTEL_INFO(dev)->gen >= 9 || IS_VALLEYVIEW(dev) ||
4505 IS_CHERRYVIEW(dev))
97e94b22
DL		 4506 latency *= 10;
4507 else if (level > 0)
369a1342
VS		 4508 latency *= 5;
4509
4510 seq_printf(m, "WM%d %u (%u.%u usec)\n",
97e94b22 4511 level, wm[level], latency / 10, latency % 10);
369a1342
VS		 4512 }
4513
4514 drm_modeset_unlock_all(dev);
4515}
4516
4517static int pri_wm_latency_show(struct seq_file *m, void *data)
4518{
4519 struct drm_device *dev = m->private;
97e94b22
DL		 4520 struct drm_i915_private *dev_priv = dev->dev_private;
4521 const uint16_t *latencies;
4522
4523 if (INTEL_INFO(dev)->gen >= 9)
4524 latencies = dev_priv->wm.skl_latency;
4525 else
4526 latencies = to_i915(dev)->wm.pri_latency;
369a1342 4527
97e94b22 4528 wm_latency_show(m, latencies);
369a1342
VS		 4529
4530 return 0;
4531}
4532
4533static int spr_wm_latency_show(struct seq_file *m, void *data)
4534{
4535 struct drm_device *dev = m->private;
97e94b22
DL		 4536 struct drm_i915_private *dev_priv = dev->dev_private;
4537 const uint16_t *latencies;
4538
4539 if (INTEL_INFO(dev)->gen >= 9)
4540 latencies = dev_priv->wm.skl_latency;
4541 else
4542 latencies = to_i915(dev)->wm.spr_latency;
369a1342 4543
97e94b22 4544 wm_latency_show(m, latencies);
369a1342
VS		 4545
4546 return 0;
4547}
4548
4549static int cur_wm_latency_show(struct seq_file *m, void *data)
4550{
4551 struct drm_device *dev = m->private;
97e94b22
DL		 4552 struct drm_i915_private *dev_priv = dev->dev_private;
4553 const uint16_t *latencies;
4554
4555 if (INTEL_INFO(dev)->gen >= 9)
4556 latencies = dev_priv->wm.skl_latency;
4557 else
4558 latencies = to_i915(dev)->wm.cur_latency;
369a1342 4559
97e94b22 4560 wm_latency_show(m, latencies);
369a1342
VS		 4561
4562 return 0;
4563}
4564
4565static int pri_wm_latency_open(struct inode *inode, struct file *file)
4566{
4567 struct drm_device *dev = inode->i_private;
4568
de38b95c 4569 if (INTEL_INFO(dev)->gen < 5)
369a1342
VS		 4570 return -ENODEV;
4571
4572 return single_open(file, pri_wm_latency_show, dev);
4573}
4574
4575static int spr_wm_latency_open(struct inode *inode, struct file *file)
4576{
4577 struct drm_device *dev = inode->i_private;
4578
9ad0257c 4579 if (HAS_GMCH_DISPLAY(dev))
369a1342
VS		 4580 return -ENODEV;
4581
4582 return single_open(file, spr_wm_latency_show, dev);
4583}
4584
4585static int cur_wm_latency_open(struct inode *inode, struct file *file)
4586{
4587 struct drm_device *dev = inode->i_private;
4588
9ad0257c 4589 if (HAS_GMCH_DISPLAY(dev))
369a1342
VS		 4590 return -ENODEV;
4591
4592 return single_open(file, cur_wm_latency_show, dev);
4593}
4594
4595static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
97e94b22 4596 size_t len, loff_t *offp, uint16_t wm[8])
369a1342
VS		 4597{
4598 struct seq_file *m = file->private_data;
4599 struct drm_device *dev = m->private;
97e94b22 4600 uint16_t new[8] = { 0 };
de38b95c 4601 int num_levels;
369a1342
VS		 4602 int level;
4603 int ret;
4604 char tmp[32];
4605
de38b95c
VS		 4606 if (IS_CHERRYVIEW(dev))
4607 num_levels = 3;
4608 else if (IS_VALLEYVIEW(dev))
4609 num_levels = 1;
4610 else
4611 num_levels = ilk_wm_max_level(dev) + 1;
4612
369a1342
VS		 4613 if (len >= sizeof(tmp))
4614 return -EINVAL;
4615
4616 if (copy_from_user(tmp, ubuf, len))
4617 return -EFAULT;
4618
4619 tmp[len] = '\0';
4620
97e94b22
DL		 4621 ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
4622 &new[0], &new[1], &new[2], &new[3],
4623 &new[4], &new[5], &new[6], &new[7]);
369a1342
VS		 4624 if (ret != num_levels)
4625 return -EINVAL;
4626
4627 drm_modeset_lock_all(dev);
4628
4629 for (level = 0; level < num_levels; level++)
4630 wm[level] = new[level];
4631
4632 drm_modeset_unlock_all(dev);
4633
4634 return len;
4635}
4636
4637
4638static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
4639 size_t len, loff_t *offp)
4640{
4641 struct seq_file *m = file->private_data;
4642 struct drm_device *dev = m->private;
97e94b22
DL		 4643 struct drm_i915_private *dev_priv = dev->dev_private;
4644 uint16_t *latencies;
369a1342 4645
97e94b22
DL		 4646 if (INTEL_INFO(dev)->gen >= 9)
4647 latencies = dev_priv->wm.skl_latency;
4648 else
4649 latencies = to_i915(dev)->wm.pri_latency;
4650
4651 return wm_latency_write(file, ubuf, len, offp, latencies);
369a1342
VS		 4652}
4653
4654static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
4655 size_t len, loff_t *offp)
4656{
4657 struct seq_file *m = file->private_data;
4658 struct drm_device *dev = m->private;
97e94b22
DL		 4659 struct drm_i915_private *dev_priv = dev->dev_private;
4660 uint16_t *latencies;
369a1342 4661
97e94b22
DL		 4662 if (INTEL_INFO(dev)->gen >= 9)
4663 latencies = dev_priv->wm.skl_latency;
4664 else
4665 latencies = to_i915(dev)->wm.spr_latency;
4666
4667 return wm_latency_write(file, ubuf, len, offp, latencies);
369a1342
VS		 4668}
4669
4670static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
4671 size_t len, loff_t *offp)
4672{
4673 struct seq_file *m = file->private_data;
4674 struct drm_device *dev = m->private;
97e94b22
DL		 4675 struct drm_i915_private *dev_priv = dev->dev_private;
4676 uint16_t *latencies;
4677
4678 if (INTEL_INFO(dev)->gen >= 9)
4679 latencies = dev_priv->wm.skl_latency;
4680 else
4681 latencies = to_i915(dev)->wm.cur_latency;
369a1342 4682
97e94b22 4683 return wm_latency_write(file, ubuf, len, offp, latencies);
369a1342
VS		 4684}
4685
4686static const struct file_operations i915_pri_wm_latency_fops = {
4687 .owner = THIS_MODULE,
4688 .open = pri_wm_latency_open,
4689 .read = seq_read,
4690 .llseek = seq_lseek,
4691 .release = single_release,
4692 .write = pri_wm_latency_write
4693};
4694
4695static const struct file_operations i915_spr_wm_latency_fops = {
4696 .owner = THIS_MODULE,
4697 .open = spr_wm_latency_open,
4698 .read = seq_read,
4699 .llseek = seq_lseek,
4700 .release = single_release,
4701 .write = spr_wm_latency_write
4702};
4703
4704static const struct file_operations i915_cur_wm_latency_fops = {
4705 .owner = THIS_MODULE,
4706 .open = cur_wm_latency_open,
4707 .read = seq_read,
4708 .llseek = seq_lseek,
4709 .release = single_release,
4710 .write = cur_wm_latency_write
4711};
4712
647416f9
KC		 4713static int
4714i915_wedged_get(void *data, u64 *val)
f3cd474b 4715{
647416f9 4716 struct drm_device *dev = data;
e277a1f8 4717 struct drm_i915_private *dev_priv = dev->dev_private;
f3cd474b 4718
647416f9 4719 *val = atomic_read(&dev_priv->gpu_error.reset_counter);
f3cd474b 4720
647416f9 4721 return 0;
f3cd474b
CW		 4722}
4723
647416f9
KC		 4724static int
4725i915_wedged_set(void *data, u64 val)
f3cd474b 4726{
647416f9 4727 struct drm_device *dev = data;
d46c0517
ID		 4728 struct drm_i915_private *dev_priv = dev->dev_private;
4729
b8d24a06
MK		 4730 /*
4731 * There is no safeguard against this debugfs entry colliding
4732 * with the hangcheck calling same i915_handle_error() in
4733 * parallel, causing an explosion. For now we assume that the
4734 * test harness is responsible enough not to inject gpu hangs
4735 * while it is writing to 'i915_wedged'
4736 */
4737
4738 if (i915_reset_in_progress(&dev_priv->gpu_error))
4739 return -EAGAIN;
4740
d46c0517 4741 intel_runtime_pm_get(dev_priv);
f3cd474b 4742
58174462
MK		 4743 i915_handle_error(dev, val,
4744 "Manually setting wedged to %llu", val);
d46c0517
ID		 4745
4746 intel_runtime_pm_put(dev_priv);
4747
647416f9 4748 return 0;
f3cd474b
CW		 4749}
4750
647416f9
KC		 4751DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
4752 i915_wedged_get, i915_wedged_set,
3a3b4f98 4753 "%llu\n");
f3cd474b 4754
647416f9
KC		 4755static int
4756i915_ring_stop_get(void *data, u64 *val)
e5eb3d63 4757{
647416f9 4758 struct drm_device *dev = data;
e277a1f8 4759 struct drm_i915_private *dev_priv = dev->dev_private;
e5eb3d63 4760
647416f9 4761 *val = dev_priv->gpu_error.stop_rings;
e5eb3d63 4762
647416f9 4763 return 0;
e5eb3d63
DV		 4764}
4765
647416f9
KC		 4766static int
4767i915_ring_stop_set(void *data, u64 val)
e5eb3d63 4768{
647416f9 4769 struct drm_device *dev = data;
e5eb3d63 4770 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 4771 int ret;
e5eb3d63 4772
647416f9 4773 DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val);
e5eb3d63 4774
22bcfc6a
DV		 4775 ret = mutex_lock_interruptible(&dev->struct_mutex);
4776 if (ret)
4777 return ret;
4778
99584db3 4779 dev_priv->gpu_error.stop_rings = val;
e5eb3d63
DV		 4780 mutex_unlock(&dev->struct_mutex);
4781
647416f9 4782 return 0;
e5eb3d63
DV		 4783}
4784
647416f9
KC		 4785DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops,
4786 i915_ring_stop_get, i915_ring_stop_set,
4787 "0x%08llx\n");
d5442303 4788
094f9a54
CW		 4789static int
4790i915_ring_missed_irq_get(void *data, u64 *val)
4791{
4792 struct drm_device *dev = data;
4793 struct drm_i915_private *dev_priv = dev->dev_private;
4794
4795 *val = dev_priv->gpu_error.missed_irq_rings;
4796 return 0;
4797}
4798
4799static int
4800i915_ring_missed_irq_set(void *data, u64 val)
4801{
4802 struct drm_device *dev = data;
4803 struct drm_i915_private *dev_priv = dev->dev_private;
4804 int ret;
4805
4806 /* Lock against concurrent debugfs callers */
4807 ret = mutex_lock_interruptible(&dev->struct_mutex);
4808 if (ret)
4809 return ret;
4810 dev_priv->gpu_error.missed_irq_rings = val;
4811 mutex_unlock(&dev->struct_mutex);
4812
4813 return 0;
4814}
4815
4816DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
4817 i915_ring_missed_irq_get, i915_ring_missed_irq_set,
4818 "0x%08llx\n");
4819
4820static int
4821i915_ring_test_irq_get(void *data, u64 *val)
4822{
4823 struct drm_device *dev = data;
4824 struct drm_i915_private *dev_priv = dev->dev_private;
4825
4826 *val = dev_priv->gpu_error.test_irq_rings;
4827
4828 return 0;
4829}
4830
4831static int
4832i915_ring_test_irq_set(void *data, u64 val)
4833{
4834 struct drm_device *dev = data;
4835 struct drm_i915_private *dev_priv = dev->dev_private;
4836 int ret;
4837
4838 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
4839
4840 /* Lock against concurrent debugfs callers */
4841 ret = mutex_lock_interruptible(&dev->struct_mutex);
4842 if (ret)
4843 return ret;
4844
4845 dev_priv->gpu_error.test_irq_rings = val;
4846 mutex_unlock(&dev->struct_mutex);
4847
4848 return 0;
4849}
4850
4851DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
4852 i915_ring_test_irq_get, i915_ring_test_irq_set,
4853 "0x%08llx\n");
4854
dd624afd
CW		 4855#define DROP_UNBOUND 0x1
4856#define DROP_BOUND 0x2
4857#define DROP_RETIRE 0x4
4858#define DROP_ACTIVE 0x8
4859#define DROP_ALL (DROP_UNBOUND | \
4860 DROP_BOUND | \
4861 DROP_RETIRE | \
4862 DROP_ACTIVE)
647416f9
KC		 4863static int
4864i915_drop_caches_get(void *data, u64 *val)
dd624afd 4865{
647416f9 4866 *val = DROP_ALL;
dd624afd 4867
647416f9 4868 return 0;
dd624afd
CW		 4869}
4870
647416f9
KC		 4871static int
4872i915_drop_caches_set(void *data, u64 val)
dd624afd 4873{
647416f9 4874 struct drm_device *dev = data;
dd624afd 4875 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 4876 int ret;
dd624afd 4877
2f9fe5ff 4878 DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
dd624afd
CW		 4879
4880 /* No need to check and wait for gpu resets, only libdrm auto-restarts
4881 * on ioctls on -EAGAIN. */
4882 ret = mutex_lock_interruptible(&dev->struct_mutex);
4883 if (ret)
4884 return ret;
4885
4886 if (val & DROP_ACTIVE) {
4887 ret = i915_gpu_idle(dev);
4888 if (ret)
4889 goto unlock;
4890 }
4891
4892 if (val & (DROP_RETIRE | DROP_ACTIVE))
4893 i915_gem_retire_requests(dev);
4894
21ab4e74
CW		 4895 if (val & DROP_BOUND)
4896 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND);
4ad72b7f 4897
21ab4e74
CW		 4898 if (val & DROP_UNBOUND)
4899 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND);
dd624afd
CW		 4900
4901unlock:
4902 mutex_unlock(&dev->struct_mutex);
4903
647416f9 4904 return ret;
dd624afd
CW		 4905}
4906
647416f9
KC		 4907DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
4908 i915_drop_caches_get, i915_drop_caches_set,
4909 "0x%08llx\n");
dd624afd 4910
647416f9
KC		 4911static int
4912i915_max_freq_get(void *data, u64 *val)
358733e9 4913{
647416f9 4914 struct drm_device *dev = data;
e277a1f8 4915 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 4916 int ret;
004777cb 4917
daa3afb2 4918 if (INTEL_INFO(dev)->gen < 6)
004777cb
DV		 4919 return -ENODEV;
4920
5c9669ce
TR		 4921 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4922
4fc688ce 4923 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 4924 if (ret)
4925 return ret;
358733e9 4926
7c59a9c1 4927 *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
4fc688ce 4928 mutex_unlock(&dev_priv->rps.hw_lock);
358733e9 4929
647416f9 4930 return 0;
358733e9
JB		 4931}
4932
647416f9
KC		 4933static int
4934i915_max_freq_set(void *data, u64 val)
358733e9 4935{
647416f9 4936 struct drm_device *dev = data;
358733e9 4937 struct drm_i915_private *dev_priv = dev->dev_private;
bc4d91f6 4938 u32 hw_max, hw_min;
647416f9 4939 int ret;
004777cb 4940
daa3afb2 4941 if (INTEL_INFO(dev)->gen < 6)
004777cb 4942 return -ENODEV;
358733e9 4943
5c9669ce
TR		 4944 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4945
647416f9 4946 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
358733e9 4947
4fc688ce 4948 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 4949 if (ret)
4950 return ret;
4951
358733e9
JB		 4952 /*
4953 * Turbo will still be enabled, but won't go above the set value.
4954 */
bc4d91f6 4955 val = intel_freq_opcode(dev_priv, val);
dd0a1aa1 4956
bc4d91f6
AG		 4957 hw_max = dev_priv->rps.max_freq;
4958 hw_min = dev_priv->rps.min_freq;
dd0a1aa1 4959
b39fb297 4960 if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
dd0a1aa1
JM		 4961 mutex_unlock(&dev_priv->rps.hw_lock);
4962 return -EINVAL;
0a073b84
JB		 4963 }
4964
b39fb297 4965 dev_priv->rps.max_freq_softlimit = val;
dd0a1aa1 4966
ffe02b40 4967 intel_set_rps(dev, val);
dd0a1aa1 4968
4fc688ce 4969 mutex_unlock(&dev_priv->rps.hw_lock);
358733e9 4970
647416f9 4971 return 0;
358733e9
JB		 4972}
4973
647416f9
KC		 4974DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
4975 i915_max_freq_get, i915_max_freq_set,
3a3b4f98 4976 "%llu\n");
358733e9 4977
647416f9
KC		 4978static int
4979i915_min_freq_get(void *data, u64 *val)
1523c310 4980{
647416f9 4981 struct drm_device *dev = data;
e277a1f8 4982 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 4983 int ret;
004777cb 4984
daa3afb2 4985 if (INTEL_INFO(dev)->gen < 6)
004777cb
DV		 4986 return -ENODEV;
4987
5c9669ce
TR		 4988 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4989
4fc688ce 4990 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 4991 if (ret)
4992 return ret;
1523c310 4993
7c59a9c1 4994 *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
4fc688ce 4995 mutex_unlock(&dev_priv->rps.hw_lock);
1523c310 4996
647416f9 4997 return 0;
1523c310
JB		 4998}
4999
647416f9
KC		 5000static int
5001i915_min_freq_set(void *data, u64 val)
1523c310 5002{
647416f9 5003 struct drm_device *dev = data;
1523c310 5004 struct drm_i915_private *dev_priv = dev->dev_private;
bc4d91f6 5005 u32 hw_max, hw_min;
647416f9 5006 int ret;
004777cb 5007
daa3afb2 5008 if (INTEL_INFO(dev)->gen < 6)
004777cb 5009 return -ENODEV;
1523c310 5010
5c9669ce
TR		 5011 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
5012
647416f9 5013 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
1523c310 5014
4fc688ce 5015 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 5016 if (ret)
5017 return ret;
5018
1523c310
JB		 5019 /*
5020 * Turbo will still be enabled, but won't go below the set value.
5021 */
bc4d91f6 5022 val = intel_freq_opcode(dev_priv, val);
dd0a1aa1 5023
bc4d91f6
AG		 5024 hw_max = dev_priv->rps.max_freq;
5025 hw_min = dev_priv->rps.min_freq;
dd0a1aa1 5026
b39fb297 5027 if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
dd0a1aa1
JM		 5028 mutex_unlock(&dev_priv->rps.hw_lock);
5029 return -EINVAL;
0a073b84 5030 }
dd0a1aa1 5031
b39fb297 5032 dev_priv->rps.min_freq_softlimit = val;
dd0a1aa1 5033
ffe02b40 5034 intel_set_rps(dev, val);
dd0a1aa1 5035
4fc688ce 5036 mutex_unlock(&dev_priv->rps.hw_lock);
1523c310 5037
647416f9 5038 return 0;
1523c310
JB		 5039}
5040
647416f9
KC		 5041DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
5042 i915_min_freq_get, i915_min_freq_set,
3a3b4f98 5043 "%llu\n");
1523c310 5044
647416f9
KC		 5045static int
5046i915_cache_sharing_get(void *data, u64 *val)
07b7ddd9 5047{
647416f9 5048 struct drm_device *dev = data;
e277a1f8 5049 struct drm_i915_private *dev_priv = dev->dev_private;
07b7ddd9 5050 u32 snpcr;
647416f9 5051 int ret;
07b7ddd9 5052
004777cb
DV		 5053 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
5054 return -ENODEV;
5055
22bcfc6a
DV		 5056 ret = mutex_lock_interruptible(&dev->struct_mutex);
5057 if (ret)
5058 return ret;
c8c8fb33 5059 intel_runtime_pm_get(dev_priv);
22bcfc6a 5060
07b7ddd9 5061 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
c8c8fb33
PZ		 5062
5063 intel_runtime_pm_put(dev_priv);
07b7ddd9
JB		 5064 mutex_unlock(&dev_priv->dev->struct_mutex);
5065
647416f9 5066 *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
07b7ddd9 5067
647416f9 5068 return 0;
07b7ddd9
JB		 5069}
5070
647416f9
KC		 5071static int
5072i915_cache_sharing_set(void *data, u64 val)
07b7ddd9 5073{
647416f9 5074 struct drm_device *dev = data;
07b7ddd9 5075 struct drm_i915_private *dev_priv = dev->dev_private;
07b7ddd9 5076 u32 snpcr;
07b7ddd9 5077
004777cb
DV		 5078 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
5079 return -ENODEV;
5080
647416f9 5081 if (val > 3)
07b7ddd9
JB		 5082 return -EINVAL;
5083
c8c8fb33 5084 intel_runtime_pm_get(dev_priv);
647416f9 5085 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
07b7ddd9
JB		 5086
5087 /* Update the cache sharing policy here as well */
5088 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5089 snpcr &= ~GEN6_MBC_SNPCR_MASK;
5090 snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
5091 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
5092
c8c8fb33 5093 intel_runtime_pm_put(dev_priv);
647416f9 5094 return 0;
07b7ddd9
JB		 5095}
5096
647416f9
KC		 5097DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
5098 i915_cache_sharing_get, i915_cache_sharing_set,
5099 "%llu\n");
07b7ddd9 5100
5d39525a
JM		 5101struct sseu_dev_status {
5102 unsigned int slice_total;
5103 unsigned int subslice_total;
5104 unsigned int subslice_per_slice;
5105 unsigned int eu_total;
5106 unsigned int eu_per_subslice;
5107};
5108
5109static void cherryview_sseu_device_status(struct drm_device *dev,
5110 struct sseu_dev_status *stat)
5111{
5112 struct drm_i915_private *dev_priv = dev->dev_private;
0a0b457f 5113 int ss_max = 2;
5d39525a
JM		 5114 int ss;
5115 u32 sig1[ss_max], sig2[ss_max];
5116
5117 sig1[0] = I915_READ(CHV_POWER_SS0_SIG1);
5118 sig1[1] = I915_READ(CHV_POWER_SS1_SIG1);
5119 sig2[0] = I915_READ(CHV_POWER_SS0_SIG2);
5120 sig2[1] = I915_READ(CHV_POWER_SS1_SIG2);
5121
5122 for (ss = 0; ss < ss_max; ss++) {
5123 unsigned int eu_cnt;
5124
5125 if (sig1[ss] & CHV_SS_PG_ENABLE)
5126 /* skip disabled subslice */
5127 continue;
5128
5129 stat->slice_total = 1;
5130 stat->subslice_per_slice++;
5131 eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
5132 ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
5133 ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
5134 ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2);
5135 stat->eu_total += eu_cnt;
5136 stat->eu_per_subslice = max(stat->eu_per_subslice, eu_cnt);
5137 }
5138 stat->subslice_total = stat->subslice_per_slice;
5139}
5140
5141static void gen9_sseu_device_status(struct drm_device *dev,
5142 struct sseu_dev_status *stat)
5143{
5144 struct drm_i915_private *dev_priv = dev->dev_private;
1c046bc1 5145 int s_max = 3, ss_max = 4;
5d39525a
JM		 5146 int s, ss;
5147 u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
5148
1c046bc1
JM		 5149 /* BXT has a single slice and at most 3 subslices. */
5150 if (IS_BROXTON(dev)) {
5151 s_max = 1;
5152 ss_max = 3;
5153 }
5154
5155 for (s = 0; s < s_max; s++) {
5156 s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s));
5157 eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s));
5158 eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s));
5159 }
5160
5d39525a
JM		 5161 eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
5162 GEN9_PGCTL_SSA_EU19_ACK |
5163 GEN9_PGCTL_SSA_EU210_ACK |
5164 GEN9_PGCTL_SSA_EU311_ACK;
5165 eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
5166 GEN9_PGCTL_SSB_EU19_ACK |
5167 GEN9_PGCTL_SSB_EU210_ACK |
5168 GEN9_PGCTL_SSB_EU311_ACK;
5169
5170 for (s = 0; s < s_max; s++) {
1c046bc1
JM		 5171 unsigned int ss_cnt = 0;
5172
5d39525a
JM		 5173 if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
5174 /* skip disabled slice */
5175 continue;
5176
5177 stat->slice_total++;
1c046bc1 5178
ef11bdb3 5179 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
1c046bc1
JM		 5180 ss_cnt = INTEL_INFO(dev)->subslice_per_slice;
5181
5d39525a
JM		 5182 for (ss = 0; ss < ss_max; ss++) {
5183 unsigned int eu_cnt;
5184
1c046bc1
JM		 5185 if (IS_BROXTON(dev) &&
5186 !(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
5187 /* skip disabled subslice */
5188 continue;
5189
5190 if (IS_BROXTON(dev))
5191 ss_cnt++;
5192
5d39525a
JM		 5193 eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
5194 eu_mask[ss%2]);
5195 stat->eu_total += eu_cnt;
5196 stat->eu_per_subslice = max(stat->eu_per_subslice,
5197 eu_cnt);
5198 }
1c046bc1
JM		 5199
5200 stat->subslice_total += ss_cnt;
5201 stat->subslice_per_slice = max(stat->subslice_per_slice,
5202 ss_cnt);
5d39525a
JM		 5203 }
5204}
5205
91bedd34
ŁD		 5206static void broadwell_sseu_device_status(struct drm_device *dev,
5207 struct sseu_dev_status *stat)
5208{
5209 struct drm_i915_private *dev_priv = dev->dev_private;
5210 int s;
5211 u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO);
5212
5213 stat->slice_total = hweight32(slice_info & GEN8_LSLICESTAT_MASK);
5214
5215 if (stat->slice_total) {
5216 stat->subslice_per_slice = INTEL_INFO(dev)->subslice_per_slice;
5217 stat->subslice_total = stat->slice_total *
5218 stat->subslice_per_slice;
5219 stat->eu_per_subslice = INTEL_INFO(dev)->eu_per_subslice;
5220 stat->eu_total = stat->eu_per_subslice * stat->subslice_total;
5221
5222 /* subtract fused off EU(s) from enabled slice(s) */
5223 for (s = 0; s < stat->slice_total; s++) {
5224 u8 subslice_7eu = INTEL_INFO(dev)->subslice_7eu[s];
5225
5226 stat->eu_total -= hweight8(subslice_7eu);
5227 }
5228 }
5229}
5230
3873218f
JM		 5231static int i915_sseu_status(struct seq_file *m, void *unused)
5232{
5233 struct drm_info_node *node = (struct drm_info_node *) m->private;
5234 struct drm_device *dev = node->minor->dev;
5d39525a 5235 struct sseu_dev_status stat;
3873218f 5236
91bedd34 5237 if (INTEL_INFO(dev)->gen < 8)
3873218f
JM		 5238 return -ENODEV;
5239
5240 seq_puts(m, "SSEU Device Info\n");
5241 seq_printf(m, " Available Slice Total: %u\n",
5242 INTEL_INFO(dev)->slice_total);
5243 seq_printf(m, " Available Subslice Total: %u\n",
5244 INTEL_INFO(dev)->subslice_total);
5245 seq_printf(m, " Available Subslice Per Slice: %u\n",
5246 INTEL_INFO(dev)->subslice_per_slice);
5247 seq_printf(m, " Available EU Total: %u\n",
5248 INTEL_INFO(dev)->eu_total);
5249 seq_printf(m, " Available EU Per Subslice: %u\n",
5250 INTEL_INFO(dev)->eu_per_subslice);
5251 seq_printf(m, " Has Slice Power Gating: %s\n",
5252 yesno(INTEL_INFO(dev)->has_slice_pg));
5253 seq_printf(m, " Has Subslice Power Gating: %s\n",
5254 yesno(INTEL_INFO(dev)->has_subslice_pg));
5255 seq_printf(m, " Has EU Power Gating: %s\n",
5256 yesno(INTEL_INFO(dev)->has_eu_pg));
5257
7f992aba 5258 seq_puts(m, "SSEU Device Status\n");
5d39525a 5259 memset(&stat, 0, sizeof(stat));
5575f03a 5260 if (IS_CHERRYVIEW(dev)) {
5d39525a 5261 cherryview_sseu_device_status(dev, &stat);
91bedd34
ŁD		 5262 } else if (IS_BROADWELL(dev)) {
5263 broadwell_sseu_device_status(dev, &stat);
1c046bc1 5264 } else if (INTEL_INFO(dev)->gen >= 9) {
5d39525a 5265 gen9_sseu_device_status(dev, &stat);
7f992aba 5266 }
5d39525a
JM		 5267 seq_printf(m, " Enabled Slice Total: %u\n",
5268 stat.slice_total);
5269 seq_printf(m, " Enabled Subslice Total: %u\n",
5270 stat.subslice_total);
5271 seq_printf(m, " Enabled Subslice Per Slice: %u\n",
5272 stat.subslice_per_slice);
5273 seq_printf(m, " Enabled EU Total: %u\n",
5274 stat.eu_total);
5275 seq_printf(m, " Enabled EU Per Subslice: %u\n",
5276 stat.eu_per_subslice);
7f992aba 5277
3873218f
JM		 5278 return 0;
5279}
5280
6d794d42
BW		 5281static int i915_forcewake_open(struct inode *inode, struct file *file)
5282{
5283 struct drm_device *dev = inode->i_private;
5284 struct drm_i915_private *dev_priv = dev->dev_private;
6d794d42 5285
075edca4 5286 if (INTEL_INFO(dev)->gen < 6)
6d794d42
BW		 5287 return 0;
5288
6daccb0b 5289 intel_runtime_pm_get(dev_priv);
59bad947 5290 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6d794d42
BW		 5291
5292 return 0;
5293}
5294
c43b5634 5295static int i915_forcewake_release(struct inode *inode, struct file *file)
6d794d42
BW		 5296{
5297 struct drm_device *dev = inode->i_private;
5298 struct drm_i915_private *dev_priv = dev->dev_private;
5299
075edca4 5300 if (INTEL_INFO(dev)->gen < 6)
6d794d42
BW		 5301 return 0;
5302
59bad947 5303 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6daccb0b 5304 intel_runtime_pm_put(dev_priv);
6d794d42
BW		 5305
5306 return 0;
5307}
5308
5309static const struct file_operations i915_forcewake_fops = {
5310 .owner = THIS_MODULE,
5311 .open = i915_forcewake_open,
5312 .release = i915_forcewake_release,
5313};
5314
5315static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
5316{
5317 struct drm_device *dev = minor->dev;
5318 struct dentry *ent;
5319
5320 ent = debugfs_create_file("i915_forcewake_user",
8eb57294 5321 S_IRUSR,
6d794d42
BW		 5322 root, dev,
5323 &i915_forcewake_fops);
f3c5fe97
WY		 5324 if (!ent)
5325 return -ENOMEM;
6d794d42 5326
8eb57294 5327 return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
6d794d42
BW		 5328}
5329
6a9c308d
DV		 5330static int i915_debugfs_create(struct dentry *root,
5331 struct drm_minor *minor,
5332 const char *name,
5333 const struct file_operations *fops)
07b7ddd9
JB		 5334{
5335 struct drm_device *dev = minor->dev;
5336 struct dentry *ent;
5337
6a9c308d 5338 ent = debugfs_create_file(name,
07b7ddd9
JB		 5339 S_IRUGO | S_IWUSR,
5340 root, dev,
6a9c308d 5341 fops);
f3c5fe97
WY		 5342 if (!ent)
5343 return -ENOMEM;
07b7ddd9 5344
6a9c308d 5345 return drm_add_fake_info_node(minor, ent, fops);
07b7ddd9
JB		 5346}
5347
06c5bf8c 5348static const struct drm_info_list i915_debugfs_list[] = {
311bd68e 5349 {"i915_capabilities", i915_capabilities, 0},
73aa808f 5350 {"i915_gem_objects", i915_gem_object_info, 0},
08c18323 5351 {"i915_gem_gtt", i915_gem_gtt_info, 0},
1b50247a 5352 {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
433e12f7 5353 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
433e12f7 5354 {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
6d2b8885 5355 {"i915_gem_stolen", i915_gem_stolen_list_info },
4e5359cd 5356 {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
2017263e
BG		 5357 {"i915_gem_request", i915_gem_request_info, 0},
5358 {"i915_gem_seqno", i915_gem_seqno_info, 0},
a6172a80 5359 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
2017263e 5360 {"i915_gem_interrupt", i915_interrupt_info, 0},
1ec14ad3
CW		 5361 {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
5362 {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
5363 {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
9010ebfd 5364 {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
493018dc 5365 {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0},
8b417c26 5366 {"i915_guc_info", i915_guc_info, 0},
fdf5d357 5367 {"i915_guc_load_status", i915_guc_load_status_info, 0},
4c7e77fc 5368 {"i915_guc_log_dump", i915_guc_log_dump, 0},
adb4bd12 5369 {"i915_frequency_info", i915_frequency_info, 0},
f654449a 5370 {"i915_hangcheck_info", i915_hangcheck_info, 0},
f97108d1 5371 {"i915_drpc_info", i915_drpc_info, 0},
7648fa99 5372 {"i915_emon_status", i915_emon_status, 0},
23b2f8bb 5373 {"i915_ring_freq_table", i915_ring_freq_table, 0},
9a851789 5374 {"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0},
b5e50c3f 5375 {"i915_fbc_status", i915_fbc_status, 0},
92d44621 5376 {"i915_ips_status", i915_ips_status, 0},
4a9bef37 5377 {"i915_sr_status", i915_sr_status, 0},
44834a67 5378 {"i915_opregion", i915_opregion, 0},
ada8f955 5379 {"i915_vbt", i915_vbt, 0},
37811fcc 5380 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
e76d3630 5381 {"i915_context_status", i915_context_status, 0},
c0ab1ae9 5382 {"i915_dump_lrc", i915_dump_lrc, 0},
4ba70e44 5383 {"i915_execlists", i915_execlists, 0},
f65367b5 5384 {"i915_forcewake_domains", i915_forcewake_domains, 0},
ea16a3cd 5385 {"i915_swizzle_info", i915_swizzle_info, 0},
3cf17fc5 5386 {"i915_ppgtt_info", i915_ppgtt_info, 0},
63573eb7 5387 {"i915_llc", i915_llc, 0},
e91fd8c6 5388 {"i915_edp_psr_status", i915_edp_psr_status, 0},
d2e216d0 5389 {"i915_sink_crc_eDP1", i915_sink_crc, 0},
ec013e7f 5390 {"i915_energy_uJ", i915_energy_uJ, 0},
6455c870 5391 {"i915_runtime_pm_status", i915_runtime_pm_status, 0},
1da51581 5392 {"i915_power_domain_info", i915_power_domain_info, 0},
b7cec66d 5393 {"i915_dmc_info", i915_dmc_info, 0},
53f5e3ca 5394 {"i915_display_info", i915_display_info, 0},
e04934cf 5395 {"i915_semaphore_status", i915_semaphore_status, 0},
728e29d7 5396 {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
11bed958 5397 {"i915_dp_mst_info", i915_dp_mst_info, 0},
1ed1ef9d 5398 {"i915_wa_registers", i915_wa_registers, 0},
c5511e44 5399 {"i915_ddb_info", i915_ddb_info, 0},
3873218f 5400 {"i915_sseu_status", i915_sseu_status, 0},
a54746e3 5401 {"i915_drrs_status", i915_drrs_status, 0},
1854d5ca 5402 {"i915_rps_boost_info", i915_rps_boost_info, 0},
2017263e 5403};
27c202ad 5404#define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
2017263e 5405
06c5bf8c 5406static const struct i915_debugfs_files {
34b9674c
DV		 5407 const char *name;
5408 const struct file_operations *fops;
5409} i915_debugfs_files[] = {
5410 {"i915_wedged", &i915_wedged_fops},
5411 {"i915_max_freq", &i915_max_freq_fops},
5412 {"i915_min_freq", &i915_min_freq_fops},
5413 {"i915_cache_sharing", &i915_cache_sharing_fops},
5414 {"i915_ring_stop", &i915_ring_stop_fops},
094f9a54
CW		 5415 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
5416 {"i915_ring_test_irq", &i915_ring_test_irq_fops},
34b9674c
DV		 5417 {"i915_gem_drop_caches", &i915_drop_caches_fops},
5418 {"i915_error_state", &i915_error_state_fops},
5419 {"i915_next_seqno", &i915_next_seqno_fops},
bd9db02f 5420 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
369a1342
VS		 5421 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
5422 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
5423 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
da46f936 5424 {"i915_fbc_false_color", &i915_fbc_fc_fops},
eb3394fa
TP		 5425 {"i915_dp_test_data", &i915_displayport_test_data_fops},
5426 {"i915_dp_test_type", &i915_displayport_test_type_fops},
5427 {"i915_dp_test_active", &i915_displayport_test_active_fops}
34b9674c
DV		 5428};
5429
07144428
DL		 5430void intel_display_crc_init(struct drm_device *dev)
5431{
5432 struct drm_i915_private *dev_priv = dev->dev_private;
b378360e 5433 enum pipe pipe;
07144428 5434
055e393f 5435 for_each_pipe(dev_priv, pipe) {
b378360e 5436 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
07144428 5437
d538bbdf
DL		 5438 pipe_crc->opened = false;
5439 spin_lock_init(&pipe_crc->lock);
07144428
DL		 5440 init_waitqueue_head(&pipe_crc->wq);
5441 }
5442}
5443
27c202ad 5444int i915_debugfs_init(struct drm_minor *minor)
2017263e 5445{
34b9674c 5446 int ret, i;
f3cd474b 5447
6d794d42 5448 ret = i915_forcewake_create(minor->debugfs_root, minor);
358733e9
JB		 5449 if (ret)
5450 return ret;
6a9c308d 5451
07144428
DL		 5452 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5453 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
5454 if (ret)
5455 return ret;
5456 }
5457
34b9674c
DV		 5458 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5459 ret = i915_debugfs_create(minor->debugfs_root, minor,
5460 i915_debugfs_files[i].name,
5461 i915_debugfs_files[i].fops);
5462 if (ret)
5463 return ret;
5464 }
40633219 5465
27c202ad
BG		 5466 return drm_debugfs_create_files(i915_debugfs_list,
5467 I915_DEBUGFS_ENTRIES,
2017263e
BG		 5468 minor->debugfs_root, minor);
5469}
5470
27c202ad 5471void i915_debugfs_cleanup(struct drm_minor *minor)
2017263e 5472{
34b9674c
DV		 5473 int i;
5474
27c202ad
BG		 5475 drm_debugfs_remove_files(i915_debugfs_list,
5476 I915_DEBUGFS_ENTRIES, minor);
07144428 5477
6d794d42
BW		 5478 drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
5479 1, minor);
07144428 5480
e309a997 5481 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
07144428
DL		 5482 struct drm_info_list *info_list =
5483 (struct drm_info_list *)&i915_pipe_crc_data[i];
5484
5485 drm_debugfs_remove_files(info_list, 1, minor);
5486 }
5487
34b9674c
DV		 5488 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5489 struct drm_info_list *info_list =
5490 (struct drm_info_list *) i915_debugfs_files[i].fops;
5491
5492 drm_debugfs_remove_files(info_list, 1, minor);
5493 }
2017263e 5494}
aa7471d2
JN		 5495
5496struct dpcd_block {
5497 /* DPCD dump start address. */
5498 unsigned int offset;
5499 /* DPCD dump end address, inclusive. If unset, .size will be used. */
5500 unsigned int end;
5501 /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */
5502 size_t size;
5503 /* Only valid for eDP. */
5504 bool edp;
5505};
5506
5507static const struct dpcd_block i915_dpcd_debug[] = {
5508 { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE },
5509 { .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS },
5510 { .offset = DP_DOWNSTREAM_PORT_0, .size = 16 },
5511 { .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET },
5512 { .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 },
5513 { .offset = DP_SET_POWER },
5514 { .offset = DP_EDP_DPCD_REV },
5515 { .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 },
5516 { .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB },
5517 { .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET },
5518};
5519
5520static int i915_dpcd_show(struct seq_file *m, void *data)
5521{
5522 struct drm_connector *connector = m->private;
5523 struct intel_dp *intel_dp =
5524 enc_to_intel_dp(&intel_attached_encoder(connector)->base);
5525 uint8_t buf[16];
5526 ssize_t err;
5527 int i;
5528
5c1a8875
MK		 5529 if (connector->status != connector_status_connected)
5530 return -ENODEV;
5531
aa7471d2
JN		 5532 for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) {
5533 const struct dpcd_block *b = &i915_dpcd_debug[i];
5534 size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1);
5535
5536 if (b->edp &&
5537 connector->connector_type != DRM_MODE_CONNECTOR_eDP)
5538 continue;
5539
5540 /* low tech for now */
5541 if (WARN_ON(size > sizeof(buf)))
5542 continue;
5543
5544 err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size);
5545 if (err <= 0) {
5546 DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n",
5547 size, b->offset, err);
5548 continue;
5549 }
5550
5551 seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf);
b3f9d7d7 5552 }
aa7471d2
JN		 5553
5554 return 0;
5555}
5556
5557static int i915_dpcd_open(struct inode *inode, struct file *file)
5558{
5559 return single_open(file, i915_dpcd_show, inode->i_private);
5560}
5561
5562static const struct file_operations i915_dpcd_fops = {
5563 .owner = THIS_MODULE,
5564 .open = i915_dpcd_open,
5565 .read = seq_read,
5566 .llseek = seq_lseek,
5567 .release = single_release,
5568};
5569
5570/**
5571 * i915_debugfs_connector_add - add i915 specific connector debugfs files
5572 * @connector: pointer to a registered drm_connector
5573 *
5574 * Cleanup will be done by drm_connector_unregister() through a call to
5575 * drm_debugfs_connector_remove().
5576 *
5577 * Returns 0 on success, negative error codes on error.
5578 */
5579int i915_debugfs_connector_add(struct drm_connector *connector)
5580{
5581 struct dentry *root = connector->debugfs_entry;
5582
5583 /* The connector must have been registered beforehands. */
5584 if (!root)
5585 return -ENODEV;
5586
5587 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
5588 connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5589 debugfs_create_file("i915_dpcd", S_IRUGO, root, connector,
5590 &i915_dpcd_fops);
5591
5592 return 0;
5593}
Linux kernel - Deliverables
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