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drm/i915: Add error code into error state
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_debugfs.c
CommitLineData
2017263e
BG		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 *
27 */
28
29#include <linux/seq_file.h>
b2c88f5b 30#include <linux/circ_buf.h>
926321d5 31#include <linux/ctype.h>
f3cd474b 32#include <linux/debugfs.h>
5a0e3ad6 33#include <linux/slab.h>
2d1a8a48 34#include <linux/export.h>
6d2b8885 35#include <linux/list_sort.h>
ec013e7f 36#include <asm/msr-index.h>
760285e7 37#include <drm/drmP.h>
4e5359cd 38#include "intel_drv.h"
e5c65260 39#include "intel_ringbuffer.h"
760285e7 40#include <drm/i915_drm.h>
2017263e
BG		 41#include "i915_drv.h"
42
f13d3f73 43enum {
69dc4987 44 ACTIVE_LIST,
f13d3f73 45 INACTIVE_LIST,
d21d5975 46 PINNED_LIST,
f13d3f73 47};
2017263e 48
70d39fe4
CW		 49static const char *yesno(int v)
50{
51 return v ? "yes" : "no";
52}
53
497666d8
DL		 54/* As the drm_debugfs_init() routines are called before dev->dev_private is
55 * allocated we need to hook into the minor for release. */
56static int
57drm_add_fake_info_node(struct drm_minor *minor,
58 struct dentry *ent,
59 const void *key)
60{
61 struct drm_info_node *node;
62
63 node = kmalloc(sizeof(*node), GFP_KERNEL);
64 if (node == NULL) {
65 debugfs_remove(ent);
66 return -ENOMEM;
67 }
68
69 node->minor = minor;
70 node->dent = ent;
71 node->info_ent = (void *) key;
72
73 mutex_lock(&minor->debugfs_lock);
74 list_add(&node->list, &minor->debugfs_list);
75 mutex_unlock(&minor->debugfs_lock);
76
77 return 0;
78}
79
70d39fe4
CW		 80static int i915_capabilities(struct seq_file *m, void *data)
81{
82 struct drm_info_node *node = (struct drm_info_node *) m->private;
83 struct drm_device *dev = node->minor->dev;
84 const struct intel_device_info *info = INTEL_INFO(dev);
85
86 seq_printf(m, "gen: %d\n", info->gen);
03d00ac5 87 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
79fc46df
DL		 88#define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
89#define SEP_SEMICOLON ;
90 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
91#undef PRINT_FLAG
92#undef SEP_SEMICOLON
70d39fe4
CW		 93
94 return 0;
95}
2017263e 96
05394f39 97static const char *get_pin_flag(struct drm_i915_gem_object *obj)
a6172a80 98{
05394f39 99 if (obj->user_pin_count > 0)
a6172a80 100 return "P";
d7f46fc4 101 else if (i915_gem_obj_is_pinned(obj))
a6172a80
CW		 102 return "p";
103 else
104 return " ";
105}
106
05394f39 107static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
a6172a80 108{
0206e353
AJ		 109 switch (obj->tiling_mode) {
110 default:
111 case I915_TILING_NONE: return " ";
112 case I915_TILING_X: return "X";
113 case I915_TILING_Y: return "Y";
114 }
a6172a80
CW		 115}
116
1d693bcc
BW		 117static inline const char *get_global_flag(struct drm_i915_gem_object *obj)
118{
119 return obj->has_global_gtt_mapping ? "g" : " ";
120}
121
37811fcc
CW		 122static void
123describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
124{
1d693bcc 125 struct i915_vma *vma;
d7f46fc4
BW		 126 int pin_count = 0;
127
fb1ae911 128 seq_printf(m, "%pK: %s%s%s %8zdKiB %02x %02x %u %u %u%s%s%s",
37811fcc
CW		 129 &obj->base,
130 get_pin_flag(obj),
131 get_tiling_flag(obj),
1d693bcc 132 get_global_flag(obj),
a05a5862 133 obj->base.size / 1024,
37811fcc
CW		 134 obj->base.read_domains,
135 obj->base.write_domain,
0201f1ec
CW		 136 obj->last_read_seqno,
137 obj->last_write_seqno,
caea7476 138 obj->last_fenced_seqno,
84734a04 139 i915_cache_level_str(obj->cache_level),
37811fcc
CW		 140 obj->dirty ? " dirty" : "",
141 obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
142 if (obj->base.name)
143 seq_printf(m, " (name: %d)", obj->base.name);
d7f46fc4
BW		 144 list_for_each_entry(vma, &obj->vma_list, vma_link)
145 if (vma->pin_count > 0)
146 pin_count++;
147 seq_printf(m, " (pinned x %d)", pin_count);
cc98b413
CW		 148 if (obj->pin_display)
149 seq_printf(m, " (display)");
37811fcc
CW		 150 if (obj->fence_reg != I915_FENCE_REG_NONE)
151 seq_printf(m, " (fence: %d)", obj->fence_reg);
1d693bcc
BW		 152 list_for_each_entry(vma, &obj->vma_list, vma_link) {
153 if (!i915_is_ggtt(vma->vm))
154 seq_puts(m, " (pp");
155 else
156 seq_puts(m, " (g");
157 seq_printf(m, "gtt offset: %08lx, size: %08lx)",
158 vma->node.start, vma->node.size);
159 }
c1ad11fc
CW		 160 if (obj->stolen)
161 seq_printf(m, " (stolen: %08lx)", obj->stolen->start);
6299f992
CW		 162 if (obj->pin_mappable || obj->fault_mappable) {
163 char s[3], *t = s;
164 if (obj->pin_mappable)
165 *t++ = 'p';
166 if (obj->fault_mappable)
167 *t++ = 'f';
168 *t = '\0';
169 seq_printf(m, " (%s mappable)", s);
170 }
69dc4987
CW		 171 if (obj->ring != NULL)
172 seq_printf(m, " (%s)", obj->ring->name);
37811fcc
CW		 173}
174
3ccfd19d
BW		 175static void describe_ctx(struct seq_file *m, struct i915_hw_context *ctx)
176{
177 seq_putc(m, ctx->is_initialized ? 'I' : 'i');
178 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
179 seq_putc(m, ' ');
180}
181
433e12f7 182static int i915_gem_object_list_info(struct seq_file *m, void *data)
2017263e
BG		 183{
184 struct drm_info_node *node = (struct drm_info_node *) m->private;
433e12f7
BG		 185 uintptr_t list = (uintptr_t) node->info_ent->data;
186 struct list_head *head;
2017263e 187 struct drm_device *dev = node->minor->dev;
5cef07e1
BW		 188 struct drm_i915_private *dev_priv = dev->dev_private;
189 struct i915_address_space *vm = &dev_priv->gtt.base;
ca191b13 190 struct i915_vma *vma;
8f2480fb
CW		 191 size_t total_obj_size, total_gtt_size;
192 int count, ret;
de227ef0
CW		 193
194 ret = mutex_lock_interruptible(&dev->struct_mutex);
195 if (ret)
196 return ret;
2017263e 197
ca191b13 198 /* FIXME: the user of this interface might want more than just GGTT */
433e12f7
BG		 199 switch (list) {
200 case ACTIVE_LIST:
267f0c90 201 seq_puts(m, "Active:\n");
5cef07e1 202 head = &vm->active_list;
433e12f7
BG		 203 break;
204 case INACTIVE_LIST:
267f0c90 205 seq_puts(m, "Inactive:\n");
5cef07e1 206 head = &vm->inactive_list;
433e12f7 207 break;
433e12f7 208 default:
de227ef0
CW		 209 mutex_unlock(&dev->struct_mutex);
210 return -EINVAL;
2017263e 211 }
2017263e 212
8f2480fb 213 total_obj_size = total_gtt_size = count = 0;
ca191b13
BW		 214 list_for_each_entry(vma, head, mm_list) {
215 seq_printf(m, " ");
216 describe_obj(m, vma->obj);
217 seq_printf(m, "\n");
218 total_obj_size += vma->obj->base.size;
219 total_gtt_size += vma->node.size;
8f2480fb 220 count++;
2017263e 221 }
de227ef0 222 mutex_unlock(&dev->struct_mutex);
5e118f41 223
8f2480fb
CW		 224 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
225 count, total_obj_size, total_gtt_size);
2017263e
BG		 226 return 0;
227}
228
6d2b8885
CW		 229static int obj_rank_by_stolen(void *priv,
230 struct list_head *A, struct list_head *B)
231{
232 struct drm_i915_gem_object *a =
b25cb2f8 233 container_of(A, struct drm_i915_gem_object, obj_exec_link);
6d2b8885 234 struct drm_i915_gem_object *b =
b25cb2f8 235 container_of(B, struct drm_i915_gem_object, obj_exec_link);
6d2b8885
CW		 236
237 return a->stolen->start - b->stolen->start;
238}
239
240static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
241{
242 struct drm_info_node *node = (struct drm_info_node *) m->private;
243 struct drm_device *dev = node->minor->dev;
244 struct drm_i915_private *dev_priv = dev->dev_private;
245 struct drm_i915_gem_object *obj;
246 size_t total_obj_size, total_gtt_size;
247 LIST_HEAD(stolen);
248 int count, ret;
249
250 ret = mutex_lock_interruptible(&dev->struct_mutex);
251 if (ret)
252 return ret;
253
254 total_obj_size = total_gtt_size = count = 0;
255 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
256 if (obj->stolen == NULL)
257 continue;
258
b25cb2f8 259 list_add(&obj->obj_exec_link, &stolen);
6d2b8885
CW		 260
261 total_obj_size += obj->base.size;
262 total_gtt_size += i915_gem_obj_ggtt_size(obj);
263 count++;
264 }
265 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
266 if (obj->stolen == NULL)
267 continue;
268
b25cb2f8 269 list_add(&obj->obj_exec_link, &stolen);
6d2b8885
CW		 270
271 total_obj_size += obj->base.size;
272 count++;
273 }
274 list_sort(NULL, &stolen, obj_rank_by_stolen);
275 seq_puts(m, "Stolen:\n");
276 while (!list_empty(&stolen)) {
b25cb2f8 277 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
6d2b8885
CW		 278 seq_puts(m, " ");
279 describe_obj(m, obj);
280 seq_putc(m, '\n');
b25cb2f8 281 list_del_init(&obj->obj_exec_link);
6d2b8885
CW		 282 }
283 mutex_unlock(&dev->struct_mutex);
284
285 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
286 count, total_obj_size, total_gtt_size);
287 return 0;
288}
289
6299f992
CW		 290#define count_objects(list, member) do { \
291 list_for_each_entry(obj, list, member) { \
f343c5f6 292 size += i915_gem_obj_ggtt_size(obj); \
6299f992
CW		 293 ++count; \
294 if (obj->map_and_fenceable) { \
f343c5f6 295 mappable_size += i915_gem_obj_ggtt_size(obj); \
6299f992
CW		 296 ++mappable_count; \
297 } \
298 } \
0206e353 299} while (0)
6299f992 300
2db8e9d6
CW		 301struct file_stats {
302 int count;
303 size_t total, active, inactive, unbound;
304};
305
306static int per_file_stats(int id, void *ptr, void *data)
307{
308 struct drm_i915_gem_object *obj = ptr;
309 struct file_stats *stats = data;
310
311 stats->count++;
312 stats->total += obj->base.size;
313
f343c5f6 314 if (i915_gem_obj_ggtt_bound(obj)) {
2db8e9d6
CW		 315 if (!list_empty(&obj->ring_list))
316 stats->active += obj->base.size;
317 else
318 stats->inactive += obj->base.size;
319 } else {
320 if (!list_empty(&obj->global_list))
321 stats->unbound += obj->base.size;
322 }
323
324 return 0;
325}
326
ca191b13
BW		 327#define count_vmas(list, member) do { \
328 list_for_each_entry(vma, list, member) { \
329 size += i915_gem_obj_ggtt_size(vma->obj); \
330 ++count; \
331 if (vma->obj->map_and_fenceable) { \
332 mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
333 ++mappable_count; \
334 } \
335 } \
336} while (0)
337
338static int i915_gem_object_info(struct seq_file *m, void* data)
73aa808f
CW		 339{
340 struct drm_info_node *node = (struct drm_info_node *) m->private;
341 struct drm_device *dev = node->minor->dev;
342 struct drm_i915_private *dev_priv = dev->dev_private;
b7abb714
CW		 343 u32 count, mappable_count, purgeable_count;
344 size_t size, mappable_size, purgeable_size;
6299f992 345 struct drm_i915_gem_object *obj;
5cef07e1 346 struct i915_address_space *vm = &dev_priv->gtt.base;
2db8e9d6 347 struct drm_file *file;
ca191b13 348 struct i915_vma *vma;
73aa808f
CW		 349 int ret;
350
351 ret = mutex_lock_interruptible(&dev->struct_mutex);
352 if (ret)
353 return ret;
354
6299f992
CW		 355 seq_printf(m, "%u objects, %zu bytes\n",
356 dev_priv->mm.object_count,
357 dev_priv->mm.object_memory);
358
359 size = count = mappable_size = mappable_count = 0;
35c20a60 360 count_objects(&dev_priv->mm.bound_list, global_list);
6299f992
CW		 361 seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n",
362 count, mappable_count, size, mappable_size);
363
364 size = count = mappable_size = mappable_count = 0;
ca191b13 365 count_vmas(&vm->active_list, mm_list);
6299f992
CW		 366 seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n",
367 count, mappable_count, size, mappable_size);
368
6299f992 369 size = count = mappable_size = mappable_count = 0;
ca191b13 370 count_vmas(&vm->inactive_list, mm_list);
6299f992
CW		 371 seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n",
372 count, mappable_count, size, mappable_size);
373
b7abb714 374 size = count = purgeable_size = purgeable_count = 0;
35c20a60 375 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
6c085a72 376 size += obj->base.size, ++count;
b7abb714
CW		 377 if (obj->madv == I915_MADV_DONTNEED)
378 purgeable_size += obj->base.size, ++purgeable_count;
379 }
6c085a72
CW		 380 seq_printf(m, "%u unbound objects, %zu bytes\n", count, size);
381
6299f992 382 size = count = mappable_size = mappable_count = 0;
35c20a60 383 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
6299f992 384 if (obj->fault_mappable) {
f343c5f6 385 size += i915_gem_obj_ggtt_size(obj);
6299f992
CW		 386 ++count;
387 }
388 if (obj->pin_mappable) {
f343c5f6 389 mappable_size += i915_gem_obj_ggtt_size(obj);
6299f992
CW		 390 ++mappable_count;
391 }
b7abb714
CW		 392 if (obj->madv == I915_MADV_DONTNEED) {
393 purgeable_size += obj->base.size;
394 ++purgeable_count;
395 }
6299f992 396 }
b7abb714
CW		 397 seq_printf(m, "%u purgeable objects, %zu bytes\n",
398 purgeable_count, purgeable_size);
6299f992
CW		 399 seq_printf(m, "%u pinned mappable objects, %zu bytes\n",
400 mappable_count, mappable_size);
401 seq_printf(m, "%u fault mappable objects, %zu bytes\n",
402 count, size);
403
93d18799 404 seq_printf(m, "%zu [%lu] gtt total\n",
853ba5d2
BW		 405 dev_priv->gtt.base.total,
406 dev_priv->gtt.mappable_end - dev_priv->gtt.base.start);
73aa808f 407
267f0c90 408 seq_putc(m, '\n');
2db8e9d6
CW		 409 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
410 struct file_stats stats;
3ec2f427 411 struct task_struct *task;
2db8e9d6
CW		 412
413 memset(&stats, 0, sizeof(stats));
414 idr_for_each(&file->object_idr, per_file_stats, &stats);
3ec2f427
TH		 415 /*
416 * Although we have a valid reference on file->pid, that does
417 * not guarantee that the task_struct who called get_pid() is
418 * still alive (e.g. get_pid(current) => fork() => exit()).
419 * Therefore, we need to protect this ->comm access using RCU.
420 */
421 rcu_read_lock();
422 task = pid_task(file->pid, PIDTYPE_PID);
2db8e9d6 423 seq_printf(m, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu unbound)\n",
3ec2f427 424 task ? task->comm : "<unknown>",
2db8e9d6
CW		 425 stats.count,
426 stats.total,
427 stats.active,
428 stats.inactive,
429 stats.unbound);
3ec2f427 430 rcu_read_unlock();
2db8e9d6
CW		 431 }
432
73aa808f
CW		 433 mutex_unlock(&dev->struct_mutex);
434
435 return 0;
436}
437
aee56cff 438static int i915_gem_gtt_info(struct seq_file *m, void *data)
08c18323
CW		 439{
440 struct drm_info_node *node = (struct drm_info_node *) m->private;
441 struct drm_device *dev = node->minor->dev;
1b50247a 442 uintptr_t list = (uintptr_t) node->info_ent->data;
08c18323
CW		 443 struct drm_i915_private *dev_priv = dev->dev_private;
444 struct drm_i915_gem_object *obj;
445 size_t total_obj_size, total_gtt_size;
446 int count, ret;
447
448 ret = mutex_lock_interruptible(&dev->struct_mutex);
449 if (ret)
450 return ret;
451
452 total_obj_size = total_gtt_size = count = 0;
35c20a60 453 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
d7f46fc4 454 if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj))
1b50247a
CW		 455 continue;
456
267f0c90 457 seq_puts(m, " ");
08c18323 458 describe_obj(m, obj);
267f0c90 459 seq_putc(m, '\n');
08c18323 460 total_obj_size += obj->base.size;
f343c5f6 461 total_gtt_size += i915_gem_obj_ggtt_size(obj);
08c18323
CW		 462 count++;
463 }
464
465 mutex_unlock(&dev->struct_mutex);
466
467 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
468 count, total_obj_size, total_gtt_size);
469
470 return 0;
471}
472
4e5359cd
SF		 473static int i915_gem_pageflip_info(struct seq_file *m, void *data)
474{
475 struct drm_info_node *node = (struct drm_info_node *) m->private;
476 struct drm_device *dev = node->minor->dev;
477 unsigned long flags;
478 struct intel_crtc *crtc;
479
480 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
9db4a9c7
JB		 481 const char pipe = pipe_name(crtc->pipe);
482 const char plane = plane_name(crtc->plane);
4e5359cd
SF		 483 struct intel_unpin_work *work;
484
485 spin_lock_irqsave(&dev->event_lock, flags);
486 work = crtc->unpin_work;
487 if (work == NULL) {
9db4a9c7 488 seq_printf(m, "No flip due on pipe %c (plane %c)\n",
4e5359cd
SF		 489 pipe, plane);
490 } else {
e7d841ca 491 if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9db4a9c7 492 seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
4e5359cd
SF		 493 pipe, plane);
494 } else {
9db4a9c7 495 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
4e5359cd
SF		 496 pipe, plane);
497 }
498 if (work->enable_stall_check)
267f0c90 499 seq_puts(m, "Stall check enabled, ");
4e5359cd 500 else
267f0c90 501 seq_puts(m, "Stall check waiting for page flip ioctl, ");
e7d841ca 502 seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
4e5359cd
SF		 503
504 if (work->old_fb_obj) {
05394f39
CW		 505 struct drm_i915_gem_object *obj = work->old_fb_obj;
506 if (obj)
f343c5f6
BW		 507 seq_printf(m, "Old framebuffer gtt_offset 0x%08lx\n",
508 i915_gem_obj_ggtt_offset(obj));
4e5359cd
SF		 509 }
510 if (work->pending_flip_obj) {
05394f39
CW		 511 struct drm_i915_gem_object *obj = work->pending_flip_obj;
512 if (obj)
f343c5f6
BW		 513 seq_printf(m, "New framebuffer gtt_offset 0x%08lx\n",
514 i915_gem_obj_ggtt_offset(obj));
4e5359cd
SF		 515 }
516 }
517 spin_unlock_irqrestore(&dev->event_lock, flags);
518 }
519
520 return 0;
521}
522
2017263e
BG		 523static int i915_gem_request_info(struct seq_file *m, void *data)
524{
525 struct drm_info_node *node = (struct drm_info_node *) m->private;
526 struct drm_device *dev = node->minor->dev;
527 drm_i915_private_t *dev_priv = dev->dev_private;
a2c7f6fd 528 struct intel_ring_buffer *ring;
2017263e 529 struct drm_i915_gem_request *gem_request;
a2c7f6fd 530 int ret, count, i;
de227ef0
CW		 531
532 ret = mutex_lock_interruptible(&dev->struct_mutex);
533 if (ret)
534 return ret;
2017263e 535
c2c347a9 536 count = 0;
a2c7f6fd
CW		 537 for_each_ring(ring, dev_priv, i) {
538 if (list_empty(&ring->request_list))
539 continue;
540
541 seq_printf(m, "%s requests:\n", ring->name);
c2c347a9 542 list_for_each_entry(gem_request,
a2c7f6fd 543 &ring->request_list,
c2c347a9
CW		 544 list) {
545 seq_printf(m, " %d @ %d\n",
546 gem_request->seqno,
547 (int) (jiffies - gem_request->emitted_jiffies));
548 }
549 count++;
2017263e 550 }
de227ef0
CW		 551 mutex_unlock(&dev->struct_mutex);
552
c2c347a9 553 if (count == 0)
267f0c90 554 seq_puts(m, "No requests\n");
c2c347a9 555
2017263e
BG		 556 return 0;
557}
558
b2223497
CW		 559static void i915_ring_seqno_info(struct seq_file *m,
560 struct intel_ring_buffer *ring)
561{
562 if (ring->get_seqno) {
43a7b924 563 seq_printf(m, "Current sequence (%s): %u\n",
b2eadbc8 564 ring->name, ring->get_seqno(ring, false));
b2223497
CW		 565 }
566}
567
2017263e
BG		 568static int i915_gem_seqno_info(struct seq_file *m, void *data)
569{
570 struct drm_info_node *node = (struct drm_info_node *) m->private;
571 struct drm_device *dev = node->minor->dev;
572 drm_i915_private_t *dev_priv = dev->dev_private;
a2c7f6fd 573 struct intel_ring_buffer *ring;
1ec14ad3 574 int ret, i;
de227ef0
CW		 575
576 ret = mutex_lock_interruptible(&dev->struct_mutex);
577 if (ret)
578 return ret;
c8c8fb33 579 intel_runtime_pm_get(dev_priv);
2017263e 580
a2c7f6fd
CW		 581 for_each_ring(ring, dev_priv, i)
582 i915_ring_seqno_info(m, ring);
de227ef0 583
c8c8fb33 584 intel_runtime_pm_put(dev_priv);
de227ef0
CW		 585 mutex_unlock(&dev->struct_mutex);
586
2017263e
BG		 587 return 0;
588}
589
590
591static int i915_interrupt_info(struct seq_file *m, void *data)
592{
593 struct drm_info_node *node = (struct drm_info_node *) m->private;
594 struct drm_device *dev = node->minor->dev;
595 drm_i915_private_t *dev_priv = dev->dev_private;
a2c7f6fd 596 struct intel_ring_buffer *ring;
9db4a9c7 597 int ret, i, pipe;
de227ef0
CW		 598
599 ret = mutex_lock_interruptible(&dev->struct_mutex);
600 if (ret)
601 return ret;
c8c8fb33 602 intel_runtime_pm_get(dev_priv);
2017263e 603
a123f157
BW		 604 if (INTEL_INFO(dev)->gen >= 8) {
605 int i;
606 seq_printf(m, "Master Interrupt Control:\t%08x\n",
607 I915_READ(GEN8_MASTER_IRQ));
608
609 for (i = 0; i < 4; i++) {
610 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
611 i, I915_READ(GEN8_GT_IMR(i)));
612 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
613 i, I915_READ(GEN8_GT_IIR(i)));
614 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
615 i, I915_READ(GEN8_GT_IER(i)));
616 }
617
618 for_each_pipe(i) {
619 seq_printf(m, "Pipe %c IMR:\t%08x\n",
620 pipe_name(i),
621 I915_READ(GEN8_DE_PIPE_IMR(i)));
622 seq_printf(m, "Pipe %c IIR:\t%08x\n",
623 pipe_name(i),
624 I915_READ(GEN8_DE_PIPE_IIR(i)));
625 seq_printf(m, "Pipe %c IER:\t%08x\n",
626 pipe_name(i),
627 I915_READ(GEN8_DE_PIPE_IER(i)));
628 }
629
630 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
631 I915_READ(GEN8_DE_PORT_IMR));
632 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
633 I915_READ(GEN8_DE_PORT_IIR));
634 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
635 I915_READ(GEN8_DE_PORT_IER));
636
637 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
638 I915_READ(GEN8_DE_MISC_IMR));
639 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
640 I915_READ(GEN8_DE_MISC_IIR));
641 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
642 I915_READ(GEN8_DE_MISC_IER));
643
644 seq_printf(m, "PCU interrupt mask:\t%08x\n",
645 I915_READ(GEN8_PCU_IMR));
646 seq_printf(m, "PCU interrupt identity:\t%08x\n",
647 I915_READ(GEN8_PCU_IIR));
648 seq_printf(m, "PCU interrupt enable:\t%08x\n",
649 I915_READ(GEN8_PCU_IER));
650 } else if (IS_VALLEYVIEW(dev)) {
7e231dbe
JB		 651 seq_printf(m, "Display IER:\t%08x\n",
652 I915_READ(VLV_IER));
653 seq_printf(m, "Display IIR:\t%08x\n",
654 I915_READ(VLV_IIR));
655 seq_printf(m, "Display IIR_RW:\t%08x\n",
656 I915_READ(VLV_IIR_RW));
657 seq_printf(m, "Display IMR:\t%08x\n",
658 I915_READ(VLV_IMR));
659 for_each_pipe(pipe)
660 seq_printf(m, "Pipe %c stat:\t%08x\n",
661 pipe_name(pipe),
662 I915_READ(PIPESTAT(pipe)));
663
664 seq_printf(m, "Master IER:\t%08x\n",
665 I915_READ(VLV_MASTER_IER));
666
667 seq_printf(m, "Render IER:\t%08x\n",
668 I915_READ(GTIER));
669 seq_printf(m, "Render IIR:\t%08x\n",
670 I915_READ(GTIIR));
671 seq_printf(m, "Render IMR:\t%08x\n",
672 I915_READ(GTIMR));
673
674 seq_printf(m, "PM IER:\t\t%08x\n",
675 I915_READ(GEN6_PMIER));
676 seq_printf(m, "PM IIR:\t\t%08x\n",
677 I915_READ(GEN6_PMIIR));
678 seq_printf(m, "PM IMR:\t\t%08x\n",
679 I915_READ(GEN6_PMIMR));
680
681 seq_printf(m, "Port hotplug:\t%08x\n",
682 I915_READ(PORT_HOTPLUG_EN));
683 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
684 I915_READ(VLV_DPFLIPSTAT));
685 seq_printf(m, "DPINVGTT:\t%08x\n",
686 I915_READ(DPINVGTT));
687
688 } else if (!HAS_PCH_SPLIT(dev)) {
5f6a1695
ZW		 689 seq_printf(m, "Interrupt enable: %08x\n",
690 I915_READ(IER));
691 seq_printf(m, "Interrupt identity: %08x\n",
692 I915_READ(IIR));
693 seq_printf(m, "Interrupt mask: %08x\n",
694 I915_READ(IMR));
9db4a9c7
JB		 695 for_each_pipe(pipe)
696 seq_printf(m, "Pipe %c stat: %08x\n",
697 pipe_name(pipe),
698 I915_READ(PIPESTAT(pipe)));
5f6a1695
ZW		 699 } else {
700 seq_printf(m, "North Display Interrupt enable: %08x\n",
701 I915_READ(DEIER));
702 seq_printf(m, "North Display Interrupt identity: %08x\n",
703 I915_READ(DEIIR));
704 seq_printf(m, "North Display Interrupt mask: %08x\n",
705 I915_READ(DEIMR));
706 seq_printf(m, "South Display Interrupt enable: %08x\n",
707 I915_READ(SDEIER));
708 seq_printf(m, "South Display Interrupt identity: %08x\n",
709 I915_READ(SDEIIR));
710 seq_printf(m, "South Display Interrupt mask: %08x\n",
711 I915_READ(SDEIMR));
712 seq_printf(m, "Graphics Interrupt enable: %08x\n",
713 I915_READ(GTIER));
714 seq_printf(m, "Graphics Interrupt identity: %08x\n",
715 I915_READ(GTIIR));
716 seq_printf(m, "Graphics Interrupt mask: %08x\n",
717 I915_READ(GTIMR));
718 }
a2c7f6fd 719 for_each_ring(ring, dev_priv, i) {
a123f157 720 if (INTEL_INFO(dev)->gen >= 6) {
a2c7f6fd
CW		 721 seq_printf(m,
722 "Graphics Interrupt mask (%s): %08x\n",
723 ring->name, I915_READ_IMR(ring));
9862e600 724 }
a2c7f6fd 725 i915_ring_seqno_info(m, ring);
9862e600 726 }
c8c8fb33 727 intel_runtime_pm_put(dev_priv);
de227ef0
CW		 728 mutex_unlock(&dev->struct_mutex);
729
2017263e
BG		 730 return 0;
731}
732
a6172a80
CW		 733static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
734{
735 struct drm_info_node *node = (struct drm_info_node *) m->private;
736 struct drm_device *dev = node->minor->dev;
737 drm_i915_private_t *dev_priv = dev->dev_private;
de227ef0
CW		 738 int i, ret;
739
740 ret = mutex_lock_interruptible(&dev->struct_mutex);
741 if (ret)
742 return ret;
a6172a80
CW		 743
744 seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
745 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
746 for (i = 0; i < dev_priv->num_fence_regs; i++) {
05394f39 747 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
a6172a80 748
6c085a72
CW		 749 seq_printf(m, "Fence %d, pin count = %d, object = ",
750 i, dev_priv->fence_regs[i].pin_count);
c2c347a9 751 if (obj == NULL)
267f0c90 752 seq_puts(m, "unused");
c2c347a9 753 else
05394f39 754 describe_obj(m, obj);
267f0c90 755 seq_putc(m, '\n');
a6172a80
CW		 756 }
757
05394f39 758 mutex_unlock(&dev->struct_mutex);
a6172a80
CW		 759 return 0;
760}
761
2017263e
BG		 762static int i915_hws_info(struct seq_file *m, void *data)
763{
764 struct drm_info_node *node = (struct drm_info_node *) m->private;
765 struct drm_device *dev = node->minor->dev;
766 drm_i915_private_t *dev_priv = dev->dev_private;
4066c0ae 767 struct intel_ring_buffer *ring;
1a240d4d 768 const u32 *hws;
4066c0ae
CW		 769 int i;
770
1ec14ad3 771 ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
1a240d4d 772 hws = ring->status_page.page_addr;
2017263e
BG		 773 if (hws == NULL)
774 return 0;
775
776 for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
777 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
778 i * 4,
779 hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
780 }
781 return 0;
782}
783
d5442303
DV		 784static ssize_t
785i915_error_state_write(struct file *filp,
786 const char __user *ubuf,
787 size_t cnt,
788 loff_t *ppos)
789{
edc3d884 790 struct i915_error_state_file_priv *error_priv = filp->private_data;
d5442303 791 struct drm_device *dev = error_priv->dev;
22bcfc6a 792 int ret;
d5442303
DV		 793
794 DRM_DEBUG_DRIVER("Resetting error state\n");
795
22bcfc6a
DV		 796 ret = mutex_lock_interruptible(&dev->struct_mutex);
797 if (ret)
798 return ret;
799
d5442303
DV		 800 i915_destroy_error_state(dev);
801 mutex_unlock(&dev->struct_mutex);
802
803 return cnt;
804}
805
806static int i915_error_state_open(struct inode *inode, struct file *file)
807{
808 struct drm_device *dev = inode->i_private;
d5442303 809 struct i915_error_state_file_priv *error_priv;
d5442303
DV		 810
811 error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
812 if (!error_priv)
813 return -ENOMEM;
814
815 error_priv->dev = dev;
816
95d5bfb3 817 i915_error_state_get(dev, error_priv);
d5442303 818
edc3d884
MK		 819 file->private_data = error_priv;
820
821 return 0;
d5442303
DV		 822}
823
824static int i915_error_state_release(struct inode *inode, struct file *file)
825{
edc3d884 826 struct i915_error_state_file_priv *error_priv = file->private_data;
d5442303 827
95d5bfb3 828 i915_error_state_put(error_priv);
d5442303
DV		 829 kfree(error_priv);
830
edc3d884
MK		 831 return 0;
832}
833
4dc955f7
MK		 834static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
835 size_t count, loff_t *pos)
836{
837 struct i915_error_state_file_priv *error_priv = file->private_data;
838 struct drm_i915_error_state_buf error_str;
839 loff_t tmp_pos = 0;
840 ssize_t ret_count = 0;
841 int ret;
842
843 ret = i915_error_state_buf_init(&error_str, count, *pos);
844 if (ret)
845 return ret;
edc3d884 846
fc16b48b 847 ret = i915_error_state_to_str(&error_str, error_priv);
edc3d884
MK		 848 if (ret)
849 goto out;
850
edc3d884
MK		 851 ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
852 error_str.buf,
853 error_str.bytes);
854
855 if (ret_count < 0)
856 ret = ret_count;
857 else
858 *pos = error_str.start + ret_count;
859out:
4dc955f7 860 i915_error_state_buf_release(&error_str);
edc3d884 861 return ret ?: ret_count;
d5442303
DV		 862}
863
864static const struct file_operations i915_error_state_fops = {
865 .owner = THIS_MODULE,
866 .open = i915_error_state_open,
edc3d884 867 .read = i915_error_state_read,
d5442303
DV		 868 .write = i915_error_state_write,
869 .llseek = default_llseek,
870 .release = i915_error_state_release,
871};
872
647416f9
KC		 873static int
874i915_next_seqno_get(void *data, u64 *val)
40633219 875{
647416f9 876 struct drm_device *dev = data;
40633219 877 drm_i915_private_t *dev_priv = dev->dev_private;
40633219
MK		 878 int ret;
879
880 ret = mutex_lock_interruptible(&dev->struct_mutex);
881 if (ret)
882 return ret;
883
647416f9 884 *val = dev_priv->next_seqno;
40633219
MK		 885 mutex_unlock(&dev->struct_mutex);
886
647416f9 887 return 0;
40633219
MK		 888}
889
647416f9
KC		 890static int
891i915_next_seqno_set(void *data, u64 val)
892{
893 struct drm_device *dev = data;
40633219
MK		 894 int ret;
895
40633219
MK		 896 ret = mutex_lock_interruptible(&dev->struct_mutex);
897 if (ret)
898 return ret;
899
e94fbaa8 900 ret = i915_gem_set_seqno(dev, val);
40633219
MK		 901 mutex_unlock(&dev->struct_mutex);
902
647416f9 903 return ret;
40633219
MK		 904}
905
647416f9
KC		 906DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
907 i915_next_seqno_get, i915_next_seqno_set,
3a3b4f98 908 "0x%llx\n");
40633219 909
f97108d1
JB		 910static int i915_rstdby_delays(struct seq_file *m, void *unused)
911{
912 struct drm_info_node *node = (struct drm_info_node *) m->private;
913 struct drm_device *dev = node->minor->dev;
914 drm_i915_private_t *dev_priv = dev->dev_private;
616fdb5a
BW		 915 u16 crstanddelay;
916 int ret;
917
918 ret = mutex_lock_interruptible(&dev->struct_mutex);
919 if (ret)
920 return ret;
c8c8fb33 921 intel_runtime_pm_get(dev_priv);
616fdb5a
BW		 922
923 crstanddelay = I915_READ16(CRSTANDVID);
924
c8c8fb33 925 intel_runtime_pm_put(dev_priv);
616fdb5a 926 mutex_unlock(&dev->struct_mutex);
f97108d1
JB		 927
928 seq_printf(m, "w/ctx: %d, w/o ctx: %d\n", (crstanddelay >> 8) & 0x3f, (crstanddelay & 0x3f));
929
930 return 0;
931}
932
933static int i915_cur_delayinfo(struct seq_file *m, void *unused)
934{
935 struct drm_info_node *node = (struct drm_info_node *) m->private;
936 struct drm_device *dev = node->minor->dev;
937 drm_i915_private_t *dev_priv = dev->dev_private;
c8c8fb33
PZ		 938 int ret = 0;
939
940 intel_runtime_pm_get(dev_priv);
3b8d8d91 941
5c9669ce
TR		 942 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
943
3b8d8d91
JB		 944 if (IS_GEN5(dev)) {
945 u16 rgvswctl = I915_READ16(MEMSWCTL);
946 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
947
948 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
949 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
950 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
951 MEMSTAT_VID_SHIFT);
952 seq_printf(m, "Current P-state: %d\n",
953 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
0a073b84 954 } else if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) {
3b8d8d91
JB		 955 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
956 u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
957 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
8e8c06cd 958 u32 rpstat, cagf, reqf;
ccab5c82
JB		 959 u32 rpupei, rpcurup, rpprevup;
960 u32 rpdownei, rpcurdown, rpprevdown;
3b8d8d91
JB		 961 int max_freq;
962
963 /* RPSTAT1 is in the GT power well */
d1ebd816
BW		 964 ret = mutex_lock_interruptible(&dev->struct_mutex);
965 if (ret)
c8c8fb33 966 goto out;
d1ebd816 967
c8d9a590 968 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3b8d8d91 969
8e8c06cd
CW		 970 reqf = I915_READ(GEN6_RPNSWREQ);
971 reqf &= ~GEN6_TURBO_DISABLE;
972 if (IS_HASWELL(dev))
973 reqf >>= 24;
974 else
975 reqf >>= 25;
976 reqf *= GT_FREQUENCY_MULTIPLIER;
977
ccab5c82
JB		 978 rpstat = I915_READ(GEN6_RPSTAT1);
979 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
980 rpcurup = I915_READ(GEN6_RP_CUR_UP);
981 rpprevup = I915_READ(GEN6_RP_PREV_UP);
982 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
983 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
984 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
f82855d3
BW		 985 if (IS_HASWELL(dev))
986 cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
987 else
988 cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
989 cagf *= GT_FREQUENCY_MULTIPLIER;
ccab5c82 990
c8d9a590 991 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
d1ebd816
BW		 992 mutex_unlock(&dev->struct_mutex);
993
3b8d8d91 994 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
ccab5c82 995 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
3b8d8d91
JB		 996 seq_printf(m, "Render p-state ratio: %d\n",
997 (gt_perf_status & 0xff00) >> 8);
998 seq_printf(m, "Render p-state VID: %d\n",
999 gt_perf_status & 0xff);
1000 seq_printf(m, "Render p-state limit: %d\n",
1001 rp_state_limits & 0xff);
8e8c06cd 1002 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
f82855d3 1003 seq_printf(m, "CAGF: %dMHz\n", cagf);
ccab5c82
JB		 1004 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
1005 GEN6_CURICONT_MASK);
1006 seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
1007 GEN6_CURBSYTAVG_MASK);
1008 seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
1009 GEN6_CURBSYTAVG_MASK);
1010 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
1011 GEN6_CURIAVG_MASK);
1012 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
1013 GEN6_CURBSYTAVG_MASK);
1014 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
1015 GEN6_CURBSYTAVG_MASK);
3b8d8d91
JB		 1016
1017 max_freq = (rp_state_cap & 0xff0000) >> 16;
1018 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
c8735b0c 1019 max_freq * GT_FREQUENCY_MULTIPLIER);
3b8d8d91
JB		 1020
1021 max_freq = (rp_state_cap & 0xff00) >> 8;
1022 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
c8735b0c 1023 max_freq * GT_FREQUENCY_MULTIPLIER);
3b8d8d91
JB		 1024
1025 max_freq = rp_state_cap & 0xff;
1026 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
c8735b0c 1027 max_freq * GT_FREQUENCY_MULTIPLIER);
31c77388
BW		 1028
1029 seq_printf(m, "Max overclocked frequency: %dMHz\n",
1030 dev_priv->rps.hw_max * GT_FREQUENCY_MULTIPLIER);
0a073b84
JB		 1031 } else if (IS_VALLEYVIEW(dev)) {
1032 u32 freq_sts, val;
1033
259bd5d4 1034 mutex_lock(&dev_priv->rps.hw_lock);
64936258 1035 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
0a073b84
JB		 1036 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1037 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1038
c5bd2bf6 1039 val = valleyview_rps_max_freq(dev_priv);
0a073b84 1040 seq_printf(m, "max GPU freq: %d MHz\n",
2ec3815f 1041 vlv_gpu_freq(dev_priv, val));
0a073b84 1042
c5bd2bf6 1043 val = valleyview_rps_min_freq(dev_priv);
0a073b84 1044 seq_printf(m, "min GPU freq: %d MHz\n",
2ec3815f 1045 vlv_gpu_freq(dev_priv, val));
0a073b84
JB		 1046
1047 seq_printf(m, "current GPU freq: %d MHz\n",
2ec3815f 1048 vlv_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
259bd5d4 1049 mutex_unlock(&dev_priv->rps.hw_lock);
3b8d8d91 1050 } else {
267f0c90 1051 seq_puts(m, "no P-state info available\n");
3b8d8d91 1052 }
f97108d1 1053
c8c8fb33
PZ		 1054out:
1055 intel_runtime_pm_put(dev_priv);
1056 return ret;
f97108d1
JB		 1057}
1058
1059static int i915_delayfreq_table(struct seq_file *m, void *unused)
1060{
1061 struct drm_info_node *node = (struct drm_info_node *) m->private;
1062 struct drm_device *dev = node->minor->dev;
1063 drm_i915_private_t *dev_priv = dev->dev_private;
1064 u32 delayfreq;
616fdb5a
BW		 1065 int ret, i;
1066
1067 ret = mutex_lock_interruptible(&dev->struct_mutex);
1068 if (ret)
1069 return ret;
c8c8fb33 1070 intel_runtime_pm_get(dev_priv);
f97108d1
JB		 1071
1072 for (i = 0; i < 16; i++) {
1073 delayfreq = I915_READ(PXVFREQ_BASE + i * 4);
7648fa99
JB		 1074 seq_printf(m, "P%02dVIDFREQ: 0x%08x (VID: %d)\n", i, delayfreq,
1075 (delayfreq & PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT);
f97108d1
JB		 1076 }
1077
c8c8fb33
PZ		 1078 intel_runtime_pm_put(dev_priv);
1079
616fdb5a
BW		 1080 mutex_unlock(&dev->struct_mutex);
1081
f97108d1
JB		 1082 return 0;
1083}
1084
1085static inline int MAP_TO_MV(int map)
1086{
1087 return 1250 - (map * 25);
1088}
1089
1090static int i915_inttoext_table(struct seq_file *m, void *unused)
1091{
1092 struct drm_info_node *node = (struct drm_info_node *) m->private;
1093 struct drm_device *dev = node->minor->dev;
1094 drm_i915_private_t *dev_priv = dev->dev_private;
1095 u32 inttoext;
616fdb5a
BW		 1096 int ret, i;
1097
1098 ret = mutex_lock_interruptible(&dev->struct_mutex);
1099 if (ret)
1100 return ret;
c8c8fb33 1101 intel_runtime_pm_get(dev_priv);
f97108d1
JB		 1102
1103 for (i = 1; i <= 32; i++) {
1104 inttoext = I915_READ(INTTOEXT_BASE_ILK + i * 4);
1105 seq_printf(m, "INTTOEXT%02d: 0x%08x\n", i, inttoext);
1106 }
1107
c8c8fb33 1108 intel_runtime_pm_put(dev_priv);
616fdb5a
BW		 1109 mutex_unlock(&dev->struct_mutex);
1110
f97108d1
JB		 1111 return 0;
1112}
1113
4d85529d 1114static int ironlake_drpc_info(struct seq_file *m)
f97108d1
JB		 1115{
1116 struct drm_info_node *node = (struct drm_info_node *) m->private;
1117 struct drm_device *dev = node->minor->dev;
1118 drm_i915_private_t *dev_priv = dev->dev_private;
616fdb5a
BW		 1119 u32 rgvmodectl, rstdbyctl;
1120 u16 crstandvid;
1121 int ret;
1122
1123 ret = mutex_lock_interruptible(&dev->struct_mutex);
1124 if (ret)
1125 return ret;
c8c8fb33 1126 intel_runtime_pm_get(dev_priv);
616fdb5a
BW		 1127
1128 rgvmodectl = I915_READ(MEMMODECTL);
1129 rstdbyctl = I915_READ(RSTDBYCTL);
1130 crstandvid = I915_READ16(CRSTANDVID);
1131
c8c8fb33 1132 intel_runtime_pm_put(dev_priv);
616fdb5a 1133 mutex_unlock(&dev->struct_mutex);
f97108d1
JB		 1134
1135 seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
1136 "yes" : "no");
1137 seq_printf(m, "Boost freq: %d\n",
1138 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1139 MEMMODE_BOOST_FREQ_SHIFT);
1140 seq_printf(m, "HW control enabled: %s\n",
1141 rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");
1142 seq_printf(m, "SW control enabled: %s\n",
1143 rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");
1144 seq_printf(m, "Gated voltage change: %s\n",
1145 rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");
1146 seq_printf(m, "Starting frequency: P%d\n",
1147 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
7648fa99 1148 seq_printf(m, "Max P-state: P%d\n",
f97108d1 1149 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
7648fa99
JB		 1150 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1151 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1152 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1153 seq_printf(m, "Render standby enabled: %s\n",
1154 (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes");
267f0c90 1155 seq_puts(m, "Current RS state: ");
88271da3
JB		 1156 switch (rstdbyctl & RSX_STATUS_MASK) {
1157 case RSX_STATUS_ON:
267f0c90 1158 seq_puts(m, "on\n");
88271da3
JB		 1159 break;
1160 case RSX_STATUS_RC1:
267f0c90 1161 seq_puts(m, "RC1\n");
88271da3
JB		 1162 break;
1163 case RSX_STATUS_RC1E:
267f0c90 1164 seq_puts(m, "RC1E\n");
88271da3
JB		 1165 break;
1166 case RSX_STATUS_RS1:
267f0c90 1167 seq_puts(m, "RS1\n");
88271da3
JB		 1168 break;
1169 case RSX_STATUS_RS2:
267f0c90 1170 seq_puts(m, "RS2 (RC6)\n");
88271da3
JB		 1171 break;
1172 case RSX_STATUS_RS3:
267f0c90 1173 seq_puts(m, "RC3 (RC6+)\n");
88271da3
JB		 1174 break;
1175 default:
267f0c90 1176 seq_puts(m, "unknown\n");
88271da3
JB		 1177 break;
1178 }
f97108d1
JB		 1179
1180 return 0;
1181}
1182
669ab5aa
D		 1183static int vlv_drpc_info(struct seq_file *m)
1184{
1185
1186 struct drm_info_node *node = (struct drm_info_node *) m->private;
1187 struct drm_device *dev = node->minor->dev;
1188 struct drm_i915_private *dev_priv = dev->dev_private;
1189 u32 rpmodectl1, rcctl1;
1190 unsigned fw_rendercount = 0, fw_mediacount = 0;
1191
1192 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1193 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1194
1195 seq_printf(m, "Video Turbo Mode: %s\n",
1196 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1197 seq_printf(m, "Turbo enabled: %s\n",
1198 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1199 seq_printf(m, "HW control enabled: %s\n",
1200 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1201 seq_printf(m, "SW control enabled: %s\n",
1202 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1203 GEN6_RP_MEDIA_SW_MODE));
1204 seq_printf(m, "RC6 Enabled: %s\n",
1205 yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1206 GEN6_RC_CTL_EI_MODE(1))));
1207 seq_printf(m, "Render Power Well: %s\n",
1208 (I915_READ(VLV_GTLC_PW_STATUS) &
1209 VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
1210 seq_printf(m, "Media Power Well: %s\n",
1211 (I915_READ(VLV_GTLC_PW_STATUS) &
1212 VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
1213
1214 spin_lock_irq(&dev_priv->uncore.lock);
1215 fw_rendercount = dev_priv->uncore.fw_rendercount;
1216 fw_mediacount = dev_priv->uncore.fw_mediacount;
1217 spin_unlock_irq(&dev_priv->uncore.lock);
1218
1219 seq_printf(m, "Forcewake Render Count = %u\n", fw_rendercount);
1220 seq_printf(m, "Forcewake Media Count = %u\n", fw_mediacount);
1221
1222
1223 return 0;
1224}
1225
1226
4d85529d
BW		 1227static int gen6_drpc_info(struct seq_file *m)
1228{
1229
1230 struct drm_info_node *node = (struct drm_info_node *) m->private;
1231 struct drm_device *dev = node->minor->dev;
1232 struct drm_i915_private *dev_priv = dev->dev_private;
ecd8faea 1233 u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
93b525dc 1234 unsigned forcewake_count;
aee56cff 1235 int count = 0, ret;
4d85529d
BW		 1236
1237 ret = mutex_lock_interruptible(&dev->struct_mutex);
1238 if (ret)
1239 return ret;
c8c8fb33 1240 intel_runtime_pm_get(dev_priv);
4d85529d 1241
907b28c5
CW		 1242 spin_lock_irq(&dev_priv->uncore.lock);
1243 forcewake_count = dev_priv->uncore.forcewake_count;
1244 spin_unlock_irq(&dev_priv->uncore.lock);
93b525dc
DV		 1245
1246 if (forcewake_count) {
267f0c90
DL		 1247 seq_puts(m, "RC information inaccurate because somebody "
1248 "holds a forcewake reference \n");
4d85529d
BW		 1249 } else {
1250 /* NB: we cannot use forcewake, else we read the wrong values */
1251 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1252 udelay(10);
1253 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1254 }
1255
1256 gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS);
ed71f1b4 1257 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
4d85529d
BW		 1258
1259 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1260 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1261 mutex_unlock(&dev->struct_mutex);
44cbd338
BW		 1262 mutex_lock(&dev_priv->rps.hw_lock);
1263 sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1264 mutex_unlock(&dev_priv->rps.hw_lock);
4d85529d 1265
c8c8fb33
PZ		 1266 intel_runtime_pm_put(dev_priv);
1267
4d85529d
BW		 1268 seq_printf(m, "Video Turbo Mode: %s\n",
1269 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1270 seq_printf(m, "HW control enabled: %s\n",
1271 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1272 seq_printf(m, "SW control enabled: %s\n",
1273 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1274 GEN6_RP_MEDIA_SW_MODE));
fff24e21 1275 seq_printf(m, "RC1e Enabled: %s\n",
4d85529d
BW		 1276 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1277 seq_printf(m, "RC6 Enabled: %s\n",
1278 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1279 seq_printf(m, "Deep RC6 Enabled: %s\n",
1280 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1281 seq_printf(m, "Deepest RC6 Enabled: %s\n",
1282 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
267f0c90 1283 seq_puts(m, "Current RC state: ");
4d85529d
BW		 1284 switch (gt_core_status & GEN6_RCn_MASK) {
1285 case GEN6_RC0:
1286 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
267f0c90 1287 seq_puts(m, "Core Power Down\n");
4d85529d 1288 else
267f0c90 1289 seq_puts(m, "on\n");
4d85529d
BW		 1290 break;
1291 case GEN6_RC3:
267f0c90 1292 seq_puts(m, "RC3\n");
4d85529d
BW		 1293 break;
1294 case GEN6_RC6:
267f0c90 1295 seq_puts(m, "RC6\n");
4d85529d
BW		 1296 break;
1297 case GEN6_RC7:
267f0c90 1298 seq_puts(m, "RC7\n");
4d85529d
BW		 1299 break;
1300 default:
267f0c90 1301 seq_puts(m, "Unknown\n");
4d85529d
BW		 1302 break;
1303 }
1304
1305 seq_printf(m, "Core Power Down: %s\n",
1306 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
cce66a28
BW		 1307
1308 /* Not exactly sure what this is */
1309 seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1310 I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1311 seq_printf(m, "RC6 residency since boot: %u\n",
1312 I915_READ(GEN6_GT_GFX_RC6));
1313 seq_printf(m, "RC6+ residency since boot: %u\n",
1314 I915_READ(GEN6_GT_GFX_RC6p));
1315 seq_printf(m, "RC6++ residency since boot: %u\n",
1316 I915_READ(GEN6_GT_GFX_RC6pp));
1317
ecd8faea
BW		 1318 seq_printf(m, "RC6 voltage: %dmV\n",
1319 GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1320 seq_printf(m, "RC6+ voltage: %dmV\n",
1321 GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1322 seq_printf(m, "RC6++ voltage: %dmV\n",
1323 GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
4d85529d
BW		 1324 return 0;
1325}
1326
1327static int i915_drpc_info(struct seq_file *m, void *unused)
1328{
1329 struct drm_info_node *node = (struct drm_info_node *) m->private;
1330 struct drm_device *dev = node->minor->dev;
1331
669ab5aa
D		 1332 if (IS_VALLEYVIEW(dev))
1333 return vlv_drpc_info(m);
1334 else if (IS_GEN6(dev) || IS_GEN7(dev))
4d85529d
BW		 1335 return gen6_drpc_info(m);
1336 else
1337 return ironlake_drpc_info(m);
1338}
1339
b5e50c3f
JB		 1340static int i915_fbc_status(struct seq_file *m, void *unused)
1341{
1342 struct drm_info_node *node = (struct drm_info_node *) m->private;
1343 struct drm_device *dev = node->minor->dev;
b5e50c3f 1344 drm_i915_private_t *dev_priv = dev->dev_private;
b5e50c3f 1345
3a77c4c4 1346 if (!HAS_FBC(dev)) {
267f0c90 1347 seq_puts(m, "FBC unsupported on this chipset\n");
b5e50c3f
JB		 1348 return 0;
1349 }
1350
36623ef8
PZ		 1351 intel_runtime_pm_get(dev_priv);
1352
ee5382ae 1353 if (intel_fbc_enabled(dev)) {
267f0c90 1354 seq_puts(m, "FBC enabled\n");
b5e50c3f 1355 } else {
267f0c90 1356 seq_puts(m, "FBC disabled: ");
5c3fe8b0 1357 switch (dev_priv->fbc.no_fbc_reason) {
29ebf90f
CW		 1358 case FBC_OK:
1359 seq_puts(m, "FBC actived, but currently disabled in hardware");
1360 break;
1361 case FBC_UNSUPPORTED:
1362 seq_puts(m, "unsupported by this chipset");
1363 break;
bed4a673 1364 case FBC_NO_OUTPUT:
267f0c90 1365 seq_puts(m, "no outputs");
bed4a673 1366 break;
b5e50c3f 1367 case FBC_STOLEN_TOO_SMALL:
267f0c90 1368 seq_puts(m, "not enough stolen memory");
b5e50c3f
JB		 1369 break;
1370 case FBC_UNSUPPORTED_MODE:
267f0c90 1371 seq_puts(m, "mode not supported");
b5e50c3f
JB		 1372 break;
1373 case FBC_MODE_TOO_LARGE:
267f0c90 1374 seq_puts(m, "mode too large");
b5e50c3f
JB		 1375 break;
1376 case FBC_BAD_PLANE:
267f0c90 1377 seq_puts(m, "FBC unsupported on plane");
b5e50c3f
JB		 1378 break;
1379 case FBC_NOT_TILED:
267f0c90 1380 seq_puts(m, "scanout buffer not tiled");
b5e50c3f 1381 break;
9c928d16 1382 case FBC_MULTIPLE_PIPES:
267f0c90 1383 seq_puts(m, "multiple pipes are enabled");
9c928d16 1384 break;
c1a9f047 1385 case FBC_MODULE_PARAM:
267f0c90 1386 seq_puts(m, "disabled per module param (default off)");
c1a9f047 1387 break;
8a5729a3 1388 case FBC_CHIP_DEFAULT:
267f0c90 1389 seq_puts(m, "disabled per chip default");
8a5729a3 1390 break;
b5e50c3f 1391 default:
267f0c90 1392 seq_puts(m, "unknown reason");
b5e50c3f 1393 }
267f0c90 1394 seq_putc(m, '\n');
b5e50c3f 1395 }
36623ef8
PZ		 1396
1397 intel_runtime_pm_put(dev_priv);
1398
b5e50c3f
JB		 1399 return 0;
1400}
1401
92d44621
PZ		 1402static int i915_ips_status(struct seq_file *m, void *unused)
1403{
1404 struct drm_info_node *node = (struct drm_info_node *) m->private;
1405 struct drm_device *dev = node->minor->dev;
1406 struct drm_i915_private *dev_priv = dev->dev_private;
1407
f5adf94e 1408 if (!HAS_IPS(dev)) {
92d44621
PZ		 1409 seq_puts(m, "not supported\n");
1410 return 0;
1411 }
1412
36623ef8
PZ		 1413 intel_runtime_pm_get(dev_priv);
1414
e59150dc 1415 if (IS_BROADWELL(dev) || I915_READ(IPS_CTL) & IPS_ENABLE)
92d44621
PZ		 1416 seq_puts(m, "enabled\n");
1417 else
1418 seq_puts(m, "disabled\n");
1419
36623ef8
PZ		 1420 intel_runtime_pm_put(dev_priv);
1421
92d44621
PZ		 1422 return 0;
1423}
1424
4a9bef37
JB		 1425static int i915_sr_status(struct seq_file *m, void *unused)
1426{
1427 struct drm_info_node *node = (struct drm_info_node *) m->private;
1428 struct drm_device *dev = node->minor->dev;
1429 drm_i915_private_t *dev_priv = dev->dev_private;
1430 bool sr_enabled = false;
1431
36623ef8
PZ		 1432 intel_runtime_pm_get(dev_priv);
1433
1398261a 1434 if (HAS_PCH_SPLIT(dev))
5ba2aaaa 1435 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
a6c45cf0 1436 else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))
4a9bef37
JB		 1437 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1438 else if (IS_I915GM(dev))
1439 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1440 else if (IS_PINEVIEW(dev))
1441 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1442
36623ef8
PZ		 1443 intel_runtime_pm_put(dev_priv);
1444
5ba2aaaa
CW		 1445 seq_printf(m, "self-refresh: %s\n",
1446 sr_enabled ? "enabled" : "disabled");
4a9bef37
JB		 1447
1448 return 0;
1449}
1450
7648fa99
JB		 1451static int i915_emon_status(struct seq_file *m, void *unused)
1452{
1453 struct drm_info_node *node = (struct drm_info_node *) m->private;
1454 struct drm_device *dev = node->minor->dev;
1455 drm_i915_private_t *dev_priv = dev->dev_private;
1456 unsigned long temp, chipset, gfx;
de227ef0
CW		 1457 int ret;
1458
582be6b4
CW		 1459 if (!IS_GEN5(dev))
1460 return -ENODEV;
1461
de227ef0
CW		 1462 ret = mutex_lock_interruptible(&dev->struct_mutex);
1463 if (ret)
1464 return ret;
7648fa99
JB		 1465
1466 temp = i915_mch_val(dev_priv);
1467 chipset = i915_chipset_val(dev_priv);
1468 gfx = i915_gfx_val(dev_priv);
de227ef0 1469 mutex_unlock(&dev->struct_mutex);
7648fa99
JB		 1470
1471 seq_printf(m, "GMCH temp: %ld\n", temp);
1472 seq_printf(m, "Chipset power: %ld\n", chipset);
1473 seq_printf(m, "GFX power: %ld\n", gfx);
1474 seq_printf(m, "Total power: %ld\n", chipset + gfx);
1475
1476 return 0;
1477}
1478
23b2f8bb
JB		 1479static int i915_ring_freq_table(struct seq_file *m, void *unused)
1480{
1481 struct drm_info_node *node = (struct drm_info_node *) m->private;
1482 struct drm_device *dev = node->minor->dev;
1483 drm_i915_private_t *dev_priv = dev->dev_private;
5bfa0199 1484 int ret = 0;
23b2f8bb
JB		 1485 int gpu_freq, ia_freq;
1486
1c70c0ce 1487 if (!(IS_GEN6(dev) || IS_GEN7(dev))) {
267f0c90 1488 seq_puts(m, "unsupported on this chipset\n");
23b2f8bb
JB		 1489 return 0;
1490 }
1491
5bfa0199
PZ		 1492 intel_runtime_pm_get(dev_priv);
1493
5c9669ce
TR		 1494 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1495
4fc688ce 1496 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
23b2f8bb 1497 if (ret)
5bfa0199 1498 goto out;
23b2f8bb 1499
267f0c90 1500 seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
23b2f8bb 1501
c6a828d3
DV		 1502 for (gpu_freq = dev_priv->rps.min_delay;
1503 gpu_freq <= dev_priv->rps.max_delay;
23b2f8bb 1504 gpu_freq++) {
42c0526c
BW		 1505 ia_freq = gpu_freq;
1506 sandybridge_pcode_read(dev_priv,
1507 GEN6_PCODE_READ_MIN_FREQ_TABLE,
1508 &ia_freq);
3ebecd07
CW		 1509 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1510 gpu_freq * GT_FREQUENCY_MULTIPLIER,
1511 ((ia_freq >> 0) & 0xff) * 100,
1512 ((ia_freq >> 8) & 0xff) * 100);
23b2f8bb
JB		 1513 }
1514
4fc688ce 1515 mutex_unlock(&dev_priv->rps.hw_lock);
23b2f8bb 1516
5bfa0199
PZ		 1517out:
1518 intel_runtime_pm_put(dev_priv);
1519 return ret;
23b2f8bb
JB		 1520}
1521
7648fa99
JB		 1522static int i915_gfxec(struct seq_file *m, void *unused)
1523{
1524 struct drm_info_node *node = (struct drm_info_node *) m->private;
1525 struct drm_device *dev = node->minor->dev;
1526 drm_i915_private_t *dev_priv = dev->dev_private;
616fdb5a
BW		 1527 int ret;
1528
1529 ret = mutex_lock_interruptible(&dev->struct_mutex);
1530 if (ret)
1531 return ret;
c8c8fb33 1532 intel_runtime_pm_get(dev_priv);
7648fa99
JB		 1533
1534 seq_printf(m, "GFXEC: %ld\n", (unsigned long)I915_READ(0x112f4));
c8c8fb33 1535 intel_runtime_pm_put(dev_priv);
7648fa99 1536
616fdb5a
BW		 1537 mutex_unlock(&dev->struct_mutex);
1538
7648fa99
JB		 1539 return 0;
1540}
1541
44834a67
CW		 1542static int i915_opregion(struct seq_file *m, void *unused)
1543{
1544 struct drm_info_node *node = (struct drm_info_node *) m->private;
1545 struct drm_device *dev = node->minor->dev;
1546 drm_i915_private_t *dev_priv = dev->dev_private;
1547 struct intel_opregion *opregion = &dev_priv->opregion;
0d38f009 1548 void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL);
44834a67
CW		 1549 int ret;
1550
0d38f009
DV		 1551 if (data == NULL)
1552 return -ENOMEM;
1553
44834a67
CW		 1554 ret = mutex_lock_interruptible(&dev->struct_mutex);
1555 if (ret)
0d38f009 1556 goto out;
44834a67 1557
0d38f009
DV		 1558 if (opregion->header) {
1559 memcpy_fromio(data, opregion->header, OPREGION_SIZE);
1560 seq_write(m, data, OPREGION_SIZE);
1561 }
44834a67
CW		 1562
1563 mutex_unlock(&dev->struct_mutex);
1564
0d38f009
DV		 1565out:
1566 kfree(data);
44834a67
CW		 1567 return 0;
1568}
1569
37811fcc
CW		 1570static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1571{
1572 struct drm_info_node *node = (struct drm_info_node *) m->private;
1573 struct drm_device *dev = node->minor->dev;
4520f53a 1574 struct intel_fbdev *ifbdev = NULL;
37811fcc 1575 struct intel_framebuffer *fb;
37811fcc 1576
4520f53a
DV		 1577#ifdef CONFIG_DRM_I915_FBDEV
1578 struct drm_i915_private *dev_priv = dev->dev_private;
1579 int ret = mutex_lock_interruptible(&dev->mode_config.mutex);
37811fcc
CW		 1580 if (ret)
1581 return ret;
1582
1583 ifbdev = dev_priv->fbdev;
1584 fb = to_intel_framebuffer(ifbdev->helper.fb);
1585
623f9783 1586 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
37811fcc
CW		 1587 fb->base.width,
1588 fb->base.height,
1589 fb->base.depth,
623f9783
DV		 1590 fb->base.bits_per_pixel,
1591 atomic_read(&fb->base.refcount.refcount));
05394f39 1592 describe_obj(m, fb->obj);
267f0c90 1593 seq_putc(m, '\n');
4b096ac1 1594 mutex_unlock(&dev->mode_config.mutex);
4520f53a 1595#endif
37811fcc 1596
4b096ac1 1597 mutex_lock(&dev->mode_config.fb_lock);
37811fcc 1598 list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) {
131a56dc 1599 if (ifbdev && &fb->base == ifbdev->helper.fb)
37811fcc
CW		 1600 continue;
1601
623f9783 1602 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
37811fcc
CW		 1603 fb->base.width,
1604 fb->base.height,
1605 fb->base.depth,
623f9783
DV		 1606 fb->base.bits_per_pixel,
1607 atomic_read(&fb->base.refcount.refcount));
05394f39 1608 describe_obj(m, fb->obj);
267f0c90 1609 seq_putc(m, '\n');
37811fcc 1610 }
4b096ac1 1611 mutex_unlock(&dev->mode_config.fb_lock);
37811fcc
CW		 1612
1613 return 0;
1614}
1615
e76d3630
BW		 1616static int i915_context_status(struct seq_file *m, void *unused)
1617{
1618 struct drm_info_node *node = (struct drm_info_node *) m->private;
1619 struct drm_device *dev = node->minor->dev;
1620 drm_i915_private_t *dev_priv = dev->dev_private;
a168c293 1621 struct intel_ring_buffer *ring;
a33afea5 1622 struct i915_hw_context *ctx;
a168c293 1623 int ret, i;
e76d3630
BW		 1624
1625 ret = mutex_lock_interruptible(&dev->mode_config.mutex);
1626 if (ret)
1627 return ret;
1628
3e373948 1629 if (dev_priv->ips.pwrctx) {
267f0c90 1630 seq_puts(m, "power context ");
3e373948 1631 describe_obj(m, dev_priv->ips.pwrctx);
267f0c90 1632 seq_putc(m, '\n');
dc501fbc 1633 }
e76d3630 1634
3e373948 1635 if (dev_priv->ips.renderctx) {
267f0c90 1636 seq_puts(m, "render context ");
3e373948 1637 describe_obj(m, dev_priv->ips.renderctx);
267f0c90 1638 seq_putc(m, '\n');
dc501fbc 1639 }
e76d3630 1640
a33afea5
BW		 1641 list_for_each_entry(ctx, &dev_priv->context_list, link) {
1642 seq_puts(m, "HW context ");
3ccfd19d 1643 describe_ctx(m, ctx);
a33afea5
BW		 1644 for_each_ring(ring, dev_priv, i)
1645 if (ring->default_context == ctx)
1646 seq_printf(m, "(default context %s) ", ring->name);
1647
1648 describe_obj(m, ctx->obj);
1649 seq_putc(m, '\n');
a168c293
BW		 1650 }
1651
e76d3630
BW		 1652 mutex_unlock(&dev->mode_config.mutex);
1653
1654 return 0;
1655}
1656
6d794d42
BW		 1657static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data)
1658{
1659 struct drm_info_node *node = (struct drm_info_node *) m->private;
1660 struct drm_device *dev = node->minor->dev;
1661 struct drm_i915_private *dev_priv = dev->dev_private;
43709ba0 1662 unsigned forcewake_count = 0, fw_rendercount = 0, fw_mediacount = 0;
6d794d42 1663
907b28c5 1664 spin_lock_irq(&dev_priv->uncore.lock);
43709ba0
D		 1665 if (IS_VALLEYVIEW(dev)) {
1666 fw_rendercount = dev_priv->uncore.fw_rendercount;
1667 fw_mediacount = dev_priv->uncore.fw_mediacount;
1668 } else
1669 forcewake_count = dev_priv->uncore.forcewake_count;
907b28c5 1670 spin_unlock_irq(&dev_priv->uncore.lock);
6d794d42 1671
43709ba0
D		 1672 if (IS_VALLEYVIEW(dev)) {
1673 seq_printf(m, "fw_rendercount = %u\n", fw_rendercount);
1674 seq_printf(m, "fw_mediacount = %u\n", fw_mediacount);
1675 } else
1676 seq_printf(m, "forcewake count = %u\n", forcewake_count);
6d794d42
BW		 1677
1678 return 0;
1679}
1680
ea16a3cd
DV		 1681static const char *swizzle_string(unsigned swizzle)
1682{
aee56cff 1683 switch (swizzle) {
ea16a3cd
DV		 1684 case I915_BIT_6_SWIZZLE_NONE:
1685 return "none";
1686 case I915_BIT_6_SWIZZLE_9:
1687 return "bit9";
1688 case I915_BIT_6_SWIZZLE_9_10:
1689 return "bit9/bit10";
1690 case I915_BIT_6_SWIZZLE_9_11:
1691 return "bit9/bit11";
1692 case I915_BIT_6_SWIZZLE_9_10_11:
1693 return "bit9/bit10/bit11";
1694 case I915_BIT_6_SWIZZLE_9_17:
1695 return "bit9/bit17";
1696 case I915_BIT_6_SWIZZLE_9_10_17:
1697 return "bit9/bit10/bit17";
1698 case I915_BIT_6_SWIZZLE_UNKNOWN:
8a168ca7 1699 return "unknown";
ea16a3cd
DV		 1700 }
1701
1702 return "bug";
1703}
1704
1705static int i915_swizzle_info(struct seq_file *m, void *data)
1706{
1707 struct drm_info_node *node = (struct drm_info_node *) m->private;
1708 struct drm_device *dev = node->minor->dev;
1709 struct drm_i915_private *dev_priv = dev->dev_private;
22bcfc6a
DV		 1710 int ret;
1711
1712 ret = mutex_lock_interruptible(&dev->struct_mutex);
1713 if (ret)
1714 return ret;
c8c8fb33 1715 intel_runtime_pm_get(dev_priv);
ea16a3cd 1716
ea16a3cd
DV		 1717 seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
1718 swizzle_string(dev_priv->mm.bit_6_swizzle_x));
1719 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
1720 swizzle_string(dev_priv->mm.bit_6_swizzle_y));
1721
1722 if (IS_GEN3(dev) || IS_GEN4(dev)) {
1723 seq_printf(m, "DDC = 0x%08x\n",
1724 I915_READ(DCC));
1725 seq_printf(m, "C0DRB3 = 0x%04x\n",
1726 I915_READ16(C0DRB3));
1727 seq_printf(m, "C1DRB3 = 0x%04x\n",
1728 I915_READ16(C1DRB3));
9d3203e1 1729 } else if (INTEL_INFO(dev)->gen >= 6) {
3fa7d235
DV		 1730 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
1731 I915_READ(MAD_DIMM_C0));
1732 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
1733 I915_READ(MAD_DIMM_C1));
1734 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
1735 I915_READ(MAD_DIMM_C2));
1736 seq_printf(m, "TILECTL = 0x%08x\n",
1737 I915_READ(TILECTL));
9d3203e1
BW		 1738 if (IS_GEN8(dev))
1739 seq_printf(m, "GAMTARBMODE = 0x%08x\n",
1740 I915_READ(GAMTARBMODE));
1741 else
1742 seq_printf(m, "ARB_MODE = 0x%08x\n",
1743 I915_READ(ARB_MODE));
3fa7d235
DV		 1744 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
1745 I915_READ(DISP_ARB_CTL));
ea16a3cd 1746 }
c8c8fb33 1747 intel_runtime_pm_put(dev_priv);
ea16a3cd
DV		 1748 mutex_unlock(&dev->struct_mutex);
1749
1750 return 0;
1751}
1752
1c60fef5
BW		 1753static int per_file_ctx(int id, void *ptr, void *data)
1754{
1755 struct i915_hw_context *ctx = ptr;
1756 struct seq_file *m = data;
1757 struct i915_hw_ppgtt *ppgtt = ctx_to_ppgtt(ctx);
1758
1759 ppgtt->debug_dump(ppgtt, m);
1760
1761 return 0;
1762}
1763
77df6772 1764static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev)
3cf17fc5 1765{
3cf17fc5
DV		 1766 struct drm_i915_private *dev_priv = dev->dev_private;
1767 struct intel_ring_buffer *ring;
77df6772
BW		 1768 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
1769 int unused, i;
3cf17fc5 1770
77df6772
BW		 1771 if (!ppgtt)
1772 return;
1773
1774 seq_printf(m, "Page directories: %d\n", ppgtt->num_pd_pages);
5abbcca3 1775 seq_printf(m, "Page tables: %d\n", ppgtt->num_pd_entries);
77df6772
BW		 1776 for_each_ring(ring, dev_priv, unused) {
1777 seq_printf(m, "%s\n", ring->name);
1778 for (i = 0; i < 4; i++) {
1779 u32 offset = 0x270 + i * 8;
1780 u64 pdp = I915_READ(ring->mmio_base + offset + 4);
1781 pdp <<= 32;
1782 pdp |= I915_READ(ring->mmio_base + offset);
1783 for (i = 0; i < 4; i++)
1784 seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
1785 }
1786 }
1787}
1788
1789static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev)
1790{
1791 struct drm_i915_private *dev_priv = dev->dev_private;
1792 struct intel_ring_buffer *ring;
1c60fef5 1793 struct drm_file *file;
77df6772 1794 int i;
3cf17fc5 1795
3cf17fc5
DV		 1796 if (INTEL_INFO(dev)->gen == 6)
1797 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
1798
a2c7f6fd 1799 for_each_ring(ring, dev_priv, i) {
3cf17fc5
DV		 1800 seq_printf(m, "%s\n", ring->name);
1801 if (INTEL_INFO(dev)->gen == 7)
1802 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
1803 seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
1804 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
1805 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring)));
1806 }
1807 if (dev_priv->mm.aliasing_ppgtt) {
1808 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
1809
267f0c90 1810 seq_puts(m, "aliasing PPGTT:\n");
3cf17fc5 1811 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset);
1c60fef5 1812
87d60b63 1813 ppgtt->debug_dump(ppgtt, m);
1c60fef5
BW		 1814 } else
1815 return;
1816
1817 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
1818 struct drm_i915_file_private *file_priv = file->driver_priv;
1819 struct i915_hw_ppgtt *pvt_ppgtt;
1820
1821 pvt_ppgtt = ctx_to_ppgtt(file_priv->private_default_ctx);
1822 seq_printf(m, "proc: %s\n",
1823 get_pid_task(file->pid, PIDTYPE_PID)->comm);
1824 seq_puts(m, " default context:\n");
1825 idr_for_each(&file_priv->context_idr, per_file_ctx, m);
3cf17fc5
DV		 1826 }
1827 seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
77df6772
BW		 1828}
1829
1830static int i915_ppgtt_info(struct seq_file *m, void *data)
1831{
1832 struct drm_info_node *node = (struct drm_info_node *) m->private;
1833 struct drm_device *dev = node->minor->dev;
c8c8fb33 1834 struct drm_i915_private *dev_priv = dev->dev_private;
77df6772
BW		 1835
1836 int ret = mutex_lock_interruptible(&dev->struct_mutex);
1837 if (ret)
1838 return ret;
c8c8fb33 1839 intel_runtime_pm_get(dev_priv);
77df6772
BW		 1840
1841 if (INTEL_INFO(dev)->gen >= 8)
1842 gen8_ppgtt_info(m, dev);
1843 else if (INTEL_INFO(dev)->gen >= 6)
1844 gen6_ppgtt_info(m, dev);
1845
c8c8fb33 1846 intel_runtime_pm_put(dev_priv);
3cf17fc5
DV		 1847 mutex_unlock(&dev->struct_mutex);
1848
1849 return 0;
1850}
1851
57f350b6
JB		 1852static int i915_dpio_info(struct seq_file *m, void *data)
1853{
1854 struct drm_info_node *node = (struct drm_info_node *) m->private;
1855 struct drm_device *dev = node->minor->dev;
1856 struct drm_i915_private *dev_priv = dev->dev_private;
1857 int ret;
1858
1859
1860 if (!IS_VALLEYVIEW(dev)) {
267f0c90 1861 seq_puts(m, "unsupported\n");
57f350b6
JB		 1862 return 0;
1863 }
1864
09153000 1865 ret = mutex_lock_interruptible(&dev_priv->dpio_lock);
57f350b6
JB		 1866 if (ret)
1867 return ret;
1868
1869 seq_printf(m, "DPIO_CTL: 0x%08x\n", I915_READ(DPIO_CTL));
1870
ab3c759a
CML		 1871 seq_printf(m, "DPIO PLL DW3 CH0 : 0x%08x\n",
1872 vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW3(0)));
1873 seq_printf(m, "DPIO PLL DW3 CH1: 0x%08x\n",
1874 vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW3(1)));
1875
1876 seq_printf(m, "DPIO PLL DW5 CH0: 0x%08x\n",
1877 vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW5(0)));
1878 seq_printf(m, "DPIO PLL DW5 CH1: 0x%08x\n",
1879 vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW5(1)));
1880
1881 seq_printf(m, "DPIO PLL DW7 CH0: 0x%08x\n",
1882 vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW7(0)));
1883 seq_printf(m, "DPIO PLL DW7 CH1: 0x%08x\n",
1884 vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW7(1)));
1885
1886 seq_printf(m, "DPIO PLL DW10 CH0: 0x%08x\n",
1887 vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW10(0)));
1888 seq_printf(m, "DPIO PLL DW10 CH1: 0x%08x\n",
1889 vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW10(1)));
57f350b6
JB		 1890
1891 seq_printf(m, "DPIO_FASTCLK_DISABLE: 0x%08x\n",
ab3c759a 1892 vlv_dpio_read(dev_priv, PIPE_A, VLV_CMN_DW0));
57f350b6 1893
09153000 1894 mutex_unlock(&dev_priv->dpio_lock);
57f350b6
JB		 1895
1896 return 0;
1897}
1898
63573eb7
BW		 1899static int i915_llc(struct seq_file *m, void *data)
1900{
1901 struct drm_info_node *node = (struct drm_info_node *) m->private;
1902 struct drm_device *dev = node->minor->dev;
1903 struct drm_i915_private *dev_priv = dev->dev_private;
1904
1905 /* Size calculation for LLC is a bit of a pain. Ignore for now. */
1906 seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
1907 seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size);
1908
1909 return 0;
1910}
1911
e91fd8c6
RV		 1912static int i915_edp_psr_status(struct seq_file *m, void *data)
1913{
1914 struct drm_info_node *node = m->private;
1915 struct drm_device *dev = node->minor->dev;
1916 struct drm_i915_private *dev_priv = dev->dev_private;
a031d709
RV		 1917 u32 psrperf = 0;
1918 bool enabled = false;
e91fd8c6 1919
c8c8fb33
PZ		 1920 intel_runtime_pm_get(dev_priv);
1921
a031d709
RV		 1922 seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
1923 seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
e91fd8c6 1924
a031d709
RV		 1925 enabled = HAS_PSR(dev) &&
1926 I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
1927 seq_printf(m, "Enabled: %s\n", yesno(enabled));
e91fd8c6 1928
a031d709
RV		 1929 if (HAS_PSR(dev))
1930 psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) &
1931 EDP_PSR_PERF_CNT_MASK;
1932 seq_printf(m, "Performance_Counter: %u\n", psrperf);
e91fd8c6 1933
c8c8fb33 1934 intel_runtime_pm_put(dev_priv);
e91fd8c6
RV		 1935 return 0;
1936}
1937
d2e216d0
RV		 1938static int i915_sink_crc(struct seq_file *m, void *data)
1939{
1940 struct drm_info_node *node = m->private;
1941 struct drm_device *dev = node->minor->dev;
1942 struct intel_encoder *encoder;
1943 struct intel_connector *connector;
1944 struct intel_dp *intel_dp = NULL;
1945 int ret;
1946 u8 crc[6];
1947
1948 drm_modeset_lock_all(dev);
1949 list_for_each_entry(connector, &dev->mode_config.connector_list,
1950 base.head) {
1951
1952 if (connector->base.dpms != DRM_MODE_DPMS_ON)
1953 continue;
1954
b6ae3c7c
PZ		 1955 if (!connector->base.encoder)
1956 continue;
1957
d2e216d0
RV		 1958 encoder = to_intel_encoder(connector->base.encoder);
1959 if (encoder->type != INTEL_OUTPUT_EDP)
1960 continue;
1961
1962 intel_dp = enc_to_intel_dp(&encoder->base);
1963
1964 ret = intel_dp_sink_crc(intel_dp, crc);
1965 if (ret)
1966 goto out;
1967
1968 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
1969 crc[0], crc[1], crc[2],
1970 crc[3], crc[4], crc[5]);
1971 goto out;
1972 }
1973 ret = -ENODEV;
1974out:
1975 drm_modeset_unlock_all(dev);
1976 return ret;
1977}
1978
ec013e7f
JB		 1979static int i915_energy_uJ(struct seq_file *m, void *data)
1980{
1981 struct drm_info_node *node = m->private;
1982 struct drm_device *dev = node->minor->dev;
1983 struct drm_i915_private *dev_priv = dev->dev_private;
1984 u64 power;
1985 u32 units;
1986
1987 if (INTEL_INFO(dev)->gen < 6)
1988 return -ENODEV;
1989
36623ef8
PZ		 1990 intel_runtime_pm_get(dev_priv);
1991
ec013e7f
JB		 1992 rdmsrl(MSR_RAPL_POWER_UNIT, power);
1993 power = (power & 0x1f00) >> 8;
1994 units = 1000000 / (1 << power); /* convert to uJ */
1995 power = I915_READ(MCH_SECP_NRG_STTS);
1996 power *= units;
1997
36623ef8
PZ		 1998 intel_runtime_pm_put(dev_priv);
1999
ec013e7f 2000 seq_printf(m, "%llu", (long long unsigned)power);
371db66a
PZ		 2001
2002 return 0;
2003}
2004
2005static int i915_pc8_status(struct seq_file *m, void *unused)
2006{
2007 struct drm_info_node *node = (struct drm_info_node *) m->private;
2008 struct drm_device *dev = node->minor->dev;
2009 struct drm_i915_private *dev_priv = dev->dev_private;
2010
2011 if (!IS_HASWELL(dev)) {
2012 seq_puts(m, "not supported\n");
2013 return 0;
2014 }
2015
2016 mutex_lock(&dev_priv->pc8.lock);
2017 seq_printf(m, "Requirements met: %s\n",
2018 yesno(dev_priv->pc8.requirements_met));
86c4ec0d 2019 seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy));
371db66a
PZ		 2020 seq_printf(m, "Disable count: %d\n", dev_priv->pc8.disable_count);
2021 seq_printf(m, "IRQs disabled: %s\n",
2022 yesno(dev_priv->pc8.irqs_disabled));
2023 seq_printf(m, "Enabled: %s\n", yesno(dev_priv->pc8.enabled));
2024 mutex_unlock(&dev_priv->pc8.lock);
2025
ec013e7f
JB		 2026 return 0;
2027}
2028
1da51581
ID		 2029static const char *power_domain_str(enum intel_display_power_domain domain)
2030{
2031 switch (domain) {
2032 case POWER_DOMAIN_PIPE_A:
2033 return "PIPE_A";
2034 case POWER_DOMAIN_PIPE_B:
2035 return "PIPE_B";
2036 case POWER_DOMAIN_PIPE_C:
2037 return "PIPE_C";
2038 case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
2039 return "PIPE_A_PANEL_FITTER";
2040 case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
2041 return "PIPE_B_PANEL_FITTER";
2042 case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
2043 return "PIPE_C_PANEL_FITTER";
2044 case POWER_DOMAIN_TRANSCODER_A:
2045 return "TRANSCODER_A";
2046 case POWER_DOMAIN_TRANSCODER_B:
2047 return "TRANSCODER_B";
2048 case POWER_DOMAIN_TRANSCODER_C:
2049 return "TRANSCODER_C";
2050 case POWER_DOMAIN_TRANSCODER_EDP:
2051 return "TRANSCODER_EDP";
2052 case POWER_DOMAIN_VGA:
2053 return "VGA";
2054 case POWER_DOMAIN_AUDIO:
2055 return "AUDIO";
2056 case POWER_DOMAIN_INIT:
2057 return "INIT";
2058 default:
2059 WARN_ON(1);
2060 return "?";
2061 }
2062}
2063
2064static int i915_power_domain_info(struct seq_file *m, void *unused)
2065{
2066 struct drm_info_node *node = (struct drm_info_node *) m->private;
2067 struct drm_device *dev = node->minor->dev;
2068 struct drm_i915_private *dev_priv = dev->dev_private;
2069 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2070 int i;
2071
2072 mutex_lock(&power_domains->lock);
2073
2074 seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2075 for (i = 0; i < power_domains->power_well_count; i++) {
2076 struct i915_power_well *power_well;
2077 enum intel_display_power_domain power_domain;
2078
2079 power_well = &power_domains->power_wells[i];
2080 seq_printf(m, "%-25s %d\n", power_well->name,
2081 power_well->count);
2082
2083 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
2084 power_domain++) {
2085 if (!(BIT(power_domain) & power_well->domains))
2086 continue;
2087
2088 seq_printf(m, " %-23s %d\n",
2089 power_domain_str(power_domain),
2090 power_domains->domain_use_count[power_domain]);
2091 }
2092 }
2093
2094 mutex_unlock(&power_domains->lock);
2095
2096 return 0;
2097}
2098
53f5e3ca
JB		 2099static void intel_seq_print_mode(struct seq_file *m, int tabs,
2100 struct drm_display_mode *mode)
2101{
2102 int i;
2103
2104 for (i = 0; i < tabs; i++)
2105 seq_putc(m, '\t');
2106
2107 seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2108 mode->base.id, mode->name,
2109 mode->vrefresh, mode->clock,
2110 mode->hdisplay, mode->hsync_start,
2111 mode->hsync_end, mode->htotal,
2112 mode->vdisplay, mode->vsync_start,
2113 mode->vsync_end, mode->vtotal,
2114 mode->type, mode->flags);
2115}
2116
2117static void intel_encoder_info(struct seq_file *m,
2118 struct intel_crtc *intel_crtc,
2119 struct intel_encoder *intel_encoder)
2120{
2121 struct drm_info_node *node = (struct drm_info_node *) m->private;
2122 struct drm_device *dev = node->minor->dev;
2123 struct drm_crtc *crtc = &intel_crtc->base;
2124 struct intel_connector *intel_connector;
2125 struct drm_encoder *encoder;
2126
2127 encoder = &intel_encoder->base;
2128 seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
2129 encoder->base.id, drm_get_encoder_name(encoder));
2130 for_each_connector_on_encoder(dev, encoder, intel_connector) {
2131 struct drm_connector *connector = &intel_connector->base;
2132 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2133 connector->base.id,
2134 drm_get_connector_name(connector),
2135 drm_get_connector_status_name(connector->status));
2136 if (connector->status == connector_status_connected) {
2137 struct drm_display_mode *mode = &crtc->mode;
2138 seq_printf(m, ", mode:\n");
2139 intel_seq_print_mode(m, 2, mode);
2140 } else {
2141 seq_putc(m, '\n');
2142 }
2143 }
2144}
2145
2146static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2147{
2148 struct drm_info_node *node = (struct drm_info_node *) m->private;
2149 struct drm_device *dev = node->minor->dev;
2150 struct drm_crtc *crtc = &intel_crtc->base;
2151 struct intel_encoder *intel_encoder;
2152
2153 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2154 crtc->fb->base.id, crtc->x, crtc->y,
2155 crtc->fb->width, crtc->fb->height);
2156 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2157 intel_encoder_info(m, intel_crtc, intel_encoder);
2158}
2159
2160static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2161{
2162 struct drm_display_mode *mode = panel->fixed_mode;
2163
2164 seq_printf(m, "\tfixed mode:\n");
2165 intel_seq_print_mode(m, 2, mode);
2166}
2167
2168static void intel_dp_info(struct seq_file *m,
2169 struct intel_connector *intel_connector)
2170{
2171 struct intel_encoder *intel_encoder = intel_connector->encoder;
2172 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2173
2174 seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2175 seq_printf(m, "\taudio support: %s\n", intel_dp->has_audio ? "yes" :
2176 "no");
2177 if (intel_encoder->type == INTEL_OUTPUT_EDP)
2178 intel_panel_info(m, &intel_connector->panel);
2179}
2180
2181static void intel_hdmi_info(struct seq_file *m,
2182 struct intel_connector *intel_connector)
2183{
2184 struct intel_encoder *intel_encoder = intel_connector->encoder;
2185 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2186
2187 seq_printf(m, "\taudio support: %s\n", intel_hdmi->has_audio ? "yes" :
2188 "no");
2189}
2190
2191static void intel_lvds_info(struct seq_file *m,
2192 struct intel_connector *intel_connector)
2193{
2194 intel_panel_info(m, &intel_connector->panel);
2195}
2196
2197static void intel_connector_info(struct seq_file *m,
2198 struct drm_connector *connector)
2199{
2200 struct intel_connector *intel_connector = to_intel_connector(connector);
2201 struct intel_encoder *intel_encoder = intel_connector->encoder;
f103fc7d 2202 struct drm_display_mode *mode;
53f5e3ca
JB		 2203
2204 seq_printf(m, "connector %d: type %s, status: %s\n",
2205 connector->base.id, drm_get_connector_name(connector),
2206 drm_get_connector_status_name(connector->status));
2207 if (connector->status == connector_status_connected) {
2208 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2209 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2210 connector->display_info.width_mm,
2211 connector->display_info.height_mm);
2212 seq_printf(m, "\tsubpixel order: %s\n",
2213 drm_get_subpixel_order_name(connector->display_info.subpixel_order));
2214 seq_printf(m, "\tCEA rev: %d\n",
2215 connector->display_info.cea_rev);
2216 }
2217 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2218 intel_encoder->type == INTEL_OUTPUT_EDP)
2219 intel_dp_info(m, intel_connector);
2220 else if (intel_encoder->type == INTEL_OUTPUT_HDMI)
2221 intel_hdmi_info(m, intel_connector);
2222 else if (intel_encoder->type == INTEL_OUTPUT_LVDS)
2223 intel_lvds_info(m, intel_connector);
2224
f103fc7d
JB		 2225 seq_printf(m, "\tmodes:\n");
2226 list_for_each_entry(mode, &connector->modes, head)
2227 intel_seq_print_mode(m, 2, mode);
53f5e3ca
JB		 2228}
2229
2230static int i915_display_info(struct seq_file *m, void *unused)
2231{
2232 struct drm_info_node *node = (struct drm_info_node *) m->private;
2233 struct drm_device *dev = node->minor->dev;
2234 struct drm_crtc *crtc;
2235 struct drm_connector *connector;
2236
2237 drm_modeset_lock_all(dev);
2238 seq_printf(m, "CRTC info\n");
2239 seq_printf(m, "---------\n");
2240 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2241 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2242
2243 seq_printf(m, "CRTC %d: pipe: %c, active: %s\n",
2244 crtc->base.id, pipe_name(intel_crtc->pipe),
2245 intel_crtc->active ? "yes" : "no");
2246 if (intel_crtc->active)
2247 intel_crtc_info(m, intel_crtc);
2248 }
2249
2250 seq_printf(m, "\n");
2251 seq_printf(m, "Connector info\n");
2252 seq_printf(m, "--------------\n");
2253 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2254 intel_connector_info(m, connector);
2255 }
2256 drm_modeset_unlock_all(dev);
2257
2258 return 0;
2259}
2260
07144428
DL		 2261struct pipe_crc_info {
2262 const char *name;
2263 struct drm_device *dev;
2264 enum pipe pipe;
2265};
2266
2267static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
2268{
be5c7a90
DL		 2269 struct pipe_crc_info *info = inode->i_private;
2270 struct drm_i915_private *dev_priv = info->dev->dev_private;
2271 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2272
7eb1c496
DV		 2273 if (info->pipe >= INTEL_INFO(info->dev)->num_pipes)
2274 return -ENODEV;
2275
d538bbdf
DL		 2276 spin_lock_irq(&pipe_crc->lock);
2277
2278 if (pipe_crc->opened) {
2279 spin_unlock_irq(&pipe_crc->lock);
be5c7a90
DL		 2280 return -EBUSY; /* already open */
2281 }
2282
d538bbdf 2283 pipe_crc->opened = true;
07144428
DL		 2284 filep->private_data = inode->i_private;
2285
d538bbdf
DL		 2286 spin_unlock_irq(&pipe_crc->lock);
2287
07144428
DL		 2288 return 0;
2289}
2290
2291static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
2292{
be5c7a90
DL		 2293 struct pipe_crc_info *info = inode->i_private;
2294 struct drm_i915_private *dev_priv = info->dev->dev_private;
2295 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2296
d538bbdf
DL		 2297 spin_lock_irq(&pipe_crc->lock);
2298 pipe_crc->opened = false;
2299 spin_unlock_irq(&pipe_crc->lock);
be5c7a90 2300
07144428
DL		 2301 return 0;
2302}
2303
2304/* (6 fields, 8 chars each, space separated (5) + '\n') */
2305#define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
2306/* account for \'0' */
2307#define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1)
2308
2309static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
8bf1e9f1 2310{
d538bbdf
DL		 2311 assert_spin_locked(&pipe_crc->lock);
2312 return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
2313 INTEL_PIPE_CRC_ENTRIES_NR);
07144428
DL		 2314}
2315
2316static ssize_t
2317i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
2318 loff_t *pos)
2319{
2320 struct pipe_crc_info *info = filep->private_data;
2321 struct drm_device *dev = info->dev;
2322 struct drm_i915_private *dev_priv = dev->dev_private;
2323 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2324 char buf[PIPE_CRC_BUFFER_LEN];
2325 int head, tail, n_entries, n;
2326 ssize_t bytes_read;
2327
2328 /*
2329 * Don't allow user space to provide buffers not big enough to hold
2330 * a line of data.
2331 */
2332 if (count < PIPE_CRC_LINE_LEN)
2333 return -EINVAL;
2334
2335 if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
8bf1e9f1 2336 return 0;
07144428
DL		 2337
2338 /* nothing to read */
d538bbdf 2339 spin_lock_irq(&pipe_crc->lock);
07144428 2340 while (pipe_crc_data_count(pipe_crc) == 0) {
d538bbdf
DL		 2341 int ret;
2342
2343 if (filep->f_flags & O_NONBLOCK) {
2344 spin_unlock_irq(&pipe_crc->lock);
07144428 2345 return -EAGAIN;
d538bbdf 2346 }
07144428 2347
d538bbdf
DL		 2348 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
2349 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
2350 if (ret) {
2351 spin_unlock_irq(&pipe_crc->lock);
2352 return ret;
2353 }
8bf1e9f1
SH		 2354 }
2355
07144428 2356 /* We now have one or more entries to read */
d538bbdf
DL		 2357 head = pipe_crc->head;
2358 tail = pipe_crc->tail;
07144428
DL		 2359 n_entries = min((size_t)CIRC_CNT(head, tail, INTEL_PIPE_CRC_ENTRIES_NR),
2360 count / PIPE_CRC_LINE_LEN);
d538bbdf
DL		 2361 spin_unlock_irq(&pipe_crc->lock);
2362
07144428
DL		 2363 bytes_read = 0;
2364 n = 0;
2365 do {
b2c88f5b 2366 struct intel_pipe_crc_entry *entry = &pipe_crc->entries[tail];
07144428 2367 int ret;
8bf1e9f1 2368
07144428
DL		 2369 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
2370 "%8u %8x %8x %8x %8x %8x\n",
2371 entry->frame, entry->crc[0],
2372 entry->crc[1], entry->crc[2],
2373 entry->crc[3], entry->crc[4]);
2374
2375 ret = copy_to_user(user_buf + n * PIPE_CRC_LINE_LEN,
2376 buf, PIPE_CRC_LINE_LEN);
2377 if (ret == PIPE_CRC_LINE_LEN)
2378 return -EFAULT;
b2c88f5b
DL		 2379
2380 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
2381 tail = (tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
07144428
DL		 2382 n++;
2383 } while (--n_entries);
8bf1e9f1 2384
d538bbdf
DL		 2385 spin_lock_irq(&pipe_crc->lock);
2386 pipe_crc->tail = tail;
2387 spin_unlock_irq(&pipe_crc->lock);
2388
07144428
DL		 2389 return bytes_read;
2390}
2391
2392static const struct file_operations i915_pipe_crc_fops = {
2393 .owner = THIS_MODULE,
2394 .open = i915_pipe_crc_open,
2395 .read = i915_pipe_crc_read,
2396 .release = i915_pipe_crc_release,
2397};
2398
2399static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
2400 {
2401 .name = "i915_pipe_A_crc",
2402 .pipe = PIPE_A,
2403 },
2404 {
2405 .name = "i915_pipe_B_crc",
2406 .pipe = PIPE_B,
2407 },
2408 {
2409 .name = "i915_pipe_C_crc",
2410 .pipe = PIPE_C,
2411 },
2412};
2413
2414static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
2415 enum pipe pipe)
2416{
2417 struct drm_device *dev = minor->dev;
2418 struct dentry *ent;
2419 struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
2420
2421 info->dev = dev;
2422 ent = debugfs_create_file(info->name, S_IRUGO, root, info,
2423 &i915_pipe_crc_fops);
f3c5fe97
WY		 2424 if (!ent)
2425 return -ENOMEM;
07144428
DL		 2426
2427 return drm_add_fake_info_node(minor, ent, info);
8bf1e9f1
SH		 2428}
2429
e8dfcf78 2430static const char * const pipe_crc_sources[] = {
926321d5
DV		 2431 "none",
2432 "plane1",
2433 "plane2",
2434 "pf",
5b3a856b 2435 "pipe",
3d099a05
DV		 2436 "TV",
2437 "DP-B",
2438 "DP-C",
2439 "DP-D",
46a19188 2440 "auto",
926321d5
DV		 2441};
2442
2443static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
2444{
2445 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
2446 return pipe_crc_sources[source];
2447}
2448
bd9db02f 2449static int display_crc_ctl_show(struct seq_file *m, void *data)
926321d5
DV		 2450{
2451 struct drm_device *dev = m->private;
2452 struct drm_i915_private *dev_priv = dev->dev_private;
2453 int i;
2454
2455 for (i = 0; i < I915_MAX_PIPES; i++)
2456 seq_printf(m, "%c %s\n", pipe_name(i),
2457 pipe_crc_source_name(dev_priv->pipe_crc[i].source));
2458
2459 return 0;
2460}
2461
bd9db02f 2462static int display_crc_ctl_open(struct inode *inode, struct file *file)
926321d5
DV		 2463{
2464 struct drm_device *dev = inode->i_private;
2465
bd9db02f 2466 return single_open(file, display_crc_ctl_show, dev);
926321d5
DV		 2467}
2468
46a19188 2469static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
52f843f6
DV		 2470 uint32_t *val)
2471{
46a19188
DV		 2472 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
2473 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
2474
2475 switch (*source) {
52f843f6
DV		 2476 case INTEL_PIPE_CRC_SOURCE_PIPE:
2477 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
2478 break;
2479 case INTEL_PIPE_CRC_SOURCE_NONE:
2480 *val = 0;
2481 break;
2482 default:
2483 return -EINVAL;
2484 }
2485
2486 return 0;
2487}
2488
46a19188
DV		 2489static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe,
2490 enum intel_pipe_crc_source *source)
2491{
2492 struct intel_encoder *encoder;
2493 struct intel_crtc *crtc;
26756809 2494 struct intel_digital_port *dig_port;
46a19188
DV		 2495 int ret = 0;
2496
2497 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
2498
2499 mutex_lock(&dev->mode_config.mutex);
2500 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
2501 base.head) {
2502 if (!encoder->base.crtc)
2503 continue;
2504
2505 crtc = to_intel_crtc(encoder->base.crtc);
2506
2507 if (crtc->pipe != pipe)
2508 continue;
2509
2510 switch (encoder->type) {
2511 case INTEL_OUTPUT_TVOUT:
2512 *source = INTEL_PIPE_CRC_SOURCE_TV;
2513 break;
2514 case INTEL_OUTPUT_DISPLAYPORT:
2515 case INTEL_OUTPUT_EDP:
26756809
DV		 2516 dig_port = enc_to_dig_port(&encoder->base);
2517 switch (dig_port->port) {
2518 case PORT_B:
2519 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
2520 break;
2521 case PORT_C:
2522 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
2523 break;
2524 case PORT_D:
2525 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
2526 break;
2527 default:
2528 WARN(1, "nonexisting DP port %c\n",
2529 port_name(dig_port->port));
2530 break;
2531 }
46a19188
DV		 2532 break;
2533 }
2534 }
2535 mutex_unlock(&dev->mode_config.mutex);
2536
2537 return ret;
2538}
2539
2540static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
2541 enum pipe pipe,
2542 enum intel_pipe_crc_source *source,
7ac0129b
DV		 2543 uint32_t *val)
2544{
8d2f24ca
DV		 2545 struct drm_i915_private *dev_priv = dev->dev_private;
2546 bool need_stable_symbols = false;
2547
46a19188
DV		 2548 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
2549 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
2550 if (ret)
2551 return ret;
2552 }
2553
2554 switch (*source) {
7ac0129b
DV		 2555 case INTEL_PIPE_CRC_SOURCE_PIPE:
2556 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
2557 break;
2558 case INTEL_PIPE_CRC_SOURCE_DP_B:
2559 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
8d2f24ca 2560 need_stable_symbols = true;
7ac0129b
DV		 2561 break;
2562 case INTEL_PIPE_CRC_SOURCE_DP_C:
2563 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
8d2f24ca 2564 need_stable_symbols = true;
7ac0129b
DV		 2565 break;
2566 case INTEL_PIPE_CRC_SOURCE_NONE:
2567 *val = 0;
2568 break;
2569 default:
2570 return -EINVAL;
2571 }
2572
8d2f24ca
DV		 2573 /*
2574 * When the pipe CRC tap point is after the transcoders we need
2575 * to tweak symbol-level features to produce a deterministic series of
2576 * symbols for a given frame. We need to reset those features only once
2577 * a frame (instead of every nth symbol):
2578 * - DC-balance: used to ensure a better clock recovery from the data
2579 * link (SDVO)
2580 * - DisplayPort scrambling: used for EMI reduction
2581 */
2582 if (need_stable_symbols) {
2583 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
2584
2585 WARN_ON(!IS_G4X(dev));
2586
2587 tmp |= DC_BALANCE_RESET_VLV;
2588 if (pipe == PIPE_A)
2589 tmp |= PIPE_A_SCRAMBLE_RESET;
2590 else
2591 tmp |= PIPE_B_SCRAMBLE_RESET;
2592
2593 I915_WRITE(PORT_DFT2_G4X, tmp);
2594 }
2595
7ac0129b
DV		 2596 return 0;
2597}
2598
4b79ebf7 2599static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
46a19188
DV		 2600 enum pipe pipe,
2601 enum intel_pipe_crc_source *source,
4b79ebf7
DV		 2602 uint32_t *val)
2603{
84093603
DV		 2604 struct drm_i915_private *dev_priv = dev->dev_private;
2605 bool need_stable_symbols = false;
2606
46a19188
DV		 2607 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
2608 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
2609 if (ret)
2610 return ret;
2611 }
2612
2613 switch (*source) {
4b79ebf7
DV		 2614 case INTEL_PIPE_CRC_SOURCE_PIPE:
2615 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
2616 break;
2617 case INTEL_PIPE_CRC_SOURCE_TV:
2618 if (!SUPPORTS_TV(dev))
2619 return -EINVAL;
2620 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
2621 break;
2622 case INTEL_PIPE_CRC_SOURCE_DP_B:
2623 if (!IS_G4X(dev))
2624 return -EINVAL;
2625 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
84093603 2626 need_stable_symbols = true;
4b79ebf7
DV		 2627 break;
2628 case INTEL_PIPE_CRC_SOURCE_DP_C:
2629 if (!IS_G4X(dev))
2630 return -EINVAL;
2631 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
84093603 2632 need_stable_symbols = true;
4b79ebf7
DV		 2633 break;
2634 case INTEL_PIPE_CRC_SOURCE_DP_D:
2635 if (!IS_G4X(dev))
2636 return -EINVAL;
2637 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
84093603 2638 need_stable_symbols = true;
4b79ebf7
DV		 2639 break;
2640 case INTEL_PIPE_CRC_SOURCE_NONE:
2641 *val = 0;
2642 break;
2643 default:
2644 return -EINVAL;
2645 }
2646
84093603
DV		 2647 /*
2648 * When the pipe CRC tap point is after the transcoders we need
2649 * to tweak symbol-level features to produce a deterministic series of
2650 * symbols for a given frame. We need to reset those features only once
2651 * a frame (instead of every nth symbol):
2652 * - DC-balance: used to ensure a better clock recovery from the data
2653 * link (SDVO)
2654 * - DisplayPort scrambling: used for EMI reduction
2655 */
2656 if (need_stable_symbols) {
2657 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
2658
2659 WARN_ON(!IS_G4X(dev));
2660
2661 I915_WRITE(PORT_DFT_I9XX,
2662 I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
2663
2664 if (pipe == PIPE_A)
2665 tmp |= PIPE_A_SCRAMBLE_RESET;
2666 else
2667 tmp |= PIPE_B_SCRAMBLE_RESET;
2668
2669 I915_WRITE(PORT_DFT2_G4X, tmp);
2670 }
2671
4b79ebf7
DV		 2672 return 0;
2673}
2674
8d2f24ca
DV		 2675static void vlv_undo_pipe_scramble_reset(struct drm_device *dev,
2676 enum pipe pipe)
2677{
2678 struct drm_i915_private *dev_priv = dev->dev_private;
2679 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
2680
2681 if (pipe == PIPE_A)
2682 tmp &= ~PIPE_A_SCRAMBLE_RESET;
2683 else
2684 tmp &= ~PIPE_B_SCRAMBLE_RESET;
2685 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
2686 tmp &= ~DC_BALANCE_RESET_VLV;
2687 I915_WRITE(PORT_DFT2_G4X, tmp);
2688
2689}
2690
84093603
DV		 2691static void g4x_undo_pipe_scramble_reset(struct drm_device *dev,
2692 enum pipe pipe)
2693{
2694 struct drm_i915_private *dev_priv = dev->dev_private;
2695 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
2696
2697 if (pipe == PIPE_A)
2698 tmp &= ~PIPE_A_SCRAMBLE_RESET;
2699 else
2700 tmp &= ~PIPE_B_SCRAMBLE_RESET;
2701 I915_WRITE(PORT_DFT2_G4X, tmp);
2702
2703 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
2704 I915_WRITE(PORT_DFT_I9XX,
2705 I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
2706 }
2707}
2708
46a19188 2709static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
5b3a856b
DV		 2710 uint32_t *val)
2711{
46a19188
DV		 2712 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
2713 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
2714
2715 switch (*source) {
5b3a856b
DV		 2716 case INTEL_PIPE_CRC_SOURCE_PLANE1:
2717 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
2718 break;
2719 case INTEL_PIPE_CRC_SOURCE_PLANE2:
2720 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
2721 break;
5b3a856b
DV		 2722 case INTEL_PIPE_CRC_SOURCE_PIPE:
2723 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
2724 break;
3d099a05 2725 case INTEL_PIPE_CRC_SOURCE_NONE:
5b3a856b
DV		 2726 *val = 0;
2727 break;
3d099a05
DV		 2728 default:
2729 return -EINVAL;
5b3a856b
DV		 2730 }
2731
2732 return 0;
2733}
2734
46a19188 2735static int ivb_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
5b3a856b
DV		 2736 uint32_t *val)
2737{
46a19188
DV		 2738 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
2739 *source = INTEL_PIPE_CRC_SOURCE_PF;
2740
2741 switch (*source) {
5b3a856b
DV		 2742 case INTEL_PIPE_CRC_SOURCE_PLANE1:
2743 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
2744 break;
2745 case INTEL_PIPE_CRC_SOURCE_PLANE2:
2746 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
2747 break;
2748 case INTEL_PIPE_CRC_SOURCE_PF:
2749 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
2750 break;
3d099a05 2751 case INTEL_PIPE_CRC_SOURCE_NONE:
5b3a856b
DV		 2752 *val = 0;
2753 break;
3d099a05
DV		 2754 default:
2755 return -EINVAL;
5b3a856b
DV		 2756 }
2757
2758 return 0;
2759}
2760
926321d5
DV		 2761static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
2762 enum intel_pipe_crc_source source)
2763{
2764 struct drm_i915_private *dev_priv = dev->dev_private;
cc3da175 2765 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
432f3342 2766 u32 val = 0; /* shut up gcc */
5b3a856b 2767 int ret;
926321d5 2768
cc3da175
DL		 2769 if (pipe_crc->source == source)
2770 return 0;
2771
ae676fcd
DL		 2772 /* forbid changing the source without going back to 'none' */
2773 if (pipe_crc->source && source)
2774 return -EINVAL;
2775
52f843f6 2776 if (IS_GEN2(dev))
46a19188 2777 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
52f843f6 2778 else if (INTEL_INFO(dev)->gen < 5)
46a19188 2779 ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
7ac0129b 2780 else if (IS_VALLEYVIEW(dev))
46a19188 2781 ret = vlv_pipe_crc_ctl_reg(dev,pipe, &source, &val);
4b79ebf7 2782 else if (IS_GEN5(dev) || IS_GEN6(dev))
46a19188 2783 ret = ilk_pipe_crc_ctl_reg(&source, &val);
5b3a856b 2784 else
46a19188 2785 ret = ivb_pipe_crc_ctl_reg(&source, &val);
5b3a856b
DV		 2786
2787 if (ret != 0)
2788 return ret;
2789
4b584369
DL		 2790 /* none -> real source transition */
2791 if (source) {
7cd6ccff
DL		 2792 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
2793 pipe_name(pipe), pipe_crc_source_name(source));
2794
e5f75aca
DL		 2795 pipe_crc->entries = kzalloc(sizeof(*pipe_crc->entries) *
2796 INTEL_PIPE_CRC_ENTRIES_NR,
2797 GFP_KERNEL);
2798 if (!pipe_crc->entries)
2799 return -ENOMEM;
2800
d538bbdf
DL		 2801 spin_lock_irq(&pipe_crc->lock);
2802 pipe_crc->head = 0;
2803 pipe_crc->tail = 0;
2804 spin_unlock_irq(&pipe_crc->lock);
4b584369
DL		 2805 }
2806
cc3da175 2807 pipe_crc->source = source;
926321d5 2808
926321d5
DV		 2809 I915_WRITE(PIPE_CRC_CTL(pipe), val);
2810 POSTING_READ(PIPE_CRC_CTL(pipe));
2811
e5f75aca
DL		 2812 /* real source -> none transition */
2813 if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
d538bbdf
DL		 2814 struct intel_pipe_crc_entry *entries;
2815
7cd6ccff
DL		 2816 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
2817 pipe_name(pipe));
2818
bcf17ab2
DV		 2819 intel_wait_for_vblank(dev, pipe);
2820
d538bbdf
DL		 2821 spin_lock_irq(&pipe_crc->lock);
2822 entries = pipe_crc->entries;
e5f75aca 2823 pipe_crc->entries = NULL;
d538bbdf
DL		 2824 spin_unlock_irq(&pipe_crc->lock);
2825
2826 kfree(entries);
84093603
DV		 2827
2828 if (IS_G4X(dev))
2829 g4x_undo_pipe_scramble_reset(dev, pipe);
8d2f24ca
DV		 2830 else if (IS_VALLEYVIEW(dev))
2831 vlv_undo_pipe_scramble_reset(dev, pipe);
e5f75aca
DL		 2832 }
2833
926321d5
DV		 2834 return 0;
2835}
2836
2837/*
2838 * Parse pipe CRC command strings:
b94dec87
DL		 2839 * command: wsp* object wsp+ name wsp+ source wsp*
2840 * object: 'pipe'
2841 * name: (A | B | C)
926321d5
DV		 2842 * source: (none | plane1 | plane2 | pf)
2843 * wsp: (#0x20 | #0x9 | #0xA)+
2844 *
2845 * eg.:
b94dec87
DL		 2846 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A
2847 * "pipe A none" -> Stop CRC
926321d5 2848 */
bd9db02f 2849static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
926321d5
DV		 2850{
2851 int n_words = 0;
2852
2853 while (*buf) {
2854 char *end;
2855
2856 /* skip leading white space */
2857 buf = skip_spaces(buf);
2858 if (!*buf)
2859 break; /* end of buffer */
2860
2861 /* find end of word */
2862 for (end = buf; *end && !isspace(*end); end++)
2863 ;
2864
2865 if (n_words == max_words) {
2866 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
2867 max_words);
2868 return -EINVAL; /* ran out of words[] before bytes */
2869 }
2870
2871 if (*end)
2872 *end++ = '\0';
2873 words[n_words++] = buf;
2874 buf = end;
2875 }
2876
2877 return n_words;
2878}
2879
b94dec87
DL		 2880enum intel_pipe_crc_object {
2881 PIPE_CRC_OBJECT_PIPE,
2882};
2883
e8dfcf78 2884static const char * const pipe_crc_objects[] = {
b94dec87
DL		 2885 "pipe",
2886};
2887
2888static int
bd9db02f 2889display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
b94dec87
DL		 2890{
2891 int i;
2892
2893 for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
2894 if (!strcmp(buf, pipe_crc_objects[i])) {
bd9db02f 2895 *o = i;
b94dec87
DL		 2896 return 0;
2897 }
2898
2899 return -EINVAL;
2900}
2901
bd9db02f 2902static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
926321d5
DV		 2903{
2904 const char name = buf[0];
2905
2906 if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
2907 return -EINVAL;
2908
2909 *pipe = name - 'A';
2910
2911 return 0;
2912}
2913
2914static int
bd9db02f 2915display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
926321d5
DV		 2916{
2917 int i;
2918
2919 for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
2920 if (!strcmp(buf, pipe_crc_sources[i])) {
bd9db02f 2921 *s = i;
926321d5
DV		 2922 return 0;
2923 }
2924
2925 return -EINVAL;
2926}
2927
bd9db02f 2928static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len)
926321d5 2929{
b94dec87 2930#define N_WORDS 3
926321d5 2931 int n_words;
b94dec87 2932 char *words[N_WORDS];
926321d5 2933 enum pipe pipe;
b94dec87 2934 enum intel_pipe_crc_object object;
926321d5
DV		 2935 enum intel_pipe_crc_source source;
2936
bd9db02f 2937 n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
b94dec87
DL		 2938 if (n_words != N_WORDS) {
2939 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
2940 N_WORDS);
2941 return -EINVAL;
2942 }
2943
bd9db02f 2944 if (display_crc_ctl_parse_object(words[0], &object) < 0) {
b94dec87 2945 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
926321d5
DV		 2946 return -EINVAL;
2947 }
2948
bd9db02f 2949 if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
b94dec87 2950 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
926321d5
DV		 2951 return -EINVAL;
2952 }
2953
bd9db02f 2954 if (display_crc_ctl_parse_source(words[2], &source) < 0) {
b94dec87 2955 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
926321d5
DV		 2956 return -EINVAL;
2957 }
2958
2959 return pipe_crc_set_source(dev, pipe, source);
2960}
2961
bd9db02f
DL		 2962static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
2963 size_t len, loff_t *offp)
926321d5
DV		 2964{
2965 struct seq_file *m = file->private_data;
2966 struct drm_device *dev = m->private;
2967 char *tmpbuf;
2968 int ret;
2969
2970 if (len == 0)
2971 return 0;
2972
2973 if (len > PAGE_SIZE - 1) {
2974 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
2975 PAGE_SIZE);
2976 return -E2BIG;
2977 }
2978
2979 tmpbuf = kmalloc(len + 1, GFP_KERNEL);
2980 if (!tmpbuf)
2981 return -ENOMEM;
2982
2983 if (copy_from_user(tmpbuf, ubuf, len)) {
2984 ret = -EFAULT;
2985 goto out;
2986 }
2987 tmpbuf[len] = '\0';
2988
bd9db02f 2989 ret = display_crc_ctl_parse(dev, tmpbuf, len);
926321d5
DV		 2990
2991out:
2992 kfree(tmpbuf);
2993 if (ret < 0)
2994 return ret;
2995
2996 *offp += len;
2997 return len;
2998}
2999
bd9db02f 3000static const struct file_operations i915_display_crc_ctl_fops = {
926321d5 3001 .owner = THIS_MODULE,
bd9db02f 3002 .open = display_crc_ctl_open,
926321d5
DV		 3003 .read = seq_read,
3004 .llseek = seq_lseek,
3005 .release = single_release,
bd9db02f 3006 .write = display_crc_ctl_write
926321d5
DV		 3007};
3008
369a1342
VS		 3009static void wm_latency_show(struct seq_file *m, const uint16_t wm[5])
3010{
3011 struct drm_device *dev = m->private;
3012 int num_levels = IS_HASWELL(dev) || IS_BROADWELL(dev) ? 5 : 4;
3013 int level;
3014
3015 drm_modeset_lock_all(dev);
3016
3017 for (level = 0; level < num_levels; level++) {
3018 unsigned int latency = wm[level];
3019
3020 /* WM1+ latency values in 0.5us units */
3021 if (level > 0)
3022 latency *= 5;
3023
3024 seq_printf(m, "WM%d %u (%u.%u usec)\n",
3025 level, wm[level],
3026 latency / 10, latency % 10);
3027 }
3028
3029 drm_modeset_unlock_all(dev);
3030}
3031
3032static int pri_wm_latency_show(struct seq_file *m, void *data)
3033{
3034 struct drm_device *dev = m->private;
3035
3036 wm_latency_show(m, to_i915(dev)->wm.pri_latency);
3037
3038 return 0;
3039}
3040
3041static int spr_wm_latency_show(struct seq_file *m, void *data)
3042{
3043 struct drm_device *dev = m->private;
3044
3045 wm_latency_show(m, to_i915(dev)->wm.spr_latency);
3046
3047 return 0;
3048}
3049
3050static int cur_wm_latency_show(struct seq_file *m, void *data)
3051{
3052 struct drm_device *dev = m->private;
3053
3054 wm_latency_show(m, to_i915(dev)->wm.cur_latency);
3055
3056 return 0;
3057}
3058
3059static int pri_wm_latency_open(struct inode *inode, struct file *file)
3060{
3061 struct drm_device *dev = inode->i_private;
3062
3063 if (!HAS_PCH_SPLIT(dev))
3064 return -ENODEV;
3065
3066 return single_open(file, pri_wm_latency_show, dev);
3067}
3068
3069static int spr_wm_latency_open(struct inode *inode, struct file *file)
3070{
3071 struct drm_device *dev = inode->i_private;
3072
3073 if (!HAS_PCH_SPLIT(dev))
3074 return -ENODEV;
3075
3076 return single_open(file, spr_wm_latency_show, dev);
3077}
3078
3079static int cur_wm_latency_open(struct inode *inode, struct file *file)
3080{
3081 struct drm_device *dev = inode->i_private;
3082
3083 if (!HAS_PCH_SPLIT(dev))
3084 return -ENODEV;
3085
3086 return single_open(file, cur_wm_latency_show, dev);
3087}
3088
3089static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
3090 size_t len, loff_t *offp, uint16_t wm[5])
3091{
3092 struct seq_file *m = file->private_data;
3093 struct drm_device *dev = m->private;
3094 uint16_t new[5] = { 0 };
3095 int num_levels = IS_HASWELL(dev) || IS_BROADWELL(dev) ? 5 : 4;
3096 int level;
3097 int ret;
3098 char tmp[32];
3099
3100 if (len >= sizeof(tmp))
3101 return -EINVAL;
3102
3103 if (copy_from_user(tmp, ubuf, len))
3104 return -EFAULT;
3105
3106 tmp[len] = '\0';
3107
3108 ret = sscanf(tmp, "%hu %hu %hu %hu %hu", &new[0], &new[1], &new[2], &new[3], &new[4]);
3109 if (ret != num_levels)
3110 return -EINVAL;
3111
3112 drm_modeset_lock_all(dev);
3113
3114 for (level = 0; level < num_levels; level++)
3115 wm[level] = new[level];
3116
3117 drm_modeset_unlock_all(dev);
3118
3119 return len;
3120}
3121
3122
3123static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
3124 size_t len, loff_t *offp)
3125{
3126 struct seq_file *m = file->private_data;
3127 struct drm_device *dev = m->private;
3128
3129 return wm_latency_write(file, ubuf, len, offp, to_i915(dev)->wm.pri_latency);
3130}
3131
3132static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
3133 size_t len, loff_t *offp)
3134{
3135 struct seq_file *m = file->private_data;
3136 struct drm_device *dev = m->private;
3137
3138 return wm_latency_write(file, ubuf, len, offp, to_i915(dev)->wm.spr_latency);
3139}
3140
3141static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
3142 size_t len, loff_t *offp)
3143{
3144 struct seq_file *m = file->private_data;
3145 struct drm_device *dev = m->private;
3146
3147 return wm_latency_write(file, ubuf, len, offp, to_i915(dev)->wm.cur_latency);
3148}
3149
3150static const struct file_operations i915_pri_wm_latency_fops = {
3151 .owner = THIS_MODULE,
3152 .open = pri_wm_latency_open,
3153 .read = seq_read,
3154 .llseek = seq_lseek,
3155 .release = single_release,
3156 .write = pri_wm_latency_write
3157};
3158
3159static const struct file_operations i915_spr_wm_latency_fops = {
3160 .owner = THIS_MODULE,
3161 .open = spr_wm_latency_open,
3162 .read = seq_read,
3163 .llseek = seq_lseek,
3164 .release = single_release,
3165 .write = spr_wm_latency_write
3166};
3167
3168static const struct file_operations i915_cur_wm_latency_fops = {
3169 .owner = THIS_MODULE,
3170 .open = cur_wm_latency_open,
3171 .read = seq_read,
3172 .llseek = seq_lseek,
3173 .release = single_release,
3174 .write = cur_wm_latency_write
3175};
3176
647416f9
KC		 3177static int
3178i915_wedged_get(void *data, u64 *val)
f3cd474b 3179{
647416f9 3180 struct drm_device *dev = data;
f3cd474b 3181 drm_i915_private_t *dev_priv = dev->dev_private;
f3cd474b 3182
647416f9 3183 *val = atomic_read(&dev_priv->gpu_error.reset_counter);
f3cd474b 3184
647416f9 3185 return 0;
f3cd474b
CW		 3186}
3187
647416f9
KC		 3188static int
3189i915_wedged_set(void *data, u64 val)
f3cd474b 3190{
647416f9 3191 struct drm_device *dev = data;
f3cd474b 3192
647416f9 3193 DRM_INFO("Manually setting wedged to %llu\n", val);
527f9e90 3194 i915_handle_error(dev, val);
f3cd474b 3195
647416f9 3196 return 0;
f3cd474b
CW		 3197}
3198
647416f9
KC		 3199DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
3200 i915_wedged_get, i915_wedged_set,
3a3b4f98 3201 "%llu\n");
f3cd474b 3202
647416f9
KC		 3203static int
3204i915_ring_stop_get(void *data, u64 *val)
e5eb3d63 3205{
647416f9 3206 struct drm_device *dev = data;
e5eb3d63 3207 drm_i915_private_t *dev_priv = dev->dev_private;
e5eb3d63 3208
647416f9 3209 *val = dev_priv->gpu_error.stop_rings;
e5eb3d63 3210
647416f9 3211 return 0;
e5eb3d63
DV		 3212}
3213
647416f9
KC		 3214static int
3215i915_ring_stop_set(void *data, u64 val)
e5eb3d63 3216{
647416f9 3217 struct drm_device *dev = data;
e5eb3d63 3218 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 3219 int ret;
e5eb3d63 3220
647416f9 3221 DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val);
e5eb3d63 3222
22bcfc6a
DV		 3223 ret = mutex_lock_interruptible(&dev->struct_mutex);
3224 if (ret)
3225 return ret;
3226
99584db3 3227 dev_priv->gpu_error.stop_rings = val;
e5eb3d63
DV		 3228 mutex_unlock(&dev->struct_mutex);
3229
647416f9 3230 return 0;
e5eb3d63
DV		 3231}
3232
647416f9
KC		 3233DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops,
3234 i915_ring_stop_get, i915_ring_stop_set,
3235 "0x%08llx\n");
d5442303 3236
094f9a54
CW		 3237static int
3238i915_ring_missed_irq_get(void *data, u64 *val)
3239{
3240 struct drm_device *dev = data;
3241 struct drm_i915_private *dev_priv = dev->dev_private;
3242
3243 *val = dev_priv->gpu_error.missed_irq_rings;
3244 return 0;
3245}
3246
3247static int
3248i915_ring_missed_irq_set(void *data, u64 val)
3249{
3250 struct drm_device *dev = data;
3251 struct drm_i915_private *dev_priv = dev->dev_private;
3252 int ret;
3253
3254 /* Lock against concurrent debugfs callers */
3255 ret = mutex_lock_interruptible(&dev->struct_mutex);
3256 if (ret)
3257 return ret;
3258 dev_priv->gpu_error.missed_irq_rings = val;
3259 mutex_unlock(&dev->struct_mutex);
3260
3261 return 0;
3262}
3263
3264DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
3265 i915_ring_missed_irq_get, i915_ring_missed_irq_set,
3266 "0x%08llx\n");
3267
3268static int
3269i915_ring_test_irq_get(void *data, u64 *val)
3270{
3271 struct drm_device *dev = data;
3272 struct drm_i915_private *dev_priv = dev->dev_private;
3273
3274 *val = dev_priv->gpu_error.test_irq_rings;
3275
3276 return 0;
3277}
3278
3279static int
3280i915_ring_test_irq_set(void *data, u64 val)
3281{
3282 struct drm_device *dev = data;
3283 struct drm_i915_private *dev_priv = dev->dev_private;
3284 int ret;
3285
3286 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
3287
3288 /* Lock against concurrent debugfs callers */
3289 ret = mutex_lock_interruptible(&dev->struct_mutex);
3290 if (ret)
3291 return ret;
3292
3293 dev_priv->gpu_error.test_irq_rings = val;
3294 mutex_unlock(&dev->struct_mutex);
3295
3296 return 0;
3297}
3298
3299DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
3300 i915_ring_test_irq_get, i915_ring_test_irq_set,
3301 "0x%08llx\n");
3302
dd624afd
CW		 3303#define DROP_UNBOUND 0x1
3304#define DROP_BOUND 0x2
3305#define DROP_RETIRE 0x4
3306#define DROP_ACTIVE 0x8
3307#define DROP_ALL (DROP_UNBOUND | \
3308 DROP_BOUND | \
3309 DROP_RETIRE | \
3310 DROP_ACTIVE)
647416f9
KC		 3311static int
3312i915_drop_caches_get(void *data, u64 *val)
dd624afd 3313{
647416f9 3314 *val = DROP_ALL;
dd624afd 3315
647416f9 3316 return 0;
dd624afd
CW		 3317}
3318
647416f9
KC		 3319static int
3320i915_drop_caches_set(void *data, u64 val)
dd624afd 3321{
647416f9 3322 struct drm_device *dev = data;
dd624afd
CW		 3323 struct drm_i915_private *dev_priv = dev->dev_private;
3324 struct drm_i915_gem_object *obj, *next;
ca191b13
BW		 3325 struct i915_address_space *vm;
3326 struct i915_vma *vma, *x;
647416f9 3327 int ret;
dd624afd 3328
2f9fe5ff 3329 DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
dd624afd
CW		 3330
3331 /* No need to check and wait for gpu resets, only libdrm auto-restarts
3332 * on ioctls on -EAGAIN. */
3333 ret = mutex_lock_interruptible(&dev->struct_mutex);
3334 if (ret)
3335 return ret;
3336
3337 if (val & DROP_ACTIVE) {
3338 ret = i915_gpu_idle(dev);
3339 if (ret)
3340 goto unlock;
3341 }
3342
3343 if (val & (DROP_RETIRE | DROP_ACTIVE))
3344 i915_gem_retire_requests(dev);
3345
3346 if (val & DROP_BOUND) {
ca191b13
BW		 3347 list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
3348 list_for_each_entry_safe(vma, x, &vm->inactive_list,
3349 mm_list) {
d7f46fc4 3350 if (vma->pin_count)
ca191b13
BW		 3351 continue;
3352
3353 ret = i915_vma_unbind(vma);
3354 if (ret)
3355 goto unlock;
3356 }
31a46c9c 3357 }
dd624afd
CW		 3358 }
3359
3360 if (val & DROP_UNBOUND) {
35c20a60
BW		 3361 list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list,
3362 global_list)
dd624afd
CW		 3363 if (obj->pages_pin_count == 0) {
3364 ret = i915_gem_object_put_pages(obj);
3365 if (ret)
3366 goto unlock;
3367 }
3368 }
3369
3370unlock:
3371 mutex_unlock(&dev->struct_mutex);
3372
647416f9 3373 return ret;
dd624afd
CW		 3374}
3375
647416f9
KC		 3376DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
3377 i915_drop_caches_get, i915_drop_caches_set,
3378 "0x%08llx\n");
dd624afd 3379
647416f9
KC		 3380static int
3381i915_max_freq_get(void *data, u64 *val)
358733e9 3382{
647416f9 3383 struct drm_device *dev = data;
358733e9 3384 drm_i915_private_t *dev_priv = dev->dev_private;
647416f9 3385 int ret;
004777cb
DV		 3386
3387 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
3388 return -ENODEV;
3389
5c9669ce
TR		 3390 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
3391
4fc688ce 3392 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 3393 if (ret)
3394 return ret;
358733e9 3395
0a073b84 3396 if (IS_VALLEYVIEW(dev))
2ec3815f 3397 *val = vlv_gpu_freq(dev_priv, dev_priv->rps.max_delay);
0a073b84
JB		 3398 else
3399 *val = dev_priv->rps.max_delay * GT_FREQUENCY_MULTIPLIER;
4fc688ce 3400 mutex_unlock(&dev_priv->rps.hw_lock);
358733e9 3401
647416f9 3402 return 0;
358733e9
JB		 3403}
3404
647416f9
KC		 3405static int
3406i915_max_freq_set(void *data, u64 val)
358733e9 3407{
647416f9 3408 struct drm_device *dev = data;
358733e9 3409 struct drm_i915_private *dev_priv = dev->dev_private;
dd0a1aa1 3410 u32 rp_state_cap, hw_max, hw_min;
647416f9 3411 int ret;
004777cb
DV		 3412
3413 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
3414 return -ENODEV;
358733e9 3415
5c9669ce
TR		 3416 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
3417
647416f9 3418 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
358733e9 3419
4fc688ce 3420 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 3421 if (ret)
3422 return ret;
3423
358733e9
JB		 3424 /*
3425 * Turbo will still be enabled, but won't go above the set value.
3426 */
0a073b84 3427 if (IS_VALLEYVIEW(dev)) {
2ec3815f 3428 val = vlv_freq_opcode(dev_priv, val);
dd0a1aa1
JM		 3429
3430 hw_max = valleyview_rps_max_freq(dev_priv);
3431 hw_min = valleyview_rps_min_freq(dev_priv);
0a073b84
JB		 3432 } else {
3433 do_div(val, GT_FREQUENCY_MULTIPLIER);
dd0a1aa1
JM		 3434
3435 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3436 hw_max = dev_priv->rps.hw_max;
3437 hw_min = (rp_state_cap >> 16) & 0xff;
3438 }
3439
3440 if (val < hw_min || val > hw_max || val < dev_priv->rps.min_delay) {
3441 mutex_unlock(&dev_priv->rps.hw_lock);
3442 return -EINVAL;
0a073b84
JB		 3443 }
3444
dd0a1aa1
JM		 3445 dev_priv->rps.max_delay = val;
3446
3447 if (IS_VALLEYVIEW(dev))
3448 valleyview_set_rps(dev, val);
3449 else
3450 gen6_set_rps(dev, val);
3451
4fc688ce 3452 mutex_unlock(&dev_priv->rps.hw_lock);
358733e9 3453
647416f9 3454 return 0;
358733e9
JB		 3455}
3456
647416f9
KC		 3457DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
3458 i915_max_freq_get, i915_max_freq_set,
3a3b4f98 3459 "%llu\n");
358733e9 3460
647416f9
KC		 3461static int
3462i915_min_freq_get(void *data, u64 *val)
1523c310 3463{
647416f9 3464 struct drm_device *dev = data;
1523c310 3465 drm_i915_private_t *dev_priv = dev->dev_private;
647416f9 3466 int ret;
004777cb
DV		 3467
3468 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
3469 return -ENODEV;
3470
5c9669ce
TR		 3471 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
3472
4fc688ce 3473 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 3474 if (ret)
3475 return ret;
1523c310 3476
0a073b84 3477 if (IS_VALLEYVIEW(dev))
2ec3815f 3478 *val = vlv_gpu_freq(dev_priv, dev_priv->rps.min_delay);
0a073b84
JB		 3479 else
3480 *val = dev_priv->rps.min_delay * GT_FREQUENCY_MULTIPLIER;
4fc688ce 3481 mutex_unlock(&dev_priv->rps.hw_lock);
1523c310 3482
647416f9 3483 return 0;
1523c310
JB		 3484}
3485
647416f9
KC		 3486static int
3487i915_min_freq_set(void *data, u64 val)
1523c310 3488{
647416f9 3489 struct drm_device *dev = data;
1523c310 3490 struct drm_i915_private *dev_priv = dev->dev_private;
dd0a1aa1 3491 u32 rp_state_cap, hw_max, hw_min;
647416f9 3492 int ret;
004777cb
DV		 3493
3494 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
3495 return -ENODEV;
1523c310 3496
5c9669ce
TR		 3497 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
3498
647416f9 3499 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
1523c310 3500
4fc688ce 3501 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 3502 if (ret)
3503 return ret;
3504
1523c310
JB		 3505 /*
3506 * Turbo will still be enabled, but won't go below the set value.
3507 */
0a073b84 3508 if (IS_VALLEYVIEW(dev)) {
2ec3815f 3509 val = vlv_freq_opcode(dev_priv, val);
dd0a1aa1
JM		 3510
3511 hw_max = valleyview_rps_max_freq(dev_priv);
3512 hw_min = valleyview_rps_min_freq(dev_priv);
0a073b84
JB		 3513 } else {
3514 do_div(val, GT_FREQUENCY_MULTIPLIER);
dd0a1aa1
JM		 3515
3516 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3517 hw_max = dev_priv->rps.hw_max;
3518 hw_min = (rp_state_cap >> 16) & 0xff;
3519 }
3520
3521 if (val < hw_min || val > hw_max || val > dev_priv->rps.max_delay) {
3522 mutex_unlock(&dev_priv->rps.hw_lock);
3523 return -EINVAL;
0a073b84 3524 }
dd0a1aa1
JM		 3525
3526 dev_priv->rps.min_delay = val;
3527
3528 if (IS_VALLEYVIEW(dev))
3529 valleyview_set_rps(dev, val);
3530 else
3531 gen6_set_rps(dev, val);
3532
4fc688ce 3533 mutex_unlock(&dev_priv->rps.hw_lock);
1523c310 3534
647416f9 3535 return 0;
1523c310
JB		 3536}
3537
647416f9
KC		 3538DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
3539 i915_min_freq_get, i915_min_freq_set,
3a3b4f98 3540 "%llu\n");
1523c310 3541
647416f9
KC		 3542static int
3543i915_cache_sharing_get(void *data, u64 *val)
07b7ddd9 3544{
647416f9 3545 struct drm_device *dev = data;
07b7ddd9 3546 drm_i915_private_t *dev_priv = dev->dev_private;
07b7ddd9 3547 u32 snpcr;
647416f9 3548 int ret;
07b7ddd9 3549
004777cb
DV		 3550 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
3551 return -ENODEV;
3552
22bcfc6a
DV		 3553 ret = mutex_lock_interruptible(&dev->struct_mutex);
3554 if (ret)
3555 return ret;
c8c8fb33 3556 intel_runtime_pm_get(dev_priv);
22bcfc6a 3557
07b7ddd9 3558 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
c8c8fb33
PZ		 3559
3560 intel_runtime_pm_put(dev_priv);
07b7ddd9
JB		 3561 mutex_unlock(&dev_priv->dev->struct_mutex);
3562
647416f9 3563 *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
07b7ddd9 3564
647416f9 3565 return 0;
07b7ddd9
JB		 3566}
3567
647416f9
KC		 3568static int
3569i915_cache_sharing_set(void *data, u64 val)
07b7ddd9 3570{
647416f9 3571 struct drm_device *dev = data;
07b7ddd9 3572 struct drm_i915_private *dev_priv = dev->dev_private;
07b7ddd9 3573 u32 snpcr;
07b7ddd9 3574
004777cb
DV		 3575 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
3576 return -ENODEV;
3577
647416f9 3578 if (val > 3)
07b7ddd9
JB		 3579 return -EINVAL;
3580
c8c8fb33 3581 intel_runtime_pm_get(dev_priv);
647416f9 3582 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
07b7ddd9
JB		 3583
3584 /* Update the cache sharing policy here as well */
3585 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
3586 snpcr &= ~GEN6_MBC_SNPCR_MASK;
3587 snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
3588 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3589
c8c8fb33 3590 intel_runtime_pm_put(dev_priv);
647416f9 3591 return 0;
07b7ddd9
JB		 3592}
3593
647416f9
KC		 3594DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
3595 i915_cache_sharing_get, i915_cache_sharing_set,
3596 "%llu\n");
07b7ddd9 3597
6d794d42
BW		 3598static int i915_forcewake_open(struct inode *inode, struct file *file)
3599{
3600 struct drm_device *dev = inode->i_private;
3601 struct drm_i915_private *dev_priv = dev->dev_private;
6d794d42 3602
075edca4 3603 if (INTEL_INFO(dev)->gen < 6)
6d794d42
BW		 3604 return 0;
3605
c8c8fb33 3606 intel_runtime_pm_get(dev_priv);
c8d9a590 3607 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
6d794d42
BW		 3608
3609 return 0;
3610}
3611
c43b5634 3612static int i915_forcewake_release(struct inode *inode, struct file *file)
6d794d42
BW		 3613{
3614 struct drm_device *dev = inode->i_private;
3615 struct drm_i915_private *dev_priv = dev->dev_private;
3616
075edca4 3617 if (INTEL_INFO(dev)->gen < 6)
6d794d42
BW		 3618 return 0;
3619
c8d9a590 3620 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
c8c8fb33 3621 intel_runtime_pm_put(dev_priv);
6d794d42
BW		 3622
3623 return 0;
3624}
3625
3626static const struct file_operations i915_forcewake_fops = {
3627 .owner = THIS_MODULE,
3628 .open = i915_forcewake_open,
3629 .release = i915_forcewake_release,
3630};
3631
3632static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
3633{
3634 struct drm_device *dev = minor->dev;
3635 struct dentry *ent;
3636
3637 ent = debugfs_create_file("i915_forcewake_user",
8eb57294 3638 S_IRUSR,
6d794d42
BW		 3639 root, dev,
3640 &i915_forcewake_fops);
f3c5fe97
WY		 3641 if (!ent)
3642 return -ENOMEM;
6d794d42 3643
8eb57294 3644 return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
6d794d42
BW		 3645}
3646
6a9c308d
DV		 3647static int i915_debugfs_create(struct dentry *root,
3648 struct drm_minor *minor,
3649 const char *name,
3650 const struct file_operations *fops)
07b7ddd9
JB		 3651{
3652 struct drm_device *dev = minor->dev;
3653 struct dentry *ent;
3654
6a9c308d 3655 ent = debugfs_create_file(name,
07b7ddd9
JB		 3656 S_IRUGO | S_IWUSR,
3657 root, dev,
6a9c308d 3658 fops);
f3c5fe97
WY		 3659 if (!ent)
3660 return -ENOMEM;
07b7ddd9 3661
6a9c308d 3662 return drm_add_fake_info_node(minor, ent, fops);
07b7ddd9
JB		 3663}
3664
06c5bf8c 3665static const struct drm_info_list i915_debugfs_list[] = {
311bd68e 3666 {"i915_capabilities", i915_capabilities, 0},
73aa808f 3667 {"i915_gem_objects", i915_gem_object_info, 0},
08c18323 3668 {"i915_gem_gtt", i915_gem_gtt_info, 0},
1b50247a 3669 {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
433e12f7 3670 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
433e12f7 3671 {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
6d2b8885 3672 {"i915_gem_stolen", i915_gem_stolen_list_info },
4e5359cd 3673 {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
2017263e
BG		 3674 {"i915_gem_request", i915_gem_request_info, 0},
3675 {"i915_gem_seqno", i915_gem_seqno_info, 0},
a6172a80 3676 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
2017263e 3677 {"i915_gem_interrupt", i915_interrupt_info, 0},
1ec14ad3
CW		 3678 {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
3679 {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
3680 {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
9010ebfd 3681 {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
f97108d1
JB		 3682 {"i915_rstdby_delays", i915_rstdby_delays, 0},
3683 {"i915_cur_delayinfo", i915_cur_delayinfo, 0},
3684 {"i915_delayfreq_table", i915_delayfreq_table, 0},
3685 {"i915_inttoext_table", i915_inttoext_table, 0},
3686 {"i915_drpc_info", i915_drpc_info, 0},
7648fa99 3687 {"i915_emon_status", i915_emon_status, 0},
23b2f8bb 3688 {"i915_ring_freq_table", i915_ring_freq_table, 0},
7648fa99 3689 {"i915_gfxec", i915_gfxec, 0},
b5e50c3f 3690 {"i915_fbc_status", i915_fbc_status, 0},
92d44621 3691 {"i915_ips_status", i915_ips_status, 0},
4a9bef37 3692 {"i915_sr_status", i915_sr_status, 0},
44834a67 3693 {"i915_opregion", i915_opregion, 0},
37811fcc 3694 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
e76d3630 3695 {"i915_context_status", i915_context_status, 0},
6d794d42 3696 {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0},
ea16a3cd 3697 {"i915_swizzle_info", i915_swizzle_info, 0},
3cf17fc5 3698 {"i915_ppgtt_info", i915_ppgtt_info, 0},
57f350b6 3699 {"i915_dpio", i915_dpio_info, 0},
63573eb7 3700 {"i915_llc", i915_llc, 0},
e91fd8c6 3701 {"i915_edp_psr_status", i915_edp_psr_status, 0},
d2e216d0 3702 {"i915_sink_crc_eDP1", i915_sink_crc, 0},
ec013e7f 3703 {"i915_energy_uJ", i915_energy_uJ, 0},
371db66a 3704 {"i915_pc8_status", i915_pc8_status, 0},
1da51581 3705 {"i915_power_domain_info", i915_power_domain_info, 0},
53f5e3ca 3706 {"i915_display_info", i915_display_info, 0},
2017263e 3707};
27c202ad 3708#define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
2017263e 3709
06c5bf8c 3710static const struct i915_debugfs_files {
34b9674c
DV		 3711 const char *name;
3712 const struct file_operations *fops;
3713} i915_debugfs_files[] = {
3714 {"i915_wedged", &i915_wedged_fops},
3715 {"i915_max_freq", &i915_max_freq_fops},
3716 {"i915_min_freq", &i915_min_freq_fops},
3717 {"i915_cache_sharing", &i915_cache_sharing_fops},
3718 {"i915_ring_stop", &i915_ring_stop_fops},
094f9a54
CW		 3719 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
3720 {"i915_ring_test_irq", &i915_ring_test_irq_fops},
34b9674c
DV		 3721 {"i915_gem_drop_caches", &i915_drop_caches_fops},
3722 {"i915_error_state", &i915_error_state_fops},
3723 {"i915_next_seqno", &i915_next_seqno_fops},
bd9db02f 3724 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
369a1342
VS		 3725 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
3726 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
3727 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
34b9674c
DV		 3728};
3729
07144428
DL		 3730void intel_display_crc_init(struct drm_device *dev)
3731{
3732 struct drm_i915_private *dev_priv = dev->dev_private;
b378360e 3733 enum pipe pipe;
07144428 3734
b378360e
DV		 3735 for_each_pipe(pipe) {
3736 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
07144428 3737
d538bbdf
DL		 3738 pipe_crc->opened = false;
3739 spin_lock_init(&pipe_crc->lock);
07144428
DL		 3740 init_waitqueue_head(&pipe_crc->wq);
3741 }
3742}
3743
27c202ad 3744int i915_debugfs_init(struct drm_minor *minor)
2017263e 3745{
34b9674c 3746 int ret, i;
f3cd474b 3747
6d794d42 3748 ret = i915_forcewake_create(minor->debugfs_root, minor);
358733e9
JB		 3749 if (ret)
3750 return ret;
6a9c308d 3751
07144428
DL		 3752 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
3753 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
3754 if (ret)
3755 return ret;
3756 }
3757
34b9674c
DV		 3758 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
3759 ret = i915_debugfs_create(minor->debugfs_root, minor,
3760 i915_debugfs_files[i].name,
3761 i915_debugfs_files[i].fops);
3762 if (ret)
3763 return ret;
3764 }
40633219 3765
27c202ad
BG		 3766 return drm_debugfs_create_files(i915_debugfs_list,
3767 I915_DEBUGFS_ENTRIES,
2017263e
BG		 3768 minor->debugfs_root, minor);
3769}
3770
27c202ad 3771void i915_debugfs_cleanup(struct drm_minor *minor)
2017263e 3772{
34b9674c
DV		 3773 int i;
3774
27c202ad
BG		 3775 drm_debugfs_remove_files(i915_debugfs_list,
3776 I915_DEBUGFS_ENTRIES, minor);
07144428 3777
6d794d42
BW		 3778 drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
3779 1, minor);
07144428 3780
e309a997 3781 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
07144428
DL		 3782 struct drm_info_list *info_list =
3783 (struct drm_info_list *)&i915_pipe_crc_data[i];
3784
3785 drm_debugfs_remove_files(info_list, 1, minor);
3786 }
3787
34b9674c
DV		 3788 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
3789 struct drm_info_list *info_list =
3790 (struct drm_info_list *) i915_debugfs_files[i].fops;
3791
3792 drm_debugfs_remove_files(info_list, 1, minor);
3793 }
2017263e 3794}
Linux kernel - Deliverables
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