Commit | Line | Data |
---|---|---|
2017263e BG |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Keith Packard <keithp@keithp.com> | |
26 | * | |
27 | */ | |
28 | ||
29 | #include <linux/seq_file.h> | |
b2c88f5b | 30 | #include <linux/circ_buf.h> |
926321d5 | 31 | #include <linux/ctype.h> |
f3cd474b | 32 | #include <linux/debugfs.h> |
5a0e3ad6 | 33 | #include <linux/slab.h> |
2d1a8a48 | 34 | #include <linux/export.h> |
6d2b8885 | 35 | #include <linux/list_sort.h> |
ec013e7f | 36 | #include <asm/msr-index.h> |
760285e7 | 37 | #include <drm/drmP.h> |
4e5359cd | 38 | #include "intel_drv.h" |
e5c65260 | 39 | #include "intel_ringbuffer.h" |
760285e7 | 40 | #include <drm/i915_drm.h> |
2017263e BG |
41 | #include "i915_drv.h" |
42 | ||
f13d3f73 | 43 | enum { |
69dc4987 | 44 | ACTIVE_LIST, |
f13d3f73 | 45 | INACTIVE_LIST, |
d21d5975 | 46 | PINNED_LIST, |
f13d3f73 | 47 | }; |
2017263e | 48 | |
70d39fe4 CW |
49 | static const char *yesno(int v) |
50 | { | |
51 | return v ? "yes" : "no"; | |
52 | } | |
53 | ||
497666d8 DL |
54 | /* As the drm_debugfs_init() routines are called before dev->dev_private is |
55 | * allocated we need to hook into the minor for release. */ | |
56 | static int | |
57 | drm_add_fake_info_node(struct drm_minor *minor, | |
58 | struct dentry *ent, | |
59 | const void *key) | |
60 | { | |
61 | struct drm_info_node *node; | |
62 | ||
63 | node = kmalloc(sizeof(*node), GFP_KERNEL); | |
64 | if (node == NULL) { | |
65 | debugfs_remove(ent); | |
66 | return -ENOMEM; | |
67 | } | |
68 | ||
69 | node->minor = minor; | |
70 | node->dent = ent; | |
71 | node->info_ent = (void *) key; | |
72 | ||
73 | mutex_lock(&minor->debugfs_lock); | |
74 | list_add(&node->list, &minor->debugfs_list); | |
75 | mutex_unlock(&minor->debugfs_lock); | |
76 | ||
77 | return 0; | |
78 | } | |
79 | ||
70d39fe4 CW |
80 | static int i915_capabilities(struct seq_file *m, void *data) |
81 | { | |
9f25d007 | 82 | struct drm_info_node *node = m->private; |
70d39fe4 CW |
83 | struct drm_device *dev = node->minor->dev; |
84 | const struct intel_device_info *info = INTEL_INFO(dev); | |
85 | ||
86 | seq_printf(m, "gen: %d\n", info->gen); | |
03d00ac5 | 87 | seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev)); |
79fc46df DL |
88 | #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x)) |
89 | #define SEP_SEMICOLON ; | |
90 | DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON); | |
91 | #undef PRINT_FLAG | |
92 | #undef SEP_SEMICOLON | |
70d39fe4 CW |
93 | |
94 | return 0; | |
95 | } | |
2017263e | 96 | |
05394f39 | 97 | static const char *get_pin_flag(struct drm_i915_gem_object *obj) |
a6172a80 | 98 | { |
4feb7659 | 99 | if (i915_gem_obj_is_pinned(obj)) |
a6172a80 CW |
100 | return "p"; |
101 | else | |
102 | return " "; | |
103 | } | |
104 | ||
05394f39 | 105 | static const char *get_tiling_flag(struct drm_i915_gem_object *obj) |
a6172a80 | 106 | { |
0206e353 AJ |
107 | switch (obj->tiling_mode) { |
108 | default: | |
109 | case I915_TILING_NONE: return " "; | |
110 | case I915_TILING_X: return "X"; | |
111 | case I915_TILING_Y: return "Y"; | |
112 | } | |
a6172a80 CW |
113 | } |
114 | ||
1d693bcc BW |
115 | static inline const char *get_global_flag(struct drm_i915_gem_object *obj) |
116 | { | |
aff43766 | 117 | return i915_gem_obj_to_ggtt(obj) ? "g" : " "; |
1d693bcc BW |
118 | } |
119 | ||
37811fcc CW |
120 | static void |
121 | describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj) | |
122 | { | |
1d693bcc | 123 | struct i915_vma *vma; |
d7f46fc4 BW |
124 | int pin_count = 0; |
125 | ||
20e28fba | 126 | seq_printf(m, "%pK: %s%s%s %8zdKiB %02x %02x %x %x %x%s%s%s", |
37811fcc CW |
127 | &obj->base, |
128 | get_pin_flag(obj), | |
129 | get_tiling_flag(obj), | |
1d693bcc | 130 | get_global_flag(obj), |
a05a5862 | 131 | obj->base.size / 1024, |
37811fcc CW |
132 | obj->base.read_domains, |
133 | obj->base.write_domain, | |
97b2a6a1 JH |
134 | i915_gem_request_get_seqno(obj->last_read_req), |
135 | i915_gem_request_get_seqno(obj->last_write_req), | |
136 | i915_gem_request_get_seqno(obj->last_fenced_req), | |
0a4cd7c8 | 137 | i915_cache_level_str(to_i915(obj->base.dev), obj->cache_level), |
37811fcc CW |
138 | obj->dirty ? " dirty" : "", |
139 | obj->madv == I915_MADV_DONTNEED ? " purgeable" : ""); | |
140 | if (obj->base.name) | |
141 | seq_printf(m, " (name: %d)", obj->base.name); | |
d7f46fc4 BW |
142 | list_for_each_entry(vma, &obj->vma_list, vma_link) |
143 | if (vma->pin_count > 0) | |
144 | pin_count++; | |
145 | seq_printf(m, " (pinned x %d)", pin_count); | |
cc98b413 CW |
146 | if (obj->pin_display) |
147 | seq_printf(m, " (display)"); | |
37811fcc CW |
148 | if (obj->fence_reg != I915_FENCE_REG_NONE) |
149 | seq_printf(m, " (fence: %d)", obj->fence_reg); | |
1d693bcc BW |
150 | list_for_each_entry(vma, &obj->vma_list, vma_link) { |
151 | if (!i915_is_ggtt(vma->vm)) | |
152 | seq_puts(m, " (pp"); | |
153 | else | |
154 | seq_puts(m, " (g"); | |
fe14d5f4 TU |
155 | seq_printf(m, "gtt offset: %08lx, size: %08lx, type: %u)", |
156 | vma->node.start, vma->node.size, | |
157 | vma->ggtt_view.type); | |
1d693bcc | 158 | } |
c1ad11fc CW |
159 | if (obj->stolen) |
160 | seq_printf(m, " (stolen: %08lx)", obj->stolen->start); | |
6299f992 CW |
161 | if (obj->pin_mappable || obj->fault_mappable) { |
162 | char s[3], *t = s; | |
163 | if (obj->pin_mappable) | |
164 | *t++ = 'p'; | |
165 | if (obj->fault_mappable) | |
166 | *t++ = 'f'; | |
167 | *t = '\0'; | |
168 | seq_printf(m, " (%s mappable)", s); | |
169 | } | |
41c52415 JH |
170 | if (obj->last_read_req != NULL) |
171 | seq_printf(m, " (%s)", | |
172 | i915_gem_request_get_ring(obj->last_read_req)->name); | |
d5a81ef1 DV |
173 | if (obj->frontbuffer_bits) |
174 | seq_printf(m, " (frontbuffer: 0x%03x)", obj->frontbuffer_bits); | |
37811fcc CW |
175 | } |
176 | ||
273497e5 | 177 | static void describe_ctx(struct seq_file *m, struct intel_context *ctx) |
3ccfd19d | 178 | { |
ea0c76f8 | 179 | seq_putc(m, ctx->legacy_hw_ctx.initialized ? 'I' : 'i'); |
3ccfd19d BW |
180 | seq_putc(m, ctx->remap_slice ? 'R' : 'r'); |
181 | seq_putc(m, ' '); | |
182 | } | |
183 | ||
433e12f7 | 184 | static int i915_gem_object_list_info(struct seq_file *m, void *data) |
2017263e | 185 | { |
9f25d007 | 186 | struct drm_info_node *node = m->private; |
433e12f7 BG |
187 | uintptr_t list = (uintptr_t) node->info_ent->data; |
188 | struct list_head *head; | |
2017263e | 189 | struct drm_device *dev = node->minor->dev; |
5cef07e1 BW |
190 | struct drm_i915_private *dev_priv = dev->dev_private; |
191 | struct i915_address_space *vm = &dev_priv->gtt.base; | |
ca191b13 | 192 | struct i915_vma *vma; |
8f2480fb CW |
193 | size_t total_obj_size, total_gtt_size; |
194 | int count, ret; | |
de227ef0 CW |
195 | |
196 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
197 | if (ret) | |
198 | return ret; | |
2017263e | 199 | |
ca191b13 | 200 | /* FIXME: the user of this interface might want more than just GGTT */ |
433e12f7 BG |
201 | switch (list) { |
202 | case ACTIVE_LIST: | |
267f0c90 | 203 | seq_puts(m, "Active:\n"); |
5cef07e1 | 204 | head = &vm->active_list; |
433e12f7 BG |
205 | break; |
206 | case INACTIVE_LIST: | |
267f0c90 | 207 | seq_puts(m, "Inactive:\n"); |
5cef07e1 | 208 | head = &vm->inactive_list; |
433e12f7 | 209 | break; |
433e12f7 | 210 | default: |
de227ef0 CW |
211 | mutex_unlock(&dev->struct_mutex); |
212 | return -EINVAL; | |
2017263e | 213 | } |
2017263e | 214 | |
8f2480fb | 215 | total_obj_size = total_gtt_size = count = 0; |
ca191b13 BW |
216 | list_for_each_entry(vma, head, mm_list) { |
217 | seq_printf(m, " "); | |
218 | describe_obj(m, vma->obj); | |
219 | seq_printf(m, "\n"); | |
220 | total_obj_size += vma->obj->base.size; | |
221 | total_gtt_size += vma->node.size; | |
8f2480fb | 222 | count++; |
2017263e | 223 | } |
de227ef0 | 224 | mutex_unlock(&dev->struct_mutex); |
5e118f41 | 225 | |
8f2480fb CW |
226 | seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n", |
227 | count, total_obj_size, total_gtt_size); | |
2017263e BG |
228 | return 0; |
229 | } | |
230 | ||
6d2b8885 CW |
231 | static int obj_rank_by_stolen(void *priv, |
232 | struct list_head *A, struct list_head *B) | |
233 | { | |
234 | struct drm_i915_gem_object *a = | |
b25cb2f8 | 235 | container_of(A, struct drm_i915_gem_object, obj_exec_link); |
6d2b8885 | 236 | struct drm_i915_gem_object *b = |
b25cb2f8 | 237 | container_of(B, struct drm_i915_gem_object, obj_exec_link); |
6d2b8885 CW |
238 | |
239 | return a->stolen->start - b->stolen->start; | |
240 | } | |
241 | ||
242 | static int i915_gem_stolen_list_info(struct seq_file *m, void *data) | |
243 | { | |
9f25d007 | 244 | struct drm_info_node *node = m->private; |
6d2b8885 CW |
245 | struct drm_device *dev = node->minor->dev; |
246 | struct drm_i915_private *dev_priv = dev->dev_private; | |
247 | struct drm_i915_gem_object *obj; | |
248 | size_t total_obj_size, total_gtt_size; | |
249 | LIST_HEAD(stolen); | |
250 | int count, ret; | |
251 | ||
252 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
253 | if (ret) | |
254 | return ret; | |
255 | ||
256 | total_obj_size = total_gtt_size = count = 0; | |
257 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { | |
258 | if (obj->stolen == NULL) | |
259 | continue; | |
260 | ||
b25cb2f8 | 261 | list_add(&obj->obj_exec_link, &stolen); |
6d2b8885 CW |
262 | |
263 | total_obj_size += obj->base.size; | |
264 | total_gtt_size += i915_gem_obj_ggtt_size(obj); | |
265 | count++; | |
266 | } | |
267 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) { | |
268 | if (obj->stolen == NULL) | |
269 | continue; | |
270 | ||
b25cb2f8 | 271 | list_add(&obj->obj_exec_link, &stolen); |
6d2b8885 CW |
272 | |
273 | total_obj_size += obj->base.size; | |
274 | count++; | |
275 | } | |
276 | list_sort(NULL, &stolen, obj_rank_by_stolen); | |
277 | seq_puts(m, "Stolen:\n"); | |
278 | while (!list_empty(&stolen)) { | |
b25cb2f8 | 279 | obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link); |
6d2b8885 CW |
280 | seq_puts(m, " "); |
281 | describe_obj(m, obj); | |
282 | seq_putc(m, '\n'); | |
b25cb2f8 | 283 | list_del_init(&obj->obj_exec_link); |
6d2b8885 CW |
284 | } |
285 | mutex_unlock(&dev->struct_mutex); | |
286 | ||
287 | seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n", | |
288 | count, total_obj_size, total_gtt_size); | |
289 | return 0; | |
290 | } | |
291 | ||
6299f992 CW |
292 | #define count_objects(list, member) do { \ |
293 | list_for_each_entry(obj, list, member) { \ | |
f343c5f6 | 294 | size += i915_gem_obj_ggtt_size(obj); \ |
6299f992 CW |
295 | ++count; \ |
296 | if (obj->map_and_fenceable) { \ | |
f343c5f6 | 297 | mappable_size += i915_gem_obj_ggtt_size(obj); \ |
6299f992 CW |
298 | ++mappable_count; \ |
299 | } \ | |
300 | } \ | |
0206e353 | 301 | } while (0) |
6299f992 | 302 | |
2db8e9d6 | 303 | struct file_stats { |
6313c204 | 304 | struct drm_i915_file_private *file_priv; |
2db8e9d6 | 305 | int count; |
c67a17e9 CW |
306 | size_t total, unbound; |
307 | size_t global, shared; | |
308 | size_t active, inactive; | |
2db8e9d6 CW |
309 | }; |
310 | ||
311 | static int per_file_stats(int id, void *ptr, void *data) | |
312 | { | |
313 | struct drm_i915_gem_object *obj = ptr; | |
314 | struct file_stats *stats = data; | |
6313c204 | 315 | struct i915_vma *vma; |
2db8e9d6 CW |
316 | |
317 | stats->count++; | |
318 | stats->total += obj->base.size; | |
319 | ||
c67a17e9 CW |
320 | if (obj->base.name || obj->base.dma_buf) |
321 | stats->shared += obj->base.size; | |
322 | ||
6313c204 CW |
323 | if (USES_FULL_PPGTT(obj->base.dev)) { |
324 | list_for_each_entry(vma, &obj->vma_list, vma_link) { | |
325 | struct i915_hw_ppgtt *ppgtt; | |
326 | ||
327 | if (!drm_mm_node_allocated(&vma->node)) | |
328 | continue; | |
329 | ||
330 | if (i915_is_ggtt(vma->vm)) { | |
331 | stats->global += obj->base.size; | |
332 | continue; | |
333 | } | |
334 | ||
335 | ppgtt = container_of(vma->vm, struct i915_hw_ppgtt, base); | |
4d884705 | 336 | if (ppgtt->file_priv != stats->file_priv) |
6313c204 CW |
337 | continue; |
338 | ||
41c52415 | 339 | if (obj->active) /* XXX per-vma statistic */ |
6313c204 CW |
340 | stats->active += obj->base.size; |
341 | else | |
342 | stats->inactive += obj->base.size; | |
343 | ||
344 | return 0; | |
345 | } | |
2db8e9d6 | 346 | } else { |
6313c204 CW |
347 | if (i915_gem_obj_ggtt_bound(obj)) { |
348 | stats->global += obj->base.size; | |
41c52415 | 349 | if (obj->active) |
6313c204 CW |
350 | stats->active += obj->base.size; |
351 | else | |
352 | stats->inactive += obj->base.size; | |
353 | return 0; | |
354 | } | |
2db8e9d6 CW |
355 | } |
356 | ||
6313c204 CW |
357 | if (!list_empty(&obj->global_list)) |
358 | stats->unbound += obj->base.size; | |
359 | ||
2db8e9d6 CW |
360 | return 0; |
361 | } | |
362 | ||
493018dc BV |
363 | #define print_file_stats(m, name, stats) \ |
364 | seq_printf(m, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu global, %zu shared, %zu unbound)\n", \ | |
365 | name, \ | |
366 | stats.count, \ | |
367 | stats.total, \ | |
368 | stats.active, \ | |
369 | stats.inactive, \ | |
370 | stats.global, \ | |
371 | stats.shared, \ | |
372 | stats.unbound) | |
373 | ||
374 | static void print_batch_pool_stats(struct seq_file *m, | |
375 | struct drm_i915_private *dev_priv) | |
376 | { | |
377 | struct drm_i915_gem_object *obj; | |
378 | struct file_stats stats; | |
379 | ||
380 | memset(&stats, 0, sizeof(stats)); | |
381 | ||
382 | list_for_each_entry(obj, | |
383 | &dev_priv->mm.batch_pool.cache_list, | |
384 | batch_pool_list) | |
385 | per_file_stats(0, obj, &stats); | |
386 | ||
387 | print_file_stats(m, "batch pool", stats); | |
388 | } | |
389 | ||
ca191b13 BW |
390 | #define count_vmas(list, member) do { \ |
391 | list_for_each_entry(vma, list, member) { \ | |
392 | size += i915_gem_obj_ggtt_size(vma->obj); \ | |
393 | ++count; \ | |
394 | if (vma->obj->map_and_fenceable) { \ | |
395 | mappable_size += i915_gem_obj_ggtt_size(vma->obj); \ | |
396 | ++mappable_count; \ | |
397 | } \ | |
398 | } \ | |
399 | } while (0) | |
400 | ||
401 | static int i915_gem_object_info(struct seq_file *m, void* data) | |
73aa808f | 402 | { |
9f25d007 | 403 | struct drm_info_node *node = m->private; |
73aa808f CW |
404 | struct drm_device *dev = node->minor->dev; |
405 | struct drm_i915_private *dev_priv = dev->dev_private; | |
b7abb714 CW |
406 | u32 count, mappable_count, purgeable_count; |
407 | size_t size, mappable_size, purgeable_size; | |
6299f992 | 408 | struct drm_i915_gem_object *obj; |
5cef07e1 | 409 | struct i915_address_space *vm = &dev_priv->gtt.base; |
2db8e9d6 | 410 | struct drm_file *file; |
ca191b13 | 411 | struct i915_vma *vma; |
73aa808f CW |
412 | int ret; |
413 | ||
414 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
415 | if (ret) | |
416 | return ret; | |
417 | ||
6299f992 CW |
418 | seq_printf(m, "%u objects, %zu bytes\n", |
419 | dev_priv->mm.object_count, | |
420 | dev_priv->mm.object_memory); | |
421 | ||
422 | size = count = mappable_size = mappable_count = 0; | |
35c20a60 | 423 | count_objects(&dev_priv->mm.bound_list, global_list); |
6299f992 CW |
424 | seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n", |
425 | count, mappable_count, size, mappable_size); | |
426 | ||
427 | size = count = mappable_size = mappable_count = 0; | |
ca191b13 | 428 | count_vmas(&vm->active_list, mm_list); |
6299f992 CW |
429 | seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n", |
430 | count, mappable_count, size, mappable_size); | |
431 | ||
6299f992 | 432 | size = count = mappable_size = mappable_count = 0; |
ca191b13 | 433 | count_vmas(&vm->inactive_list, mm_list); |
6299f992 CW |
434 | seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n", |
435 | count, mappable_count, size, mappable_size); | |
436 | ||
b7abb714 | 437 | size = count = purgeable_size = purgeable_count = 0; |
35c20a60 | 438 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) { |
6c085a72 | 439 | size += obj->base.size, ++count; |
b7abb714 CW |
440 | if (obj->madv == I915_MADV_DONTNEED) |
441 | purgeable_size += obj->base.size, ++purgeable_count; | |
442 | } | |
6c085a72 CW |
443 | seq_printf(m, "%u unbound objects, %zu bytes\n", count, size); |
444 | ||
6299f992 | 445 | size = count = mappable_size = mappable_count = 0; |
35c20a60 | 446 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
6299f992 | 447 | if (obj->fault_mappable) { |
f343c5f6 | 448 | size += i915_gem_obj_ggtt_size(obj); |
6299f992 CW |
449 | ++count; |
450 | } | |
451 | if (obj->pin_mappable) { | |
f343c5f6 | 452 | mappable_size += i915_gem_obj_ggtt_size(obj); |
6299f992 CW |
453 | ++mappable_count; |
454 | } | |
b7abb714 CW |
455 | if (obj->madv == I915_MADV_DONTNEED) { |
456 | purgeable_size += obj->base.size; | |
457 | ++purgeable_count; | |
458 | } | |
6299f992 | 459 | } |
b7abb714 CW |
460 | seq_printf(m, "%u purgeable objects, %zu bytes\n", |
461 | purgeable_count, purgeable_size); | |
6299f992 CW |
462 | seq_printf(m, "%u pinned mappable objects, %zu bytes\n", |
463 | mappable_count, mappable_size); | |
464 | seq_printf(m, "%u fault mappable objects, %zu bytes\n", | |
465 | count, size); | |
466 | ||
93d18799 | 467 | seq_printf(m, "%zu [%lu] gtt total\n", |
853ba5d2 BW |
468 | dev_priv->gtt.base.total, |
469 | dev_priv->gtt.mappable_end - dev_priv->gtt.base.start); | |
73aa808f | 470 | |
493018dc BV |
471 | seq_putc(m, '\n'); |
472 | print_batch_pool_stats(m, dev_priv); | |
473 | ||
267f0c90 | 474 | seq_putc(m, '\n'); |
2db8e9d6 CW |
475 | list_for_each_entry_reverse(file, &dev->filelist, lhead) { |
476 | struct file_stats stats; | |
3ec2f427 | 477 | struct task_struct *task; |
2db8e9d6 CW |
478 | |
479 | memset(&stats, 0, sizeof(stats)); | |
6313c204 | 480 | stats.file_priv = file->driver_priv; |
5b5ffff0 | 481 | spin_lock(&file->table_lock); |
2db8e9d6 | 482 | idr_for_each(&file->object_idr, per_file_stats, &stats); |
5b5ffff0 | 483 | spin_unlock(&file->table_lock); |
3ec2f427 TH |
484 | /* |
485 | * Although we have a valid reference on file->pid, that does | |
486 | * not guarantee that the task_struct who called get_pid() is | |
487 | * still alive (e.g. get_pid(current) => fork() => exit()). | |
488 | * Therefore, we need to protect this ->comm access using RCU. | |
489 | */ | |
490 | rcu_read_lock(); | |
491 | task = pid_task(file->pid, PIDTYPE_PID); | |
493018dc | 492 | print_file_stats(m, task ? task->comm : "<unknown>", stats); |
3ec2f427 | 493 | rcu_read_unlock(); |
2db8e9d6 CW |
494 | } |
495 | ||
73aa808f CW |
496 | mutex_unlock(&dev->struct_mutex); |
497 | ||
498 | return 0; | |
499 | } | |
500 | ||
aee56cff | 501 | static int i915_gem_gtt_info(struct seq_file *m, void *data) |
08c18323 | 502 | { |
9f25d007 | 503 | struct drm_info_node *node = m->private; |
08c18323 | 504 | struct drm_device *dev = node->minor->dev; |
1b50247a | 505 | uintptr_t list = (uintptr_t) node->info_ent->data; |
08c18323 CW |
506 | struct drm_i915_private *dev_priv = dev->dev_private; |
507 | struct drm_i915_gem_object *obj; | |
508 | size_t total_obj_size, total_gtt_size; | |
509 | int count, ret; | |
510 | ||
511 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
512 | if (ret) | |
513 | return ret; | |
514 | ||
515 | total_obj_size = total_gtt_size = count = 0; | |
35c20a60 | 516 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
d7f46fc4 | 517 | if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj)) |
1b50247a CW |
518 | continue; |
519 | ||
267f0c90 | 520 | seq_puts(m, " "); |
08c18323 | 521 | describe_obj(m, obj); |
267f0c90 | 522 | seq_putc(m, '\n'); |
08c18323 | 523 | total_obj_size += obj->base.size; |
f343c5f6 | 524 | total_gtt_size += i915_gem_obj_ggtt_size(obj); |
08c18323 CW |
525 | count++; |
526 | } | |
527 | ||
528 | mutex_unlock(&dev->struct_mutex); | |
529 | ||
530 | seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n", | |
531 | count, total_obj_size, total_gtt_size); | |
532 | ||
533 | return 0; | |
534 | } | |
535 | ||
4e5359cd SF |
536 | static int i915_gem_pageflip_info(struct seq_file *m, void *data) |
537 | { | |
9f25d007 | 538 | struct drm_info_node *node = m->private; |
4e5359cd | 539 | struct drm_device *dev = node->minor->dev; |
d6bbafa1 | 540 | struct drm_i915_private *dev_priv = dev->dev_private; |
4e5359cd | 541 | struct intel_crtc *crtc; |
8a270ebf DV |
542 | int ret; |
543 | ||
544 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
545 | if (ret) | |
546 | return ret; | |
4e5359cd | 547 | |
d3fcc808 | 548 | for_each_intel_crtc(dev, crtc) { |
9db4a9c7 JB |
549 | const char pipe = pipe_name(crtc->pipe); |
550 | const char plane = plane_name(crtc->plane); | |
4e5359cd SF |
551 | struct intel_unpin_work *work; |
552 | ||
5e2d7afc | 553 | spin_lock_irq(&dev->event_lock); |
4e5359cd SF |
554 | work = crtc->unpin_work; |
555 | if (work == NULL) { | |
9db4a9c7 | 556 | seq_printf(m, "No flip due on pipe %c (plane %c)\n", |
4e5359cd SF |
557 | pipe, plane); |
558 | } else { | |
d6bbafa1 CW |
559 | u32 addr; |
560 | ||
e7d841ca | 561 | if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { |
9db4a9c7 | 562 | seq_printf(m, "Flip queued on pipe %c (plane %c)\n", |
4e5359cd SF |
563 | pipe, plane); |
564 | } else { | |
9db4a9c7 | 565 | seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n", |
4e5359cd SF |
566 | pipe, plane); |
567 | } | |
3a8a946e DV |
568 | if (work->flip_queued_req) { |
569 | struct intel_engine_cs *ring = | |
570 | i915_gem_request_get_ring(work->flip_queued_req); | |
571 | ||
20e28fba | 572 | seq_printf(m, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n", |
3a8a946e | 573 | ring->name, |
f06cc1b9 | 574 | i915_gem_request_get_seqno(work->flip_queued_req), |
d6bbafa1 | 575 | dev_priv->next_seqno, |
3a8a946e | 576 | ring->get_seqno(ring, true), |
1b5a433a | 577 | i915_gem_request_completed(work->flip_queued_req, true)); |
d6bbafa1 CW |
578 | } else |
579 | seq_printf(m, "Flip not associated with any ring\n"); | |
580 | seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n", | |
581 | work->flip_queued_vblank, | |
582 | work->flip_ready_vblank, | |
583 | drm_vblank_count(dev, crtc->pipe)); | |
4e5359cd | 584 | if (work->enable_stall_check) |
267f0c90 | 585 | seq_puts(m, "Stall check enabled, "); |
4e5359cd | 586 | else |
267f0c90 | 587 | seq_puts(m, "Stall check waiting for page flip ioctl, "); |
e7d841ca | 588 | seq_printf(m, "%d prepares\n", atomic_read(&work->pending)); |
4e5359cd | 589 | |
d6bbafa1 CW |
590 | if (INTEL_INFO(dev)->gen >= 4) |
591 | addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane))); | |
592 | else | |
593 | addr = I915_READ(DSPADDR(crtc->plane)); | |
594 | seq_printf(m, "Current scanout address 0x%08x\n", addr); | |
595 | ||
4e5359cd | 596 | if (work->pending_flip_obj) { |
d6bbafa1 CW |
597 | seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset); |
598 | seq_printf(m, "MMIO update completed? %d\n", addr == work->gtt_offset); | |
4e5359cd SF |
599 | } |
600 | } | |
5e2d7afc | 601 | spin_unlock_irq(&dev->event_lock); |
4e5359cd SF |
602 | } |
603 | ||
8a270ebf DV |
604 | mutex_unlock(&dev->struct_mutex); |
605 | ||
4e5359cd SF |
606 | return 0; |
607 | } | |
608 | ||
493018dc BV |
609 | static int i915_gem_batch_pool_info(struct seq_file *m, void *data) |
610 | { | |
611 | struct drm_info_node *node = m->private; | |
612 | struct drm_device *dev = node->minor->dev; | |
613 | struct drm_i915_private *dev_priv = dev->dev_private; | |
614 | struct drm_i915_gem_object *obj; | |
615 | int count = 0; | |
616 | int ret; | |
617 | ||
618 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
619 | if (ret) | |
620 | return ret; | |
621 | ||
622 | seq_puts(m, "cache:\n"); | |
623 | list_for_each_entry(obj, | |
624 | &dev_priv->mm.batch_pool.cache_list, | |
625 | batch_pool_list) { | |
626 | seq_puts(m, " "); | |
627 | describe_obj(m, obj); | |
628 | seq_putc(m, '\n'); | |
629 | count++; | |
630 | } | |
631 | ||
632 | seq_printf(m, "total: %d\n", count); | |
633 | ||
634 | mutex_unlock(&dev->struct_mutex); | |
635 | ||
636 | return 0; | |
637 | } | |
638 | ||
2017263e BG |
639 | static int i915_gem_request_info(struct seq_file *m, void *data) |
640 | { | |
9f25d007 | 641 | struct drm_info_node *node = m->private; |
2017263e | 642 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 643 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 644 | struct intel_engine_cs *ring; |
2017263e | 645 | struct drm_i915_gem_request *gem_request; |
a2c7f6fd | 646 | int ret, count, i; |
de227ef0 CW |
647 | |
648 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
649 | if (ret) | |
650 | return ret; | |
2017263e | 651 | |
c2c347a9 | 652 | count = 0; |
a2c7f6fd CW |
653 | for_each_ring(ring, dev_priv, i) { |
654 | if (list_empty(&ring->request_list)) | |
655 | continue; | |
656 | ||
657 | seq_printf(m, "%s requests:\n", ring->name); | |
c2c347a9 | 658 | list_for_each_entry(gem_request, |
a2c7f6fd | 659 | &ring->request_list, |
c2c347a9 | 660 | list) { |
20e28fba | 661 | seq_printf(m, " %x @ %d\n", |
c2c347a9 CW |
662 | gem_request->seqno, |
663 | (int) (jiffies - gem_request->emitted_jiffies)); | |
664 | } | |
665 | count++; | |
2017263e | 666 | } |
de227ef0 CW |
667 | mutex_unlock(&dev->struct_mutex); |
668 | ||
c2c347a9 | 669 | if (count == 0) |
267f0c90 | 670 | seq_puts(m, "No requests\n"); |
c2c347a9 | 671 | |
2017263e BG |
672 | return 0; |
673 | } | |
674 | ||
b2223497 | 675 | static void i915_ring_seqno_info(struct seq_file *m, |
a4872ba6 | 676 | struct intel_engine_cs *ring) |
b2223497 CW |
677 | { |
678 | if (ring->get_seqno) { | |
20e28fba | 679 | seq_printf(m, "Current sequence (%s): %x\n", |
b2eadbc8 | 680 | ring->name, ring->get_seqno(ring, false)); |
b2223497 CW |
681 | } |
682 | } | |
683 | ||
2017263e BG |
684 | static int i915_gem_seqno_info(struct seq_file *m, void *data) |
685 | { | |
9f25d007 | 686 | struct drm_info_node *node = m->private; |
2017263e | 687 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 688 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 689 | struct intel_engine_cs *ring; |
1ec14ad3 | 690 | int ret, i; |
de227ef0 CW |
691 | |
692 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
693 | if (ret) | |
694 | return ret; | |
c8c8fb33 | 695 | intel_runtime_pm_get(dev_priv); |
2017263e | 696 | |
a2c7f6fd CW |
697 | for_each_ring(ring, dev_priv, i) |
698 | i915_ring_seqno_info(m, ring); | |
de227ef0 | 699 | |
c8c8fb33 | 700 | intel_runtime_pm_put(dev_priv); |
de227ef0 CW |
701 | mutex_unlock(&dev->struct_mutex); |
702 | ||
2017263e BG |
703 | return 0; |
704 | } | |
705 | ||
706 | ||
707 | static int i915_interrupt_info(struct seq_file *m, void *data) | |
708 | { | |
9f25d007 | 709 | struct drm_info_node *node = m->private; |
2017263e | 710 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 711 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 712 | struct intel_engine_cs *ring; |
9db4a9c7 | 713 | int ret, i, pipe; |
de227ef0 CW |
714 | |
715 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
716 | if (ret) | |
717 | return ret; | |
c8c8fb33 | 718 | intel_runtime_pm_get(dev_priv); |
2017263e | 719 | |
74e1ca8c | 720 | if (IS_CHERRYVIEW(dev)) { |
74e1ca8c VS |
721 | seq_printf(m, "Master Interrupt Control:\t%08x\n", |
722 | I915_READ(GEN8_MASTER_IRQ)); | |
723 | ||
724 | seq_printf(m, "Display IER:\t%08x\n", | |
725 | I915_READ(VLV_IER)); | |
726 | seq_printf(m, "Display IIR:\t%08x\n", | |
727 | I915_READ(VLV_IIR)); | |
728 | seq_printf(m, "Display IIR_RW:\t%08x\n", | |
729 | I915_READ(VLV_IIR_RW)); | |
730 | seq_printf(m, "Display IMR:\t%08x\n", | |
731 | I915_READ(VLV_IMR)); | |
055e393f | 732 | for_each_pipe(dev_priv, pipe) |
74e1ca8c VS |
733 | seq_printf(m, "Pipe %c stat:\t%08x\n", |
734 | pipe_name(pipe), | |
735 | I915_READ(PIPESTAT(pipe))); | |
736 | ||
737 | seq_printf(m, "Port hotplug:\t%08x\n", | |
738 | I915_READ(PORT_HOTPLUG_EN)); | |
739 | seq_printf(m, "DPFLIPSTAT:\t%08x\n", | |
740 | I915_READ(VLV_DPFLIPSTAT)); | |
741 | seq_printf(m, "DPINVGTT:\t%08x\n", | |
742 | I915_READ(DPINVGTT)); | |
743 | ||
744 | for (i = 0; i < 4; i++) { | |
745 | seq_printf(m, "GT Interrupt IMR %d:\t%08x\n", | |
746 | i, I915_READ(GEN8_GT_IMR(i))); | |
747 | seq_printf(m, "GT Interrupt IIR %d:\t%08x\n", | |
748 | i, I915_READ(GEN8_GT_IIR(i))); | |
749 | seq_printf(m, "GT Interrupt IER %d:\t%08x\n", | |
750 | i, I915_READ(GEN8_GT_IER(i))); | |
751 | } | |
752 | ||
753 | seq_printf(m, "PCU interrupt mask:\t%08x\n", | |
754 | I915_READ(GEN8_PCU_IMR)); | |
755 | seq_printf(m, "PCU interrupt identity:\t%08x\n", | |
756 | I915_READ(GEN8_PCU_IIR)); | |
757 | seq_printf(m, "PCU interrupt enable:\t%08x\n", | |
758 | I915_READ(GEN8_PCU_IER)); | |
759 | } else if (INTEL_INFO(dev)->gen >= 8) { | |
a123f157 BW |
760 | seq_printf(m, "Master Interrupt Control:\t%08x\n", |
761 | I915_READ(GEN8_MASTER_IRQ)); | |
762 | ||
763 | for (i = 0; i < 4; i++) { | |
764 | seq_printf(m, "GT Interrupt IMR %d:\t%08x\n", | |
765 | i, I915_READ(GEN8_GT_IMR(i))); | |
766 | seq_printf(m, "GT Interrupt IIR %d:\t%08x\n", | |
767 | i, I915_READ(GEN8_GT_IIR(i))); | |
768 | seq_printf(m, "GT Interrupt IER %d:\t%08x\n", | |
769 | i, I915_READ(GEN8_GT_IER(i))); | |
770 | } | |
771 | ||
055e393f | 772 | for_each_pipe(dev_priv, pipe) { |
f458ebbc | 773 | if (!intel_display_power_is_enabled(dev_priv, |
22c59960 PZ |
774 | POWER_DOMAIN_PIPE(pipe))) { |
775 | seq_printf(m, "Pipe %c power disabled\n", | |
776 | pipe_name(pipe)); | |
777 | continue; | |
778 | } | |
a123f157 | 779 | seq_printf(m, "Pipe %c IMR:\t%08x\n", |
07d27e20 DL |
780 | pipe_name(pipe), |
781 | I915_READ(GEN8_DE_PIPE_IMR(pipe))); | |
a123f157 | 782 | seq_printf(m, "Pipe %c IIR:\t%08x\n", |
07d27e20 DL |
783 | pipe_name(pipe), |
784 | I915_READ(GEN8_DE_PIPE_IIR(pipe))); | |
a123f157 | 785 | seq_printf(m, "Pipe %c IER:\t%08x\n", |
07d27e20 DL |
786 | pipe_name(pipe), |
787 | I915_READ(GEN8_DE_PIPE_IER(pipe))); | |
a123f157 BW |
788 | } |
789 | ||
790 | seq_printf(m, "Display Engine port interrupt mask:\t%08x\n", | |
791 | I915_READ(GEN8_DE_PORT_IMR)); | |
792 | seq_printf(m, "Display Engine port interrupt identity:\t%08x\n", | |
793 | I915_READ(GEN8_DE_PORT_IIR)); | |
794 | seq_printf(m, "Display Engine port interrupt enable:\t%08x\n", | |
795 | I915_READ(GEN8_DE_PORT_IER)); | |
796 | ||
797 | seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n", | |
798 | I915_READ(GEN8_DE_MISC_IMR)); | |
799 | seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n", | |
800 | I915_READ(GEN8_DE_MISC_IIR)); | |
801 | seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n", | |
802 | I915_READ(GEN8_DE_MISC_IER)); | |
803 | ||
804 | seq_printf(m, "PCU interrupt mask:\t%08x\n", | |
805 | I915_READ(GEN8_PCU_IMR)); | |
806 | seq_printf(m, "PCU interrupt identity:\t%08x\n", | |
807 | I915_READ(GEN8_PCU_IIR)); | |
808 | seq_printf(m, "PCU interrupt enable:\t%08x\n", | |
809 | I915_READ(GEN8_PCU_IER)); | |
810 | } else if (IS_VALLEYVIEW(dev)) { | |
7e231dbe JB |
811 | seq_printf(m, "Display IER:\t%08x\n", |
812 | I915_READ(VLV_IER)); | |
813 | seq_printf(m, "Display IIR:\t%08x\n", | |
814 | I915_READ(VLV_IIR)); | |
815 | seq_printf(m, "Display IIR_RW:\t%08x\n", | |
816 | I915_READ(VLV_IIR_RW)); | |
817 | seq_printf(m, "Display IMR:\t%08x\n", | |
818 | I915_READ(VLV_IMR)); | |
055e393f | 819 | for_each_pipe(dev_priv, pipe) |
7e231dbe JB |
820 | seq_printf(m, "Pipe %c stat:\t%08x\n", |
821 | pipe_name(pipe), | |
822 | I915_READ(PIPESTAT(pipe))); | |
823 | ||
824 | seq_printf(m, "Master IER:\t%08x\n", | |
825 | I915_READ(VLV_MASTER_IER)); | |
826 | ||
827 | seq_printf(m, "Render IER:\t%08x\n", | |
828 | I915_READ(GTIER)); | |
829 | seq_printf(m, "Render IIR:\t%08x\n", | |
830 | I915_READ(GTIIR)); | |
831 | seq_printf(m, "Render IMR:\t%08x\n", | |
832 | I915_READ(GTIMR)); | |
833 | ||
834 | seq_printf(m, "PM IER:\t\t%08x\n", | |
835 | I915_READ(GEN6_PMIER)); | |
836 | seq_printf(m, "PM IIR:\t\t%08x\n", | |
837 | I915_READ(GEN6_PMIIR)); | |
838 | seq_printf(m, "PM IMR:\t\t%08x\n", | |
839 | I915_READ(GEN6_PMIMR)); | |
840 | ||
841 | seq_printf(m, "Port hotplug:\t%08x\n", | |
842 | I915_READ(PORT_HOTPLUG_EN)); | |
843 | seq_printf(m, "DPFLIPSTAT:\t%08x\n", | |
844 | I915_READ(VLV_DPFLIPSTAT)); | |
845 | seq_printf(m, "DPINVGTT:\t%08x\n", | |
846 | I915_READ(DPINVGTT)); | |
847 | ||
848 | } else if (!HAS_PCH_SPLIT(dev)) { | |
5f6a1695 ZW |
849 | seq_printf(m, "Interrupt enable: %08x\n", |
850 | I915_READ(IER)); | |
851 | seq_printf(m, "Interrupt identity: %08x\n", | |
852 | I915_READ(IIR)); | |
853 | seq_printf(m, "Interrupt mask: %08x\n", | |
854 | I915_READ(IMR)); | |
055e393f | 855 | for_each_pipe(dev_priv, pipe) |
9db4a9c7 JB |
856 | seq_printf(m, "Pipe %c stat: %08x\n", |
857 | pipe_name(pipe), | |
858 | I915_READ(PIPESTAT(pipe))); | |
5f6a1695 ZW |
859 | } else { |
860 | seq_printf(m, "North Display Interrupt enable: %08x\n", | |
861 | I915_READ(DEIER)); | |
862 | seq_printf(m, "North Display Interrupt identity: %08x\n", | |
863 | I915_READ(DEIIR)); | |
864 | seq_printf(m, "North Display Interrupt mask: %08x\n", | |
865 | I915_READ(DEIMR)); | |
866 | seq_printf(m, "South Display Interrupt enable: %08x\n", | |
867 | I915_READ(SDEIER)); | |
868 | seq_printf(m, "South Display Interrupt identity: %08x\n", | |
869 | I915_READ(SDEIIR)); | |
870 | seq_printf(m, "South Display Interrupt mask: %08x\n", | |
871 | I915_READ(SDEIMR)); | |
872 | seq_printf(m, "Graphics Interrupt enable: %08x\n", | |
873 | I915_READ(GTIER)); | |
874 | seq_printf(m, "Graphics Interrupt identity: %08x\n", | |
875 | I915_READ(GTIIR)); | |
876 | seq_printf(m, "Graphics Interrupt mask: %08x\n", | |
877 | I915_READ(GTIMR)); | |
878 | } | |
a2c7f6fd | 879 | for_each_ring(ring, dev_priv, i) { |
a123f157 | 880 | if (INTEL_INFO(dev)->gen >= 6) { |
a2c7f6fd CW |
881 | seq_printf(m, |
882 | "Graphics Interrupt mask (%s): %08x\n", | |
883 | ring->name, I915_READ_IMR(ring)); | |
9862e600 | 884 | } |
a2c7f6fd | 885 | i915_ring_seqno_info(m, ring); |
9862e600 | 886 | } |
c8c8fb33 | 887 | intel_runtime_pm_put(dev_priv); |
de227ef0 CW |
888 | mutex_unlock(&dev->struct_mutex); |
889 | ||
2017263e BG |
890 | return 0; |
891 | } | |
892 | ||
a6172a80 CW |
893 | static int i915_gem_fence_regs_info(struct seq_file *m, void *data) |
894 | { | |
9f25d007 | 895 | struct drm_info_node *node = m->private; |
a6172a80 | 896 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 897 | struct drm_i915_private *dev_priv = dev->dev_private; |
de227ef0 CW |
898 | int i, ret; |
899 | ||
900 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
901 | if (ret) | |
902 | return ret; | |
a6172a80 CW |
903 | |
904 | seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start); | |
905 | seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs); | |
906 | for (i = 0; i < dev_priv->num_fence_regs; i++) { | |
05394f39 | 907 | struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj; |
a6172a80 | 908 | |
6c085a72 CW |
909 | seq_printf(m, "Fence %d, pin count = %d, object = ", |
910 | i, dev_priv->fence_regs[i].pin_count); | |
c2c347a9 | 911 | if (obj == NULL) |
267f0c90 | 912 | seq_puts(m, "unused"); |
c2c347a9 | 913 | else |
05394f39 | 914 | describe_obj(m, obj); |
267f0c90 | 915 | seq_putc(m, '\n'); |
a6172a80 CW |
916 | } |
917 | ||
05394f39 | 918 | mutex_unlock(&dev->struct_mutex); |
a6172a80 CW |
919 | return 0; |
920 | } | |
921 | ||
2017263e BG |
922 | static int i915_hws_info(struct seq_file *m, void *data) |
923 | { | |
9f25d007 | 924 | struct drm_info_node *node = m->private; |
2017263e | 925 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 926 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 927 | struct intel_engine_cs *ring; |
1a240d4d | 928 | const u32 *hws; |
4066c0ae CW |
929 | int i; |
930 | ||
1ec14ad3 | 931 | ring = &dev_priv->ring[(uintptr_t)node->info_ent->data]; |
1a240d4d | 932 | hws = ring->status_page.page_addr; |
2017263e BG |
933 | if (hws == NULL) |
934 | return 0; | |
935 | ||
936 | for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) { | |
937 | seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n", | |
938 | i * 4, | |
939 | hws[i], hws[i + 1], hws[i + 2], hws[i + 3]); | |
940 | } | |
941 | return 0; | |
942 | } | |
943 | ||
d5442303 DV |
944 | static ssize_t |
945 | i915_error_state_write(struct file *filp, | |
946 | const char __user *ubuf, | |
947 | size_t cnt, | |
948 | loff_t *ppos) | |
949 | { | |
edc3d884 | 950 | struct i915_error_state_file_priv *error_priv = filp->private_data; |
d5442303 | 951 | struct drm_device *dev = error_priv->dev; |
22bcfc6a | 952 | int ret; |
d5442303 DV |
953 | |
954 | DRM_DEBUG_DRIVER("Resetting error state\n"); | |
955 | ||
22bcfc6a DV |
956 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
957 | if (ret) | |
958 | return ret; | |
959 | ||
d5442303 DV |
960 | i915_destroy_error_state(dev); |
961 | mutex_unlock(&dev->struct_mutex); | |
962 | ||
963 | return cnt; | |
964 | } | |
965 | ||
966 | static int i915_error_state_open(struct inode *inode, struct file *file) | |
967 | { | |
968 | struct drm_device *dev = inode->i_private; | |
d5442303 | 969 | struct i915_error_state_file_priv *error_priv; |
d5442303 DV |
970 | |
971 | error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL); | |
972 | if (!error_priv) | |
973 | return -ENOMEM; | |
974 | ||
975 | error_priv->dev = dev; | |
976 | ||
95d5bfb3 | 977 | i915_error_state_get(dev, error_priv); |
d5442303 | 978 | |
edc3d884 MK |
979 | file->private_data = error_priv; |
980 | ||
981 | return 0; | |
d5442303 DV |
982 | } |
983 | ||
984 | static int i915_error_state_release(struct inode *inode, struct file *file) | |
985 | { | |
edc3d884 | 986 | struct i915_error_state_file_priv *error_priv = file->private_data; |
d5442303 | 987 | |
95d5bfb3 | 988 | i915_error_state_put(error_priv); |
d5442303 DV |
989 | kfree(error_priv); |
990 | ||
edc3d884 MK |
991 | return 0; |
992 | } | |
993 | ||
4dc955f7 MK |
994 | static ssize_t i915_error_state_read(struct file *file, char __user *userbuf, |
995 | size_t count, loff_t *pos) | |
996 | { | |
997 | struct i915_error_state_file_priv *error_priv = file->private_data; | |
998 | struct drm_i915_error_state_buf error_str; | |
999 | loff_t tmp_pos = 0; | |
1000 | ssize_t ret_count = 0; | |
1001 | int ret; | |
1002 | ||
0a4cd7c8 | 1003 | ret = i915_error_state_buf_init(&error_str, to_i915(error_priv->dev), count, *pos); |
4dc955f7 MK |
1004 | if (ret) |
1005 | return ret; | |
edc3d884 | 1006 | |
fc16b48b | 1007 | ret = i915_error_state_to_str(&error_str, error_priv); |
edc3d884 MK |
1008 | if (ret) |
1009 | goto out; | |
1010 | ||
edc3d884 MK |
1011 | ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos, |
1012 | error_str.buf, | |
1013 | error_str.bytes); | |
1014 | ||
1015 | if (ret_count < 0) | |
1016 | ret = ret_count; | |
1017 | else | |
1018 | *pos = error_str.start + ret_count; | |
1019 | out: | |
4dc955f7 | 1020 | i915_error_state_buf_release(&error_str); |
edc3d884 | 1021 | return ret ?: ret_count; |
d5442303 DV |
1022 | } |
1023 | ||
1024 | static const struct file_operations i915_error_state_fops = { | |
1025 | .owner = THIS_MODULE, | |
1026 | .open = i915_error_state_open, | |
edc3d884 | 1027 | .read = i915_error_state_read, |
d5442303 DV |
1028 | .write = i915_error_state_write, |
1029 | .llseek = default_llseek, | |
1030 | .release = i915_error_state_release, | |
1031 | }; | |
1032 | ||
647416f9 KC |
1033 | static int |
1034 | i915_next_seqno_get(void *data, u64 *val) | |
40633219 | 1035 | { |
647416f9 | 1036 | struct drm_device *dev = data; |
e277a1f8 | 1037 | struct drm_i915_private *dev_priv = dev->dev_private; |
40633219 MK |
1038 | int ret; |
1039 | ||
1040 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1041 | if (ret) | |
1042 | return ret; | |
1043 | ||
647416f9 | 1044 | *val = dev_priv->next_seqno; |
40633219 MK |
1045 | mutex_unlock(&dev->struct_mutex); |
1046 | ||
647416f9 | 1047 | return 0; |
40633219 MK |
1048 | } |
1049 | ||
647416f9 KC |
1050 | static int |
1051 | i915_next_seqno_set(void *data, u64 val) | |
1052 | { | |
1053 | struct drm_device *dev = data; | |
40633219 MK |
1054 | int ret; |
1055 | ||
40633219 MK |
1056 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1057 | if (ret) | |
1058 | return ret; | |
1059 | ||
e94fbaa8 | 1060 | ret = i915_gem_set_seqno(dev, val); |
40633219 MK |
1061 | mutex_unlock(&dev->struct_mutex); |
1062 | ||
647416f9 | 1063 | return ret; |
40633219 MK |
1064 | } |
1065 | ||
647416f9 KC |
1066 | DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops, |
1067 | i915_next_seqno_get, i915_next_seqno_set, | |
3a3b4f98 | 1068 | "0x%llx\n"); |
40633219 | 1069 | |
adb4bd12 | 1070 | static int i915_frequency_info(struct seq_file *m, void *unused) |
f97108d1 | 1071 | { |
9f25d007 | 1072 | struct drm_info_node *node = m->private; |
f97108d1 | 1073 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 1074 | struct drm_i915_private *dev_priv = dev->dev_private; |
c8c8fb33 PZ |
1075 | int ret = 0; |
1076 | ||
1077 | intel_runtime_pm_get(dev_priv); | |
3b8d8d91 | 1078 | |
5c9669ce TR |
1079 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
1080 | ||
3b8d8d91 JB |
1081 | if (IS_GEN5(dev)) { |
1082 | u16 rgvswctl = I915_READ16(MEMSWCTL); | |
1083 | u16 rgvstat = I915_READ16(MEMSTAT_ILK); | |
1084 | ||
1085 | seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf); | |
1086 | seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f); | |
1087 | seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >> | |
1088 | MEMSTAT_VID_SHIFT); | |
1089 | seq_printf(m, "Current P-state: %d\n", | |
1090 | (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT); | |
daa3afb2 TR |
1091 | } else if (IS_GEN6(dev) || (IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) || |
1092 | IS_BROADWELL(dev)) { | |
3b8d8d91 JB |
1093 | u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS); |
1094 | u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS); | |
1095 | u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); | |
0d8f9491 | 1096 | u32 rpmodectl, rpinclimit, rpdeclimit; |
8e8c06cd | 1097 | u32 rpstat, cagf, reqf; |
ccab5c82 JB |
1098 | u32 rpupei, rpcurup, rpprevup; |
1099 | u32 rpdownei, rpcurdown, rpprevdown; | |
9dd3c605 | 1100 | u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask; |
3b8d8d91 JB |
1101 | int max_freq; |
1102 | ||
1103 | /* RPSTAT1 is in the GT power well */ | |
d1ebd816 BW |
1104 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1105 | if (ret) | |
c8c8fb33 | 1106 | goto out; |
d1ebd816 | 1107 | |
59bad947 | 1108 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
3b8d8d91 | 1109 | |
8e8c06cd CW |
1110 | reqf = I915_READ(GEN6_RPNSWREQ); |
1111 | reqf &= ~GEN6_TURBO_DISABLE; | |
daa3afb2 | 1112 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
8e8c06cd CW |
1113 | reqf >>= 24; |
1114 | else | |
1115 | reqf >>= 25; | |
7c59a9c1 | 1116 | reqf = intel_gpu_freq(dev_priv, reqf); |
8e8c06cd | 1117 | |
0d8f9491 CW |
1118 | rpmodectl = I915_READ(GEN6_RP_CONTROL); |
1119 | rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD); | |
1120 | rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD); | |
1121 | ||
ccab5c82 JB |
1122 | rpstat = I915_READ(GEN6_RPSTAT1); |
1123 | rpupei = I915_READ(GEN6_RP_CUR_UP_EI); | |
1124 | rpcurup = I915_READ(GEN6_RP_CUR_UP); | |
1125 | rpprevup = I915_READ(GEN6_RP_PREV_UP); | |
1126 | rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI); | |
1127 | rpcurdown = I915_READ(GEN6_RP_CUR_DOWN); | |
1128 | rpprevdown = I915_READ(GEN6_RP_PREV_DOWN); | |
daa3afb2 | 1129 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
f82855d3 BW |
1130 | cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT; |
1131 | else | |
1132 | cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT; | |
7c59a9c1 | 1133 | cagf = intel_gpu_freq(dev_priv, cagf); |
ccab5c82 | 1134 | |
59bad947 | 1135 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
d1ebd816 BW |
1136 | mutex_unlock(&dev->struct_mutex); |
1137 | ||
9dd3c605 PZ |
1138 | if (IS_GEN6(dev) || IS_GEN7(dev)) { |
1139 | pm_ier = I915_READ(GEN6_PMIER); | |
1140 | pm_imr = I915_READ(GEN6_PMIMR); | |
1141 | pm_isr = I915_READ(GEN6_PMISR); | |
1142 | pm_iir = I915_READ(GEN6_PMIIR); | |
1143 | pm_mask = I915_READ(GEN6_PMINTRMSK); | |
1144 | } else { | |
1145 | pm_ier = I915_READ(GEN8_GT_IER(2)); | |
1146 | pm_imr = I915_READ(GEN8_GT_IMR(2)); | |
1147 | pm_isr = I915_READ(GEN8_GT_ISR(2)); | |
1148 | pm_iir = I915_READ(GEN8_GT_IIR(2)); | |
1149 | pm_mask = I915_READ(GEN6_PMINTRMSK); | |
1150 | } | |
0d8f9491 | 1151 | seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n", |
9dd3c605 | 1152 | pm_ier, pm_imr, pm_isr, pm_iir, pm_mask); |
3b8d8d91 | 1153 | seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status); |
3b8d8d91 JB |
1154 | seq_printf(m, "Render p-state ratio: %d\n", |
1155 | (gt_perf_status & 0xff00) >> 8); | |
1156 | seq_printf(m, "Render p-state VID: %d\n", | |
1157 | gt_perf_status & 0xff); | |
1158 | seq_printf(m, "Render p-state limit: %d\n", | |
1159 | rp_state_limits & 0xff); | |
0d8f9491 CW |
1160 | seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat); |
1161 | seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl); | |
1162 | seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit); | |
1163 | seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit); | |
8e8c06cd | 1164 | seq_printf(m, "RPNSWREQ: %dMHz\n", reqf); |
f82855d3 | 1165 | seq_printf(m, "CAGF: %dMHz\n", cagf); |
ccab5c82 JB |
1166 | seq_printf(m, "RP CUR UP EI: %dus\n", rpupei & |
1167 | GEN6_CURICONT_MASK); | |
1168 | seq_printf(m, "RP CUR UP: %dus\n", rpcurup & | |
1169 | GEN6_CURBSYTAVG_MASK); | |
1170 | seq_printf(m, "RP PREV UP: %dus\n", rpprevup & | |
1171 | GEN6_CURBSYTAVG_MASK); | |
1172 | seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei & | |
1173 | GEN6_CURIAVG_MASK); | |
1174 | seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown & | |
1175 | GEN6_CURBSYTAVG_MASK); | |
1176 | seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown & | |
1177 | GEN6_CURBSYTAVG_MASK); | |
3b8d8d91 JB |
1178 | |
1179 | max_freq = (rp_state_cap & 0xff0000) >> 16; | |
1180 | seq_printf(m, "Lowest (RPN) frequency: %dMHz\n", | |
7c59a9c1 | 1181 | intel_gpu_freq(dev_priv, max_freq)); |
3b8d8d91 JB |
1182 | |
1183 | max_freq = (rp_state_cap & 0xff00) >> 8; | |
1184 | seq_printf(m, "Nominal (RP1) frequency: %dMHz\n", | |
7c59a9c1 | 1185 | intel_gpu_freq(dev_priv, max_freq)); |
3b8d8d91 JB |
1186 | |
1187 | max_freq = rp_state_cap & 0xff; | |
1188 | seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n", | |
7c59a9c1 | 1189 | intel_gpu_freq(dev_priv, max_freq)); |
31c77388 BW |
1190 | |
1191 | seq_printf(m, "Max overclocked frequency: %dMHz\n", | |
7c59a9c1 | 1192 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); |
0a073b84 | 1193 | } else if (IS_VALLEYVIEW(dev)) { |
03af2045 | 1194 | u32 freq_sts; |
0a073b84 | 1195 | |
259bd5d4 | 1196 | mutex_lock(&dev_priv->rps.hw_lock); |
64936258 | 1197 | freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); |
0a073b84 JB |
1198 | seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts); |
1199 | seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq); | |
1200 | ||
0a073b84 | 1201 | seq_printf(m, "max GPU freq: %d MHz\n", |
7c59a9c1 | 1202 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); |
0a073b84 | 1203 | |
0a073b84 | 1204 | seq_printf(m, "min GPU freq: %d MHz\n", |
7c59a9c1 | 1205 | intel_gpu_freq(dev_priv, dev_priv->rps.min_freq)); |
03af2045 | 1206 | |
7c59a9c1 VS |
1207 | seq_printf(m, |
1208 | "efficient (RPe) frequency: %d MHz\n", | |
1209 | intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq)); | |
0a073b84 JB |
1210 | |
1211 | seq_printf(m, "current GPU freq: %d MHz\n", | |
7c59a9c1 | 1212 | intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff)); |
259bd5d4 | 1213 | mutex_unlock(&dev_priv->rps.hw_lock); |
3b8d8d91 | 1214 | } else { |
267f0c90 | 1215 | seq_puts(m, "no P-state info available\n"); |
3b8d8d91 | 1216 | } |
f97108d1 | 1217 | |
c8c8fb33 PZ |
1218 | out: |
1219 | intel_runtime_pm_put(dev_priv); | |
1220 | return ret; | |
f97108d1 JB |
1221 | } |
1222 | ||
f654449a CW |
1223 | static int i915_hangcheck_info(struct seq_file *m, void *unused) |
1224 | { | |
1225 | struct drm_info_node *node = m->private; | |
1226 | struct drm_i915_private *dev_priv = to_i915(node->minor->dev); | |
1227 | struct intel_engine_cs *ring; | |
1228 | int i; | |
1229 | ||
1230 | if (!i915.enable_hangcheck) { | |
1231 | seq_printf(m, "Hangcheck disabled\n"); | |
1232 | return 0; | |
1233 | } | |
1234 | ||
1235 | if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) { | |
1236 | seq_printf(m, "Hangcheck active, fires in %dms\n", | |
1237 | jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires - | |
1238 | jiffies)); | |
1239 | } else | |
1240 | seq_printf(m, "Hangcheck inactive\n"); | |
1241 | ||
1242 | for_each_ring(ring, dev_priv, i) { | |
1243 | seq_printf(m, "%s:\n", ring->name); | |
1244 | seq_printf(m, "\tseqno = %x [current %x]\n", | |
1245 | ring->hangcheck.seqno, ring->get_seqno(ring, false)); | |
1246 | seq_printf(m, "\taction = %d\n", ring->hangcheck.action); | |
1247 | seq_printf(m, "\tscore = %d\n", ring->hangcheck.score); | |
1248 | seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n", | |
1249 | (long long)ring->hangcheck.acthd, | |
1250 | (long long)intel_ring_get_active_head(ring)); | |
1251 | seq_printf(m, "\tmax ACTHD = 0x%08llx\n", | |
1252 | (long long)ring->hangcheck.max_acthd); | |
1253 | } | |
1254 | ||
1255 | return 0; | |
1256 | } | |
1257 | ||
4d85529d | 1258 | static int ironlake_drpc_info(struct seq_file *m) |
f97108d1 | 1259 | { |
9f25d007 | 1260 | struct drm_info_node *node = m->private; |
f97108d1 | 1261 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 1262 | struct drm_i915_private *dev_priv = dev->dev_private; |
616fdb5a BW |
1263 | u32 rgvmodectl, rstdbyctl; |
1264 | u16 crstandvid; | |
1265 | int ret; | |
1266 | ||
1267 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1268 | if (ret) | |
1269 | return ret; | |
c8c8fb33 | 1270 | intel_runtime_pm_get(dev_priv); |
616fdb5a BW |
1271 | |
1272 | rgvmodectl = I915_READ(MEMMODECTL); | |
1273 | rstdbyctl = I915_READ(RSTDBYCTL); | |
1274 | crstandvid = I915_READ16(CRSTANDVID); | |
1275 | ||
c8c8fb33 | 1276 | intel_runtime_pm_put(dev_priv); |
616fdb5a | 1277 | mutex_unlock(&dev->struct_mutex); |
f97108d1 JB |
1278 | |
1279 | seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ? | |
1280 | "yes" : "no"); | |
1281 | seq_printf(m, "Boost freq: %d\n", | |
1282 | (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >> | |
1283 | MEMMODE_BOOST_FREQ_SHIFT); | |
1284 | seq_printf(m, "HW control enabled: %s\n", | |
1285 | rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no"); | |
1286 | seq_printf(m, "SW control enabled: %s\n", | |
1287 | rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no"); | |
1288 | seq_printf(m, "Gated voltage change: %s\n", | |
1289 | rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no"); | |
1290 | seq_printf(m, "Starting frequency: P%d\n", | |
1291 | (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT); | |
7648fa99 | 1292 | seq_printf(m, "Max P-state: P%d\n", |
f97108d1 | 1293 | (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT); |
7648fa99 JB |
1294 | seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK)); |
1295 | seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f)); | |
1296 | seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f)); | |
1297 | seq_printf(m, "Render standby enabled: %s\n", | |
1298 | (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes"); | |
267f0c90 | 1299 | seq_puts(m, "Current RS state: "); |
88271da3 JB |
1300 | switch (rstdbyctl & RSX_STATUS_MASK) { |
1301 | case RSX_STATUS_ON: | |
267f0c90 | 1302 | seq_puts(m, "on\n"); |
88271da3 JB |
1303 | break; |
1304 | case RSX_STATUS_RC1: | |
267f0c90 | 1305 | seq_puts(m, "RC1\n"); |
88271da3 JB |
1306 | break; |
1307 | case RSX_STATUS_RC1E: | |
267f0c90 | 1308 | seq_puts(m, "RC1E\n"); |
88271da3 JB |
1309 | break; |
1310 | case RSX_STATUS_RS1: | |
267f0c90 | 1311 | seq_puts(m, "RS1\n"); |
88271da3 JB |
1312 | break; |
1313 | case RSX_STATUS_RS2: | |
267f0c90 | 1314 | seq_puts(m, "RS2 (RC6)\n"); |
88271da3 JB |
1315 | break; |
1316 | case RSX_STATUS_RS3: | |
267f0c90 | 1317 | seq_puts(m, "RC3 (RC6+)\n"); |
88271da3 JB |
1318 | break; |
1319 | default: | |
267f0c90 | 1320 | seq_puts(m, "unknown\n"); |
88271da3 JB |
1321 | break; |
1322 | } | |
f97108d1 JB |
1323 | |
1324 | return 0; | |
1325 | } | |
1326 | ||
f65367b5 | 1327 | static int i915_forcewake_domains(struct seq_file *m, void *data) |
669ab5aa | 1328 | { |
b2cff0db CW |
1329 | struct drm_info_node *node = m->private; |
1330 | struct drm_device *dev = node->minor->dev; | |
1331 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1332 | struct intel_uncore_forcewake_domain *fw_domain; | |
b2cff0db CW |
1333 | int i; |
1334 | ||
1335 | spin_lock_irq(&dev_priv->uncore.lock); | |
1336 | for_each_fw_domain(fw_domain, dev_priv, i) { | |
1337 | seq_printf(m, "%s.wake_count = %u\n", | |
05a2fb15 | 1338 | intel_uncore_forcewake_domain_to_str(i), |
b2cff0db CW |
1339 | fw_domain->wake_count); |
1340 | } | |
1341 | spin_unlock_irq(&dev_priv->uncore.lock); | |
669ab5aa | 1342 | |
b2cff0db CW |
1343 | return 0; |
1344 | } | |
1345 | ||
1346 | static int vlv_drpc_info(struct seq_file *m) | |
1347 | { | |
9f25d007 | 1348 | struct drm_info_node *node = m->private; |
669ab5aa D |
1349 | struct drm_device *dev = node->minor->dev; |
1350 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6b312cd3 | 1351 | u32 rpmodectl1, rcctl1, pw_status; |
669ab5aa | 1352 | |
d46c0517 ID |
1353 | intel_runtime_pm_get(dev_priv); |
1354 | ||
6b312cd3 | 1355 | pw_status = I915_READ(VLV_GTLC_PW_STATUS); |
669ab5aa D |
1356 | rpmodectl1 = I915_READ(GEN6_RP_CONTROL); |
1357 | rcctl1 = I915_READ(GEN6_RC_CONTROL); | |
1358 | ||
d46c0517 ID |
1359 | intel_runtime_pm_put(dev_priv); |
1360 | ||
669ab5aa D |
1361 | seq_printf(m, "Video Turbo Mode: %s\n", |
1362 | yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO)); | |
1363 | seq_printf(m, "Turbo enabled: %s\n", | |
1364 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); | |
1365 | seq_printf(m, "HW control enabled: %s\n", | |
1366 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); | |
1367 | seq_printf(m, "SW control enabled: %s\n", | |
1368 | yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) == | |
1369 | GEN6_RP_MEDIA_SW_MODE)); | |
1370 | seq_printf(m, "RC6 Enabled: %s\n", | |
1371 | yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE | | |
1372 | GEN6_RC_CTL_EI_MODE(1)))); | |
1373 | seq_printf(m, "Render Power Well: %s\n", | |
6b312cd3 | 1374 | (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down"); |
669ab5aa | 1375 | seq_printf(m, "Media Power Well: %s\n", |
6b312cd3 | 1376 | (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down"); |
669ab5aa | 1377 | |
9cc19be5 ID |
1378 | seq_printf(m, "Render RC6 residency since boot: %u\n", |
1379 | I915_READ(VLV_GT_RENDER_RC6)); | |
1380 | seq_printf(m, "Media RC6 residency since boot: %u\n", | |
1381 | I915_READ(VLV_GT_MEDIA_RC6)); | |
1382 | ||
f65367b5 | 1383 | return i915_forcewake_domains(m, NULL); |
669ab5aa D |
1384 | } |
1385 | ||
4d85529d BW |
1386 | static int gen6_drpc_info(struct seq_file *m) |
1387 | { | |
9f25d007 | 1388 | struct drm_info_node *node = m->private; |
4d85529d BW |
1389 | struct drm_device *dev = node->minor->dev; |
1390 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ecd8faea | 1391 | u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0; |
93b525dc | 1392 | unsigned forcewake_count; |
aee56cff | 1393 | int count = 0, ret; |
4d85529d BW |
1394 | |
1395 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1396 | if (ret) | |
1397 | return ret; | |
c8c8fb33 | 1398 | intel_runtime_pm_get(dev_priv); |
4d85529d | 1399 | |
907b28c5 | 1400 | spin_lock_irq(&dev_priv->uncore.lock); |
b2cff0db | 1401 | forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count; |
907b28c5 | 1402 | spin_unlock_irq(&dev_priv->uncore.lock); |
93b525dc DV |
1403 | |
1404 | if (forcewake_count) { | |
267f0c90 DL |
1405 | seq_puts(m, "RC information inaccurate because somebody " |
1406 | "holds a forcewake reference \n"); | |
4d85529d BW |
1407 | } else { |
1408 | /* NB: we cannot use forcewake, else we read the wrong values */ | |
1409 | while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1)) | |
1410 | udelay(10); | |
1411 | seq_printf(m, "RC information accurate: %s\n", yesno(count < 51)); | |
1412 | } | |
1413 | ||
1414 | gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS); | |
ed71f1b4 | 1415 | trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true); |
4d85529d BW |
1416 | |
1417 | rpmodectl1 = I915_READ(GEN6_RP_CONTROL); | |
1418 | rcctl1 = I915_READ(GEN6_RC_CONTROL); | |
1419 | mutex_unlock(&dev->struct_mutex); | |
44cbd338 BW |
1420 | mutex_lock(&dev_priv->rps.hw_lock); |
1421 | sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids); | |
1422 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4d85529d | 1423 | |
c8c8fb33 PZ |
1424 | intel_runtime_pm_put(dev_priv); |
1425 | ||
4d85529d BW |
1426 | seq_printf(m, "Video Turbo Mode: %s\n", |
1427 | yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO)); | |
1428 | seq_printf(m, "HW control enabled: %s\n", | |
1429 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); | |
1430 | seq_printf(m, "SW control enabled: %s\n", | |
1431 | yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) == | |
1432 | GEN6_RP_MEDIA_SW_MODE)); | |
fff24e21 | 1433 | seq_printf(m, "RC1e Enabled: %s\n", |
4d85529d BW |
1434 | yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE)); |
1435 | seq_printf(m, "RC6 Enabled: %s\n", | |
1436 | yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE)); | |
1437 | seq_printf(m, "Deep RC6 Enabled: %s\n", | |
1438 | yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE)); | |
1439 | seq_printf(m, "Deepest RC6 Enabled: %s\n", | |
1440 | yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE)); | |
267f0c90 | 1441 | seq_puts(m, "Current RC state: "); |
4d85529d BW |
1442 | switch (gt_core_status & GEN6_RCn_MASK) { |
1443 | case GEN6_RC0: | |
1444 | if (gt_core_status & GEN6_CORE_CPD_STATE_MASK) | |
267f0c90 | 1445 | seq_puts(m, "Core Power Down\n"); |
4d85529d | 1446 | else |
267f0c90 | 1447 | seq_puts(m, "on\n"); |
4d85529d BW |
1448 | break; |
1449 | case GEN6_RC3: | |
267f0c90 | 1450 | seq_puts(m, "RC3\n"); |
4d85529d BW |
1451 | break; |
1452 | case GEN6_RC6: | |
267f0c90 | 1453 | seq_puts(m, "RC6\n"); |
4d85529d BW |
1454 | break; |
1455 | case GEN6_RC7: | |
267f0c90 | 1456 | seq_puts(m, "RC7\n"); |
4d85529d BW |
1457 | break; |
1458 | default: | |
267f0c90 | 1459 | seq_puts(m, "Unknown\n"); |
4d85529d BW |
1460 | break; |
1461 | } | |
1462 | ||
1463 | seq_printf(m, "Core Power Down: %s\n", | |
1464 | yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK)); | |
cce66a28 BW |
1465 | |
1466 | /* Not exactly sure what this is */ | |
1467 | seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n", | |
1468 | I915_READ(GEN6_GT_GFX_RC6_LOCKED)); | |
1469 | seq_printf(m, "RC6 residency since boot: %u\n", | |
1470 | I915_READ(GEN6_GT_GFX_RC6)); | |
1471 | seq_printf(m, "RC6+ residency since boot: %u\n", | |
1472 | I915_READ(GEN6_GT_GFX_RC6p)); | |
1473 | seq_printf(m, "RC6++ residency since boot: %u\n", | |
1474 | I915_READ(GEN6_GT_GFX_RC6pp)); | |
1475 | ||
ecd8faea BW |
1476 | seq_printf(m, "RC6 voltage: %dmV\n", |
1477 | GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff))); | |
1478 | seq_printf(m, "RC6+ voltage: %dmV\n", | |
1479 | GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff))); | |
1480 | seq_printf(m, "RC6++ voltage: %dmV\n", | |
1481 | GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff))); | |
4d85529d BW |
1482 | return 0; |
1483 | } | |
1484 | ||
1485 | static int i915_drpc_info(struct seq_file *m, void *unused) | |
1486 | { | |
9f25d007 | 1487 | struct drm_info_node *node = m->private; |
4d85529d BW |
1488 | struct drm_device *dev = node->minor->dev; |
1489 | ||
669ab5aa D |
1490 | if (IS_VALLEYVIEW(dev)) |
1491 | return vlv_drpc_info(m); | |
ac66cf4b | 1492 | else if (INTEL_INFO(dev)->gen >= 6) |
4d85529d BW |
1493 | return gen6_drpc_info(m); |
1494 | else | |
1495 | return ironlake_drpc_info(m); | |
1496 | } | |
1497 | ||
b5e50c3f JB |
1498 | static int i915_fbc_status(struct seq_file *m, void *unused) |
1499 | { | |
9f25d007 | 1500 | struct drm_info_node *node = m->private; |
b5e50c3f | 1501 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 1502 | struct drm_i915_private *dev_priv = dev->dev_private; |
b5e50c3f | 1503 | |
3a77c4c4 | 1504 | if (!HAS_FBC(dev)) { |
267f0c90 | 1505 | seq_puts(m, "FBC unsupported on this chipset\n"); |
b5e50c3f JB |
1506 | return 0; |
1507 | } | |
1508 | ||
36623ef8 PZ |
1509 | intel_runtime_pm_get(dev_priv); |
1510 | ||
ee5382ae | 1511 | if (intel_fbc_enabled(dev)) { |
267f0c90 | 1512 | seq_puts(m, "FBC enabled\n"); |
b5e50c3f | 1513 | } else { |
267f0c90 | 1514 | seq_puts(m, "FBC disabled: "); |
5c3fe8b0 | 1515 | switch (dev_priv->fbc.no_fbc_reason) { |
29ebf90f CW |
1516 | case FBC_OK: |
1517 | seq_puts(m, "FBC actived, but currently disabled in hardware"); | |
1518 | break; | |
1519 | case FBC_UNSUPPORTED: | |
1520 | seq_puts(m, "unsupported by this chipset"); | |
1521 | break; | |
bed4a673 | 1522 | case FBC_NO_OUTPUT: |
267f0c90 | 1523 | seq_puts(m, "no outputs"); |
bed4a673 | 1524 | break; |
b5e50c3f | 1525 | case FBC_STOLEN_TOO_SMALL: |
267f0c90 | 1526 | seq_puts(m, "not enough stolen memory"); |
b5e50c3f JB |
1527 | break; |
1528 | case FBC_UNSUPPORTED_MODE: | |
267f0c90 | 1529 | seq_puts(m, "mode not supported"); |
b5e50c3f JB |
1530 | break; |
1531 | case FBC_MODE_TOO_LARGE: | |
267f0c90 | 1532 | seq_puts(m, "mode too large"); |
b5e50c3f JB |
1533 | break; |
1534 | case FBC_BAD_PLANE: | |
267f0c90 | 1535 | seq_puts(m, "FBC unsupported on plane"); |
b5e50c3f JB |
1536 | break; |
1537 | case FBC_NOT_TILED: | |
267f0c90 | 1538 | seq_puts(m, "scanout buffer not tiled"); |
b5e50c3f | 1539 | break; |
9c928d16 | 1540 | case FBC_MULTIPLE_PIPES: |
267f0c90 | 1541 | seq_puts(m, "multiple pipes are enabled"); |
9c928d16 | 1542 | break; |
c1a9f047 | 1543 | case FBC_MODULE_PARAM: |
267f0c90 | 1544 | seq_puts(m, "disabled per module param (default off)"); |
c1a9f047 | 1545 | break; |
8a5729a3 | 1546 | case FBC_CHIP_DEFAULT: |
267f0c90 | 1547 | seq_puts(m, "disabled per chip default"); |
8a5729a3 | 1548 | break; |
b5e50c3f | 1549 | default: |
267f0c90 | 1550 | seq_puts(m, "unknown reason"); |
b5e50c3f | 1551 | } |
267f0c90 | 1552 | seq_putc(m, '\n'); |
b5e50c3f | 1553 | } |
36623ef8 PZ |
1554 | |
1555 | intel_runtime_pm_put(dev_priv); | |
1556 | ||
b5e50c3f JB |
1557 | return 0; |
1558 | } | |
1559 | ||
da46f936 RV |
1560 | static int i915_fbc_fc_get(void *data, u64 *val) |
1561 | { | |
1562 | struct drm_device *dev = data; | |
1563 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1564 | ||
1565 | if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev)) | |
1566 | return -ENODEV; | |
1567 | ||
1568 | drm_modeset_lock_all(dev); | |
1569 | *val = dev_priv->fbc.false_color; | |
1570 | drm_modeset_unlock_all(dev); | |
1571 | ||
1572 | return 0; | |
1573 | } | |
1574 | ||
1575 | static int i915_fbc_fc_set(void *data, u64 val) | |
1576 | { | |
1577 | struct drm_device *dev = data; | |
1578 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1579 | u32 reg; | |
1580 | ||
1581 | if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev)) | |
1582 | return -ENODEV; | |
1583 | ||
1584 | drm_modeset_lock_all(dev); | |
1585 | ||
1586 | reg = I915_READ(ILK_DPFC_CONTROL); | |
1587 | dev_priv->fbc.false_color = val; | |
1588 | ||
1589 | I915_WRITE(ILK_DPFC_CONTROL, val ? | |
1590 | (reg | FBC_CTL_FALSE_COLOR) : | |
1591 | (reg & ~FBC_CTL_FALSE_COLOR)); | |
1592 | ||
1593 | drm_modeset_unlock_all(dev); | |
1594 | return 0; | |
1595 | } | |
1596 | ||
1597 | DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops, | |
1598 | i915_fbc_fc_get, i915_fbc_fc_set, | |
1599 | "%llu\n"); | |
1600 | ||
92d44621 PZ |
1601 | static int i915_ips_status(struct seq_file *m, void *unused) |
1602 | { | |
9f25d007 | 1603 | struct drm_info_node *node = m->private; |
92d44621 PZ |
1604 | struct drm_device *dev = node->minor->dev; |
1605 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1606 | ||
f5adf94e | 1607 | if (!HAS_IPS(dev)) { |
92d44621 PZ |
1608 | seq_puts(m, "not supported\n"); |
1609 | return 0; | |
1610 | } | |
1611 | ||
36623ef8 PZ |
1612 | intel_runtime_pm_get(dev_priv); |
1613 | ||
0eaa53f0 RV |
1614 | seq_printf(m, "Enabled by kernel parameter: %s\n", |
1615 | yesno(i915.enable_ips)); | |
1616 | ||
1617 | if (INTEL_INFO(dev)->gen >= 8) { | |
1618 | seq_puts(m, "Currently: unknown\n"); | |
1619 | } else { | |
1620 | if (I915_READ(IPS_CTL) & IPS_ENABLE) | |
1621 | seq_puts(m, "Currently: enabled\n"); | |
1622 | else | |
1623 | seq_puts(m, "Currently: disabled\n"); | |
1624 | } | |
92d44621 | 1625 | |
36623ef8 PZ |
1626 | intel_runtime_pm_put(dev_priv); |
1627 | ||
92d44621 PZ |
1628 | return 0; |
1629 | } | |
1630 | ||
4a9bef37 JB |
1631 | static int i915_sr_status(struct seq_file *m, void *unused) |
1632 | { | |
9f25d007 | 1633 | struct drm_info_node *node = m->private; |
4a9bef37 | 1634 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 1635 | struct drm_i915_private *dev_priv = dev->dev_private; |
4a9bef37 JB |
1636 | bool sr_enabled = false; |
1637 | ||
36623ef8 PZ |
1638 | intel_runtime_pm_get(dev_priv); |
1639 | ||
1398261a | 1640 | if (HAS_PCH_SPLIT(dev)) |
5ba2aaaa | 1641 | sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN; |
a6c45cf0 | 1642 | else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev)) |
4a9bef37 JB |
1643 | sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN; |
1644 | else if (IS_I915GM(dev)) | |
1645 | sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN; | |
1646 | else if (IS_PINEVIEW(dev)) | |
1647 | sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN; | |
1648 | ||
36623ef8 PZ |
1649 | intel_runtime_pm_put(dev_priv); |
1650 | ||
5ba2aaaa CW |
1651 | seq_printf(m, "self-refresh: %s\n", |
1652 | sr_enabled ? "enabled" : "disabled"); | |
4a9bef37 JB |
1653 | |
1654 | return 0; | |
1655 | } | |
1656 | ||
7648fa99 JB |
1657 | static int i915_emon_status(struct seq_file *m, void *unused) |
1658 | { | |
9f25d007 | 1659 | struct drm_info_node *node = m->private; |
7648fa99 | 1660 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 1661 | struct drm_i915_private *dev_priv = dev->dev_private; |
7648fa99 | 1662 | unsigned long temp, chipset, gfx; |
de227ef0 CW |
1663 | int ret; |
1664 | ||
582be6b4 CW |
1665 | if (!IS_GEN5(dev)) |
1666 | return -ENODEV; | |
1667 | ||
de227ef0 CW |
1668 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1669 | if (ret) | |
1670 | return ret; | |
7648fa99 JB |
1671 | |
1672 | temp = i915_mch_val(dev_priv); | |
1673 | chipset = i915_chipset_val(dev_priv); | |
1674 | gfx = i915_gfx_val(dev_priv); | |
de227ef0 | 1675 | mutex_unlock(&dev->struct_mutex); |
7648fa99 JB |
1676 | |
1677 | seq_printf(m, "GMCH temp: %ld\n", temp); | |
1678 | seq_printf(m, "Chipset power: %ld\n", chipset); | |
1679 | seq_printf(m, "GFX power: %ld\n", gfx); | |
1680 | seq_printf(m, "Total power: %ld\n", chipset + gfx); | |
1681 | ||
1682 | return 0; | |
1683 | } | |
1684 | ||
23b2f8bb JB |
1685 | static int i915_ring_freq_table(struct seq_file *m, void *unused) |
1686 | { | |
9f25d007 | 1687 | struct drm_info_node *node = m->private; |
23b2f8bb | 1688 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 1689 | struct drm_i915_private *dev_priv = dev->dev_private; |
5bfa0199 | 1690 | int ret = 0; |
23b2f8bb JB |
1691 | int gpu_freq, ia_freq; |
1692 | ||
1c70c0ce | 1693 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) { |
267f0c90 | 1694 | seq_puts(m, "unsupported on this chipset\n"); |
23b2f8bb JB |
1695 | return 0; |
1696 | } | |
1697 | ||
5bfa0199 PZ |
1698 | intel_runtime_pm_get(dev_priv); |
1699 | ||
5c9669ce TR |
1700 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
1701 | ||
4fc688ce | 1702 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
23b2f8bb | 1703 | if (ret) |
5bfa0199 | 1704 | goto out; |
23b2f8bb | 1705 | |
267f0c90 | 1706 | seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n"); |
23b2f8bb | 1707 | |
b39fb297 BW |
1708 | for (gpu_freq = dev_priv->rps.min_freq_softlimit; |
1709 | gpu_freq <= dev_priv->rps.max_freq_softlimit; | |
23b2f8bb | 1710 | gpu_freq++) { |
42c0526c BW |
1711 | ia_freq = gpu_freq; |
1712 | sandybridge_pcode_read(dev_priv, | |
1713 | GEN6_PCODE_READ_MIN_FREQ_TABLE, | |
1714 | &ia_freq); | |
3ebecd07 | 1715 | seq_printf(m, "%d\t\t%d\t\t\t\t%d\n", |
7c59a9c1 | 1716 | intel_gpu_freq(dev_priv, gpu_freq), |
3ebecd07 CW |
1717 | ((ia_freq >> 0) & 0xff) * 100, |
1718 | ((ia_freq >> 8) & 0xff) * 100); | |
23b2f8bb JB |
1719 | } |
1720 | ||
4fc688ce | 1721 | mutex_unlock(&dev_priv->rps.hw_lock); |
23b2f8bb | 1722 | |
5bfa0199 PZ |
1723 | out: |
1724 | intel_runtime_pm_put(dev_priv); | |
1725 | return ret; | |
23b2f8bb JB |
1726 | } |
1727 | ||
44834a67 CW |
1728 | static int i915_opregion(struct seq_file *m, void *unused) |
1729 | { | |
9f25d007 | 1730 | struct drm_info_node *node = m->private; |
44834a67 | 1731 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 1732 | struct drm_i915_private *dev_priv = dev->dev_private; |
44834a67 | 1733 | struct intel_opregion *opregion = &dev_priv->opregion; |
0d38f009 | 1734 | void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL); |
44834a67 CW |
1735 | int ret; |
1736 | ||
0d38f009 DV |
1737 | if (data == NULL) |
1738 | return -ENOMEM; | |
1739 | ||
44834a67 CW |
1740 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1741 | if (ret) | |
0d38f009 | 1742 | goto out; |
44834a67 | 1743 | |
0d38f009 DV |
1744 | if (opregion->header) { |
1745 | memcpy_fromio(data, opregion->header, OPREGION_SIZE); | |
1746 | seq_write(m, data, OPREGION_SIZE); | |
1747 | } | |
44834a67 CW |
1748 | |
1749 | mutex_unlock(&dev->struct_mutex); | |
1750 | ||
0d38f009 DV |
1751 | out: |
1752 | kfree(data); | |
44834a67 CW |
1753 | return 0; |
1754 | } | |
1755 | ||
37811fcc CW |
1756 | static int i915_gem_framebuffer_info(struct seq_file *m, void *data) |
1757 | { | |
9f25d007 | 1758 | struct drm_info_node *node = m->private; |
37811fcc | 1759 | struct drm_device *dev = node->minor->dev; |
4520f53a | 1760 | struct intel_fbdev *ifbdev = NULL; |
37811fcc | 1761 | struct intel_framebuffer *fb; |
37811fcc | 1762 | |
4520f53a DV |
1763 | #ifdef CONFIG_DRM_I915_FBDEV |
1764 | struct drm_i915_private *dev_priv = dev->dev_private; | |
37811fcc CW |
1765 | |
1766 | ifbdev = dev_priv->fbdev; | |
1767 | fb = to_intel_framebuffer(ifbdev->helper.fb); | |
1768 | ||
623f9783 | 1769 | seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, refcount %d, obj ", |
37811fcc CW |
1770 | fb->base.width, |
1771 | fb->base.height, | |
1772 | fb->base.depth, | |
623f9783 DV |
1773 | fb->base.bits_per_pixel, |
1774 | atomic_read(&fb->base.refcount.refcount)); | |
05394f39 | 1775 | describe_obj(m, fb->obj); |
267f0c90 | 1776 | seq_putc(m, '\n'); |
4520f53a | 1777 | #endif |
37811fcc | 1778 | |
4b096ac1 | 1779 | mutex_lock(&dev->mode_config.fb_lock); |
37811fcc | 1780 | list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) { |
131a56dc | 1781 | if (ifbdev && &fb->base == ifbdev->helper.fb) |
37811fcc CW |
1782 | continue; |
1783 | ||
623f9783 | 1784 | seq_printf(m, "user size: %d x %d, depth %d, %d bpp, refcount %d, obj ", |
37811fcc CW |
1785 | fb->base.width, |
1786 | fb->base.height, | |
1787 | fb->base.depth, | |
623f9783 DV |
1788 | fb->base.bits_per_pixel, |
1789 | atomic_read(&fb->base.refcount.refcount)); | |
05394f39 | 1790 | describe_obj(m, fb->obj); |
267f0c90 | 1791 | seq_putc(m, '\n'); |
37811fcc | 1792 | } |
4b096ac1 | 1793 | mutex_unlock(&dev->mode_config.fb_lock); |
37811fcc CW |
1794 | |
1795 | return 0; | |
1796 | } | |
1797 | ||
c9fe99bd OM |
1798 | static void describe_ctx_ringbuf(struct seq_file *m, |
1799 | struct intel_ringbuffer *ringbuf) | |
1800 | { | |
1801 | seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)", | |
1802 | ringbuf->space, ringbuf->head, ringbuf->tail, | |
1803 | ringbuf->last_retired_head); | |
1804 | } | |
1805 | ||
e76d3630 BW |
1806 | static int i915_context_status(struct seq_file *m, void *unused) |
1807 | { | |
9f25d007 | 1808 | struct drm_info_node *node = m->private; |
e76d3630 | 1809 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 1810 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 1811 | struct intel_engine_cs *ring; |
273497e5 | 1812 | struct intel_context *ctx; |
a168c293 | 1813 | int ret, i; |
e76d3630 | 1814 | |
f3d28878 | 1815 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
e76d3630 BW |
1816 | if (ret) |
1817 | return ret; | |
1818 | ||
3e373948 | 1819 | if (dev_priv->ips.pwrctx) { |
267f0c90 | 1820 | seq_puts(m, "power context "); |
3e373948 | 1821 | describe_obj(m, dev_priv->ips.pwrctx); |
267f0c90 | 1822 | seq_putc(m, '\n'); |
dc501fbc | 1823 | } |
e76d3630 | 1824 | |
3e373948 | 1825 | if (dev_priv->ips.renderctx) { |
267f0c90 | 1826 | seq_puts(m, "render context "); |
3e373948 | 1827 | describe_obj(m, dev_priv->ips.renderctx); |
267f0c90 | 1828 | seq_putc(m, '\n'); |
dc501fbc | 1829 | } |
e76d3630 | 1830 | |
a33afea5 | 1831 | list_for_each_entry(ctx, &dev_priv->context_list, link) { |
c9fe99bd OM |
1832 | if (!i915.enable_execlists && |
1833 | ctx->legacy_hw_ctx.rcs_state == NULL) | |
b77f6997 CW |
1834 | continue; |
1835 | ||
a33afea5 | 1836 | seq_puts(m, "HW context "); |
3ccfd19d | 1837 | describe_ctx(m, ctx); |
c9fe99bd | 1838 | for_each_ring(ring, dev_priv, i) { |
a33afea5 | 1839 | if (ring->default_context == ctx) |
c9fe99bd OM |
1840 | seq_printf(m, "(default context %s) ", |
1841 | ring->name); | |
1842 | } | |
1843 | ||
1844 | if (i915.enable_execlists) { | |
1845 | seq_putc(m, '\n'); | |
1846 | for_each_ring(ring, dev_priv, i) { | |
1847 | struct drm_i915_gem_object *ctx_obj = | |
1848 | ctx->engine[i].state; | |
1849 | struct intel_ringbuffer *ringbuf = | |
1850 | ctx->engine[i].ringbuf; | |
1851 | ||
1852 | seq_printf(m, "%s: ", ring->name); | |
1853 | if (ctx_obj) | |
1854 | describe_obj(m, ctx_obj); | |
1855 | if (ringbuf) | |
1856 | describe_ctx_ringbuf(m, ringbuf); | |
1857 | seq_putc(m, '\n'); | |
1858 | } | |
1859 | } else { | |
1860 | describe_obj(m, ctx->legacy_hw_ctx.rcs_state); | |
1861 | } | |
a33afea5 | 1862 | |
a33afea5 | 1863 | seq_putc(m, '\n'); |
a168c293 BW |
1864 | } |
1865 | ||
f3d28878 | 1866 | mutex_unlock(&dev->struct_mutex); |
e76d3630 BW |
1867 | |
1868 | return 0; | |
1869 | } | |
1870 | ||
064ca1d2 TD |
1871 | static void i915_dump_lrc_obj(struct seq_file *m, |
1872 | struct intel_engine_cs *ring, | |
1873 | struct drm_i915_gem_object *ctx_obj) | |
1874 | { | |
1875 | struct page *page; | |
1876 | uint32_t *reg_state; | |
1877 | int j; | |
1878 | unsigned long ggtt_offset = 0; | |
1879 | ||
1880 | if (ctx_obj == NULL) { | |
1881 | seq_printf(m, "Context on %s with no gem object\n", | |
1882 | ring->name); | |
1883 | return; | |
1884 | } | |
1885 | ||
1886 | seq_printf(m, "CONTEXT: %s %u\n", ring->name, | |
1887 | intel_execlists_ctx_id(ctx_obj)); | |
1888 | ||
1889 | if (!i915_gem_obj_ggtt_bound(ctx_obj)) | |
1890 | seq_puts(m, "\tNot bound in GGTT\n"); | |
1891 | else | |
1892 | ggtt_offset = i915_gem_obj_ggtt_offset(ctx_obj); | |
1893 | ||
1894 | if (i915_gem_object_get_pages(ctx_obj)) { | |
1895 | seq_puts(m, "\tFailed to get pages for context object\n"); | |
1896 | return; | |
1897 | } | |
1898 | ||
1899 | page = i915_gem_object_get_page(ctx_obj, 1); | |
1900 | if (!WARN_ON(page == NULL)) { | |
1901 | reg_state = kmap_atomic(page); | |
1902 | ||
1903 | for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) { | |
1904 | seq_printf(m, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n", | |
1905 | ggtt_offset + 4096 + (j * 4), | |
1906 | reg_state[j], reg_state[j + 1], | |
1907 | reg_state[j + 2], reg_state[j + 3]); | |
1908 | } | |
1909 | kunmap_atomic(reg_state); | |
1910 | } | |
1911 | ||
1912 | seq_putc(m, '\n'); | |
1913 | } | |
1914 | ||
c0ab1ae9 BW |
1915 | static int i915_dump_lrc(struct seq_file *m, void *unused) |
1916 | { | |
1917 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1918 | struct drm_device *dev = node->minor->dev; | |
1919 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1920 | struct intel_engine_cs *ring; | |
1921 | struct intel_context *ctx; | |
1922 | int ret, i; | |
1923 | ||
1924 | if (!i915.enable_execlists) { | |
1925 | seq_printf(m, "Logical Ring Contexts are disabled\n"); | |
1926 | return 0; | |
1927 | } | |
1928 | ||
1929 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1930 | if (ret) | |
1931 | return ret; | |
1932 | ||
1933 | list_for_each_entry(ctx, &dev_priv->context_list, link) { | |
1934 | for_each_ring(ring, dev_priv, i) { | |
064ca1d2 TD |
1935 | if (ring->default_context != ctx) |
1936 | i915_dump_lrc_obj(m, ring, | |
1937 | ctx->engine[i].state); | |
c0ab1ae9 BW |
1938 | } |
1939 | } | |
1940 | ||
1941 | mutex_unlock(&dev->struct_mutex); | |
1942 | ||
1943 | return 0; | |
1944 | } | |
1945 | ||
4ba70e44 OM |
1946 | static int i915_execlists(struct seq_file *m, void *data) |
1947 | { | |
1948 | struct drm_info_node *node = (struct drm_info_node *)m->private; | |
1949 | struct drm_device *dev = node->minor->dev; | |
1950 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1951 | struct intel_engine_cs *ring; | |
1952 | u32 status_pointer; | |
1953 | u8 read_pointer; | |
1954 | u8 write_pointer; | |
1955 | u32 status; | |
1956 | u32 ctx_id; | |
1957 | struct list_head *cursor; | |
1958 | int ring_id, i; | |
1959 | int ret; | |
1960 | ||
1961 | if (!i915.enable_execlists) { | |
1962 | seq_puts(m, "Logical Ring Contexts are disabled\n"); | |
1963 | return 0; | |
1964 | } | |
1965 | ||
1966 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1967 | if (ret) | |
1968 | return ret; | |
1969 | ||
fc0412ec MT |
1970 | intel_runtime_pm_get(dev_priv); |
1971 | ||
4ba70e44 | 1972 | for_each_ring(ring, dev_priv, ring_id) { |
6d3d8274 | 1973 | struct drm_i915_gem_request *head_req = NULL; |
4ba70e44 OM |
1974 | int count = 0; |
1975 | unsigned long flags; | |
1976 | ||
1977 | seq_printf(m, "%s\n", ring->name); | |
1978 | ||
1979 | status = I915_READ(RING_EXECLIST_STATUS(ring)); | |
1980 | ctx_id = I915_READ(RING_EXECLIST_STATUS(ring) + 4); | |
1981 | seq_printf(m, "\tExeclist status: 0x%08X, context: %u\n", | |
1982 | status, ctx_id); | |
1983 | ||
1984 | status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(ring)); | |
1985 | seq_printf(m, "\tStatus pointer: 0x%08X\n", status_pointer); | |
1986 | ||
1987 | read_pointer = ring->next_context_status_buffer; | |
1988 | write_pointer = status_pointer & 0x07; | |
1989 | if (read_pointer > write_pointer) | |
1990 | write_pointer += 6; | |
1991 | seq_printf(m, "\tRead pointer: 0x%08X, write pointer 0x%08X\n", | |
1992 | read_pointer, write_pointer); | |
1993 | ||
1994 | for (i = 0; i < 6; i++) { | |
1995 | status = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + 8*i); | |
1996 | ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + 8*i + 4); | |
1997 | ||
1998 | seq_printf(m, "\tStatus buffer %d: 0x%08X, context: %u\n", | |
1999 | i, status, ctx_id); | |
2000 | } | |
2001 | ||
2002 | spin_lock_irqsave(&ring->execlist_lock, flags); | |
2003 | list_for_each(cursor, &ring->execlist_queue) | |
2004 | count++; | |
2005 | head_req = list_first_entry_or_null(&ring->execlist_queue, | |
6d3d8274 | 2006 | struct drm_i915_gem_request, execlist_link); |
4ba70e44 OM |
2007 | spin_unlock_irqrestore(&ring->execlist_lock, flags); |
2008 | ||
2009 | seq_printf(m, "\t%d requests in queue\n", count); | |
2010 | if (head_req) { | |
2011 | struct drm_i915_gem_object *ctx_obj; | |
2012 | ||
6d3d8274 | 2013 | ctx_obj = head_req->ctx->engine[ring_id].state; |
4ba70e44 OM |
2014 | seq_printf(m, "\tHead request id: %u\n", |
2015 | intel_execlists_ctx_id(ctx_obj)); | |
2016 | seq_printf(m, "\tHead request tail: %u\n", | |
6d3d8274 | 2017 | head_req->tail); |
4ba70e44 OM |
2018 | } |
2019 | ||
2020 | seq_putc(m, '\n'); | |
2021 | } | |
2022 | ||
fc0412ec | 2023 | intel_runtime_pm_put(dev_priv); |
4ba70e44 OM |
2024 | mutex_unlock(&dev->struct_mutex); |
2025 | ||
2026 | return 0; | |
2027 | } | |
2028 | ||
ea16a3cd DV |
2029 | static const char *swizzle_string(unsigned swizzle) |
2030 | { | |
aee56cff | 2031 | switch (swizzle) { |
ea16a3cd DV |
2032 | case I915_BIT_6_SWIZZLE_NONE: |
2033 | return "none"; | |
2034 | case I915_BIT_6_SWIZZLE_9: | |
2035 | return "bit9"; | |
2036 | case I915_BIT_6_SWIZZLE_9_10: | |
2037 | return "bit9/bit10"; | |
2038 | case I915_BIT_6_SWIZZLE_9_11: | |
2039 | return "bit9/bit11"; | |
2040 | case I915_BIT_6_SWIZZLE_9_10_11: | |
2041 | return "bit9/bit10/bit11"; | |
2042 | case I915_BIT_6_SWIZZLE_9_17: | |
2043 | return "bit9/bit17"; | |
2044 | case I915_BIT_6_SWIZZLE_9_10_17: | |
2045 | return "bit9/bit10/bit17"; | |
2046 | case I915_BIT_6_SWIZZLE_UNKNOWN: | |
8a168ca7 | 2047 | return "unknown"; |
ea16a3cd DV |
2048 | } |
2049 | ||
2050 | return "bug"; | |
2051 | } | |
2052 | ||
2053 | static int i915_swizzle_info(struct seq_file *m, void *data) | |
2054 | { | |
9f25d007 | 2055 | struct drm_info_node *node = m->private; |
ea16a3cd DV |
2056 | struct drm_device *dev = node->minor->dev; |
2057 | struct drm_i915_private *dev_priv = dev->dev_private; | |
22bcfc6a DV |
2058 | int ret; |
2059 | ||
2060 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
2061 | if (ret) | |
2062 | return ret; | |
c8c8fb33 | 2063 | intel_runtime_pm_get(dev_priv); |
ea16a3cd | 2064 | |
ea16a3cd DV |
2065 | seq_printf(m, "bit6 swizzle for X-tiling = %s\n", |
2066 | swizzle_string(dev_priv->mm.bit_6_swizzle_x)); | |
2067 | seq_printf(m, "bit6 swizzle for Y-tiling = %s\n", | |
2068 | swizzle_string(dev_priv->mm.bit_6_swizzle_y)); | |
2069 | ||
2070 | if (IS_GEN3(dev) || IS_GEN4(dev)) { | |
2071 | seq_printf(m, "DDC = 0x%08x\n", | |
2072 | I915_READ(DCC)); | |
656bfa3a DV |
2073 | seq_printf(m, "DDC2 = 0x%08x\n", |
2074 | I915_READ(DCC2)); | |
ea16a3cd DV |
2075 | seq_printf(m, "C0DRB3 = 0x%04x\n", |
2076 | I915_READ16(C0DRB3)); | |
2077 | seq_printf(m, "C1DRB3 = 0x%04x\n", | |
2078 | I915_READ16(C1DRB3)); | |
9d3203e1 | 2079 | } else if (INTEL_INFO(dev)->gen >= 6) { |
3fa7d235 DV |
2080 | seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n", |
2081 | I915_READ(MAD_DIMM_C0)); | |
2082 | seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n", | |
2083 | I915_READ(MAD_DIMM_C1)); | |
2084 | seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n", | |
2085 | I915_READ(MAD_DIMM_C2)); | |
2086 | seq_printf(m, "TILECTL = 0x%08x\n", | |
2087 | I915_READ(TILECTL)); | |
5907f5fb | 2088 | if (INTEL_INFO(dev)->gen >= 8) |
9d3203e1 BW |
2089 | seq_printf(m, "GAMTARBMODE = 0x%08x\n", |
2090 | I915_READ(GAMTARBMODE)); | |
2091 | else | |
2092 | seq_printf(m, "ARB_MODE = 0x%08x\n", | |
2093 | I915_READ(ARB_MODE)); | |
3fa7d235 DV |
2094 | seq_printf(m, "DISP_ARB_CTL = 0x%08x\n", |
2095 | I915_READ(DISP_ARB_CTL)); | |
ea16a3cd | 2096 | } |
656bfa3a DV |
2097 | |
2098 | if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) | |
2099 | seq_puts(m, "L-shaped memory detected\n"); | |
2100 | ||
c8c8fb33 | 2101 | intel_runtime_pm_put(dev_priv); |
ea16a3cd DV |
2102 | mutex_unlock(&dev->struct_mutex); |
2103 | ||
2104 | return 0; | |
2105 | } | |
2106 | ||
1c60fef5 BW |
2107 | static int per_file_ctx(int id, void *ptr, void *data) |
2108 | { | |
273497e5 | 2109 | struct intel_context *ctx = ptr; |
1c60fef5 | 2110 | struct seq_file *m = data; |
ae6c4806 DV |
2111 | struct i915_hw_ppgtt *ppgtt = ctx->ppgtt; |
2112 | ||
2113 | if (!ppgtt) { | |
2114 | seq_printf(m, " no ppgtt for context %d\n", | |
2115 | ctx->user_handle); | |
2116 | return 0; | |
2117 | } | |
1c60fef5 | 2118 | |
f83d6518 OM |
2119 | if (i915_gem_context_is_default(ctx)) |
2120 | seq_puts(m, " default context:\n"); | |
2121 | else | |
821d66dd | 2122 | seq_printf(m, " context %d:\n", ctx->user_handle); |
1c60fef5 BW |
2123 | ppgtt->debug_dump(ppgtt, m); |
2124 | ||
2125 | return 0; | |
2126 | } | |
2127 | ||
77df6772 | 2128 | static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev) |
3cf17fc5 | 2129 | { |
3cf17fc5 | 2130 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 2131 | struct intel_engine_cs *ring; |
77df6772 BW |
2132 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; |
2133 | int unused, i; | |
3cf17fc5 | 2134 | |
77df6772 BW |
2135 | if (!ppgtt) |
2136 | return; | |
2137 | ||
2138 | seq_printf(m, "Page directories: %d\n", ppgtt->num_pd_pages); | |
5abbcca3 | 2139 | seq_printf(m, "Page tables: %d\n", ppgtt->num_pd_entries); |
77df6772 BW |
2140 | for_each_ring(ring, dev_priv, unused) { |
2141 | seq_printf(m, "%s\n", ring->name); | |
2142 | for (i = 0; i < 4; i++) { | |
2143 | u32 offset = 0x270 + i * 8; | |
2144 | u64 pdp = I915_READ(ring->mmio_base + offset + 4); | |
2145 | pdp <<= 32; | |
2146 | pdp |= I915_READ(ring->mmio_base + offset); | |
a2a5b15c | 2147 | seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp); |
77df6772 BW |
2148 | } |
2149 | } | |
2150 | } | |
2151 | ||
2152 | static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev) | |
2153 | { | |
2154 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a4872ba6 | 2155 | struct intel_engine_cs *ring; |
1c60fef5 | 2156 | struct drm_file *file; |
77df6772 | 2157 | int i; |
3cf17fc5 | 2158 | |
3cf17fc5 DV |
2159 | if (INTEL_INFO(dev)->gen == 6) |
2160 | seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE)); | |
2161 | ||
a2c7f6fd | 2162 | for_each_ring(ring, dev_priv, i) { |
3cf17fc5 DV |
2163 | seq_printf(m, "%s\n", ring->name); |
2164 | if (INTEL_INFO(dev)->gen == 7) | |
2165 | seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring))); | |
2166 | seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring))); | |
2167 | seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring))); | |
2168 | seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring))); | |
2169 | } | |
2170 | if (dev_priv->mm.aliasing_ppgtt) { | |
2171 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
2172 | ||
267f0c90 | 2173 | seq_puts(m, "aliasing PPGTT:\n"); |
3cf17fc5 | 2174 | seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset); |
1c60fef5 | 2175 | |
87d60b63 | 2176 | ppgtt->debug_dump(ppgtt, m); |
ae6c4806 | 2177 | } |
1c60fef5 BW |
2178 | |
2179 | list_for_each_entry_reverse(file, &dev->filelist, lhead) { | |
2180 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
1c60fef5 | 2181 | |
1c60fef5 BW |
2182 | seq_printf(m, "proc: %s\n", |
2183 | get_pid_task(file->pid, PIDTYPE_PID)->comm); | |
1c60fef5 | 2184 | idr_for_each(&file_priv->context_idr, per_file_ctx, m); |
3cf17fc5 DV |
2185 | } |
2186 | seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK)); | |
77df6772 BW |
2187 | } |
2188 | ||
2189 | static int i915_ppgtt_info(struct seq_file *m, void *data) | |
2190 | { | |
9f25d007 | 2191 | struct drm_info_node *node = m->private; |
77df6772 | 2192 | struct drm_device *dev = node->minor->dev; |
c8c8fb33 | 2193 | struct drm_i915_private *dev_priv = dev->dev_private; |
77df6772 BW |
2194 | |
2195 | int ret = mutex_lock_interruptible(&dev->struct_mutex); | |
2196 | if (ret) | |
2197 | return ret; | |
c8c8fb33 | 2198 | intel_runtime_pm_get(dev_priv); |
77df6772 BW |
2199 | |
2200 | if (INTEL_INFO(dev)->gen >= 8) | |
2201 | gen8_ppgtt_info(m, dev); | |
2202 | else if (INTEL_INFO(dev)->gen >= 6) | |
2203 | gen6_ppgtt_info(m, dev); | |
2204 | ||
c8c8fb33 | 2205 | intel_runtime_pm_put(dev_priv); |
3cf17fc5 DV |
2206 | mutex_unlock(&dev->struct_mutex); |
2207 | ||
2208 | return 0; | |
2209 | } | |
2210 | ||
63573eb7 BW |
2211 | static int i915_llc(struct seq_file *m, void *data) |
2212 | { | |
9f25d007 | 2213 | struct drm_info_node *node = m->private; |
63573eb7 BW |
2214 | struct drm_device *dev = node->minor->dev; |
2215 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2216 | ||
2217 | /* Size calculation for LLC is a bit of a pain. Ignore for now. */ | |
2218 | seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev))); | |
2219 | seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size); | |
2220 | ||
2221 | return 0; | |
2222 | } | |
2223 | ||
e91fd8c6 RV |
2224 | static int i915_edp_psr_status(struct seq_file *m, void *data) |
2225 | { | |
2226 | struct drm_info_node *node = m->private; | |
2227 | struct drm_device *dev = node->minor->dev; | |
2228 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a031d709 | 2229 | u32 psrperf = 0; |
a6cbdb8e RV |
2230 | u32 stat[3]; |
2231 | enum pipe pipe; | |
a031d709 | 2232 | bool enabled = false; |
e91fd8c6 | 2233 | |
c8c8fb33 PZ |
2234 | intel_runtime_pm_get(dev_priv); |
2235 | ||
fa128fa6 | 2236 | mutex_lock(&dev_priv->psr.lock); |
a031d709 RV |
2237 | seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support)); |
2238 | seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok)); | |
2807cf69 | 2239 | seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled)); |
5755c78f | 2240 | seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active)); |
fa128fa6 DV |
2241 | seq_printf(m, "Busy frontbuffer bits: 0x%03x\n", |
2242 | dev_priv->psr.busy_frontbuffer_bits); | |
2243 | seq_printf(m, "Re-enable work scheduled: %s\n", | |
2244 | yesno(work_busy(&dev_priv->psr.work.work))); | |
e91fd8c6 | 2245 | |
a6cbdb8e RV |
2246 | if (HAS_PSR(dev)) { |
2247 | if (HAS_DDI(dev)) | |
2248 | enabled = I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE; | |
2249 | else { | |
2250 | for_each_pipe(dev_priv, pipe) { | |
2251 | stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) & | |
2252 | VLV_EDP_PSR_CURR_STATE_MASK; | |
2253 | if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) || | |
2254 | (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE)) | |
2255 | enabled = true; | |
2256 | } | |
2257 | } | |
2258 | } | |
2259 | seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled)); | |
2260 | ||
2261 | if (!HAS_DDI(dev)) | |
2262 | for_each_pipe(dev_priv, pipe) { | |
2263 | if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) || | |
2264 | (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE)) | |
2265 | seq_printf(m, " pipe %c", pipe_name(pipe)); | |
2266 | } | |
2267 | seq_puts(m, "\n"); | |
e91fd8c6 | 2268 | |
fb495814 RV |
2269 | seq_printf(m, "Link standby: %s\n", |
2270 | yesno((bool)dev_priv->psr.link_standby)); | |
2271 | ||
a6cbdb8e RV |
2272 | /* CHV PSR has no kind of performance counter */ |
2273 | if (HAS_PSR(dev) && HAS_DDI(dev)) { | |
a031d709 RV |
2274 | psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) & |
2275 | EDP_PSR_PERF_CNT_MASK; | |
a6cbdb8e RV |
2276 | |
2277 | seq_printf(m, "Performance_Counter: %u\n", psrperf); | |
2278 | } | |
fa128fa6 | 2279 | mutex_unlock(&dev_priv->psr.lock); |
e91fd8c6 | 2280 | |
c8c8fb33 | 2281 | intel_runtime_pm_put(dev_priv); |
e91fd8c6 RV |
2282 | return 0; |
2283 | } | |
2284 | ||
d2e216d0 RV |
2285 | static int i915_sink_crc(struct seq_file *m, void *data) |
2286 | { | |
2287 | struct drm_info_node *node = m->private; | |
2288 | struct drm_device *dev = node->minor->dev; | |
2289 | struct intel_encoder *encoder; | |
2290 | struct intel_connector *connector; | |
2291 | struct intel_dp *intel_dp = NULL; | |
2292 | int ret; | |
2293 | u8 crc[6]; | |
2294 | ||
2295 | drm_modeset_lock_all(dev); | |
2296 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
2297 | base.head) { | |
2298 | ||
2299 | if (connector->base.dpms != DRM_MODE_DPMS_ON) | |
2300 | continue; | |
2301 | ||
b6ae3c7c PZ |
2302 | if (!connector->base.encoder) |
2303 | continue; | |
2304 | ||
d2e216d0 RV |
2305 | encoder = to_intel_encoder(connector->base.encoder); |
2306 | if (encoder->type != INTEL_OUTPUT_EDP) | |
2307 | continue; | |
2308 | ||
2309 | intel_dp = enc_to_intel_dp(&encoder->base); | |
2310 | ||
2311 | ret = intel_dp_sink_crc(intel_dp, crc); | |
2312 | if (ret) | |
2313 | goto out; | |
2314 | ||
2315 | seq_printf(m, "%02x%02x%02x%02x%02x%02x\n", | |
2316 | crc[0], crc[1], crc[2], | |
2317 | crc[3], crc[4], crc[5]); | |
2318 | goto out; | |
2319 | } | |
2320 | ret = -ENODEV; | |
2321 | out: | |
2322 | drm_modeset_unlock_all(dev); | |
2323 | return ret; | |
2324 | } | |
2325 | ||
ec013e7f JB |
2326 | static int i915_energy_uJ(struct seq_file *m, void *data) |
2327 | { | |
2328 | struct drm_info_node *node = m->private; | |
2329 | struct drm_device *dev = node->minor->dev; | |
2330 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2331 | u64 power; | |
2332 | u32 units; | |
2333 | ||
2334 | if (INTEL_INFO(dev)->gen < 6) | |
2335 | return -ENODEV; | |
2336 | ||
36623ef8 PZ |
2337 | intel_runtime_pm_get(dev_priv); |
2338 | ||
ec013e7f JB |
2339 | rdmsrl(MSR_RAPL_POWER_UNIT, power); |
2340 | power = (power & 0x1f00) >> 8; | |
2341 | units = 1000000 / (1 << power); /* convert to uJ */ | |
2342 | power = I915_READ(MCH_SECP_NRG_STTS); | |
2343 | power *= units; | |
2344 | ||
36623ef8 PZ |
2345 | intel_runtime_pm_put(dev_priv); |
2346 | ||
ec013e7f | 2347 | seq_printf(m, "%llu", (long long unsigned)power); |
371db66a PZ |
2348 | |
2349 | return 0; | |
2350 | } | |
2351 | ||
2352 | static int i915_pc8_status(struct seq_file *m, void *unused) | |
2353 | { | |
9f25d007 | 2354 | struct drm_info_node *node = m->private; |
371db66a PZ |
2355 | struct drm_device *dev = node->minor->dev; |
2356 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2357 | ||
85b8d5c2 | 2358 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) { |
371db66a PZ |
2359 | seq_puts(m, "not supported\n"); |
2360 | return 0; | |
2361 | } | |
2362 | ||
86c4ec0d | 2363 | seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy)); |
371db66a | 2364 | seq_printf(m, "IRQs disabled: %s\n", |
9df7575f | 2365 | yesno(!intel_irqs_enabled(dev_priv))); |
371db66a | 2366 | |
ec013e7f JB |
2367 | return 0; |
2368 | } | |
2369 | ||
1da51581 ID |
2370 | static const char *power_domain_str(enum intel_display_power_domain domain) |
2371 | { | |
2372 | switch (domain) { | |
2373 | case POWER_DOMAIN_PIPE_A: | |
2374 | return "PIPE_A"; | |
2375 | case POWER_DOMAIN_PIPE_B: | |
2376 | return "PIPE_B"; | |
2377 | case POWER_DOMAIN_PIPE_C: | |
2378 | return "PIPE_C"; | |
2379 | case POWER_DOMAIN_PIPE_A_PANEL_FITTER: | |
2380 | return "PIPE_A_PANEL_FITTER"; | |
2381 | case POWER_DOMAIN_PIPE_B_PANEL_FITTER: | |
2382 | return "PIPE_B_PANEL_FITTER"; | |
2383 | case POWER_DOMAIN_PIPE_C_PANEL_FITTER: | |
2384 | return "PIPE_C_PANEL_FITTER"; | |
2385 | case POWER_DOMAIN_TRANSCODER_A: | |
2386 | return "TRANSCODER_A"; | |
2387 | case POWER_DOMAIN_TRANSCODER_B: | |
2388 | return "TRANSCODER_B"; | |
2389 | case POWER_DOMAIN_TRANSCODER_C: | |
2390 | return "TRANSCODER_C"; | |
2391 | case POWER_DOMAIN_TRANSCODER_EDP: | |
2392 | return "TRANSCODER_EDP"; | |
319be8ae ID |
2393 | case POWER_DOMAIN_PORT_DDI_A_2_LANES: |
2394 | return "PORT_DDI_A_2_LANES"; | |
2395 | case POWER_DOMAIN_PORT_DDI_A_4_LANES: | |
2396 | return "PORT_DDI_A_4_LANES"; | |
2397 | case POWER_DOMAIN_PORT_DDI_B_2_LANES: | |
2398 | return "PORT_DDI_B_2_LANES"; | |
2399 | case POWER_DOMAIN_PORT_DDI_B_4_LANES: | |
2400 | return "PORT_DDI_B_4_LANES"; | |
2401 | case POWER_DOMAIN_PORT_DDI_C_2_LANES: | |
2402 | return "PORT_DDI_C_2_LANES"; | |
2403 | case POWER_DOMAIN_PORT_DDI_C_4_LANES: | |
2404 | return "PORT_DDI_C_4_LANES"; | |
2405 | case POWER_DOMAIN_PORT_DDI_D_2_LANES: | |
2406 | return "PORT_DDI_D_2_LANES"; | |
2407 | case POWER_DOMAIN_PORT_DDI_D_4_LANES: | |
2408 | return "PORT_DDI_D_4_LANES"; | |
2409 | case POWER_DOMAIN_PORT_DSI: | |
2410 | return "PORT_DSI"; | |
2411 | case POWER_DOMAIN_PORT_CRT: | |
2412 | return "PORT_CRT"; | |
2413 | case POWER_DOMAIN_PORT_OTHER: | |
2414 | return "PORT_OTHER"; | |
1da51581 ID |
2415 | case POWER_DOMAIN_VGA: |
2416 | return "VGA"; | |
2417 | case POWER_DOMAIN_AUDIO: | |
2418 | return "AUDIO"; | |
bd2bb1b9 PZ |
2419 | case POWER_DOMAIN_PLLS: |
2420 | return "PLLS"; | |
1407121a S |
2421 | case POWER_DOMAIN_AUX_A: |
2422 | return "AUX_A"; | |
2423 | case POWER_DOMAIN_AUX_B: | |
2424 | return "AUX_B"; | |
2425 | case POWER_DOMAIN_AUX_C: | |
2426 | return "AUX_C"; | |
2427 | case POWER_DOMAIN_AUX_D: | |
2428 | return "AUX_D"; | |
1da51581 ID |
2429 | case POWER_DOMAIN_INIT: |
2430 | return "INIT"; | |
2431 | default: | |
5f77eeb0 | 2432 | MISSING_CASE(domain); |
1da51581 ID |
2433 | return "?"; |
2434 | } | |
2435 | } | |
2436 | ||
2437 | static int i915_power_domain_info(struct seq_file *m, void *unused) | |
2438 | { | |
9f25d007 | 2439 | struct drm_info_node *node = m->private; |
1da51581 ID |
2440 | struct drm_device *dev = node->minor->dev; |
2441 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2442 | struct i915_power_domains *power_domains = &dev_priv->power_domains; | |
2443 | int i; | |
2444 | ||
2445 | mutex_lock(&power_domains->lock); | |
2446 | ||
2447 | seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count"); | |
2448 | for (i = 0; i < power_domains->power_well_count; i++) { | |
2449 | struct i915_power_well *power_well; | |
2450 | enum intel_display_power_domain power_domain; | |
2451 | ||
2452 | power_well = &power_domains->power_wells[i]; | |
2453 | seq_printf(m, "%-25s %d\n", power_well->name, | |
2454 | power_well->count); | |
2455 | ||
2456 | for (power_domain = 0; power_domain < POWER_DOMAIN_NUM; | |
2457 | power_domain++) { | |
2458 | if (!(BIT(power_domain) & power_well->domains)) | |
2459 | continue; | |
2460 | ||
2461 | seq_printf(m, " %-23s %d\n", | |
2462 | power_domain_str(power_domain), | |
2463 | power_domains->domain_use_count[power_domain]); | |
2464 | } | |
2465 | } | |
2466 | ||
2467 | mutex_unlock(&power_domains->lock); | |
2468 | ||
2469 | return 0; | |
2470 | } | |
2471 | ||
53f5e3ca JB |
2472 | static void intel_seq_print_mode(struct seq_file *m, int tabs, |
2473 | struct drm_display_mode *mode) | |
2474 | { | |
2475 | int i; | |
2476 | ||
2477 | for (i = 0; i < tabs; i++) | |
2478 | seq_putc(m, '\t'); | |
2479 | ||
2480 | seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n", | |
2481 | mode->base.id, mode->name, | |
2482 | mode->vrefresh, mode->clock, | |
2483 | mode->hdisplay, mode->hsync_start, | |
2484 | mode->hsync_end, mode->htotal, | |
2485 | mode->vdisplay, mode->vsync_start, | |
2486 | mode->vsync_end, mode->vtotal, | |
2487 | mode->type, mode->flags); | |
2488 | } | |
2489 | ||
2490 | static void intel_encoder_info(struct seq_file *m, | |
2491 | struct intel_crtc *intel_crtc, | |
2492 | struct intel_encoder *intel_encoder) | |
2493 | { | |
9f25d007 | 2494 | struct drm_info_node *node = m->private; |
53f5e3ca JB |
2495 | struct drm_device *dev = node->minor->dev; |
2496 | struct drm_crtc *crtc = &intel_crtc->base; | |
2497 | struct intel_connector *intel_connector; | |
2498 | struct drm_encoder *encoder; | |
2499 | ||
2500 | encoder = &intel_encoder->base; | |
2501 | seq_printf(m, "\tencoder %d: type: %s, connectors:\n", | |
8e329a03 | 2502 | encoder->base.id, encoder->name); |
53f5e3ca JB |
2503 | for_each_connector_on_encoder(dev, encoder, intel_connector) { |
2504 | struct drm_connector *connector = &intel_connector->base; | |
2505 | seq_printf(m, "\t\tconnector %d: type: %s, status: %s", | |
2506 | connector->base.id, | |
c23cc417 | 2507 | connector->name, |
53f5e3ca JB |
2508 | drm_get_connector_status_name(connector->status)); |
2509 | if (connector->status == connector_status_connected) { | |
2510 | struct drm_display_mode *mode = &crtc->mode; | |
2511 | seq_printf(m, ", mode:\n"); | |
2512 | intel_seq_print_mode(m, 2, mode); | |
2513 | } else { | |
2514 | seq_putc(m, '\n'); | |
2515 | } | |
2516 | } | |
2517 | } | |
2518 | ||
2519 | static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc) | |
2520 | { | |
9f25d007 | 2521 | struct drm_info_node *node = m->private; |
53f5e3ca JB |
2522 | struct drm_device *dev = node->minor->dev; |
2523 | struct drm_crtc *crtc = &intel_crtc->base; | |
2524 | struct intel_encoder *intel_encoder; | |
2525 | ||
5aa8a937 MR |
2526 | if (crtc->primary->fb) |
2527 | seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n", | |
2528 | crtc->primary->fb->base.id, crtc->x, crtc->y, | |
2529 | crtc->primary->fb->width, crtc->primary->fb->height); | |
2530 | else | |
2531 | seq_puts(m, "\tprimary plane disabled\n"); | |
53f5e3ca JB |
2532 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) |
2533 | intel_encoder_info(m, intel_crtc, intel_encoder); | |
2534 | } | |
2535 | ||
2536 | static void intel_panel_info(struct seq_file *m, struct intel_panel *panel) | |
2537 | { | |
2538 | struct drm_display_mode *mode = panel->fixed_mode; | |
2539 | ||
2540 | seq_printf(m, "\tfixed mode:\n"); | |
2541 | intel_seq_print_mode(m, 2, mode); | |
2542 | } | |
2543 | ||
2544 | static void intel_dp_info(struct seq_file *m, | |
2545 | struct intel_connector *intel_connector) | |
2546 | { | |
2547 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
2548 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); | |
2549 | ||
2550 | seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]); | |
2551 | seq_printf(m, "\taudio support: %s\n", intel_dp->has_audio ? "yes" : | |
2552 | "no"); | |
2553 | if (intel_encoder->type == INTEL_OUTPUT_EDP) | |
2554 | intel_panel_info(m, &intel_connector->panel); | |
2555 | } | |
2556 | ||
2557 | static void intel_hdmi_info(struct seq_file *m, | |
2558 | struct intel_connector *intel_connector) | |
2559 | { | |
2560 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
2561 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base); | |
2562 | ||
2563 | seq_printf(m, "\taudio support: %s\n", intel_hdmi->has_audio ? "yes" : | |
2564 | "no"); | |
2565 | } | |
2566 | ||
2567 | static void intel_lvds_info(struct seq_file *m, | |
2568 | struct intel_connector *intel_connector) | |
2569 | { | |
2570 | intel_panel_info(m, &intel_connector->panel); | |
2571 | } | |
2572 | ||
2573 | static void intel_connector_info(struct seq_file *m, | |
2574 | struct drm_connector *connector) | |
2575 | { | |
2576 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
2577 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
f103fc7d | 2578 | struct drm_display_mode *mode; |
53f5e3ca JB |
2579 | |
2580 | seq_printf(m, "connector %d: type %s, status: %s\n", | |
c23cc417 | 2581 | connector->base.id, connector->name, |
53f5e3ca JB |
2582 | drm_get_connector_status_name(connector->status)); |
2583 | if (connector->status == connector_status_connected) { | |
2584 | seq_printf(m, "\tname: %s\n", connector->display_info.name); | |
2585 | seq_printf(m, "\tphysical dimensions: %dx%dmm\n", | |
2586 | connector->display_info.width_mm, | |
2587 | connector->display_info.height_mm); | |
2588 | seq_printf(m, "\tsubpixel order: %s\n", | |
2589 | drm_get_subpixel_order_name(connector->display_info.subpixel_order)); | |
2590 | seq_printf(m, "\tCEA rev: %d\n", | |
2591 | connector->display_info.cea_rev); | |
2592 | } | |
36cd7444 DA |
2593 | if (intel_encoder) { |
2594 | if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT || | |
2595 | intel_encoder->type == INTEL_OUTPUT_EDP) | |
2596 | intel_dp_info(m, intel_connector); | |
2597 | else if (intel_encoder->type == INTEL_OUTPUT_HDMI) | |
2598 | intel_hdmi_info(m, intel_connector); | |
2599 | else if (intel_encoder->type == INTEL_OUTPUT_LVDS) | |
2600 | intel_lvds_info(m, intel_connector); | |
2601 | } | |
53f5e3ca | 2602 | |
f103fc7d JB |
2603 | seq_printf(m, "\tmodes:\n"); |
2604 | list_for_each_entry(mode, &connector->modes, head) | |
2605 | intel_seq_print_mode(m, 2, mode); | |
53f5e3ca JB |
2606 | } |
2607 | ||
065f2ec2 CW |
2608 | static bool cursor_active(struct drm_device *dev, int pipe) |
2609 | { | |
2610 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2611 | u32 state; | |
2612 | ||
2613 | if (IS_845G(dev) || IS_I865G(dev)) | |
2614 | state = I915_READ(_CURACNTR) & CURSOR_ENABLE; | |
065f2ec2 | 2615 | else |
5efb3e28 | 2616 | state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
065f2ec2 CW |
2617 | |
2618 | return state; | |
2619 | } | |
2620 | ||
2621 | static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y) | |
2622 | { | |
2623 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2624 | u32 pos; | |
2625 | ||
5efb3e28 | 2626 | pos = I915_READ(CURPOS(pipe)); |
065f2ec2 CW |
2627 | |
2628 | *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK; | |
2629 | if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT)) | |
2630 | *x = -*x; | |
2631 | ||
2632 | *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK; | |
2633 | if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT)) | |
2634 | *y = -*y; | |
2635 | ||
2636 | return cursor_active(dev, pipe); | |
2637 | } | |
2638 | ||
53f5e3ca JB |
2639 | static int i915_display_info(struct seq_file *m, void *unused) |
2640 | { | |
9f25d007 | 2641 | struct drm_info_node *node = m->private; |
53f5e3ca | 2642 | struct drm_device *dev = node->minor->dev; |
b0e5ddf3 | 2643 | struct drm_i915_private *dev_priv = dev->dev_private; |
065f2ec2 | 2644 | struct intel_crtc *crtc; |
53f5e3ca JB |
2645 | struct drm_connector *connector; |
2646 | ||
b0e5ddf3 | 2647 | intel_runtime_pm_get(dev_priv); |
53f5e3ca JB |
2648 | drm_modeset_lock_all(dev); |
2649 | seq_printf(m, "CRTC info\n"); | |
2650 | seq_printf(m, "---------\n"); | |
d3fcc808 | 2651 | for_each_intel_crtc(dev, crtc) { |
065f2ec2 CW |
2652 | bool active; |
2653 | int x, y; | |
53f5e3ca | 2654 | |
57127efa | 2655 | seq_printf(m, "CRTC %d: pipe: %c, active=%s (size=%dx%d)\n", |
065f2ec2 | 2656 | crtc->base.base.id, pipe_name(crtc->pipe), |
6e3c9717 ACO |
2657 | yesno(crtc->active), crtc->config->pipe_src_w, |
2658 | crtc->config->pipe_src_h); | |
a23dc658 | 2659 | if (crtc->active) { |
065f2ec2 CW |
2660 | intel_crtc_info(m, crtc); |
2661 | ||
a23dc658 | 2662 | active = cursor_position(dev, crtc->pipe, &x, &y); |
57127efa | 2663 | seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n", |
4b0e333e | 2664 | yesno(crtc->cursor_base), |
57127efa CW |
2665 | x, y, crtc->cursor_width, crtc->cursor_height, |
2666 | crtc->cursor_addr, yesno(active)); | |
a23dc658 | 2667 | } |
cace841c DV |
2668 | |
2669 | seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n", | |
2670 | yesno(!crtc->cpu_fifo_underrun_disabled), | |
2671 | yesno(!crtc->pch_fifo_underrun_disabled)); | |
53f5e3ca JB |
2672 | } |
2673 | ||
2674 | seq_printf(m, "\n"); | |
2675 | seq_printf(m, "Connector info\n"); | |
2676 | seq_printf(m, "--------------\n"); | |
2677 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
2678 | intel_connector_info(m, connector); | |
2679 | } | |
2680 | drm_modeset_unlock_all(dev); | |
b0e5ddf3 | 2681 | intel_runtime_pm_put(dev_priv); |
53f5e3ca JB |
2682 | |
2683 | return 0; | |
2684 | } | |
2685 | ||
e04934cf BW |
2686 | static int i915_semaphore_status(struct seq_file *m, void *unused) |
2687 | { | |
2688 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
2689 | struct drm_device *dev = node->minor->dev; | |
2690 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2691 | struct intel_engine_cs *ring; | |
2692 | int num_rings = hweight32(INTEL_INFO(dev)->ring_mask); | |
2693 | int i, j, ret; | |
2694 | ||
2695 | if (!i915_semaphore_is_enabled(dev)) { | |
2696 | seq_puts(m, "Semaphores are disabled\n"); | |
2697 | return 0; | |
2698 | } | |
2699 | ||
2700 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
2701 | if (ret) | |
2702 | return ret; | |
03872064 | 2703 | intel_runtime_pm_get(dev_priv); |
e04934cf BW |
2704 | |
2705 | if (IS_BROADWELL(dev)) { | |
2706 | struct page *page; | |
2707 | uint64_t *seqno; | |
2708 | ||
2709 | page = i915_gem_object_get_page(dev_priv->semaphore_obj, 0); | |
2710 | ||
2711 | seqno = (uint64_t *)kmap_atomic(page); | |
2712 | for_each_ring(ring, dev_priv, i) { | |
2713 | uint64_t offset; | |
2714 | ||
2715 | seq_printf(m, "%s\n", ring->name); | |
2716 | ||
2717 | seq_puts(m, " Last signal:"); | |
2718 | for (j = 0; j < num_rings; j++) { | |
2719 | offset = i * I915_NUM_RINGS + j; | |
2720 | seq_printf(m, "0x%08llx (0x%02llx) ", | |
2721 | seqno[offset], offset * 8); | |
2722 | } | |
2723 | seq_putc(m, '\n'); | |
2724 | ||
2725 | seq_puts(m, " Last wait: "); | |
2726 | for (j = 0; j < num_rings; j++) { | |
2727 | offset = i + (j * I915_NUM_RINGS); | |
2728 | seq_printf(m, "0x%08llx (0x%02llx) ", | |
2729 | seqno[offset], offset * 8); | |
2730 | } | |
2731 | seq_putc(m, '\n'); | |
2732 | ||
2733 | } | |
2734 | kunmap_atomic(seqno); | |
2735 | } else { | |
2736 | seq_puts(m, " Last signal:"); | |
2737 | for_each_ring(ring, dev_priv, i) | |
2738 | for (j = 0; j < num_rings; j++) | |
2739 | seq_printf(m, "0x%08x\n", | |
2740 | I915_READ(ring->semaphore.mbox.signal[j])); | |
2741 | seq_putc(m, '\n'); | |
2742 | } | |
2743 | ||
2744 | seq_puts(m, "\nSync seqno:\n"); | |
2745 | for_each_ring(ring, dev_priv, i) { | |
2746 | for (j = 0; j < num_rings; j++) { | |
2747 | seq_printf(m, " 0x%08x ", ring->semaphore.sync_seqno[j]); | |
2748 | } | |
2749 | seq_putc(m, '\n'); | |
2750 | } | |
2751 | seq_putc(m, '\n'); | |
2752 | ||
03872064 | 2753 | intel_runtime_pm_put(dev_priv); |
e04934cf BW |
2754 | mutex_unlock(&dev->struct_mutex); |
2755 | return 0; | |
2756 | } | |
2757 | ||
728e29d7 DV |
2758 | static int i915_shared_dplls_info(struct seq_file *m, void *unused) |
2759 | { | |
2760 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
2761 | struct drm_device *dev = node->minor->dev; | |
2762 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2763 | int i; | |
2764 | ||
2765 | drm_modeset_lock_all(dev); | |
2766 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
2767 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
2768 | ||
2769 | seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id); | |
1e6f2ddc | 2770 | seq_printf(m, " crtc_mask: 0x%08x, active: %d, on: %s\n", |
3e369b76 | 2771 | pll->config.crtc_mask, pll->active, yesno(pll->on)); |
728e29d7 | 2772 | seq_printf(m, " tracked hardware state:\n"); |
3e369b76 ACO |
2773 | seq_printf(m, " dpll: 0x%08x\n", pll->config.hw_state.dpll); |
2774 | seq_printf(m, " dpll_md: 0x%08x\n", | |
2775 | pll->config.hw_state.dpll_md); | |
2776 | seq_printf(m, " fp0: 0x%08x\n", pll->config.hw_state.fp0); | |
2777 | seq_printf(m, " fp1: 0x%08x\n", pll->config.hw_state.fp1); | |
2778 | seq_printf(m, " wrpll: 0x%08x\n", pll->config.hw_state.wrpll); | |
728e29d7 DV |
2779 | } |
2780 | drm_modeset_unlock_all(dev); | |
2781 | ||
2782 | return 0; | |
2783 | } | |
2784 | ||
1ed1ef9d | 2785 | static int i915_wa_registers(struct seq_file *m, void *unused) |
888b5995 AS |
2786 | { |
2787 | int i; | |
2788 | int ret; | |
2789 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
2790 | struct drm_device *dev = node->minor->dev; | |
2791 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2792 | ||
888b5995 AS |
2793 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
2794 | if (ret) | |
2795 | return ret; | |
2796 | ||
2797 | intel_runtime_pm_get(dev_priv); | |
2798 | ||
7225342a MK |
2799 | seq_printf(m, "Workarounds applied: %d\n", dev_priv->workarounds.count); |
2800 | for (i = 0; i < dev_priv->workarounds.count; ++i) { | |
2fa60f6d MK |
2801 | u32 addr, mask, value, read; |
2802 | bool ok; | |
888b5995 | 2803 | |
7225342a MK |
2804 | addr = dev_priv->workarounds.reg[i].addr; |
2805 | mask = dev_priv->workarounds.reg[i].mask; | |
2fa60f6d MK |
2806 | value = dev_priv->workarounds.reg[i].value; |
2807 | read = I915_READ(addr); | |
2808 | ok = (value & mask) == (read & mask); | |
2809 | seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n", | |
2810 | addr, value, mask, read, ok ? "OK" : "FAIL"); | |
888b5995 AS |
2811 | } |
2812 | ||
2813 | intel_runtime_pm_put(dev_priv); | |
2814 | mutex_unlock(&dev->struct_mutex); | |
2815 | ||
2816 | return 0; | |
2817 | } | |
2818 | ||
c5511e44 DL |
2819 | static int i915_ddb_info(struct seq_file *m, void *unused) |
2820 | { | |
2821 | struct drm_info_node *node = m->private; | |
2822 | struct drm_device *dev = node->minor->dev; | |
2823 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2824 | struct skl_ddb_allocation *ddb; | |
2825 | struct skl_ddb_entry *entry; | |
2826 | enum pipe pipe; | |
2827 | int plane; | |
2828 | ||
2fcffe19 DL |
2829 | if (INTEL_INFO(dev)->gen < 9) |
2830 | return 0; | |
2831 | ||
c5511e44 DL |
2832 | drm_modeset_lock_all(dev); |
2833 | ||
2834 | ddb = &dev_priv->wm.skl_hw.ddb; | |
2835 | ||
2836 | seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size"); | |
2837 | ||
2838 | for_each_pipe(dev_priv, pipe) { | |
2839 | seq_printf(m, "Pipe %c\n", pipe_name(pipe)); | |
2840 | ||
2841 | for_each_plane(pipe, plane) { | |
2842 | entry = &ddb->plane[pipe][plane]; | |
2843 | seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane + 1, | |
2844 | entry->start, entry->end, | |
2845 | skl_ddb_entry_size(entry)); | |
2846 | } | |
2847 | ||
2848 | entry = &ddb->cursor[pipe]; | |
2849 | seq_printf(m, " %-13s%8u%8u%8u\n", "Cursor", entry->start, | |
2850 | entry->end, skl_ddb_entry_size(entry)); | |
2851 | } | |
2852 | ||
2853 | drm_modeset_unlock_all(dev); | |
2854 | ||
2855 | return 0; | |
2856 | } | |
2857 | ||
07144428 DL |
2858 | struct pipe_crc_info { |
2859 | const char *name; | |
2860 | struct drm_device *dev; | |
2861 | enum pipe pipe; | |
2862 | }; | |
2863 | ||
11bed958 DA |
2864 | static int i915_dp_mst_info(struct seq_file *m, void *unused) |
2865 | { | |
2866 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
2867 | struct drm_device *dev = node->minor->dev; | |
2868 | struct drm_encoder *encoder; | |
2869 | struct intel_encoder *intel_encoder; | |
2870 | struct intel_digital_port *intel_dig_port; | |
2871 | drm_modeset_lock_all(dev); | |
2872 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | |
2873 | intel_encoder = to_intel_encoder(encoder); | |
2874 | if (intel_encoder->type != INTEL_OUTPUT_DISPLAYPORT) | |
2875 | continue; | |
2876 | intel_dig_port = enc_to_dig_port(encoder); | |
2877 | if (!intel_dig_port->dp.can_mst) | |
2878 | continue; | |
2879 | ||
2880 | drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr); | |
2881 | } | |
2882 | drm_modeset_unlock_all(dev); | |
2883 | return 0; | |
2884 | } | |
2885 | ||
07144428 DL |
2886 | static int i915_pipe_crc_open(struct inode *inode, struct file *filep) |
2887 | { | |
be5c7a90 DL |
2888 | struct pipe_crc_info *info = inode->i_private; |
2889 | struct drm_i915_private *dev_priv = info->dev->dev_private; | |
2890 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe]; | |
2891 | ||
7eb1c496 DV |
2892 | if (info->pipe >= INTEL_INFO(info->dev)->num_pipes) |
2893 | return -ENODEV; | |
2894 | ||
d538bbdf DL |
2895 | spin_lock_irq(&pipe_crc->lock); |
2896 | ||
2897 | if (pipe_crc->opened) { | |
2898 | spin_unlock_irq(&pipe_crc->lock); | |
be5c7a90 DL |
2899 | return -EBUSY; /* already open */ |
2900 | } | |
2901 | ||
d538bbdf | 2902 | pipe_crc->opened = true; |
07144428 DL |
2903 | filep->private_data = inode->i_private; |
2904 | ||
d538bbdf DL |
2905 | spin_unlock_irq(&pipe_crc->lock); |
2906 | ||
07144428 DL |
2907 | return 0; |
2908 | } | |
2909 | ||
2910 | static int i915_pipe_crc_release(struct inode *inode, struct file *filep) | |
2911 | { | |
be5c7a90 DL |
2912 | struct pipe_crc_info *info = inode->i_private; |
2913 | struct drm_i915_private *dev_priv = info->dev->dev_private; | |
2914 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe]; | |
2915 | ||
d538bbdf DL |
2916 | spin_lock_irq(&pipe_crc->lock); |
2917 | pipe_crc->opened = false; | |
2918 | spin_unlock_irq(&pipe_crc->lock); | |
be5c7a90 | 2919 | |
07144428 DL |
2920 | return 0; |
2921 | } | |
2922 | ||
2923 | /* (6 fields, 8 chars each, space separated (5) + '\n') */ | |
2924 | #define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1) | |
2925 | /* account for \'0' */ | |
2926 | #define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1) | |
2927 | ||
2928 | static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc) | |
8bf1e9f1 | 2929 | { |
d538bbdf DL |
2930 | assert_spin_locked(&pipe_crc->lock); |
2931 | return CIRC_CNT(pipe_crc->head, pipe_crc->tail, | |
2932 | INTEL_PIPE_CRC_ENTRIES_NR); | |
07144428 DL |
2933 | } |
2934 | ||
2935 | static ssize_t | |
2936 | i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count, | |
2937 | loff_t *pos) | |
2938 | { | |
2939 | struct pipe_crc_info *info = filep->private_data; | |
2940 | struct drm_device *dev = info->dev; | |
2941 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2942 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe]; | |
2943 | char buf[PIPE_CRC_BUFFER_LEN]; | |
9ad6d99f | 2944 | int n_entries; |
07144428 DL |
2945 | ssize_t bytes_read; |
2946 | ||
2947 | /* | |
2948 | * Don't allow user space to provide buffers not big enough to hold | |
2949 | * a line of data. | |
2950 | */ | |
2951 | if (count < PIPE_CRC_LINE_LEN) | |
2952 | return -EINVAL; | |
2953 | ||
2954 | if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE) | |
8bf1e9f1 | 2955 | return 0; |
07144428 DL |
2956 | |
2957 | /* nothing to read */ | |
d538bbdf | 2958 | spin_lock_irq(&pipe_crc->lock); |
07144428 | 2959 | while (pipe_crc_data_count(pipe_crc) == 0) { |
d538bbdf DL |
2960 | int ret; |
2961 | ||
2962 | if (filep->f_flags & O_NONBLOCK) { | |
2963 | spin_unlock_irq(&pipe_crc->lock); | |
07144428 | 2964 | return -EAGAIN; |
d538bbdf | 2965 | } |
07144428 | 2966 | |
d538bbdf DL |
2967 | ret = wait_event_interruptible_lock_irq(pipe_crc->wq, |
2968 | pipe_crc_data_count(pipe_crc), pipe_crc->lock); | |
2969 | if (ret) { | |
2970 | spin_unlock_irq(&pipe_crc->lock); | |
2971 | return ret; | |
2972 | } | |
8bf1e9f1 SH |
2973 | } |
2974 | ||
07144428 | 2975 | /* We now have one or more entries to read */ |
9ad6d99f | 2976 | n_entries = count / PIPE_CRC_LINE_LEN; |
d538bbdf | 2977 | |
07144428 | 2978 | bytes_read = 0; |
9ad6d99f VS |
2979 | while (n_entries > 0) { |
2980 | struct intel_pipe_crc_entry *entry = | |
2981 | &pipe_crc->entries[pipe_crc->tail]; | |
07144428 | 2982 | int ret; |
8bf1e9f1 | 2983 | |
9ad6d99f VS |
2984 | if (CIRC_CNT(pipe_crc->head, pipe_crc->tail, |
2985 | INTEL_PIPE_CRC_ENTRIES_NR) < 1) | |
2986 | break; | |
2987 | ||
2988 | BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR); | |
2989 | pipe_crc->tail = (pipe_crc->tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1); | |
2990 | ||
07144428 DL |
2991 | bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN, |
2992 | "%8u %8x %8x %8x %8x %8x\n", | |
2993 | entry->frame, entry->crc[0], | |
2994 | entry->crc[1], entry->crc[2], | |
2995 | entry->crc[3], entry->crc[4]); | |
2996 | ||
9ad6d99f VS |
2997 | spin_unlock_irq(&pipe_crc->lock); |
2998 | ||
2999 | ret = copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN); | |
07144428 DL |
3000 | if (ret == PIPE_CRC_LINE_LEN) |
3001 | return -EFAULT; | |
b2c88f5b | 3002 | |
9ad6d99f VS |
3003 | user_buf += PIPE_CRC_LINE_LEN; |
3004 | n_entries--; | |
3005 | ||
3006 | spin_lock_irq(&pipe_crc->lock); | |
3007 | } | |
8bf1e9f1 | 3008 | |
d538bbdf DL |
3009 | spin_unlock_irq(&pipe_crc->lock); |
3010 | ||
07144428 DL |
3011 | return bytes_read; |
3012 | } | |
3013 | ||
3014 | static const struct file_operations i915_pipe_crc_fops = { | |
3015 | .owner = THIS_MODULE, | |
3016 | .open = i915_pipe_crc_open, | |
3017 | .read = i915_pipe_crc_read, | |
3018 | .release = i915_pipe_crc_release, | |
3019 | }; | |
3020 | ||
3021 | static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = { | |
3022 | { | |
3023 | .name = "i915_pipe_A_crc", | |
3024 | .pipe = PIPE_A, | |
3025 | }, | |
3026 | { | |
3027 | .name = "i915_pipe_B_crc", | |
3028 | .pipe = PIPE_B, | |
3029 | }, | |
3030 | { | |
3031 | .name = "i915_pipe_C_crc", | |
3032 | .pipe = PIPE_C, | |
3033 | }, | |
3034 | }; | |
3035 | ||
3036 | static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor, | |
3037 | enum pipe pipe) | |
3038 | { | |
3039 | struct drm_device *dev = minor->dev; | |
3040 | struct dentry *ent; | |
3041 | struct pipe_crc_info *info = &i915_pipe_crc_data[pipe]; | |
3042 | ||
3043 | info->dev = dev; | |
3044 | ent = debugfs_create_file(info->name, S_IRUGO, root, info, | |
3045 | &i915_pipe_crc_fops); | |
f3c5fe97 WY |
3046 | if (!ent) |
3047 | return -ENOMEM; | |
07144428 DL |
3048 | |
3049 | return drm_add_fake_info_node(minor, ent, info); | |
8bf1e9f1 SH |
3050 | } |
3051 | ||
e8dfcf78 | 3052 | static const char * const pipe_crc_sources[] = { |
926321d5 DV |
3053 | "none", |
3054 | "plane1", | |
3055 | "plane2", | |
3056 | "pf", | |
5b3a856b | 3057 | "pipe", |
3d099a05 DV |
3058 | "TV", |
3059 | "DP-B", | |
3060 | "DP-C", | |
3061 | "DP-D", | |
46a19188 | 3062 | "auto", |
926321d5 DV |
3063 | }; |
3064 | ||
3065 | static const char *pipe_crc_source_name(enum intel_pipe_crc_source source) | |
3066 | { | |
3067 | BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX); | |
3068 | return pipe_crc_sources[source]; | |
3069 | } | |
3070 | ||
bd9db02f | 3071 | static int display_crc_ctl_show(struct seq_file *m, void *data) |
926321d5 DV |
3072 | { |
3073 | struct drm_device *dev = m->private; | |
3074 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3075 | int i; | |
3076 | ||
3077 | for (i = 0; i < I915_MAX_PIPES; i++) | |
3078 | seq_printf(m, "%c %s\n", pipe_name(i), | |
3079 | pipe_crc_source_name(dev_priv->pipe_crc[i].source)); | |
3080 | ||
3081 | return 0; | |
3082 | } | |
3083 | ||
bd9db02f | 3084 | static int display_crc_ctl_open(struct inode *inode, struct file *file) |
926321d5 DV |
3085 | { |
3086 | struct drm_device *dev = inode->i_private; | |
3087 | ||
bd9db02f | 3088 | return single_open(file, display_crc_ctl_show, dev); |
926321d5 DV |
3089 | } |
3090 | ||
46a19188 | 3091 | static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source, |
52f843f6 DV |
3092 | uint32_t *val) |
3093 | { | |
46a19188 DV |
3094 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) |
3095 | *source = INTEL_PIPE_CRC_SOURCE_PIPE; | |
3096 | ||
3097 | switch (*source) { | |
52f843f6 DV |
3098 | case INTEL_PIPE_CRC_SOURCE_PIPE: |
3099 | *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX; | |
3100 | break; | |
3101 | case INTEL_PIPE_CRC_SOURCE_NONE: | |
3102 | *val = 0; | |
3103 | break; | |
3104 | default: | |
3105 | return -EINVAL; | |
3106 | } | |
3107 | ||
3108 | return 0; | |
3109 | } | |
3110 | ||
46a19188 DV |
3111 | static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe, |
3112 | enum intel_pipe_crc_source *source) | |
3113 | { | |
3114 | struct intel_encoder *encoder; | |
3115 | struct intel_crtc *crtc; | |
26756809 | 3116 | struct intel_digital_port *dig_port; |
46a19188 DV |
3117 | int ret = 0; |
3118 | ||
3119 | *source = INTEL_PIPE_CRC_SOURCE_PIPE; | |
3120 | ||
6e9f798d | 3121 | drm_modeset_lock_all(dev); |
b2784e15 | 3122 | for_each_intel_encoder(dev, encoder) { |
46a19188 DV |
3123 | if (!encoder->base.crtc) |
3124 | continue; | |
3125 | ||
3126 | crtc = to_intel_crtc(encoder->base.crtc); | |
3127 | ||
3128 | if (crtc->pipe != pipe) | |
3129 | continue; | |
3130 | ||
3131 | switch (encoder->type) { | |
3132 | case INTEL_OUTPUT_TVOUT: | |
3133 | *source = INTEL_PIPE_CRC_SOURCE_TV; | |
3134 | break; | |
3135 | case INTEL_OUTPUT_DISPLAYPORT: | |
3136 | case INTEL_OUTPUT_EDP: | |
26756809 DV |
3137 | dig_port = enc_to_dig_port(&encoder->base); |
3138 | switch (dig_port->port) { | |
3139 | case PORT_B: | |
3140 | *source = INTEL_PIPE_CRC_SOURCE_DP_B; | |
3141 | break; | |
3142 | case PORT_C: | |
3143 | *source = INTEL_PIPE_CRC_SOURCE_DP_C; | |
3144 | break; | |
3145 | case PORT_D: | |
3146 | *source = INTEL_PIPE_CRC_SOURCE_DP_D; | |
3147 | break; | |
3148 | default: | |
3149 | WARN(1, "nonexisting DP port %c\n", | |
3150 | port_name(dig_port->port)); | |
3151 | break; | |
3152 | } | |
46a19188 | 3153 | break; |
6847d71b PZ |
3154 | default: |
3155 | break; | |
46a19188 DV |
3156 | } |
3157 | } | |
6e9f798d | 3158 | drm_modeset_unlock_all(dev); |
46a19188 DV |
3159 | |
3160 | return ret; | |
3161 | } | |
3162 | ||
3163 | static int vlv_pipe_crc_ctl_reg(struct drm_device *dev, | |
3164 | enum pipe pipe, | |
3165 | enum intel_pipe_crc_source *source, | |
7ac0129b DV |
3166 | uint32_t *val) |
3167 | { | |
8d2f24ca DV |
3168 | struct drm_i915_private *dev_priv = dev->dev_private; |
3169 | bool need_stable_symbols = false; | |
3170 | ||
46a19188 DV |
3171 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) { |
3172 | int ret = i9xx_pipe_crc_auto_source(dev, pipe, source); | |
3173 | if (ret) | |
3174 | return ret; | |
3175 | } | |
3176 | ||
3177 | switch (*source) { | |
7ac0129b DV |
3178 | case INTEL_PIPE_CRC_SOURCE_PIPE: |
3179 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV; | |
3180 | break; | |
3181 | case INTEL_PIPE_CRC_SOURCE_DP_B: | |
3182 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV; | |
8d2f24ca | 3183 | need_stable_symbols = true; |
7ac0129b DV |
3184 | break; |
3185 | case INTEL_PIPE_CRC_SOURCE_DP_C: | |
3186 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV; | |
8d2f24ca | 3187 | need_stable_symbols = true; |
7ac0129b | 3188 | break; |
2be57922 VS |
3189 | case INTEL_PIPE_CRC_SOURCE_DP_D: |
3190 | if (!IS_CHERRYVIEW(dev)) | |
3191 | return -EINVAL; | |
3192 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV; | |
3193 | need_stable_symbols = true; | |
3194 | break; | |
7ac0129b DV |
3195 | case INTEL_PIPE_CRC_SOURCE_NONE: |
3196 | *val = 0; | |
3197 | break; | |
3198 | default: | |
3199 | return -EINVAL; | |
3200 | } | |
3201 | ||
8d2f24ca DV |
3202 | /* |
3203 | * When the pipe CRC tap point is after the transcoders we need | |
3204 | * to tweak symbol-level features to produce a deterministic series of | |
3205 | * symbols for a given frame. We need to reset those features only once | |
3206 | * a frame (instead of every nth symbol): | |
3207 | * - DC-balance: used to ensure a better clock recovery from the data | |
3208 | * link (SDVO) | |
3209 | * - DisplayPort scrambling: used for EMI reduction | |
3210 | */ | |
3211 | if (need_stable_symbols) { | |
3212 | uint32_t tmp = I915_READ(PORT_DFT2_G4X); | |
3213 | ||
8d2f24ca | 3214 | tmp |= DC_BALANCE_RESET_VLV; |
eb736679 VS |
3215 | switch (pipe) { |
3216 | case PIPE_A: | |
8d2f24ca | 3217 | tmp |= PIPE_A_SCRAMBLE_RESET; |
eb736679 VS |
3218 | break; |
3219 | case PIPE_B: | |
8d2f24ca | 3220 | tmp |= PIPE_B_SCRAMBLE_RESET; |
eb736679 VS |
3221 | break; |
3222 | case PIPE_C: | |
3223 | tmp |= PIPE_C_SCRAMBLE_RESET; | |
3224 | break; | |
3225 | default: | |
3226 | return -EINVAL; | |
3227 | } | |
8d2f24ca DV |
3228 | I915_WRITE(PORT_DFT2_G4X, tmp); |
3229 | } | |
3230 | ||
7ac0129b DV |
3231 | return 0; |
3232 | } | |
3233 | ||
4b79ebf7 | 3234 | static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev, |
46a19188 DV |
3235 | enum pipe pipe, |
3236 | enum intel_pipe_crc_source *source, | |
4b79ebf7 DV |
3237 | uint32_t *val) |
3238 | { | |
84093603 DV |
3239 | struct drm_i915_private *dev_priv = dev->dev_private; |
3240 | bool need_stable_symbols = false; | |
3241 | ||
46a19188 DV |
3242 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) { |
3243 | int ret = i9xx_pipe_crc_auto_source(dev, pipe, source); | |
3244 | if (ret) | |
3245 | return ret; | |
3246 | } | |
3247 | ||
3248 | switch (*source) { | |
4b79ebf7 DV |
3249 | case INTEL_PIPE_CRC_SOURCE_PIPE: |
3250 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX; | |
3251 | break; | |
3252 | case INTEL_PIPE_CRC_SOURCE_TV: | |
3253 | if (!SUPPORTS_TV(dev)) | |
3254 | return -EINVAL; | |
3255 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE; | |
3256 | break; | |
3257 | case INTEL_PIPE_CRC_SOURCE_DP_B: | |
3258 | if (!IS_G4X(dev)) | |
3259 | return -EINVAL; | |
3260 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X; | |
84093603 | 3261 | need_stable_symbols = true; |
4b79ebf7 DV |
3262 | break; |
3263 | case INTEL_PIPE_CRC_SOURCE_DP_C: | |
3264 | if (!IS_G4X(dev)) | |
3265 | return -EINVAL; | |
3266 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X; | |
84093603 | 3267 | need_stable_symbols = true; |
4b79ebf7 DV |
3268 | break; |
3269 | case INTEL_PIPE_CRC_SOURCE_DP_D: | |
3270 | if (!IS_G4X(dev)) | |
3271 | return -EINVAL; | |
3272 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X; | |
84093603 | 3273 | need_stable_symbols = true; |
4b79ebf7 DV |
3274 | break; |
3275 | case INTEL_PIPE_CRC_SOURCE_NONE: | |
3276 | *val = 0; | |
3277 | break; | |
3278 | default: | |
3279 | return -EINVAL; | |
3280 | } | |
3281 | ||
84093603 DV |
3282 | /* |
3283 | * When the pipe CRC tap point is after the transcoders we need | |
3284 | * to tweak symbol-level features to produce a deterministic series of | |
3285 | * symbols for a given frame. We need to reset those features only once | |
3286 | * a frame (instead of every nth symbol): | |
3287 | * - DC-balance: used to ensure a better clock recovery from the data | |
3288 | * link (SDVO) | |
3289 | * - DisplayPort scrambling: used for EMI reduction | |
3290 | */ | |
3291 | if (need_stable_symbols) { | |
3292 | uint32_t tmp = I915_READ(PORT_DFT2_G4X); | |
3293 | ||
3294 | WARN_ON(!IS_G4X(dev)); | |
3295 | ||
3296 | I915_WRITE(PORT_DFT_I9XX, | |
3297 | I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET); | |
3298 | ||
3299 | if (pipe == PIPE_A) | |
3300 | tmp |= PIPE_A_SCRAMBLE_RESET; | |
3301 | else | |
3302 | tmp |= PIPE_B_SCRAMBLE_RESET; | |
3303 | ||
3304 | I915_WRITE(PORT_DFT2_G4X, tmp); | |
3305 | } | |
3306 | ||
4b79ebf7 DV |
3307 | return 0; |
3308 | } | |
3309 | ||
8d2f24ca DV |
3310 | static void vlv_undo_pipe_scramble_reset(struct drm_device *dev, |
3311 | enum pipe pipe) | |
3312 | { | |
3313 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3314 | uint32_t tmp = I915_READ(PORT_DFT2_G4X); | |
3315 | ||
eb736679 VS |
3316 | switch (pipe) { |
3317 | case PIPE_A: | |
8d2f24ca | 3318 | tmp &= ~PIPE_A_SCRAMBLE_RESET; |
eb736679 VS |
3319 | break; |
3320 | case PIPE_B: | |
8d2f24ca | 3321 | tmp &= ~PIPE_B_SCRAMBLE_RESET; |
eb736679 VS |
3322 | break; |
3323 | case PIPE_C: | |
3324 | tmp &= ~PIPE_C_SCRAMBLE_RESET; | |
3325 | break; | |
3326 | default: | |
3327 | return; | |
3328 | } | |
8d2f24ca DV |
3329 | if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) |
3330 | tmp &= ~DC_BALANCE_RESET_VLV; | |
3331 | I915_WRITE(PORT_DFT2_G4X, tmp); | |
3332 | ||
3333 | } | |
3334 | ||
84093603 DV |
3335 | static void g4x_undo_pipe_scramble_reset(struct drm_device *dev, |
3336 | enum pipe pipe) | |
3337 | { | |
3338 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3339 | uint32_t tmp = I915_READ(PORT_DFT2_G4X); | |
3340 | ||
3341 | if (pipe == PIPE_A) | |
3342 | tmp &= ~PIPE_A_SCRAMBLE_RESET; | |
3343 | else | |
3344 | tmp &= ~PIPE_B_SCRAMBLE_RESET; | |
3345 | I915_WRITE(PORT_DFT2_G4X, tmp); | |
3346 | ||
3347 | if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) { | |
3348 | I915_WRITE(PORT_DFT_I9XX, | |
3349 | I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET); | |
3350 | } | |
3351 | } | |
3352 | ||
46a19188 | 3353 | static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source, |
5b3a856b DV |
3354 | uint32_t *val) |
3355 | { | |
46a19188 DV |
3356 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) |
3357 | *source = INTEL_PIPE_CRC_SOURCE_PIPE; | |
3358 | ||
3359 | switch (*source) { | |
5b3a856b DV |
3360 | case INTEL_PIPE_CRC_SOURCE_PLANE1: |
3361 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK; | |
3362 | break; | |
3363 | case INTEL_PIPE_CRC_SOURCE_PLANE2: | |
3364 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK; | |
3365 | break; | |
5b3a856b DV |
3366 | case INTEL_PIPE_CRC_SOURCE_PIPE: |
3367 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK; | |
3368 | break; | |
3d099a05 | 3369 | case INTEL_PIPE_CRC_SOURCE_NONE: |
5b3a856b DV |
3370 | *val = 0; |
3371 | break; | |
3d099a05 DV |
3372 | default: |
3373 | return -EINVAL; | |
5b3a856b DV |
3374 | } |
3375 | ||
3376 | return 0; | |
3377 | } | |
3378 | ||
fabf6e51 DV |
3379 | static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device *dev) |
3380 | { | |
3381 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3382 | struct intel_crtc *crtc = | |
3383 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]); | |
3384 | ||
3385 | drm_modeset_lock_all(dev); | |
3386 | /* | |
3387 | * If we use the eDP transcoder we need to make sure that we don't | |
3388 | * bypass the pfit, since otherwise the pipe CRC source won't work. Only | |
3389 | * relevant on hsw with pipe A when using the always-on power well | |
3390 | * routing. | |
3391 | */ | |
6e3c9717 ACO |
3392 | if (crtc->config->cpu_transcoder == TRANSCODER_EDP && |
3393 | !crtc->config->pch_pfit.enabled) { | |
3394 | crtc->config->pch_pfit.force_thru = true; | |
fabf6e51 DV |
3395 | |
3396 | intel_display_power_get(dev_priv, | |
3397 | POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A)); | |
3398 | ||
3399 | dev_priv->display.crtc_disable(&crtc->base); | |
3400 | dev_priv->display.crtc_enable(&crtc->base); | |
3401 | } | |
3402 | drm_modeset_unlock_all(dev); | |
3403 | } | |
3404 | ||
3405 | static void hsw_undo_trans_edp_pipe_A_crc_wa(struct drm_device *dev) | |
3406 | { | |
3407 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3408 | struct intel_crtc *crtc = | |
3409 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]); | |
3410 | ||
3411 | drm_modeset_lock_all(dev); | |
3412 | /* | |
3413 | * If we use the eDP transcoder we need to make sure that we don't | |
3414 | * bypass the pfit, since otherwise the pipe CRC source won't work. Only | |
3415 | * relevant on hsw with pipe A when using the always-on power well | |
3416 | * routing. | |
3417 | */ | |
6e3c9717 ACO |
3418 | if (crtc->config->pch_pfit.force_thru) { |
3419 | crtc->config->pch_pfit.force_thru = false; | |
fabf6e51 DV |
3420 | |
3421 | dev_priv->display.crtc_disable(&crtc->base); | |
3422 | dev_priv->display.crtc_enable(&crtc->base); | |
3423 | ||
3424 | intel_display_power_put(dev_priv, | |
3425 | POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A)); | |
3426 | } | |
3427 | drm_modeset_unlock_all(dev); | |
3428 | } | |
3429 | ||
3430 | static int ivb_pipe_crc_ctl_reg(struct drm_device *dev, | |
3431 | enum pipe pipe, | |
3432 | enum intel_pipe_crc_source *source, | |
5b3a856b DV |
3433 | uint32_t *val) |
3434 | { | |
46a19188 DV |
3435 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) |
3436 | *source = INTEL_PIPE_CRC_SOURCE_PF; | |
3437 | ||
3438 | switch (*source) { | |
5b3a856b DV |
3439 | case INTEL_PIPE_CRC_SOURCE_PLANE1: |
3440 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB; | |
3441 | break; | |
3442 | case INTEL_PIPE_CRC_SOURCE_PLANE2: | |
3443 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB; | |
3444 | break; | |
3445 | case INTEL_PIPE_CRC_SOURCE_PF: | |
fabf6e51 DV |
3446 | if (IS_HASWELL(dev) && pipe == PIPE_A) |
3447 | hsw_trans_edp_pipe_A_crc_wa(dev); | |
3448 | ||
5b3a856b DV |
3449 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB; |
3450 | break; | |
3d099a05 | 3451 | case INTEL_PIPE_CRC_SOURCE_NONE: |
5b3a856b DV |
3452 | *val = 0; |
3453 | break; | |
3d099a05 DV |
3454 | default: |
3455 | return -EINVAL; | |
5b3a856b DV |
3456 | } |
3457 | ||
3458 | return 0; | |
3459 | } | |
3460 | ||
926321d5 DV |
3461 | static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe, |
3462 | enum intel_pipe_crc_source source) | |
3463 | { | |
3464 | struct drm_i915_private *dev_priv = dev->dev_private; | |
cc3da175 | 3465 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; |
8c740dce PZ |
3466 | struct intel_crtc *crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, |
3467 | pipe)); | |
432f3342 | 3468 | u32 val = 0; /* shut up gcc */ |
5b3a856b | 3469 | int ret; |
926321d5 | 3470 | |
cc3da175 DL |
3471 | if (pipe_crc->source == source) |
3472 | return 0; | |
3473 | ||
ae676fcd DL |
3474 | /* forbid changing the source without going back to 'none' */ |
3475 | if (pipe_crc->source && source) | |
3476 | return -EINVAL; | |
3477 | ||
9d8b0588 DV |
3478 | if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PIPE(pipe))) { |
3479 | DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n"); | |
3480 | return -EIO; | |
3481 | } | |
3482 | ||
52f843f6 | 3483 | if (IS_GEN2(dev)) |
46a19188 | 3484 | ret = i8xx_pipe_crc_ctl_reg(&source, &val); |
52f843f6 | 3485 | else if (INTEL_INFO(dev)->gen < 5) |
46a19188 | 3486 | ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val); |
7ac0129b | 3487 | else if (IS_VALLEYVIEW(dev)) |
fabf6e51 | 3488 | ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val); |
4b79ebf7 | 3489 | else if (IS_GEN5(dev) || IS_GEN6(dev)) |
46a19188 | 3490 | ret = ilk_pipe_crc_ctl_reg(&source, &val); |
5b3a856b | 3491 | else |
fabf6e51 | 3492 | ret = ivb_pipe_crc_ctl_reg(dev, pipe, &source, &val); |
5b3a856b DV |
3493 | |
3494 | if (ret != 0) | |
3495 | return ret; | |
3496 | ||
4b584369 DL |
3497 | /* none -> real source transition */ |
3498 | if (source) { | |
4252fbc3 VS |
3499 | struct intel_pipe_crc_entry *entries; |
3500 | ||
7cd6ccff DL |
3501 | DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n", |
3502 | pipe_name(pipe), pipe_crc_source_name(source)); | |
3503 | ||
3cf54b34 VS |
3504 | entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR, |
3505 | sizeof(pipe_crc->entries[0]), | |
4252fbc3 VS |
3506 | GFP_KERNEL); |
3507 | if (!entries) | |
e5f75aca DL |
3508 | return -ENOMEM; |
3509 | ||
8c740dce PZ |
3510 | /* |
3511 | * When IPS gets enabled, the pipe CRC changes. Since IPS gets | |
3512 | * enabled and disabled dynamically based on package C states, | |
3513 | * user space can't make reliable use of the CRCs, so let's just | |
3514 | * completely disable it. | |
3515 | */ | |
3516 | hsw_disable_ips(crtc); | |
3517 | ||
d538bbdf | 3518 | spin_lock_irq(&pipe_crc->lock); |
64387b61 | 3519 | kfree(pipe_crc->entries); |
4252fbc3 | 3520 | pipe_crc->entries = entries; |
d538bbdf DL |
3521 | pipe_crc->head = 0; |
3522 | pipe_crc->tail = 0; | |
3523 | spin_unlock_irq(&pipe_crc->lock); | |
4b584369 DL |
3524 | } |
3525 | ||
cc3da175 | 3526 | pipe_crc->source = source; |
926321d5 | 3527 | |
926321d5 DV |
3528 | I915_WRITE(PIPE_CRC_CTL(pipe), val); |
3529 | POSTING_READ(PIPE_CRC_CTL(pipe)); | |
3530 | ||
e5f75aca DL |
3531 | /* real source -> none transition */ |
3532 | if (source == INTEL_PIPE_CRC_SOURCE_NONE) { | |
d538bbdf | 3533 | struct intel_pipe_crc_entry *entries; |
a33d7105 DV |
3534 | struct intel_crtc *crtc = |
3535 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
d538bbdf | 3536 | |
7cd6ccff DL |
3537 | DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n", |
3538 | pipe_name(pipe)); | |
3539 | ||
a33d7105 DV |
3540 | drm_modeset_lock(&crtc->base.mutex, NULL); |
3541 | if (crtc->active) | |
3542 | intel_wait_for_vblank(dev, pipe); | |
3543 | drm_modeset_unlock(&crtc->base.mutex); | |
bcf17ab2 | 3544 | |
d538bbdf DL |
3545 | spin_lock_irq(&pipe_crc->lock); |
3546 | entries = pipe_crc->entries; | |
e5f75aca | 3547 | pipe_crc->entries = NULL; |
9ad6d99f VS |
3548 | pipe_crc->head = 0; |
3549 | pipe_crc->tail = 0; | |
d538bbdf DL |
3550 | spin_unlock_irq(&pipe_crc->lock); |
3551 | ||
3552 | kfree(entries); | |
84093603 DV |
3553 | |
3554 | if (IS_G4X(dev)) | |
3555 | g4x_undo_pipe_scramble_reset(dev, pipe); | |
8d2f24ca DV |
3556 | else if (IS_VALLEYVIEW(dev)) |
3557 | vlv_undo_pipe_scramble_reset(dev, pipe); | |
fabf6e51 DV |
3558 | else if (IS_HASWELL(dev) && pipe == PIPE_A) |
3559 | hsw_undo_trans_edp_pipe_A_crc_wa(dev); | |
8c740dce PZ |
3560 | |
3561 | hsw_enable_ips(crtc); | |
e5f75aca DL |
3562 | } |
3563 | ||
926321d5 DV |
3564 | return 0; |
3565 | } | |
3566 | ||
3567 | /* | |
3568 | * Parse pipe CRC command strings: | |
b94dec87 DL |
3569 | * command: wsp* object wsp+ name wsp+ source wsp* |
3570 | * object: 'pipe' | |
3571 | * name: (A | B | C) | |
926321d5 DV |
3572 | * source: (none | plane1 | plane2 | pf) |
3573 | * wsp: (#0x20 | #0x9 | #0xA)+ | |
3574 | * | |
3575 | * eg.: | |
b94dec87 DL |
3576 | * "pipe A plane1" -> Start CRC computations on plane1 of pipe A |
3577 | * "pipe A none" -> Stop CRC | |
926321d5 | 3578 | */ |
bd9db02f | 3579 | static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words) |
926321d5 DV |
3580 | { |
3581 | int n_words = 0; | |
3582 | ||
3583 | while (*buf) { | |
3584 | char *end; | |
3585 | ||
3586 | /* skip leading white space */ | |
3587 | buf = skip_spaces(buf); | |
3588 | if (!*buf) | |
3589 | break; /* end of buffer */ | |
3590 | ||
3591 | /* find end of word */ | |
3592 | for (end = buf; *end && !isspace(*end); end++) | |
3593 | ; | |
3594 | ||
3595 | if (n_words == max_words) { | |
3596 | DRM_DEBUG_DRIVER("too many words, allowed <= %d\n", | |
3597 | max_words); | |
3598 | return -EINVAL; /* ran out of words[] before bytes */ | |
3599 | } | |
3600 | ||
3601 | if (*end) | |
3602 | *end++ = '\0'; | |
3603 | words[n_words++] = buf; | |
3604 | buf = end; | |
3605 | } | |
3606 | ||
3607 | return n_words; | |
3608 | } | |
3609 | ||
b94dec87 DL |
3610 | enum intel_pipe_crc_object { |
3611 | PIPE_CRC_OBJECT_PIPE, | |
3612 | }; | |
3613 | ||
e8dfcf78 | 3614 | static const char * const pipe_crc_objects[] = { |
b94dec87 DL |
3615 | "pipe", |
3616 | }; | |
3617 | ||
3618 | static int | |
bd9db02f | 3619 | display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o) |
b94dec87 DL |
3620 | { |
3621 | int i; | |
3622 | ||
3623 | for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++) | |
3624 | if (!strcmp(buf, pipe_crc_objects[i])) { | |
bd9db02f | 3625 | *o = i; |
b94dec87 DL |
3626 | return 0; |
3627 | } | |
3628 | ||
3629 | return -EINVAL; | |
3630 | } | |
3631 | ||
bd9db02f | 3632 | static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe) |
926321d5 DV |
3633 | { |
3634 | const char name = buf[0]; | |
3635 | ||
3636 | if (name < 'A' || name >= pipe_name(I915_MAX_PIPES)) | |
3637 | return -EINVAL; | |
3638 | ||
3639 | *pipe = name - 'A'; | |
3640 | ||
3641 | return 0; | |
3642 | } | |
3643 | ||
3644 | static int | |
bd9db02f | 3645 | display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s) |
926321d5 DV |
3646 | { |
3647 | int i; | |
3648 | ||
3649 | for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++) | |
3650 | if (!strcmp(buf, pipe_crc_sources[i])) { | |
bd9db02f | 3651 | *s = i; |
926321d5 DV |
3652 | return 0; |
3653 | } | |
3654 | ||
3655 | return -EINVAL; | |
3656 | } | |
3657 | ||
bd9db02f | 3658 | static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len) |
926321d5 | 3659 | { |
b94dec87 | 3660 | #define N_WORDS 3 |
926321d5 | 3661 | int n_words; |
b94dec87 | 3662 | char *words[N_WORDS]; |
926321d5 | 3663 | enum pipe pipe; |
b94dec87 | 3664 | enum intel_pipe_crc_object object; |
926321d5 DV |
3665 | enum intel_pipe_crc_source source; |
3666 | ||
bd9db02f | 3667 | n_words = display_crc_ctl_tokenize(buf, words, N_WORDS); |
b94dec87 DL |
3668 | if (n_words != N_WORDS) { |
3669 | DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n", | |
3670 | N_WORDS); | |
3671 | return -EINVAL; | |
3672 | } | |
3673 | ||
bd9db02f | 3674 | if (display_crc_ctl_parse_object(words[0], &object) < 0) { |
b94dec87 | 3675 | DRM_DEBUG_DRIVER("unknown object %s\n", words[0]); |
926321d5 DV |
3676 | return -EINVAL; |
3677 | } | |
3678 | ||
bd9db02f | 3679 | if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) { |
b94dec87 | 3680 | DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]); |
926321d5 DV |
3681 | return -EINVAL; |
3682 | } | |
3683 | ||
bd9db02f | 3684 | if (display_crc_ctl_parse_source(words[2], &source) < 0) { |
b94dec87 | 3685 | DRM_DEBUG_DRIVER("unknown source %s\n", words[2]); |
926321d5 DV |
3686 | return -EINVAL; |
3687 | } | |
3688 | ||
3689 | return pipe_crc_set_source(dev, pipe, source); | |
3690 | } | |
3691 | ||
bd9db02f DL |
3692 | static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf, |
3693 | size_t len, loff_t *offp) | |
926321d5 DV |
3694 | { |
3695 | struct seq_file *m = file->private_data; | |
3696 | struct drm_device *dev = m->private; | |
3697 | char *tmpbuf; | |
3698 | int ret; | |
3699 | ||
3700 | if (len == 0) | |
3701 | return 0; | |
3702 | ||
3703 | if (len > PAGE_SIZE - 1) { | |
3704 | DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n", | |
3705 | PAGE_SIZE); | |
3706 | return -E2BIG; | |
3707 | } | |
3708 | ||
3709 | tmpbuf = kmalloc(len + 1, GFP_KERNEL); | |
3710 | if (!tmpbuf) | |
3711 | return -ENOMEM; | |
3712 | ||
3713 | if (copy_from_user(tmpbuf, ubuf, len)) { | |
3714 | ret = -EFAULT; | |
3715 | goto out; | |
3716 | } | |
3717 | tmpbuf[len] = '\0'; | |
3718 | ||
bd9db02f | 3719 | ret = display_crc_ctl_parse(dev, tmpbuf, len); |
926321d5 DV |
3720 | |
3721 | out: | |
3722 | kfree(tmpbuf); | |
3723 | if (ret < 0) | |
3724 | return ret; | |
3725 | ||
3726 | *offp += len; | |
3727 | return len; | |
3728 | } | |
3729 | ||
bd9db02f | 3730 | static const struct file_operations i915_display_crc_ctl_fops = { |
926321d5 | 3731 | .owner = THIS_MODULE, |
bd9db02f | 3732 | .open = display_crc_ctl_open, |
926321d5 DV |
3733 | .read = seq_read, |
3734 | .llseek = seq_lseek, | |
3735 | .release = single_release, | |
bd9db02f | 3736 | .write = display_crc_ctl_write |
926321d5 DV |
3737 | }; |
3738 | ||
97e94b22 | 3739 | static void wm_latency_show(struct seq_file *m, const uint16_t wm[8]) |
369a1342 VS |
3740 | { |
3741 | struct drm_device *dev = m->private; | |
546c81fd | 3742 | int num_levels = ilk_wm_max_level(dev) + 1; |
369a1342 VS |
3743 | int level; |
3744 | ||
3745 | drm_modeset_lock_all(dev); | |
3746 | ||
3747 | for (level = 0; level < num_levels; level++) { | |
3748 | unsigned int latency = wm[level]; | |
3749 | ||
97e94b22 DL |
3750 | /* |
3751 | * - WM1+ latency values in 0.5us units | |
3752 | * - latencies are in us on gen9 | |
3753 | */ | |
3754 | if (INTEL_INFO(dev)->gen >= 9) | |
3755 | latency *= 10; | |
3756 | else if (level > 0) | |
369a1342 VS |
3757 | latency *= 5; |
3758 | ||
3759 | seq_printf(m, "WM%d %u (%u.%u usec)\n", | |
97e94b22 | 3760 | level, wm[level], latency / 10, latency % 10); |
369a1342 VS |
3761 | } |
3762 | ||
3763 | drm_modeset_unlock_all(dev); | |
3764 | } | |
3765 | ||
3766 | static int pri_wm_latency_show(struct seq_file *m, void *data) | |
3767 | { | |
3768 | struct drm_device *dev = m->private; | |
97e94b22 DL |
3769 | struct drm_i915_private *dev_priv = dev->dev_private; |
3770 | const uint16_t *latencies; | |
3771 | ||
3772 | if (INTEL_INFO(dev)->gen >= 9) | |
3773 | latencies = dev_priv->wm.skl_latency; | |
3774 | else | |
3775 | latencies = to_i915(dev)->wm.pri_latency; | |
369a1342 | 3776 | |
97e94b22 | 3777 | wm_latency_show(m, latencies); |
369a1342 VS |
3778 | |
3779 | return 0; | |
3780 | } | |
3781 | ||
3782 | static int spr_wm_latency_show(struct seq_file *m, void *data) | |
3783 | { | |
3784 | struct drm_device *dev = m->private; | |
97e94b22 DL |
3785 | struct drm_i915_private *dev_priv = dev->dev_private; |
3786 | const uint16_t *latencies; | |
3787 | ||
3788 | if (INTEL_INFO(dev)->gen >= 9) | |
3789 | latencies = dev_priv->wm.skl_latency; | |
3790 | else | |
3791 | latencies = to_i915(dev)->wm.spr_latency; | |
369a1342 | 3792 | |
97e94b22 | 3793 | wm_latency_show(m, latencies); |
369a1342 VS |
3794 | |
3795 | return 0; | |
3796 | } | |
3797 | ||
3798 | static int cur_wm_latency_show(struct seq_file *m, void *data) | |
3799 | { | |
3800 | struct drm_device *dev = m->private; | |
97e94b22 DL |
3801 | struct drm_i915_private *dev_priv = dev->dev_private; |
3802 | const uint16_t *latencies; | |
3803 | ||
3804 | if (INTEL_INFO(dev)->gen >= 9) | |
3805 | latencies = dev_priv->wm.skl_latency; | |
3806 | else | |
3807 | latencies = to_i915(dev)->wm.cur_latency; | |
369a1342 | 3808 | |
97e94b22 | 3809 | wm_latency_show(m, latencies); |
369a1342 VS |
3810 | |
3811 | return 0; | |
3812 | } | |
3813 | ||
3814 | static int pri_wm_latency_open(struct inode *inode, struct file *file) | |
3815 | { | |
3816 | struct drm_device *dev = inode->i_private; | |
3817 | ||
9ad0257c | 3818 | if (HAS_GMCH_DISPLAY(dev)) |
369a1342 VS |
3819 | return -ENODEV; |
3820 | ||
3821 | return single_open(file, pri_wm_latency_show, dev); | |
3822 | } | |
3823 | ||
3824 | static int spr_wm_latency_open(struct inode *inode, struct file *file) | |
3825 | { | |
3826 | struct drm_device *dev = inode->i_private; | |
3827 | ||
9ad0257c | 3828 | if (HAS_GMCH_DISPLAY(dev)) |
369a1342 VS |
3829 | return -ENODEV; |
3830 | ||
3831 | return single_open(file, spr_wm_latency_show, dev); | |
3832 | } | |
3833 | ||
3834 | static int cur_wm_latency_open(struct inode *inode, struct file *file) | |
3835 | { | |
3836 | struct drm_device *dev = inode->i_private; | |
3837 | ||
9ad0257c | 3838 | if (HAS_GMCH_DISPLAY(dev)) |
369a1342 VS |
3839 | return -ENODEV; |
3840 | ||
3841 | return single_open(file, cur_wm_latency_show, dev); | |
3842 | } | |
3843 | ||
3844 | static ssize_t wm_latency_write(struct file *file, const char __user *ubuf, | |
97e94b22 | 3845 | size_t len, loff_t *offp, uint16_t wm[8]) |
369a1342 VS |
3846 | { |
3847 | struct seq_file *m = file->private_data; | |
3848 | struct drm_device *dev = m->private; | |
97e94b22 | 3849 | uint16_t new[8] = { 0 }; |
546c81fd | 3850 | int num_levels = ilk_wm_max_level(dev) + 1; |
369a1342 VS |
3851 | int level; |
3852 | int ret; | |
3853 | char tmp[32]; | |
3854 | ||
3855 | if (len >= sizeof(tmp)) | |
3856 | return -EINVAL; | |
3857 | ||
3858 | if (copy_from_user(tmp, ubuf, len)) | |
3859 | return -EFAULT; | |
3860 | ||
3861 | tmp[len] = '\0'; | |
3862 | ||
97e94b22 DL |
3863 | ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu", |
3864 | &new[0], &new[1], &new[2], &new[3], | |
3865 | &new[4], &new[5], &new[6], &new[7]); | |
369a1342 VS |
3866 | if (ret != num_levels) |
3867 | return -EINVAL; | |
3868 | ||
3869 | drm_modeset_lock_all(dev); | |
3870 | ||
3871 | for (level = 0; level < num_levels; level++) | |
3872 | wm[level] = new[level]; | |
3873 | ||
3874 | drm_modeset_unlock_all(dev); | |
3875 | ||
3876 | return len; | |
3877 | } | |
3878 | ||
3879 | ||
3880 | static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf, | |
3881 | size_t len, loff_t *offp) | |
3882 | { | |
3883 | struct seq_file *m = file->private_data; | |
3884 | struct drm_device *dev = m->private; | |
97e94b22 DL |
3885 | struct drm_i915_private *dev_priv = dev->dev_private; |
3886 | uint16_t *latencies; | |
369a1342 | 3887 | |
97e94b22 DL |
3888 | if (INTEL_INFO(dev)->gen >= 9) |
3889 | latencies = dev_priv->wm.skl_latency; | |
3890 | else | |
3891 | latencies = to_i915(dev)->wm.pri_latency; | |
3892 | ||
3893 | return wm_latency_write(file, ubuf, len, offp, latencies); | |
369a1342 VS |
3894 | } |
3895 | ||
3896 | static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf, | |
3897 | size_t len, loff_t *offp) | |
3898 | { | |
3899 | struct seq_file *m = file->private_data; | |
3900 | struct drm_device *dev = m->private; | |
97e94b22 DL |
3901 | struct drm_i915_private *dev_priv = dev->dev_private; |
3902 | uint16_t *latencies; | |
369a1342 | 3903 | |
97e94b22 DL |
3904 | if (INTEL_INFO(dev)->gen >= 9) |
3905 | latencies = dev_priv->wm.skl_latency; | |
3906 | else | |
3907 | latencies = to_i915(dev)->wm.spr_latency; | |
3908 | ||
3909 | return wm_latency_write(file, ubuf, len, offp, latencies); | |
369a1342 VS |
3910 | } |
3911 | ||
3912 | static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf, | |
3913 | size_t len, loff_t *offp) | |
3914 | { | |
3915 | struct seq_file *m = file->private_data; | |
3916 | struct drm_device *dev = m->private; | |
97e94b22 DL |
3917 | struct drm_i915_private *dev_priv = dev->dev_private; |
3918 | uint16_t *latencies; | |
3919 | ||
3920 | if (INTEL_INFO(dev)->gen >= 9) | |
3921 | latencies = dev_priv->wm.skl_latency; | |
3922 | else | |
3923 | latencies = to_i915(dev)->wm.cur_latency; | |
369a1342 | 3924 | |
97e94b22 | 3925 | return wm_latency_write(file, ubuf, len, offp, latencies); |
369a1342 VS |
3926 | } |
3927 | ||
3928 | static const struct file_operations i915_pri_wm_latency_fops = { | |
3929 | .owner = THIS_MODULE, | |
3930 | .open = pri_wm_latency_open, | |
3931 | .read = seq_read, | |
3932 | .llseek = seq_lseek, | |
3933 | .release = single_release, | |
3934 | .write = pri_wm_latency_write | |
3935 | }; | |
3936 | ||
3937 | static const struct file_operations i915_spr_wm_latency_fops = { | |
3938 | .owner = THIS_MODULE, | |
3939 | .open = spr_wm_latency_open, | |
3940 | .read = seq_read, | |
3941 | .llseek = seq_lseek, | |
3942 | .release = single_release, | |
3943 | .write = spr_wm_latency_write | |
3944 | }; | |
3945 | ||
3946 | static const struct file_operations i915_cur_wm_latency_fops = { | |
3947 | .owner = THIS_MODULE, | |
3948 | .open = cur_wm_latency_open, | |
3949 | .read = seq_read, | |
3950 | .llseek = seq_lseek, | |
3951 | .release = single_release, | |
3952 | .write = cur_wm_latency_write | |
3953 | }; | |
3954 | ||
647416f9 KC |
3955 | static int |
3956 | i915_wedged_get(void *data, u64 *val) | |
f3cd474b | 3957 | { |
647416f9 | 3958 | struct drm_device *dev = data; |
e277a1f8 | 3959 | struct drm_i915_private *dev_priv = dev->dev_private; |
f3cd474b | 3960 | |
647416f9 | 3961 | *val = atomic_read(&dev_priv->gpu_error.reset_counter); |
f3cd474b | 3962 | |
647416f9 | 3963 | return 0; |
f3cd474b CW |
3964 | } |
3965 | ||
647416f9 KC |
3966 | static int |
3967 | i915_wedged_set(void *data, u64 val) | |
f3cd474b | 3968 | { |
647416f9 | 3969 | struct drm_device *dev = data; |
d46c0517 ID |
3970 | struct drm_i915_private *dev_priv = dev->dev_private; |
3971 | ||
b8d24a06 MK |
3972 | /* |
3973 | * There is no safeguard against this debugfs entry colliding | |
3974 | * with the hangcheck calling same i915_handle_error() in | |
3975 | * parallel, causing an explosion. For now we assume that the | |
3976 | * test harness is responsible enough not to inject gpu hangs | |
3977 | * while it is writing to 'i915_wedged' | |
3978 | */ | |
3979 | ||
3980 | if (i915_reset_in_progress(&dev_priv->gpu_error)) | |
3981 | return -EAGAIN; | |
3982 | ||
d46c0517 | 3983 | intel_runtime_pm_get(dev_priv); |
f3cd474b | 3984 | |
58174462 MK |
3985 | i915_handle_error(dev, val, |
3986 | "Manually setting wedged to %llu", val); | |
d46c0517 ID |
3987 | |
3988 | intel_runtime_pm_put(dev_priv); | |
3989 | ||
647416f9 | 3990 | return 0; |
f3cd474b CW |
3991 | } |
3992 | ||
647416f9 KC |
3993 | DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops, |
3994 | i915_wedged_get, i915_wedged_set, | |
3a3b4f98 | 3995 | "%llu\n"); |
f3cd474b | 3996 | |
647416f9 KC |
3997 | static int |
3998 | i915_ring_stop_get(void *data, u64 *val) | |
e5eb3d63 | 3999 | { |
647416f9 | 4000 | struct drm_device *dev = data; |
e277a1f8 | 4001 | struct drm_i915_private *dev_priv = dev->dev_private; |
e5eb3d63 | 4002 | |
647416f9 | 4003 | *val = dev_priv->gpu_error.stop_rings; |
e5eb3d63 | 4004 | |
647416f9 | 4005 | return 0; |
e5eb3d63 DV |
4006 | } |
4007 | ||
647416f9 KC |
4008 | static int |
4009 | i915_ring_stop_set(void *data, u64 val) | |
e5eb3d63 | 4010 | { |
647416f9 | 4011 | struct drm_device *dev = data; |
e5eb3d63 | 4012 | struct drm_i915_private *dev_priv = dev->dev_private; |
647416f9 | 4013 | int ret; |
e5eb3d63 | 4014 | |
647416f9 | 4015 | DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val); |
e5eb3d63 | 4016 | |
22bcfc6a DV |
4017 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
4018 | if (ret) | |
4019 | return ret; | |
4020 | ||
99584db3 | 4021 | dev_priv->gpu_error.stop_rings = val; |
e5eb3d63 DV |
4022 | mutex_unlock(&dev->struct_mutex); |
4023 | ||
647416f9 | 4024 | return 0; |
e5eb3d63 DV |
4025 | } |
4026 | ||
647416f9 KC |
4027 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops, |
4028 | i915_ring_stop_get, i915_ring_stop_set, | |
4029 | "0x%08llx\n"); | |
d5442303 | 4030 | |
094f9a54 CW |
4031 | static int |
4032 | i915_ring_missed_irq_get(void *data, u64 *val) | |
4033 | { | |
4034 | struct drm_device *dev = data; | |
4035 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4036 | ||
4037 | *val = dev_priv->gpu_error.missed_irq_rings; | |
4038 | return 0; | |
4039 | } | |
4040 | ||
4041 | static int | |
4042 | i915_ring_missed_irq_set(void *data, u64 val) | |
4043 | { | |
4044 | struct drm_device *dev = data; | |
4045 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4046 | int ret; | |
4047 | ||
4048 | /* Lock against concurrent debugfs callers */ | |
4049 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
4050 | if (ret) | |
4051 | return ret; | |
4052 | dev_priv->gpu_error.missed_irq_rings = val; | |
4053 | mutex_unlock(&dev->struct_mutex); | |
4054 | ||
4055 | return 0; | |
4056 | } | |
4057 | ||
4058 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops, | |
4059 | i915_ring_missed_irq_get, i915_ring_missed_irq_set, | |
4060 | "0x%08llx\n"); | |
4061 | ||
4062 | static int | |
4063 | i915_ring_test_irq_get(void *data, u64 *val) | |
4064 | { | |
4065 | struct drm_device *dev = data; | |
4066 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4067 | ||
4068 | *val = dev_priv->gpu_error.test_irq_rings; | |
4069 | ||
4070 | return 0; | |
4071 | } | |
4072 | ||
4073 | static int | |
4074 | i915_ring_test_irq_set(void *data, u64 val) | |
4075 | { | |
4076 | struct drm_device *dev = data; | |
4077 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4078 | int ret; | |
4079 | ||
4080 | DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val); | |
4081 | ||
4082 | /* Lock against concurrent debugfs callers */ | |
4083 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
4084 | if (ret) | |
4085 | return ret; | |
4086 | ||
4087 | dev_priv->gpu_error.test_irq_rings = val; | |
4088 | mutex_unlock(&dev->struct_mutex); | |
4089 | ||
4090 | return 0; | |
4091 | } | |
4092 | ||
4093 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops, | |
4094 | i915_ring_test_irq_get, i915_ring_test_irq_set, | |
4095 | "0x%08llx\n"); | |
4096 | ||
dd624afd CW |
4097 | #define DROP_UNBOUND 0x1 |
4098 | #define DROP_BOUND 0x2 | |
4099 | #define DROP_RETIRE 0x4 | |
4100 | #define DROP_ACTIVE 0x8 | |
4101 | #define DROP_ALL (DROP_UNBOUND | \ | |
4102 | DROP_BOUND | \ | |
4103 | DROP_RETIRE | \ | |
4104 | DROP_ACTIVE) | |
647416f9 KC |
4105 | static int |
4106 | i915_drop_caches_get(void *data, u64 *val) | |
dd624afd | 4107 | { |
647416f9 | 4108 | *val = DROP_ALL; |
dd624afd | 4109 | |
647416f9 | 4110 | return 0; |
dd624afd CW |
4111 | } |
4112 | ||
647416f9 KC |
4113 | static int |
4114 | i915_drop_caches_set(void *data, u64 val) | |
dd624afd | 4115 | { |
647416f9 | 4116 | struct drm_device *dev = data; |
dd624afd | 4117 | struct drm_i915_private *dev_priv = dev->dev_private; |
647416f9 | 4118 | int ret; |
dd624afd | 4119 | |
2f9fe5ff | 4120 | DRM_DEBUG("Dropping caches: 0x%08llx\n", val); |
dd624afd CW |
4121 | |
4122 | /* No need to check and wait for gpu resets, only libdrm auto-restarts | |
4123 | * on ioctls on -EAGAIN. */ | |
4124 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
4125 | if (ret) | |
4126 | return ret; | |
4127 | ||
4128 | if (val & DROP_ACTIVE) { | |
4129 | ret = i915_gpu_idle(dev); | |
4130 | if (ret) | |
4131 | goto unlock; | |
4132 | } | |
4133 | ||
4134 | if (val & (DROP_RETIRE | DROP_ACTIVE)) | |
4135 | i915_gem_retire_requests(dev); | |
4136 | ||
21ab4e74 CW |
4137 | if (val & DROP_BOUND) |
4138 | i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND); | |
4ad72b7f | 4139 | |
21ab4e74 CW |
4140 | if (val & DROP_UNBOUND) |
4141 | i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND); | |
dd624afd CW |
4142 | |
4143 | unlock: | |
4144 | mutex_unlock(&dev->struct_mutex); | |
4145 | ||
647416f9 | 4146 | return ret; |
dd624afd CW |
4147 | } |
4148 | ||
647416f9 KC |
4149 | DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops, |
4150 | i915_drop_caches_get, i915_drop_caches_set, | |
4151 | "0x%08llx\n"); | |
dd624afd | 4152 | |
647416f9 KC |
4153 | static int |
4154 | i915_max_freq_get(void *data, u64 *val) | |
358733e9 | 4155 | { |
647416f9 | 4156 | struct drm_device *dev = data; |
e277a1f8 | 4157 | struct drm_i915_private *dev_priv = dev->dev_private; |
647416f9 | 4158 | int ret; |
004777cb | 4159 | |
daa3afb2 | 4160 | if (INTEL_INFO(dev)->gen < 6) |
004777cb DV |
4161 | return -ENODEV; |
4162 | ||
5c9669ce TR |
4163 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
4164 | ||
4fc688ce | 4165 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
4166 | if (ret) |
4167 | return ret; | |
358733e9 | 4168 | |
7c59a9c1 | 4169 | *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit); |
4fc688ce | 4170 | mutex_unlock(&dev_priv->rps.hw_lock); |
358733e9 | 4171 | |
647416f9 | 4172 | return 0; |
358733e9 JB |
4173 | } |
4174 | ||
647416f9 KC |
4175 | static int |
4176 | i915_max_freq_set(void *data, u64 val) | |
358733e9 | 4177 | { |
647416f9 | 4178 | struct drm_device *dev = data; |
358733e9 | 4179 | struct drm_i915_private *dev_priv = dev->dev_private; |
dd0a1aa1 | 4180 | u32 rp_state_cap, hw_max, hw_min; |
647416f9 | 4181 | int ret; |
004777cb | 4182 | |
daa3afb2 | 4183 | if (INTEL_INFO(dev)->gen < 6) |
004777cb | 4184 | return -ENODEV; |
358733e9 | 4185 | |
5c9669ce TR |
4186 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
4187 | ||
647416f9 | 4188 | DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val); |
358733e9 | 4189 | |
4fc688ce | 4190 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
4191 | if (ret) |
4192 | return ret; | |
4193 | ||
358733e9 JB |
4194 | /* |
4195 | * Turbo will still be enabled, but won't go above the set value. | |
4196 | */ | |
0a073b84 | 4197 | if (IS_VALLEYVIEW(dev)) { |
7c59a9c1 | 4198 | val = intel_freq_opcode(dev_priv, val); |
dd0a1aa1 | 4199 | |
03af2045 VS |
4200 | hw_max = dev_priv->rps.max_freq; |
4201 | hw_min = dev_priv->rps.min_freq; | |
0a073b84 | 4202 | } else { |
7c59a9c1 | 4203 | val = intel_freq_opcode(dev_priv, val); |
dd0a1aa1 JM |
4204 | |
4205 | rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); | |
b39fb297 | 4206 | hw_max = dev_priv->rps.max_freq; |
dd0a1aa1 JM |
4207 | hw_min = (rp_state_cap >> 16) & 0xff; |
4208 | } | |
4209 | ||
b39fb297 | 4210 | if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) { |
dd0a1aa1 JM |
4211 | mutex_unlock(&dev_priv->rps.hw_lock); |
4212 | return -EINVAL; | |
0a073b84 JB |
4213 | } |
4214 | ||
b39fb297 | 4215 | dev_priv->rps.max_freq_softlimit = val; |
dd0a1aa1 JM |
4216 | |
4217 | if (IS_VALLEYVIEW(dev)) | |
4218 | valleyview_set_rps(dev, val); | |
4219 | else | |
4220 | gen6_set_rps(dev, val); | |
4221 | ||
4fc688ce | 4222 | mutex_unlock(&dev_priv->rps.hw_lock); |
358733e9 | 4223 | |
647416f9 | 4224 | return 0; |
358733e9 JB |
4225 | } |
4226 | ||
647416f9 KC |
4227 | DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops, |
4228 | i915_max_freq_get, i915_max_freq_set, | |
3a3b4f98 | 4229 | "%llu\n"); |
358733e9 | 4230 | |
647416f9 KC |
4231 | static int |
4232 | i915_min_freq_get(void *data, u64 *val) | |
1523c310 | 4233 | { |
647416f9 | 4234 | struct drm_device *dev = data; |
e277a1f8 | 4235 | struct drm_i915_private *dev_priv = dev->dev_private; |
647416f9 | 4236 | int ret; |
004777cb | 4237 | |
daa3afb2 | 4238 | if (INTEL_INFO(dev)->gen < 6) |
004777cb DV |
4239 | return -ENODEV; |
4240 | ||
5c9669ce TR |
4241 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
4242 | ||
4fc688ce | 4243 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
4244 | if (ret) |
4245 | return ret; | |
1523c310 | 4246 | |
7c59a9c1 | 4247 | *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit); |
4fc688ce | 4248 | mutex_unlock(&dev_priv->rps.hw_lock); |
1523c310 | 4249 | |
647416f9 | 4250 | return 0; |
1523c310 JB |
4251 | } |
4252 | ||
647416f9 KC |
4253 | static int |
4254 | i915_min_freq_set(void *data, u64 val) | |
1523c310 | 4255 | { |
647416f9 | 4256 | struct drm_device *dev = data; |
1523c310 | 4257 | struct drm_i915_private *dev_priv = dev->dev_private; |
dd0a1aa1 | 4258 | u32 rp_state_cap, hw_max, hw_min; |
647416f9 | 4259 | int ret; |
004777cb | 4260 | |
daa3afb2 | 4261 | if (INTEL_INFO(dev)->gen < 6) |
004777cb | 4262 | return -ENODEV; |
1523c310 | 4263 | |
5c9669ce TR |
4264 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
4265 | ||
647416f9 | 4266 | DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val); |
1523c310 | 4267 | |
4fc688ce | 4268 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
4269 | if (ret) |
4270 | return ret; | |
4271 | ||
1523c310 JB |
4272 | /* |
4273 | * Turbo will still be enabled, but won't go below the set value. | |
4274 | */ | |
0a073b84 | 4275 | if (IS_VALLEYVIEW(dev)) { |
7c59a9c1 | 4276 | val = intel_freq_opcode(dev_priv, val); |
dd0a1aa1 | 4277 | |
03af2045 VS |
4278 | hw_max = dev_priv->rps.max_freq; |
4279 | hw_min = dev_priv->rps.min_freq; | |
0a073b84 | 4280 | } else { |
7c59a9c1 | 4281 | val = intel_freq_opcode(dev_priv, val); |
dd0a1aa1 JM |
4282 | |
4283 | rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); | |
b39fb297 | 4284 | hw_max = dev_priv->rps.max_freq; |
dd0a1aa1 JM |
4285 | hw_min = (rp_state_cap >> 16) & 0xff; |
4286 | } | |
4287 | ||
b39fb297 | 4288 | if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) { |
dd0a1aa1 JM |
4289 | mutex_unlock(&dev_priv->rps.hw_lock); |
4290 | return -EINVAL; | |
0a073b84 | 4291 | } |
dd0a1aa1 | 4292 | |
b39fb297 | 4293 | dev_priv->rps.min_freq_softlimit = val; |
dd0a1aa1 JM |
4294 | |
4295 | if (IS_VALLEYVIEW(dev)) | |
4296 | valleyview_set_rps(dev, val); | |
4297 | else | |
4298 | gen6_set_rps(dev, val); | |
4299 | ||
4fc688ce | 4300 | mutex_unlock(&dev_priv->rps.hw_lock); |
1523c310 | 4301 | |
647416f9 | 4302 | return 0; |
1523c310 JB |
4303 | } |
4304 | ||
647416f9 KC |
4305 | DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops, |
4306 | i915_min_freq_get, i915_min_freq_set, | |
3a3b4f98 | 4307 | "%llu\n"); |
1523c310 | 4308 | |
647416f9 KC |
4309 | static int |
4310 | i915_cache_sharing_get(void *data, u64 *val) | |
07b7ddd9 | 4311 | { |
647416f9 | 4312 | struct drm_device *dev = data; |
e277a1f8 | 4313 | struct drm_i915_private *dev_priv = dev->dev_private; |
07b7ddd9 | 4314 | u32 snpcr; |
647416f9 | 4315 | int ret; |
07b7ddd9 | 4316 | |
004777cb DV |
4317 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) |
4318 | return -ENODEV; | |
4319 | ||
22bcfc6a DV |
4320 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
4321 | if (ret) | |
4322 | return ret; | |
c8c8fb33 | 4323 | intel_runtime_pm_get(dev_priv); |
22bcfc6a | 4324 | |
07b7ddd9 | 4325 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); |
c8c8fb33 PZ |
4326 | |
4327 | intel_runtime_pm_put(dev_priv); | |
07b7ddd9 JB |
4328 | mutex_unlock(&dev_priv->dev->struct_mutex); |
4329 | ||
647416f9 | 4330 | *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT; |
07b7ddd9 | 4331 | |
647416f9 | 4332 | return 0; |
07b7ddd9 JB |
4333 | } |
4334 | ||
647416f9 KC |
4335 | static int |
4336 | i915_cache_sharing_set(void *data, u64 val) | |
07b7ddd9 | 4337 | { |
647416f9 | 4338 | struct drm_device *dev = data; |
07b7ddd9 | 4339 | struct drm_i915_private *dev_priv = dev->dev_private; |
07b7ddd9 | 4340 | u32 snpcr; |
07b7ddd9 | 4341 | |
004777cb DV |
4342 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) |
4343 | return -ENODEV; | |
4344 | ||
647416f9 | 4345 | if (val > 3) |
07b7ddd9 JB |
4346 | return -EINVAL; |
4347 | ||
c8c8fb33 | 4348 | intel_runtime_pm_get(dev_priv); |
647416f9 | 4349 | DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val); |
07b7ddd9 JB |
4350 | |
4351 | /* Update the cache sharing policy here as well */ | |
4352 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); | |
4353 | snpcr &= ~GEN6_MBC_SNPCR_MASK; | |
4354 | snpcr |= (val << GEN6_MBC_SNPCR_SHIFT); | |
4355 | I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); | |
4356 | ||
c8c8fb33 | 4357 | intel_runtime_pm_put(dev_priv); |
647416f9 | 4358 | return 0; |
07b7ddd9 JB |
4359 | } |
4360 | ||
647416f9 KC |
4361 | DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops, |
4362 | i915_cache_sharing_get, i915_cache_sharing_set, | |
4363 | "%llu\n"); | |
07b7ddd9 | 4364 | |
6d794d42 BW |
4365 | static int i915_forcewake_open(struct inode *inode, struct file *file) |
4366 | { | |
4367 | struct drm_device *dev = inode->i_private; | |
4368 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6d794d42 | 4369 | |
075edca4 | 4370 | if (INTEL_INFO(dev)->gen < 6) |
6d794d42 BW |
4371 | return 0; |
4372 | ||
6daccb0b | 4373 | intel_runtime_pm_get(dev_priv); |
59bad947 | 4374 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
6d794d42 BW |
4375 | |
4376 | return 0; | |
4377 | } | |
4378 | ||
c43b5634 | 4379 | static int i915_forcewake_release(struct inode *inode, struct file *file) |
6d794d42 BW |
4380 | { |
4381 | struct drm_device *dev = inode->i_private; | |
4382 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4383 | ||
075edca4 | 4384 | if (INTEL_INFO(dev)->gen < 6) |
6d794d42 BW |
4385 | return 0; |
4386 | ||
59bad947 | 4387 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
6daccb0b | 4388 | intel_runtime_pm_put(dev_priv); |
6d794d42 BW |
4389 | |
4390 | return 0; | |
4391 | } | |
4392 | ||
4393 | static const struct file_operations i915_forcewake_fops = { | |
4394 | .owner = THIS_MODULE, | |
4395 | .open = i915_forcewake_open, | |
4396 | .release = i915_forcewake_release, | |
4397 | }; | |
4398 | ||
4399 | static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor) | |
4400 | { | |
4401 | struct drm_device *dev = minor->dev; | |
4402 | struct dentry *ent; | |
4403 | ||
4404 | ent = debugfs_create_file("i915_forcewake_user", | |
8eb57294 | 4405 | S_IRUSR, |
6d794d42 BW |
4406 | root, dev, |
4407 | &i915_forcewake_fops); | |
f3c5fe97 WY |
4408 | if (!ent) |
4409 | return -ENOMEM; | |
6d794d42 | 4410 | |
8eb57294 | 4411 | return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops); |
6d794d42 BW |
4412 | } |
4413 | ||
6a9c308d DV |
4414 | static int i915_debugfs_create(struct dentry *root, |
4415 | struct drm_minor *minor, | |
4416 | const char *name, | |
4417 | const struct file_operations *fops) | |
07b7ddd9 JB |
4418 | { |
4419 | struct drm_device *dev = minor->dev; | |
4420 | struct dentry *ent; | |
4421 | ||
6a9c308d | 4422 | ent = debugfs_create_file(name, |
07b7ddd9 JB |
4423 | S_IRUGO | S_IWUSR, |
4424 | root, dev, | |
6a9c308d | 4425 | fops); |
f3c5fe97 WY |
4426 | if (!ent) |
4427 | return -ENOMEM; | |
07b7ddd9 | 4428 | |
6a9c308d | 4429 | return drm_add_fake_info_node(minor, ent, fops); |
07b7ddd9 JB |
4430 | } |
4431 | ||
06c5bf8c | 4432 | static const struct drm_info_list i915_debugfs_list[] = { |
311bd68e | 4433 | {"i915_capabilities", i915_capabilities, 0}, |
73aa808f | 4434 | {"i915_gem_objects", i915_gem_object_info, 0}, |
08c18323 | 4435 | {"i915_gem_gtt", i915_gem_gtt_info, 0}, |
1b50247a | 4436 | {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST}, |
433e12f7 | 4437 | {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST}, |
433e12f7 | 4438 | {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST}, |
6d2b8885 | 4439 | {"i915_gem_stolen", i915_gem_stolen_list_info }, |
4e5359cd | 4440 | {"i915_gem_pageflip", i915_gem_pageflip_info, 0}, |
2017263e BG |
4441 | {"i915_gem_request", i915_gem_request_info, 0}, |
4442 | {"i915_gem_seqno", i915_gem_seqno_info, 0}, | |
a6172a80 | 4443 | {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0}, |
2017263e | 4444 | {"i915_gem_interrupt", i915_interrupt_info, 0}, |
1ec14ad3 CW |
4445 | {"i915_gem_hws", i915_hws_info, 0, (void *)RCS}, |
4446 | {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS}, | |
4447 | {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS}, | |
9010ebfd | 4448 | {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS}, |
493018dc | 4449 | {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0}, |
adb4bd12 | 4450 | {"i915_frequency_info", i915_frequency_info, 0}, |
f654449a | 4451 | {"i915_hangcheck_info", i915_hangcheck_info, 0}, |
f97108d1 | 4452 | {"i915_drpc_info", i915_drpc_info, 0}, |
7648fa99 | 4453 | {"i915_emon_status", i915_emon_status, 0}, |
23b2f8bb | 4454 | {"i915_ring_freq_table", i915_ring_freq_table, 0}, |
b5e50c3f | 4455 | {"i915_fbc_status", i915_fbc_status, 0}, |
92d44621 | 4456 | {"i915_ips_status", i915_ips_status, 0}, |
4a9bef37 | 4457 | {"i915_sr_status", i915_sr_status, 0}, |
44834a67 | 4458 | {"i915_opregion", i915_opregion, 0}, |
37811fcc | 4459 | {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0}, |
e76d3630 | 4460 | {"i915_context_status", i915_context_status, 0}, |
c0ab1ae9 | 4461 | {"i915_dump_lrc", i915_dump_lrc, 0}, |
4ba70e44 | 4462 | {"i915_execlists", i915_execlists, 0}, |
f65367b5 | 4463 | {"i915_forcewake_domains", i915_forcewake_domains, 0}, |
ea16a3cd | 4464 | {"i915_swizzle_info", i915_swizzle_info, 0}, |
3cf17fc5 | 4465 | {"i915_ppgtt_info", i915_ppgtt_info, 0}, |
63573eb7 | 4466 | {"i915_llc", i915_llc, 0}, |
e91fd8c6 | 4467 | {"i915_edp_psr_status", i915_edp_psr_status, 0}, |
d2e216d0 | 4468 | {"i915_sink_crc_eDP1", i915_sink_crc, 0}, |
ec013e7f | 4469 | {"i915_energy_uJ", i915_energy_uJ, 0}, |
371db66a | 4470 | {"i915_pc8_status", i915_pc8_status, 0}, |
1da51581 | 4471 | {"i915_power_domain_info", i915_power_domain_info, 0}, |
53f5e3ca | 4472 | {"i915_display_info", i915_display_info, 0}, |
e04934cf | 4473 | {"i915_semaphore_status", i915_semaphore_status, 0}, |
728e29d7 | 4474 | {"i915_shared_dplls_info", i915_shared_dplls_info, 0}, |
11bed958 | 4475 | {"i915_dp_mst_info", i915_dp_mst_info, 0}, |
1ed1ef9d | 4476 | {"i915_wa_registers", i915_wa_registers, 0}, |
c5511e44 | 4477 | {"i915_ddb_info", i915_ddb_info, 0}, |
2017263e | 4478 | }; |
27c202ad | 4479 | #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list) |
2017263e | 4480 | |
06c5bf8c | 4481 | static const struct i915_debugfs_files { |
34b9674c DV |
4482 | const char *name; |
4483 | const struct file_operations *fops; | |
4484 | } i915_debugfs_files[] = { | |
4485 | {"i915_wedged", &i915_wedged_fops}, | |
4486 | {"i915_max_freq", &i915_max_freq_fops}, | |
4487 | {"i915_min_freq", &i915_min_freq_fops}, | |
4488 | {"i915_cache_sharing", &i915_cache_sharing_fops}, | |
4489 | {"i915_ring_stop", &i915_ring_stop_fops}, | |
094f9a54 CW |
4490 | {"i915_ring_missed_irq", &i915_ring_missed_irq_fops}, |
4491 | {"i915_ring_test_irq", &i915_ring_test_irq_fops}, | |
34b9674c DV |
4492 | {"i915_gem_drop_caches", &i915_drop_caches_fops}, |
4493 | {"i915_error_state", &i915_error_state_fops}, | |
4494 | {"i915_next_seqno", &i915_next_seqno_fops}, | |
bd9db02f | 4495 | {"i915_display_crc_ctl", &i915_display_crc_ctl_fops}, |
369a1342 VS |
4496 | {"i915_pri_wm_latency", &i915_pri_wm_latency_fops}, |
4497 | {"i915_spr_wm_latency", &i915_spr_wm_latency_fops}, | |
4498 | {"i915_cur_wm_latency", &i915_cur_wm_latency_fops}, | |
da46f936 | 4499 | {"i915_fbc_false_color", &i915_fbc_fc_fops}, |
34b9674c DV |
4500 | }; |
4501 | ||
07144428 DL |
4502 | void intel_display_crc_init(struct drm_device *dev) |
4503 | { | |
4504 | struct drm_i915_private *dev_priv = dev->dev_private; | |
b378360e | 4505 | enum pipe pipe; |
07144428 | 4506 | |
055e393f | 4507 | for_each_pipe(dev_priv, pipe) { |
b378360e | 4508 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; |
07144428 | 4509 | |
d538bbdf DL |
4510 | pipe_crc->opened = false; |
4511 | spin_lock_init(&pipe_crc->lock); | |
07144428 DL |
4512 | init_waitqueue_head(&pipe_crc->wq); |
4513 | } | |
4514 | } | |
4515 | ||
27c202ad | 4516 | int i915_debugfs_init(struct drm_minor *minor) |
2017263e | 4517 | { |
34b9674c | 4518 | int ret, i; |
f3cd474b | 4519 | |
6d794d42 | 4520 | ret = i915_forcewake_create(minor->debugfs_root, minor); |
358733e9 JB |
4521 | if (ret) |
4522 | return ret; | |
6a9c308d | 4523 | |
07144428 DL |
4524 | for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) { |
4525 | ret = i915_pipe_crc_create(minor->debugfs_root, minor, i); | |
4526 | if (ret) | |
4527 | return ret; | |
4528 | } | |
4529 | ||
34b9674c DV |
4530 | for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) { |
4531 | ret = i915_debugfs_create(minor->debugfs_root, minor, | |
4532 | i915_debugfs_files[i].name, | |
4533 | i915_debugfs_files[i].fops); | |
4534 | if (ret) | |
4535 | return ret; | |
4536 | } | |
40633219 | 4537 | |
27c202ad BG |
4538 | return drm_debugfs_create_files(i915_debugfs_list, |
4539 | I915_DEBUGFS_ENTRIES, | |
2017263e BG |
4540 | minor->debugfs_root, minor); |
4541 | } | |
4542 | ||
27c202ad | 4543 | void i915_debugfs_cleanup(struct drm_minor *minor) |
2017263e | 4544 | { |
34b9674c DV |
4545 | int i; |
4546 | ||
27c202ad BG |
4547 | drm_debugfs_remove_files(i915_debugfs_list, |
4548 | I915_DEBUGFS_ENTRIES, minor); | |
07144428 | 4549 | |
6d794d42 BW |
4550 | drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops, |
4551 | 1, minor); | |
07144428 | 4552 | |
e309a997 | 4553 | for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) { |
07144428 DL |
4554 | struct drm_info_list *info_list = |
4555 | (struct drm_info_list *)&i915_pipe_crc_data[i]; | |
4556 | ||
4557 | drm_debugfs_remove_files(info_list, 1, minor); | |
4558 | } | |
4559 | ||
34b9674c DV |
4560 | for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) { |
4561 | struct drm_info_list *info_list = | |
4562 | (struct drm_info_list *) i915_debugfs_files[i].fops; | |
4563 | ||
4564 | drm_debugfs_remove_files(info_list, 1, minor); | |
4565 | } | |
2017263e | 4566 | } |