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drm/i915: grab a pages pin count for preallocate stolen
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_debugfs.c
CommitLineData
2017263e
BG		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 *
27 */
28
29#include <linux/seq_file.h>
b2c88f5b 30#include <linux/circ_buf.h>
926321d5 31#include <linux/ctype.h>
f3cd474b 32#include <linux/debugfs.h>
5a0e3ad6 33#include <linux/slab.h>
2d1a8a48 34#include <linux/export.h>
6d2b8885 35#include <linux/list_sort.h>
ec013e7f 36#include <asm/msr-index.h>
760285e7 37#include <drm/drmP.h>
4e5359cd 38#include "intel_drv.h"
e5c65260 39#include "intel_ringbuffer.h"
760285e7 40#include <drm/i915_drm.h>
2017263e
BG		 41#include "i915_drv.h"
42
f13d3f73 43enum {
69dc4987 44 ACTIVE_LIST,
f13d3f73 45 INACTIVE_LIST,
d21d5975 46 PINNED_LIST,
f13d3f73 47};
2017263e 48
70d39fe4
CW		 49static const char *yesno(int v)
50{
51 return v ? "yes" : "no";
52}
53
497666d8
DL		 54/* As the drm_debugfs_init() routines are called before dev->dev_private is
55 * allocated we need to hook into the minor for release. */
56static int
57drm_add_fake_info_node(struct drm_minor *minor,
58 struct dentry *ent,
59 const void *key)
60{
61 struct drm_info_node *node;
62
63 node = kmalloc(sizeof(*node), GFP_KERNEL);
64 if (node == NULL) {
65 debugfs_remove(ent);
66 return -ENOMEM;
67 }
68
69 node->minor = minor;
70 node->dent = ent;
71 node->info_ent = (void *) key;
72
73 mutex_lock(&minor->debugfs_lock);
74 list_add(&node->list, &minor->debugfs_list);
75 mutex_unlock(&minor->debugfs_lock);
76
77 return 0;
78}
79
70d39fe4
CW		 80static int i915_capabilities(struct seq_file *m, void *data)
81{
82 struct drm_info_node *node = (struct drm_info_node *) m->private;
83 struct drm_device *dev = node->minor->dev;
84 const struct intel_device_info *info = INTEL_INFO(dev);
85
86 seq_printf(m, "gen: %d\n", info->gen);
03d00ac5 87 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
79fc46df
DL		 88#define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
89#define SEP_SEMICOLON ;
90 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
91#undef PRINT_FLAG
92#undef SEP_SEMICOLON
70d39fe4
CW		 93
94 return 0;
95}
2017263e 96
05394f39 97static const char *get_pin_flag(struct drm_i915_gem_object *obj)
a6172a80 98{
05394f39 99 if (obj->user_pin_count > 0)
a6172a80 100 return "P";
05394f39 101 else if (obj->pin_count > 0)
a6172a80
CW		 102 return "p";
103 else
104 return " ";
105}
106
05394f39 107static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
a6172a80 108{
0206e353
AJ		 109 switch (obj->tiling_mode) {
110 default:
111 case I915_TILING_NONE: return " ";
112 case I915_TILING_X: return "X";
113 case I915_TILING_Y: return "Y";
114 }
a6172a80
CW		 115}
116
1d693bcc
BW		 117static inline const char *get_global_flag(struct drm_i915_gem_object *obj)
118{
119 return obj->has_global_gtt_mapping ? "g" : " ";
120}
121
37811fcc
CW		 122static void
123describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
124{
1d693bcc 125 struct i915_vma *vma;
fb1ae911 126 seq_printf(m, "%pK: %s%s%s %8zdKiB %02x %02x %u %u %u%s%s%s",
37811fcc
CW		 127 &obj->base,
128 get_pin_flag(obj),
129 get_tiling_flag(obj),
1d693bcc 130 get_global_flag(obj),
a05a5862 131 obj->base.size / 1024,
37811fcc
CW		 132 obj->base.read_domains,
133 obj->base.write_domain,
0201f1ec
CW		 134 obj->last_read_seqno,
135 obj->last_write_seqno,
caea7476 136 obj->last_fenced_seqno,
84734a04 137 i915_cache_level_str(obj->cache_level),
37811fcc
CW		 138 obj->dirty ? " dirty" : "",
139 obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
140 if (obj->base.name)
141 seq_printf(m, " (name: %d)", obj->base.name);
c110a6d7
CW		 142 if (obj->pin_count)
143 seq_printf(m, " (pinned x %d)", obj->pin_count);
cc98b413
CW		 144 if (obj->pin_display)
145 seq_printf(m, " (display)");
37811fcc
CW		 146 if (obj->fence_reg != I915_FENCE_REG_NONE)
147 seq_printf(m, " (fence: %d)", obj->fence_reg);
1d693bcc
BW		 148 list_for_each_entry(vma, &obj->vma_list, vma_link) {
149 if (!i915_is_ggtt(vma->vm))
150 seq_puts(m, " (pp");
151 else
152 seq_puts(m, " (g");
153 seq_printf(m, "gtt offset: %08lx, size: %08lx)",
154 vma->node.start, vma->node.size);
155 }
c1ad11fc
CW		 156 if (obj->stolen)
157 seq_printf(m, " (stolen: %08lx)", obj->stolen->start);
6299f992
CW		 158 if (obj->pin_mappable || obj->fault_mappable) {
159 char s[3], *t = s;
160 if (obj->pin_mappable)
161 *t++ = 'p';
162 if (obj->fault_mappable)
163 *t++ = 'f';
164 *t = '\0';
165 seq_printf(m, " (%s mappable)", s);
166 }
69dc4987
CW		 167 if (obj->ring != NULL)
168 seq_printf(m, " (%s)", obj->ring->name);
37811fcc
CW		 169}
170
3ccfd19d
BW		 171static void describe_ctx(struct seq_file *m, struct i915_hw_context *ctx)
172{
173 seq_putc(m, ctx->is_initialized ? 'I' : 'i');
174 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
175 seq_putc(m, ' ');
176}
177
433e12f7 178static int i915_gem_object_list_info(struct seq_file *m, void *data)
2017263e
BG		 179{
180 struct drm_info_node *node = (struct drm_info_node *) m->private;
433e12f7
BG		 181 uintptr_t list = (uintptr_t) node->info_ent->data;
182 struct list_head *head;
2017263e 183 struct drm_device *dev = node->minor->dev;
5cef07e1
BW		 184 struct drm_i915_private *dev_priv = dev->dev_private;
185 struct i915_address_space *vm = &dev_priv->gtt.base;
ca191b13 186 struct i915_vma *vma;
8f2480fb
CW		 187 size_t total_obj_size, total_gtt_size;
188 int count, ret;
de227ef0
CW		 189
190 ret = mutex_lock_interruptible(&dev->struct_mutex);
191 if (ret)
192 return ret;
2017263e 193
ca191b13 194 /* FIXME: the user of this interface might want more than just GGTT */
433e12f7
BG		 195 switch (list) {
196 case ACTIVE_LIST:
267f0c90 197 seq_puts(m, "Active:\n");
5cef07e1 198 head = &vm->active_list;
433e12f7
BG		 199 break;
200 case INACTIVE_LIST:
267f0c90 201 seq_puts(m, "Inactive:\n");
5cef07e1 202 head = &vm->inactive_list;
433e12f7 203 break;
433e12f7 204 default:
de227ef0
CW		 205 mutex_unlock(&dev->struct_mutex);
206 return -EINVAL;
2017263e 207 }
2017263e 208
8f2480fb 209 total_obj_size = total_gtt_size = count = 0;
ca191b13
BW		 210 list_for_each_entry(vma, head, mm_list) {
211 seq_printf(m, " ");
212 describe_obj(m, vma->obj);
213 seq_printf(m, "\n");
214 total_obj_size += vma->obj->base.size;
215 total_gtt_size += vma->node.size;
8f2480fb 216 count++;
2017263e 217 }
de227ef0 218 mutex_unlock(&dev->struct_mutex);
5e118f41 219
8f2480fb
CW		 220 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
221 count, total_obj_size, total_gtt_size);
2017263e
BG		 222 return 0;
223}
224
6d2b8885
CW		 225static int obj_rank_by_stolen(void *priv,
226 struct list_head *A, struct list_head *B)
227{
228 struct drm_i915_gem_object *a =
b25cb2f8 229 container_of(A, struct drm_i915_gem_object, obj_exec_link);
6d2b8885 230 struct drm_i915_gem_object *b =
b25cb2f8 231 container_of(B, struct drm_i915_gem_object, obj_exec_link);
6d2b8885
CW		 232
233 return a->stolen->start - b->stolen->start;
234}
235
236static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
237{
238 struct drm_info_node *node = (struct drm_info_node *) m->private;
239 struct drm_device *dev = node->minor->dev;
240 struct drm_i915_private *dev_priv = dev->dev_private;
241 struct drm_i915_gem_object *obj;
242 size_t total_obj_size, total_gtt_size;
243 LIST_HEAD(stolen);
244 int count, ret;
245
246 ret = mutex_lock_interruptible(&dev->struct_mutex);
247 if (ret)
248 return ret;
249
250 total_obj_size = total_gtt_size = count = 0;
251 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
252 if (obj->stolen == NULL)
253 continue;
254
b25cb2f8 255 list_add(&obj->obj_exec_link, &stolen);
6d2b8885
CW		 256
257 total_obj_size += obj->base.size;
258 total_gtt_size += i915_gem_obj_ggtt_size(obj);
259 count++;
260 }
261 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
262 if (obj->stolen == NULL)
263 continue;
264
b25cb2f8 265 list_add(&obj->obj_exec_link, &stolen);
6d2b8885
CW		 266
267 total_obj_size += obj->base.size;
268 count++;
269 }
270 list_sort(NULL, &stolen, obj_rank_by_stolen);
271 seq_puts(m, "Stolen:\n");
272 while (!list_empty(&stolen)) {
b25cb2f8 273 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
6d2b8885
CW		 274 seq_puts(m, " ");
275 describe_obj(m, obj);
276 seq_putc(m, '\n');
b25cb2f8 277 list_del_init(&obj->obj_exec_link);
6d2b8885
CW		 278 }
279 mutex_unlock(&dev->struct_mutex);
280
281 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
282 count, total_obj_size, total_gtt_size);
283 return 0;
284}
285
6299f992
CW		 286#define count_objects(list, member) do { \
287 list_for_each_entry(obj, list, member) { \
f343c5f6 288 size += i915_gem_obj_ggtt_size(obj); \
6299f992
CW		 289 ++count; \
290 if (obj->map_and_fenceable) { \
f343c5f6 291 mappable_size += i915_gem_obj_ggtt_size(obj); \
6299f992
CW		 292 ++mappable_count; \
293 } \
294 } \
0206e353 295} while (0)
6299f992 296
2db8e9d6
CW		 297struct file_stats {
298 int count;
299 size_t total, active, inactive, unbound;
300};
301
302static int per_file_stats(int id, void *ptr, void *data)
303{
304 struct drm_i915_gem_object *obj = ptr;
305 struct file_stats *stats = data;
306
307 stats->count++;
308 stats->total += obj->base.size;
309
f343c5f6 310 if (i915_gem_obj_ggtt_bound(obj)) {
2db8e9d6
CW		 311 if (!list_empty(&obj->ring_list))
312 stats->active += obj->base.size;
313 else
314 stats->inactive += obj->base.size;
315 } else {
316 if (!list_empty(&obj->global_list))
317 stats->unbound += obj->base.size;
318 }
319
320 return 0;
321}
322
ca191b13
BW		 323#define count_vmas(list, member) do { \
324 list_for_each_entry(vma, list, member) { \
325 size += i915_gem_obj_ggtt_size(vma->obj); \
326 ++count; \
327 if (vma->obj->map_and_fenceable) { \
328 mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
329 ++mappable_count; \
330 } \
331 } \
332} while (0)
333
334static int i915_gem_object_info(struct seq_file *m, void* data)
73aa808f
CW		 335{
336 struct drm_info_node *node = (struct drm_info_node *) m->private;
337 struct drm_device *dev = node->minor->dev;
338 struct drm_i915_private *dev_priv = dev->dev_private;
b7abb714
CW		 339 u32 count, mappable_count, purgeable_count;
340 size_t size, mappable_size, purgeable_size;
6299f992 341 struct drm_i915_gem_object *obj;
5cef07e1 342 struct i915_address_space *vm = &dev_priv->gtt.base;
2db8e9d6 343 struct drm_file *file;
ca191b13 344 struct i915_vma *vma;
73aa808f
CW		 345 int ret;
346
347 ret = mutex_lock_interruptible(&dev->struct_mutex);
348 if (ret)
349 return ret;
350
6299f992
CW		 351 seq_printf(m, "%u objects, %zu bytes\n",
352 dev_priv->mm.object_count,
353 dev_priv->mm.object_memory);
354
355 size = count = mappable_size = mappable_count = 0;
35c20a60 356 count_objects(&dev_priv->mm.bound_list, global_list);
6299f992
CW		 357 seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n",
358 count, mappable_count, size, mappable_size);
359
360 size = count = mappable_size = mappable_count = 0;
ca191b13 361 count_vmas(&vm->active_list, mm_list);
6299f992
CW		 362 seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n",
363 count, mappable_count, size, mappable_size);
364
6299f992 365 size = count = mappable_size = mappable_count = 0;
ca191b13 366 count_vmas(&vm->inactive_list, mm_list);
6299f992
CW		 367 seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n",
368 count, mappable_count, size, mappable_size);
369
b7abb714 370 size = count = purgeable_size = purgeable_count = 0;
35c20a60 371 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
6c085a72 372 size += obj->base.size, ++count;
b7abb714
CW		 373 if (obj->madv == I915_MADV_DONTNEED)
374 purgeable_size += obj->base.size, ++purgeable_count;
375 }
6c085a72
CW		 376 seq_printf(m, "%u unbound objects, %zu bytes\n", count, size);
377
6299f992 378 size = count = mappable_size = mappable_count = 0;
35c20a60 379 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
6299f992 380 if (obj->fault_mappable) {
f343c5f6 381 size += i915_gem_obj_ggtt_size(obj);
6299f992
CW		 382 ++count;
383 }
384 if (obj->pin_mappable) {
f343c5f6 385 mappable_size += i915_gem_obj_ggtt_size(obj);
6299f992
CW		 386 ++mappable_count;
387 }
b7abb714
CW		 388 if (obj->madv == I915_MADV_DONTNEED) {
389 purgeable_size += obj->base.size;
390 ++purgeable_count;
391 }
6299f992 392 }
b7abb714
CW		 393 seq_printf(m, "%u purgeable objects, %zu bytes\n",
394 purgeable_count, purgeable_size);
6299f992
CW		 395 seq_printf(m, "%u pinned mappable objects, %zu bytes\n",
396 mappable_count, mappable_size);
397 seq_printf(m, "%u fault mappable objects, %zu bytes\n",
398 count, size);
399
93d18799 400 seq_printf(m, "%zu [%lu] gtt total\n",
853ba5d2
BW		 401 dev_priv->gtt.base.total,
402 dev_priv->gtt.mappable_end - dev_priv->gtt.base.start);
73aa808f 403
267f0c90 404 seq_putc(m, '\n');
2db8e9d6
CW		 405 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
406 struct file_stats stats;
407
408 memset(&stats, 0, sizeof(stats));
409 idr_for_each(&file->object_idr, per_file_stats, &stats);
410 seq_printf(m, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu unbound)\n",
411 get_pid_task(file->pid, PIDTYPE_PID)->comm,
412 stats.count,
413 stats.total,
414 stats.active,
415 stats.inactive,
416 stats.unbound);
417 }
418
73aa808f
CW		 419 mutex_unlock(&dev->struct_mutex);
420
421 return 0;
422}
423
aee56cff 424static int i915_gem_gtt_info(struct seq_file *m, void *data)
08c18323
CW		 425{
426 struct drm_info_node *node = (struct drm_info_node *) m->private;
427 struct drm_device *dev = node->minor->dev;
1b50247a 428 uintptr_t list = (uintptr_t) node->info_ent->data;
08c18323
CW		 429 struct drm_i915_private *dev_priv = dev->dev_private;
430 struct drm_i915_gem_object *obj;
431 size_t total_obj_size, total_gtt_size;
432 int count, ret;
433
434 ret = mutex_lock_interruptible(&dev->struct_mutex);
435 if (ret)
436 return ret;
437
438 total_obj_size = total_gtt_size = count = 0;
35c20a60 439 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
1b50247a
CW		 440 if (list == PINNED_LIST && obj->pin_count == 0)
441 continue;
442
267f0c90 443 seq_puts(m, " ");
08c18323 444 describe_obj(m, obj);
267f0c90 445 seq_putc(m, '\n');
08c18323 446 total_obj_size += obj->base.size;
f343c5f6 447 total_gtt_size += i915_gem_obj_ggtt_size(obj);
08c18323
CW		 448 count++;
449 }
450
451 mutex_unlock(&dev->struct_mutex);
452
453 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
454 count, total_obj_size, total_gtt_size);
455
456 return 0;
457}
458
4e5359cd
SF		 459static int i915_gem_pageflip_info(struct seq_file *m, void *data)
460{
461 struct drm_info_node *node = (struct drm_info_node *) m->private;
462 struct drm_device *dev = node->minor->dev;
463 unsigned long flags;
464 struct intel_crtc *crtc;
465
466 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
9db4a9c7
JB		 467 const char pipe = pipe_name(crtc->pipe);
468 const char plane = plane_name(crtc->plane);
4e5359cd
SF		 469 struct intel_unpin_work *work;
470
471 spin_lock_irqsave(&dev->event_lock, flags);
472 work = crtc->unpin_work;
473 if (work == NULL) {
9db4a9c7 474 seq_printf(m, "No flip due on pipe %c (plane %c)\n",
4e5359cd
SF		 475 pipe, plane);
476 } else {
e7d841ca 477 if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9db4a9c7 478 seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
4e5359cd
SF		 479 pipe, plane);
480 } else {
9db4a9c7 481 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
4e5359cd
SF		 482 pipe, plane);
483 }
484 if (work->enable_stall_check)
267f0c90 485 seq_puts(m, "Stall check enabled, ");
4e5359cd 486 else
267f0c90 487 seq_puts(m, "Stall check waiting for page flip ioctl, ");
e7d841ca 488 seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
4e5359cd
SF		 489
490 if (work->old_fb_obj) {
05394f39
CW		 491 struct drm_i915_gem_object *obj = work->old_fb_obj;
492 if (obj)
f343c5f6
BW		 493 seq_printf(m, "Old framebuffer gtt_offset 0x%08lx\n",
494 i915_gem_obj_ggtt_offset(obj));
4e5359cd
SF		 495 }
496 if (work->pending_flip_obj) {
05394f39
CW		 497 struct drm_i915_gem_object *obj = work->pending_flip_obj;
498 if (obj)
f343c5f6
BW		 499 seq_printf(m, "New framebuffer gtt_offset 0x%08lx\n",
500 i915_gem_obj_ggtt_offset(obj));
4e5359cd
SF		 501 }
502 }
503 spin_unlock_irqrestore(&dev->event_lock, flags);
504 }
505
506 return 0;
507}
508
2017263e
BG		 509static int i915_gem_request_info(struct seq_file *m, void *data)
510{
511 struct drm_info_node *node = (struct drm_info_node *) m->private;
512 struct drm_device *dev = node->minor->dev;
513 drm_i915_private_t *dev_priv = dev->dev_private;
a2c7f6fd 514 struct intel_ring_buffer *ring;
2017263e 515 struct drm_i915_gem_request *gem_request;
a2c7f6fd 516 int ret, count, i;
de227ef0
CW		 517
518 ret = mutex_lock_interruptible(&dev->struct_mutex);
519 if (ret)
520 return ret;
2017263e 521
c2c347a9 522 count = 0;
a2c7f6fd
CW		 523 for_each_ring(ring, dev_priv, i) {
524 if (list_empty(&ring->request_list))
525 continue;
526
527 seq_printf(m, "%s requests:\n", ring->name);
c2c347a9 528 list_for_each_entry(gem_request,
a2c7f6fd 529 &ring->request_list,
c2c347a9
CW		 530 list) {
531 seq_printf(m, " %d @ %d\n",
532 gem_request->seqno,
533 (int) (jiffies - gem_request->emitted_jiffies));
534 }
535 count++;
2017263e 536 }
de227ef0
CW		 537 mutex_unlock(&dev->struct_mutex);
538
c2c347a9 539 if (count == 0)
267f0c90 540 seq_puts(m, "No requests\n");
c2c347a9 541
2017263e
BG		 542 return 0;
543}
544
b2223497
CW		 545static void i915_ring_seqno_info(struct seq_file *m,
546 struct intel_ring_buffer *ring)
547{
548 if (ring->get_seqno) {
43a7b924 549 seq_printf(m, "Current sequence (%s): %u\n",
b2eadbc8 550 ring->name, ring->get_seqno(ring, false));
b2223497
CW		 551 }
552}
553
2017263e
BG		 554static int i915_gem_seqno_info(struct seq_file *m, void *data)
555{
556 struct drm_info_node *node = (struct drm_info_node *) m->private;
557 struct drm_device *dev = node->minor->dev;
558 drm_i915_private_t *dev_priv = dev->dev_private;
a2c7f6fd 559 struct intel_ring_buffer *ring;
1ec14ad3 560 int ret, i;
de227ef0
CW		 561
562 ret = mutex_lock_interruptible(&dev->struct_mutex);
563 if (ret)
564 return ret;
c8c8fb33 565 intel_runtime_pm_get(dev_priv);
2017263e 566
a2c7f6fd
CW		 567 for_each_ring(ring, dev_priv, i)
568 i915_ring_seqno_info(m, ring);
de227ef0 569
c8c8fb33 570 intel_runtime_pm_put(dev_priv);
de227ef0
CW		 571 mutex_unlock(&dev->struct_mutex);
572
2017263e
BG		 573 return 0;
574}
575
576
577static int i915_interrupt_info(struct seq_file *m, void *data)
578{
579 struct drm_info_node *node = (struct drm_info_node *) m->private;
580 struct drm_device *dev = node->minor->dev;
581 drm_i915_private_t *dev_priv = dev->dev_private;
a2c7f6fd 582 struct intel_ring_buffer *ring;
9db4a9c7 583 int ret, i, pipe;
de227ef0
CW		 584
585 ret = mutex_lock_interruptible(&dev->struct_mutex);
586 if (ret)
587 return ret;
c8c8fb33 588 intel_runtime_pm_get(dev_priv);
2017263e 589
a123f157
BW		 590 if (INTEL_INFO(dev)->gen >= 8) {
591 int i;
592 seq_printf(m, "Master Interrupt Control:\t%08x\n",
593 I915_READ(GEN8_MASTER_IRQ));
594
595 for (i = 0; i < 4; i++) {
596 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
597 i, I915_READ(GEN8_GT_IMR(i)));
598 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
599 i, I915_READ(GEN8_GT_IIR(i)));
600 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
601 i, I915_READ(GEN8_GT_IER(i)));
602 }
603
604 for_each_pipe(i) {
605 seq_printf(m, "Pipe %c IMR:\t%08x\n",
606 pipe_name(i),
607 I915_READ(GEN8_DE_PIPE_IMR(i)));
608 seq_printf(m, "Pipe %c IIR:\t%08x\n",
609 pipe_name(i),
610 I915_READ(GEN8_DE_PIPE_IIR(i)));
611 seq_printf(m, "Pipe %c IER:\t%08x\n",
612 pipe_name(i),
613 I915_READ(GEN8_DE_PIPE_IER(i)));
614 }
615
616 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
617 I915_READ(GEN8_DE_PORT_IMR));
618 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
619 I915_READ(GEN8_DE_PORT_IIR));
620 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
621 I915_READ(GEN8_DE_PORT_IER));
622
623 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
624 I915_READ(GEN8_DE_MISC_IMR));
625 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
626 I915_READ(GEN8_DE_MISC_IIR));
627 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
628 I915_READ(GEN8_DE_MISC_IER));
629
630 seq_printf(m, "PCU interrupt mask:\t%08x\n",
631 I915_READ(GEN8_PCU_IMR));
632 seq_printf(m, "PCU interrupt identity:\t%08x\n",
633 I915_READ(GEN8_PCU_IIR));
634 seq_printf(m, "PCU interrupt enable:\t%08x\n",
635 I915_READ(GEN8_PCU_IER));
636 } else if (IS_VALLEYVIEW(dev)) {
7e231dbe
JB		 637 seq_printf(m, "Display IER:\t%08x\n",
638 I915_READ(VLV_IER));
639 seq_printf(m, "Display IIR:\t%08x\n",
640 I915_READ(VLV_IIR));
641 seq_printf(m, "Display IIR_RW:\t%08x\n",
642 I915_READ(VLV_IIR_RW));
643 seq_printf(m, "Display IMR:\t%08x\n",
644 I915_READ(VLV_IMR));
645 for_each_pipe(pipe)
646 seq_printf(m, "Pipe %c stat:\t%08x\n",
647 pipe_name(pipe),
648 I915_READ(PIPESTAT(pipe)));
649
650 seq_printf(m, "Master IER:\t%08x\n",
651 I915_READ(VLV_MASTER_IER));
652
653 seq_printf(m, "Render IER:\t%08x\n",
654 I915_READ(GTIER));
655 seq_printf(m, "Render IIR:\t%08x\n",
656 I915_READ(GTIIR));
657 seq_printf(m, "Render IMR:\t%08x\n",
658 I915_READ(GTIMR));
659
660 seq_printf(m, "PM IER:\t\t%08x\n",
661 I915_READ(GEN6_PMIER));
662 seq_printf(m, "PM IIR:\t\t%08x\n",
663 I915_READ(GEN6_PMIIR));
664 seq_printf(m, "PM IMR:\t\t%08x\n",
665 I915_READ(GEN6_PMIMR));
666
667 seq_printf(m, "Port hotplug:\t%08x\n",
668 I915_READ(PORT_HOTPLUG_EN));
669 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
670 I915_READ(VLV_DPFLIPSTAT));
671 seq_printf(m, "DPINVGTT:\t%08x\n",
672 I915_READ(DPINVGTT));
673
674 } else if (!HAS_PCH_SPLIT(dev)) {
5f6a1695
ZW		 675 seq_printf(m, "Interrupt enable: %08x\n",
676 I915_READ(IER));
677 seq_printf(m, "Interrupt identity: %08x\n",
678 I915_READ(IIR));
679 seq_printf(m, "Interrupt mask: %08x\n",
680 I915_READ(IMR));
9db4a9c7
JB		 681 for_each_pipe(pipe)
682 seq_printf(m, "Pipe %c stat: %08x\n",
683 pipe_name(pipe),
684 I915_READ(PIPESTAT(pipe)));
5f6a1695
ZW		 685 } else {
686 seq_printf(m, "North Display Interrupt enable: %08x\n",
687 I915_READ(DEIER));
688 seq_printf(m, "North Display Interrupt identity: %08x\n",
689 I915_READ(DEIIR));
690 seq_printf(m, "North Display Interrupt mask: %08x\n",
691 I915_READ(DEIMR));
692 seq_printf(m, "South Display Interrupt enable: %08x\n",
693 I915_READ(SDEIER));
694 seq_printf(m, "South Display Interrupt identity: %08x\n",
695 I915_READ(SDEIIR));
696 seq_printf(m, "South Display Interrupt mask: %08x\n",
697 I915_READ(SDEIMR));
698 seq_printf(m, "Graphics Interrupt enable: %08x\n",
699 I915_READ(GTIER));
700 seq_printf(m, "Graphics Interrupt identity: %08x\n",
701 I915_READ(GTIIR));
702 seq_printf(m, "Graphics Interrupt mask: %08x\n",
703 I915_READ(GTIMR));
704 }
2017263e
BG		 705 seq_printf(m, "Interrupts received: %d\n",
706 atomic_read(&dev_priv->irq_received));
a2c7f6fd 707 for_each_ring(ring, dev_priv, i) {
a123f157 708 if (INTEL_INFO(dev)->gen >= 6) {
a2c7f6fd
CW		 709 seq_printf(m,
710 "Graphics Interrupt mask (%s): %08x\n",
711 ring->name, I915_READ_IMR(ring));
9862e600 712 }
a2c7f6fd 713 i915_ring_seqno_info(m, ring);
9862e600 714 }
c8c8fb33 715 intel_runtime_pm_put(dev_priv);
de227ef0
CW		 716 mutex_unlock(&dev->struct_mutex);
717
2017263e
BG		 718 return 0;
719}
720
a6172a80
CW		 721static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
722{
723 struct drm_info_node *node = (struct drm_info_node *) m->private;
724 struct drm_device *dev = node->minor->dev;
725 drm_i915_private_t *dev_priv = dev->dev_private;
de227ef0
CW		 726 int i, ret;
727
728 ret = mutex_lock_interruptible(&dev->struct_mutex);
729 if (ret)
730 return ret;
a6172a80
CW		 731
732 seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
733 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
734 for (i = 0; i < dev_priv->num_fence_regs; i++) {
05394f39 735 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
a6172a80 736
6c085a72
CW		 737 seq_printf(m, "Fence %d, pin count = %d, object = ",
738 i, dev_priv->fence_regs[i].pin_count);
c2c347a9 739 if (obj == NULL)
267f0c90 740 seq_puts(m, "unused");
c2c347a9 741 else
05394f39 742 describe_obj(m, obj);
267f0c90 743 seq_putc(m, '\n');
a6172a80
CW		 744 }
745
05394f39 746 mutex_unlock(&dev->struct_mutex);
a6172a80
CW		 747 return 0;
748}
749
2017263e
BG		 750static int i915_hws_info(struct seq_file *m, void *data)
751{
752 struct drm_info_node *node = (struct drm_info_node *) m->private;
753 struct drm_device *dev = node->minor->dev;
754 drm_i915_private_t *dev_priv = dev->dev_private;
4066c0ae 755 struct intel_ring_buffer *ring;
1a240d4d 756 const u32 *hws;
4066c0ae
CW		 757 int i;
758
1ec14ad3 759 ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
1a240d4d 760 hws = ring->status_page.page_addr;
2017263e
BG		 761 if (hws == NULL)
762 return 0;
763
764 for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
765 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
766 i * 4,
767 hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
768 }
769 return 0;
770}
771
d5442303
DV		 772static ssize_t
773i915_error_state_write(struct file *filp,
774 const char __user *ubuf,
775 size_t cnt,
776 loff_t *ppos)
777{
edc3d884 778 struct i915_error_state_file_priv *error_priv = filp->private_data;
d5442303 779 struct drm_device *dev = error_priv->dev;
22bcfc6a 780 int ret;
d5442303
DV		 781
782 DRM_DEBUG_DRIVER("Resetting error state\n");
783
22bcfc6a
DV		 784 ret = mutex_lock_interruptible(&dev->struct_mutex);
785 if (ret)
786 return ret;
787
d5442303
DV		 788 i915_destroy_error_state(dev);
789 mutex_unlock(&dev->struct_mutex);
790
791 return cnt;
792}
793
794static int i915_error_state_open(struct inode *inode, struct file *file)
795{
796 struct drm_device *dev = inode->i_private;
d5442303 797 struct i915_error_state_file_priv *error_priv;
d5442303
DV		 798
799 error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
800 if (!error_priv)
801 return -ENOMEM;
802
803 error_priv->dev = dev;
804
95d5bfb3 805 i915_error_state_get(dev, error_priv);
d5442303 806
edc3d884
MK		 807 file->private_data = error_priv;
808
809 return 0;
d5442303
DV		 810}
811
812static int i915_error_state_release(struct inode *inode, struct file *file)
813{
edc3d884 814 struct i915_error_state_file_priv *error_priv = file->private_data;
d5442303 815
95d5bfb3 816 i915_error_state_put(error_priv);
d5442303
DV		 817 kfree(error_priv);
818
edc3d884
MK		 819 return 0;
820}
821
4dc955f7
MK		 822static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
823 size_t count, loff_t *pos)
824{
825 struct i915_error_state_file_priv *error_priv = file->private_data;
826 struct drm_i915_error_state_buf error_str;
827 loff_t tmp_pos = 0;
828 ssize_t ret_count = 0;
829 int ret;
830
831 ret = i915_error_state_buf_init(&error_str, count, *pos);
832 if (ret)
833 return ret;
edc3d884 834
fc16b48b 835 ret = i915_error_state_to_str(&error_str, error_priv);
edc3d884
MK		 836 if (ret)
837 goto out;
838
edc3d884
MK		 839 ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
840 error_str.buf,
841 error_str.bytes);
842
843 if (ret_count < 0)
844 ret = ret_count;
845 else
846 *pos = error_str.start + ret_count;
847out:
4dc955f7 848 i915_error_state_buf_release(&error_str);
edc3d884 849 return ret ?: ret_count;
d5442303
DV		 850}
851
852static const struct file_operations i915_error_state_fops = {
853 .owner = THIS_MODULE,
854 .open = i915_error_state_open,
edc3d884 855 .read = i915_error_state_read,
d5442303
DV		 856 .write = i915_error_state_write,
857 .llseek = default_llseek,
858 .release = i915_error_state_release,
859};
860
647416f9
KC		 861static int
862i915_next_seqno_get(void *data, u64 *val)
40633219 863{
647416f9 864 struct drm_device *dev = data;
40633219 865 drm_i915_private_t *dev_priv = dev->dev_private;
40633219
MK		 866 int ret;
867
868 ret = mutex_lock_interruptible(&dev->struct_mutex);
869 if (ret)
870 return ret;
871
647416f9 872 *val = dev_priv->next_seqno;
40633219
MK		 873 mutex_unlock(&dev->struct_mutex);
874
647416f9 875 return 0;
40633219
MK		 876}
877
647416f9
KC		 878static int
879i915_next_seqno_set(void *data, u64 val)
880{
881 struct drm_device *dev = data;
40633219
MK		 882 int ret;
883
40633219
MK		 884 ret = mutex_lock_interruptible(&dev->struct_mutex);
885 if (ret)
886 return ret;
887
e94fbaa8 888 ret = i915_gem_set_seqno(dev, val);
40633219
MK		 889 mutex_unlock(&dev->struct_mutex);
890
647416f9 891 return ret;
40633219
MK		 892}
893
647416f9
KC		 894DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
895 i915_next_seqno_get, i915_next_seqno_set,
3a3b4f98 896 "0x%llx\n");
40633219 897
f97108d1
JB		 898static int i915_rstdby_delays(struct seq_file *m, void *unused)
899{
900 struct drm_info_node *node = (struct drm_info_node *) m->private;
901 struct drm_device *dev = node->minor->dev;
902 drm_i915_private_t *dev_priv = dev->dev_private;
616fdb5a
BW		 903 u16 crstanddelay;
904 int ret;
905
906 ret = mutex_lock_interruptible(&dev->struct_mutex);
907 if (ret)
908 return ret;
c8c8fb33 909 intel_runtime_pm_get(dev_priv);
616fdb5a
BW		 910
911 crstanddelay = I915_READ16(CRSTANDVID);
912
c8c8fb33 913 intel_runtime_pm_put(dev_priv);
616fdb5a 914 mutex_unlock(&dev->struct_mutex);
f97108d1
JB		 915
916 seq_printf(m, "w/ctx: %d, w/o ctx: %d\n", (crstanddelay >> 8) & 0x3f, (crstanddelay & 0x3f));
917
918 return 0;
919}
920
921static int i915_cur_delayinfo(struct seq_file *m, void *unused)
922{
923 struct drm_info_node *node = (struct drm_info_node *) m->private;
924 struct drm_device *dev = node->minor->dev;
925 drm_i915_private_t *dev_priv = dev->dev_private;
c8c8fb33
PZ		 926 int ret = 0;
927
928 intel_runtime_pm_get(dev_priv);
3b8d8d91 929
5c9669ce
TR		 930 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
931
3b8d8d91
JB		 932 if (IS_GEN5(dev)) {
933 u16 rgvswctl = I915_READ16(MEMSWCTL);
934 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
935
936 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
937 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
938 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
939 MEMSTAT_VID_SHIFT);
940 seq_printf(m, "Current P-state: %d\n",
941 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
0a073b84 942 } else if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) {
3b8d8d91
JB		 943 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
944 u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
945 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
8e8c06cd 946 u32 rpstat, cagf, reqf;
ccab5c82
JB		 947 u32 rpupei, rpcurup, rpprevup;
948 u32 rpdownei, rpcurdown, rpprevdown;
3b8d8d91
JB		 949 int max_freq;
950
951 /* RPSTAT1 is in the GT power well */
d1ebd816
BW		 952 ret = mutex_lock_interruptible(&dev->struct_mutex);
953 if (ret)
c8c8fb33 954 goto out;
d1ebd816 955
c8d9a590 956 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3b8d8d91 957
8e8c06cd
CW		 958 reqf = I915_READ(GEN6_RPNSWREQ);
959 reqf &= ~GEN6_TURBO_DISABLE;
960 if (IS_HASWELL(dev))
961 reqf >>= 24;
962 else
963 reqf >>= 25;
964 reqf *= GT_FREQUENCY_MULTIPLIER;
965
ccab5c82
JB		 966 rpstat = I915_READ(GEN6_RPSTAT1);
967 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
968 rpcurup = I915_READ(GEN6_RP_CUR_UP);
969 rpprevup = I915_READ(GEN6_RP_PREV_UP);
970 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
971 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
972 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
f82855d3
BW		 973 if (IS_HASWELL(dev))
974 cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
975 else
976 cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
977 cagf *= GT_FREQUENCY_MULTIPLIER;
ccab5c82 978
c8d9a590 979 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
d1ebd816
BW		 980 mutex_unlock(&dev->struct_mutex);
981
3b8d8d91 982 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
ccab5c82 983 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
3b8d8d91
JB		 984 seq_printf(m, "Render p-state ratio: %d\n",
985 (gt_perf_status & 0xff00) >> 8);
986 seq_printf(m, "Render p-state VID: %d\n",
987 gt_perf_status & 0xff);
988 seq_printf(m, "Render p-state limit: %d\n",
989 rp_state_limits & 0xff);
8e8c06cd 990 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
f82855d3 991 seq_printf(m, "CAGF: %dMHz\n", cagf);
ccab5c82
JB		 992 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
993 GEN6_CURICONT_MASK);
994 seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
995 GEN6_CURBSYTAVG_MASK);
996 seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
997 GEN6_CURBSYTAVG_MASK);
998 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
999 GEN6_CURIAVG_MASK);
1000 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
1001 GEN6_CURBSYTAVG_MASK);
1002 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
1003 GEN6_CURBSYTAVG_MASK);
3b8d8d91
JB		 1004
1005 max_freq = (rp_state_cap & 0xff0000) >> 16;
1006 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
c8735b0c 1007 max_freq * GT_FREQUENCY_MULTIPLIER);
3b8d8d91
JB		 1008
1009 max_freq = (rp_state_cap & 0xff00) >> 8;
1010 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
c8735b0c 1011 max_freq * GT_FREQUENCY_MULTIPLIER);
3b8d8d91
JB		 1012
1013 max_freq = rp_state_cap & 0xff;
1014 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
c8735b0c 1015 max_freq * GT_FREQUENCY_MULTIPLIER);
31c77388
BW		 1016
1017 seq_printf(m, "Max overclocked frequency: %dMHz\n",
1018 dev_priv->rps.hw_max * GT_FREQUENCY_MULTIPLIER);
0a073b84
JB		 1019 } else if (IS_VALLEYVIEW(dev)) {
1020 u32 freq_sts, val;
1021
259bd5d4 1022 mutex_lock(&dev_priv->rps.hw_lock);
64936258 1023 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
0a073b84
JB		 1024 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1025 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1026
c5bd2bf6 1027 val = valleyview_rps_max_freq(dev_priv);
0a073b84 1028 seq_printf(m, "max GPU freq: %d MHz\n",
2ec3815f 1029 vlv_gpu_freq(dev_priv, val));
0a073b84 1030
c5bd2bf6 1031 val = valleyview_rps_min_freq(dev_priv);
0a073b84 1032 seq_printf(m, "min GPU freq: %d MHz\n",
2ec3815f 1033 vlv_gpu_freq(dev_priv, val));
0a073b84
JB		 1034
1035 seq_printf(m, "current GPU freq: %d MHz\n",
2ec3815f 1036 vlv_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
259bd5d4 1037 mutex_unlock(&dev_priv->rps.hw_lock);
3b8d8d91 1038 } else {
267f0c90 1039 seq_puts(m, "no P-state info available\n");
3b8d8d91 1040 }
f97108d1 1041
c8c8fb33
PZ		 1042out:
1043 intel_runtime_pm_put(dev_priv);
1044 return ret;
f97108d1
JB		 1045}
1046
1047static int i915_delayfreq_table(struct seq_file *m, void *unused)
1048{
1049 struct drm_info_node *node = (struct drm_info_node *) m->private;
1050 struct drm_device *dev = node->minor->dev;
1051 drm_i915_private_t *dev_priv = dev->dev_private;
1052 u32 delayfreq;
616fdb5a
BW		 1053 int ret, i;
1054
1055 ret = mutex_lock_interruptible(&dev->struct_mutex);
1056 if (ret)
1057 return ret;
c8c8fb33 1058 intel_runtime_pm_get(dev_priv);
f97108d1
JB		 1059
1060 for (i = 0; i < 16; i++) {
1061 delayfreq = I915_READ(PXVFREQ_BASE + i * 4);
7648fa99
JB		 1062 seq_printf(m, "P%02dVIDFREQ: 0x%08x (VID: %d)\n", i, delayfreq,
1063 (delayfreq & PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT);
f97108d1
JB		 1064 }
1065
c8c8fb33
PZ		 1066 intel_runtime_pm_put(dev_priv);
1067
616fdb5a
BW		 1068 mutex_unlock(&dev->struct_mutex);
1069
f97108d1
JB		 1070 return 0;
1071}
1072
1073static inline int MAP_TO_MV(int map)
1074{
1075 return 1250 - (map * 25);
1076}
1077
1078static int i915_inttoext_table(struct seq_file *m, void *unused)
1079{
1080 struct drm_info_node *node = (struct drm_info_node *) m->private;
1081 struct drm_device *dev = node->minor->dev;
1082 drm_i915_private_t *dev_priv = dev->dev_private;
1083 u32 inttoext;
616fdb5a
BW		 1084 int ret, i;
1085
1086 ret = mutex_lock_interruptible(&dev->struct_mutex);
1087 if (ret)
1088 return ret;
c8c8fb33 1089 intel_runtime_pm_get(dev_priv);
f97108d1
JB		 1090
1091 for (i = 1; i <= 32; i++) {
1092 inttoext = I915_READ(INTTOEXT_BASE_ILK + i * 4);
1093 seq_printf(m, "INTTOEXT%02d: 0x%08x\n", i, inttoext);
1094 }
1095
c8c8fb33 1096 intel_runtime_pm_put(dev_priv);
616fdb5a
BW		 1097 mutex_unlock(&dev->struct_mutex);
1098
f97108d1
JB		 1099 return 0;
1100}
1101
4d85529d 1102static int ironlake_drpc_info(struct seq_file *m)
f97108d1
JB		 1103{
1104 struct drm_info_node *node = (struct drm_info_node *) m->private;
1105 struct drm_device *dev = node->minor->dev;
1106 drm_i915_private_t *dev_priv = dev->dev_private;
616fdb5a
BW		 1107 u32 rgvmodectl, rstdbyctl;
1108 u16 crstandvid;
1109 int ret;
1110
1111 ret = mutex_lock_interruptible(&dev->struct_mutex);
1112 if (ret)
1113 return ret;
c8c8fb33 1114 intel_runtime_pm_get(dev_priv);
616fdb5a
BW		 1115
1116 rgvmodectl = I915_READ(MEMMODECTL);
1117 rstdbyctl = I915_READ(RSTDBYCTL);
1118 crstandvid = I915_READ16(CRSTANDVID);
1119
c8c8fb33 1120 intel_runtime_pm_put(dev_priv);
616fdb5a 1121 mutex_unlock(&dev->struct_mutex);
f97108d1
JB		 1122
1123 seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
1124 "yes" : "no");
1125 seq_printf(m, "Boost freq: %d\n",
1126 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1127 MEMMODE_BOOST_FREQ_SHIFT);
1128 seq_printf(m, "HW control enabled: %s\n",
1129 rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");
1130 seq_printf(m, "SW control enabled: %s\n",
1131 rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");
1132 seq_printf(m, "Gated voltage change: %s\n",
1133 rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");
1134 seq_printf(m, "Starting frequency: P%d\n",
1135 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
7648fa99 1136 seq_printf(m, "Max P-state: P%d\n",
f97108d1 1137 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
7648fa99
JB		 1138 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1139 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1140 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1141 seq_printf(m, "Render standby enabled: %s\n",
1142 (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes");
267f0c90 1143 seq_puts(m, "Current RS state: ");
88271da3
JB		 1144 switch (rstdbyctl & RSX_STATUS_MASK) {
1145 case RSX_STATUS_ON:
267f0c90 1146 seq_puts(m, "on\n");
88271da3
JB		 1147 break;
1148 case RSX_STATUS_RC1:
267f0c90 1149 seq_puts(m, "RC1\n");
88271da3
JB		 1150 break;
1151 case RSX_STATUS_RC1E:
267f0c90 1152 seq_puts(m, "RC1E\n");
88271da3
JB		 1153 break;
1154 case RSX_STATUS_RS1:
267f0c90 1155 seq_puts(m, "RS1\n");
88271da3
JB		 1156 break;
1157 case RSX_STATUS_RS2:
267f0c90 1158 seq_puts(m, "RS2 (RC6)\n");
88271da3
JB		 1159 break;
1160 case RSX_STATUS_RS3:
267f0c90 1161 seq_puts(m, "RC3 (RC6+)\n");
88271da3
JB		 1162 break;
1163 default:
267f0c90 1164 seq_puts(m, "unknown\n");
88271da3
JB		 1165 break;
1166 }
f97108d1
JB		 1167
1168 return 0;
1169}
1170
4d85529d
BW		 1171static int gen6_drpc_info(struct seq_file *m)
1172{
1173
1174 struct drm_info_node *node = (struct drm_info_node *) m->private;
1175 struct drm_device *dev = node->minor->dev;
1176 struct drm_i915_private *dev_priv = dev->dev_private;
ecd8faea 1177 u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
93b525dc 1178 unsigned forcewake_count;
aee56cff 1179 int count = 0, ret;
4d85529d
BW		 1180
1181 ret = mutex_lock_interruptible(&dev->struct_mutex);
1182 if (ret)
1183 return ret;
c8c8fb33 1184 intel_runtime_pm_get(dev_priv);
4d85529d 1185
907b28c5
CW		 1186 spin_lock_irq(&dev_priv->uncore.lock);
1187 forcewake_count = dev_priv->uncore.forcewake_count;
1188 spin_unlock_irq(&dev_priv->uncore.lock);
93b525dc
DV		 1189
1190 if (forcewake_count) {
267f0c90
DL		 1191 seq_puts(m, "RC information inaccurate because somebody "
1192 "holds a forcewake reference \n");
4d85529d
BW		 1193 } else {
1194 /* NB: we cannot use forcewake, else we read the wrong values */
1195 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1196 udelay(10);
1197 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1198 }
1199
1200 gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS);
ed71f1b4 1201 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
4d85529d
BW		 1202
1203 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1204 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1205 mutex_unlock(&dev->struct_mutex);
44cbd338
BW		 1206 mutex_lock(&dev_priv->rps.hw_lock);
1207 sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1208 mutex_unlock(&dev_priv->rps.hw_lock);
4d85529d 1209
c8c8fb33
PZ		 1210 intel_runtime_pm_put(dev_priv);
1211
4d85529d
BW		 1212 seq_printf(m, "Video Turbo Mode: %s\n",
1213 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1214 seq_printf(m, "HW control enabled: %s\n",
1215 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1216 seq_printf(m, "SW control enabled: %s\n",
1217 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1218 GEN6_RP_MEDIA_SW_MODE));
fff24e21 1219 seq_printf(m, "RC1e Enabled: %s\n",
4d85529d
BW		 1220 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1221 seq_printf(m, "RC6 Enabled: %s\n",
1222 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1223 seq_printf(m, "Deep RC6 Enabled: %s\n",
1224 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1225 seq_printf(m, "Deepest RC6 Enabled: %s\n",
1226 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
267f0c90 1227 seq_puts(m, "Current RC state: ");
4d85529d
BW		 1228 switch (gt_core_status & GEN6_RCn_MASK) {
1229 case GEN6_RC0:
1230 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
267f0c90 1231 seq_puts(m, "Core Power Down\n");
4d85529d 1232 else
267f0c90 1233 seq_puts(m, "on\n");
4d85529d
BW		 1234 break;
1235 case GEN6_RC3:
267f0c90 1236 seq_puts(m, "RC3\n");
4d85529d
BW		 1237 break;
1238 case GEN6_RC6:
267f0c90 1239 seq_puts(m, "RC6\n");
4d85529d
BW		 1240 break;
1241 case GEN6_RC7:
267f0c90 1242 seq_puts(m, "RC7\n");
4d85529d
BW		 1243 break;
1244 default:
267f0c90 1245 seq_puts(m, "Unknown\n");
4d85529d
BW		 1246 break;
1247 }
1248
1249 seq_printf(m, "Core Power Down: %s\n",
1250 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
cce66a28
BW		 1251
1252 /* Not exactly sure what this is */
1253 seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1254 I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1255 seq_printf(m, "RC6 residency since boot: %u\n",
1256 I915_READ(GEN6_GT_GFX_RC6));
1257 seq_printf(m, "RC6+ residency since boot: %u\n",
1258 I915_READ(GEN6_GT_GFX_RC6p));
1259 seq_printf(m, "RC6++ residency since boot: %u\n",
1260 I915_READ(GEN6_GT_GFX_RC6pp));
1261
ecd8faea
BW		 1262 seq_printf(m, "RC6 voltage: %dmV\n",
1263 GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1264 seq_printf(m, "RC6+ voltage: %dmV\n",
1265 GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1266 seq_printf(m, "RC6++ voltage: %dmV\n",
1267 GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
4d85529d
BW		 1268 return 0;
1269}
1270
1271static int i915_drpc_info(struct seq_file *m, void *unused)
1272{
1273 struct drm_info_node *node = (struct drm_info_node *) m->private;
1274 struct drm_device *dev = node->minor->dev;
1275
1276 if (IS_GEN6(dev) || IS_GEN7(dev))
1277 return gen6_drpc_info(m);
1278 else
1279 return ironlake_drpc_info(m);
1280}
1281
b5e50c3f
JB		 1282static int i915_fbc_status(struct seq_file *m, void *unused)
1283{
1284 struct drm_info_node *node = (struct drm_info_node *) m->private;
1285 struct drm_device *dev = node->minor->dev;
b5e50c3f 1286 drm_i915_private_t *dev_priv = dev->dev_private;
b5e50c3f 1287
ee5382ae 1288 if (!I915_HAS_FBC(dev)) {
267f0c90 1289 seq_puts(m, "FBC unsupported on this chipset\n");
b5e50c3f
JB		 1290 return 0;
1291 }
1292
ee5382ae 1293 if (intel_fbc_enabled(dev)) {
267f0c90 1294 seq_puts(m, "FBC enabled\n");
b5e50c3f 1295 } else {
267f0c90 1296 seq_puts(m, "FBC disabled: ");
5c3fe8b0 1297 switch (dev_priv->fbc.no_fbc_reason) {
29ebf90f
CW		 1298 case FBC_OK:
1299 seq_puts(m, "FBC actived, but currently disabled in hardware");
1300 break;
1301 case FBC_UNSUPPORTED:
1302 seq_puts(m, "unsupported by this chipset");
1303 break;
bed4a673 1304 case FBC_NO_OUTPUT:
267f0c90 1305 seq_puts(m, "no outputs");
bed4a673 1306 break;
b5e50c3f 1307 case FBC_STOLEN_TOO_SMALL:
267f0c90 1308 seq_puts(m, "not enough stolen memory");
b5e50c3f
JB		 1309 break;
1310 case FBC_UNSUPPORTED_MODE:
267f0c90 1311 seq_puts(m, "mode not supported");
b5e50c3f
JB		 1312 break;
1313 case FBC_MODE_TOO_LARGE:
267f0c90 1314 seq_puts(m, "mode too large");
b5e50c3f
JB		 1315 break;
1316 case FBC_BAD_PLANE:
267f0c90 1317 seq_puts(m, "FBC unsupported on plane");
b5e50c3f
JB		 1318 break;
1319 case FBC_NOT_TILED:
267f0c90 1320 seq_puts(m, "scanout buffer not tiled");
b5e50c3f 1321 break;
9c928d16 1322 case FBC_MULTIPLE_PIPES:
267f0c90 1323 seq_puts(m, "multiple pipes are enabled");
9c928d16 1324 break;
c1a9f047 1325 case FBC_MODULE_PARAM:
267f0c90 1326 seq_puts(m, "disabled per module param (default off)");
c1a9f047 1327 break;
8a5729a3 1328 case FBC_CHIP_DEFAULT:
267f0c90 1329 seq_puts(m, "disabled per chip default");
8a5729a3 1330 break;
b5e50c3f 1331 default:
267f0c90 1332 seq_puts(m, "unknown reason");
b5e50c3f 1333 }
267f0c90 1334 seq_putc(m, '\n');
b5e50c3f
JB		 1335 }
1336 return 0;
1337}
1338
92d44621
PZ		 1339static int i915_ips_status(struct seq_file *m, void *unused)
1340{
1341 struct drm_info_node *node = (struct drm_info_node *) m->private;
1342 struct drm_device *dev = node->minor->dev;
1343 struct drm_i915_private *dev_priv = dev->dev_private;
1344
f5adf94e 1345 if (!HAS_IPS(dev)) {
92d44621
PZ		 1346 seq_puts(m, "not supported\n");
1347 return 0;
1348 }
1349
1350 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1351 seq_puts(m, "enabled\n");
1352 else
1353 seq_puts(m, "disabled\n");
1354
1355 return 0;
1356}
1357
4a9bef37
JB		 1358static int i915_sr_status(struct seq_file *m, void *unused)
1359{
1360 struct drm_info_node *node = (struct drm_info_node *) m->private;
1361 struct drm_device *dev = node->minor->dev;
1362 drm_i915_private_t *dev_priv = dev->dev_private;
1363 bool sr_enabled = false;
1364
1398261a 1365 if (HAS_PCH_SPLIT(dev))
5ba2aaaa 1366 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
a6c45cf0 1367 else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))
4a9bef37
JB		 1368 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1369 else if (IS_I915GM(dev))
1370 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1371 else if (IS_PINEVIEW(dev))
1372 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1373
5ba2aaaa
CW		 1374 seq_printf(m, "self-refresh: %s\n",
1375 sr_enabled ? "enabled" : "disabled");
4a9bef37
JB		 1376
1377 return 0;
1378}
1379
7648fa99
JB		 1380static int i915_emon_status(struct seq_file *m, void *unused)
1381{
1382 struct drm_info_node *node = (struct drm_info_node *) m->private;
1383 struct drm_device *dev = node->minor->dev;
1384 drm_i915_private_t *dev_priv = dev->dev_private;
1385 unsigned long temp, chipset, gfx;
de227ef0
CW		 1386 int ret;
1387
582be6b4
CW		 1388 if (!IS_GEN5(dev))
1389 return -ENODEV;
1390
de227ef0
CW		 1391 ret = mutex_lock_interruptible(&dev->struct_mutex);
1392 if (ret)
1393 return ret;
7648fa99
JB		 1394
1395 temp = i915_mch_val(dev_priv);
1396 chipset = i915_chipset_val(dev_priv);
1397 gfx = i915_gfx_val(dev_priv);
de227ef0 1398 mutex_unlock(&dev->struct_mutex);
7648fa99
JB		 1399
1400 seq_printf(m, "GMCH temp: %ld\n", temp);
1401 seq_printf(m, "Chipset power: %ld\n", chipset);
1402 seq_printf(m, "GFX power: %ld\n", gfx);
1403 seq_printf(m, "Total power: %ld\n", chipset + gfx);
1404
1405 return 0;
1406}
1407
23b2f8bb
JB		 1408static int i915_ring_freq_table(struct seq_file *m, void *unused)
1409{
1410 struct drm_info_node *node = (struct drm_info_node *) m->private;
1411 struct drm_device *dev = node->minor->dev;
1412 drm_i915_private_t *dev_priv = dev->dev_private;
1413 int ret;
1414 int gpu_freq, ia_freq;
1415
1c70c0ce 1416 if (!(IS_GEN6(dev) || IS_GEN7(dev))) {
267f0c90 1417 seq_puts(m, "unsupported on this chipset\n");
23b2f8bb
JB		 1418 return 0;
1419 }
1420
5c9669ce
TR		 1421 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1422
4fc688ce 1423 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
23b2f8bb
JB		 1424 if (ret)
1425 return ret;
c8c8fb33 1426 intel_runtime_pm_get(dev_priv);
23b2f8bb 1427
267f0c90 1428 seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
23b2f8bb 1429
c6a828d3
DV		 1430 for (gpu_freq = dev_priv->rps.min_delay;
1431 gpu_freq <= dev_priv->rps.max_delay;
23b2f8bb 1432 gpu_freq++) {
42c0526c
BW		 1433 ia_freq = gpu_freq;
1434 sandybridge_pcode_read(dev_priv,
1435 GEN6_PCODE_READ_MIN_FREQ_TABLE,
1436 &ia_freq);
3ebecd07
CW		 1437 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1438 gpu_freq * GT_FREQUENCY_MULTIPLIER,
1439 ((ia_freq >> 0) & 0xff) * 100,
1440 ((ia_freq >> 8) & 0xff) * 100);
23b2f8bb
JB		 1441 }
1442
c8c8fb33 1443 intel_runtime_pm_put(dev_priv);
4fc688ce 1444 mutex_unlock(&dev_priv->rps.hw_lock);
23b2f8bb
JB		 1445
1446 return 0;
1447}
1448
7648fa99
JB		 1449static int i915_gfxec(struct seq_file *m, void *unused)
1450{
1451 struct drm_info_node *node = (struct drm_info_node *) m->private;
1452 struct drm_device *dev = node->minor->dev;
1453 drm_i915_private_t *dev_priv = dev->dev_private;
616fdb5a
BW		 1454 int ret;
1455
1456 ret = mutex_lock_interruptible(&dev->struct_mutex);
1457 if (ret)
1458 return ret;
c8c8fb33 1459 intel_runtime_pm_get(dev_priv);
7648fa99
JB		 1460
1461 seq_printf(m, "GFXEC: %ld\n", (unsigned long)I915_READ(0x112f4));
c8c8fb33 1462 intel_runtime_pm_put(dev_priv);
7648fa99 1463
616fdb5a
BW		 1464 mutex_unlock(&dev->struct_mutex);
1465
7648fa99
JB		 1466 return 0;
1467}
1468
44834a67
CW		 1469static int i915_opregion(struct seq_file *m, void *unused)
1470{
1471 struct drm_info_node *node = (struct drm_info_node *) m->private;
1472 struct drm_device *dev = node->minor->dev;
1473 drm_i915_private_t *dev_priv = dev->dev_private;
1474 struct intel_opregion *opregion = &dev_priv->opregion;
0d38f009 1475 void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL);
44834a67
CW		 1476 int ret;
1477
0d38f009
DV		 1478 if (data == NULL)
1479 return -ENOMEM;
1480
44834a67
CW		 1481 ret = mutex_lock_interruptible(&dev->struct_mutex);
1482 if (ret)
0d38f009 1483 goto out;
44834a67 1484
0d38f009
DV		 1485 if (opregion->header) {
1486 memcpy_fromio(data, opregion->header, OPREGION_SIZE);
1487 seq_write(m, data, OPREGION_SIZE);
1488 }
44834a67
CW		 1489
1490 mutex_unlock(&dev->struct_mutex);
1491
0d38f009
DV		 1492out:
1493 kfree(data);
44834a67
CW		 1494 return 0;
1495}
1496
37811fcc
CW		 1497static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1498{
1499 struct drm_info_node *node = (struct drm_info_node *) m->private;
1500 struct drm_device *dev = node->minor->dev;
4520f53a 1501 struct intel_fbdev *ifbdev = NULL;
37811fcc 1502 struct intel_framebuffer *fb;
37811fcc 1503
4520f53a
DV		 1504#ifdef CONFIG_DRM_I915_FBDEV
1505 struct drm_i915_private *dev_priv = dev->dev_private;
1506 int ret = mutex_lock_interruptible(&dev->mode_config.mutex);
37811fcc
CW		 1507 if (ret)
1508 return ret;
1509
1510 ifbdev = dev_priv->fbdev;
1511 fb = to_intel_framebuffer(ifbdev->helper.fb);
1512
623f9783 1513 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
37811fcc
CW		 1514 fb->base.width,
1515 fb->base.height,
1516 fb->base.depth,
623f9783
DV		 1517 fb->base.bits_per_pixel,
1518 atomic_read(&fb->base.refcount.refcount));
05394f39 1519 describe_obj(m, fb->obj);
267f0c90 1520 seq_putc(m, '\n');
4b096ac1 1521 mutex_unlock(&dev->mode_config.mutex);
4520f53a 1522#endif
37811fcc 1523
4b096ac1 1524 mutex_lock(&dev->mode_config.fb_lock);
37811fcc 1525 list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) {
131a56dc 1526 if (ifbdev && &fb->base == ifbdev->helper.fb)
37811fcc
CW		 1527 continue;
1528
623f9783 1529 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
37811fcc
CW		 1530 fb->base.width,
1531 fb->base.height,
1532 fb->base.depth,
623f9783
DV		 1533 fb->base.bits_per_pixel,
1534 atomic_read(&fb->base.refcount.refcount));
05394f39 1535 describe_obj(m, fb->obj);
267f0c90 1536 seq_putc(m, '\n');
37811fcc 1537 }
4b096ac1 1538 mutex_unlock(&dev->mode_config.fb_lock);
37811fcc
CW		 1539
1540 return 0;
1541}
1542
e76d3630
BW		 1543static int i915_context_status(struct seq_file *m, void *unused)
1544{
1545 struct drm_info_node *node = (struct drm_info_node *) m->private;
1546 struct drm_device *dev = node->minor->dev;
1547 drm_i915_private_t *dev_priv = dev->dev_private;
a168c293 1548 struct intel_ring_buffer *ring;
a33afea5 1549 struct i915_hw_context *ctx;
a168c293 1550 int ret, i;
e76d3630
BW		 1551
1552 ret = mutex_lock_interruptible(&dev->mode_config.mutex);
1553 if (ret)
1554 return ret;
1555
3e373948 1556 if (dev_priv->ips.pwrctx) {
267f0c90 1557 seq_puts(m, "power context ");
3e373948 1558 describe_obj(m, dev_priv->ips.pwrctx);
267f0c90 1559 seq_putc(m, '\n');
dc501fbc 1560 }
e76d3630 1561
3e373948 1562 if (dev_priv->ips.renderctx) {
267f0c90 1563 seq_puts(m, "render context ");
3e373948 1564 describe_obj(m, dev_priv->ips.renderctx);
267f0c90 1565 seq_putc(m, '\n');
dc501fbc 1566 }
e76d3630 1567
a33afea5
BW		 1568 list_for_each_entry(ctx, &dev_priv->context_list, link) {
1569 seq_puts(m, "HW context ");
3ccfd19d 1570 describe_ctx(m, ctx);
a33afea5
BW		 1571 for_each_ring(ring, dev_priv, i)
1572 if (ring->default_context == ctx)
1573 seq_printf(m, "(default context %s) ", ring->name);
1574
1575 describe_obj(m, ctx->obj);
1576 seq_putc(m, '\n');
a168c293
BW		 1577 }
1578
e76d3630
BW		 1579 mutex_unlock(&dev->mode_config.mutex);
1580
1581 return 0;
1582}
1583
6d794d42
BW		 1584static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data)
1585{
1586 struct drm_info_node *node = (struct drm_info_node *) m->private;
1587 struct drm_device *dev = node->minor->dev;
1588 struct drm_i915_private *dev_priv = dev->dev_private;
43709ba0 1589 unsigned forcewake_count = 0, fw_rendercount = 0, fw_mediacount = 0;
6d794d42 1590
907b28c5 1591 spin_lock_irq(&dev_priv->uncore.lock);
43709ba0
D		 1592 if (IS_VALLEYVIEW(dev)) {
1593 fw_rendercount = dev_priv->uncore.fw_rendercount;
1594 fw_mediacount = dev_priv->uncore.fw_mediacount;
1595 } else
1596 forcewake_count = dev_priv->uncore.forcewake_count;
907b28c5 1597 spin_unlock_irq(&dev_priv->uncore.lock);
6d794d42 1598
43709ba0
D		 1599 if (IS_VALLEYVIEW(dev)) {
1600 seq_printf(m, "fw_rendercount = %u\n", fw_rendercount);
1601 seq_printf(m, "fw_mediacount = %u\n", fw_mediacount);
1602 } else
1603 seq_printf(m, "forcewake count = %u\n", forcewake_count);
6d794d42
BW		 1604
1605 return 0;
1606}
1607
ea16a3cd
DV		 1608static const char *swizzle_string(unsigned swizzle)
1609{
aee56cff 1610 switch (swizzle) {
ea16a3cd
DV		 1611 case I915_BIT_6_SWIZZLE_NONE:
1612 return "none";
1613 case I915_BIT_6_SWIZZLE_9:
1614 return "bit9";
1615 case I915_BIT_6_SWIZZLE_9_10:
1616 return "bit9/bit10";
1617 case I915_BIT_6_SWIZZLE_9_11:
1618 return "bit9/bit11";
1619 case I915_BIT_6_SWIZZLE_9_10_11:
1620 return "bit9/bit10/bit11";
1621 case I915_BIT_6_SWIZZLE_9_17:
1622 return "bit9/bit17";
1623 case I915_BIT_6_SWIZZLE_9_10_17:
1624 return "bit9/bit10/bit17";
1625 case I915_BIT_6_SWIZZLE_UNKNOWN:
8a168ca7 1626 return "unknown";
ea16a3cd
DV		 1627 }
1628
1629 return "bug";
1630}
1631
1632static int i915_swizzle_info(struct seq_file *m, void *data)
1633{
1634 struct drm_info_node *node = (struct drm_info_node *) m->private;
1635 struct drm_device *dev = node->minor->dev;
1636 struct drm_i915_private *dev_priv = dev->dev_private;
22bcfc6a
DV		 1637 int ret;
1638
1639 ret = mutex_lock_interruptible(&dev->struct_mutex);
1640 if (ret)
1641 return ret;
c8c8fb33 1642 intel_runtime_pm_get(dev_priv);
ea16a3cd 1643
ea16a3cd
DV		 1644 seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
1645 swizzle_string(dev_priv->mm.bit_6_swizzle_x));
1646 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
1647 swizzle_string(dev_priv->mm.bit_6_swizzle_y));
1648
1649 if (IS_GEN3(dev) || IS_GEN4(dev)) {
1650 seq_printf(m, "DDC = 0x%08x\n",
1651 I915_READ(DCC));
1652 seq_printf(m, "C0DRB3 = 0x%04x\n",
1653 I915_READ16(C0DRB3));
1654 seq_printf(m, "C1DRB3 = 0x%04x\n",
1655 I915_READ16(C1DRB3));
9d3203e1 1656 } else if (INTEL_INFO(dev)->gen >= 6) {
3fa7d235
DV		 1657 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
1658 I915_READ(MAD_DIMM_C0));
1659 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
1660 I915_READ(MAD_DIMM_C1));
1661 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
1662 I915_READ(MAD_DIMM_C2));
1663 seq_printf(m, "TILECTL = 0x%08x\n",
1664 I915_READ(TILECTL));
9d3203e1
BW		 1665 if (IS_GEN8(dev))
1666 seq_printf(m, "GAMTARBMODE = 0x%08x\n",
1667 I915_READ(GAMTARBMODE));
1668 else
1669 seq_printf(m, "ARB_MODE = 0x%08x\n",
1670 I915_READ(ARB_MODE));
3fa7d235
DV		 1671 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
1672 I915_READ(DISP_ARB_CTL));
ea16a3cd 1673 }
c8c8fb33 1674 intel_runtime_pm_put(dev_priv);
ea16a3cd
DV		 1675 mutex_unlock(&dev->struct_mutex);
1676
1677 return 0;
1678}
1679
77df6772 1680static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev)
3cf17fc5 1681{
3cf17fc5
DV		 1682 struct drm_i915_private *dev_priv = dev->dev_private;
1683 struct intel_ring_buffer *ring;
77df6772
BW		 1684 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
1685 int unused, i;
3cf17fc5 1686
77df6772
BW		 1687 if (!ppgtt)
1688 return;
1689
1690 seq_printf(m, "Page directories: %d\n", ppgtt->num_pd_pages);
1691 seq_printf(m, "Page tables: %d\n", ppgtt->num_pt_pages);
1692 for_each_ring(ring, dev_priv, unused) {
1693 seq_printf(m, "%s\n", ring->name);
1694 for (i = 0; i < 4; i++) {
1695 u32 offset = 0x270 + i * 8;
1696 u64 pdp = I915_READ(ring->mmio_base + offset + 4);
1697 pdp <<= 32;
1698 pdp |= I915_READ(ring->mmio_base + offset);
1699 for (i = 0; i < 4; i++)
1700 seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
1701 }
1702 }
1703}
1704
1705static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev)
1706{
1707 struct drm_i915_private *dev_priv = dev->dev_private;
1708 struct intel_ring_buffer *ring;
1709 int i;
3cf17fc5 1710
3cf17fc5
DV		 1711 if (INTEL_INFO(dev)->gen == 6)
1712 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
1713
a2c7f6fd 1714 for_each_ring(ring, dev_priv, i) {
3cf17fc5
DV		 1715 seq_printf(m, "%s\n", ring->name);
1716 if (INTEL_INFO(dev)->gen == 7)
1717 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
1718 seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
1719 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
1720 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring)));
1721 }
1722 if (dev_priv->mm.aliasing_ppgtt) {
1723 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
1724
267f0c90 1725 seq_puts(m, "aliasing PPGTT:\n");
3cf17fc5
DV		 1726 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset);
1727 }
1728 seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
77df6772
BW		 1729}
1730
1731static int i915_ppgtt_info(struct seq_file *m, void *data)
1732{
1733 struct drm_info_node *node = (struct drm_info_node *) m->private;
1734 struct drm_device *dev = node->minor->dev;
c8c8fb33 1735 struct drm_i915_private *dev_priv = dev->dev_private;
77df6772
BW		 1736
1737 int ret = mutex_lock_interruptible(&dev->struct_mutex);
1738 if (ret)
1739 return ret;
c8c8fb33 1740 intel_runtime_pm_get(dev_priv);
77df6772
BW		 1741
1742 if (INTEL_INFO(dev)->gen >= 8)
1743 gen8_ppgtt_info(m, dev);
1744 else if (INTEL_INFO(dev)->gen >= 6)
1745 gen6_ppgtt_info(m, dev);
1746
c8c8fb33 1747 intel_runtime_pm_put(dev_priv);
3cf17fc5
DV		 1748 mutex_unlock(&dev->struct_mutex);
1749
1750 return 0;
1751}
1752
57f350b6
JB		 1753static int i915_dpio_info(struct seq_file *m, void *data)
1754{
1755 struct drm_info_node *node = (struct drm_info_node *) m->private;
1756 struct drm_device *dev = node->minor->dev;
1757 struct drm_i915_private *dev_priv = dev->dev_private;
1758 int ret;
1759
1760
1761 if (!IS_VALLEYVIEW(dev)) {
267f0c90 1762 seq_puts(m, "unsupported\n");
57f350b6
JB		 1763 return 0;
1764 }
1765
09153000 1766 ret = mutex_lock_interruptible(&dev_priv->dpio_lock);
57f350b6
JB		 1767 if (ret)
1768 return ret;
1769
1770 seq_printf(m, "DPIO_CTL: 0x%08x\n", I915_READ(DPIO_CTL));
1771
ab3c759a
CML		 1772 seq_printf(m, "DPIO PLL DW3 CH0 : 0x%08x\n",
1773 vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW3(0)));
1774 seq_printf(m, "DPIO PLL DW3 CH1: 0x%08x\n",
1775 vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW3(1)));
1776
1777 seq_printf(m, "DPIO PLL DW5 CH0: 0x%08x\n",
1778 vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW5(0)));
1779 seq_printf(m, "DPIO PLL DW5 CH1: 0x%08x\n",
1780 vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW5(1)));
1781
1782 seq_printf(m, "DPIO PLL DW7 CH0: 0x%08x\n",
1783 vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW7(0)));
1784 seq_printf(m, "DPIO PLL DW7 CH1: 0x%08x\n",
1785 vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW7(1)));
1786
1787 seq_printf(m, "DPIO PLL DW10 CH0: 0x%08x\n",
1788 vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW10(0)));
1789 seq_printf(m, "DPIO PLL DW10 CH1: 0x%08x\n",
1790 vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW10(1)));
57f350b6
JB		 1791
1792 seq_printf(m, "DPIO_FASTCLK_DISABLE: 0x%08x\n",
ab3c759a 1793 vlv_dpio_read(dev_priv, PIPE_A, VLV_CMN_DW0));
57f350b6 1794
09153000 1795 mutex_unlock(&dev_priv->dpio_lock);
57f350b6
JB		 1796
1797 return 0;
1798}
1799
63573eb7
BW		 1800static int i915_llc(struct seq_file *m, void *data)
1801{
1802 struct drm_info_node *node = (struct drm_info_node *) m->private;
1803 struct drm_device *dev = node->minor->dev;
1804 struct drm_i915_private *dev_priv = dev->dev_private;
1805
1806 /* Size calculation for LLC is a bit of a pain. Ignore for now. */
1807 seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
1808 seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size);
1809
1810 return 0;
1811}
1812
e91fd8c6
RV		 1813static int i915_edp_psr_status(struct seq_file *m, void *data)
1814{
1815 struct drm_info_node *node = m->private;
1816 struct drm_device *dev = node->minor->dev;
1817 struct drm_i915_private *dev_priv = dev->dev_private;
a031d709
RV		 1818 u32 psrperf = 0;
1819 bool enabled = false;
e91fd8c6 1820
c8c8fb33
PZ		 1821 intel_runtime_pm_get(dev_priv);
1822
a031d709
RV		 1823 seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
1824 seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
e91fd8c6 1825
a031d709
RV		 1826 enabled = HAS_PSR(dev) &&
1827 I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
1828 seq_printf(m, "Enabled: %s\n", yesno(enabled));
e91fd8c6 1829
a031d709
RV		 1830 if (HAS_PSR(dev))
1831 psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) &
1832 EDP_PSR_PERF_CNT_MASK;
1833 seq_printf(m, "Performance_Counter: %u\n", psrperf);
e91fd8c6 1834
c8c8fb33 1835 intel_runtime_pm_put(dev_priv);
e91fd8c6
RV		 1836 return 0;
1837}
1838
ec013e7f
JB		 1839static int i915_energy_uJ(struct seq_file *m, void *data)
1840{
1841 struct drm_info_node *node = m->private;
1842 struct drm_device *dev = node->minor->dev;
1843 struct drm_i915_private *dev_priv = dev->dev_private;
1844 u64 power;
1845 u32 units;
1846
1847 if (INTEL_INFO(dev)->gen < 6)
1848 return -ENODEV;
1849
1850 rdmsrl(MSR_RAPL_POWER_UNIT, power);
1851 power = (power & 0x1f00) >> 8;
1852 units = 1000000 / (1 << power); /* convert to uJ */
1853 power = I915_READ(MCH_SECP_NRG_STTS);
1854 power *= units;
1855
1856 seq_printf(m, "%llu", (long long unsigned)power);
371db66a
PZ		 1857
1858 return 0;
1859}
1860
1861static int i915_pc8_status(struct seq_file *m, void *unused)
1862{
1863 struct drm_info_node *node = (struct drm_info_node *) m->private;
1864 struct drm_device *dev = node->minor->dev;
1865 struct drm_i915_private *dev_priv = dev->dev_private;
1866
1867 if (!IS_HASWELL(dev)) {
1868 seq_puts(m, "not supported\n");
1869 return 0;
1870 }
1871
1872 mutex_lock(&dev_priv->pc8.lock);
1873 seq_printf(m, "Requirements met: %s\n",
1874 yesno(dev_priv->pc8.requirements_met));
1875 seq_printf(m, "GPU idle: %s\n", yesno(dev_priv->pc8.gpu_idle));
1876 seq_printf(m, "Disable count: %d\n", dev_priv->pc8.disable_count);
1877 seq_printf(m, "IRQs disabled: %s\n",
1878 yesno(dev_priv->pc8.irqs_disabled));
1879 seq_printf(m, "Enabled: %s\n", yesno(dev_priv->pc8.enabled));
1880 mutex_unlock(&dev_priv->pc8.lock);
1881
ec013e7f
JB		 1882 return 0;
1883}
1884
1da51581
ID		 1885static const char *power_domain_str(enum intel_display_power_domain domain)
1886{
1887 switch (domain) {
1888 case POWER_DOMAIN_PIPE_A:
1889 return "PIPE_A";
1890 case POWER_DOMAIN_PIPE_B:
1891 return "PIPE_B";
1892 case POWER_DOMAIN_PIPE_C:
1893 return "PIPE_C";
1894 case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
1895 return "PIPE_A_PANEL_FITTER";
1896 case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
1897 return "PIPE_B_PANEL_FITTER";
1898 case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
1899 return "PIPE_C_PANEL_FITTER";
1900 case POWER_DOMAIN_TRANSCODER_A:
1901 return "TRANSCODER_A";
1902 case POWER_DOMAIN_TRANSCODER_B:
1903 return "TRANSCODER_B";
1904 case POWER_DOMAIN_TRANSCODER_C:
1905 return "TRANSCODER_C";
1906 case POWER_DOMAIN_TRANSCODER_EDP:
1907 return "TRANSCODER_EDP";
1908 case POWER_DOMAIN_VGA:
1909 return "VGA";
1910 case POWER_DOMAIN_AUDIO:
1911 return "AUDIO";
1912 case POWER_DOMAIN_INIT:
1913 return "INIT";
1914 default:
1915 WARN_ON(1);
1916 return "?";
1917 }
1918}
1919
1920static int i915_power_domain_info(struct seq_file *m, void *unused)
1921{
1922 struct drm_info_node *node = (struct drm_info_node *) m->private;
1923 struct drm_device *dev = node->minor->dev;
1924 struct drm_i915_private *dev_priv = dev->dev_private;
1925 struct i915_power_domains *power_domains = &dev_priv->power_domains;
1926 int i;
1927
1928 mutex_lock(&power_domains->lock);
1929
1930 seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
1931 for (i = 0; i < power_domains->power_well_count; i++) {
1932 struct i915_power_well *power_well;
1933 enum intel_display_power_domain power_domain;
1934
1935 power_well = &power_domains->power_wells[i];
1936 seq_printf(m, "%-25s %d\n", power_well->name,
1937 power_well->count);
1938
1939 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
1940 power_domain++) {
1941 if (!(BIT(power_domain) & power_well->domains))
1942 continue;
1943
1944 seq_printf(m, " %-23s %d\n",
1945 power_domain_str(power_domain),
1946 power_domains->domain_use_count[power_domain]);
1947 }
1948 }
1949
1950 mutex_unlock(&power_domains->lock);
1951
1952 return 0;
1953}
1954
07144428
DL		 1955struct pipe_crc_info {
1956 const char *name;
1957 struct drm_device *dev;
1958 enum pipe pipe;
1959};
1960
1961static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
1962{
be5c7a90
DL		 1963 struct pipe_crc_info *info = inode->i_private;
1964 struct drm_i915_private *dev_priv = info->dev->dev_private;
1965 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
1966
7eb1c496
DV		 1967 if (info->pipe >= INTEL_INFO(info->dev)->num_pipes)
1968 return -ENODEV;
1969
d538bbdf
DL		 1970 spin_lock_irq(&pipe_crc->lock);
1971
1972 if (pipe_crc->opened) {
1973 spin_unlock_irq(&pipe_crc->lock);
be5c7a90
DL		 1974 return -EBUSY; /* already open */
1975 }
1976
d538bbdf 1977 pipe_crc->opened = true;
07144428
DL		 1978 filep->private_data = inode->i_private;
1979
d538bbdf
DL		 1980 spin_unlock_irq(&pipe_crc->lock);
1981
07144428
DL		 1982 return 0;
1983}
1984
1985static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
1986{
be5c7a90
DL		 1987 struct pipe_crc_info *info = inode->i_private;
1988 struct drm_i915_private *dev_priv = info->dev->dev_private;
1989 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
1990
d538bbdf
DL		 1991 spin_lock_irq(&pipe_crc->lock);
1992 pipe_crc->opened = false;
1993 spin_unlock_irq(&pipe_crc->lock);
be5c7a90 1994
07144428
DL		 1995 return 0;
1996}
1997
1998/* (6 fields, 8 chars each, space separated (5) + '\n') */
1999#define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
2000/* account for \'0' */
2001#define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1)
2002
2003static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
8bf1e9f1 2004{
d538bbdf
DL		 2005 assert_spin_locked(&pipe_crc->lock);
2006 return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
2007 INTEL_PIPE_CRC_ENTRIES_NR);
07144428
DL		 2008}
2009
2010static ssize_t
2011i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
2012 loff_t *pos)
2013{
2014 struct pipe_crc_info *info = filep->private_data;
2015 struct drm_device *dev = info->dev;
2016 struct drm_i915_private *dev_priv = dev->dev_private;
2017 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2018 char buf[PIPE_CRC_BUFFER_LEN];
2019 int head, tail, n_entries, n;
2020 ssize_t bytes_read;
2021
2022 /*
2023 * Don't allow user space to provide buffers not big enough to hold
2024 * a line of data.
2025 */
2026 if (count < PIPE_CRC_LINE_LEN)
2027 return -EINVAL;
2028
2029 if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
8bf1e9f1 2030 return 0;
07144428
DL		 2031
2032 /* nothing to read */
d538bbdf 2033 spin_lock_irq(&pipe_crc->lock);
07144428 2034 while (pipe_crc_data_count(pipe_crc) == 0) {
d538bbdf
DL		 2035 int ret;
2036
2037 if (filep->f_flags & O_NONBLOCK) {
2038 spin_unlock_irq(&pipe_crc->lock);
07144428 2039 return -EAGAIN;
d538bbdf 2040 }
07144428 2041
d538bbdf
DL		 2042 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
2043 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
2044 if (ret) {
2045 spin_unlock_irq(&pipe_crc->lock);
2046 return ret;
2047 }
8bf1e9f1
SH		 2048 }
2049
07144428 2050 /* We now have one or more entries to read */
d538bbdf
DL		 2051 head = pipe_crc->head;
2052 tail = pipe_crc->tail;
07144428
DL		 2053 n_entries = min((size_t)CIRC_CNT(head, tail, INTEL_PIPE_CRC_ENTRIES_NR),
2054 count / PIPE_CRC_LINE_LEN);
d538bbdf
DL		 2055 spin_unlock_irq(&pipe_crc->lock);
2056
07144428
DL		 2057 bytes_read = 0;
2058 n = 0;
2059 do {
b2c88f5b 2060 struct intel_pipe_crc_entry *entry = &pipe_crc->entries[tail];
07144428 2061 int ret;
8bf1e9f1 2062
07144428
DL		 2063 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
2064 "%8u %8x %8x %8x %8x %8x\n",
2065 entry->frame, entry->crc[0],
2066 entry->crc[1], entry->crc[2],
2067 entry->crc[3], entry->crc[4]);
2068
2069 ret = copy_to_user(user_buf + n * PIPE_CRC_LINE_LEN,
2070 buf, PIPE_CRC_LINE_LEN);
2071 if (ret == PIPE_CRC_LINE_LEN)
2072 return -EFAULT;
b2c88f5b
DL		 2073
2074 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
2075 tail = (tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
07144428
DL		 2076 n++;
2077 } while (--n_entries);
8bf1e9f1 2078
d538bbdf
DL		 2079 spin_lock_irq(&pipe_crc->lock);
2080 pipe_crc->tail = tail;
2081 spin_unlock_irq(&pipe_crc->lock);
2082
07144428
DL		 2083 return bytes_read;
2084}
2085
2086static const struct file_operations i915_pipe_crc_fops = {
2087 .owner = THIS_MODULE,
2088 .open = i915_pipe_crc_open,
2089 .read = i915_pipe_crc_read,
2090 .release = i915_pipe_crc_release,
2091};
2092
2093static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
2094 {
2095 .name = "i915_pipe_A_crc",
2096 .pipe = PIPE_A,
2097 },
2098 {
2099 .name = "i915_pipe_B_crc",
2100 .pipe = PIPE_B,
2101 },
2102 {
2103 .name = "i915_pipe_C_crc",
2104 .pipe = PIPE_C,
2105 },
2106};
2107
2108static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
2109 enum pipe pipe)
2110{
2111 struct drm_device *dev = minor->dev;
2112 struct dentry *ent;
2113 struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
2114
2115 info->dev = dev;
2116 ent = debugfs_create_file(info->name, S_IRUGO, root, info,
2117 &i915_pipe_crc_fops);
f3c5fe97
WY		 2118 if (!ent)
2119 return -ENOMEM;
07144428
DL		 2120
2121 return drm_add_fake_info_node(minor, ent, info);
8bf1e9f1
SH		 2122}
2123
e8dfcf78 2124static const char * const pipe_crc_sources[] = {
926321d5
DV		 2125 "none",
2126 "plane1",
2127 "plane2",
2128 "pf",
5b3a856b 2129 "pipe",
3d099a05
DV		 2130 "TV",
2131 "DP-B",
2132 "DP-C",
2133 "DP-D",
46a19188 2134 "auto",
926321d5
DV		 2135};
2136
2137static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
2138{
2139 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
2140 return pipe_crc_sources[source];
2141}
2142
bd9db02f 2143static int display_crc_ctl_show(struct seq_file *m, void *data)
926321d5
DV		 2144{
2145 struct drm_device *dev = m->private;
2146 struct drm_i915_private *dev_priv = dev->dev_private;
2147 int i;
2148
2149 for (i = 0; i < I915_MAX_PIPES; i++)
2150 seq_printf(m, "%c %s\n", pipe_name(i),
2151 pipe_crc_source_name(dev_priv->pipe_crc[i].source));
2152
2153 return 0;
2154}
2155
bd9db02f 2156static int display_crc_ctl_open(struct inode *inode, struct file *file)
926321d5
DV		 2157{
2158 struct drm_device *dev = inode->i_private;
2159
bd9db02f 2160 return single_open(file, display_crc_ctl_show, dev);
926321d5
DV		 2161}
2162
46a19188 2163static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
52f843f6
DV		 2164 uint32_t *val)
2165{
46a19188
DV		 2166 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
2167 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
2168
2169 switch (*source) {
52f843f6
DV		 2170 case INTEL_PIPE_CRC_SOURCE_PIPE:
2171 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
2172 break;
2173 case INTEL_PIPE_CRC_SOURCE_NONE:
2174 *val = 0;
2175 break;
2176 default:
2177 return -EINVAL;
2178 }
2179
2180 return 0;
2181}
2182
46a19188
DV		 2183static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe,
2184 enum intel_pipe_crc_source *source)
2185{
2186 struct intel_encoder *encoder;
2187 struct intel_crtc *crtc;
26756809 2188 struct intel_digital_port *dig_port;
46a19188
DV		 2189 int ret = 0;
2190
2191 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
2192
2193 mutex_lock(&dev->mode_config.mutex);
2194 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
2195 base.head) {
2196 if (!encoder->base.crtc)
2197 continue;
2198
2199 crtc = to_intel_crtc(encoder->base.crtc);
2200
2201 if (crtc->pipe != pipe)
2202 continue;
2203
2204 switch (encoder->type) {
2205 case INTEL_OUTPUT_TVOUT:
2206 *source = INTEL_PIPE_CRC_SOURCE_TV;
2207 break;
2208 case INTEL_OUTPUT_DISPLAYPORT:
2209 case INTEL_OUTPUT_EDP:
26756809
DV		 2210 dig_port = enc_to_dig_port(&encoder->base);
2211 switch (dig_port->port) {
2212 case PORT_B:
2213 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
2214 break;
2215 case PORT_C:
2216 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
2217 break;
2218 case PORT_D:
2219 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
2220 break;
2221 default:
2222 WARN(1, "nonexisting DP port %c\n",
2223 port_name(dig_port->port));
2224 break;
2225 }
46a19188
DV		 2226 break;
2227 }
2228 }
2229 mutex_unlock(&dev->mode_config.mutex);
2230
2231 return ret;
2232}
2233
2234static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
2235 enum pipe pipe,
2236 enum intel_pipe_crc_source *source,
7ac0129b
DV		 2237 uint32_t *val)
2238{
8d2f24ca
DV		 2239 struct drm_i915_private *dev_priv = dev->dev_private;
2240 bool need_stable_symbols = false;
2241
46a19188
DV		 2242 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
2243 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
2244 if (ret)
2245 return ret;
2246 }
2247
2248 switch (*source) {
7ac0129b
DV		 2249 case INTEL_PIPE_CRC_SOURCE_PIPE:
2250 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
2251 break;
2252 case INTEL_PIPE_CRC_SOURCE_DP_B:
2253 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
8d2f24ca 2254 need_stable_symbols = true;
7ac0129b
DV		 2255 break;
2256 case INTEL_PIPE_CRC_SOURCE_DP_C:
2257 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
8d2f24ca 2258 need_stable_symbols = true;
7ac0129b
DV		 2259 break;
2260 case INTEL_PIPE_CRC_SOURCE_NONE:
2261 *val = 0;
2262 break;
2263 default:
2264 return -EINVAL;
2265 }
2266
8d2f24ca
DV		 2267 /*
2268 * When the pipe CRC tap point is after the transcoders we need
2269 * to tweak symbol-level features to produce a deterministic series of
2270 * symbols for a given frame. We need to reset those features only once
2271 * a frame (instead of every nth symbol):
2272 * - DC-balance: used to ensure a better clock recovery from the data
2273 * link (SDVO)
2274 * - DisplayPort scrambling: used for EMI reduction
2275 */
2276 if (need_stable_symbols) {
2277 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
2278
2279 WARN_ON(!IS_G4X(dev));
2280
2281 tmp |= DC_BALANCE_RESET_VLV;
2282 if (pipe == PIPE_A)
2283 tmp |= PIPE_A_SCRAMBLE_RESET;
2284 else
2285 tmp |= PIPE_B_SCRAMBLE_RESET;
2286
2287 I915_WRITE(PORT_DFT2_G4X, tmp);
2288 }
2289
7ac0129b
DV		 2290 return 0;
2291}
2292
4b79ebf7 2293static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
46a19188
DV		 2294 enum pipe pipe,
2295 enum intel_pipe_crc_source *source,
4b79ebf7
DV		 2296 uint32_t *val)
2297{
84093603
DV		 2298 struct drm_i915_private *dev_priv = dev->dev_private;
2299 bool need_stable_symbols = false;
2300
46a19188
DV		 2301 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
2302 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
2303 if (ret)
2304 return ret;
2305 }
2306
2307 switch (*source) {
4b79ebf7
DV		 2308 case INTEL_PIPE_CRC_SOURCE_PIPE:
2309 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
2310 break;
2311 case INTEL_PIPE_CRC_SOURCE_TV:
2312 if (!SUPPORTS_TV(dev))
2313 return -EINVAL;
2314 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
2315 break;
2316 case INTEL_PIPE_CRC_SOURCE_DP_B:
2317 if (!IS_G4X(dev))
2318 return -EINVAL;
2319 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
84093603 2320 need_stable_symbols = true;
4b79ebf7
DV		 2321 break;
2322 case INTEL_PIPE_CRC_SOURCE_DP_C:
2323 if (!IS_G4X(dev))
2324 return -EINVAL;
2325 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
84093603 2326 need_stable_symbols = true;
4b79ebf7
DV		 2327 break;
2328 case INTEL_PIPE_CRC_SOURCE_DP_D:
2329 if (!IS_G4X(dev))
2330 return -EINVAL;
2331 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
84093603 2332 need_stable_symbols = true;
4b79ebf7
DV		 2333 break;
2334 case INTEL_PIPE_CRC_SOURCE_NONE:
2335 *val = 0;
2336 break;
2337 default:
2338 return -EINVAL;
2339 }
2340
84093603
DV		 2341 /*
2342 * When the pipe CRC tap point is after the transcoders we need
2343 * to tweak symbol-level features to produce a deterministic series of
2344 * symbols for a given frame. We need to reset those features only once
2345 * a frame (instead of every nth symbol):
2346 * - DC-balance: used to ensure a better clock recovery from the data
2347 * link (SDVO)
2348 * - DisplayPort scrambling: used for EMI reduction
2349 */
2350 if (need_stable_symbols) {
2351 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
2352
2353 WARN_ON(!IS_G4X(dev));
2354
2355 I915_WRITE(PORT_DFT_I9XX,
2356 I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
2357
2358 if (pipe == PIPE_A)
2359 tmp |= PIPE_A_SCRAMBLE_RESET;
2360 else
2361 tmp |= PIPE_B_SCRAMBLE_RESET;
2362
2363 I915_WRITE(PORT_DFT2_G4X, tmp);
2364 }
2365
4b79ebf7
DV		 2366 return 0;
2367}
2368
8d2f24ca
DV		 2369static void vlv_undo_pipe_scramble_reset(struct drm_device *dev,
2370 enum pipe pipe)
2371{
2372 struct drm_i915_private *dev_priv = dev->dev_private;
2373 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
2374
2375 if (pipe == PIPE_A)
2376 tmp &= ~PIPE_A_SCRAMBLE_RESET;
2377 else
2378 tmp &= ~PIPE_B_SCRAMBLE_RESET;
2379 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
2380 tmp &= ~DC_BALANCE_RESET_VLV;
2381 I915_WRITE(PORT_DFT2_G4X, tmp);
2382
2383}
2384
84093603
DV		 2385static void g4x_undo_pipe_scramble_reset(struct drm_device *dev,
2386 enum pipe pipe)
2387{
2388 struct drm_i915_private *dev_priv = dev->dev_private;
2389 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
2390
2391 if (pipe == PIPE_A)
2392 tmp &= ~PIPE_A_SCRAMBLE_RESET;
2393 else
2394 tmp &= ~PIPE_B_SCRAMBLE_RESET;
2395 I915_WRITE(PORT_DFT2_G4X, tmp);
2396
2397 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
2398 I915_WRITE(PORT_DFT_I9XX,
2399 I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
2400 }
2401}
2402
46a19188 2403static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
5b3a856b
DV		 2404 uint32_t *val)
2405{
46a19188
DV		 2406 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
2407 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
2408
2409 switch (*source) {
5b3a856b
DV		 2410 case INTEL_PIPE_CRC_SOURCE_PLANE1:
2411 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
2412 break;
2413 case INTEL_PIPE_CRC_SOURCE_PLANE2:
2414 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
2415 break;
5b3a856b
DV		 2416 case INTEL_PIPE_CRC_SOURCE_PIPE:
2417 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
2418 break;
3d099a05 2419 case INTEL_PIPE_CRC_SOURCE_NONE:
5b3a856b
DV		 2420 *val = 0;
2421 break;
3d099a05
DV		 2422 default:
2423 return -EINVAL;
5b3a856b
DV		 2424 }
2425
2426 return 0;
2427}
2428
46a19188 2429static int ivb_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
5b3a856b
DV		 2430 uint32_t *val)
2431{
46a19188
DV		 2432 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
2433 *source = INTEL_PIPE_CRC_SOURCE_PF;
2434
2435 switch (*source) {
5b3a856b
DV		 2436 case INTEL_PIPE_CRC_SOURCE_PLANE1:
2437 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
2438 break;
2439 case INTEL_PIPE_CRC_SOURCE_PLANE2:
2440 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
2441 break;
2442 case INTEL_PIPE_CRC_SOURCE_PF:
2443 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
2444 break;
3d099a05 2445 case INTEL_PIPE_CRC_SOURCE_NONE:
5b3a856b
DV		 2446 *val = 0;
2447 break;
3d099a05
DV		 2448 default:
2449 return -EINVAL;
5b3a856b
DV		 2450 }
2451
2452 return 0;
2453}
2454
926321d5
DV		 2455static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
2456 enum intel_pipe_crc_source source)
2457{
2458 struct drm_i915_private *dev_priv = dev->dev_private;
cc3da175 2459 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
432f3342 2460 u32 val = 0; /* shut up gcc */
5b3a856b 2461 int ret;
926321d5 2462
cc3da175
DL		 2463 if (pipe_crc->source == source)
2464 return 0;
2465
ae676fcd
DL		 2466 /* forbid changing the source without going back to 'none' */
2467 if (pipe_crc->source && source)
2468 return -EINVAL;
2469
52f843f6 2470 if (IS_GEN2(dev))
46a19188 2471 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
52f843f6 2472 else if (INTEL_INFO(dev)->gen < 5)
46a19188 2473 ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
7ac0129b 2474 else if (IS_VALLEYVIEW(dev))
46a19188 2475 ret = vlv_pipe_crc_ctl_reg(dev,pipe, &source, &val);
4b79ebf7 2476 else if (IS_GEN5(dev) || IS_GEN6(dev))
46a19188 2477 ret = ilk_pipe_crc_ctl_reg(&source, &val);
5b3a856b 2478 else
46a19188 2479 ret = ivb_pipe_crc_ctl_reg(&source, &val);
5b3a856b
DV		 2480
2481 if (ret != 0)
2482 return ret;
2483
4b584369
DL		 2484 /* none -> real source transition */
2485 if (source) {
7cd6ccff
DL		 2486 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
2487 pipe_name(pipe), pipe_crc_source_name(source));
2488
e5f75aca
DL		 2489 pipe_crc->entries = kzalloc(sizeof(*pipe_crc->entries) *
2490 INTEL_PIPE_CRC_ENTRIES_NR,
2491 GFP_KERNEL);
2492 if (!pipe_crc->entries)
2493 return -ENOMEM;
2494
d538bbdf
DL		 2495 spin_lock_irq(&pipe_crc->lock);
2496 pipe_crc->head = 0;
2497 pipe_crc->tail = 0;
2498 spin_unlock_irq(&pipe_crc->lock);
4b584369
DL		 2499 }
2500
cc3da175 2501 pipe_crc->source = source;
926321d5 2502
926321d5
DV		 2503 I915_WRITE(PIPE_CRC_CTL(pipe), val);
2504 POSTING_READ(PIPE_CRC_CTL(pipe));
2505
e5f75aca
DL		 2506 /* real source -> none transition */
2507 if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
d538bbdf
DL		 2508 struct intel_pipe_crc_entry *entries;
2509
7cd6ccff
DL		 2510 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
2511 pipe_name(pipe));
2512
bcf17ab2
DV		 2513 intel_wait_for_vblank(dev, pipe);
2514
d538bbdf
DL		 2515 spin_lock_irq(&pipe_crc->lock);
2516 entries = pipe_crc->entries;
e5f75aca 2517 pipe_crc->entries = NULL;
d538bbdf
DL		 2518 spin_unlock_irq(&pipe_crc->lock);
2519
2520 kfree(entries);
84093603
DV		 2521
2522 if (IS_G4X(dev))
2523 g4x_undo_pipe_scramble_reset(dev, pipe);
8d2f24ca
DV		 2524 else if (IS_VALLEYVIEW(dev))
2525 vlv_undo_pipe_scramble_reset(dev, pipe);
e5f75aca
DL		 2526 }
2527
926321d5
DV		 2528 return 0;
2529}
2530
2531/*
2532 * Parse pipe CRC command strings:
b94dec87
DL		 2533 * command: wsp* object wsp+ name wsp+ source wsp*
2534 * object: 'pipe'
2535 * name: (A | B | C)
926321d5
DV		 2536 * source: (none | plane1 | plane2 | pf)
2537 * wsp: (#0x20 | #0x9 | #0xA)+
2538 *
2539 * eg.:
b94dec87
DL		 2540 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A
2541 * "pipe A none" -> Stop CRC
926321d5 2542 */
bd9db02f 2543static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
926321d5
DV		 2544{
2545 int n_words = 0;
2546
2547 while (*buf) {
2548 char *end;
2549
2550 /* skip leading white space */
2551 buf = skip_spaces(buf);
2552 if (!*buf)
2553 break; /* end of buffer */
2554
2555 /* find end of word */
2556 for (end = buf; *end && !isspace(*end); end++)
2557 ;
2558
2559 if (n_words == max_words) {
2560 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
2561 max_words);
2562 return -EINVAL; /* ran out of words[] before bytes */
2563 }
2564
2565 if (*end)
2566 *end++ = '\0';
2567 words[n_words++] = buf;
2568 buf = end;
2569 }
2570
2571 return n_words;
2572}
2573
b94dec87
DL		 2574enum intel_pipe_crc_object {
2575 PIPE_CRC_OBJECT_PIPE,
2576};
2577
e8dfcf78 2578static const char * const pipe_crc_objects[] = {
b94dec87
DL		 2579 "pipe",
2580};
2581
2582static int
bd9db02f 2583display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
b94dec87
DL		 2584{
2585 int i;
2586
2587 for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
2588 if (!strcmp(buf, pipe_crc_objects[i])) {
bd9db02f 2589 *o = i;
b94dec87
DL		 2590 return 0;
2591 }
2592
2593 return -EINVAL;
2594}
2595
bd9db02f 2596static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
926321d5
DV		 2597{
2598 const char name = buf[0];
2599
2600 if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
2601 return -EINVAL;
2602
2603 *pipe = name - 'A';
2604
2605 return 0;
2606}
2607
2608static int
bd9db02f 2609display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
926321d5
DV		 2610{
2611 int i;
2612
2613 for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
2614 if (!strcmp(buf, pipe_crc_sources[i])) {
bd9db02f 2615 *s = i;
926321d5
DV		 2616 return 0;
2617 }
2618
2619 return -EINVAL;
2620}
2621
bd9db02f 2622static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len)
926321d5 2623{
b94dec87 2624#define N_WORDS 3
926321d5 2625 int n_words;
b94dec87 2626 char *words[N_WORDS];
926321d5 2627 enum pipe pipe;
b94dec87 2628 enum intel_pipe_crc_object object;
926321d5
DV		 2629 enum intel_pipe_crc_source source;
2630
bd9db02f 2631 n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
b94dec87
DL		 2632 if (n_words != N_WORDS) {
2633 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
2634 N_WORDS);
2635 return -EINVAL;
2636 }
2637
bd9db02f 2638 if (display_crc_ctl_parse_object(words[0], &object) < 0) {
b94dec87 2639 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
926321d5
DV		 2640 return -EINVAL;
2641 }
2642
bd9db02f 2643 if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
b94dec87 2644 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
926321d5
DV		 2645 return -EINVAL;
2646 }
2647
bd9db02f 2648 if (display_crc_ctl_parse_source(words[2], &source) < 0) {
b94dec87 2649 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
926321d5
DV		 2650 return -EINVAL;
2651 }
2652
2653 return pipe_crc_set_source(dev, pipe, source);
2654}
2655
bd9db02f
DL		 2656static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
2657 size_t len, loff_t *offp)
926321d5
DV		 2658{
2659 struct seq_file *m = file->private_data;
2660 struct drm_device *dev = m->private;
2661 char *tmpbuf;
2662 int ret;
2663
2664 if (len == 0)
2665 return 0;
2666
2667 if (len > PAGE_SIZE - 1) {
2668 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
2669 PAGE_SIZE);
2670 return -E2BIG;
2671 }
2672
2673 tmpbuf = kmalloc(len + 1, GFP_KERNEL);
2674 if (!tmpbuf)
2675 return -ENOMEM;
2676
2677 if (copy_from_user(tmpbuf, ubuf, len)) {
2678 ret = -EFAULT;
2679 goto out;
2680 }
2681 tmpbuf[len] = '\0';
2682
bd9db02f 2683 ret = display_crc_ctl_parse(dev, tmpbuf, len);
926321d5
DV		 2684
2685out:
2686 kfree(tmpbuf);
2687 if (ret < 0)
2688 return ret;
2689
2690 *offp += len;
2691 return len;
2692}
2693
bd9db02f 2694static const struct file_operations i915_display_crc_ctl_fops = {
926321d5 2695 .owner = THIS_MODULE,
bd9db02f 2696 .open = display_crc_ctl_open,
926321d5
DV		 2697 .read = seq_read,
2698 .llseek = seq_lseek,
2699 .release = single_release,
bd9db02f 2700 .write = display_crc_ctl_write
926321d5
DV		 2701};
2702
647416f9
KC		 2703static int
2704i915_wedged_get(void *data, u64 *val)
f3cd474b 2705{
647416f9 2706 struct drm_device *dev = data;
f3cd474b 2707 drm_i915_private_t *dev_priv = dev->dev_private;
f3cd474b 2708
647416f9 2709 *val = atomic_read(&dev_priv->gpu_error.reset_counter);
f3cd474b 2710
647416f9 2711 return 0;
f3cd474b
CW		 2712}
2713
647416f9
KC		 2714static int
2715i915_wedged_set(void *data, u64 val)
f3cd474b 2716{
647416f9 2717 struct drm_device *dev = data;
f3cd474b 2718
647416f9 2719 DRM_INFO("Manually setting wedged to %llu\n", val);
527f9e90 2720 i915_handle_error(dev, val);
f3cd474b 2721
647416f9 2722 return 0;
f3cd474b
CW		 2723}
2724
647416f9
KC		 2725DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
2726 i915_wedged_get, i915_wedged_set,
3a3b4f98 2727 "%llu\n");
f3cd474b 2728
647416f9
KC		 2729static int
2730i915_ring_stop_get(void *data, u64 *val)
e5eb3d63 2731{
647416f9 2732 struct drm_device *dev = data;
e5eb3d63 2733 drm_i915_private_t *dev_priv = dev->dev_private;
e5eb3d63 2734
647416f9 2735 *val = dev_priv->gpu_error.stop_rings;
e5eb3d63 2736
647416f9 2737 return 0;
e5eb3d63
DV		 2738}
2739
647416f9
KC		 2740static int
2741i915_ring_stop_set(void *data, u64 val)
e5eb3d63 2742{
647416f9 2743 struct drm_device *dev = data;
e5eb3d63 2744 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 2745 int ret;
e5eb3d63 2746
647416f9 2747 DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val);
e5eb3d63 2748
22bcfc6a
DV		 2749 ret = mutex_lock_interruptible(&dev->struct_mutex);
2750 if (ret)
2751 return ret;
2752
99584db3 2753 dev_priv->gpu_error.stop_rings = val;
e5eb3d63
DV		 2754 mutex_unlock(&dev->struct_mutex);
2755
647416f9 2756 return 0;
e5eb3d63
DV		 2757}
2758
647416f9
KC		 2759DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops,
2760 i915_ring_stop_get, i915_ring_stop_set,
2761 "0x%08llx\n");
d5442303 2762
094f9a54
CW		 2763static int
2764i915_ring_missed_irq_get(void *data, u64 *val)
2765{
2766 struct drm_device *dev = data;
2767 struct drm_i915_private *dev_priv = dev->dev_private;
2768
2769 *val = dev_priv->gpu_error.missed_irq_rings;
2770 return 0;
2771}
2772
2773static int
2774i915_ring_missed_irq_set(void *data, u64 val)
2775{
2776 struct drm_device *dev = data;
2777 struct drm_i915_private *dev_priv = dev->dev_private;
2778 int ret;
2779
2780 /* Lock against concurrent debugfs callers */
2781 ret = mutex_lock_interruptible(&dev->struct_mutex);
2782 if (ret)
2783 return ret;
2784 dev_priv->gpu_error.missed_irq_rings = val;
2785 mutex_unlock(&dev->struct_mutex);
2786
2787 return 0;
2788}
2789
2790DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
2791 i915_ring_missed_irq_get, i915_ring_missed_irq_set,
2792 "0x%08llx\n");
2793
2794static int
2795i915_ring_test_irq_get(void *data, u64 *val)
2796{
2797 struct drm_device *dev = data;
2798 struct drm_i915_private *dev_priv = dev->dev_private;
2799
2800 *val = dev_priv->gpu_error.test_irq_rings;
2801
2802 return 0;
2803}
2804
2805static int
2806i915_ring_test_irq_set(void *data, u64 val)
2807{
2808 struct drm_device *dev = data;
2809 struct drm_i915_private *dev_priv = dev->dev_private;
2810 int ret;
2811
2812 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
2813
2814 /* Lock against concurrent debugfs callers */
2815 ret = mutex_lock_interruptible(&dev->struct_mutex);
2816 if (ret)
2817 return ret;
2818
2819 dev_priv->gpu_error.test_irq_rings = val;
2820 mutex_unlock(&dev->struct_mutex);
2821
2822 return 0;
2823}
2824
2825DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
2826 i915_ring_test_irq_get, i915_ring_test_irq_set,
2827 "0x%08llx\n");
2828
dd624afd
CW		 2829#define DROP_UNBOUND 0x1
2830#define DROP_BOUND 0x2
2831#define DROP_RETIRE 0x4
2832#define DROP_ACTIVE 0x8
2833#define DROP_ALL (DROP_UNBOUND | \
2834 DROP_BOUND | \
2835 DROP_RETIRE | \
2836 DROP_ACTIVE)
647416f9
KC		 2837static int
2838i915_drop_caches_get(void *data, u64 *val)
dd624afd 2839{
647416f9 2840 *val = DROP_ALL;
dd624afd 2841
647416f9 2842 return 0;
dd624afd
CW		 2843}
2844
647416f9
KC		 2845static int
2846i915_drop_caches_set(void *data, u64 val)
dd624afd 2847{
647416f9 2848 struct drm_device *dev = data;
dd624afd
CW		 2849 struct drm_i915_private *dev_priv = dev->dev_private;
2850 struct drm_i915_gem_object *obj, *next;
ca191b13
BW		 2851 struct i915_address_space *vm;
2852 struct i915_vma *vma, *x;
647416f9 2853 int ret;
dd624afd 2854
2f9fe5ff 2855 DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
dd624afd
CW		 2856
2857 /* No need to check and wait for gpu resets, only libdrm auto-restarts
2858 * on ioctls on -EAGAIN. */
2859 ret = mutex_lock_interruptible(&dev->struct_mutex);
2860 if (ret)
2861 return ret;
2862
2863 if (val & DROP_ACTIVE) {
2864 ret = i915_gpu_idle(dev);
2865 if (ret)
2866 goto unlock;
2867 }
2868
2869 if (val & (DROP_RETIRE | DROP_ACTIVE))
2870 i915_gem_retire_requests(dev);
2871
2872 if (val & DROP_BOUND) {
ca191b13
BW		 2873 list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
2874 list_for_each_entry_safe(vma, x, &vm->inactive_list,
2875 mm_list) {
2876 if (vma->obj->pin_count)
2877 continue;
2878
2879 ret = i915_vma_unbind(vma);
2880 if (ret)
2881 goto unlock;
2882 }
31a46c9c 2883 }
dd624afd
CW		 2884 }
2885
2886 if (val & DROP_UNBOUND) {
35c20a60
BW		 2887 list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list,
2888 global_list)
dd624afd
CW		 2889 if (obj->pages_pin_count == 0) {
2890 ret = i915_gem_object_put_pages(obj);
2891 if (ret)
2892 goto unlock;
2893 }
2894 }
2895
2896unlock:
2897 mutex_unlock(&dev->struct_mutex);
2898
647416f9 2899 return ret;
dd624afd
CW		 2900}
2901
647416f9
KC		 2902DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
2903 i915_drop_caches_get, i915_drop_caches_set,
2904 "0x%08llx\n");
dd624afd 2905
647416f9
KC		 2906static int
2907i915_max_freq_get(void *data, u64 *val)
358733e9 2908{
647416f9 2909 struct drm_device *dev = data;
358733e9 2910 drm_i915_private_t *dev_priv = dev->dev_private;
647416f9 2911 int ret;
004777cb
DV		 2912
2913 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
2914 return -ENODEV;
2915
5c9669ce
TR		 2916 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
2917
4fc688ce 2918 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 2919 if (ret)
2920 return ret;
358733e9 2921
0a073b84 2922 if (IS_VALLEYVIEW(dev))
2ec3815f 2923 *val = vlv_gpu_freq(dev_priv, dev_priv->rps.max_delay);
0a073b84
JB		 2924 else
2925 *val = dev_priv->rps.max_delay * GT_FREQUENCY_MULTIPLIER;
4fc688ce 2926 mutex_unlock(&dev_priv->rps.hw_lock);
358733e9 2927
647416f9 2928 return 0;
358733e9
JB		 2929}
2930
647416f9
KC		 2931static int
2932i915_max_freq_set(void *data, u64 val)
358733e9 2933{
647416f9 2934 struct drm_device *dev = data;
358733e9 2935 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 2936 int ret;
004777cb
DV		 2937
2938 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
2939 return -ENODEV;
358733e9 2940
5c9669ce
TR		 2941 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
2942
647416f9 2943 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
358733e9 2944
4fc688ce 2945 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 2946 if (ret)
2947 return ret;
2948
358733e9
JB		 2949 /*
2950 * Turbo will still be enabled, but won't go above the set value.
2951 */
0a073b84 2952 if (IS_VALLEYVIEW(dev)) {
2ec3815f 2953 val = vlv_freq_opcode(dev_priv, val);
0a073b84 2954 dev_priv->rps.max_delay = val;
6917c7b9 2955 valleyview_set_rps(dev, val);
0a073b84
JB		 2956 } else {
2957 do_div(val, GT_FREQUENCY_MULTIPLIER);
2958 dev_priv->rps.max_delay = val;
2959 gen6_set_rps(dev, val);
2960 }
2961
4fc688ce 2962 mutex_unlock(&dev_priv->rps.hw_lock);
358733e9 2963
647416f9 2964 return 0;
358733e9
JB		 2965}
2966
647416f9
KC		 2967DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
2968 i915_max_freq_get, i915_max_freq_set,
3a3b4f98 2969 "%llu\n");
358733e9 2970
647416f9
KC		 2971static int
2972i915_min_freq_get(void *data, u64 *val)
1523c310 2973{
647416f9 2974 struct drm_device *dev = data;
1523c310 2975 drm_i915_private_t *dev_priv = dev->dev_private;
647416f9 2976 int ret;
004777cb
DV		 2977
2978 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
2979 return -ENODEV;
2980
5c9669ce
TR		 2981 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
2982
4fc688ce 2983 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 2984 if (ret)
2985 return ret;
1523c310 2986
0a073b84 2987 if (IS_VALLEYVIEW(dev))
2ec3815f 2988 *val = vlv_gpu_freq(dev_priv, dev_priv->rps.min_delay);
0a073b84
JB		 2989 else
2990 *val = dev_priv->rps.min_delay * GT_FREQUENCY_MULTIPLIER;
4fc688ce 2991 mutex_unlock(&dev_priv->rps.hw_lock);
1523c310 2992
647416f9 2993 return 0;
1523c310
JB		 2994}
2995
647416f9
KC		 2996static int
2997i915_min_freq_set(void *data, u64 val)
1523c310 2998{
647416f9 2999 struct drm_device *dev = data;
1523c310 3000 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 3001 int ret;
004777cb
DV		 3002
3003 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
3004 return -ENODEV;
1523c310 3005
5c9669ce
TR		 3006 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
3007
647416f9 3008 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
1523c310 3009
4fc688ce 3010 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 3011 if (ret)
3012 return ret;
3013
1523c310
JB		 3014 /*
3015 * Turbo will still be enabled, but won't go below the set value.
3016 */
0a073b84 3017 if (IS_VALLEYVIEW(dev)) {
2ec3815f 3018 val = vlv_freq_opcode(dev_priv, val);
0a073b84
JB		 3019 dev_priv->rps.min_delay = val;
3020 valleyview_set_rps(dev, val);
3021 } else {
3022 do_div(val, GT_FREQUENCY_MULTIPLIER);
3023 dev_priv->rps.min_delay = val;
3024 gen6_set_rps(dev, val);
3025 }
4fc688ce 3026 mutex_unlock(&dev_priv->rps.hw_lock);
1523c310 3027
647416f9 3028 return 0;
1523c310
JB		 3029}
3030
647416f9
KC		 3031DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
3032 i915_min_freq_get, i915_min_freq_set,
3a3b4f98 3033 "%llu\n");
1523c310 3034
647416f9
KC		 3035static int
3036i915_cache_sharing_get(void *data, u64 *val)
07b7ddd9 3037{
647416f9 3038 struct drm_device *dev = data;
07b7ddd9 3039 drm_i915_private_t *dev_priv = dev->dev_private;
07b7ddd9 3040 u32 snpcr;
647416f9 3041 int ret;
07b7ddd9 3042
004777cb
DV		 3043 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
3044 return -ENODEV;
3045
22bcfc6a
DV		 3046 ret = mutex_lock_interruptible(&dev->struct_mutex);
3047 if (ret)
3048 return ret;
c8c8fb33 3049 intel_runtime_pm_get(dev_priv);
22bcfc6a 3050
07b7ddd9 3051 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
c8c8fb33
PZ		 3052
3053 intel_runtime_pm_put(dev_priv);
07b7ddd9
JB		 3054 mutex_unlock(&dev_priv->dev->struct_mutex);
3055
647416f9 3056 *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
07b7ddd9 3057
647416f9 3058 return 0;
07b7ddd9
JB		 3059}
3060
647416f9
KC		 3061static int
3062i915_cache_sharing_set(void *data, u64 val)
07b7ddd9 3063{
647416f9 3064 struct drm_device *dev = data;
07b7ddd9 3065 struct drm_i915_private *dev_priv = dev->dev_private;
07b7ddd9 3066 u32 snpcr;
07b7ddd9 3067
004777cb
DV		 3068 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
3069 return -ENODEV;
3070
647416f9 3071 if (val > 3)
07b7ddd9
JB		 3072 return -EINVAL;
3073
c8c8fb33 3074 intel_runtime_pm_get(dev_priv);
647416f9 3075 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
07b7ddd9
JB		 3076
3077 /* Update the cache sharing policy here as well */
3078 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
3079 snpcr &= ~GEN6_MBC_SNPCR_MASK;
3080 snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
3081 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3082
c8c8fb33 3083 intel_runtime_pm_put(dev_priv);
647416f9 3084 return 0;
07b7ddd9
JB		 3085}
3086
647416f9
KC		 3087DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
3088 i915_cache_sharing_get, i915_cache_sharing_set,
3089 "%llu\n");
07b7ddd9 3090
6d794d42
BW		 3091static int i915_forcewake_open(struct inode *inode, struct file *file)
3092{
3093 struct drm_device *dev = inode->i_private;
3094 struct drm_i915_private *dev_priv = dev->dev_private;
6d794d42 3095
075edca4 3096 if (INTEL_INFO(dev)->gen < 6)
6d794d42
BW		 3097 return 0;
3098
c8c8fb33 3099 intel_runtime_pm_get(dev_priv);
c8d9a590 3100 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
6d794d42
BW		 3101
3102 return 0;
3103}
3104
c43b5634 3105static int i915_forcewake_release(struct inode *inode, struct file *file)
6d794d42
BW		 3106{
3107 struct drm_device *dev = inode->i_private;
3108 struct drm_i915_private *dev_priv = dev->dev_private;
3109
075edca4 3110 if (INTEL_INFO(dev)->gen < 6)
6d794d42
BW		 3111 return 0;
3112
c8d9a590 3113 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
c8c8fb33 3114 intel_runtime_pm_put(dev_priv);
6d794d42
BW		 3115
3116 return 0;
3117}
3118
3119static const struct file_operations i915_forcewake_fops = {
3120 .owner = THIS_MODULE,
3121 .open = i915_forcewake_open,
3122 .release = i915_forcewake_release,
3123};
3124
3125static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
3126{
3127 struct drm_device *dev = minor->dev;
3128 struct dentry *ent;
3129
3130 ent = debugfs_create_file("i915_forcewake_user",
8eb57294 3131 S_IRUSR,
6d794d42
BW		 3132 root, dev,
3133 &i915_forcewake_fops);
f3c5fe97
WY		 3134 if (!ent)
3135 return -ENOMEM;
6d794d42 3136
8eb57294 3137 return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
6d794d42
BW		 3138}
3139
6a9c308d
DV		 3140static int i915_debugfs_create(struct dentry *root,
3141 struct drm_minor *minor,
3142 const char *name,
3143 const struct file_operations *fops)
07b7ddd9
JB		 3144{
3145 struct drm_device *dev = minor->dev;
3146 struct dentry *ent;
3147
6a9c308d 3148 ent = debugfs_create_file(name,
07b7ddd9
JB		 3149 S_IRUGO | S_IWUSR,
3150 root, dev,
6a9c308d 3151 fops);
f3c5fe97
WY		 3152 if (!ent)
3153 return -ENOMEM;
07b7ddd9 3154
6a9c308d 3155 return drm_add_fake_info_node(minor, ent, fops);
07b7ddd9
JB		 3156}
3157
06c5bf8c 3158static const struct drm_info_list i915_debugfs_list[] = {
311bd68e 3159 {"i915_capabilities", i915_capabilities, 0},
73aa808f 3160 {"i915_gem_objects", i915_gem_object_info, 0},
08c18323 3161 {"i915_gem_gtt", i915_gem_gtt_info, 0},
1b50247a 3162 {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
433e12f7 3163 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
433e12f7 3164 {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
6d2b8885 3165 {"i915_gem_stolen", i915_gem_stolen_list_info },
4e5359cd 3166 {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
2017263e
BG		 3167 {"i915_gem_request", i915_gem_request_info, 0},
3168 {"i915_gem_seqno", i915_gem_seqno_info, 0},
a6172a80 3169 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
2017263e 3170 {"i915_gem_interrupt", i915_interrupt_info, 0},
1ec14ad3
CW		 3171 {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
3172 {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
3173 {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
9010ebfd 3174 {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
f97108d1
JB		 3175 {"i915_rstdby_delays", i915_rstdby_delays, 0},
3176 {"i915_cur_delayinfo", i915_cur_delayinfo, 0},
3177 {"i915_delayfreq_table", i915_delayfreq_table, 0},
3178 {"i915_inttoext_table", i915_inttoext_table, 0},
3179 {"i915_drpc_info", i915_drpc_info, 0},
7648fa99 3180 {"i915_emon_status", i915_emon_status, 0},
23b2f8bb 3181 {"i915_ring_freq_table", i915_ring_freq_table, 0},
7648fa99 3182 {"i915_gfxec", i915_gfxec, 0},
b5e50c3f 3183 {"i915_fbc_status", i915_fbc_status, 0},
92d44621 3184 {"i915_ips_status", i915_ips_status, 0},
4a9bef37 3185 {"i915_sr_status", i915_sr_status, 0},
44834a67 3186 {"i915_opregion", i915_opregion, 0},
37811fcc 3187 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
e76d3630 3188 {"i915_context_status", i915_context_status, 0},
6d794d42 3189 {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0},
ea16a3cd 3190 {"i915_swizzle_info", i915_swizzle_info, 0},
3cf17fc5 3191 {"i915_ppgtt_info", i915_ppgtt_info, 0},
57f350b6 3192 {"i915_dpio", i915_dpio_info, 0},
63573eb7 3193 {"i915_llc", i915_llc, 0},
e91fd8c6 3194 {"i915_edp_psr_status", i915_edp_psr_status, 0},
ec013e7f 3195 {"i915_energy_uJ", i915_energy_uJ, 0},
371db66a 3196 {"i915_pc8_status", i915_pc8_status, 0},
1da51581 3197 {"i915_power_domain_info", i915_power_domain_info, 0},
2017263e 3198};
27c202ad 3199#define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
2017263e 3200
06c5bf8c 3201static const struct i915_debugfs_files {
34b9674c
DV		 3202 const char *name;
3203 const struct file_operations *fops;
3204} i915_debugfs_files[] = {
3205 {"i915_wedged", &i915_wedged_fops},
3206 {"i915_max_freq", &i915_max_freq_fops},
3207 {"i915_min_freq", &i915_min_freq_fops},
3208 {"i915_cache_sharing", &i915_cache_sharing_fops},
3209 {"i915_ring_stop", &i915_ring_stop_fops},
094f9a54
CW		 3210 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
3211 {"i915_ring_test_irq", &i915_ring_test_irq_fops},
34b9674c
DV		 3212 {"i915_gem_drop_caches", &i915_drop_caches_fops},
3213 {"i915_error_state", &i915_error_state_fops},
3214 {"i915_next_seqno", &i915_next_seqno_fops},
bd9db02f 3215 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
34b9674c
DV		 3216};
3217
07144428
DL		 3218void intel_display_crc_init(struct drm_device *dev)
3219{
3220 struct drm_i915_private *dev_priv = dev->dev_private;
b378360e 3221 enum pipe pipe;
07144428 3222
b378360e
DV		 3223 for_each_pipe(pipe) {
3224 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
07144428 3225
d538bbdf
DL		 3226 pipe_crc->opened = false;
3227 spin_lock_init(&pipe_crc->lock);
07144428
DL		 3228 init_waitqueue_head(&pipe_crc->wq);
3229 }
3230}
3231
27c202ad 3232int i915_debugfs_init(struct drm_minor *minor)
2017263e 3233{
34b9674c 3234 int ret, i;
f3cd474b 3235
6d794d42 3236 ret = i915_forcewake_create(minor->debugfs_root, minor);
358733e9
JB		 3237 if (ret)
3238 return ret;
6a9c308d 3239
07144428
DL		 3240 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
3241 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
3242 if (ret)
3243 return ret;
3244 }
3245
34b9674c
DV		 3246 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
3247 ret = i915_debugfs_create(minor->debugfs_root, minor,
3248 i915_debugfs_files[i].name,
3249 i915_debugfs_files[i].fops);
3250 if (ret)
3251 return ret;
3252 }
40633219 3253
27c202ad
BG		 3254 return drm_debugfs_create_files(i915_debugfs_list,
3255 I915_DEBUGFS_ENTRIES,
2017263e
BG		 3256 minor->debugfs_root, minor);
3257}
3258
27c202ad 3259void i915_debugfs_cleanup(struct drm_minor *minor)
2017263e 3260{
34b9674c
DV		 3261 int i;
3262
27c202ad
BG		 3263 drm_debugfs_remove_files(i915_debugfs_list,
3264 I915_DEBUGFS_ENTRIES, minor);
07144428 3265
6d794d42
BW		 3266 drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
3267 1, minor);
07144428 3268
e309a997 3269 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
07144428
DL		 3270 struct drm_info_list *info_list =
3271 (struct drm_info_list *)&i915_pipe_crc_data[i];
3272
3273 drm_debugfs_remove_files(info_list, 1, minor);
3274 }
3275
34b9674c
DV		 3276 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
3277 struct drm_info_list *info_list =
3278 (struct drm_info_list *) i915_debugfs_files[i].fops;
3279
3280 drm_debugfs_remove_files(info_list, 1, minor);
3281 }
2017263e 3282}
Linux kernel - Deliverables
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