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drm/i915: Rebalance runtime pm vs forcewake
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_debugfs.c
CommitLineData
2017263e
BG		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 *
27 */
28
29#include <linux/seq_file.h>
b2c88f5b 30#include <linux/circ_buf.h>
926321d5 31#include <linux/ctype.h>
f3cd474b 32#include <linux/debugfs.h>
5a0e3ad6 33#include <linux/slab.h>
2d1a8a48 34#include <linux/export.h>
6d2b8885 35#include <linux/list_sort.h>
ec013e7f 36#include <asm/msr-index.h>
760285e7 37#include <drm/drmP.h>
4e5359cd 38#include "intel_drv.h"
e5c65260 39#include "intel_ringbuffer.h"
760285e7 40#include <drm/i915_drm.h>
2017263e
BG		 41#include "i915_drv.h"
42
f13d3f73 43enum {
69dc4987 44 ACTIVE_LIST,
f13d3f73 45 INACTIVE_LIST,
d21d5975 46 PINNED_LIST,
f13d3f73 47};
2017263e 48
70d39fe4
CW		 49static const char *yesno(int v)
50{
51 return v ? "yes" : "no";
52}
53
497666d8
DL		 54/* As the drm_debugfs_init() routines are called before dev->dev_private is
55 * allocated we need to hook into the minor for release. */
56static int
57drm_add_fake_info_node(struct drm_minor *minor,
58 struct dentry *ent,
59 const void *key)
60{
61 struct drm_info_node *node;
62
63 node = kmalloc(sizeof(*node), GFP_KERNEL);
64 if (node == NULL) {
65 debugfs_remove(ent);
66 return -ENOMEM;
67 }
68
69 node->minor = minor;
70 node->dent = ent;
71 node->info_ent = (void *) key;
72
73 mutex_lock(&minor->debugfs_lock);
74 list_add(&node->list, &minor->debugfs_list);
75 mutex_unlock(&minor->debugfs_lock);
76
77 return 0;
78}
79
70d39fe4
CW		 80static int i915_capabilities(struct seq_file *m, void *data)
81{
9f25d007 82 struct drm_info_node *node = m->private;
70d39fe4
CW		 83 struct drm_device *dev = node->minor->dev;
84 const struct intel_device_info *info = INTEL_INFO(dev);
85
86 seq_printf(m, "gen: %d\n", info->gen);
03d00ac5 87 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
79fc46df
DL		 88#define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
89#define SEP_SEMICOLON ;
90 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
91#undef PRINT_FLAG
92#undef SEP_SEMICOLON
70d39fe4
CW		 93
94 return 0;
95}
2017263e 96
05394f39 97static const char *get_pin_flag(struct drm_i915_gem_object *obj)
a6172a80 98{
4feb7659 99 if (i915_gem_obj_is_pinned(obj))
a6172a80
CW		 100 return "p";
101 else
102 return " ";
103}
104
05394f39 105static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
a6172a80 106{
0206e353
AJ		 107 switch (obj->tiling_mode) {
108 default:
109 case I915_TILING_NONE: return " ";
110 case I915_TILING_X: return "X";
111 case I915_TILING_Y: return "Y";
112 }
a6172a80
CW		 113}
114
1d693bcc
BW		 115static inline const char *get_global_flag(struct drm_i915_gem_object *obj)
116{
aff43766 117 return i915_gem_obj_to_ggtt(obj) ? "g" : " ";
1d693bcc
BW		 118}
119
37811fcc
CW		 120static void
121describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
122{
1d693bcc 123 struct i915_vma *vma;
d7f46fc4
BW		 124 int pin_count = 0;
125
fb1ae911 126 seq_printf(m, "%pK: %s%s%s %8zdKiB %02x %02x %u %u %u%s%s%s",
37811fcc
CW		 127 &obj->base,
128 get_pin_flag(obj),
129 get_tiling_flag(obj),
1d693bcc 130 get_global_flag(obj),
a05a5862 131 obj->base.size / 1024,
37811fcc
CW		 132 obj->base.read_domains,
133 obj->base.write_domain,
97b2a6a1
JH		 134 i915_gem_request_get_seqno(obj->last_read_req),
135 i915_gem_request_get_seqno(obj->last_write_req),
136 i915_gem_request_get_seqno(obj->last_fenced_req),
0a4cd7c8 137 i915_cache_level_str(to_i915(obj->base.dev), obj->cache_level),
37811fcc
CW		 138 obj->dirty ? " dirty" : "",
139 obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
140 if (obj->base.name)
141 seq_printf(m, " (name: %d)", obj->base.name);
d7f46fc4
BW		 142 list_for_each_entry(vma, &obj->vma_list, vma_link)
143 if (vma->pin_count > 0)
144 pin_count++;
145 seq_printf(m, " (pinned x %d)", pin_count);
cc98b413
CW		 146 if (obj->pin_display)
147 seq_printf(m, " (display)");
37811fcc
CW		 148 if (obj->fence_reg != I915_FENCE_REG_NONE)
149 seq_printf(m, " (fence: %d)", obj->fence_reg);
1d693bcc
BW		 150 list_for_each_entry(vma, &obj->vma_list, vma_link) {
151 if (!i915_is_ggtt(vma->vm))
152 seq_puts(m, " (pp");
153 else
154 seq_puts(m, " (g");
fe14d5f4
TU		 155 seq_printf(m, "gtt offset: %08lx, size: %08lx, type: %u)",
156 vma->node.start, vma->node.size,
157 vma->ggtt_view.type);
1d693bcc 158 }
c1ad11fc
CW		 159 if (obj->stolen)
160 seq_printf(m, " (stolen: %08lx)", obj->stolen->start);
6299f992
CW		 161 if (obj->pin_mappable || obj->fault_mappable) {
162 char s[3], *t = s;
163 if (obj->pin_mappable)
164 *t++ = 'p';
165 if (obj->fault_mappable)
166 *t++ = 'f';
167 *t = '\0';
168 seq_printf(m, " (%s mappable)", s);
169 }
41c52415
JH		 170 if (obj->last_read_req != NULL)
171 seq_printf(m, " (%s)",
172 i915_gem_request_get_ring(obj->last_read_req)->name);
d5a81ef1
DV		 173 if (obj->frontbuffer_bits)
174 seq_printf(m, " (frontbuffer: 0x%03x)", obj->frontbuffer_bits);
37811fcc
CW		 175}
176
273497e5 177static void describe_ctx(struct seq_file *m, struct intel_context *ctx)
3ccfd19d 178{
ea0c76f8 179 seq_putc(m, ctx->legacy_hw_ctx.initialized ? 'I' : 'i');
3ccfd19d
BW		 180 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
181 seq_putc(m, ' ');
182}
183
433e12f7 184static int i915_gem_object_list_info(struct seq_file *m, void *data)
2017263e 185{
9f25d007 186 struct drm_info_node *node = m->private;
433e12f7
BG		 187 uintptr_t list = (uintptr_t) node->info_ent->data;
188 struct list_head *head;
2017263e 189 struct drm_device *dev = node->minor->dev;
5cef07e1
BW		 190 struct drm_i915_private *dev_priv = dev->dev_private;
191 struct i915_address_space *vm = &dev_priv->gtt.base;
ca191b13 192 struct i915_vma *vma;
8f2480fb
CW		 193 size_t total_obj_size, total_gtt_size;
194 int count, ret;
de227ef0
CW		 195
196 ret = mutex_lock_interruptible(&dev->struct_mutex);
197 if (ret)
198 return ret;
2017263e 199
ca191b13 200 /* FIXME: the user of this interface might want more than just GGTT */
433e12f7
BG		 201 switch (list) {
202 case ACTIVE_LIST:
267f0c90 203 seq_puts(m, "Active:\n");
5cef07e1 204 head = &vm->active_list;
433e12f7
BG		 205 break;
206 case INACTIVE_LIST:
267f0c90 207 seq_puts(m, "Inactive:\n");
5cef07e1 208 head = &vm->inactive_list;
433e12f7 209 break;
433e12f7 210 default:
de227ef0
CW		 211 mutex_unlock(&dev->struct_mutex);
212 return -EINVAL;
2017263e 213 }
2017263e 214
8f2480fb 215 total_obj_size = total_gtt_size = count = 0;
ca191b13
BW		 216 list_for_each_entry(vma, head, mm_list) {
217 seq_printf(m, " ");
218 describe_obj(m, vma->obj);
219 seq_printf(m, "\n");
220 total_obj_size += vma->obj->base.size;
221 total_gtt_size += vma->node.size;
8f2480fb 222 count++;
2017263e 223 }
de227ef0 224 mutex_unlock(&dev->struct_mutex);
5e118f41 225
8f2480fb
CW		 226 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
227 count, total_obj_size, total_gtt_size);
2017263e
BG		 228 return 0;
229}
230
6d2b8885
CW		 231static int obj_rank_by_stolen(void *priv,
232 struct list_head *A, struct list_head *B)
233{
234 struct drm_i915_gem_object *a =
b25cb2f8 235 container_of(A, struct drm_i915_gem_object, obj_exec_link);
6d2b8885 236 struct drm_i915_gem_object *b =
b25cb2f8 237 container_of(B, struct drm_i915_gem_object, obj_exec_link);
6d2b8885
CW		 238
239 return a->stolen->start - b->stolen->start;
240}
241
242static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
243{
9f25d007 244 struct drm_info_node *node = m->private;
6d2b8885
CW		 245 struct drm_device *dev = node->minor->dev;
246 struct drm_i915_private *dev_priv = dev->dev_private;
247 struct drm_i915_gem_object *obj;
248 size_t total_obj_size, total_gtt_size;
249 LIST_HEAD(stolen);
250 int count, ret;
251
252 ret = mutex_lock_interruptible(&dev->struct_mutex);
253 if (ret)
254 return ret;
255
256 total_obj_size = total_gtt_size = count = 0;
257 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
258 if (obj->stolen == NULL)
259 continue;
260
b25cb2f8 261 list_add(&obj->obj_exec_link, &stolen);
6d2b8885
CW		 262
263 total_obj_size += obj->base.size;
264 total_gtt_size += i915_gem_obj_ggtt_size(obj);
265 count++;
266 }
267 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
268 if (obj->stolen == NULL)
269 continue;
270
b25cb2f8 271 list_add(&obj->obj_exec_link, &stolen);
6d2b8885
CW		 272
273 total_obj_size += obj->base.size;
274 count++;
275 }
276 list_sort(NULL, &stolen, obj_rank_by_stolen);
277 seq_puts(m, "Stolen:\n");
278 while (!list_empty(&stolen)) {
b25cb2f8 279 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
6d2b8885
CW		 280 seq_puts(m, " ");
281 describe_obj(m, obj);
282 seq_putc(m, '\n');
b25cb2f8 283 list_del_init(&obj->obj_exec_link);
6d2b8885
CW		 284 }
285 mutex_unlock(&dev->struct_mutex);
286
287 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
288 count, total_obj_size, total_gtt_size);
289 return 0;
290}
291
6299f992
CW		 292#define count_objects(list, member) do { \
293 list_for_each_entry(obj, list, member) { \
f343c5f6 294 size += i915_gem_obj_ggtt_size(obj); \
6299f992
CW		 295 ++count; \
296 if (obj->map_and_fenceable) { \
f343c5f6 297 mappable_size += i915_gem_obj_ggtt_size(obj); \
6299f992
CW		 298 ++mappable_count; \
299 } \
300 } \
0206e353 301} while (0)
6299f992 302
2db8e9d6 303struct file_stats {
6313c204 304 struct drm_i915_file_private *file_priv;
2db8e9d6 305 int count;
c67a17e9
CW		 306 size_t total, unbound;
307 size_t global, shared;
308 size_t active, inactive;
2db8e9d6
CW		 309};
310
311static int per_file_stats(int id, void *ptr, void *data)
312{
313 struct drm_i915_gem_object *obj = ptr;
314 struct file_stats *stats = data;
6313c204 315 struct i915_vma *vma;
2db8e9d6
CW		 316
317 stats->count++;
318 stats->total += obj->base.size;
319
c67a17e9
CW		 320 if (obj->base.name || obj->base.dma_buf)
321 stats->shared += obj->base.size;
322
6313c204
CW		 323 if (USES_FULL_PPGTT(obj->base.dev)) {
324 list_for_each_entry(vma, &obj->vma_list, vma_link) {
325 struct i915_hw_ppgtt *ppgtt;
326
327 if (!drm_mm_node_allocated(&vma->node))
328 continue;
329
330 if (i915_is_ggtt(vma->vm)) {
331 stats->global += obj->base.size;
332 continue;
333 }
334
335 ppgtt = container_of(vma->vm, struct i915_hw_ppgtt, base);
4d884705 336 if (ppgtt->file_priv != stats->file_priv)
6313c204
CW		 337 continue;
338
41c52415 339 if (obj->active) /* XXX per-vma statistic */
6313c204
CW		 340 stats->active += obj->base.size;
341 else
342 stats->inactive += obj->base.size;
343
344 return 0;
345 }
2db8e9d6 346 } else {
6313c204
CW		 347 if (i915_gem_obj_ggtt_bound(obj)) {
348 stats->global += obj->base.size;
41c52415 349 if (obj->active)
6313c204
CW		 350 stats->active += obj->base.size;
351 else
352 stats->inactive += obj->base.size;
353 return 0;
354 }
2db8e9d6
CW		 355 }
356
6313c204
CW		 357 if (!list_empty(&obj->global_list))
358 stats->unbound += obj->base.size;
359
2db8e9d6
CW		 360 return 0;
361}
362
493018dc
BV		 363#define print_file_stats(m, name, stats) \
364 seq_printf(m, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu global, %zu shared, %zu unbound)\n", \
365 name, \
366 stats.count, \
367 stats.total, \
368 stats.active, \
369 stats.inactive, \
370 stats.global, \
371 stats.shared, \
372 stats.unbound)
373
374static void print_batch_pool_stats(struct seq_file *m,
375 struct drm_i915_private *dev_priv)
376{
377 struct drm_i915_gem_object *obj;
378 struct file_stats stats;
379
380 memset(&stats, 0, sizeof(stats));
381
382 list_for_each_entry(obj,
383 &dev_priv->mm.batch_pool.cache_list,
384 batch_pool_list)
385 per_file_stats(0, obj, &stats);
386
387 print_file_stats(m, "batch pool", stats);
388}
389
ca191b13
BW		 390#define count_vmas(list, member) do { \
391 list_for_each_entry(vma, list, member) { \
392 size += i915_gem_obj_ggtt_size(vma->obj); \
393 ++count; \
394 if (vma->obj->map_and_fenceable) { \
395 mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
396 ++mappable_count; \
397 } \
398 } \
399} while (0)
400
401static int i915_gem_object_info(struct seq_file *m, void* data)
73aa808f 402{
9f25d007 403 struct drm_info_node *node = m->private;
73aa808f
CW		 404 struct drm_device *dev = node->minor->dev;
405 struct drm_i915_private *dev_priv = dev->dev_private;
b7abb714
CW		 406 u32 count, mappable_count, purgeable_count;
407 size_t size, mappable_size, purgeable_size;
6299f992 408 struct drm_i915_gem_object *obj;
5cef07e1 409 struct i915_address_space *vm = &dev_priv->gtt.base;
2db8e9d6 410 struct drm_file *file;
ca191b13 411 struct i915_vma *vma;
73aa808f
CW		 412 int ret;
413
414 ret = mutex_lock_interruptible(&dev->struct_mutex);
415 if (ret)
416 return ret;
417
6299f992
CW		 418 seq_printf(m, "%u objects, %zu bytes\n",
419 dev_priv->mm.object_count,
420 dev_priv->mm.object_memory);
421
422 size = count = mappable_size = mappable_count = 0;
35c20a60 423 count_objects(&dev_priv->mm.bound_list, global_list);
6299f992
CW		 424 seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n",
425 count, mappable_count, size, mappable_size);
426
427 size = count = mappable_size = mappable_count = 0;
ca191b13 428 count_vmas(&vm->active_list, mm_list);
6299f992
CW		 429 seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n",
430 count, mappable_count, size, mappable_size);
431
6299f992 432 size = count = mappable_size = mappable_count = 0;
ca191b13 433 count_vmas(&vm->inactive_list, mm_list);
6299f992
CW		 434 seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n",
435 count, mappable_count, size, mappable_size);
436
b7abb714 437 size = count = purgeable_size = purgeable_count = 0;
35c20a60 438 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
6c085a72 439 size += obj->base.size, ++count;
b7abb714
CW		 440 if (obj->madv == I915_MADV_DONTNEED)
441 purgeable_size += obj->base.size, ++purgeable_count;
442 }
6c085a72
CW		 443 seq_printf(m, "%u unbound objects, %zu bytes\n", count, size);
444
6299f992 445 size = count = mappable_size = mappable_count = 0;
35c20a60 446 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
6299f992 447 if (obj->fault_mappable) {
f343c5f6 448 size += i915_gem_obj_ggtt_size(obj);
6299f992
CW		 449 ++count;
450 }
451 if (obj->pin_mappable) {
f343c5f6 452 mappable_size += i915_gem_obj_ggtt_size(obj);
6299f992
CW		 453 ++mappable_count;
454 }
b7abb714
CW		 455 if (obj->madv == I915_MADV_DONTNEED) {
456 purgeable_size += obj->base.size;
457 ++purgeable_count;
458 }
6299f992 459 }
b7abb714
CW		 460 seq_printf(m, "%u purgeable objects, %zu bytes\n",
461 purgeable_count, purgeable_size);
6299f992
CW		 462 seq_printf(m, "%u pinned mappable objects, %zu bytes\n",
463 mappable_count, mappable_size);
464 seq_printf(m, "%u fault mappable objects, %zu bytes\n",
465 count, size);
466
93d18799 467 seq_printf(m, "%zu [%lu] gtt total\n",
853ba5d2
BW		 468 dev_priv->gtt.base.total,
469 dev_priv->gtt.mappable_end - dev_priv->gtt.base.start);
73aa808f 470
493018dc
BV		 471 seq_putc(m, '\n');
472 print_batch_pool_stats(m, dev_priv);
473
267f0c90 474 seq_putc(m, '\n');
2db8e9d6
CW		 475 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
476 struct file_stats stats;
3ec2f427 477 struct task_struct *task;
2db8e9d6
CW		 478
479 memset(&stats, 0, sizeof(stats));
6313c204 480 stats.file_priv = file->driver_priv;
5b5ffff0 481 spin_lock(&file->table_lock);
2db8e9d6 482 idr_for_each(&file->object_idr, per_file_stats, &stats);
5b5ffff0 483 spin_unlock(&file->table_lock);
3ec2f427
TH		 484 /*
485 * Although we have a valid reference on file->pid, that does
486 * not guarantee that the task_struct who called get_pid() is
487 * still alive (e.g. get_pid(current) => fork() => exit()).
488 * Therefore, we need to protect this ->comm access using RCU.
489 */
490 rcu_read_lock();
491 task = pid_task(file->pid, PIDTYPE_PID);
493018dc 492 print_file_stats(m, task ? task->comm : "<unknown>", stats);
3ec2f427 493 rcu_read_unlock();
2db8e9d6
CW		 494 }
495
73aa808f
CW		 496 mutex_unlock(&dev->struct_mutex);
497
498 return 0;
499}
500
aee56cff 501static int i915_gem_gtt_info(struct seq_file *m, void *data)
08c18323 502{
9f25d007 503 struct drm_info_node *node = m->private;
08c18323 504 struct drm_device *dev = node->minor->dev;
1b50247a 505 uintptr_t list = (uintptr_t) node->info_ent->data;
08c18323
CW		 506 struct drm_i915_private *dev_priv = dev->dev_private;
507 struct drm_i915_gem_object *obj;
508 size_t total_obj_size, total_gtt_size;
509 int count, ret;
510
511 ret = mutex_lock_interruptible(&dev->struct_mutex);
512 if (ret)
513 return ret;
514
515 total_obj_size = total_gtt_size = count = 0;
35c20a60 516 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
d7f46fc4 517 if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj))
1b50247a
CW		 518 continue;
519
267f0c90 520 seq_puts(m, " ");
08c18323 521 describe_obj(m, obj);
267f0c90 522 seq_putc(m, '\n');
08c18323 523 total_obj_size += obj->base.size;
f343c5f6 524 total_gtt_size += i915_gem_obj_ggtt_size(obj);
08c18323
CW		 525 count++;
526 }
527
528 mutex_unlock(&dev->struct_mutex);
529
530 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
531 count, total_obj_size, total_gtt_size);
532
533 return 0;
534}
535
4e5359cd
SF		 536static int i915_gem_pageflip_info(struct seq_file *m, void *data)
537{
9f25d007 538 struct drm_info_node *node = m->private;
4e5359cd 539 struct drm_device *dev = node->minor->dev;
d6bbafa1 540 struct drm_i915_private *dev_priv = dev->dev_private;
4e5359cd 541 struct intel_crtc *crtc;
8a270ebf
DV		 542 int ret;
543
544 ret = mutex_lock_interruptible(&dev->struct_mutex);
545 if (ret)
546 return ret;
4e5359cd 547
d3fcc808 548 for_each_intel_crtc(dev, crtc) {
9db4a9c7
JB		 549 const char pipe = pipe_name(crtc->pipe);
550 const char plane = plane_name(crtc->plane);
4e5359cd
SF		 551 struct intel_unpin_work *work;
552
5e2d7afc 553 spin_lock_irq(&dev->event_lock);
4e5359cd
SF		 554 work = crtc->unpin_work;
555 if (work == NULL) {
9db4a9c7 556 seq_printf(m, "No flip due on pipe %c (plane %c)\n",
4e5359cd
SF		 557 pipe, plane);
558 } else {
d6bbafa1
CW		 559 u32 addr;
560
e7d841ca 561 if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9db4a9c7 562 seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
4e5359cd
SF		 563 pipe, plane);
564 } else {
9db4a9c7 565 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
4e5359cd
SF		 566 pipe, plane);
567 }
3a8a946e
DV		 568 if (work->flip_queued_req) {
569 struct intel_engine_cs *ring =
570 i915_gem_request_get_ring(work->flip_queued_req);
571
d6bbafa1 572 seq_printf(m, "Flip queued on %s at seqno %u, next seqno %u [current breadcrumb %u], completed? %d\n",
3a8a946e 573 ring->name,
f06cc1b9 574 i915_gem_request_get_seqno(work->flip_queued_req),
d6bbafa1 575 dev_priv->next_seqno,
3a8a946e 576 ring->get_seqno(ring, true),
1b5a433a 577 i915_gem_request_completed(work->flip_queued_req, true));
d6bbafa1
CW		 578 } else
579 seq_printf(m, "Flip not associated with any ring\n");
580 seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
581 work->flip_queued_vblank,
582 work->flip_ready_vblank,
583 drm_vblank_count(dev, crtc->pipe));
4e5359cd 584 if (work->enable_stall_check)
267f0c90 585 seq_puts(m, "Stall check enabled, ");
4e5359cd 586 else
267f0c90 587 seq_puts(m, "Stall check waiting for page flip ioctl, ");
e7d841ca 588 seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
4e5359cd 589
d6bbafa1
CW		 590 if (INTEL_INFO(dev)->gen >= 4)
591 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane)));
592 else
593 addr = I915_READ(DSPADDR(crtc->plane));
594 seq_printf(m, "Current scanout address 0x%08x\n", addr);
595
4e5359cd 596 if (work->pending_flip_obj) {
d6bbafa1
CW		 597 seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset);
598 seq_printf(m, "MMIO update completed? %d\n", addr == work->gtt_offset);
4e5359cd
SF		 599 }
600 }
5e2d7afc 601 spin_unlock_irq(&dev->event_lock);
4e5359cd
SF		 602 }
603
8a270ebf
DV		 604 mutex_unlock(&dev->struct_mutex);
605
4e5359cd
SF		 606 return 0;
607}
608
493018dc
BV		 609static int i915_gem_batch_pool_info(struct seq_file *m, void *data)
610{
611 struct drm_info_node *node = m->private;
612 struct drm_device *dev = node->minor->dev;
613 struct drm_i915_private *dev_priv = dev->dev_private;
614 struct drm_i915_gem_object *obj;
615 int count = 0;
616 int ret;
617
618 ret = mutex_lock_interruptible(&dev->struct_mutex);
619 if (ret)
620 return ret;
621
622 seq_puts(m, "cache:\n");
623 list_for_each_entry(obj,
624 &dev_priv->mm.batch_pool.cache_list,
625 batch_pool_list) {
626 seq_puts(m, " ");
627 describe_obj(m, obj);
628 seq_putc(m, '\n');
629 count++;
630 }
631
632 seq_printf(m, "total: %d\n", count);
633
634 mutex_unlock(&dev->struct_mutex);
635
636 return 0;
637}
638
2017263e
BG		 639static int i915_gem_request_info(struct seq_file *m, void *data)
640{
9f25d007 641 struct drm_info_node *node = m->private;
2017263e 642 struct drm_device *dev = node->minor->dev;
e277a1f8 643 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 644 struct intel_engine_cs *ring;
2017263e 645 struct drm_i915_gem_request *gem_request;
a2c7f6fd 646 int ret, count, i;
de227ef0
CW		 647
648 ret = mutex_lock_interruptible(&dev->struct_mutex);
649 if (ret)
650 return ret;
2017263e 651
c2c347a9 652 count = 0;
a2c7f6fd
CW		 653 for_each_ring(ring, dev_priv, i) {
654 if (list_empty(&ring->request_list))
655 continue;
656
657 seq_printf(m, "%s requests:\n", ring->name);
c2c347a9 658 list_for_each_entry(gem_request,
a2c7f6fd 659 &ring->request_list,
c2c347a9
CW		 660 list) {
661 seq_printf(m, " %d @ %d\n",
662 gem_request->seqno,
663 (int) (jiffies - gem_request->emitted_jiffies));
664 }
665 count++;
2017263e 666 }
de227ef0
CW		 667 mutex_unlock(&dev->struct_mutex);
668
c2c347a9 669 if (count == 0)
267f0c90 670 seq_puts(m, "No requests\n");
c2c347a9 671
2017263e
BG		 672 return 0;
673}
674
b2223497 675static void i915_ring_seqno_info(struct seq_file *m,
a4872ba6 676 struct intel_engine_cs *ring)
b2223497
CW		 677{
678 if (ring->get_seqno) {
43a7b924 679 seq_printf(m, "Current sequence (%s): %u\n",
b2eadbc8 680 ring->name, ring->get_seqno(ring, false));
b2223497
CW		 681 }
682}
683
2017263e
BG		 684static int i915_gem_seqno_info(struct seq_file *m, void *data)
685{
9f25d007 686 struct drm_info_node *node = m->private;
2017263e 687 struct drm_device *dev = node->minor->dev;
e277a1f8 688 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 689 struct intel_engine_cs *ring;
1ec14ad3 690 int ret, i;
de227ef0
CW		 691
692 ret = mutex_lock_interruptible(&dev->struct_mutex);
693 if (ret)
694 return ret;
c8c8fb33 695 intel_runtime_pm_get(dev_priv);
2017263e 696
a2c7f6fd
CW		 697 for_each_ring(ring, dev_priv, i)
698 i915_ring_seqno_info(m, ring);
de227ef0 699
c8c8fb33 700 intel_runtime_pm_put(dev_priv);
de227ef0
CW		 701 mutex_unlock(&dev->struct_mutex);
702
2017263e
BG		 703 return 0;
704}
705
706
707static int i915_interrupt_info(struct seq_file *m, void *data)
708{
9f25d007 709 struct drm_info_node *node = m->private;
2017263e 710 struct drm_device *dev = node->minor->dev;
e277a1f8 711 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 712 struct intel_engine_cs *ring;
9db4a9c7 713 int ret, i, pipe;
de227ef0
CW		 714
715 ret = mutex_lock_interruptible(&dev->struct_mutex);
716 if (ret)
717 return ret;
c8c8fb33 718 intel_runtime_pm_get(dev_priv);
2017263e 719
74e1ca8c 720 if (IS_CHERRYVIEW(dev)) {
74e1ca8c
VS		 721 seq_printf(m, "Master Interrupt Control:\t%08x\n",
722 I915_READ(GEN8_MASTER_IRQ));
723
724 seq_printf(m, "Display IER:\t%08x\n",
725 I915_READ(VLV_IER));
726 seq_printf(m, "Display IIR:\t%08x\n",
727 I915_READ(VLV_IIR));
728 seq_printf(m, "Display IIR_RW:\t%08x\n",
729 I915_READ(VLV_IIR_RW));
730 seq_printf(m, "Display IMR:\t%08x\n",
731 I915_READ(VLV_IMR));
055e393f 732 for_each_pipe(dev_priv, pipe)
74e1ca8c
VS		 733 seq_printf(m, "Pipe %c stat:\t%08x\n",
734 pipe_name(pipe),
735 I915_READ(PIPESTAT(pipe)));
736
737 seq_printf(m, "Port hotplug:\t%08x\n",
738 I915_READ(PORT_HOTPLUG_EN));
739 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
740 I915_READ(VLV_DPFLIPSTAT));
741 seq_printf(m, "DPINVGTT:\t%08x\n",
742 I915_READ(DPINVGTT));
743
744 for (i = 0; i < 4; i++) {
745 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
746 i, I915_READ(GEN8_GT_IMR(i)));
747 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
748 i, I915_READ(GEN8_GT_IIR(i)));
749 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
750 i, I915_READ(GEN8_GT_IER(i)));
751 }
752
753 seq_printf(m, "PCU interrupt mask:\t%08x\n",
754 I915_READ(GEN8_PCU_IMR));
755 seq_printf(m, "PCU interrupt identity:\t%08x\n",
756 I915_READ(GEN8_PCU_IIR));
757 seq_printf(m, "PCU interrupt enable:\t%08x\n",
758 I915_READ(GEN8_PCU_IER));
759 } else if (INTEL_INFO(dev)->gen >= 8) {
a123f157
BW		 760 seq_printf(m, "Master Interrupt Control:\t%08x\n",
761 I915_READ(GEN8_MASTER_IRQ));
762
763 for (i = 0; i < 4; i++) {
764 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
765 i, I915_READ(GEN8_GT_IMR(i)));
766 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
767 i, I915_READ(GEN8_GT_IIR(i)));
768 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
769 i, I915_READ(GEN8_GT_IER(i)));
770 }
771
055e393f 772 for_each_pipe(dev_priv, pipe) {
f458ebbc 773 if (!intel_display_power_is_enabled(dev_priv,
22c59960
PZ		 774 POWER_DOMAIN_PIPE(pipe))) {
775 seq_printf(m, "Pipe %c power disabled\n",
776 pipe_name(pipe));
777 continue;
778 }
a123f157 779 seq_printf(m, "Pipe %c IMR:\t%08x\n",
07d27e20
DL		 780 pipe_name(pipe),
781 I915_READ(GEN8_DE_PIPE_IMR(pipe)));
a123f157 782 seq_printf(m, "Pipe %c IIR:\t%08x\n",
07d27e20
DL		 783 pipe_name(pipe),
784 I915_READ(GEN8_DE_PIPE_IIR(pipe)));
a123f157 785 seq_printf(m, "Pipe %c IER:\t%08x\n",
07d27e20
DL		 786 pipe_name(pipe),
787 I915_READ(GEN8_DE_PIPE_IER(pipe)));
a123f157
BW		 788 }
789
790 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
791 I915_READ(GEN8_DE_PORT_IMR));
792 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
793 I915_READ(GEN8_DE_PORT_IIR));
794 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
795 I915_READ(GEN8_DE_PORT_IER));
796
797 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
798 I915_READ(GEN8_DE_MISC_IMR));
799 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
800 I915_READ(GEN8_DE_MISC_IIR));
801 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
802 I915_READ(GEN8_DE_MISC_IER));
803
804 seq_printf(m, "PCU interrupt mask:\t%08x\n",
805 I915_READ(GEN8_PCU_IMR));
806 seq_printf(m, "PCU interrupt identity:\t%08x\n",
807 I915_READ(GEN8_PCU_IIR));
808 seq_printf(m, "PCU interrupt enable:\t%08x\n",
809 I915_READ(GEN8_PCU_IER));
810 } else if (IS_VALLEYVIEW(dev)) {
7e231dbe
JB		 811 seq_printf(m, "Display IER:\t%08x\n",
812 I915_READ(VLV_IER));
813 seq_printf(m, "Display IIR:\t%08x\n",
814 I915_READ(VLV_IIR));
815 seq_printf(m, "Display IIR_RW:\t%08x\n",
816 I915_READ(VLV_IIR_RW));
817 seq_printf(m, "Display IMR:\t%08x\n",
818 I915_READ(VLV_IMR));
055e393f 819 for_each_pipe(dev_priv, pipe)
7e231dbe
JB		 820 seq_printf(m, "Pipe %c stat:\t%08x\n",
821 pipe_name(pipe),
822 I915_READ(PIPESTAT(pipe)));
823
824 seq_printf(m, "Master IER:\t%08x\n",
825 I915_READ(VLV_MASTER_IER));
826
827 seq_printf(m, "Render IER:\t%08x\n",
828 I915_READ(GTIER));
829 seq_printf(m, "Render IIR:\t%08x\n",
830 I915_READ(GTIIR));
831 seq_printf(m, "Render IMR:\t%08x\n",
832 I915_READ(GTIMR));
833
834 seq_printf(m, "PM IER:\t\t%08x\n",
835 I915_READ(GEN6_PMIER));
836 seq_printf(m, "PM IIR:\t\t%08x\n",
837 I915_READ(GEN6_PMIIR));
838 seq_printf(m, "PM IMR:\t\t%08x\n",
839 I915_READ(GEN6_PMIMR));
840
841 seq_printf(m, "Port hotplug:\t%08x\n",
842 I915_READ(PORT_HOTPLUG_EN));
843 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
844 I915_READ(VLV_DPFLIPSTAT));
845 seq_printf(m, "DPINVGTT:\t%08x\n",
846 I915_READ(DPINVGTT));
847
848 } else if (!HAS_PCH_SPLIT(dev)) {
5f6a1695
ZW		 849 seq_printf(m, "Interrupt enable: %08x\n",
850 I915_READ(IER));
851 seq_printf(m, "Interrupt identity: %08x\n",
852 I915_READ(IIR));
853 seq_printf(m, "Interrupt mask: %08x\n",
854 I915_READ(IMR));
055e393f 855 for_each_pipe(dev_priv, pipe)
9db4a9c7
JB		 856 seq_printf(m, "Pipe %c stat: %08x\n",
857 pipe_name(pipe),
858 I915_READ(PIPESTAT(pipe)));
5f6a1695
ZW		 859 } else {
860 seq_printf(m, "North Display Interrupt enable: %08x\n",
861 I915_READ(DEIER));
862 seq_printf(m, "North Display Interrupt identity: %08x\n",
863 I915_READ(DEIIR));
864 seq_printf(m, "North Display Interrupt mask: %08x\n",
865 I915_READ(DEIMR));
866 seq_printf(m, "South Display Interrupt enable: %08x\n",
867 I915_READ(SDEIER));
868 seq_printf(m, "South Display Interrupt identity: %08x\n",
869 I915_READ(SDEIIR));
870 seq_printf(m, "South Display Interrupt mask: %08x\n",
871 I915_READ(SDEIMR));
872 seq_printf(m, "Graphics Interrupt enable: %08x\n",
873 I915_READ(GTIER));
874 seq_printf(m, "Graphics Interrupt identity: %08x\n",
875 I915_READ(GTIIR));
876 seq_printf(m, "Graphics Interrupt mask: %08x\n",
877 I915_READ(GTIMR));
878 }
a2c7f6fd 879 for_each_ring(ring, dev_priv, i) {
a123f157 880 if (INTEL_INFO(dev)->gen >= 6) {
a2c7f6fd
CW		 881 seq_printf(m,
882 "Graphics Interrupt mask (%s): %08x\n",
883 ring->name, I915_READ_IMR(ring));
9862e600 884 }
a2c7f6fd 885 i915_ring_seqno_info(m, ring);
9862e600 886 }
c8c8fb33 887 intel_runtime_pm_put(dev_priv);
de227ef0
CW		 888 mutex_unlock(&dev->struct_mutex);
889
2017263e
BG		 890 return 0;
891}
892
a6172a80
CW		 893static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
894{
9f25d007 895 struct drm_info_node *node = m->private;
a6172a80 896 struct drm_device *dev = node->minor->dev;
e277a1f8 897 struct drm_i915_private *dev_priv = dev->dev_private;
de227ef0
CW		 898 int i, ret;
899
900 ret = mutex_lock_interruptible(&dev->struct_mutex);
901 if (ret)
902 return ret;
a6172a80
CW		 903
904 seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
905 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
906 for (i = 0; i < dev_priv->num_fence_regs; i++) {
05394f39 907 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
a6172a80 908
6c085a72
CW		 909 seq_printf(m, "Fence %d, pin count = %d, object = ",
910 i, dev_priv->fence_regs[i].pin_count);
c2c347a9 911 if (obj == NULL)
267f0c90 912 seq_puts(m, "unused");
c2c347a9 913 else
05394f39 914 describe_obj(m, obj);
267f0c90 915 seq_putc(m, '\n');
a6172a80
CW		 916 }
917
05394f39 918 mutex_unlock(&dev->struct_mutex);
a6172a80
CW		 919 return 0;
920}
921
2017263e
BG		 922static int i915_hws_info(struct seq_file *m, void *data)
923{
9f25d007 924 struct drm_info_node *node = m->private;
2017263e 925 struct drm_device *dev = node->minor->dev;
e277a1f8 926 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 927 struct intel_engine_cs *ring;
1a240d4d 928 const u32 *hws;
4066c0ae
CW		 929 int i;
930
1ec14ad3 931 ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
1a240d4d 932 hws = ring->status_page.page_addr;
2017263e
BG		 933 if (hws == NULL)
934 return 0;
935
936 for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
937 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
938 i * 4,
939 hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
940 }
941 return 0;
942}
943
d5442303
DV		 944static ssize_t
945i915_error_state_write(struct file *filp,
946 const char __user *ubuf,
947 size_t cnt,
948 loff_t *ppos)
949{
edc3d884 950 struct i915_error_state_file_priv *error_priv = filp->private_data;
d5442303 951 struct drm_device *dev = error_priv->dev;
22bcfc6a 952 int ret;
d5442303
DV		 953
954 DRM_DEBUG_DRIVER("Resetting error state\n");
955
22bcfc6a
DV		 956 ret = mutex_lock_interruptible(&dev->struct_mutex);
957 if (ret)
958 return ret;
959
d5442303
DV		 960 i915_destroy_error_state(dev);
961 mutex_unlock(&dev->struct_mutex);
962
963 return cnt;
964}
965
966static int i915_error_state_open(struct inode *inode, struct file *file)
967{
968 struct drm_device *dev = inode->i_private;
d5442303 969 struct i915_error_state_file_priv *error_priv;
d5442303
DV		 970
971 error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
972 if (!error_priv)
973 return -ENOMEM;
974
975 error_priv->dev = dev;
976
95d5bfb3 977 i915_error_state_get(dev, error_priv);
d5442303 978
edc3d884
MK		 979 file->private_data = error_priv;
980
981 return 0;
d5442303
DV		 982}
983
984static int i915_error_state_release(struct inode *inode, struct file *file)
985{
edc3d884 986 struct i915_error_state_file_priv *error_priv = file->private_data;
d5442303 987
95d5bfb3 988 i915_error_state_put(error_priv);
d5442303
DV		 989 kfree(error_priv);
990
edc3d884
MK		 991 return 0;
992}
993
4dc955f7
MK		 994static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
995 size_t count, loff_t *pos)
996{
997 struct i915_error_state_file_priv *error_priv = file->private_data;
998 struct drm_i915_error_state_buf error_str;
999 loff_t tmp_pos = 0;
1000 ssize_t ret_count = 0;
1001 int ret;
1002
0a4cd7c8 1003 ret = i915_error_state_buf_init(&error_str, to_i915(error_priv->dev), count, *pos);
4dc955f7
MK		 1004 if (ret)
1005 return ret;
edc3d884 1006
fc16b48b 1007 ret = i915_error_state_to_str(&error_str, error_priv);
edc3d884
MK		 1008 if (ret)
1009 goto out;
1010
edc3d884
MK		 1011 ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
1012 error_str.buf,
1013 error_str.bytes);
1014
1015 if (ret_count < 0)
1016 ret = ret_count;
1017 else
1018 *pos = error_str.start + ret_count;
1019out:
4dc955f7 1020 i915_error_state_buf_release(&error_str);
edc3d884 1021 return ret ?: ret_count;
d5442303
DV		 1022}
1023
1024static const struct file_operations i915_error_state_fops = {
1025 .owner = THIS_MODULE,
1026 .open = i915_error_state_open,
edc3d884 1027 .read = i915_error_state_read,
d5442303
DV		 1028 .write = i915_error_state_write,
1029 .llseek = default_llseek,
1030 .release = i915_error_state_release,
1031};
1032
647416f9
KC		 1033static int
1034i915_next_seqno_get(void *data, u64 *val)
40633219 1035{
647416f9 1036 struct drm_device *dev = data;
e277a1f8 1037 struct drm_i915_private *dev_priv = dev->dev_private;
40633219
MK		 1038 int ret;
1039
1040 ret = mutex_lock_interruptible(&dev->struct_mutex);
1041 if (ret)
1042 return ret;
1043
647416f9 1044 *val = dev_priv->next_seqno;
40633219
MK		 1045 mutex_unlock(&dev->struct_mutex);
1046
647416f9 1047 return 0;
40633219
MK		 1048}
1049
647416f9
KC		 1050static int
1051i915_next_seqno_set(void *data, u64 val)
1052{
1053 struct drm_device *dev = data;
40633219
MK		 1054 int ret;
1055
40633219
MK		 1056 ret = mutex_lock_interruptible(&dev->struct_mutex);
1057 if (ret)
1058 return ret;
1059
e94fbaa8 1060 ret = i915_gem_set_seqno(dev, val);
40633219
MK		 1061 mutex_unlock(&dev->struct_mutex);
1062
647416f9 1063 return ret;
40633219
MK		 1064}
1065
647416f9
KC		 1066DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
1067 i915_next_seqno_get, i915_next_seqno_set,
3a3b4f98 1068 "0x%llx\n");
40633219 1069
adb4bd12 1070static int i915_frequency_info(struct seq_file *m, void *unused)
f97108d1 1071{
9f25d007 1072 struct drm_info_node *node = m->private;
f97108d1 1073 struct drm_device *dev = node->minor->dev;
e277a1f8 1074 struct drm_i915_private *dev_priv = dev->dev_private;
c8c8fb33
PZ		 1075 int ret = 0;
1076
1077 intel_runtime_pm_get(dev_priv);
3b8d8d91 1078
5c9669ce
TR		 1079 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1080
3b8d8d91
JB		 1081 if (IS_GEN5(dev)) {
1082 u16 rgvswctl = I915_READ16(MEMSWCTL);
1083 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1084
1085 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1086 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1087 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1088 MEMSTAT_VID_SHIFT);
1089 seq_printf(m, "Current P-state: %d\n",
1090 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
daa3afb2
TR		 1091 } else if (IS_GEN6(dev) || (IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) ||
1092 IS_BROADWELL(dev)) {
3b8d8d91
JB		 1093 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1094 u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1095 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
0d8f9491 1096 u32 rpmodectl, rpinclimit, rpdeclimit;
8e8c06cd 1097 u32 rpstat, cagf, reqf;
ccab5c82
JB		 1098 u32 rpupei, rpcurup, rpprevup;
1099 u32 rpdownei, rpcurdown, rpprevdown;
9dd3c605 1100 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
3b8d8d91
JB		 1101 int max_freq;
1102
1103 /* RPSTAT1 is in the GT power well */
d1ebd816
BW		 1104 ret = mutex_lock_interruptible(&dev->struct_mutex);
1105 if (ret)
c8c8fb33 1106 goto out;
d1ebd816 1107
c8d9a590 1108 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3b8d8d91 1109
8e8c06cd
CW		 1110 reqf = I915_READ(GEN6_RPNSWREQ);
1111 reqf &= ~GEN6_TURBO_DISABLE;
daa3afb2 1112 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8e8c06cd
CW		 1113 reqf >>= 24;
1114 else
1115 reqf >>= 25;
1116 reqf *= GT_FREQUENCY_MULTIPLIER;
1117
0d8f9491
CW		 1118 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1119 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1120 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1121
ccab5c82
JB		 1122 rpstat = I915_READ(GEN6_RPSTAT1);
1123 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
1124 rpcurup = I915_READ(GEN6_RP_CUR_UP);
1125 rpprevup = I915_READ(GEN6_RP_PREV_UP);
1126 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
1127 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
1128 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
daa3afb2 1129 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
f82855d3
BW		 1130 cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1131 else
1132 cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
1133 cagf *= GT_FREQUENCY_MULTIPLIER;
ccab5c82 1134
c8d9a590 1135 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
d1ebd816
BW		 1136 mutex_unlock(&dev->struct_mutex);
1137
9dd3c605
PZ		 1138 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1139 pm_ier = I915_READ(GEN6_PMIER);
1140 pm_imr = I915_READ(GEN6_PMIMR);
1141 pm_isr = I915_READ(GEN6_PMISR);
1142 pm_iir = I915_READ(GEN6_PMIIR);
1143 pm_mask = I915_READ(GEN6_PMINTRMSK);
1144 } else {
1145 pm_ier = I915_READ(GEN8_GT_IER(2));
1146 pm_imr = I915_READ(GEN8_GT_IMR(2));
1147 pm_isr = I915_READ(GEN8_GT_ISR(2));
1148 pm_iir = I915_READ(GEN8_GT_IIR(2));
1149 pm_mask = I915_READ(GEN6_PMINTRMSK);
1150 }
0d8f9491 1151 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
9dd3c605 1152 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
3b8d8d91 1153 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
3b8d8d91
JB		 1154 seq_printf(m, "Render p-state ratio: %d\n",
1155 (gt_perf_status & 0xff00) >> 8);
1156 seq_printf(m, "Render p-state VID: %d\n",
1157 gt_perf_status & 0xff);
1158 seq_printf(m, "Render p-state limit: %d\n",
1159 rp_state_limits & 0xff);
0d8f9491
CW		 1160 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1161 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1162 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1163 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
8e8c06cd 1164 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
f82855d3 1165 seq_printf(m, "CAGF: %dMHz\n", cagf);
ccab5c82
JB		 1166 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
1167 GEN6_CURICONT_MASK);
1168 seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
1169 GEN6_CURBSYTAVG_MASK);
1170 seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
1171 GEN6_CURBSYTAVG_MASK);
1172 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
1173 GEN6_CURIAVG_MASK);
1174 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
1175 GEN6_CURBSYTAVG_MASK);
1176 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
1177 GEN6_CURBSYTAVG_MASK);
3b8d8d91
JB		 1178
1179 max_freq = (rp_state_cap & 0xff0000) >> 16;
1180 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
c8735b0c 1181 max_freq * GT_FREQUENCY_MULTIPLIER);
3b8d8d91
JB		 1182
1183 max_freq = (rp_state_cap & 0xff00) >> 8;
1184 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
c8735b0c 1185 max_freq * GT_FREQUENCY_MULTIPLIER);
3b8d8d91
JB		 1186
1187 max_freq = rp_state_cap & 0xff;
1188 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
c8735b0c 1189 max_freq * GT_FREQUENCY_MULTIPLIER);
31c77388
BW		 1190
1191 seq_printf(m, "Max overclocked frequency: %dMHz\n",
b39fb297 1192 dev_priv->rps.max_freq * GT_FREQUENCY_MULTIPLIER);
0a073b84 1193 } else if (IS_VALLEYVIEW(dev)) {
03af2045 1194 u32 freq_sts;
0a073b84 1195
259bd5d4 1196 mutex_lock(&dev_priv->rps.hw_lock);
64936258 1197 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
0a073b84
JB		 1198 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1199 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1200
0a073b84 1201 seq_printf(m, "max GPU freq: %d MHz\n",
b2435c94 1202 vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq));
0a073b84 1203
0a073b84 1204 seq_printf(m, "min GPU freq: %d MHz\n",
b2435c94 1205 vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq));
03af2045
VS		 1206
1207 seq_printf(m, "efficient (RPe) frequency: %d MHz\n",
b2435c94 1208 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
0a073b84
JB		 1209
1210 seq_printf(m, "current GPU freq: %d MHz\n",
2ec3815f 1211 vlv_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
259bd5d4 1212 mutex_unlock(&dev_priv->rps.hw_lock);
3b8d8d91 1213 } else {
267f0c90 1214 seq_puts(m, "no P-state info available\n");
3b8d8d91 1215 }
f97108d1 1216
c8c8fb33
PZ		 1217out:
1218 intel_runtime_pm_put(dev_priv);
1219 return ret;
f97108d1
JB		 1220}
1221
4d85529d 1222static int ironlake_drpc_info(struct seq_file *m)
f97108d1 1223{
9f25d007 1224 struct drm_info_node *node = m->private;
f97108d1 1225 struct drm_device *dev = node->minor->dev;
e277a1f8 1226 struct drm_i915_private *dev_priv = dev->dev_private;
616fdb5a
BW		 1227 u32 rgvmodectl, rstdbyctl;
1228 u16 crstandvid;
1229 int ret;
1230
1231 ret = mutex_lock_interruptible(&dev->struct_mutex);
1232 if (ret)
1233 return ret;
c8c8fb33 1234 intel_runtime_pm_get(dev_priv);
616fdb5a
BW		 1235
1236 rgvmodectl = I915_READ(MEMMODECTL);
1237 rstdbyctl = I915_READ(RSTDBYCTL);
1238 crstandvid = I915_READ16(CRSTANDVID);
1239
c8c8fb33 1240 intel_runtime_pm_put(dev_priv);
616fdb5a 1241 mutex_unlock(&dev->struct_mutex);
f97108d1
JB		 1242
1243 seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
1244 "yes" : "no");
1245 seq_printf(m, "Boost freq: %d\n",
1246 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1247 MEMMODE_BOOST_FREQ_SHIFT);
1248 seq_printf(m, "HW control enabled: %s\n",
1249 rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");
1250 seq_printf(m, "SW control enabled: %s\n",
1251 rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");
1252 seq_printf(m, "Gated voltage change: %s\n",
1253 rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");
1254 seq_printf(m, "Starting frequency: P%d\n",
1255 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
7648fa99 1256 seq_printf(m, "Max P-state: P%d\n",
f97108d1 1257 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
7648fa99
JB		 1258 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1259 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1260 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1261 seq_printf(m, "Render standby enabled: %s\n",
1262 (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes");
267f0c90 1263 seq_puts(m, "Current RS state: ");
88271da3
JB		 1264 switch (rstdbyctl & RSX_STATUS_MASK) {
1265 case RSX_STATUS_ON:
267f0c90 1266 seq_puts(m, "on\n");
88271da3
JB		 1267 break;
1268 case RSX_STATUS_RC1:
267f0c90 1269 seq_puts(m, "RC1\n");
88271da3
JB		 1270 break;
1271 case RSX_STATUS_RC1E:
267f0c90 1272 seq_puts(m, "RC1E\n");
88271da3
JB		 1273 break;
1274 case RSX_STATUS_RS1:
267f0c90 1275 seq_puts(m, "RS1\n");
88271da3
JB		 1276 break;
1277 case RSX_STATUS_RS2:
267f0c90 1278 seq_puts(m, "RS2 (RC6)\n");
88271da3
JB		 1279 break;
1280 case RSX_STATUS_RS3:
267f0c90 1281 seq_puts(m, "RC3 (RC6+)\n");
88271da3
JB		 1282 break;
1283 default:
267f0c90 1284 seq_puts(m, "unknown\n");
88271da3
JB		 1285 break;
1286 }
f97108d1
JB		 1287
1288 return 0;
1289}
1290
669ab5aa
D		 1291static int vlv_drpc_info(struct seq_file *m)
1292{
1293
9f25d007 1294 struct drm_info_node *node = m->private;
669ab5aa
D		 1295 struct drm_device *dev = node->minor->dev;
1296 struct drm_i915_private *dev_priv = dev->dev_private;
6b312cd3 1297 u32 rpmodectl1, rcctl1, pw_status;
669ab5aa
D		 1298 unsigned fw_rendercount = 0, fw_mediacount = 0;
1299
d46c0517
ID		 1300 intel_runtime_pm_get(dev_priv);
1301
6b312cd3 1302 pw_status = I915_READ(VLV_GTLC_PW_STATUS);
669ab5aa
D		 1303 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1304 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1305
d46c0517
ID		 1306 intel_runtime_pm_put(dev_priv);
1307
669ab5aa
D		 1308 seq_printf(m, "Video Turbo Mode: %s\n",
1309 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1310 seq_printf(m, "Turbo enabled: %s\n",
1311 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1312 seq_printf(m, "HW control enabled: %s\n",
1313 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1314 seq_printf(m, "SW control enabled: %s\n",
1315 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1316 GEN6_RP_MEDIA_SW_MODE));
1317 seq_printf(m, "RC6 Enabled: %s\n",
1318 yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1319 GEN6_RC_CTL_EI_MODE(1))));
1320 seq_printf(m, "Render Power Well: %s\n",
6b312cd3 1321 (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
669ab5aa 1322 seq_printf(m, "Media Power Well: %s\n",
6b312cd3 1323 (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
669ab5aa 1324
9cc19be5
ID		 1325 seq_printf(m, "Render RC6 residency since boot: %u\n",
1326 I915_READ(VLV_GT_RENDER_RC6));
1327 seq_printf(m, "Media RC6 residency since boot: %u\n",
1328 I915_READ(VLV_GT_MEDIA_RC6));
1329
669ab5aa
D		 1330 spin_lock_irq(&dev_priv->uncore.lock);
1331 fw_rendercount = dev_priv->uncore.fw_rendercount;
1332 fw_mediacount = dev_priv->uncore.fw_mediacount;
1333 spin_unlock_irq(&dev_priv->uncore.lock);
1334
1335 seq_printf(m, "Forcewake Render Count = %u\n", fw_rendercount);
1336 seq_printf(m, "Forcewake Media Count = %u\n", fw_mediacount);
1337
1338
1339 return 0;
1340}
1341
1342
4d85529d
BW		 1343static int gen6_drpc_info(struct seq_file *m)
1344{
1345
9f25d007 1346 struct drm_info_node *node = m->private;
4d85529d
BW		 1347 struct drm_device *dev = node->minor->dev;
1348 struct drm_i915_private *dev_priv = dev->dev_private;
ecd8faea 1349 u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
93b525dc 1350 unsigned forcewake_count;
aee56cff 1351 int count = 0, ret;
4d85529d
BW		 1352
1353 ret = mutex_lock_interruptible(&dev->struct_mutex);
1354 if (ret)
1355 return ret;
c8c8fb33 1356 intel_runtime_pm_get(dev_priv);
4d85529d 1357
907b28c5
CW		 1358 spin_lock_irq(&dev_priv->uncore.lock);
1359 forcewake_count = dev_priv->uncore.forcewake_count;
1360 spin_unlock_irq(&dev_priv->uncore.lock);
93b525dc
DV		 1361
1362 if (forcewake_count) {
267f0c90
DL		 1363 seq_puts(m, "RC information inaccurate because somebody "
1364 "holds a forcewake reference \n");
4d85529d
BW		 1365 } else {
1366 /* NB: we cannot use forcewake, else we read the wrong values */
1367 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1368 udelay(10);
1369 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1370 }
1371
1372 gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS);
ed71f1b4 1373 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
4d85529d
BW		 1374
1375 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1376 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1377 mutex_unlock(&dev->struct_mutex);
44cbd338
BW		 1378 mutex_lock(&dev_priv->rps.hw_lock);
1379 sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1380 mutex_unlock(&dev_priv->rps.hw_lock);
4d85529d 1381
c8c8fb33
PZ		 1382 intel_runtime_pm_put(dev_priv);
1383
4d85529d
BW		 1384 seq_printf(m, "Video Turbo Mode: %s\n",
1385 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1386 seq_printf(m, "HW control enabled: %s\n",
1387 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1388 seq_printf(m, "SW control enabled: %s\n",
1389 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1390 GEN6_RP_MEDIA_SW_MODE));
fff24e21 1391 seq_printf(m, "RC1e Enabled: %s\n",
4d85529d
BW		 1392 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1393 seq_printf(m, "RC6 Enabled: %s\n",
1394 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1395 seq_printf(m, "Deep RC6 Enabled: %s\n",
1396 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1397 seq_printf(m, "Deepest RC6 Enabled: %s\n",
1398 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
267f0c90 1399 seq_puts(m, "Current RC state: ");
4d85529d
BW		 1400 switch (gt_core_status & GEN6_RCn_MASK) {
1401 case GEN6_RC0:
1402 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
267f0c90 1403 seq_puts(m, "Core Power Down\n");
4d85529d 1404 else
267f0c90 1405 seq_puts(m, "on\n");
4d85529d
BW		 1406 break;
1407 case GEN6_RC3:
267f0c90 1408 seq_puts(m, "RC3\n");
4d85529d
BW		 1409 break;
1410 case GEN6_RC6:
267f0c90 1411 seq_puts(m, "RC6\n");
4d85529d
BW		 1412 break;
1413 case GEN6_RC7:
267f0c90 1414 seq_puts(m, "RC7\n");
4d85529d
BW		 1415 break;
1416 default:
267f0c90 1417 seq_puts(m, "Unknown\n");
4d85529d
BW		 1418 break;
1419 }
1420
1421 seq_printf(m, "Core Power Down: %s\n",
1422 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
cce66a28
BW		 1423
1424 /* Not exactly sure what this is */
1425 seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1426 I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1427 seq_printf(m, "RC6 residency since boot: %u\n",
1428 I915_READ(GEN6_GT_GFX_RC6));
1429 seq_printf(m, "RC6+ residency since boot: %u\n",
1430 I915_READ(GEN6_GT_GFX_RC6p));
1431 seq_printf(m, "RC6++ residency since boot: %u\n",
1432 I915_READ(GEN6_GT_GFX_RC6pp));
1433
ecd8faea
BW		 1434 seq_printf(m, "RC6 voltage: %dmV\n",
1435 GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1436 seq_printf(m, "RC6+ voltage: %dmV\n",
1437 GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1438 seq_printf(m, "RC6++ voltage: %dmV\n",
1439 GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
4d85529d
BW		 1440 return 0;
1441}
1442
1443static int i915_drpc_info(struct seq_file *m, void *unused)
1444{
9f25d007 1445 struct drm_info_node *node = m->private;
4d85529d
BW		 1446 struct drm_device *dev = node->minor->dev;
1447
669ab5aa
D		 1448 if (IS_VALLEYVIEW(dev))
1449 return vlv_drpc_info(m);
ac66cf4b 1450 else if (INTEL_INFO(dev)->gen >= 6)
4d85529d
BW		 1451 return gen6_drpc_info(m);
1452 else
1453 return ironlake_drpc_info(m);
1454}
1455
b5e50c3f
JB		 1456static int i915_fbc_status(struct seq_file *m, void *unused)
1457{
9f25d007 1458 struct drm_info_node *node = m->private;
b5e50c3f 1459 struct drm_device *dev = node->minor->dev;
e277a1f8 1460 struct drm_i915_private *dev_priv = dev->dev_private;
b5e50c3f 1461
3a77c4c4 1462 if (!HAS_FBC(dev)) {
267f0c90 1463 seq_puts(m, "FBC unsupported on this chipset\n");
b5e50c3f
JB		 1464 return 0;
1465 }
1466
36623ef8
PZ		 1467 intel_runtime_pm_get(dev_priv);
1468
ee5382ae 1469 if (intel_fbc_enabled(dev)) {
267f0c90 1470 seq_puts(m, "FBC enabled\n");
b5e50c3f 1471 } else {
267f0c90 1472 seq_puts(m, "FBC disabled: ");
5c3fe8b0 1473 switch (dev_priv->fbc.no_fbc_reason) {
29ebf90f
CW		 1474 case FBC_OK:
1475 seq_puts(m, "FBC actived, but currently disabled in hardware");
1476 break;
1477 case FBC_UNSUPPORTED:
1478 seq_puts(m, "unsupported by this chipset");
1479 break;
bed4a673 1480 case FBC_NO_OUTPUT:
267f0c90 1481 seq_puts(m, "no outputs");
bed4a673 1482 break;
b5e50c3f 1483 case FBC_STOLEN_TOO_SMALL:
267f0c90 1484 seq_puts(m, "not enough stolen memory");
b5e50c3f
JB		 1485 break;
1486 case FBC_UNSUPPORTED_MODE:
267f0c90 1487 seq_puts(m, "mode not supported");
b5e50c3f
JB		 1488 break;
1489 case FBC_MODE_TOO_LARGE:
267f0c90 1490 seq_puts(m, "mode too large");
b5e50c3f
JB		 1491 break;
1492 case FBC_BAD_PLANE:
267f0c90 1493 seq_puts(m, "FBC unsupported on plane");
b5e50c3f
JB		 1494 break;
1495 case FBC_NOT_TILED:
267f0c90 1496 seq_puts(m, "scanout buffer not tiled");
b5e50c3f 1497 break;
9c928d16 1498 case FBC_MULTIPLE_PIPES:
267f0c90 1499 seq_puts(m, "multiple pipes are enabled");
9c928d16 1500 break;
c1a9f047 1501 case FBC_MODULE_PARAM:
267f0c90 1502 seq_puts(m, "disabled per module param (default off)");
c1a9f047 1503 break;
8a5729a3 1504 case FBC_CHIP_DEFAULT:
267f0c90 1505 seq_puts(m, "disabled per chip default");
8a5729a3 1506 break;
b5e50c3f 1507 default:
267f0c90 1508 seq_puts(m, "unknown reason");
b5e50c3f 1509 }
267f0c90 1510 seq_putc(m, '\n');
b5e50c3f 1511 }
36623ef8
PZ		 1512
1513 intel_runtime_pm_put(dev_priv);
1514
b5e50c3f
JB		 1515 return 0;
1516}
1517
da46f936
RV		 1518static int i915_fbc_fc_get(void *data, u64 *val)
1519{
1520 struct drm_device *dev = data;
1521 struct drm_i915_private *dev_priv = dev->dev_private;
1522
1523 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1524 return -ENODEV;
1525
1526 drm_modeset_lock_all(dev);
1527 *val = dev_priv->fbc.false_color;
1528 drm_modeset_unlock_all(dev);
1529
1530 return 0;
1531}
1532
1533static int i915_fbc_fc_set(void *data, u64 val)
1534{
1535 struct drm_device *dev = data;
1536 struct drm_i915_private *dev_priv = dev->dev_private;
1537 u32 reg;
1538
1539 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1540 return -ENODEV;
1541
1542 drm_modeset_lock_all(dev);
1543
1544 reg = I915_READ(ILK_DPFC_CONTROL);
1545 dev_priv->fbc.false_color = val;
1546
1547 I915_WRITE(ILK_DPFC_CONTROL, val ?
1548 (reg | FBC_CTL_FALSE_COLOR) :
1549 (reg & ~FBC_CTL_FALSE_COLOR));
1550
1551 drm_modeset_unlock_all(dev);
1552 return 0;
1553}
1554
1555DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops,
1556 i915_fbc_fc_get, i915_fbc_fc_set,
1557 "%llu\n");
1558
92d44621
PZ		 1559static int i915_ips_status(struct seq_file *m, void *unused)
1560{
9f25d007 1561 struct drm_info_node *node = m->private;
92d44621
PZ		 1562 struct drm_device *dev = node->minor->dev;
1563 struct drm_i915_private *dev_priv = dev->dev_private;
1564
f5adf94e 1565 if (!HAS_IPS(dev)) {
92d44621
PZ		 1566 seq_puts(m, "not supported\n");
1567 return 0;
1568 }
1569
36623ef8
PZ		 1570 intel_runtime_pm_get(dev_priv);
1571
0eaa53f0
RV		 1572 seq_printf(m, "Enabled by kernel parameter: %s\n",
1573 yesno(i915.enable_ips));
1574
1575 if (INTEL_INFO(dev)->gen >= 8) {
1576 seq_puts(m, "Currently: unknown\n");
1577 } else {
1578 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1579 seq_puts(m, "Currently: enabled\n");
1580 else
1581 seq_puts(m, "Currently: disabled\n");
1582 }
92d44621 1583
36623ef8
PZ		 1584 intel_runtime_pm_put(dev_priv);
1585
92d44621
PZ		 1586 return 0;
1587}
1588
4a9bef37
JB		 1589static int i915_sr_status(struct seq_file *m, void *unused)
1590{
9f25d007 1591 struct drm_info_node *node = m->private;
4a9bef37 1592 struct drm_device *dev = node->minor->dev;
e277a1f8 1593 struct drm_i915_private *dev_priv = dev->dev_private;
4a9bef37
JB		 1594 bool sr_enabled = false;
1595
36623ef8
PZ		 1596 intel_runtime_pm_get(dev_priv);
1597
1398261a 1598 if (HAS_PCH_SPLIT(dev))
5ba2aaaa 1599 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
a6c45cf0 1600 else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))
4a9bef37
JB		 1601 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1602 else if (IS_I915GM(dev))
1603 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1604 else if (IS_PINEVIEW(dev))
1605 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1606
36623ef8
PZ		 1607 intel_runtime_pm_put(dev_priv);
1608
5ba2aaaa
CW		 1609 seq_printf(m, "self-refresh: %s\n",
1610 sr_enabled ? "enabled" : "disabled");
4a9bef37
JB		 1611
1612 return 0;
1613}
1614
7648fa99
JB		 1615static int i915_emon_status(struct seq_file *m, void *unused)
1616{
9f25d007 1617 struct drm_info_node *node = m->private;
7648fa99 1618 struct drm_device *dev = node->minor->dev;
e277a1f8 1619 struct drm_i915_private *dev_priv = dev->dev_private;
7648fa99 1620 unsigned long temp, chipset, gfx;
de227ef0
CW		 1621 int ret;
1622
582be6b4
CW		 1623 if (!IS_GEN5(dev))
1624 return -ENODEV;
1625
de227ef0
CW		 1626 ret = mutex_lock_interruptible(&dev->struct_mutex);
1627 if (ret)
1628 return ret;
7648fa99
JB		 1629
1630 temp = i915_mch_val(dev_priv);
1631 chipset = i915_chipset_val(dev_priv);
1632 gfx = i915_gfx_val(dev_priv);
de227ef0 1633 mutex_unlock(&dev->struct_mutex);
7648fa99
JB		 1634
1635 seq_printf(m, "GMCH temp: %ld\n", temp);
1636 seq_printf(m, "Chipset power: %ld\n", chipset);
1637 seq_printf(m, "GFX power: %ld\n", gfx);
1638 seq_printf(m, "Total power: %ld\n", chipset + gfx);
1639
1640 return 0;
1641}
1642
23b2f8bb
JB		 1643static int i915_ring_freq_table(struct seq_file *m, void *unused)
1644{
9f25d007 1645 struct drm_info_node *node = m->private;
23b2f8bb 1646 struct drm_device *dev = node->minor->dev;
e277a1f8 1647 struct drm_i915_private *dev_priv = dev->dev_private;
5bfa0199 1648 int ret = 0;
23b2f8bb
JB		 1649 int gpu_freq, ia_freq;
1650
1c70c0ce 1651 if (!(IS_GEN6(dev) || IS_GEN7(dev))) {
267f0c90 1652 seq_puts(m, "unsupported on this chipset\n");
23b2f8bb
JB		 1653 return 0;
1654 }
1655
5bfa0199
PZ		 1656 intel_runtime_pm_get(dev_priv);
1657
5c9669ce
TR		 1658 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1659
4fc688ce 1660 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
23b2f8bb 1661 if (ret)
5bfa0199 1662 goto out;
23b2f8bb 1663
267f0c90 1664 seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
23b2f8bb 1665
b39fb297
BW		 1666 for (gpu_freq = dev_priv->rps.min_freq_softlimit;
1667 gpu_freq <= dev_priv->rps.max_freq_softlimit;
23b2f8bb 1668 gpu_freq++) {
42c0526c
BW		 1669 ia_freq = gpu_freq;
1670 sandybridge_pcode_read(dev_priv,
1671 GEN6_PCODE_READ_MIN_FREQ_TABLE,
1672 &ia_freq);
3ebecd07
CW		 1673 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1674 gpu_freq * GT_FREQUENCY_MULTIPLIER,
1675 ((ia_freq >> 0) & 0xff) * 100,
1676 ((ia_freq >> 8) & 0xff) * 100);
23b2f8bb
JB		 1677 }
1678
4fc688ce 1679 mutex_unlock(&dev_priv->rps.hw_lock);
23b2f8bb 1680
5bfa0199
PZ		 1681out:
1682 intel_runtime_pm_put(dev_priv);
1683 return ret;
23b2f8bb
JB		 1684}
1685
44834a67
CW		 1686static int i915_opregion(struct seq_file *m, void *unused)
1687{
9f25d007 1688 struct drm_info_node *node = m->private;
44834a67 1689 struct drm_device *dev = node->minor->dev;
e277a1f8 1690 struct drm_i915_private *dev_priv = dev->dev_private;
44834a67 1691 struct intel_opregion *opregion = &dev_priv->opregion;
0d38f009 1692 void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL);
44834a67
CW		 1693 int ret;
1694
0d38f009
DV		 1695 if (data == NULL)
1696 return -ENOMEM;
1697
44834a67
CW		 1698 ret = mutex_lock_interruptible(&dev->struct_mutex);
1699 if (ret)
0d38f009 1700 goto out;
44834a67 1701
0d38f009
DV		 1702 if (opregion->header) {
1703 memcpy_fromio(data, opregion->header, OPREGION_SIZE);
1704 seq_write(m, data, OPREGION_SIZE);
1705 }
44834a67
CW		 1706
1707 mutex_unlock(&dev->struct_mutex);
1708
0d38f009
DV		 1709out:
1710 kfree(data);
44834a67
CW		 1711 return 0;
1712}
1713
37811fcc
CW		 1714static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1715{
9f25d007 1716 struct drm_info_node *node = m->private;
37811fcc 1717 struct drm_device *dev = node->minor->dev;
4520f53a 1718 struct intel_fbdev *ifbdev = NULL;
37811fcc 1719 struct intel_framebuffer *fb;
37811fcc 1720
4520f53a
DV		 1721#ifdef CONFIG_DRM_I915_FBDEV
1722 struct drm_i915_private *dev_priv = dev->dev_private;
37811fcc
CW		 1723
1724 ifbdev = dev_priv->fbdev;
1725 fb = to_intel_framebuffer(ifbdev->helper.fb);
1726
623f9783 1727 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
37811fcc
CW		 1728 fb->base.width,
1729 fb->base.height,
1730 fb->base.depth,
623f9783
DV		 1731 fb->base.bits_per_pixel,
1732 atomic_read(&fb->base.refcount.refcount));
05394f39 1733 describe_obj(m, fb->obj);
267f0c90 1734 seq_putc(m, '\n');
4520f53a 1735#endif
37811fcc 1736
4b096ac1 1737 mutex_lock(&dev->mode_config.fb_lock);
37811fcc 1738 list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) {
131a56dc 1739 if (ifbdev && &fb->base == ifbdev->helper.fb)
37811fcc
CW		 1740 continue;
1741
623f9783 1742 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
37811fcc
CW		 1743 fb->base.width,
1744 fb->base.height,
1745 fb->base.depth,
623f9783
DV		 1746 fb->base.bits_per_pixel,
1747 atomic_read(&fb->base.refcount.refcount));
05394f39 1748 describe_obj(m, fb->obj);
267f0c90 1749 seq_putc(m, '\n');
37811fcc 1750 }
4b096ac1 1751 mutex_unlock(&dev->mode_config.fb_lock);
37811fcc
CW		 1752
1753 return 0;
1754}
1755
c9fe99bd
OM		 1756static void describe_ctx_ringbuf(struct seq_file *m,
1757 struct intel_ringbuffer *ringbuf)
1758{
1759 seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
1760 ringbuf->space, ringbuf->head, ringbuf->tail,
1761 ringbuf->last_retired_head);
1762}
1763
e76d3630
BW		 1764static int i915_context_status(struct seq_file *m, void *unused)
1765{
9f25d007 1766 struct drm_info_node *node = m->private;
e76d3630 1767 struct drm_device *dev = node->minor->dev;
e277a1f8 1768 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 1769 struct intel_engine_cs *ring;
273497e5 1770 struct intel_context *ctx;
a168c293 1771 int ret, i;
e76d3630 1772
f3d28878 1773 ret = mutex_lock_interruptible(&dev->struct_mutex);
e76d3630
BW		 1774 if (ret)
1775 return ret;
1776
3e373948 1777 if (dev_priv->ips.pwrctx) {
267f0c90 1778 seq_puts(m, "power context ");
3e373948 1779 describe_obj(m, dev_priv->ips.pwrctx);
267f0c90 1780 seq_putc(m, '\n');
dc501fbc 1781 }
e76d3630 1782
3e373948 1783 if (dev_priv->ips.renderctx) {
267f0c90 1784 seq_puts(m, "render context ");
3e373948 1785 describe_obj(m, dev_priv->ips.renderctx);
267f0c90 1786 seq_putc(m, '\n');
dc501fbc 1787 }
e76d3630 1788
a33afea5 1789 list_for_each_entry(ctx, &dev_priv->context_list, link) {
c9fe99bd
OM		 1790 if (!i915.enable_execlists &&
1791 ctx->legacy_hw_ctx.rcs_state == NULL)
b77f6997
CW		 1792 continue;
1793
a33afea5 1794 seq_puts(m, "HW context ");
3ccfd19d 1795 describe_ctx(m, ctx);
c9fe99bd 1796 for_each_ring(ring, dev_priv, i) {
a33afea5 1797 if (ring->default_context == ctx)
c9fe99bd
OM		 1798 seq_printf(m, "(default context %s) ",
1799 ring->name);
1800 }
1801
1802 if (i915.enable_execlists) {
1803 seq_putc(m, '\n');
1804 for_each_ring(ring, dev_priv, i) {
1805 struct drm_i915_gem_object *ctx_obj =
1806 ctx->engine[i].state;
1807 struct intel_ringbuffer *ringbuf =
1808 ctx->engine[i].ringbuf;
1809
1810 seq_printf(m, "%s: ", ring->name);
1811 if (ctx_obj)
1812 describe_obj(m, ctx_obj);
1813 if (ringbuf)
1814 describe_ctx_ringbuf(m, ringbuf);
1815 seq_putc(m, '\n');
1816 }
1817 } else {
1818 describe_obj(m, ctx->legacy_hw_ctx.rcs_state);
1819 }
a33afea5 1820
a33afea5 1821 seq_putc(m, '\n');
a168c293
BW		 1822 }
1823
f3d28878 1824 mutex_unlock(&dev->struct_mutex);
e76d3630
BW		 1825
1826 return 0;
1827}
1828
064ca1d2
TD		 1829static void i915_dump_lrc_obj(struct seq_file *m,
1830 struct intel_engine_cs *ring,
1831 struct drm_i915_gem_object *ctx_obj)
1832{
1833 struct page *page;
1834 uint32_t *reg_state;
1835 int j;
1836 unsigned long ggtt_offset = 0;
1837
1838 if (ctx_obj == NULL) {
1839 seq_printf(m, "Context on %s with no gem object\n",
1840 ring->name);
1841 return;
1842 }
1843
1844 seq_printf(m, "CONTEXT: %s %u\n", ring->name,
1845 intel_execlists_ctx_id(ctx_obj));
1846
1847 if (!i915_gem_obj_ggtt_bound(ctx_obj))
1848 seq_puts(m, "\tNot bound in GGTT\n");
1849 else
1850 ggtt_offset = i915_gem_obj_ggtt_offset(ctx_obj);
1851
1852 if (i915_gem_object_get_pages(ctx_obj)) {
1853 seq_puts(m, "\tFailed to get pages for context object\n");
1854 return;
1855 }
1856
1857 page = i915_gem_object_get_page(ctx_obj, 1);
1858 if (!WARN_ON(page == NULL)) {
1859 reg_state = kmap_atomic(page);
1860
1861 for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
1862 seq_printf(m, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n",
1863 ggtt_offset + 4096 + (j * 4),
1864 reg_state[j], reg_state[j + 1],
1865 reg_state[j + 2], reg_state[j + 3]);
1866 }
1867 kunmap_atomic(reg_state);
1868 }
1869
1870 seq_putc(m, '\n');
1871}
1872
c0ab1ae9
BW		 1873static int i915_dump_lrc(struct seq_file *m, void *unused)
1874{
1875 struct drm_info_node *node = (struct drm_info_node *) m->private;
1876 struct drm_device *dev = node->minor->dev;
1877 struct drm_i915_private *dev_priv = dev->dev_private;
1878 struct intel_engine_cs *ring;
1879 struct intel_context *ctx;
1880 int ret, i;
1881
1882 if (!i915.enable_execlists) {
1883 seq_printf(m, "Logical Ring Contexts are disabled\n");
1884 return 0;
1885 }
1886
1887 ret = mutex_lock_interruptible(&dev->struct_mutex);
1888 if (ret)
1889 return ret;
1890
1891 list_for_each_entry(ctx, &dev_priv->context_list, link) {
1892 for_each_ring(ring, dev_priv, i) {
064ca1d2
TD		 1893 if (ring->default_context != ctx)
1894 i915_dump_lrc_obj(m, ring,
1895 ctx->engine[i].state);
c0ab1ae9
BW		 1896 }
1897 }
1898
1899 mutex_unlock(&dev->struct_mutex);
1900
1901 return 0;
1902}
1903
4ba70e44
OM		 1904static int i915_execlists(struct seq_file *m, void *data)
1905{
1906 struct drm_info_node *node = (struct drm_info_node *)m->private;
1907 struct drm_device *dev = node->minor->dev;
1908 struct drm_i915_private *dev_priv = dev->dev_private;
1909 struct intel_engine_cs *ring;
1910 u32 status_pointer;
1911 u8 read_pointer;
1912 u8 write_pointer;
1913 u32 status;
1914 u32 ctx_id;
1915 struct list_head *cursor;
1916 int ring_id, i;
1917 int ret;
1918
1919 if (!i915.enable_execlists) {
1920 seq_puts(m, "Logical Ring Contexts are disabled\n");
1921 return 0;
1922 }
1923
1924 ret = mutex_lock_interruptible(&dev->struct_mutex);
1925 if (ret)
1926 return ret;
1927
fc0412ec
MT		 1928 intel_runtime_pm_get(dev_priv);
1929
4ba70e44 1930 for_each_ring(ring, dev_priv, ring_id) {
6d3d8274 1931 struct drm_i915_gem_request *head_req = NULL;
4ba70e44
OM		 1932 int count = 0;
1933 unsigned long flags;
1934
1935 seq_printf(m, "%s\n", ring->name);
1936
1937 status = I915_READ(RING_EXECLIST_STATUS(ring));
1938 ctx_id = I915_READ(RING_EXECLIST_STATUS(ring) + 4);
1939 seq_printf(m, "\tExeclist status: 0x%08X, context: %u\n",
1940 status, ctx_id);
1941
1942 status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(ring));
1943 seq_printf(m, "\tStatus pointer: 0x%08X\n", status_pointer);
1944
1945 read_pointer = ring->next_context_status_buffer;
1946 write_pointer = status_pointer & 0x07;
1947 if (read_pointer > write_pointer)
1948 write_pointer += 6;
1949 seq_printf(m, "\tRead pointer: 0x%08X, write pointer 0x%08X\n",
1950 read_pointer, write_pointer);
1951
1952 for (i = 0; i < 6; i++) {
1953 status = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + 8*i);
1954 ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + 8*i + 4);
1955
1956 seq_printf(m, "\tStatus buffer %d: 0x%08X, context: %u\n",
1957 i, status, ctx_id);
1958 }
1959
1960 spin_lock_irqsave(&ring->execlist_lock, flags);
1961 list_for_each(cursor, &ring->execlist_queue)
1962 count++;
1963 head_req = list_first_entry_or_null(&ring->execlist_queue,
6d3d8274 1964 struct drm_i915_gem_request, execlist_link);
4ba70e44
OM		 1965 spin_unlock_irqrestore(&ring->execlist_lock, flags);
1966
1967 seq_printf(m, "\t%d requests in queue\n", count);
1968 if (head_req) {
1969 struct drm_i915_gem_object *ctx_obj;
1970
6d3d8274 1971 ctx_obj = head_req->ctx->engine[ring_id].state;
4ba70e44
OM		 1972 seq_printf(m, "\tHead request id: %u\n",
1973 intel_execlists_ctx_id(ctx_obj));
1974 seq_printf(m, "\tHead request tail: %u\n",
6d3d8274 1975 head_req->tail);
4ba70e44
OM		 1976 }
1977
1978 seq_putc(m, '\n');
1979 }
1980
fc0412ec 1981 intel_runtime_pm_put(dev_priv);
4ba70e44
OM		 1982 mutex_unlock(&dev->struct_mutex);
1983
1984 return 0;
1985}
1986
6d794d42
BW		 1987static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data)
1988{
9f25d007 1989 struct drm_info_node *node = m->private;
6d794d42
BW		 1990 struct drm_device *dev = node->minor->dev;
1991 struct drm_i915_private *dev_priv = dev->dev_private;
43709ba0 1992 unsigned forcewake_count = 0, fw_rendercount = 0, fw_mediacount = 0;
6d794d42 1993
907b28c5 1994 spin_lock_irq(&dev_priv->uncore.lock);
43709ba0
D		 1995 if (IS_VALLEYVIEW(dev)) {
1996 fw_rendercount = dev_priv->uncore.fw_rendercount;
1997 fw_mediacount = dev_priv->uncore.fw_mediacount;
1998 } else
1999 forcewake_count = dev_priv->uncore.forcewake_count;
907b28c5 2000 spin_unlock_irq(&dev_priv->uncore.lock);
6d794d42 2001
43709ba0
D		 2002 if (IS_VALLEYVIEW(dev)) {
2003 seq_printf(m, "fw_rendercount = %u\n", fw_rendercount);
2004 seq_printf(m, "fw_mediacount = %u\n", fw_mediacount);
2005 } else
2006 seq_printf(m, "forcewake count = %u\n", forcewake_count);
6d794d42
BW		 2007
2008 return 0;
2009}
2010
ea16a3cd
DV		 2011static const char *swizzle_string(unsigned swizzle)
2012{
aee56cff 2013 switch (swizzle) {
ea16a3cd
DV		 2014 case I915_BIT_6_SWIZZLE_NONE:
2015 return "none";
2016 case I915_BIT_6_SWIZZLE_9:
2017 return "bit9";
2018 case I915_BIT_6_SWIZZLE_9_10:
2019 return "bit9/bit10";
2020 case I915_BIT_6_SWIZZLE_9_11:
2021 return "bit9/bit11";
2022 case I915_BIT_6_SWIZZLE_9_10_11:
2023 return "bit9/bit10/bit11";
2024 case I915_BIT_6_SWIZZLE_9_17:
2025 return "bit9/bit17";
2026 case I915_BIT_6_SWIZZLE_9_10_17:
2027 return "bit9/bit10/bit17";
2028 case I915_BIT_6_SWIZZLE_UNKNOWN:
8a168ca7 2029 return "unknown";
ea16a3cd
DV		 2030 }
2031
2032 return "bug";
2033}
2034
2035static int i915_swizzle_info(struct seq_file *m, void *data)
2036{
9f25d007 2037 struct drm_info_node *node = m->private;
ea16a3cd
DV		 2038 struct drm_device *dev = node->minor->dev;
2039 struct drm_i915_private *dev_priv = dev->dev_private;
22bcfc6a
DV		 2040 int ret;
2041
2042 ret = mutex_lock_interruptible(&dev->struct_mutex);
2043 if (ret)
2044 return ret;
c8c8fb33 2045 intel_runtime_pm_get(dev_priv);
ea16a3cd 2046
ea16a3cd
DV		 2047 seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
2048 swizzle_string(dev_priv->mm.bit_6_swizzle_x));
2049 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
2050 swizzle_string(dev_priv->mm.bit_6_swizzle_y));
2051
2052 if (IS_GEN3(dev) || IS_GEN4(dev)) {
2053 seq_printf(m, "DDC = 0x%08x\n",
2054 I915_READ(DCC));
656bfa3a
DV		 2055 seq_printf(m, "DDC2 = 0x%08x\n",
2056 I915_READ(DCC2));
ea16a3cd
DV		 2057 seq_printf(m, "C0DRB3 = 0x%04x\n",
2058 I915_READ16(C0DRB3));
2059 seq_printf(m, "C1DRB3 = 0x%04x\n",
2060 I915_READ16(C1DRB3));
9d3203e1 2061 } else if (INTEL_INFO(dev)->gen >= 6) {
3fa7d235
DV		 2062 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
2063 I915_READ(MAD_DIMM_C0));
2064 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
2065 I915_READ(MAD_DIMM_C1));
2066 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
2067 I915_READ(MAD_DIMM_C2));
2068 seq_printf(m, "TILECTL = 0x%08x\n",
2069 I915_READ(TILECTL));
5907f5fb 2070 if (INTEL_INFO(dev)->gen >= 8)
9d3203e1
BW		 2071 seq_printf(m, "GAMTARBMODE = 0x%08x\n",
2072 I915_READ(GAMTARBMODE));
2073 else
2074 seq_printf(m, "ARB_MODE = 0x%08x\n",
2075 I915_READ(ARB_MODE));
3fa7d235
DV		 2076 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
2077 I915_READ(DISP_ARB_CTL));
ea16a3cd 2078 }
656bfa3a
DV		 2079
2080 if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2081 seq_puts(m, "L-shaped memory detected\n");
2082
c8c8fb33 2083 intel_runtime_pm_put(dev_priv);
ea16a3cd
DV		 2084 mutex_unlock(&dev->struct_mutex);
2085
2086 return 0;
2087}
2088
1c60fef5
BW		 2089static int per_file_ctx(int id, void *ptr, void *data)
2090{
273497e5 2091 struct intel_context *ctx = ptr;
1c60fef5 2092 struct seq_file *m = data;
ae6c4806
DV		 2093 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2094
2095 if (!ppgtt) {
2096 seq_printf(m, " no ppgtt for context %d\n",
2097 ctx->user_handle);
2098 return 0;
2099 }
1c60fef5 2100
f83d6518
OM		 2101 if (i915_gem_context_is_default(ctx))
2102 seq_puts(m, " default context:\n");
2103 else
821d66dd 2104 seq_printf(m, " context %d:\n", ctx->user_handle);
1c60fef5
BW		 2105 ppgtt->debug_dump(ppgtt, m);
2106
2107 return 0;
2108}
2109
77df6772 2110static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev)
3cf17fc5 2111{
3cf17fc5 2112 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2113 struct intel_engine_cs *ring;
77df6772
BW		 2114 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2115 int unused, i;
3cf17fc5 2116
77df6772
BW		 2117 if (!ppgtt)
2118 return;
2119
2120 seq_printf(m, "Page directories: %d\n", ppgtt->num_pd_pages);
5abbcca3 2121 seq_printf(m, "Page tables: %d\n", ppgtt->num_pd_entries);
77df6772
BW		 2122 for_each_ring(ring, dev_priv, unused) {
2123 seq_printf(m, "%s\n", ring->name);
2124 for (i = 0; i < 4; i++) {
2125 u32 offset = 0x270 + i * 8;
2126 u64 pdp = I915_READ(ring->mmio_base + offset + 4);
2127 pdp <<= 32;
2128 pdp |= I915_READ(ring->mmio_base + offset);
a2a5b15c 2129 seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
77df6772
BW		 2130 }
2131 }
2132}
2133
2134static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2135{
2136 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2137 struct intel_engine_cs *ring;
1c60fef5 2138 struct drm_file *file;
77df6772 2139 int i;
3cf17fc5 2140
3cf17fc5
DV		 2141 if (INTEL_INFO(dev)->gen == 6)
2142 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
2143
a2c7f6fd 2144 for_each_ring(ring, dev_priv, i) {
3cf17fc5
DV		 2145 seq_printf(m, "%s\n", ring->name);
2146 if (INTEL_INFO(dev)->gen == 7)
2147 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
2148 seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
2149 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
2150 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring)));
2151 }
2152 if (dev_priv->mm.aliasing_ppgtt) {
2153 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2154
267f0c90 2155 seq_puts(m, "aliasing PPGTT:\n");
3cf17fc5 2156 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset);
1c60fef5 2157
87d60b63 2158 ppgtt->debug_dump(ppgtt, m);
ae6c4806 2159 }
1c60fef5
BW		 2160
2161 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2162 struct drm_i915_file_private *file_priv = file->driver_priv;
1c60fef5 2163
1c60fef5
BW		 2164 seq_printf(m, "proc: %s\n",
2165 get_pid_task(file->pid, PIDTYPE_PID)->comm);
1c60fef5 2166 idr_for_each(&file_priv->context_idr, per_file_ctx, m);
3cf17fc5
DV		 2167 }
2168 seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
77df6772
BW		 2169}
2170
2171static int i915_ppgtt_info(struct seq_file *m, void *data)
2172{
9f25d007 2173 struct drm_info_node *node = m->private;
77df6772 2174 struct drm_device *dev = node->minor->dev;
c8c8fb33 2175 struct drm_i915_private *dev_priv = dev->dev_private;
77df6772
BW		 2176
2177 int ret = mutex_lock_interruptible(&dev->struct_mutex);
2178 if (ret)
2179 return ret;
c8c8fb33 2180 intel_runtime_pm_get(dev_priv);
77df6772
BW		 2181
2182 if (INTEL_INFO(dev)->gen >= 8)
2183 gen8_ppgtt_info(m, dev);
2184 else if (INTEL_INFO(dev)->gen >= 6)
2185 gen6_ppgtt_info(m, dev);
2186
c8c8fb33 2187 intel_runtime_pm_put(dev_priv);
3cf17fc5
DV		 2188 mutex_unlock(&dev->struct_mutex);
2189
2190 return 0;
2191}
2192
63573eb7
BW		 2193static int i915_llc(struct seq_file *m, void *data)
2194{
9f25d007 2195 struct drm_info_node *node = m->private;
63573eb7
BW		 2196 struct drm_device *dev = node->minor->dev;
2197 struct drm_i915_private *dev_priv = dev->dev_private;
2198
2199 /* Size calculation for LLC is a bit of a pain. Ignore for now. */
2200 seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
2201 seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size);
2202
2203 return 0;
2204}
2205
e91fd8c6
RV		 2206static int i915_edp_psr_status(struct seq_file *m, void *data)
2207{
2208 struct drm_info_node *node = m->private;
2209 struct drm_device *dev = node->minor->dev;
2210 struct drm_i915_private *dev_priv = dev->dev_private;
a031d709 2211 u32 psrperf = 0;
a6cbdb8e
RV		 2212 u32 stat[3];
2213 enum pipe pipe;
a031d709 2214 bool enabled = false;
e91fd8c6 2215
c8c8fb33
PZ		 2216 intel_runtime_pm_get(dev_priv);
2217
fa128fa6 2218 mutex_lock(&dev_priv->psr.lock);
a031d709
RV		 2219 seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
2220 seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
2807cf69 2221 seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
5755c78f 2222 seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
fa128fa6
DV		 2223 seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
2224 dev_priv->psr.busy_frontbuffer_bits);
2225 seq_printf(m, "Re-enable work scheduled: %s\n",
2226 yesno(work_busy(&dev_priv->psr.work.work)));
e91fd8c6 2227
a6cbdb8e
RV		 2228 if (HAS_PSR(dev)) {
2229 if (HAS_DDI(dev))
2230 enabled = I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
2231 else {
2232 for_each_pipe(dev_priv, pipe) {
2233 stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
2234 VLV_EDP_PSR_CURR_STATE_MASK;
2235 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2236 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2237 enabled = true;
2238 }
2239 }
2240 }
2241 seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));
2242
2243 if (!HAS_DDI(dev))
2244 for_each_pipe(dev_priv, pipe) {
2245 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2246 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2247 seq_printf(m, " pipe %c", pipe_name(pipe));
2248 }
2249 seq_puts(m, "\n");
e91fd8c6 2250
fb495814
RV		 2251 seq_printf(m, "Link standby: %s\n",
2252 yesno((bool)dev_priv->psr.link_standby));
2253
a6cbdb8e
RV		 2254 /* CHV PSR has no kind of performance counter */
2255 if (HAS_PSR(dev) && HAS_DDI(dev)) {
a031d709
RV		 2256 psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) &
2257 EDP_PSR_PERF_CNT_MASK;
a6cbdb8e
RV		 2258
2259 seq_printf(m, "Performance_Counter: %u\n", psrperf);
2260 }
fa128fa6 2261 mutex_unlock(&dev_priv->psr.lock);
e91fd8c6 2262
c8c8fb33 2263 intel_runtime_pm_put(dev_priv);
e91fd8c6
RV		 2264 return 0;
2265}
2266
d2e216d0
RV		 2267static int i915_sink_crc(struct seq_file *m, void *data)
2268{
2269 struct drm_info_node *node = m->private;
2270 struct drm_device *dev = node->minor->dev;
2271 struct intel_encoder *encoder;
2272 struct intel_connector *connector;
2273 struct intel_dp *intel_dp = NULL;
2274 int ret;
2275 u8 crc[6];
2276
2277 drm_modeset_lock_all(dev);
2278 list_for_each_entry(connector, &dev->mode_config.connector_list,
2279 base.head) {
2280
2281 if (connector->base.dpms != DRM_MODE_DPMS_ON)
2282 continue;
2283
b6ae3c7c
PZ		 2284 if (!connector->base.encoder)
2285 continue;
2286
d2e216d0
RV		 2287 encoder = to_intel_encoder(connector->base.encoder);
2288 if (encoder->type != INTEL_OUTPUT_EDP)
2289 continue;
2290
2291 intel_dp = enc_to_intel_dp(&encoder->base);
2292
2293 ret = intel_dp_sink_crc(intel_dp, crc);
2294 if (ret)
2295 goto out;
2296
2297 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2298 crc[0], crc[1], crc[2],
2299 crc[3], crc[4], crc[5]);
2300 goto out;
2301 }
2302 ret = -ENODEV;
2303out:
2304 drm_modeset_unlock_all(dev);
2305 return ret;
2306}
2307
ec013e7f
JB		 2308static int i915_energy_uJ(struct seq_file *m, void *data)
2309{
2310 struct drm_info_node *node = m->private;
2311 struct drm_device *dev = node->minor->dev;
2312 struct drm_i915_private *dev_priv = dev->dev_private;
2313 u64 power;
2314 u32 units;
2315
2316 if (INTEL_INFO(dev)->gen < 6)
2317 return -ENODEV;
2318
36623ef8
PZ		 2319 intel_runtime_pm_get(dev_priv);
2320
ec013e7f
JB		 2321 rdmsrl(MSR_RAPL_POWER_UNIT, power);
2322 power = (power & 0x1f00) >> 8;
2323 units = 1000000 / (1 << power); /* convert to uJ */
2324 power = I915_READ(MCH_SECP_NRG_STTS);
2325 power *= units;
2326
36623ef8
PZ		 2327 intel_runtime_pm_put(dev_priv);
2328
ec013e7f 2329 seq_printf(m, "%llu", (long long unsigned)power);
371db66a
PZ		 2330
2331 return 0;
2332}
2333
2334static int i915_pc8_status(struct seq_file *m, void *unused)
2335{
9f25d007 2336 struct drm_info_node *node = m->private;
371db66a
PZ		 2337 struct drm_device *dev = node->minor->dev;
2338 struct drm_i915_private *dev_priv = dev->dev_private;
2339
85b8d5c2 2340 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
371db66a
PZ		 2341 seq_puts(m, "not supported\n");
2342 return 0;
2343 }
2344
86c4ec0d 2345 seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy));
371db66a 2346 seq_printf(m, "IRQs disabled: %s\n",
9df7575f 2347 yesno(!intel_irqs_enabled(dev_priv)));
371db66a 2348
ec013e7f
JB		 2349 return 0;
2350}
2351
1da51581
ID		 2352static const char *power_domain_str(enum intel_display_power_domain domain)
2353{
2354 switch (domain) {
2355 case POWER_DOMAIN_PIPE_A:
2356 return "PIPE_A";
2357 case POWER_DOMAIN_PIPE_B:
2358 return "PIPE_B";
2359 case POWER_DOMAIN_PIPE_C:
2360 return "PIPE_C";
2361 case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
2362 return "PIPE_A_PANEL_FITTER";
2363 case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
2364 return "PIPE_B_PANEL_FITTER";
2365 case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
2366 return "PIPE_C_PANEL_FITTER";
2367 case POWER_DOMAIN_TRANSCODER_A:
2368 return "TRANSCODER_A";
2369 case POWER_DOMAIN_TRANSCODER_B:
2370 return "TRANSCODER_B";
2371 case POWER_DOMAIN_TRANSCODER_C:
2372 return "TRANSCODER_C";
2373 case POWER_DOMAIN_TRANSCODER_EDP:
2374 return "TRANSCODER_EDP";
319be8ae
ID		 2375 case POWER_DOMAIN_PORT_DDI_A_2_LANES:
2376 return "PORT_DDI_A_2_LANES";
2377 case POWER_DOMAIN_PORT_DDI_A_4_LANES:
2378 return "PORT_DDI_A_4_LANES";
2379 case POWER_DOMAIN_PORT_DDI_B_2_LANES:
2380 return "PORT_DDI_B_2_LANES";
2381 case POWER_DOMAIN_PORT_DDI_B_4_LANES:
2382 return "PORT_DDI_B_4_LANES";
2383 case POWER_DOMAIN_PORT_DDI_C_2_LANES:
2384 return "PORT_DDI_C_2_LANES";
2385 case POWER_DOMAIN_PORT_DDI_C_4_LANES:
2386 return "PORT_DDI_C_4_LANES";
2387 case POWER_DOMAIN_PORT_DDI_D_2_LANES:
2388 return "PORT_DDI_D_2_LANES";
2389 case POWER_DOMAIN_PORT_DDI_D_4_LANES:
2390 return "PORT_DDI_D_4_LANES";
2391 case POWER_DOMAIN_PORT_DSI:
2392 return "PORT_DSI";
2393 case POWER_DOMAIN_PORT_CRT:
2394 return "PORT_CRT";
2395 case POWER_DOMAIN_PORT_OTHER:
2396 return "PORT_OTHER";
1da51581
ID		 2397 case POWER_DOMAIN_VGA:
2398 return "VGA";
2399 case POWER_DOMAIN_AUDIO:
2400 return "AUDIO";
bd2bb1b9
PZ		 2401 case POWER_DOMAIN_PLLS:
2402 return "PLLS";
1da51581
ID		 2403 case POWER_DOMAIN_INIT:
2404 return "INIT";
2405 default:
5f77eeb0 2406 MISSING_CASE(domain);
1da51581
ID		 2407 return "?";
2408 }
2409}
2410
2411static int i915_power_domain_info(struct seq_file *m, void *unused)
2412{
9f25d007 2413 struct drm_info_node *node = m->private;
1da51581
ID		 2414 struct drm_device *dev = node->minor->dev;
2415 struct drm_i915_private *dev_priv = dev->dev_private;
2416 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2417 int i;
2418
2419 mutex_lock(&power_domains->lock);
2420
2421 seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2422 for (i = 0; i < power_domains->power_well_count; i++) {
2423 struct i915_power_well *power_well;
2424 enum intel_display_power_domain power_domain;
2425
2426 power_well = &power_domains->power_wells[i];
2427 seq_printf(m, "%-25s %d\n", power_well->name,
2428 power_well->count);
2429
2430 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
2431 power_domain++) {
2432 if (!(BIT(power_domain) & power_well->domains))
2433 continue;
2434
2435 seq_printf(m, " %-23s %d\n",
2436 power_domain_str(power_domain),
2437 power_domains->domain_use_count[power_domain]);
2438 }
2439 }
2440
2441 mutex_unlock(&power_domains->lock);
2442
2443 return 0;
2444}
2445
53f5e3ca
JB		 2446static void intel_seq_print_mode(struct seq_file *m, int tabs,
2447 struct drm_display_mode *mode)
2448{
2449 int i;
2450
2451 for (i = 0; i < tabs; i++)
2452 seq_putc(m, '\t');
2453
2454 seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2455 mode->base.id, mode->name,
2456 mode->vrefresh, mode->clock,
2457 mode->hdisplay, mode->hsync_start,
2458 mode->hsync_end, mode->htotal,
2459 mode->vdisplay, mode->vsync_start,
2460 mode->vsync_end, mode->vtotal,
2461 mode->type, mode->flags);
2462}
2463
2464static void intel_encoder_info(struct seq_file *m,
2465 struct intel_crtc *intel_crtc,
2466 struct intel_encoder *intel_encoder)
2467{
9f25d007 2468 struct drm_info_node *node = m->private;
53f5e3ca
JB		 2469 struct drm_device *dev = node->minor->dev;
2470 struct drm_crtc *crtc = &intel_crtc->base;
2471 struct intel_connector *intel_connector;
2472 struct drm_encoder *encoder;
2473
2474 encoder = &intel_encoder->base;
2475 seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
8e329a03 2476 encoder->base.id, encoder->name);
53f5e3ca
JB		 2477 for_each_connector_on_encoder(dev, encoder, intel_connector) {
2478 struct drm_connector *connector = &intel_connector->base;
2479 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2480 connector->base.id,
c23cc417 2481 connector->name,
53f5e3ca
JB		 2482 drm_get_connector_status_name(connector->status));
2483 if (connector->status == connector_status_connected) {
2484 struct drm_display_mode *mode = &crtc->mode;
2485 seq_printf(m, ", mode:\n");
2486 intel_seq_print_mode(m, 2, mode);
2487 } else {
2488 seq_putc(m, '\n');
2489 }
2490 }
2491}
2492
2493static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2494{
9f25d007 2495 struct drm_info_node *node = m->private;
53f5e3ca
JB		 2496 struct drm_device *dev = node->minor->dev;
2497 struct drm_crtc *crtc = &intel_crtc->base;
2498 struct intel_encoder *intel_encoder;
2499
5aa8a937
MR		 2500 if (crtc->primary->fb)
2501 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2502 crtc->primary->fb->base.id, crtc->x, crtc->y,
2503 crtc->primary->fb->width, crtc->primary->fb->height);
2504 else
2505 seq_puts(m, "\tprimary plane disabled\n");
53f5e3ca
JB		 2506 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2507 intel_encoder_info(m, intel_crtc, intel_encoder);
2508}
2509
2510static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2511{
2512 struct drm_display_mode *mode = panel->fixed_mode;
2513
2514 seq_printf(m, "\tfixed mode:\n");
2515 intel_seq_print_mode(m, 2, mode);
2516}
2517
2518static void intel_dp_info(struct seq_file *m,
2519 struct intel_connector *intel_connector)
2520{
2521 struct intel_encoder *intel_encoder = intel_connector->encoder;
2522 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2523
2524 seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2525 seq_printf(m, "\taudio support: %s\n", intel_dp->has_audio ? "yes" :
2526 "no");
2527 if (intel_encoder->type == INTEL_OUTPUT_EDP)
2528 intel_panel_info(m, &intel_connector->panel);
2529}
2530
2531static void intel_hdmi_info(struct seq_file *m,
2532 struct intel_connector *intel_connector)
2533{
2534 struct intel_encoder *intel_encoder = intel_connector->encoder;
2535 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2536
2537 seq_printf(m, "\taudio support: %s\n", intel_hdmi->has_audio ? "yes" :
2538 "no");
2539}
2540
2541static void intel_lvds_info(struct seq_file *m,
2542 struct intel_connector *intel_connector)
2543{
2544 intel_panel_info(m, &intel_connector->panel);
2545}
2546
2547static void intel_connector_info(struct seq_file *m,
2548 struct drm_connector *connector)
2549{
2550 struct intel_connector *intel_connector = to_intel_connector(connector);
2551 struct intel_encoder *intel_encoder = intel_connector->encoder;
f103fc7d 2552 struct drm_display_mode *mode;
53f5e3ca
JB		 2553
2554 seq_printf(m, "connector %d: type %s, status: %s\n",
c23cc417 2555 connector->base.id, connector->name,
53f5e3ca
JB		 2556 drm_get_connector_status_name(connector->status));
2557 if (connector->status == connector_status_connected) {
2558 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2559 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2560 connector->display_info.width_mm,
2561 connector->display_info.height_mm);
2562 seq_printf(m, "\tsubpixel order: %s\n",
2563 drm_get_subpixel_order_name(connector->display_info.subpixel_order));
2564 seq_printf(m, "\tCEA rev: %d\n",
2565 connector->display_info.cea_rev);
2566 }
36cd7444
DA		 2567 if (intel_encoder) {
2568 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2569 intel_encoder->type == INTEL_OUTPUT_EDP)
2570 intel_dp_info(m, intel_connector);
2571 else if (intel_encoder->type == INTEL_OUTPUT_HDMI)
2572 intel_hdmi_info(m, intel_connector);
2573 else if (intel_encoder->type == INTEL_OUTPUT_LVDS)
2574 intel_lvds_info(m, intel_connector);
2575 }
53f5e3ca 2576
f103fc7d
JB		 2577 seq_printf(m, "\tmodes:\n");
2578 list_for_each_entry(mode, &connector->modes, head)
2579 intel_seq_print_mode(m, 2, mode);
53f5e3ca
JB		 2580}
2581
065f2ec2
CW		 2582static bool cursor_active(struct drm_device *dev, int pipe)
2583{
2584 struct drm_i915_private *dev_priv = dev->dev_private;
2585 u32 state;
2586
2587 if (IS_845G(dev) || IS_I865G(dev))
2588 state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
065f2ec2 2589 else
5efb3e28 2590 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
065f2ec2
CW		 2591
2592 return state;
2593}
2594
2595static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y)
2596{
2597 struct drm_i915_private *dev_priv = dev->dev_private;
2598 u32 pos;
2599
5efb3e28 2600 pos = I915_READ(CURPOS(pipe));
065f2ec2
CW		 2601
2602 *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
2603 if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
2604 *x = -*x;
2605
2606 *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
2607 if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
2608 *y = -*y;
2609
2610 return cursor_active(dev, pipe);
2611}
2612
53f5e3ca
JB		 2613static int i915_display_info(struct seq_file *m, void *unused)
2614{
9f25d007 2615 struct drm_info_node *node = m->private;
53f5e3ca 2616 struct drm_device *dev = node->minor->dev;
b0e5ddf3 2617 struct drm_i915_private *dev_priv = dev->dev_private;
065f2ec2 2618 struct intel_crtc *crtc;
53f5e3ca
JB		 2619 struct drm_connector *connector;
2620
b0e5ddf3 2621 intel_runtime_pm_get(dev_priv);
53f5e3ca
JB		 2622 drm_modeset_lock_all(dev);
2623 seq_printf(m, "CRTC info\n");
2624 seq_printf(m, "---------\n");
d3fcc808 2625 for_each_intel_crtc(dev, crtc) {
065f2ec2
CW		 2626 bool active;
2627 int x, y;
53f5e3ca 2628
57127efa 2629 seq_printf(m, "CRTC %d: pipe: %c, active=%s (size=%dx%d)\n",
065f2ec2 2630 crtc->base.base.id, pipe_name(crtc->pipe),
6e3c9717
ACO		 2631 yesno(crtc->active), crtc->config->pipe_src_w,
2632 crtc->config->pipe_src_h);
a23dc658 2633 if (crtc->active) {
065f2ec2
CW		 2634 intel_crtc_info(m, crtc);
2635
a23dc658 2636 active = cursor_position(dev, crtc->pipe, &x, &y);
57127efa 2637 seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
4b0e333e 2638 yesno(crtc->cursor_base),
57127efa
CW		 2639 x, y, crtc->cursor_width, crtc->cursor_height,
2640 crtc->cursor_addr, yesno(active));
a23dc658 2641 }
cace841c
DV		 2642
2643 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
2644 yesno(!crtc->cpu_fifo_underrun_disabled),
2645 yesno(!crtc->pch_fifo_underrun_disabled));
53f5e3ca
JB		 2646 }
2647
2648 seq_printf(m, "\n");
2649 seq_printf(m, "Connector info\n");
2650 seq_printf(m, "--------------\n");
2651 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2652 intel_connector_info(m, connector);
2653 }
2654 drm_modeset_unlock_all(dev);
b0e5ddf3 2655 intel_runtime_pm_put(dev_priv);
53f5e3ca
JB		 2656
2657 return 0;
2658}
2659
e04934cf
BW		 2660static int i915_semaphore_status(struct seq_file *m, void *unused)
2661{
2662 struct drm_info_node *node = (struct drm_info_node *) m->private;
2663 struct drm_device *dev = node->minor->dev;
2664 struct drm_i915_private *dev_priv = dev->dev_private;
2665 struct intel_engine_cs *ring;
2666 int num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
2667 int i, j, ret;
2668
2669 if (!i915_semaphore_is_enabled(dev)) {
2670 seq_puts(m, "Semaphores are disabled\n");
2671 return 0;
2672 }
2673
2674 ret = mutex_lock_interruptible(&dev->struct_mutex);
2675 if (ret)
2676 return ret;
03872064 2677 intel_runtime_pm_get(dev_priv);
e04934cf
BW		 2678
2679 if (IS_BROADWELL(dev)) {
2680 struct page *page;
2681 uint64_t *seqno;
2682
2683 page = i915_gem_object_get_page(dev_priv->semaphore_obj, 0);
2684
2685 seqno = (uint64_t *)kmap_atomic(page);
2686 for_each_ring(ring, dev_priv, i) {
2687 uint64_t offset;
2688
2689 seq_printf(m, "%s\n", ring->name);
2690
2691 seq_puts(m, " Last signal:");
2692 for (j = 0; j < num_rings; j++) {
2693 offset = i * I915_NUM_RINGS + j;
2694 seq_printf(m, "0x%08llx (0x%02llx) ",
2695 seqno[offset], offset * 8);
2696 }
2697 seq_putc(m, '\n');
2698
2699 seq_puts(m, " Last wait: ");
2700 for (j = 0; j < num_rings; j++) {
2701 offset = i + (j * I915_NUM_RINGS);
2702 seq_printf(m, "0x%08llx (0x%02llx) ",
2703 seqno[offset], offset * 8);
2704 }
2705 seq_putc(m, '\n');
2706
2707 }
2708 kunmap_atomic(seqno);
2709 } else {
2710 seq_puts(m, " Last signal:");
2711 for_each_ring(ring, dev_priv, i)
2712 for (j = 0; j < num_rings; j++)
2713 seq_printf(m, "0x%08x\n",
2714 I915_READ(ring->semaphore.mbox.signal[j]));
2715 seq_putc(m, '\n');
2716 }
2717
2718 seq_puts(m, "\nSync seqno:\n");
2719 for_each_ring(ring, dev_priv, i) {
2720 for (j = 0; j < num_rings; j++) {
2721 seq_printf(m, " 0x%08x ", ring->semaphore.sync_seqno[j]);
2722 }
2723 seq_putc(m, '\n');
2724 }
2725 seq_putc(m, '\n');
2726
03872064 2727 intel_runtime_pm_put(dev_priv);
e04934cf
BW		 2728 mutex_unlock(&dev->struct_mutex);
2729 return 0;
2730}
2731
728e29d7
DV		 2732static int i915_shared_dplls_info(struct seq_file *m, void *unused)
2733{
2734 struct drm_info_node *node = (struct drm_info_node *) m->private;
2735 struct drm_device *dev = node->minor->dev;
2736 struct drm_i915_private *dev_priv = dev->dev_private;
2737 int i;
2738
2739 drm_modeset_lock_all(dev);
2740 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
2741 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
2742
2743 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
1e6f2ddc 2744 seq_printf(m, " crtc_mask: 0x%08x, active: %d, on: %s\n",
3e369b76 2745 pll->config.crtc_mask, pll->active, yesno(pll->on));
728e29d7 2746 seq_printf(m, " tracked hardware state:\n");
3e369b76
ACO		 2747 seq_printf(m, " dpll: 0x%08x\n", pll->config.hw_state.dpll);
2748 seq_printf(m, " dpll_md: 0x%08x\n",
2749 pll->config.hw_state.dpll_md);
2750 seq_printf(m, " fp0: 0x%08x\n", pll->config.hw_state.fp0);
2751 seq_printf(m, " fp1: 0x%08x\n", pll->config.hw_state.fp1);
2752 seq_printf(m, " wrpll: 0x%08x\n", pll->config.hw_state.wrpll);
728e29d7
DV		 2753 }
2754 drm_modeset_unlock_all(dev);
2755
2756 return 0;
2757}
2758
1ed1ef9d 2759static int i915_wa_registers(struct seq_file *m, void *unused)
888b5995
AS		 2760{
2761 int i;
2762 int ret;
2763 struct drm_info_node *node = (struct drm_info_node *) m->private;
2764 struct drm_device *dev = node->minor->dev;
2765 struct drm_i915_private *dev_priv = dev->dev_private;
2766
888b5995
AS		 2767 ret = mutex_lock_interruptible(&dev->struct_mutex);
2768 if (ret)
2769 return ret;
2770
2771 intel_runtime_pm_get(dev_priv);
2772
7225342a
MK		 2773 seq_printf(m, "Workarounds applied: %d\n", dev_priv->workarounds.count);
2774 for (i = 0; i < dev_priv->workarounds.count; ++i) {
2fa60f6d
MK		 2775 u32 addr, mask, value, read;
2776 bool ok;
888b5995 2777
7225342a
MK		 2778 addr = dev_priv->workarounds.reg[i].addr;
2779 mask = dev_priv->workarounds.reg[i].mask;
2fa60f6d
MK		 2780 value = dev_priv->workarounds.reg[i].value;
2781 read = I915_READ(addr);
2782 ok = (value & mask) == (read & mask);
2783 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
2784 addr, value, mask, read, ok ? "OK" : "FAIL");
888b5995
AS		 2785 }
2786
2787 intel_runtime_pm_put(dev_priv);
2788 mutex_unlock(&dev->struct_mutex);
2789
2790 return 0;
2791}
2792
c5511e44
DL		 2793static int i915_ddb_info(struct seq_file *m, void *unused)
2794{
2795 struct drm_info_node *node = m->private;
2796 struct drm_device *dev = node->minor->dev;
2797 struct drm_i915_private *dev_priv = dev->dev_private;
2798 struct skl_ddb_allocation *ddb;
2799 struct skl_ddb_entry *entry;
2800 enum pipe pipe;
2801 int plane;
2802
2fcffe19
DL		 2803 if (INTEL_INFO(dev)->gen < 9)
2804 return 0;
2805
c5511e44
DL		 2806 drm_modeset_lock_all(dev);
2807
2808 ddb = &dev_priv->wm.skl_hw.ddb;
2809
2810 seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
2811
2812 for_each_pipe(dev_priv, pipe) {
2813 seq_printf(m, "Pipe %c\n", pipe_name(pipe));
2814
2815 for_each_plane(pipe, plane) {
2816 entry = &ddb->plane[pipe][plane];
2817 seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane + 1,
2818 entry->start, entry->end,
2819 skl_ddb_entry_size(entry));
2820 }
2821
2822 entry = &ddb->cursor[pipe];
2823 seq_printf(m, " %-13s%8u%8u%8u\n", "Cursor", entry->start,
2824 entry->end, skl_ddb_entry_size(entry));
2825 }
2826
2827 drm_modeset_unlock_all(dev);
2828
2829 return 0;
2830}
2831
07144428
DL		 2832struct pipe_crc_info {
2833 const char *name;
2834 struct drm_device *dev;
2835 enum pipe pipe;
2836};
2837
11bed958
DA		 2838static int i915_dp_mst_info(struct seq_file *m, void *unused)
2839{
2840 struct drm_info_node *node = (struct drm_info_node *) m->private;
2841 struct drm_device *dev = node->minor->dev;
2842 struct drm_encoder *encoder;
2843 struct intel_encoder *intel_encoder;
2844 struct intel_digital_port *intel_dig_port;
2845 drm_modeset_lock_all(dev);
2846 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2847 intel_encoder = to_intel_encoder(encoder);
2848 if (intel_encoder->type != INTEL_OUTPUT_DISPLAYPORT)
2849 continue;
2850 intel_dig_port = enc_to_dig_port(encoder);
2851 if (!intel_dig_port->dp.can_mst)
2852 continue;
2853
2854 drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr);
2855 }
2856 drm_modeset_unlock_all(dev);
2857 return 0;
2858}
2859
07144428
DL		 2860static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
2861{
be5c7a90
DL		 2862 struct pipe_crc_info *info = inode->i_private;
2863 struct drm_i915_private *dev_priv = info->dev->dev_private;
2864 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2865
7eb1c496
DV		 2866 if (info->pipe >= INTEL_INFO(info->dev)->num_pipes)
2867 return -ENODEV;
2868
d538bbdf
DL		 2869 spin_lock_irq(&pipe_crc->lock);
2870
2871 if (pipe_crc->opened) {
2872 spin_unlock_irq(&pipe_crc->lock);
be5c7a90
DL		 2873 return -EBUSY; /* already open */
2874 }
2875
d538bbdf 2876 pipe_crc->opened = true;
07144428
DL		 2877 filep->private_data = inode->i_private;
2878
d538bbdf
DL		 2879 spin_unlock_irq(&pipe_crc->lock);
2880
07144428
DL		 2881 return 0;
2882}
2883
2884static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
2885{
be5c7a90
DL		 2886 struct pipe_crc_info *info = inode->i_private;
2887 struct drm_i915_private *dev_priv = info->dev->dev_private;
2888 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2889
d538bbdf
DL		 2890 spin_lock_irq(&pipe_crc->lock);
2891 pipe_crc->opened = false;
2892 spin_unlock_irq(&pipe_crc->lock);
be5c7a90 2893
07144428
DL		 2894 return 0;
2895}
2896
2897/* (6 fields, 8 chars each, space separated (5) + '\n') */
2898#define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
2899/* account for \'0' */
2900#define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1)
2901
2902static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
8bf1e9f1 2903{
d538bbdf
DL		 2904 assert_spin_locked(&pipe_crc->lock);
2905 return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
2906 INTEL_PIPE_CRC_ENTRIES_NR);
07144428
DL		 2907}
2908
2909static ssize_t
2910i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
2911 loff_t *pos)
2912{
2913 struct pipe_crc_info *info = filep->private_data;
2914 struct drm_device *dev = info->dev;
2915 struct drm_i915_private *dev_priv = dev->dev_private;
2916 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2917 char buf[PIPE_CRC_BUFFER_LEN];
9ad6d99f 2918 int n_entries;
07144428
DL		 2919 ssize_t bytes_read;
2920
2921 /*
2922 * Don't allow user space to provide buffers not big enough to hold
2923 * a line of data.
2924 */
2925 if (count < PIPE_CRC_LINE_LEN)
2926 return -EINVAL;
2927
2928 if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
8bf1e9f1 2929 return 0;
07144428
DL		 2930
2931 /* nothing to read */
d538bbdf 2932 spin_lock_irq(&pipe_crc->lock);
07144428 2933 while (pipe_crc_data_count(pipe_crc) == 0) {
d538bbdf
DL		 2934 int ret;
2935
2936 if (filep->f_flags & O_NONBLOCK) {
2937 spin_unlock_irq(&pipe_crc->lock);
07144428 2938 return -EAGAIN;
d538bbdf 2939 }
07144428 2940
d538bbdf
DL		 2941 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
2942 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
2943 if (ret) {
2944 spin_unlock_irq(&pipe_crc->lock);
2945 return ret;
2946 }
8bf1e9f1
SH		 2947 }
2948
07144428 2949 /* We now have one or more entries to read */
9ad6d99f 2950 n_entries = count / PIPE_CRC_LINE_LEN;
d538bbdf 2951
07144428 2952 bytes_read = 0;
9ad6d99f
VS		 2953 while (n_entries > 0) {
2954 struct intel_pipe_crc_entry *entry =
2955 &pipe_crc->entries[pipe_crc->tail];
07144428 2956 int ret;
8bf1e9f1 2957
9ad6d99f
VS		 2958 if (CIRC_CNT(pipe_crc->head, pipe_crc->tail,
2959 INTEL_PIPE_CRC_ENTRIES_NR) < 1)
2960 break;
2961
2962 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
2963 pipe_crc->tail = (pipe_crc->tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
2964
07144428
DL		 2965 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
2966 "%8u %8x %8x %8x %8x %8x\n",
2967 entry->frame, entry->crc[0],
2968 entry->crc[1], entry->crc[2],
2969 entry->crc[3], entry->crc[4]);
2970
9ad6d99f
VS		 2971 spin_unlock_irq(&pipe_crc->lock);
2972
2973 ret = copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN);
07144428
DL		 2974 if (ret == PIPE_CRC_LINE_LEN)
2975 return -EFAULT;
b2c88f5b 2976
9ad6d99f
VS		 2977 user_buf += PIPE_CRC_LINE_LEN;
2978 n_entries--;
2979
2980 spin_lock_irq(&pipe_crc->lock);
2981 }
8bf1e9f1 2982
d538bbdf
DL		 2983 spin_unlock_irq(&pipe_crc->lock);
2984
07144428
DL		 2985 return bytes_read;
2986}
2987
2988static const struct file_operations i915_pipe_crc_fops = {
2989 .owner = THIS_MODULE,
2990 .open = i915_pipe_crc_open,
2991 .read = i915_pipe_crc_read,
2992 .release = i915_pipe_crc_release,
2993};
2994
2995static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
2996 {
2997 .name = "i915_pipe_A_crc",
2998 .pipe = PIPE_A,
2999 },
3000 {
3001 .name = "i915_pipe_B_crc",
3002 .pipe = PIPE_B,
3003 },
3004 {
3005 .name = "i915_pipe_C_crc",
3006 .pipe = PIPE_C,
3007 },
3008};
3009
3010static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
3011 enum pipe pipe)
3012{
3013 struct drm_device *dev = minor->dev;
3014 struct dentry *ent;
3015 struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
3016
3017 info->dev = dev;
3018 ent = debugfs_create_file(info->name, S_IRUGO, root, info,
3019 &i915_pipe_crc_fops);
f3c5fe97
WY		 3020 if (!ent)
3021 return -ENOMEM;
07144428
DL		 3022
3023 return drm_add_fake_info_node(minor, ent, info);
8bf1e9f1
SH		 3024}
3025
e8dfcf78 3026static const char * const pipe_crc_sources[] = {
926321d5
DV		 3027 "none",
3028 "plane1",
3029 "plane2",
3030 "pf",
5b3a856b 3031 "pipe",
3d099a05
DV		 3032 "TV",
3033 "DP-B",
3034 "DP-C",
3035 "DP-D",
46a19188 3036 "auto",
926321d5
DV		 3037};
3038
3039static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
3040{
3041 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
3042 return pipe_crc_sources[source];
3043}
3044
bd9db02f 3045static int display_crc_ctl_show(struct seq_file *m, void *data)
926321d5
DV		 3046{
3047 struct drm_device *dev = m->private;
3048 struct drm_i915_private *dev_priv = dev->dev_private;
3049 int i;
3050
3051 for (i = 0; i < I915_MAX_PIPES; i++)
3052 seq_printf(m, "%c %s\n", pipe_name(i),
3053 pipe_crc_source_name(dev_priv->pipe_crc[i].source));
3054
3055 return 0;
3056}
3057
bd9db02f 3058static int display_crc_ctl_open(struct inode *inode, struct file *file)
926321d5
DV		 3059{
3060 struct drm_device *dev = inode->i_private;
3061
bd9db02f 3062 return single_open(file, display_crc_ctl_show, dev);
926321d5
DV		 3063}
3064
46a19188 3065static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
52f843f6
DV		 3066 uint32_t *val)
3067{
46a19188
DV		 3068 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3069 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3070
3071 switch (*source) {
52f843f6
DV		 3072 case INTEL_PIPE_CRC_SOURCE_PIPE:
3073 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
3074 break;
3075 case INTEL_PIPE_CRC_SOURCE_NONE:
3076 *val = 0;
3077 break;
3078 default:
3079 return -EINVAL;
3080 }
3081
3082 return 0;
3083}
3084
46a19188
DV		 3085static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe,
3086 enum intel_pipe_crc_source *source)
3087{
3088 struct intel_encoder *encoder;
3089 struct intel_crtc *crtc;
26756809 3090 struct intel_digital_port *dig_port;
46a19188
DV		 3091 int ret = 0;
3092
3093 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3094
6e9f798d 3095 drm_modeset_lock_all(dev);
b2784e15 3096 for_each_intel_encoder(dev, encoder) {
46a19188
DV		 3097 if (!encoder->base.crtc)
3098 continue;
3099
3100 crtc = to_intel_crtc(encoder->base.crtc);
3101
3102 if (crtc->pipe != pipe)
3103 continue;
3104
3105 switch (encoder->type) {
3106 case INTEL_OUTPUT_TVOUT:
3107 *source = INTEL_PIPE_CRC_SOURCE_TV;
3108 break;
3109 case INTEL_OUTPUT_DISPLAYPORT:
3110 case INTEL_OUTPUT_EDP:
26756809
DV		 3111 dig_port = enc_to_dig_port(&encoder->base);
3112 switch (dig_port->port) {
3113 case PORT_B:
3114 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
3115 break;
3116 case PORT_C:
3117 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
3118 break;
3119 case PORT_D:
3120 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
3121 break;
3122 default:
3123 WARN(1, "nonexisting DP port %c\n",
3124 port_name(dig_port->port));
3125 break;
3126 }
46a19188 3127 break;
6847d71b
PZ		 3128 default:
3129 break;
46a19188
DV		 3130 }
3131 }
6e9f798d 3132 drm_modeset_unlock_all(dev);
46a19188
DV		 3133
3134 return ret;
3135}
3136
3137static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
3138 enum pipe pipe,
3139 enum intel_pipe_crc_source *source,
7ac0129b
DV		 3140 uint32_t *val)
3141{
8d2f24ca
DV		 3142 struct drm_i915_private *dev_priv = dev->dev_private;
3143 bool need_stable_symbols = false;
3144
46a19188
DV		 3145 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3146 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3147 if (ret)
3148 return ret;
3149 }
3150
3151 switch (*source) {
7ac0129b
DV		 3152 case INTEL_PIPE_CRC_SOURCE_PIPE:
3153 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
3154 break;
3155 case INTEL_PIPE_CRC_SOURCE_DP_B:
3156 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
8d2f24ca 3157 need_stable_symbols = true;
7ac0129b
DV		 3158 break;
3159 case INTEL_PIPE_CRC_SOURCE_DP_C:
3160 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
8d2f24ca 3161 need_stable_symbols = true;
7ac0129b 3162 break;
2be57922
VS		 3163 case INTEL_PIPE_CRC_SOURCE_DP_D:
3164 if (!IS_CHERRYVIEW(dev))
3165 return -EINVAL;
3166 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV;
3167 need_stable_symbols = true;
3168 break;
7ac0129b
DV		 3169 case INTEL_PIPE_CRC_SOURCE_NONE:
3170 *val = 0;
3171 break;
3172 default:
3173 return -EINVAL;
3174 }
3175
8d2f24ca
DV		 3176 /*
3177 * When the pipe CRC tap point is after the transcoders we need
3178 * to tweak symbol-level features to produce a deterministic series of
3179 * symbols for a given frame. We need to reset those features only once
3180 * a frame (instead of every nth symbol):
3181 * - DC-balance: used to ensure a better clock recovery from the data
3182 * link (SDVO)
3183 * - DisplayPort scrambling: used for EMI reduction
3184 */
3185 if (need_stable_symbols) {
3186 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3187
8d2f24ca 3188 tmp |= DC_BALANCE_RESET_VLV;
eb736679
VS		 3189 switch (pipe) {
3190 case PIPE_A:
8d2f24ca 3191 tmp |= PIPE_A_SCRAMBLE_RESET;
eb736679
VS		 3192 break;
3193 case PIPE_B:
8d2f24ca 3194 tmp |= PIPE_B_SCRAMBLE_RESET;
eb736679
VS		 3195 break;
3196 case PIPE_C:
3197 tmp |= PIPE_C_SCRAMBLE_RESET;
3198 break;
3199 default:
3200 return -EINVAL;
3201 }
8d2f24ca
DV		 3202 I915_WRITE(PORT_DFT2_G4X, tmp);
3203 }
3204
7ac0129b
DV		 3205 return 0;
3206}
3207
4b79ebf7 3208static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
46a19188
DV		 3209 enum pipe pipe,
3210 enum intel_pipe_crc_source *source,
4b79ebf7
DV		 3211 uint32_t *val)
3212{
84093603
DV		 3213 struct drm_i915_private *dev_priv = dev->dev_private;
3214 bool need_stable_symbols = false;
3215
46a19188
DV		 3216 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3217 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3218 if (ret)
3219 return ret;
3220 }
3221
3222 switch (*source) {
4b79ebf7
DV		 3223 case INTEL_PIPE_CRC_SOURCE_PIPE:
3224 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
3225 break;
3226 case INTEL_PIPE_CRC_SOURCE_TV:
3227 if (!SUPPORTS_TV(dev))
3228 return -EINVAL;
3229 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
3230 break;
3231 case INTEL_PIPE_CRC_SOURCE_DP_B:
3232 if (!IS_G4X(dev))
3233 return -EINVAL;
3234 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
84093603 3235 need_stable_symbols = true;
4b79ebf7
DV		 3236 break;
3237 case INTEL_PIPE_CRC_SOURCE_DP_C:
3238 if (!IS_G4X(dev))
3239 return -EINVAL;
3240 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
84093603 3241 need_stable_symbols = true;
4b79ebf7
DV		 3242 break;
3243 case INTEL_PIPE_CRC_SOURCE_DP_D:
3244 if (!IS_G4X(dev))
3245 return -EINVAL;
3246 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
84093603 3247 need_stable_symbols = true;
4b79ebf7
DV		 3248 break;
3249 case INTEL_PIPE_CRC_SOURCE_NONE:
3250 *val = 0;
3251 break;
3252 default:
3253 return -EINVAL;
3254 }
3255
84093603
DV		 3256 /*
3257 * When the pipe CRC tap point is after the transcoders we need
3258 * to tweak symbol-level features to produce a deterministic series of
3259 * symbols for a given frame. We need to reset those features only once
3260 * a frame (instead of every nth symbol):
3261 * - DC-balance: used to ensure a better clock recovery from the data
3262 * link (SDVO)
3263 * - DisplayPort scrambling: used for EMI reduction
3264 */
3265 if (need_stable_symbols) {
3266 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3267
3268 WARN_ON(!IS_G4X(dev));
3269
3270 I915_WRITE(PORT_DFT_I9XX,
3271 I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
3272
3273 if (pipe == PIPE_A)
3274 tmp |= PIPE_A_SCRAMBLE_RESET;
3275 else
3276 tmp |= PIPE_B_SCRAMBLE_RESET;
3277
3278 I915_WRITE(PORT_DFT2_G4X, tmp);
3279 }
3280
4b79ebf7
DV		 3281 return 0;
3282}
3283
8d2f24ca
DV		 3284static void vlv_undo_pipe_scramble_reset(struct drm_device *dev,
3285 enum pipe pipe)
3286{
3287 struct drm_i915_private *dev_priv = dev->dev_private;
3288 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3289
eb736679
VS		 3290 switch (pipe) {
3291 case PIPE_A:
8d2f24ca 3292 tmp &= ~PIPE_A_SCRAMBLE_RESET;
eb736679
VS		 3293 break;
3294 case PIPE_B:
8d2f24ca 3295 tmp &= ~PIPE_B_SCRAMBLE_RESET;
eb736679
VS		 3296 break;
3297 case PIPE_C:
3298 tmp &= ~PIPE_C_SCRAMBLE_RESET;
3299 break;
3300 default:
3301 return;
3302 }
8d2f24ca
DV		 3303 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
3304 tmp &= ~DC_BALANCE_RESET_VLV;
3305 I915_WRITE(PORT_DFT2_G4X, tmp);
3306
3307}
3308
84093603
DV		 3309static void g4x_undo_pipe_scramble_reset(struct drm_device *dev,
3310 enum pipe pipe)
3311{
3312 struct drm_i915_private *dev_priv = dev->dev_private;
3313 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3314
3315 if (pipe == PIPE_A)
3316 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3317 else
3318 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3319 I915_WRITE(PORT_DFT2_G4X, tmp);
3320
3321 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
3322 I915_WRITE(PORT_DFT_I9XX,
3323 I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
3324 }
3325}
3326
46a19188 3327static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
5b3a856b
DV		 3328 uint32_t *val)
3329{
46a19188
DV		 3330 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3331 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3332
3333 switch (*source) {
5b3a856b
DV		 3334 case INTEL_PIPE_CRC_SOURCE_PLANE1:
3335 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
3336 break;
3337 case INTEL_PIPE_CRC_SOURCE_PLANE2:
3338 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
3339 break;
5b3a856b
DV		 3340 case INTEL_PIPE_CRC_SOURCE_PIPE:
3341 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
3342 break;
3d099a05 3343 case INTEL_PIPE_CRC_SOURCE_NONE:
5b3a856b
DV		 3344 *val = 0;
3345 break;
3d099a05
DV		 3346 default:
3347 return -EINVAL;
5b3a856b
DV		 3348 }
3349
3350 return 0;
3351}
3352
fabf6e51
DV		 3353static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device *dev)
3354{
3355 struct drm_i915_private *dev_priv = dev->dev_private;
3356 struct intel_crtc *crtc =
3357 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
3358
3359 drm_modeset_lock_all(dev);
3360 /*
3361 * If we use the eDP transcoder we need to make sure that we don't
3362 * bypass the pfit, since otherwise the pipe CRC source won't work. Only
3363 * relevant on hsw with pipe A when using the always-on power well
3364 * routing.
3365 */
6e3c9717
ACO		 3366 if (crtc->config->cpu_transcoder == TRANSCODER_EDP &&
3367 !crtc->config->pch_pfit.enabled) {
3368 crtc->config->pch_pfit.force_thru = true;
fabf6e51
DV		 3369
3370 intel_display_power_get(dev_priv,
3371 POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A));
3372
3373 dev_priv->display.crtc_disable(&crtc->base);
3374 dev_priv->display.crtc_enable(&crtc->base);
3375 }
3376 drm_modeset_unlock_all(dev);
3377}
3378
3379static void hsw_undo_trans_edp_pipe_A_crc_wa(struct drm_device *dev)
3380{
3381 struct drm_i915_private *dev_priv = dev->dev_private;
3382 struct intel_crtc *crtc =
3383 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
3384
3385 drm_modeset_lock_all(dev);
3386 /*
3387 * If we use the eDP transcoder we need to make sure that we don't
3388 * bypass the pfit, since otherwise the pipe CRC source won't work. Only
3389 * relevant on hsw with pipe A when using the always-on power well
3390 * routing.
3391 */
6e3c9717
ACO		 3392 if (crtc->config->pch_pfit.force_thru) {
3393 crtc->config->pch_pfit.force_thru = false;
fabf6e51
DV		 3394
3395 dev_priv->display.crtc_disable(&crtc->base);
3396 dev_priv->display.crtc_enable(&crtc->base);
3397
3398 intel_display_power_put(dev_priv,
3399 POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A));
3400 }
3401 drm_modeset_unlock_all(dev);
3402}
3403
3404static int ivb_pipe_crc_ctl_reg(struct drm_device *dev,
3405 enum pipe pipe,
3406 enum intel_pipe_crc_source *source,
5b3a856b
DV		 3407 uint32_t *val)
3408{
46a19188
DV		 3409 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3410 *source = INTEL_PIPE_CRC_SOURCE_PF;
3411
3412 switch (*source) {
5b3a856b
DV		 3413 case INTEL_PIPE_CRC_SOURCE_PLANE1:
3414 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
3415 break;
3416 case INTEL_PIPE_CRC_SOURCE_PLANE2:
3417 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
3418 break;
3419 case INTEL_PIPE_CRC_SOURCE_PF:
fabf6e51
DV		 3420 if (IS_HASWELL(dev) && pipe == PIPE_A)
3421 hsw_trans_edp_pipe_A_crc_wa(dev);
3422
5b3a856b
DV		 3423 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
3424 break;
3d099a05 3425 case INTEL_PIPE_CRC_SOURCE_NONE:
5b3a856b
DV		 3426 *val = 0;
3427 break;
3d099a05
DV		 3428 default:
3429 return -EINVAL;
5b3a856b
DV		 3430 }
3431
3432 return 0;
3433}
3434
926321d5
DV		 3435static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
3436 enum intel_pipe_crc_source source)
3437{
3438 struct drm_i915_private *dev_priv = dev->dev_private;
cc3da175 3439 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
8c740dce
PZ		 3440 struct intel_crtc *crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev,
3441 pipe));
432f3342 3442 u32 val = 0; /* shut up gcc */
5b3a856b 3443 int ret;
926321d5 3444
cc3da175
DL		 3445 if (pipe_crc->source == source)
3446 return 0;
3447
ae676fcd
DL		 3448 /* forbid changing the source without going back to 'none' */
3449 if (pipe_crc->source && source)
3450 return -EINVAL;
3451
9d8b0588
DV		 3452 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PIPE(pipe))) {
3453 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
3454 return -EIO;
3455 }
3456
52f843f6 3457 if (IS_GEN2(dev))
46a19188 3458 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
52f843f6 3459 else if (INTEL_INFO(dev)->gen < 5)
46a19188 3460 ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
7ac0129b 3461 else if (IS_VALLEYVIEW(dev))
fabf6e51 3462 ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val);
4b79ebf7 3463 else if (IS_GEN5(dev) || IS_GEN6(dev))
46a19188 3464 ret = ilk_pipe_crc_ctl_reg(&source, &val);
5b3a856b 3465 else
fabf6e51 3466 ret = ivb_pipe_crc_ctl_reg(dev, pipe, &source, &val);
5b3a856b
DV		 3467
3468 if (ret != 0)
3469 return ret;
3470
4b584369
DL		 3471 /* none -> real source transition */
3472 if (source) {
4252fbc3
VS		 3473 struct intel_pipe_crc_entry *entries;
3474
7cd6ccff
DL		 3475 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
3476 pipe_name(pipe), pipe_crc_source_name(source));
3477
3cf54b34
VS		 3478 entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR,
3479 sizeof(pipe_crc->entries[0]),
4252fbc3
VS		 3480 GFP_KERNEL);
3481 if (!entries)
e5f75aca
DL		 3482 return -ENOMEM;
3483
8c740dce
PZ		 3484 /*
3485 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
3486 * enabled and disabled dynamically based on package C states,
3487 * user space can't make reliable use of the CRCs, so let's just
3488 * completely disable it.
3489 */
3490 hsw_disable_ips(crtc);
3491
d538bbdf 3492 spin_lock_irq(&pipe_crc->lock);
64387b61 3493 kfree(pipe_crc->entries);
4252fbc3 3494 pipe_crc->entries = entries;
d538bbdf
DL		 3495 pipe_crc->head = 0;
3496 pipe_crc->tail = 0;
3497 spin_unlock_irq(&pipe_crc->lock);
4b584369
DL		 3498 }
3499
cc3da175 3500 pipe_crc->source = source;
926321d5 3501
926321d5
DV		 3502 I915_WRITE(PIPE_CRC_CTL(pipe), val);
3503 POSTING_READ(PIPE_CRC_CTL(pipe));
3504
e5f75aca
DL		 3505 /* real source -> none transition */
3506 if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
d538bbdf 3507 struct intel_pipe_crc_entry *entries;
a33d7105
DV		 3508 struct intel_crtc *crtc =
3509 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
d538bbdf 3510
7cd6ccff
DL		 3511 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
3512 pipe_name(pipe));
3513
a33d7105
DV		 3514 drm_modeset_lock(&crtc->base.mutex, NULL);
3515 if (crtc->active)
3516 intel_wait_for_vblank(dev, pipe);
3517 drm_modeset_unlock(&crtc->base.mutex);
bcf17ab2 3518
d538bbdf
DL		 3519 spin_lock_irq(&pipe_crc->lock);
3520 entries = pipe_crc->entries;
e5f75aca 3521 pipe_crc->entries = NULL;
9ad6d99f
VS		 3522 pipe_crc->head = 0;
3523 pipe_crc->tail = 0;
d538bbdf
DL		 3524 spin_unlock_irq(&pipe_crc->lock);
3525
3526 kfree(entries);
84093603
DV		 3527
3528 if (IS_G4X(dev))
3529 g4x_undo_pipe_scramble_reset(dev, pipe);
8d2f24ca
DV		 3530 else if (IS_VALLEYVIEW(dev))
3531 vlv_undo_pipe_scramble_reset(dev, pipe);
fabf6e51
DV		 3532 else if (IS_HASWELL(dev) && pipe == PIPE_A)
3533 hsw_undo_trans_edp_pipe_A_crc_wa(dev);
8c740dce
PZ		 3534
3535 hsw_enable_ips(crtc);
e5f75aca
DL		 3536 }
3537
926321d5
DV		 3538 return 0;
3539}
3540
3541/*
3542 * Parse pipe CRC command strings:
b94dec87
DL		 3543 * command: wsp* object wsp+ name wsp+ source wsp*
3544 * object: 'pipe'
3545 * name: (A | B | C)
926321d5
DV		 3546 * source: (none | plane1 | plane2 | pf)
3547 * wsp: (#0x20 | #0x9 | #0xA)+
3548 *
3549 * eg.:
b94dec87
DL		 3550 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A
3551 * "pipe A none" -> Stop CRC
926321d5 3552 */
bd9db02f 3553static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
926321d5
DV		 3554{
3555 int n_words = 0;
3556
3557 while (*buf) {
3558 char *end;
3559
3560 /* skip leading white space */
3561 buf = skip_spaces(buf);
3562 if (!*buf)
3563 break; /* end of buffer */
3564
3565 /* find end of word */
3566 for (end = buf; *end && !isspace(*end); end++)
3567 ;
3568
3569 if (n_words == max_words) {
3570 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
3571 max_words);
3572 return -EINVAL; /* ran out of words[] before bytes */
3573 }
3574
3575 if (*end)
3576 *end++ = '\0';
3577 words[n_words++] = buf;
3578 buf = end;
3579 }
3580
3581 return n_words;
3582}
3583
b94dec87
DL		 3584enum intel_pipe_crc_object {
3585 PIPE_CRC_OBJECT_PIPE,
3586};
3587
e8dfcf78 3588static const char * const pipe_crc_objects[] = {
b94dec87
DL		 3589 "pipe",
3590};
3591
3592static int
bd9db02f 3593display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
b94dec87
DL		 3594{
3595 int i;
3596
3597 for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
3598 if (!strcmp(buf, pipe_crc_objects[i])) {
bd9db02f 3599 *o = i;
b94dec87
DL		 3600 return 0;
3601 }
3602
3603 return -EINVAL;
3604}
3605
bd9db02f 3606static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
926321d5
DV		 3607{
3608 const char name = buf[0];
3609
3610 if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
3611 return -EINVAL;
3612
3613 *pipe = name - 'A';
3614
3615 return 0;
3616}
3617
3618static int
bd9db02f 3619display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
926321d5
DV		 3620{
3621 int i;
3622
3623 for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
3624 if (!strcmp(buf, pipe_crc_sources[i])) {
bd9db02f 3625 *s = i;
926321d5
DV		 3626 return 0;
3627 }
3628
3629 return -EINVAL;
3630}
3631
bd9db02f 3632static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len)
926321d5 3633{
b94dec87 3634#define N_WORDS 3
926321d5 3635 int n_words;
b94dec87 3636 char *words[N_WORDS];
926321d5 3637 enum pipe pipe;
b94dec87 3638 enum intel_pipe_crc_object object;
926321d5
DV		 3639 enum intel_pipe_crc_source source;
3640
bd9db02f 3641 n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
b94dec87
DL		 3642 if (n_words != N_WORDS) {
3643 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
3644 N_WORDS);
3645 return -EINVAL;
3646 }
3647
bd9db02f 3648 if (display_crc_ctl_parse_object(words[0], &object) < 0) {
b94dec87 3649 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
926321d5
DV		 3650 return -EINVAL;
3651 }
3652
bd9db02f 3653 if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
b94dec87 3654 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
926321d5
DV		 3655 return -EINVAL;
3656 }
3657
bd9db02f 3658 if (display_crc_ctl_parse_source(words[2], &source) < 0) {
b94dec87 3659 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
926321d5
DV		 3660 return -EINVAL;
3661 }
3662
3663 return pipe_crc_set_source(dev, pipe, source);
3664}
3665
bd9db02f
DL		 3666static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
3667 size_t len, loff_t *offp)
926321d5
DV		 3668{
3669 struct seq_file *m = file->private_data;
3670 struct drm_device *dev = m->private;
3671 char *tmpbuf;
3672 int ret;
3673
3674 if (len == 0)
3675 return 0;
3676
3677 if (len > PAGE_SIZE - 1) {
3678 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
3679 PAGE_SIZE);
3680 return -E2BIG;
3681 }
3682
3683 tmpbuf = kmalloc(len + 1, GFP_KERNEL);
3684 if (!tmpbuf)
3685 return -ENOMEM;
3686
3687 if (copy_from_user(tmpbuf, ubuf, len)) {
3688 ret = -EFAULT;
3689 goto out;
3690 }
3691 tmpbuf[len] = '\0';
3692
bd9db02f 3693 ret = display_crc_ctl_parse(dev, tmpbuf, len);
926321d5
DV		 3694
3695out:
3696 kfree(tmpbuf);
3697 if (ret < 0)
3698 return ret;
3699
3700 *offp += len;
3701 return len;
3702}
3703
bd9db02f 3704static const struct file_operations i915_display_crc_ctl_fops = {
926321d5 3705 .owner = THIS_MODULE,
bd9db02f 3706 .open = display_crc_ctl_open,
926321d5
DV		 3707 .read = seq_read,
3708 .llseek = seq_lseek,
3709 .release = single_release,
bd9db02f 3710 .write = display_crc_ctl_write
926321d5
DV		 3711};
3712
97e94b22 3713static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
369a1342
VS		 3714{
3715 struct drm_device *dev = m->private;
546c81fd 3716 int num_levels = ilk_wm_max_level(dev) + 1;
369a1342
VS		 3717 int level;
3718
3719 drm_modeset_lock_all(dev);
3720
3721 for (level = 0; level < num_levels; level++) {
3722 unsigned int latency = wm[level];
3723
97e94b22
DL		 3724 /*
3725 * - WM1+ latency values in 0.5us units
3726 * - latencies are in us on gen9
3727 */
3728 if (INTEL_INFO(dev)->gen >= 9)
3729 latency *= 10;
3730 else if (level > 0)
369a1342
VS		 3731 latency *= 5;
3732
3733 seq_printf(m, "WM%d %u (%u.%u usec)\n",
97e94b22 3734 level, wm[level], latency / 10, latency % 10);
369a1342
VS		 3735 }
3736
3737 drm_modeset_unlock_all(dev);
3738}
3739
3740static int pri_wm_latency_show(struct seq_file *m, void *data)
3741{
3742 struct drm_device *dev = m->private;
97e94b22
DL		 3743 struct drm_i915_private *dev_priv = dev->dev_private;
3744 const uint16_t *latencies;
3745
3746 if (INTEL_INFO(dev)->gen >= 9)
3747 latencies = dev_priv->wm.skl_latency;
3748 else
3749 latencies = to_i915(dev)->wm.pri_latency;
369a1342 3750
97e94b22 3751 wm_latency_show(m, latencies);
369a1342
VS		 3752
3753 return 0;
3754}
3755
3756static int spr_wm_latency_show(struct seq_file *m, void *data)
3757{
3758 struct drm_device *dev = m->private;
97e94b22
DL		 3759 struct drm_i915_private *dev_priv = dev->dev_private;
3760 const uint16_t *latencies;
3761
3762 if (INTEL_INFO(dev)->gen >= 9)
3763 latencies = dev_priv->wm.skl_latency;
3764 else
3765 latencies = to_i915(dev)->wm.spr_latency;
369a1342 3766
97e94b22 3767 wm_latency_show(m, latencies);
369a1342
VS		 3768
3769 return 0;
3770}
3771
3772static int cur_wm_latency_show(struct seq_file *m, void *data)
3773{
3774 struct drm_device *dev = m->private;
97e94b22
DL		 3775 struct drm_i915_private *dev_priv = dev->dev_private;
3776 const uint16_t *latencies;
3777
3778 if (INTEL_INFO(dev)->gen >= 9)
3779 latencies = dev_priv->wm.skl_latency;
3780 else
3781 latencies = to_i915(dev)->wm.cur_latency;
369a1342 3782
97e94b22 3783 wm_latency_show(m, latencies);
369a1342
VS		 3784
3785 return 0;
3786}
3787
3788static int pri_wm_latency_open(struct inode *inode, struct file *file)
3789{
3790 struct drm_device *dev = inode->i_private;
3791
9ad0257c 3792 if (HAS_GMCH_DISPLAY(dev))
369a1342
VS		 3793 return -ENODEV;
3794
3795 return single_open(file, pri_wm_latency_show, dev);
3796}
3797
3798static int spr_wm_latency_open(struct inode *inode, struct file *file)
3799{
3800 struct drm_device *dev = inode->i_private;
3801
9ad0257c 3802 if (HAS_GMCH_DISPLAY(dev))
369a1342
VS		 3803 return -ENODEV;
3804
3805 return single_open(file, spr_wm_latency_show, dev);
3806}
3807
3808static int cur_wm_latency_open(struct inode *inode, struct file *file)
3809{
3810 struct drm_device *dev = inode->i_private;
3811
9ad0257c 3812 if (HAS_GMCH_DISPLAY(dev))
369a1342
VS		 3813 return -ENODEV;
3814
3815 return single_open(file, cur_wm_latency_show, dev);
3816}
3817
3818static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
97e94b22 3819 size_t len, loff_t *offp, uint16_t wm[8])
369a1342
VS		 3820{
3821 struct seq_file *m = file->private_data;
3822 struct drm_device *dev = m->private;
97e94b22 3823 uint16_t new[8] = { 0 };
546c81fd 3824 int num_levels = ilk_wm_max_level(dev) + 1;
369a1342
VS		 3825 int level;
3826 int ret;
3827 char tmp[32];
3828
3829 if (len >= sizeof(tmp))
3830 return -EINVAL;
3831
3832 if (copy_from_user(tmp, ubuf, len))
3833 return -EFAULT;
3834
3835 tmp[len] = '\0';
3836
97e94b22
DL		 3837 ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
3838 &new[0], &new[1], &new[2], &new[3],
3839 &new[4], &new[5], &new[6], &new[7]);
369a1342
VS		 3840 if (ret != num_levels)
3841 return -EINVAL;
3842
3843 drm_modeset_lock_all(dev);
3844
3845 for (level = 0; level < num_levels; level++)
3846 wm[level] = new[level];
3847
3848 drm_modeset_unlock_all(dev);
3849
3850 return len;
3851}
3852
3853
3854static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
3855 size_t len, loff_t *offp)
3856{
3857 struct seq_file *m = file->private_data;
3858 struct drm_device *dev = m->private;
97e94b22
DL		 3859 struct drm_i915_private *dev_priv = dev->dev_private;
3860 uint16_t *latencies;
369a1342 3861
97e94b22
DL		 3862 if (INTEL_INFO(dev)->gen >= 9)
3863 latencies = dev_priv->wm.skl_latency;
3864 else
3865 latencies = to_i915(dev)->wm.pri_latency;
3866
3867 return wm_latency_write(file, ubuf, len, offp, latencies);
369a1342
VS		 3868}
3869
3870static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
3871 size_t len, loff_t *offp)
3872{
3873 struct seq_file *m = file->private_data;
3874 struct drm_device *dev = m->private;
97e94b22
DL		 3875 struct drm_i915_private *dev_priv = dev->dev_private;
3876 uint16_t *latencies;
369a1342 3877
97e94b22
DL		 3878 if (INTEL_INFO(dev)->gen >= 9)
3879 latencies = dev_priv->wm.skl_latency;
3880 else
3881 latencies = to_i915(dev)->wm.spr_latency;
3882
3883 return wm_latency_write(file, ubuf, len, offp, latencies);
369a1342
VS		 3884}
3885
3886static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
3887 size_t len, loff_t *offp)
3888{
3889 struct seq_file *m = file->private_data;
3890 struct drm_device *dev = m->private;
97e94b22
DL		 3891 struct drm_i915_private *dev_priv = dev->dev_private;
3892 uint16_t *latencies;
3893
3894 if (INTEL_INFO(dev)->gen >= 9)
3895 latencies = dev_priv->wm.skl_latency;
3896 else
3897 latencies = to_i915(dev)->wm.cur_latency;
369a1342 3898
97e94b22 3899 return wm_latency_write(file, ubuf, len, offp, latencies);
369a1342
VS		 3900}
3901
3902static const struct file_operations i915_pri_wm_latency_fops = {
3903 .owner = THIS_MODULE,
3904 .open = pri_wm_latency_open,
3905 .read = seq_read,
3906 .llseek = seq_lseek,
3907 .release = single_release,
3908 .write = pri_wm_latency_write
3909};
3910
3911static const struct file_operations i915_spr_wm_latency_fops = {
3912 .owner = THIS_MODULE,
3913 .open = spr_wm_latency_open,
3914 .read = seq_read,
3915 .llseek = seq_lseek,
3916 .release = single_release,
3917 .write = spr_wm_latency_write
3918};
3919
3920static const struct file_operations i915_cur_wm_latency_fops = {
3921 .owner = THIS_MODULE,
3922 .open = cur_wm_latency_open,
3923 .read = seq_read,
3924 .llseek = seq_lseek,
3925 .release = single_release,
3926 .write = cur_wm_latency_write
3927};
3928
647416f9
KC		 3929static int
3930i915_wedged_get(void *data, u64 *val)
f3cd474b 3931{
647416f9 3932 struct drm_device *dev = data;
e277a1f8 3933 struct drm_i915_private *dev_priv = dev->dev_private;
f3cd474b 3934
647416f9 3935 *val = atomic_read(&dev_priv->gpu_error.reset_counter);
f3cd474b 3936
647416f9 3937 return 0;
f3cd474b
CW		 3938}
3939
647416f9
KC		 3940static int
3941i915_wedged_set(void *data, u64 val)
f3cd474b 3942{
647416f9 3943 struct drm_device *dev = data;
d46c0517
ID		 3944 struct drm_i915_private *dev_priv = dev->dev_private;
3945
3946 intel_runtime_pm_get(dev_priv);
f3cd474b 3947
58174462
MK		 3948 i915_handle_error(dev, val,
3949 "Manually setting wedged to %llu", val);
d46c0517
ID		 3950
3951 intel_runtime_pm_put(dev_priv);
3952
647416f9 3953 return 0;
f3cd474b
CW		 3954}
3955
647416f9
KC		 3956DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
3957 i915_wedged_get, i915_wedged_set,
3a3b4f98 3958 "%llu\n");
f3cd474b 3959
647416f9
KC		 3960static int
3961i915_ring_stop_get(void *data, u64 *val)
e5eb3d63 3962{
647416f9 3963 struct drm_device *dev = data;
e277a1f8 3964 struct drm_i915_private *dev_priv = dev->dev_private;
e5eb3d63 3965
647416f9 3966 *val = dev_priv->gpu_error.stop_rings;
e5eb3d63 3967
647416f9 3968 return 0;
e5eb3d63
DV		 3969}
3970
647416f9
KC		 3971static int
3972i915_ring_stop_set(void *data, u64 val)
e5eb3d63 3973{
647416f9 3974 struct drm_device *dev = data;
e5eb3d63 3975 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 3976 int ret;
e5eb3d63 3977
647416f9 3978 DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val);
e5eb3d63 3979
22bcfc6a
DV		 3980 ret = mutex_lock_interruptible(&dev->struct_mutex);
3981 if (ret)
3982 return ret;
3983
99584db3 3984 dev_priv->gpu_error.stop_rings = val;
e5eb3d63
DV		 3985 mutex_unlock(&dev->struct_mutex);
3986
647416f9 3987 return 0;
e5eb3d63
DV		 3988}
3989
647416f9
KC		 3990DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops,
3991 i915_ring_stop_get, i915_ring_stop_set,
3992 "0x%08llx\n");
d5442303 3993
094f9a54
CW		 3994static int
3995i915_ring_missed_irq_get(void *data, u64 *val)
3996{
3997 struct drm_device *dev = data;
3998 struct drm_i915_private *dev_priv = dev->dev_private;
3999
4000 *val = dev_priv->gpu_error.missed_irq_rings;
4001 return 0;
4002}
4003
4004static int
4005i915_ring_missed_irq_set(void *data, u64 val)
4006{
4007 struct drm_device *dev = data;
4008 struct drm_i915_private *dev_priv = dev->dev_private;
4009 int ret;
4010
4011 /* Lock against concurrent debugfs callers */
4012 ret = mutex_lock_interruptible(&dev->struct_mutex);
4013 if (ret)
4014 return ret;
4015 dev_priv->gpu_error.missed_irq_rings = val;
4016 mutex_unlock(&dev->struct_mutex);
4017
4018 return 0;
4019}
4020
4021DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
4022 i915_ring_missed_irq_get, i915_ring_missed_irq_set,
4023 "0x%08llx\n");
4024
4025static int
4026i915_ring_test_irq_get(void *data, u64 *val)
4027{
4028 struct drm_device *dev = data;
4029 struct drm_i915_private *dev_priv = dev->dev_private;
4030
4031 *val = dev_priv->gpu_error.test_irq_rings;
4032
4033 return 0;
4034}
4035
4036static int
4037i915_ring_test_irq_set(void *data, u64 val)
4038{
4039 struct drm_device *dev = data;
4040 struct drm_i915_private *dev_priv = dev->dev_private;
4041 int ret;
4042
4043 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
4044
4045 /* Lock against concurrent debugfs callers */
4046 ret = mutex_lock_interruptible(&dev->struct_mutex);
4047 if (ret)
4048 return ret;
4049
4050 dev_priv->gpu_error.test_irq_rings = val;
4051 mutex_unlock(&dev->struct_mutex);
4052
4053 return 0;
4054}
4055
4056DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
4057 i915_ring_test_irq_get, i915_ring_test_irq_set,
4058 "0x%08llx\n");
4059
dd624afd
CW		 4060#define DROP_UNBOUND 0x1
4061#define DROP_BOUND 0x2
4062#define DROP_RETIRE 0x4
4063#define DROP_ACTIVE 0x8
4064#define DROP_ALL (DROP_UNBOUND | \
4065 DROP_BOUND | \
4066 DROP_RETIRE | \
4067 DROP_ACTIVE)
647416f9
KC		 4068static int
4069i915_drop_caches_get(void *data, u64 *val)
dd624afd 4070{
647416f9 4071 *val = DROP_ALL;
dd624afd 4072
647416f9 4073 return 0;
dd624afd
CW		 4074}
4075
647416f9
KC		 4076static int
4077i915_drop_caches_set(void *data, u64 val)
dd624afd 4078{
647416f9 4079 struct drm_device *dev = data;
dd624afd 4080 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 4081 int ret;
dd624afd 4082
2f9fe5ff 4083 DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
dd624afd
CW		 4084
4085 /* No need to check and wait for gpu resets, only libdrm auto-restarts
4086 * on ioctls on -EAGAIN. */
4087 ret = mutex_lock_interruptible(&dev->struct_mutex);
4088 if (ret)
4089 return ret;
4090
4091 if (val & DROP_ACTIVE) {
4092 ret = i915_gpu_idle(dev);
4093 if (ret)
4094 goto unlock;
4095 }
4096
4097 if (val & (DROP_RETIRE | DROP_ACTIVE))
4098 i915_gem_retire_requests(dev);
4099
21ab4e74
CW		 4100 if (val & DROP_BOUND)
4101 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND);
4ad72b7f 4102
21ab4e74
CW		 4103 if (val & DROP_UNBOUND)
4104 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND);
dd624afd
CW		 4105
4106unlock:
4107 mutex_unlock(&dev->struct_mutex);
4108
647416f9 4109 return ret;
dd624afd
CW		 4110}
4111
647416f9
KC		 4112DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
4113 i915_drop_caches_get, i915_drop_caches_set,
4114 "0x%08llx\n");
dd624afd 4115
647416f9
KC		 4116static int
4117i915_max_freq_get(void *data, u64 *val)
358733e9 4118{
647416f9 4119 struct drm_device *dev = data;
e277a1f8 4120 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 4121 int ret;
004777cb 4122
daa3afb2 4123 if (INTEL_INFO(dev)->gen < 6)
004777cb
DV		 4124 return -ENODEV;
4125
5c9669ce
TR		 4126 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4127
4fc688ce 4128 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 4129 if (ret)
4130 return ret;
358733e9 4131
0a073b84 4132 if (IS_VALLEYVIEW(dev))
b39fb297 4133 *val = vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
0a073b84 4134 else
b39fb297 4135 *val = dev_priv->rps.max_freq_softlimit * GT_FREQUENCY_MULTIPLIER;
4fc688ce 4136 mutex_unlock(&dev_priv->rps.hw_lock);
358733e9 4137
647416f9 4138 return 0;
358733e9
JB		 4139}
4140
647416f9
KC		 4141static int
4142i915_max_freq_set(void *data, u64 val)
358733e9 4143{
647416f9 4144 struct drm_device *dev = data;
358733e9 4145 struct drm_i915_private *dev_priv = dev->dev_private;
dd0a1aa1 4146 u32 rp_state_cap, hw_max, hw_min;
647416f9 4147 int ret;
004777cb 4148
daa3afb2 4149 if (INTEL_INFO(dev)->gen < 6)
004777cb 4150 return -ENODEV;
358733e9 4151
5c9669ce
TR		 4152 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4153
647416f9 4154 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
358733e9 4155
4fc688ce 4156 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 4157 if (ret)
4158 return ret;
4159
358733e9
JB		 4160 /*
4161 * Turbo will still be enabled, but won't go above the set value.
4162 */
0a073b84 4163 if (IS_VALLEYVIEW(dev)) {
2ec3815f 4164 val = vlv_freq_opcode(dev_priv, val);
dd0a1aa1 4165
03af2045
VS		 4166 hw_max = dev_priv->rps.max_freq;
4167 hw_min = dev_priv->rps.min_freq;
0a073b84
JB		 4168 } else {
4169 do_div(val, GT_FREQUENCY_MULTIPLIER);
dd0a1aa1
JM		 4170
4171 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
b39fb297 4172 hw_max = dev_priv->rps.max_freq;
dd0a1aa1
JM		 4173 hw_min = (rp_state_cap >> 16) & 0xff;
4174 }
4175
b39fb297 4176 if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
dd0a1aa1
JM		 4177 mutex_unlock(&dev_priv->rps.hw_lock);
4178 return -EINVAL;
0a073b84
JB		 4179 }
4180
b39fb297 4181 dev_priv->rps.max_freq_softlimit = val;
dd0a1aa1
JM		 4182
4183 if (IS_VALLEYVIEW(dev))
4184 valleyview_set_rps(dev, val);
4185 else
4186 gen6_set_rps(dev, val);
4187
4fc688ce 4188 mutex_unlock(&dev_priv->rps.hw_lock);
358733e9 4189
647416f9 4190 return 0;
358733e9
JB		 4191}
4192
647416f9
KC		 4193DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
4194 i915_max_freq_get, i915_max_freq_set,
3a3b4f98 4195 "%llu\n");
358733e9 4196
647416f9
KC		 4197static int
4198i915_min_freq_get(void *data, u64 *val)
1523c310 4199{
647416f9 4200 struct drm_device *dev = data;
e277a1f8 4201 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 4202 int ret;
004777cb 4203
daa3afb2 4204 if (INTEL_INFO(dev)->gen < 6)
004777cb
DV		 4205 return -ENODEV;
4206
5c9669ce
TR		 4207 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4208
4fc688ce 4209 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 4210 if (ret)
4211 return ret;
1523c310 4212
0a073b84 4213 if (IS_VALLEYVIEW(dev))
b39fb297 4214 *val = vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
0a073b84 4215 else
b39fb297 4216 *val = dev_priv->rps.min_freq_softlimit * GT_FREQUENCY_MULTIPLIER;
4fc688ce 4217 mutex_unlock(&dev_priv->rps.hw_lock);
1523c310 4218
647416f9 4219 return 0;
1523c310
JB		 4220}
4221
647416f9
KC		 4222static int
4223i915_min_freq_set(void *data, u64 val)
1523c310 4224{
647416f9 4225 struct drm_device *dev = data;
1523c310 4226 struct drm_i915_private *dev_priv = dev->dev_private;
dd0a1aa1 4227 u32 rp_state_cap, hw_max, hw_min;
647416f9 4228 int ret;
004777cb 4229
daa3afb2 4230 if (INTEL_INFO(dev)->gen < 6)
004777cb 4231 return -ENODEV;
1523c310 4232
5c9669ce
TR		 4233 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4234
647416f9 4235 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
1523c310 4236
4fc688ce 4237 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 4238 if (ret)
4239 return ret;
4240
1523c310
JB		 4241 /*
4242 * Turbo will still be enabled, but won't go below the set value.
4243 */
0a073b84 4244 if (IS_VALLEYVIEW(dev)) {
2ec3815f 4245 val = vlv_freq_opcode(dev_priv, val);
dd0a1aa1 4246
03af2045
VS		 4247 hw_max = dev_priv->rps.max_freq;
4248 hw_min = dev_priv->rps.min_freq;
0a073b84
JB		 4249 } else {
4250 do_div(val, GT_FREQUENCY_MULTIPLIER);
dd0a1aa1
JM		 4251
4252 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
b39fb297 4253 hw_max = dev_priv->rps.max_freq;
dd0a1aa1
JM		 4254 hw_min = (rp_state_cap >> 16) & 0xff;
4255 }
4256
b39fb297 4257 if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
dd0a1aa1
JM		 4258 mutex_unlock(&dev_priv->rps.hw_lock);
4259 return -EINVAL;
0a073b84 4260 }
dd0a1aa1 4261
b39fb297 4262 dev_priv->rps.min_freq_softlimit = val;
dd0a1aa1
JM		 4263
4264 if (IS_VALLEYVIEW(dev))
4265 valleyview_set_rps(dev, val);
4266 else
4267 gen6_set_rps(dev, val);
4268
4fc688ce 4269 mutex_unlock(&dev_priv->rps.hw_lock);
1523c310 4270
647416f9 4271 return 0;
1523c310
JB		 4272}
4273
647416f9
KC		 4274DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
4275 i915_min_freq_get, i915_min_freq_set,
3a3b4f98 4276 "%llu\n");
1523c310 4277
647416f9
KC		 4278static int
4279i915_cache_sharing_get(void *data, u64 *val)
07b7ddd9 4280{
647416f9 4281 struct drm_device *dev = data;
e277a1f8 4282 struct drm_i915_private *dev_priv = dev->dev_private;
07b7ddd9 4283 u32 snpcr;
647416f9 4284 int ret;
07b7ddd9 4285
004777cb
DV		 4286 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
4287 return -ENODEV;
4288
22bcfc6a
DV		 4289 ret = mutex_lock_interruptible(&dev->struct_mutex);
4290 if (ret)
4291 return ret;
c8c8fb33 4292 intel_runtime_pm_get(dev_priv);
22bcfc6a 4293
07b7ddd9 4294 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
c8c8fb33
PZ		 4295
4296 intel_runtime_pm_put(dev_priv);
07b7ddd9
JB		 4297 mutex_unlock(&dev_priv->dev->struct_mutex);
4298
647416f9 4299 *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
07b7ddd9 4300
647416f9 4301 return 0;
07b7ddd9
JB		 4302}
4303
647416f9
KC		 4304static int
4305i915_cache_sharing_set(void *data, u64 val)
07b7ddd9 4306{
647416f9 4307 struct drm_device *dev = data;
07b7ddd9 4308 struct drm_i915_private *dev_priv = dev->dev_private;
07b7ddd9 4309 u32 snpcr;
07b7ddd9 4310
004777cb
DV		 4311 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
4312 return -ENODEV;
4313
647416f9 4314 if (val > 3)
07b7ddd9
JB		 4315 return -EINVAL;
4316
c8c8fb33 4317 intel_runtime_pm_get(dev_priv);
647416f9 4318 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
07b7ddd9
JB		 4319
4320 /* Update the cache sharing policy here as well */
4321 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4322 snpcr &= ~GEN6_MBC_SNPCR_MASK;
4323 snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
4324 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
4325
c8c8fb33 4326 intel_runtime_pm_put(dev_priv);
647416f9 4327 return 0;
07b7ddd9
JB		 4328}
4329
647416f9
KC		 4330DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
4331 i915_cache_sharing_get, i915_cache_sharing_set,
4332 "%llu\n");
07b7ddd9 4333
6d794d42
BW		 4334static int i915_forcewake_open(struct inode *inode, struct file *file)
4335{
4336 struct drm_device *dev = inode->i_private;
4337 struct drm_i915_private *dev_priv = dev->dev_private;
6d794d42 4338
075edca4 4339 if (INTEL_INFO(dev)->gen < 6)
6d794d42
BW		 4340 return 0;
4341
c8d9a590 4342 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
6d794d42
BW		 4343
4344 return 0;
4345}
4346
c43b5634 4347static int i915_forcewake_release(struct inode *inode, struct file *file)
6d794d42
BW		 4348{
4349 struct drm_device *dev = inode->i_private;
4350 struct drm_i915_private *dev_priv = dev->dev_private;
4351
075edca4 4352 if (INTEL_INFO(dev)->gen < 6)
6d794d42
BW		 4353 return 0;
4354
c8d9a590 4355 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
6d794d42
BW		 4356
4357 return 0;
4358}
4359
4360static const struct file_operations i915_forcewake_fops = {
4361 .owner = THIS_MODULE,
4362 .open = i915_forcewake_open,
4363 .release = i915_forcewake_release,
4364};
4365
4366static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
4367{
4368 struct drm_device *dev = minor->dev;
4369 struct dentry *ent;
4370
4371 ent = debugfs_create_file("i915_forcewake_user",
8eb57294 4372 S_IRUSR,
6d794d42
BW		 4373 root, dev,
4374 &i915_forcewake_fops);
f3c5fe97
WY		 4375 if (!ent)
4376 return -ENOMEM;
6d794d42 4377
8eb57294 4378 return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
6d794d42
BW		 4379}
4380
6a9c308d
DV		 4381static int i915_debugfs_create(struct dentry *root,
4382 struct drm_minor *minor,
4383 const char *name,
4384 const struct file_operations *fops)
07b7ddd9
JB		 4385{
4386 struct drm_device *dev = minor->dev;
4387 struct dentry *ent;
4388
6a9c308d 4389 ent = debugfs_create_file(name,
07b7ddd9
JB		 4390 S_IRUGO | S_IWUSR,
4391 root, dev,
6a9c308d 4392 fops);
f3c5fe97
WY		 4393 if (!ent)
4394 return -ENOMEM;
07b7ddd9 4395
6a9c308d 4396 return drm_add_fake_info_node(minor, ent, fops);
07b7ddd9
JB		 4397}
4398
06c5bf8c 4399static const struct drm_info_list i915_debugfs_list[] = {
311bd68e 4400 {"i915_capabilities", i915_capabilities, 0},
73aa808f 4401 {"i915_gem_objects", i915_gem_object_info, 0},
08c18323 4402 {"i915_gem_gtt", i915_gem_gtt_info, 0},
1b50247a 4403 {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
433e12f7 4404 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
433e12f7 4405 {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
6d2b8885 4406 {"i915_gem_stolen", i915_gem_stolen_list_info },
4e5359cd 4407 {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
2017263e
BG		 4408 {"i915_gem_request", i915_gem_request_info, 0},
4409 {"i915_gem_seqno", i915_gem_seqno_info, 0},
a6172a80 4410 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
2017263e 4411 {"i915_gem_interrupt", i915_interrupt_info, 0},
1ec14ad3
CW		 4412 {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
4413 {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
4414 {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
9010ebfd 4415 {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
493018dc 4416 {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0},
adb4bd12 4417 {"i915_frequency_info", i915_frequency_info, 0},
f97108d1 4418 {"i915_drpc_info", i915_drpc_info, 0},
7648fa99 4419 {"i915_emon_status", i915_emon_status, 0},
23b2f8bb 4420 {"i915_ring_freq_table", i915_ring_freq_table, 0},
b5e50c3f 4421 {"i915_fbc_status", i915_fbc_status, 0},
92d44621 4422 {"i915_ips_status", i915_ips_status, 0},
4a9bef37 4423 {"i915_sr_status", i915_sr_status, 0},
44834a67 4424 {"i915_opregion", i915_opregion, 0},
37811fcc 4425 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
e76d3630 4426 {"i915_context_status", i915_context_status, 0},
c0ab1ae9 4427 {"i915_dump_lrc", i915_dump_lrc, 0},
4ba70e44 4428 {"i915_execlists", i915_execlists, 0},
6d794d42 4429 {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0},
ea16a3cd 4430 {"i915_swizzle_info", i915_swizzle_info, 0},
3cf17fc5 4431 {"i915_ppgtt_info", i915_ppgtt_info, 0},
63573eb7 4432 {"i915_llc", i915_llc, 0},
e91fd8c6 4433 {"i915_edp_psr_status", i915_edp_psr_status, 0},
d2e216d0 4434 {"i915_sink_crc_eDP1", i915_sink_crc, 0},
ec013e7f 4435 {"i915_energy_uJ", i915_energy_uJ, 0},
371db66a 4436 {"i915_pc8_status", i915_pc8_status, 0},
1da51581 4437 {"i915_power_domain_info", i915_power_domain_info, 0},
53f5e3ca 4438 {"i915_display_info", i915_display_info, 0},
e04934cf 4439 {"i915_semaphore_status", i915_semaphore_status, 0},
728e29d7 4440 {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
11bed958 4441 {"i915_dp_mst_info", i915_dp_mst_info, 0},
1ed1ef9d 4442 {"i915_wa_registers", i915_wa_registers, 0},
c5511e44 4443 {"i915_ddb_info", i915_ddb_info, 0},
2017263e 4444};
27c202ad 4445#define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
2017263e 4446
06c5bf8c 4447static const struct i915_debugfs_files {
34b9674c
DV		 4448 const char *name;
4449 const struct file_operations *fops;
4450} i915_debugfs_files[] = {
4451 {"i915_wedged", &i915_wedged_fops},
4452 {"i915_max_freq", &i915_max_freq_fops},
4453 {"i915_min_freq", &i915_min_freq_fops},
4454 {"i915_cache_sharing", &i915_cache_sharing_fops},
4455 {"i915_ring_stop", &i915_ring_stop_fops},
094f9a54
CW		 4456 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
4457 {"i915_ring_test_irq", &i915_ring_test_irq_fops},
34b9674c
DV		 4458 {"i915_gem_drop_caches", &i915_drop_caches_fops},
4459 {"i915_error_state", &i915_error_state_fops},
4460 {"i915_next_seqno", &i915_next_seqno_fops},
bd9db02f 4461 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
369a1342
VS		 4462 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
4463 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
4464 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
da46f936 4465 {"i915_fbc_false_color", &i915_fbc_fc_fops},
34b9674c
DV		 4466};
4467
07144428
DL		 4468void intel_display_crc_init(struct drm_device *dev)
4469{
4470 struct drm_i915_private *dev_priv = dev->dev_private;
b378360e 4471 enum pipe pipe;
07144428 4472
055e393f 4473 for_each_pipe(dev_priv, pipe) {
b378360e 4474 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
07144428 4475
d538bbdf
DL		 4476 pipe_crc->opened = false;
4477 spin_lock_init(&pipe_crc->lock);
07144428
DL		 4478 init_waitqueue_head(&pipe_crc->wq);
4479 }
4480}
4481
27c202ad 4482int i915_debugfs_init(struct drm_minor *minor)
2017263e 4483{
34b9674c 4484 int ret, i;
f3cd474b 4485
6d794d42 4486 ret = i915_forcewake_create(minor->debugfs_root, minor);
358733e9
JB		 4487 if (ret)
4488 return ret;
6a9c308d 4489
07144428
DL		 4490 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
4491 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
4492 if (ret)
4493 return ret;
4494 }
4495
34b9674c
DV		 4496 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
4497 ret = i915_debugfs_create(minor->debugfs_root, minor,
4498 i915_debugfs_files[i].name,
4499 i915_debugfs_files[i].fops);
4500 if (ret)
4501 return ret;
4502 }
40633219 4503
27c202ad
BG		 4504 return drm_debugfs_create_files(i915_debugfs_list,
4505 I915_DEBUGFS_ENTRIES,
2017263e
BG		 4506 minor->debugfs_root, minor);
4507}
4508
27c202ad 4509void i915_debugfs_cleanup(struct drm_minor *minor)
2017263e 4510{
34b9674c
DV		 4511 int i;
4512
27c202ad
BG		 4513 drm_debugfs_remove_files(i915_debugfs_list,
4514 I915_DEBUGFS_ENTRIES, minor);
07144428 4515
6d794d42
BW		 4516 drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
4517 1, minor);
07144428 4518
e309a997 4519 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
07144428
DL		 4520 struct drm_info_list *info_list =
4521 (struct drm_info_list *)&i915_pipe_crc_data[i];
4522
4523 drm_debugfs_remove_files(info_list, 1, minor);
4524 }
4525
34b9674c
DV		 4526 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
4527 struct drm_info_list *info_list =
4528 (struct drm_info_list *) i915_debugfs_files[i].fops;
4529
4530 drm_debugfs_remove_files(info_list, 1, minor);
4531 }
2017263e 4532}
Linux kernel - Deliverables
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