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agp/intel: Sandybridge doesn't require GMCH enabling
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_debugfs.c
CommitLineData
2017263e
BG		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 *
27 */
28
29#include <linux/seq_file.h>
f3cd474b 30#include <linux/debugfs.h>
5a0e3ad6 31#include <linux/slab.h>
2017263e
BG		 32#include "drmP.h"
33#include "drm.h"
4e5359cd 34#include "intel_drv.h"
2017263e
BG		 35#include "i915_drm.h"
36#include "i915_drv.h"
37
38#define DRM_I915_RING_DEBUG 1
39
40
41#if defined(CONFIG_DEBUG_FS)
42
f13d3f73 43enum {
69dc4987 44 ACTIVE_LIST,
f13d3f73
CW		 45 FLUSHING_LIST,
46 INACTIVE_LIST,
d21d5975
CW		 47 PINNED_LIST,
48 DEFERRED_FREE_LIST,
f13d3f73 49};
2017263e 50
c2c347a9
CW		 51enum {
52 RENDER_RING,
53 BSD_RING,
54 BLT_RING,
55};
56
70d39fe4
CW		 57static const char *yesno(int v)
58{
59 return v ? "yes" : "no";
60}
61
62static int i915_capabilities(struct seq_file *m, void *data)
63{
64 struct drm_info_node *node = (struct drm_info_node *) m->private;
65 struct drm_device *dev = node->minor->dev;
66 const struct intel_device_info *info = INTEL_INFO(dev);
67
68 seq_printf(m, "gen: %d\n", info->gen);
69#define B(x) seq_printf(m, #x ": %s\n", yesno(info->x))
70 B(is_mobile);
70d39fe4
CW		 71 B(is_i85x);
72 B(is_i915g);
70d39fe4 73 B(is_i945gm);
70d39fe4
CW		 74 B(is_g33);
75 B(need_gfx_hws);
76 B(is_g4x);
77 B(is_pineview);
78 B(is_broadwater);
79 B(is_crestline);
70d39fe4
CW		 80 B(has_fbc);
81 B(has_rc6);
82 B(has_pipe_cxsr);
83 B(has_hotplug);
84 B(cursor_needs_physical);
85 B(has_overlay);
86 B(overlay_needs_physical);
a6c45cf0 87 B(supports_tv);
549f7365
CW		 88 B(has_bsd_ring);
89 B(has_blt_ring);
70d39fe4
CW		 90#undef B
91
92 return 0;
93}
2017263e 94
a6172a80
CW		 95static const char *get_pin_flag(struct drm_i915_gem_object *obj_priv)
96{
97 if (obj_priv->user_pin_count > 0)
98 return "P";
99 else if (obj_priv->pin_count > 0)
100 return "p";
101 else
102 return " ";
103}
104
105static const char *get_tiling_flag(struct drm_i915_gem_object *obj_priv)
106{
107 switch (obj_priv->tiling_mode) {
108 default:
109 case I915_TILING_NONE: return " ";
110 case I915_TILING_X: return "X";
111 case I915_TILING_Y: return "Y";
112 }
113}
114
37811fcc
CW		 115static void
116describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
117{
118 seq_printf(m, "%p: %s%s %8zd %08x %08x %d%s%s",
119 &obj->base,
120 get_pin_flag(obj),
121 get_tiling_flag(obj),
122 obj->base.size,
123 obj->base.read_domains,
124 obj->base.write_domain,
125 obj->last_rendering_seqno,
126 obj->dirty ? " dirty" : "",
127 obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
128 if (obj->base.name)
129 seq_printf(m, " (name: %d)", obj->base.name);
130 if (obj->fence_reg != I915_FENCE_REG_NONE)
131 seq_printf(m, " (fence: %d)", obj->fence_reg);
132 if (obj->gtt_space != NULL)
a00b10c3
CW		 133 seq_printf(m, " (gtt offset: %08x, size: %08x)",
134 obj->gtt_offset, (unsigned int)obj->gtt_space->size);
fb7d516a
DV		 135 if (obj->pin_mappable || obj->fault_mappable)
136 seq_printf(m, " (mappable)");
69dc4987
CW		 137 if (obj->ring != NULL)
138 seq_printf(m, " (%s)", obj->ring->name);
37811fcc
CW		 139}
140
433e12f7 141static int i915_gem_object_list_info(struct seq_file *m, void *data)
2017263e
BG		 142{
143 struct drm_info_node *node = (struct drm_info_node *) m->private;
433e12f7
BG		 144 uintptr_t list = (uintptr_t) node->info_ent->data;
145 struct list_head *head;
2017263e
BG		 146 struct drm_device *dev = node->minor->dev;
147 drm_i915_private_t *dev_priv = dev->dev_private;
148 struct drm_i915_gem_object *obj_priv;
8f2480fb
CW		 149 size_t total_obj_size, total_gtt_size;
150 int count, ret;
de227ef0
CW		 151
152 ret = mutex_lock_interruptible(&dev->struct_mutex);
153 if (ret)
154 return ret;
2017263e 155
433e12f7
BG		 156 switch (list) {
157 case ACTIVE_LIST:
158 seq_printf(m, "Active:\n");
69dc4987 159 head = &dev_priv->mm.active_list;
433e12f7
BG		 160 break;
161 case INACTIVE_LIST:
a17458fc 162 seq_printf(m, "Inactive:\n");
433e12f7
BG		 163 head = &dev_priv->mm.inactive_list;
164 break;
f13d3f73
CW		 165 case PINNED_LIST:
166 seq_printf(m, "Pinned:\n");
167 head = &dev_priv->mm.pinned_list;
168 break;
433e12f7
BG		 169 case FLUSHING_LIST:
170 seq_printf(m, "Flushing:\n");
171 head = &dev_priv->mm.flushing_list;
172 break;
d21d5975
CW		 173 case DEFERRED_FREE_LIST:
174 seq_printf(m, "Deferred free:\n");
175 head = &dev_priv->mm.deferred_free_list;
176 break;
433e12f7 177 default:
de227ef0
CW		 178 mutex_unlock(&dev->struct_mutex);
179 return -EINVAL;
2017263e 180 }
2017263e 181
8f2480fb 182 total_obj_size = total_gtt_size = count = 0;
69dc4987 183 list_for_each_entry(obj_priv, head, mm_list) {
37811fcc
CW		 184 seq_printf(m, " ");
185 describe_obj(m, obj_priv);
f4ceda89 186 seq_printf(m, "\n");
8f2480fb
CW		 187 total_obj_size += obj_priv->base.size;
188 total_gtt_size += obj_priv->gtt_space->size;
189 count++;
2017263e 190 }
de227ef0 191 mutex_unlock(&dev->struct_mutex);
5e118f41 192
8f2480fb
CW		 193 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
194 count, total_obj_size, total_gtt_size);
2017263e
BG		 195 return 0;
196}
197
73aa808f
CW		 198static int i915_gem_object_info(struct seq_file *m, void* data)
199{
200 struct drm_info_node *node = (struct drm_info_node *) m->private;
201 struct drm_device *dev = node->minor->dev;
202 struct drm_i915_private *dev_priv = dev->dev_private;
203 int ret;
204
205 ret = mutex_lock_interruptible(&dev->struct_mutex);
206 if (ret)
207 return ret;
208
209 seq_printf(m, "%u objects\n", dev_priv->mm.object_count);
210 seq_printf(m, "%zu object bytes\n", dev_priv->mm.object_memory);
211 seq_printf(m, "%u pinned\n", dev_priv->mm.pin_count);
212 seq_printf(m, "%zu pin bytes\n", dev_priv->mm.pin_memory);
fb7d516a
DV		 213 seq_printf(m, "%u mappable objects in gtt\n", dev_priv->mm.gtt_mappable_count);
214 seq_printf(m, "%zu mappable gtt bytes\n", dev_priv->mm.gtt_mappable_memory);
215 seq_printf(m, "%zu mappable gtt used bytes\n", dev_priv->mm.mappable_gtt_used);
216 seq_printf(m, "%zu mappable gtt total\n", dev_priv->mm.mappable_gtt_total);
73aa808f
CW		 217 seq_printf(m, "%u objects in gtt\n", dev_priv->mm.gtt_count);
218 seq_printf(m, "%zu gtt bytes\n", dev_priv->mm.gtt_memory);
219 seq_printf(m, "%zu gtt total\n", dev_priv->mm.gtt_total);
220
221 mutex_unlock(&dev->struct_mutex);
222
223 return 0;
224}
225
226
4e5359cd
SF		 227static int i915_gem_pageflip_info(struct seq_file *m, void *data)
228{
229 struct drm_info_node *node = (struct drm_info_node *) m->private;
230 struct drm_device *dev = node->minor->dev;
231 unsigned long flags;
232 struct intel_crtc *crtc;
233
234 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
235 const char *pipe = crtc->pipe ? "B" : "A";
236 const char *plane = crtc->plane ? "B" : "A";
237 struct intel_unpin_work *work;
238
239 spin_lock_irqsave(&dev->event_lock, flags);
240 work = crtc->unpin_work;
241 if (work == NULL) {
242 seq_printf(m, "No flip due on pipe %s (plane %s)\n",
243 pipe, plane);
244 } else {
245 if (!work->pending) {
246 seq_printf(m, "Flip queued on pipe %s (plane %s)\n",
247 pipe, plane);
248 } else {
249 seq_printf(m, "Flip pending (waiting for vsync) on pipe %s (plane %s)\n",
250 pipe, plane);
251 }
252 if (work->enable_stall_check)
253 seq_printf(m, "Stall check enabled, ");
254 else
255 seq_printf(m, "Stall check waiting for page flip ioctl, ");
256 seq_printf(m, "%d prepares\n", work->pending);
257
258 if (work->old_fb_obj) {
259 struct drm_i915_gem_object *obj_priv = to_intel_bo(work->old_fb_obj);
260 if(obj_priv)
261 seq_printf(m, "Old framebuffer gtt_offset 0x%08x\n", obj_priv->gtt_offset );
262 }
263 if (work->pending_flip_obj) {
264 struct drm_i915_gem_object *obj_priv = to_intel_bo(work->pending_flip_obj);
265 if(obj_priv)
266 seq_printf(m, "New framebuffer gtt_offset 0x%08x\n", obj_priv->gtt_offset );
267 }
268 }
269 spin_unlock_irqrestore(&dev->event_lock, flags);
270 }
271
272 return 0;
273}
274
2017263e
BG		 275static int i915_gem_request_info(struct seq_file *m, void *data)
276{
277 struct drm_info_node *node = (struct drm_info_node *) m->private;
278 struct drm_device *dev = node->minor->dev;
279 drm_i915_private_t *dev_priv = dev->dev_private;
280 struct drm_i915_gem_request *gem_request;
c2c347a9 281 int ret, count;
de227ef0
CW		 282
283 ret = mutex_lock_interruptible(&dev->struct_mutex);
284 if (ret)
285 return ret;
2017263e 286
c2c347a9
CW		 287 count = 0;
288 if (!list_empty(&dev_priv->render_ring.request_list)) {
289 seq_printf(m, "Render requests:\n");
290 list_for_each_entry(gem_request,
291 &dev_priv->render_ring.request_list,
292 list) {
293 seq_printf(m, " %d @ %d\n",
294 gem_request->seqno,
295 (int) (jiffies - gem_request->emitted_jiffies));
296 }
297 count++;
298 }
299 if (!list_empty(&dev_priv->bsd_ring.request_list)) {
300 seq_printf(m, "BSD requests:\n");
301 list_for_each_entry(gem_request,
302 &dev_priv->bsd_ring.request_list,
303 list) {
304 seq_printf(m, " %d @ %d\n",
305 gem_request->seqno,
306 (int) (jiffies - gem_request->emitted_jiffies));
307 }
308 count++;
309 }
310 if (!list_empty(&dev_priv->blt_ring.request_list)) {
311 seq_printf(m, "BLT requests:\n");
312 list_for_each_entry(gem_request,
313 &dev_priv->blt_ring.request_list,
314 list) {
315 seq_printf(m, " %d @ %d\n",
316 gem_request->seqno,
317 (int) (jiffies - gem_request->emitted_jiffies));
318 }
319 count++;
2017263e 320 }
de227ef0
CW		 321 mutex_unlock(&dev->struct_mutex);
322
c2c347a9
CW		 323 if (count == 0)
324 seq_printf(m, "No requests\n");
325
2017263e
BG		 326 return 0;
327}
328
b2223497
CW		 329static void i915_ring_seqno_info(struct seq_file *m,
330 struct intel_ring_buffer *ring)
331{
332 if (ring->get_seqno) {
333 seq_printf(m, "Current sequence (%s): %d\n",
334 ring->name, ring->get_seqno(ring));
335 seq_printf(m, "Waiter sequence (%s): %d\n",
336 ring->name, ring->waiting_seqno);
337 seq_printf(m, "IRQ sequence (%s): %d\n",
338 ring->name, ring->irq_seqno);
339 }
340}
341
2017263e
BG		 342static int i915_gem_seqno_info(struct seq_file *m, void *data)
343{
344 struct drm_info_node *node = (struct drm_info_node *) m->private;
345 struct drm_device *dev = node->minor->dev;
346 drm_i915_private_t *dev_priv = dev->dev_private;
de227ef0
CW		 347 int ret;
348
349 ret = mutex_lock_interruptible(&dev->struct_mutex);
350 if (ret)
351 return ret;
2017263e 352
b2223497
CW		 353 i915_ring_seqno_info(m, &dev_priv->render_ring);
354 i915_ring_seqno_info(m, &dev_priv->bsd_ring);
355 i915_ring_seqno_info(m, &dev_priv->blt_ring);
de227ef0
CW		 356
357 mutex_unlock(&dev->struct_mutex);
358
2017263e
BG		 359 return 0;
360}
361
362
363static int i915_interrupt_info(struct seq_file *m, void *data)
364{
365 struct drm_info_node *node = (struct drm_info_node *) m->private;
366 struct drm_device *dev = node->minor->dev;
367 drm_i915_private_t *dev_priv = dev->dev_private;
de227ef0
CW		 368 int ret;
369
370 ret = mutex_lock_interruptible(&dev->struct_mutex);
371 if (ret)
372 return ret;
2017263e 373
bad720ff 374 if (!HAS_PCH_SPLIT(dev)) {
5f6a1695
ZW		 375 seq_printf(m, "Interrupt enable: %08x\n",
376 I915_READ(IER));
377 seq_printf(m, "Interrupt identity: %08x\n",
378 I915_READ(IIR));
379 seq_printf(m, "Interrupt mask: %08x\n",
380 I915_READ(IMR));
381 seq_printf(m, "Pipe A stat: %08x\n",
382 I915_READ(PIPEASTAT));
383 seq_printf(m, "Pipe B stat: %08x\n",
384 I915_READ(PIPEBSTAT));
385 } else {
386 seq_printf(m, "North Display Interrupt enable: %08x\n",
387 I915_READ(DEIER));
388 seq_printf(m, "North Display Interrupt identity: %08x\n",
389 I915_READ(DEIIR));
390 seq_printf(m, "North Display Interrupt mask: %08x\n",
391 I915_READ(DEIMR));
392 seq_printf(m, "South Display Interrupt enable: %08x\n",
393 I915_READ(SDEIER));
394 seq_printf(m, "South Display Interrupt identity: %08x\n",
395 I915_READ(SDEIIR));
396 seq_printf(m, "South Display Interrupt mask: %08x\n",
397 I915_READ(SDEIMR));
398 seq_printf(m, "Graphics Interrupt enable: %08x\n",
399 I915_READ(GTIER));
400 seq_printf(m, "Graphics Interrupt identity: %08x\n",
401 I915_READ(GTIIR));
402 seq_printf(m, "Graphics Interrupt mask: %08x\n",
403 I915_READ(GTIMR));
404 }
2017263e
BG		 405 seq_printf(m, "Interrupts received: %d\n",
406 atomic_read(&dev_priv->irq_received));
b2223497
CW		 407 i915_ring_seqno_info(m, &dev_priv->render_ring);
408 i915_ring_seqno_info(m, &dev_priv->bsd_ring);
409 i915_ring_seqno_info(m, &dev_priv->blt_ring);
de227ef0
CW		 410 mutex_unlock(&dev->struct_mutex);
411
2017263e
BG		 412 return 0;
413}
414
a6172a80
CW		 415static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
416{
417 struct drm_info_node *node = (struct drm_info_node *) m->private;
418 struct drm_device *dev = node->minor->dev;
419 drm_i915_private_t *dev_priv = dev->dev_private;
de227ef0
CW		 420 int i, ret;
421
422 ret = mutex_lock_interruptible(&dev->struct_mutex);
423 if (ret)
424 return ret;
a6172a80
CW		 425
426 seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
427 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
428 for (i = 0; i < dev_priv->num_fence_regs; i++) {
429 struct drm_gem_object *obj = dev_priv->fence_regs[i].obj;
430
c2c347a9
CW		 431 seq_printf(m, "Fenced object[%2d] = ", i);
432 if (obj == NULL)
433 seq_printf(m, "unused");
434 else
435 describe_obj(m, to_intel_bo(obj));
436 seq_printf(m, "\n");
a6172a80 437 }
de227ef0 438 mutex_unlock(&dev->struct_mutex);
a6172a80
CW		 439
440 return 0;
441}
442
2017263e
BG		 443static int i915_hws_info(struct seq_file *m, void *data)
444{
445 struct drm_info_node *node = (struct drm_info_node *) m->private;
446 struct drm_device *dev = node->minor->dev;
447 drm_i915_private_t *dev_priv = dev->dev_private;
448 int i;
449 volatile u32 *hws;
450
e20f9c64 451 hws = (volatile u32 *)dev_priv->render_ring.status_page.page_addr;
2017263e
BG		 452 if (hws == NULL)
453 return 0;
454
455 for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
456 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
457 i * 4,
458 hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
459 }
460 return 0;
461}
462
5cdf5881
CW		 463static void i915_dump_object(struct seq_file *m,
464 struct io_mapping *mapping,
465 struct drm_i915_gem_object *obj_priv)
6911a9b8 466{
5cdf5881 467 int page, page_count, i;
6911a9b8 468
5cdf5881 469 page_count = obj_priv->base.size / PAGE_SIZE;
6911a9b8 470 for (page = 0; page < page_count; page++) {
5cdf5881
CW		 471 u32 *mem = io_mapping_map_wc(mapping,
472 obj_priv->gtt_offset + page * PAGE_SIZE);
6911a9b8
BG		 473 for (i = 0; i < PAGE_SIZE; i += 4)
474 seq_printf(m, "%08x : %08x\n", i, mem[i / 4]);
5cdf5881 475 io_mapping_unmap(mem);
6911a9b8
BG		 476 }
477}
478
479static int i915_batchbuffer_info(struct seq_file *m, void *data)
480{
481 struct drm_info_node *node = (struct drm_info_node *) m->private;
482 struct drm_device *dev = node->minor->dev;
483 drm_i915_private_t *dev_priv = dev->dev_private;
484 struct drm_gem_object *obj;
485 struct drm_i915_gem_object *obj_priv;
486 int ret;
487
de227ef0
CW		 488 ret = mutex_lock_interruptible(&dev->struct_mutex);
489 if (ret)
490 return ret;
6911a9b8 491
69dc4987 492 list_for_each_entry(obj_priv, &dev_priv->mm.active_list, mm_list) {
a8089e84 493 obj = &obj_priv->base;
6911a9b8 494 if (obj->read_domains & I915_GEM_DOMAIN_COMMAND) {
5cdf5881
CW		 495 seq_printf(m, "--- gtt_offset = 0x%08x\n",
496 obj_priv->gtt_offset);
497 i915_dump_object(m, dev_priv->mm.gtt_mapping, obj_priv);
6911a9b8
BG		 498 }
499 }
500
de227ef0 501 mutex_unlock(&dev->struct_mutex);
6911a9b8
BG		 502
503 return 0;
504}
505
506static int i915_ringbuffer_data(struct seq_file *m, void *data)
507{
508 struct drm_info_node *node = (struct drm_info_node *) m->private;
509 struct drm_device *dev = node->minor->dev;
510 drm_i915_private_t *dev_priv = dev->dev_private;
c2c347a9 511 struct intel_ring_buffer *ring;
de227ef0
CW		 512 int ret;
513
c2c347a9
CW		 514 switch ((uintptr_t)node->info_ent->data) {
515 case RENDER_RING: ring = &dev_priv->render_ring; break;
516 case BSD_RING: ring = &dev_priv->bsd_ring; break;
517 case BLT_RING: ring = &dev_priv->blt_ring; break;
518 default: return -EINVAL;
519 }
520
de227ef0
CW		 521 ret = mutex_lock_interruptible(&dev->struct_mutex);
522 if (ret)
523 return ret;
6911a9b8 524
c2c347a9 525 if (!ring->gem_object) {
6911a9b8 526 seq_printf(m, "No ringbuffer setup\n");
de227ef0 527 } else {
c2c347a9 528 u8 *virt = ring->virtual_start;
de227ef0 529 uint32_t off;
6911a9b8 530
c2c347a9 531 for (off = 0; off < ring->size; off += 4) {
de227ef0
CW		 532 uint32_t *ptr = (uint32_t *)(virt + off);
533 seq_printf(m, "%08x : %08x\n", off, *ptr);
534 }
6911a9b8 535 }
de227ef0 536 mutex_unlock(&dev->struct_mutex);
6911a9b8
BG		 537
538 return 0;
539}
540
541static int i915_ringbuffer_info(struct seq_file *m, void *data)
542{
543 struct drm_info_node *node = (struct drm_info_node *) m->private;
544 struct drm_device *dev = node->minor->dev;
545 drm_i915_private_t *dev_priv = dev->dev_private;
c2c347a9
CW		 546 struct intel_ring_buffer *ring;
547
548 switch ((uintptr_t)node->info_ent->data) {
549 case RENDER_RING: ring = &dev_priv->render_ring; break;
550 case BSD_RING: ring = &dev_priv->bsd_ring; break;
551 case BLT_RING: ring = &dev_priv->blt_ring; break;
552 default: return -EINVAL;
553 }
6911a9b8 554
c2c347a9
CW		 555 if (ring->size == 0)
556 return 0;
6911a9b8 557
c2c347a9
CW		 558 seq_printf(m, "Ring %s:\n", ring->name);
559 seq_printf(m, " Head : %08x\n", I915_READ_HEAD(ring) & HEAD_ADDR);
560 seq_printf(m, " Tail : %08x\n", I915_READ_TAIL(ring) & TAIL_ADDR);
561 seq_printf(m, " Size : %08x\n", ring->size);
562 seq_printf(m, " Active : %08x\n", intel_ring_get_active_head(ring));
563 seq_printf(m, " Control : %08x\n", I915_READ_CTL(ring));
564 seq_printf(m, " Start : %08x\n", I915_READ_START(ring));
6911a9b8
BG		 565
566 return 0;
567}
568
9df30794
CW		 569static const char *pin_flag(int pinned)
570{
571 if (pinned > 0)
572 return " P";
573 else if (pinned < 0)
574 return " p";
575 else
576 return "";
577}
578
579static const char *tiling_flag(int tiling)
580{
581 switch (tiling) {
582 default:
583 case I915_TILING_NONE: return "";
584 case I915_TILING_X: return " X";
585 case I915_TILING_Y: return " Y";
586 }
587}
588
589static const char *dirty_flag(int dirty)
590{
591 return dirty ? " dirty" : "";
592}
593
594static const char *purgeable_flag(int purgeable)
595{
596 return purgeable ? " purgeable" : "";
597}
598
63eeaf38
JB		 599static int i915_error_state(struct seq_file *m, void *unused)
600{
601 struct drm_info_node *node = (struct drm_info_node *) m->private;
602 struct drm_device *dev = node->minor->dev;
603 drm_i915_private_t *dev_priv = dev->dev_private;
604 struct drm_i915_error_state *error;
605 unsigned long flags;
9df30794 606 int i, page, offset, elt;
63eeaf38
JB		 607
608 spin_lock_irqsave(&dev_priv->error_lock, flags);
609 if (!dev_priv->first_error) {
610 seq_printf(m, "no error state collected\n");
611 goto out;
612 }
613
614 error = dev_priv->first_error;
615
8a905236
JB		 616 seq_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec,
617 error->time.tv_usec);
9df30794 618 seq_printf(m, "PCI ID: 0x%04x\n", dev->pci_device);
1d8f38f4
CW		 619 seq_printf(m, "EIR: 0x%08x\n", error->eir);
620 seq_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er);
f406839f
CW		 621 if (INTEL_INFO(dev)->gen >= 6) {
622 seq_printf(m, "ERROR: 0x%08x\n", error->error);
1d8f38f4
CW		 623 seq_printf(m, "Blitter command stream:\n");
624 seq_printf(m, " ACTHD: 0x%08x\n", error->bcs_acthd);
625 seq_printf(m, " IPEHR: 0x%08x\n", error->bcs_ipehr);
626 seq_printf(m, " IPEIR: 0x%08x\n", error->bcs_ipeir);
627 seq_printf(m, " INSTDONE: 0x%08x\n", error->bcs_instdone);
628 seq_printf(m, " seqno: 0x%08x\n", error->bcs_seqno);
f406839f 629 }
1d8f38f4
CW		 630 seq_printf(m, "Render command stream:\n");
631 seq_printf(m, " ACTHD: 0x%08x\n", error->acthd);
63eeaf38
JB		 632 seq_printf(m, " IPEIR: 0x%08x\n", error->ipeir);
633 seq_printf(m, " IPEHR: 0x%08x\n", error->ipehr);
634 seq_printf(m, " INSTDONE: 0x%08x\n", error->instdone);
a6c45cf0 635 if (INTEL_INFO(dev)->gen >= 4) {
63eeaf38 636 seq_printf(m, " INSTDONE1: 0x%08x\n", error->instdone1);
1d8f38f4 637 seq_printf(m, " INSTPS: 0x%08x\n", error->instps);
63eeaf38 638 }
1d8f38f4
CW		 639 seq_printf(m, " INSTPM: 0x%08x\n", error->instpm);
640 seq_printf(m, " seqno: 0x%08x\n", error->seqno);
9df30794
CW		 641
642 if (error->active_bo_count) {
643 seq_printf(m, "Buffers [%d]:\n", error->active_bo_count);
644
645 for (i = 0; i < error->active_bo_count; i++) {
646 seq_printf(m, " %08x %8zd %08x %08x %08x%s%s%s%s",
647 error->active_bo[i].gtt_offset,
648 error->active_bo[i].size,
649 error->active_bo[i].read_domains,
650 error->active_bo[i].write_domain,
651 error->active_bo[i].seqno,
652 pin_flag(error->active_bo[i].pinned),
653 tiling_flag(error->active_bo[i].tiling),
654 dirty_flag(error->active_bo[i].dirty),
655 purgeable_flag(error->active_bo[i].purgeable));
656
657 if (error->active_bo[i].name)
658 seq_printf(m, " (name: %d)", error->active_bo[i].name);
659 if (error->active_bo[i].fence_reg != I915_FENCE_REG_NONE)
660 seq_printf(m, " (fence: %d)", error->active_bo[i].fence_reg);
661
662 seq_printf(m, "\n");
663 }
664 }
665
666 for (i = 0; i < ARRAY_SIZE(error->batchbuffer); i++) {
667 if (error->batchbuffer[i]) {
668 struct drm_i915_error_object *obj = error->batchbuffer[i];
669
670 seq_printf(m, "--- gtt_offset = 0x%08x\n", obj->gtt_offset);
671 offset = 0;
672 for (page = 0; page < obj->page_count; page++) {
673 for (elt = 0; elt < PAGE_SIZE/4; elt++) {
674 seq_printf(m, "%08x : %08x\n", offset, obj->pages[page][elt]);
675 offset += 4;
676 }
677 }
678 }
679 }
680
681 if (error->ringbuffer) {
682 struct drm_i915_error_object *obj = error->ringbuffer;
683
684 seq_printf(m, "--- ringbuffer = 0x%08x\n", obj->gtt_offset);
685 offset = 0;
686 for (page = 0; page < obj->page_count; page++) {
687 for (elt = 0; elt < PAGE_SIZE/4; elt++) {
688 seq_printf(m, "%08x : %08x\n", offset, obj->pages[page][elt]);
689 offset += 4;
690 }
691 }
692 }
63eeaf38 693
6ef3d427
CW		 694 if (error->overlay)
695 intel_overlay_print_error_state(m, error->overlay);
696
63eeaf38
JB		 697out:
698 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
699
700 return 0;
701}
6911a9b8 702
f97108d1
JB		 703static int i915_rstdby_delays(struct seq_file *m, void *unused)
704{
705 struct drm_info_node *node = (struct drm_info_node *) m->private;
706 struct drm_device *dev = node->minor->dev;
707 drm_i915_private_t *dev_priv = dev->dev_private;
708 u16 crstanddelay = I915_READ16(CRSTANDVID);
709
710 seq_printf(m, "w/ctx: %d, w/o ctx: %d\n", (crstanddelay >> 8) & 0x3f, (crstanddelay & 0x3f));
711
712 return 0;
713}
714
715static int i915_cur_delayinfo(struct seq_file *m, void *unused)
716{
717 struct drm_info_node *node = (struct drm_info_node *) m->private;
718 struct drm_device *dev = node->minor->dev;
719 drm_i915_private_t *dev_priv = dev->dev_private;
720 u16 rgvswctl = I915_READ16(MEMSWCTL);
7648fa99 721 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
f97108d1 722
7648fa99
JB		 723 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
724 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
725 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
726 MEMSTAT_VID_SHIFT);
727 seq_printf(m, "Current P-state: %d\n",
728 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
f97108d1
JB		 729
730 return 0;
731}
732
733static int i915_delayfreq_table(struct seq_file *m, void *unused)
734{
735 struct drm_info_node *node = (struct drm_info_node *) m->private;
736 struct drm_device *dev = node->minor->dev;
737 drm_i915_private_t *dev_priv = dev->dev_private;
738 u32 delayfreq;
739 int i;
740
741 for (i = 0; i < 16; i++) {
742 delayfreq = I915_READ(PXVFREQ_BASE + i * 4);
7648fa99
JB		 743 seq_printf(m, "P%02dVIDFREQ: 0x%08x (VID: %d)\n", i, delayfreq,
744 (delayfreq & PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT);
f97108d1
JB		 745 }
746
747 return 0;
748}
749
750static inline int MAP_TO_MV(int map)
751{
752 return 1250 - (map * 25);
753}
754
755static int i915_inttoext_table(struct seq_file *m, void *unused)
756{
757 struct drm_info_node *node = (struct drm_info_node *) m->private;
758 struct drm_device *dev = node->minor->dev;
759 drm_i915_private_t *dev_priv = dev->dev_private;
760 u32 inttoext;
761 int i;
762
763 for (i = 1; i <= 32; i++) {
764 inttoext = I915_READ(INTTOEXT_BASE_ILK + i * 4);
765 seq_printf(m, "INTTOEXT%02d: 0x%08x\n", i, inttoext);
766 }
767
768 return 0;
769}
770
771static int i915_drpc_info(struct seq_file *m, void *unused)
772{
773 struct drm_info_node *node = (struct drm_info_node *) m->private;
774 struct drm_device *dev = node->minor->dev;
775 drm_i915_private_t *dev_priv = dev->dev_private;
776 u32 rgvmodectl = I915_READ(MEMMODECTL);
7648fa99
JB		 777 u32 rstdbyctl = I915_READ(MCHBAR_RENDER_STANDBY);
778 u16 crstandvid = I915_READ16(CRSTANDVID);
f97108d1
JB		 779
780 seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
781 "yes" : "no");
782 seq_printf(m, "Boost freq: %d\n",
783 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
784 MEMMODE_BOOST_FREQ_SHIFT);
785 seq_printf(m, "HW control enabled: %s\n",
786 rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");
787 seq_printf(m, "SW control enabled: %s\n",
788 rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");
789 seq_printf(m, "Gated voltage change: %s\n",
790 rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");
791 seq_printf(m, "Starting frequency: P%d\n",
792 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
7648fa99 793 seq_printf(m, "Max P-state: P%d\n",
f97108d1 794 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
7648fa99
JB		 795 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
796 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
797 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
798 seq_printf(m, "Render standby enabled: %s\n",
799 (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes");
f97108d1
JB		 800
801 return 0;
802}
803
b5e50c3f
JB		 804static int i915_fbc_status(struct seq_file *m, void *unused)
805{
806 struct drm_info_node *node = (struct drm_info_node *) m->private;
807 struct drm_device *dev = node->minor->dev;
b5e50c3f 808 drm_i915_private_t *dev_priv = dev->dev_private;
b5e50c3f 809
ee5382ae 810 if (!I915_HAS_FBC(dev)) {
b5e50c3f
JB		 811 seq_printf(m, "FBC unsupported on this chipset\n");
812 return 0;
813 }
814
ee5382ae 815 if (intel_fbc_enabled(dev)) {
b5e50c3f
JB		 816 seq_printf(m, "FBC enabled\n");
817 } else {
818 seq_printf(m, "FBC disabled: ");
819 switch (dev_priv->no_fbc_reason) {
bed4a673
CW		 820 case FBC_NO_OUTPUT:
821 seq_printf(m, "no outputs");
822 break;
b5e50c3f
JB		 823 case FBC_STOLEN_TOO_SMALL:
824 seq_printf(m, "not enough stolen memory");
825 break;
826 case FBC_UNSUPPORTED_MODE:
827 seq_printf(m, "mode not supported");
828 break;
829 case FBC_MODE_TOO_LARGE:
830 seq_printf(m, "mode too large");
831 break;
832 case FBC_BAD_PLANE:
833 seq_printf(m, "FBC unsupported on plane");
834 break;
835 case FBC_NOT_TILED:
836 seq_printf(m, "scanout buffer not tiled");
837 break;
9c928d16
JB		 838 case FBC_MULTIPLE_PIPES:
839 seq_printf(m, "multiple pipes are enabled");
840 break;
b5e50c3f
JB		 841 default:
842 seq_printf(m, "unknown reason");
843 }
844 seq_printf(m, "\n");
845 }
846 return 0;
847}
848
4a9bef37
JB		 849static int i915_sr_status(struct seq_file *m, void *unused)
850{
851 struct drm_info_node *node = (struct drm_info_node *) m->private;
852 struct drm_device *dev = node->minor->dev;
853 drm_i915_private_t *dev_priv = dev->dev_private;
854 bool sr_enabled = false;
855
f00a3ddf 856 if (IS_GEN5(dev))
5ba2aaaa 857 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
a6c45cf0 858 else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))
4a9bef37
JB		 859 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
860 else if (IS_I915GM(dev))
861 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
862 else if (IS_PINEVIEW(dev))
863 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
864
5ba2aaaa
CW		 865 seq_printf(m, "self-refresh: %s\n",
866 sr_enabled ? "enabled" : "disabled");
4a9bef37
JB		 867
868 return 0;
869}
870
7648fa99
JB		 871static int i915_emon_status(struct seq_file *m, void *unused)
872{
873 struct drm_info_node *node = (struct drm_info_node *) m->private;
874 struct drm_device *dev = node->minor->dev;
875 drm_i915_private_t *dev_priv = dev->dev_private;
876 unsigned long temp, chipset, gfx;
de227ef0
CW		 877 int ret;
878
879 ret = mutex_lock_interruptible(&dev->struct_mutex);
880 if (ret)
881 return ret;
7648fa99
JB		 882
883 temp = i915_mch_val(dev_priv);
884 chipset = i915_chipset_val(dev_priv);
885 gfx = i915_gfx_val(dev_priv);
de227ef0 886 mutex_unlock(&dev->struct_mutex);
7648fa99
JB		 887
888 seq_printf(m, "GMCH temp: %ld\n", temp);
889 seq_printf(m, "Chipset power: %ld\n", chipset);
890 seq_printf(m, "GFX power: %ld\n", gfx);
891 seq_printf(m, "Total power: %ld\n", chipset + gfx);
892
893 return 0;
894}
895
896static int i915_gfxec(struct seq_file *m, void *unused)
897{
898 struct drm_info_node *node = (struct drm_info_node *) m->private;
899 struct drm_device *dev = node->minor->dev;
900 drm_i915_private_t *dev_priv = dev->dev_private;
901
902 seq_printf(m, "GFXEC: %ld\n", (unsigned long)I915_READ(0x112f4));
903
904 return 0;
905}
906
44834a67
CW		 907static int i915_opregion(struct seq_file *m, void *unused)
908{
909 struct drm_info_node *node = (struct drm_info_node *) m->private;
910 struct drm_device *dev = node->minor->dev;
911 drm_i915_private_t *dev_priv = dev->dev_private;
912 struct intel_opregion *opregion = &dev_priv->opregion;
913 int ret;
914
915 ret = mutex_lock_interruptible(&dev->struct_mutex);
916 if (ret)
917 return ret;
918
919 if (opregion->header)
920 seq_write(m, opregion->header, OPREGION_SIZE);
921
922 mutex_unlock(&dev->struct_mutex);
923
924 return 0;
925}
926
37811fcc
CW		 927static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
928{
929 struct drm_info_node *node = (struct drm_info_node *) m->private;
930 struct drm_device *dev = node->minor->dev;
931 drm_i915_private_t *dev_priv = dev->dev_private;
932 struct intel_fbdev *ifbdev;
933 struct intel_framebuffer *fb;
934 int ret;
935
936 ret = mutex_lock_interruptible(&dev->mode_config.mutex);
937 if (ret)
938 return ret;
939
940 ifbdev = dev_priv->fbdev;
941 fb = to_intel_framebuffer(ifbdev->helper.fb);
942
943 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, obj ",
944 fb->base.width,
945 fb->base.height,
946 fb->base.depth,
947 fb->base.bits_per_pixel);
948 describe_obj(m, to_intel_bo(fb->obj));
949 seq_printf(m, "\n");
950
951 list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) {
952 if (&fb->base == ifbdev->helper.fb)
953 continue;
954
955 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, obj ",
956 fb->base.width,
957 fb->base.height,
958 fb->base.depth,
959 fb->base.bits_per_pixel);
960 describe_obj(m, to_intel_bo(fb->obj));
961 seq_printf(m, "\n");
962 }
963
964 mutex_unlock(&dev->mode_config.mutex);
965
966 return 0;
967}
968
f3cd474b
CW		 969static int
970i915_wedged_open(struct inode *inode,
971 struct file *filp)
972{
973 filp->private_data = inode->i_private;
974 return 0;
975}
976
977static ssize_t
978i915_wedged_read(struct file *filp,
979 char __user *ubuf,
980 size_t max,
981 loff_t *ppos)
982{
983 struct drm_device *dev = filp->private_data;
984 drm_i915_private_t *dev_priv = dev->dev_private;
985 char buf[80];
986 int len;
987
988 len = snprintf(buf, sizeof (buf),
989 "wedged : %d\n",
990 atomic_read(&dev_priv->mm.wedged));
991
f4433a8d
DC		 992 if (len > sizeof (buf))
993 len = sizeof (buf);
994
f3cd474b
CW		 995 return simple_read_from_buffer(ubuf, max, ppos, buf, len);
996}
997
998static ssize_t
999i915_wedged_write(struct file *filp,
1000 const char __user *ubuf,
1001 size_t cnt,
1002 loff_t *ppos)
1003{
1004 struct drm_device *dev = filp->private_data;
1005 drm_i915_private_t *dev_priv = dev->dev_private;
1006 char buf[20];
1007 int val = 1;
1008
1009 if (cnt > 0) {
1010 if (cnt > sizeof (buf) - 1)
1011 return -EINVAL;
1012
1013 if (copy_from_user(buf, ubuf, cnt))
1014 return -EFAULT;
1015 buf[cnt] = 0;
1016
1017 val = simple_strtoul(buf, NULL, 0);
1018 }
1019
1020 DRM_INFO("Manually setting wedged to %d\n", val);
1021
1022 atomic_set(&dev_priv->mm.wedged, val);
1023 if (val) {
f787a5f5 1024 wake_up_all(&dev_priv->irq_queue);
f3cd474b
CW		 1025 queue_work(dev_priv->wq, &dev_priv->error_work);
1026 }
1027
1028 return cnt;
1029}
1030
1031static const struct file_operations i915_wedged_fops = {
1032 .owner = THIS_MODULE,
1033 .open = i915_wedged_open,
1034 .read = i915_wedged_read,
1035 .write = i915_wedged_write,
6038f373 1036 .llseek = default_llseek,
f3cd474b
CW		 1037};
1038
1039/* As the drm_debugfs_init() routines are called before dev->dev_private is
1040 * allocated we need to hook into the minor for release. */
1041static int
1042drm_add_fake_info_node(struct drm_minor *minor,
1043 struct dentry *ent,
1044 const void *key)
1045{
1046 struct drm_info_node *node;
1047
1048 node = kmalloc(sizeof(struct drm_info_node), GFP_KERNEL);
1049 if (node == NULL) {
1050 debugfs_remove(ent);
1051 return -ENOMEM;
1052 }
1053
1054 node->minor = minor;
1055 node->dent = ent;
1056 node->info_ent = (void *) key;
1057 list_add(&node->list, &minor->debugfs_nodes.list);
1058
1059 return 0;
1060}
1061
1062static int i915_wedged_create(struct dentry *root, struct drm_minor *minor)
1063{
1064 struct drm_device *dev = minor->dev;
1065 struct dentry *ent;
1066
1067 ent = debugfs_create_file("i915_wedged",
1068 S_IRUGO | S_IWUSR,
1069 root, dev,
1070 &i915_wedged_fops);
1071 if (IS_ERR(ent))
1072 return PTR_ERR(ent);
1073
1074 return drm_add_fake_info_node(minor, ent, &i915_wedged_fops);
1075}
9e3a6d15 1076
27c202ad 1077static struct drm_info_list i915_debugfs_list[] = {
70d39fe4 1078 {"i915_capabilities", i915_capabilities, 0, 0},
73aa808f 1079 {"i915_gem_objects", i915_gem_object_info, 0},
433e12f7
BG		 1080 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
1081 {"i915_gem_flushing", i915_gem_object_list_info, 0, (void *) FLUSHING_LIST},
1082 {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
f13d3f73 1083 {"i915_gem_pinned", i915_gem_object_list_info, 0, (void *) PINNED_LIST},
d21d5975 1084 {"i915_gem_deferred_free", i915_gem_object_list_info, 0, (void *) DEFERRED_FREE_LIST},
4e5359cd 1085 {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
2017263e
BG		 1086 {"i915_gem_request", i915_gem_request_info, 0},
1087 {"i915_gem_seqno", i915_gem_seqno_info, 0},
a6172a80 1088 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
2017263e
BG		 1089 {"i915_gem_interrupt", i915_interrupt_info, 0},
1090 {"i915_gem_hws", i915_hws_info, 0},
c2c347a9
CW		 1091 {"i915_ringbuffer_data", i915_ringbuffer_data, 0, (void *)RENDER_RING},
1092 {"i915_ringbuffer_info", i915_ringbuffer_info, 0, (void *)RENDER_RING},
1093 {"i915_bsd_ringbuffer_data", i915_ringbuffer_data, 0, (void *)BSD_RING},
1094 {"i915_bsd_ringbuffer_info", i915_ringbuffer_info, 0, (void *)BSD_RING},
1095 {"i915_blt_ringbuffer_data", i915_ringbuffer_data, 0, (void *)BLT_RING},
1096 {"i915_blt_ringbuffer_info", i915_ringbuffer_info, 0, (void *)BLT_RING},
6911a9b8 1097 {"i915_batchbuffers", i915_batchbuffer_info, 0},
63eeaf38 1098 {"i915_error_state", i915_error_state, 0},
f97108d1
JB		 1099 {"i915_rstdby_delays", i915_rstdby_delays, 0},
1100 {"i915_cur_delayinfo", i915_cur_delayinfo, 0},
1101 {"i915_delayfreq_table", i915_delayfreq_table, 0},
1102 {"i915_inttoext_table", i915_inttoext_table, 0},
1103 {"i915_drpc_info", i915_drpc_info, 0},
7648fa99
JB		 1104 {"i915_emon_status", i915_emon_status, 0},
1105 {"i915_gfxec", i915_gfxec, 0},
b5e50c3f 1106 {"i915_fbc_status", i915_fbc_status, 0},
4a9bef37 1107 {"i915_sr_status", i915_sr_status, 0},
44834a67 1108 {"i915_opregion", i915_opregion, 0},
37811fcc 1109 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
2017263e 1110};
27c202ad 1111#define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
2017263e 1112
27c202ad 1113int i915_debugfs_init(struct drm_minor *minor)
2017263e 1114{
f3cd474b
CW		 1115 int ret;
1116
1117 ret = i915_wedged_create(minor->debugfs_root, minor);
1118 if (ret)
1119 return ret;
1120
27c202ad
BG		 1121 return drm_debugfs_create_files(i915_debugfs_list,
1122 I915_DEBUGFS_ENTRIES,
2017263e
BG		 1123 minor->debugfs_root, minor);
1124}
1125
27c202ad 1126void i915_debugfs_cleanup(struct drm_minor *minor)
2017263e 1127{
27c202ad
BG		 1128 drm_debugfs_remove_files(i915_debugfs_list,
1129 I915_DEBUGFS_ENTRIES, minor);
33db679b
KH		 1130 drm_debugfs_remove_files((struct drm_info_list *) &i915_wedged_fops,
1131 1, minor);
2017263e
BG		 1132}
1133
1134#endif /* CONFIG_DEBUG_FS */
Linux kernel - Deliverables
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