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drm/i915: abolish separate per-ring default_context pointers
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_debugfs.c
CommitLineData
2017263e
BG		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 *
27 */
28
29#include <linux/seq_file.h>
b2c88f5b 30#include <linux/circ_buf.h>
926321d5 31#include <linux/ctype.h>
f3cd474b 32#include <linux/debugfs.h>
5a0e3ad6 33#include <linux/slab.h>
2d1a8a48 34#include <linux/export.h>
6d2b8885 35#include <linux/list_sort.h>
ec013e7f 36#include <asm/msr-index.h>
760285e7 37#include <drm/drmP.h>
4e5359cd 38#include "intel_drv.h"
e5c65260 39#include "intel_ringbuffer.h"
760285e7 40#include <drm/i915_drm.h>
2017263e
BG		 41#include "i915_drv.h"
42
f13d3f73 43enum {
69dc4987 44 ACTIVE_LIST,
f13d3f73 45 INACTIVE_LIST,
d21d5975 46 PINNED_LIST,
f13d3f73 47};
2017263e 48
497666d8
DL		 49/* As the drm_debugfs_init() routines are called before dev->dev_private is
50 * allocated we need to hook into the minor for release. */
51static int
52drm_add_fake_info_node(struct drm_minor *minor,
53 struct dentry *ent,
54 const void *key)
55{
56 struct drm_info_node *node;
57
58 node = kmalloc(sizeof(*node), GFP_KERNEL);
59 if (node == NULL) {
60 debugfs_remove(ent);
61 return -ENOMEM;
62 }
63
64 node->minor = minor;
65 node->dent = ent;
66 node->info_ent = (void *) key;
67
68 mutex_lock(&minor->debugfs_lock);
69 list_add(&node->list, &minor->debugfs_list);
70 mutex_unlock(&minor->debugfs_lock);
71
72 return 0;
73}
74
70d39fe4
CW		 75static int i915_capabilities(struct seq_file *m, void *data)
76{
9f25d007 77 struct drm_info_node *node = m->private;
70d39fe4
CW		 78 struct drm_device *dev = node->minor->dev;
79 const struct intel_device_info *info = INTEL_INFO(dev);
80
81 seq_printf(m, "gen: %d\n", info->gen);
03d00ac5 82 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
79fc46df
DL		 83#define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
84#define SEP_SEMICOLON ;
85 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
86#undef PRINT_FLAG
87#undef SEP_SEMICOLON
70d39fe4
CW		 88
89 return 0;
90}
2017263e 91
05394f39 92static const char *get_pin_flag(struct drm_i915_gem_object *obj)
a6172a80 93{
baaa5cfb 94 if (obj->pin_display)
a6172a80
CW		 95 return "p";
96 else
97 return " ";
98}
99
05394f39 100static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
a6172a80 101{
0206e353
AJ		 102 switch (obj->tiling_mode) {
103 default:
104 case I915_TILING_NONE: return " ";
105 case I915_TILING_X: return "X";
106 case I915_TILING_Y: return "Y";
107 }
a6172a80
CW		 108}
109
1d693bcc
BW		 110static inline const char *get_global_flag(struct drm_i915_gem_object *obj)
111{
aff43766 112 return i915_gem_obj_to_ggtt(obj) ? "g" : " ";
1d693bcc
BW		 113}
114
ca1543be
TU		 115static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj)
116{
117 u64 size = 0;
118 struct i915_vma *vma;
119
120 list_for_each_entry(vma, &obj->vma_list, vma_link) {
121 if (i915_is_ggtt(vma->vm) &&
122 drm_mm_node_allocated(&vma->node))
123 size += vma->node.size;
124 }
125
126 return size;
127}
128
37811fcc
CW		 129static void
130describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
131{
b4716185
CW		 132 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
133 struct intel_engine_cs *ring;
1d693bcc 134 struct i915_vma *vma;
d7f46fc4 135 int pin_count = 0;
b4716185 136 int i;
d7f46fc4 137
b4716185 138 seq_printf(m, "%pK: %s%s%s%s %8zdKiB %02x %02x [ ",
37811fcc 139 &obj->base,
481a3d43 140 obj->active ? "*" : " ",
37811fcc
CW		 141 get_pin_flag(obj),
142 get_tiling_flag(obj),
1d693bcc 143 get_global_flag(obj),
a05a5862 144 obj->base.size / 1024,
37811fcc 145 obj->base.read_domains,
b4716185
CW		 146 obj->base.write_domain);
147 for_each_ring(ring, dev_priv, i)
148 seq_printf(m, "%x ",
149 i915_gem_request_get_seqno(obj->last_read_req[i]));
150 seq_printf(m, "] %x %x%s%s%s",
97b2a6a1
JH		 151 i915_gem_request_get_seqno(obj->last_write_req),
152 i915_gem_request_get_seqno(obj->last_fenced_req),
0a4cd7c8 153 i915_cache_level_str(to_i915(obj->base.dev), obj->cache_level),
37811fcc
CW		 154 obj->dirty ? " dirty" : "",
155 obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
156 if (obj->base.name)
157 seq_printf(m, " (name: %d)", obj->base.name);
ba0635ff 158 list_for_each_entry(vma, &obj->vma_list, vma_link) {
d7f46fc4
BW		 159 if (vma->pin_count > 0)
160 pin_count++;
ba0635ff
DC		 161 }
162 seq_printf(m, " (pinned x %d)", pin_count);
cc98b413
CW		 163 if (obj->pin_display)
164 seq_printf(m, " (display)");
37811fcc
CW		 165 if (obj->fence_reg != I915_FENCE_REG_NONE)
166 seq_printf(m, " (fence: %d)", obj->fence_reg);
1d693bcc 167 list_for_each_entry(vma, &obj->vma_list, vma_link) {
8d2fdc3f
TU		 168 seq_printf(m, " (%sgtt offset: %08llx, size: %08llx",
169 i915_is_ggtt(vma->vm) ? "g" : "pp",
170 vma->node.start, vma->node.size);
171 if (i915_is_ggtt(vma->vm))
172 seq_printf(m, ", type: %u)", vma->ggtt_view.type);
1d693bcc 173 else
8d2fdc3f 174 seq_puts(m, ")");
1d693bcc 175 }
c1ad11fc 176 if (obj->stolen)
440fd528 177 seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
30154650 178 if (obj->pin_display || obj->fault_mappable) {
6299f992 179 char s[3], *t = s;
30154650 180 if (obj->pin_display)
6299f992
CW		 181 *t++ = 'p';
182 if (obj->fault_mappable)
183 *t++ = 'f';
184 *t = '\0';
185 seq_printf(m, " (%s mappable)", s);
186 }
b4716185 187 if (obj->last_write_req != NULL)
41c52415 188 seq_printf(m, " (%s)",
b4716185 189 i915_gem_request_get_ring(obj->last_write_req)->name);
d5a81ef1
DV		 190 if (obj->frontbuffer_bits)
191 seq_printf(m, " (frontbuffer: 0x%03x)", obj->frontbuffer_bits);
37811fcc
CW		 192}
193
273497e5 194static void describe_ctx(struct seq_file *m, struct intel_context *ctx)
3ccfd19d 195{
ea0c76f8 196 seq_putc(m, ctx->legacy_hw_ctx.initialized ? 'I' : 'i');
3ccfd19d
BW		 197 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
198 seq_putc(m, ' ');
199}
200
433e12f7 201static int i915_gem_object_list_info(struct seq_file *m, void *data)
2017263e 202{
9f25d007 203 struct drm_info_node *node = m->private;
433e12f7
BG		 204 uintptr_t list = (uintptr_t) node->info_ent->data;
205 struct list_head *head;
2017263e 206 struct drm_device *dev = node->minor->dev;
5cef07e1
BW		 207 struct drm_i915_private *dev_priv = dev->dev_private;
208 struct i915_address_space *vm = &dev_priv->gtt.base;
ca191b13 209 struct i915_vma *vma;
c44ef60e 210 u64 total_obj_size, total_gtt_size;
8f2480fb 211 int count, ret;
de227ef0
CW		 212
213 ret = mutex_lock_interruptible(&dev->struct_mutex);
214 if (ret)
215 return ret;
2017263e 216
ca191b13 217 /* FIXME: the user of this interface might want more than just GGTT */
433e12f7
BG		 218 switch (list) {
219 case ACTIVE_LIST:
267f0c90 220 seq_puts(m, "Active:\n");
5cef07e1 221 head = &vm->active_list;
433e12f7
BG		 222 break;
223 case INACTIVE_LIST:
267f0c90 224 seq_puts(m, "Inactive:\n");
5cef07e1 225 head = &vm->inactive_list;
433e12f7 226 break;
433e12f7 227 default:
de227ef0
CW		 228 mutex_unlock(&dev->struct_mutex);
229 return -EINVAL;
2017263e 230 }
2017263e 231
8f2480fb 232 total_obj_size = total_gtt_size = count = 0;
ca191b13
BW		 233 list_for_each_entry(vma, head, mm_list) {
234 seq_printf(m, " ");
235 describe_obj(m, vma->obj);
236 seq_printf(m, "\n");
237 total_obj_size += vma->obj->base.size;
238 total_gtt_size += vma->node.size;
8f2480fb 239 count++;
2017263e 240 }
de227ef0 241 mutex_unlock(&dev->struct_mutex);
5e118f41 242
c44ef60e 243 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
8f2480fb 244 count, total_obj_size, total_gtt_size);
2017263e
BG		 245 return 0;
246}
247
6d2b8885
CW		 248static int obj_rank_by_stolen(void *priv,
249 struct list_head *A, struct list_head *B)
250{
251 struct drm_i915_gem_object *a =
b25cb2f8 252 container_of(A, struct drm_i915_gem_object, obj_exec_link);
6d2b8885 253 struct drm_i915_gem_object *b =
b25cb2f8 254 container_of(B, struct drm_i915_gem_object, obj_exec_link);
6d2b8885 255
2d05fa16
RV		 256 if (a->stolen->start < b->stolen->start)
257 return -1;
258 if (a->stolen->start > b->stolen->start)
259 return 1;
260 return 0;
6d2b8885
CW		 261}
262
263static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
264{
9f25d007 265 struct drm_info_node *node = m->private;
6d2b8885
CW		 266 struct drm_device *dev = node->minor->dev;
267 struct drm_i915_private *dev_priv = dev->dev_private;
268 struct drm_i915_gem_object *obj;
c44ef60e 269 u64 total_obj_size, total_gtt_size;
6d2b8885
CW		 270 LIST_HEAD(stolen);
271 int count, ret;
272
273 ret = mutex_lock_interruptible(&dev->struct_mutex);
274 if (ret)
275 return ret;
276
277 total_obj_size = total_gtt_size = count = 0;
278 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
279 if (obj->stolen == NULL)
280 continue;
281
b25cb2f8 282 list_add(&obj->obj_exec_link, &stolen);
6d2b8885
CW		 283
284 total_obj_size += obj->base.size;
ca1543be 285 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
6d2b8885
CW		 286 count++;
287 }
288 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
289 if (obj->stolen == NULL)
290 continue;
291
b25cb2f8 292 list_add(&obj->obj_exec_link, &stolen);
6d2b8885
CW		 293
294 total_obj_size += obj->base.size;
295 count++;
296 }
297 list_sort(NULL, &stolen, obj_rank_by_stolen);
298 seq_puts(m, "Stolen:\n");
299 while (!list_empty(&stolen)) {
b25cb2f8 300 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
6d2b8885
CW		 301 seq_puts(m, " ");
302 describe_obj(m, obj);
303 seq_putc(m, '\n');
b25cb2f8 304 list_del_init(&obj->obj_exec_link);
6d2b8885
CW		 305 }
306 mutex_unlock(&dev->struct_mutex);
307
c44ef60e 308 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
6d2b8885
CW		 309 count, total_obj_size, total_gtt_size);
310 return 0;
311}
312
6299f992
CW		 313#define count_objects(list, member) do { \
314 list_for_each_entry(obj, list, member) { \
ca1543be 315 size += i915_gem_obj_total_ggtt_size(obj); \
6299f992
CW		 316 ++count; \
317 if (obj->map_and_fenceable) { \
f343c5f6 318 mappable_size += i915_gem_obj_ggtt_size(obj); \
6299f992
CW		 319 ++mappable_count; \
320 } \
321 } \
0206e353 322} while (0)
6299f992 323
2db8e9d6 324struct file_stats {
6313c204 325 struct drm_i915_file_private *file_priv;
c44ef60e
MK		 326 unsigned long count;
327 u64 total, unbound;
328 u64 global, shared;
329 u64 active, inactive;
2db8e9d6
CW		 330};
331
332static int per_file_stats(int id, void *ptr, void *data)
333{
334 struct drm_i915_gem_object *obj = ptr;
335 struct file_stats *stats = data;
6313c204 336 struct i915_vma *vma;
2db8e9d6
CW		 337
338 stats->count++;
339 stats->total += obj->base.size;
340
c67a17e9
CW		 341 if (obj->base.name || obj->base.dma_buf)
342 stats->shared += obj->base.size;
343
6313c204
CW		 344 if (USES_FULL_PPGTT(obj->base.dev)) {
345 list_for_each_entry(vma, &obj->vma_list, vma_link) {
346 struct i915_hw_ppgtt *ppgtt;
347
348 if (!drm_mm_node_allocated(&vma->node))
349 continue;
350
351 if (i915_is_ggtt(vma->vm)) {
352 stats->global += obj->base.size;
353 continue;
354 }
355
356 ppgtt = container_of(vma->vm, struct i915_hw_ppgtt, base);
4d884705 357 if (ppgtt->file_priv != stats->file_priv)
6313c204
CW		 358 continue;
359
41c52415 360 if (obj->active) /* XXX per-vma statistic */
6313c204
CW		 361 stats->active += obj->base.size;
362 else
363 stats->inactive += obj->base.size;
364
365 return 0;
366 }
2db8e9d6 367 } else {
6313c204
CW		 368 if (i915_gem_obj_ggtt_bound(obj)) {
369 stats->global += obj->base.size;
41c52415 370 if (obj->active)
6313c204
CW		 371 stats->active += obj->base.size;
372 else
373 stats->inactive += obj->base.size;
374 return 0;
375 }
2db8e9d6
CW		 376 }
377
6313c204
CW		 378 if (!list_empty(&obj->global_list))
379 stats->unbound += obj->base.size;
380
2db8e9d6
CW		 381 return 0;
382}
383
b0da1b79
CW		 384#define print_file_stats(m, name, stats) do { \
385 if (stats.count) \
c44ef60e 386 seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \
b0da1b79
CW		 387 name, \
388 stats.count, \
389 stats.total, \
390 stats.active, \
391 stats.inactive, \
392 stats.global, \
393 stats.shared, \
394 stats.unbound); \
395} while (0)
493018dc
BV		 396
397static void print_batch_pool_stats(struct seq_file *m,
398 struct drm_i915_private *dev_priv)
399{
400 struct drm_i915_gem_object *obj;
401 struct file_stats stats;
06fbca71 402 struct intel_engine_cs *ring;
8d9d5744 403 int i, j;
493018dc
BV		 404
405 memset(&stats, 0, sizeof(stats));
406
06fbca71 407 for_each_ring(ring, dev_priv, i) {
8d9d5744
CW		 408 for (j = 0; j < ARRAY_SIZE(ring->batch_pool.cache_list); j++) {
409 list_for_each_entry(obj,
410 &ring->batch_pool.cache_list[j],
411 batch_pool_link)
412 per_file_stats(0, obj, &stats);
413 }
06fbca71 414 }
493018dc 415
b0da1b79 416 print_file_stats(m, "[k]batch pool", stats);
493018dc
BV		 417}
418
ca191b13
BW		 419#define count_vmas(list, member) do { \
420 list_for_each_entry(vma, list, member) { \
ca1543be 421 size += i915_gem_obj_total_ggtt_size(vma->obj); \
ca191b13
BW		 422 ++count; \
423 if (vma->obj->map_and_fenceable) { \
424 mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
425 ++mappable_count; \
426 } \
427 } \
428} while (0)
429
430static int i915_gem_object_info(struct seq_file *m, void* data)
73aa808f 431{
9f25d007 432 struct drm_info_node *node = m->private;
73aa808f
CW		 433 struct drm_device *dev = node->minor->dev;
434 struct drm_i915_private *dev_priv = dev->dev_private;
b7abb714 435 u32 count, mappable_count, purgeable_count;
c44ef60e 436 u64 size, mappable_size, purgeable_size;
6299f992 437 struct drm_i915_gem_object *obj;
5cef07e1 438 struct i915_address_space *vm = &dev_priv->gtt.base;
2db8e9d6 439 struct drm_file *file;
ca191b13 440 struct i915_vma *vma;
73aa808f
CW		 441 int ret;
442
443 ret = mutex_lock_interruptible(&dev->struct_mutex);
444 if (ret)
445 return ret;
446
6299f992
CW		 447 seq_printf(m, "%u objects, %zu bytes\n",
448 dev_priv->mm.object_count,
449 dev_priv->mm.object_memory);
450
451 size = count = mappable_size = mappable_count = 0;
35c20a60 452 count_objects(&dev_priv->mm.bound_list, global_list);
c44ef60e 453 seq_printf(m, "%u [%u] objects, %llu [%llu] bytes in gtt\n",
6299f992
CW		 454 count, mappable_count, size, mappable_size);
455
456 size = count = mappable_size = mappable_count = 0;
ca191b13 457 count_vmas(&vm->active_list, mm_list);
c44ef60e 458 seq_printf(m, " %u [%u] active objects, %llu [%llu] bytes\n",
6299f992
CW		 459 count, mappable_count, size, mappable_size);
460
6299f992 461 size = count = mappable_size = mappable_count = 0;
ca191b13 462 count_vmas(&vm->inactive_list, mm_list);
c44ef60e 463 seq_printf(m, " %u [%u] inactive objects, %llu [%llu] bytes\n",
6299f992
CW		 464 count, mappable_count, size, mappable_size);
465
b7abb714 466 size = count = purgeable_size = purgeable_count = 0;
35c20a60 467 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
6c085a72 468 size += obj->base.size, ++count;
b7abb714
CW		 469 if (obj->madv == I915_MADV_DONTNEED)
470 purgeable_size += obj->base.size, ++purgeable_count;
471 }
c44ef60e 472 seq_printf(m, "%u unbound objects, %llu bytes\n", count, size);
6c085a72 473
6299f992 474 size = count = mappable_size = mappable_count = 0;
35c20a60 475 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
6299f992 476 if (obj->fault_mappable) {
f343c5f6 477 size += i915_gem_obj_ggtt_size(obj);
6299f992
CW		 478 ++count;
479 }
30154650 480 if (obj->pin_display) {
f343c5f6 481 mappable_size += i915_gem_obj_ggtt_size(obj);
6299f992
CW		 482 ++mappable_count;
483 }
b7abb714
CW		 484 if (obj->madv == I915_MADV_DONTNEED) {
485 purgeable_size += obj->base.size;
486 ++purgeable_count;
487 }
6299f992 488 }
c44ef60e 489 seq_printf(m, "%u purgeable objects, %llu bytes\n",
b7abb714 490 purgeable_count, purgeable_size);
c44ef60e 491 seq_printf(m, "%u pinned mappable objects, %llu bytes\n",
6299f992 492 mappable_count, mappable_size);
c44ef60e 493 seq_printf(m, "%u fault mappable objects, %llu bytes\n",
6299f992
CW		 494 count, size);
495
c44ef60e 496 seq_printf(m, "%llu [%llu] gtt total\n",
853ba5d2 497 dev_priv->gtt.base.total,
c44ef60e 498 (u64)dev_priv->gtt.mappable_end - dev_priv->gtt.base.start);
73aa808f 499
493018dc
BV		 500 seq_putc(m, '\n');
501 print_batch_pool_stats(m, dev_priv);
2db8e9d6
CW		 502 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
503 struct file_stats stats;
3ec2f427 504 struct task_struct *task;
2db8e9d6
CW		 505
506 memset(&stats, 0, sizeof(stats));
6313c204 507 stats.file_priv = file->driver_priv;
5b5ffff0 508 spin_lock(&file->table_lock);
2db8e9d6 509 idr_for_each(&file->object_idr, per_file_stats, &stats);
5b5ffff0 510 spin_unlock(&file->table_lock);
3ec2f427
TH		 511 /*
512 * Although we have a valid reference on file->pid, that does
513 * not guarantee that the task_struct who called get_pid() is
514 * still alive (e.g. get_pid(current) => fork() => exit()).
515 * Therefore, we need to protect this ->comm access using RCU.
516 */
517 rcu_read_lock();
518 task = pid_task(file->pid, PIDTYPE_PID);
493018dc 519 print_file_stats(m, task ? task->comm : "<unknown>", stats);
3ec2f427 520 rcu_read_unlock();
2db8e9d6
CW		 521 }
522
73aa808f
CW		 523 mutex_unlock(&dev->struct_mutex);
524
525 return 0;
526}
527
aee56cff 528static int i915_gem_gtt_info(struct seq_file *m, void *data)
08c18323 529{
9f25d007 530 struct drm_info_node *node = m->private;
08c18323 531 struct drm_device *dev = node->minor->dev;
1b50247a 532 uintptr_t list = (uintptr_t) node->info_ent->data;
08c18323
CW		 533 struct drm_i915_private *dev_priv = dev->dev_private;
534 struct drm_i915_gem_object *obj;
c44ef60e 535 u64 total_obj_size, total_gtt_size;
08c18323
CW		 536 int count, ret;
537
538 ret = mutex_lock_interruptible(&dev->struct_mutex);
539 if (ret)
540 return ret;
541
542 total_obj_size = total_gtt_size = count = 0;
35c20a60 543 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
d7f46fc4 544 if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj))
1b50247a
CW		 545 continue;
546
267f0c90 547 seq_puts(m, " ");
08c18323 548 describe_obj(m, obj);
267f0c90 549 seq_putc(m, '\n');
08c18323 550 total_obj_size += obj->base.size;
ca1543be 551 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
08c18323
CW		 552 count++;
553 }
554
555 mutex_unlock(&dev->struct_mutex);
556
c44ef60e 557 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
08c18323
CW		 558 count, total_obj_size, total_gtt_size);
559
560 return 0;
561}
562
4e5359cd
SF		 563static int i915_gem_pageflip_info(struct seq_file *m, void *data)
564{
9f25d007 565 struct drm_info_node *node = m->private;
4e5359cd 566 struct drm_device *dev = node->minor->dev;
d6bbafa1 567 struct drm_i915_private *dev_priv = dev->dev_private;
4e5359cd 568 struct intel_crtc *crtc;
8a270ebf
DV		 569 int ret;
570
571 ret = mutex_lock_interruptible(&dev->struct_mutex);
572 if (ret)
573 return ret;
4e5359cd 574
d3fcc808 575 for_each_intel_crtc(dev, crtc) {
9db4a9c7
JB		 576 const char pipe = pipe_name(crtc->pipe);
577 const char plane = plane_name(crtc->plane);
4e5359cd
SF		 578 struct intel_unpin_work *work;
579
5e2d7afc 580 spin_lock_irq(&dev->event_lock);
4e5359cd
SF		 581 work = crtc->unpin_work;
582 if (work == NULL) {
9db4a9c7 583 seq_printf(m, "No flip due on pipe %c (plane %c)\n",
4e5359cd
SF		 584 pipe, plane);
585 } else {
d6bbafa1
CW		 586 u32 addr;
587
e7d841ca 588 if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9db4a9c7 589 seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
4e5359cd
SF		 590 pipe, plane);
591 } else {
9db4a9c7 592 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
4e5359cd
SF		 593 pipe, plane);
594 }
3a8a946e
DV		 595 if (work->flip_queued_req) {
596 struct intel_engine_cs *ring =
597 i915_gem_request_get_ring(work->flip_queued_req);
598
20e28fba 599 seq_printf(m, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n",
3a8a946e 600 ring->name,
f06cc1b9 601 i915_gem_request_get_seqno(work->flip_queued_req),
d6bbafa1 602 dev_priv->next_seqno,
3a8a946e 603 ring->get_seqno(ring, true),
1b5a433a 604 i915_gem_request_completed(work->flip_queued_req, true));
d6bbafa1
CW		 605 } else
606 seq_printf(m, "Flip not associated with any ring\n");
607 seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
608 work->flip_queued_vblank,
609 work->flip_ready_vblank,
1e3feefd 610 drm_crtc_vblank_count(&crtc->base));
4e5359cd 611 if (work->enable_stall_check)
267f0c90 612 seq_puts(m, "Stall check enabled, ");
4e5359cd 613 else
267f0c90 614 seq_puts(m, "Stall check waiting for page flip ioctl, ");
e7d841ca 615 seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
4e5359cd 616
d6bbafa1
CW		 617 if (INTEL_INFO(dev)->gen >= 4)
618 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane)));
619 else
620 addr = I915_READ(DSPADDR(crtc->plane));
621 seq_printf(m, "Current scanout address 0x%08x\n", addr);
622
4e5359cd 623 if (work->pending_flip_obj) {
d6bbafa1
CW		 624 seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset);
625 seq_printf(m, "MMIO update completed? %d\n", addr == work->gtt_offset);
4e5359cd
SF		 626 }
627 }
5e2d7afc 628 spin_unlock_irq(&dev->event_lock);
4e5359cd
SF		 629 }
630
8a270ebf
DV		 631 mutex_unlock(&dev->struct_mutex);
632
4e5359cd
SF		 633 return 0;
634}
635
493018dc
BV		 636static int i915_gem_batch_pool_info(struct seq_file *m, void *data)
637{
638 struct drm_info_node *node = m->private;
639 struct drm_device *dev = node->minor->dev;
640 struct drm_i915_private *dev_priv = dev->dev_private;
641 struct drm_i915_gem_object *obj;
06fbca71 642 struct intel_engine_cs *ring;
8d9d5744
CW		 643 int total = 0;
644 int ret, i, j;
493018dc
BV		 645
646 ret = mutex_lock_interruptible(&dev->struct_mutex);
647 if (ret)
648 return ret;
649
06fbca71 650 for_each_ring(ring, dev_priv, i) {
8d9d5744
CW		 651 for (j = 0; j < ARRAY_SIZE(ring->batch_pool.cache_list); j++) {
652 int count;
653
654 count = 0;
655 list_for_each_entry(obj,
656 &ring->batch_pool.cache_list[j],
657 batch_pool_link)
658 count++;
659 seq_printf(m, "%s cache[%d]: %d objects\n",
660 ring->name, j, count);
661
662 list_for_each_entry(obj,
663 &ring->batch_pool.cache_list[j],
664 batch_pool_link) {
665 seq_puts(m, " ");
666 describe_obj(m, obj);
667 seq_putc(m, '\n');
668 }
669
670 total += count;
06fbca71 671 }
493018dc
BV		 672 }
673
8d9d5744 674 seq_printf(m, "total: %d\n", total);
493018dc
BV		 675
676 mutex_unlock(&dev->struct_mutex);
677
678 return 0;
679}
680
2017263e
BG		 681static int i915_gem_request_info(struct seq_file *m, void *data)
682{
9f25d007 683 struct drm_info_node *node = m->private;
2017263e 684 struct drm_device *dev = node->minor->dev;
e277a1f8 685 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 686 struct intel_engine_cs *ring;
eed29a5b 687 struct drm_i915_gem_request *req;
2d1070b2 688 int ret, any, i;
de227ef0
CW		 689
690 ret = mutex_lock_interruptible(&dev->struct_mutex);
691 if (ret)
692 return ret;
2017263e 693
2d1070b2 694 any = 0;
a2c7f6fd 695 for_each_ring(ring, dev_priv, i) {
2d1070b2
CW		 696 int count;
697
698 count = 0;
eed29a5b 699 list_for_each_entry(req, &ring->request_list, list)
2d1070b2
CW		 700 count++;
701 if (count == 0)
a2c7f6fd
CW		 702 continue;
703
2d1070b2 704 seq_printf(m, "%s requests: %d\n", ring->name, count);
eed29a5b 705 list_for_each_entry(req, &ring->request_list, list) {
2d1070b2
CW		 706 struct task_struct *task;
707
708 rcu_read_lock();
709 task = NULL;
eed29a5b
DV		 710 if (req->pid)
711 task = pid_task(req->pid, PIDTYPE_PID);
2d1070b2 712 seq_printf(m, " %x @ %d: %s [%d]\n",
eed29a5b
DV		 713 req->seqno,
714 (int) (jiffies - req->emitted_jiffies),
2d1070b2
CW		 715 task ? task->comm : "<unknown>",
716 task ? task->pid : -1);
717 rcu_read_unlock();
c2c347a9 718 }
2d1070b2
CW		 719
720 any++;
2017263e 721 }
de227ef0
CW		 722 mutex_unlock(&dev->struct_mutex);
723
2d1070b2 724 if (any == 0)
267f0c90 725 seq_puts(m, "No requests\n");
c2c347a9 726
2017263e
BG		 727 return 0;
728}
729
b2223497 730static void i915_ring_seqno_info(struct seq_file *m,
a4872ba6 731 struct intel_engine_cs *ring)
b2223497
CW		 732{
733 if (ring->get_seqno) {
20e28fba 734 seq_printf(m, "Current sequence (%s): %x\n",
b2eadbc8 735 ring->name, ring->get_seqno(ring, false));
b2223497
CW		 736 }
737}
738
2017263e
BG		 739static int i915_gem_seqno_info(struct seq_file *m, void *data)
740{
9f25d007 741 struct drm_info_node *node = m->private;
2017263e 742 struct drm_device *dev = node->minor->dev;
e277a1f8 743 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 744 struct intel_engine_cs *ring;
1ec14ad3 745 int ret, i;
de227ef0
CW		 746
747 ret = mutex_lock_interruptible(&dev->struct_mutex);
748 if (ret)
749 return ret;
c8c8fb33 750 intel_runtime_pm_get(dev_priv);
2017263e 751
a2c7f6fd
CW		 752 for_each_ring(ring, dev_priv, i)
753 i915_ring_seqno_info(m, ring);
de227ef0 754
c8c8fb33 755 intel_runtime_pm_put(dev_priv);
de227ef0
CW		 756 mutex_unlock(&dev->struct_mutex);
757
2017263e
BG		 758 return 0;
759}
760
761
762static int i915_interrupt_info(struct seq_file *m, void *data)
763{
9f25d007 764 struct drm_info_node *node = m->private;
2017263e 765 struct drm_device *dev = node->minor->dev;
e277a1f8 766 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 767 struct intel_engine_cs *ring;
9db4a9c7 768 int ret, i, pipe;
de227ef0
CW		 769
770 ret = mutex_lock_interruptible(&dev->struct_mutex);
771 if (ret)
772 return ret;
c8c8fb33 773 intel_runtime_pm_get(dev_priv);
2017263e 774
74e1ca8c 775 if (IS_CHERRYVIEW(dev)) {
74e1ca8c
VS		 776 seq_printf(m, "Master Interrupt Control:\t%08x\n",
777 I915_READ(GEN8_MASTER_IRQ));
778
779 seq_printf(m, "Display IER:\t%08x\n",
780 I915_READ(VLV_IER));
781 seq_printf(m, "Display IIR:\t%08x\n",
782 I915_READ(VLV_IIR));
783 seq_printf(m, "Display IIR_RW:\t%08x\n",
784 I915_READ(VLV_IIR_RW));
785 seq_printf(m, "Display IMR:\t%08x\n",
786 I915_READ(VLV_IMR));
055e393f 787 for_each_pipe(dev_priv, pipe)
74e1ca8c
VS		 788 seq_printf(m, "Pipe %c stat:\t%08x\n",
789 pipe_name(pipe),
790 I915_READ(PIPESTAT(pipe)));
791
792 seq_printf(m, "Port hotplug:\t%08x\n",
793 I915_READ(PORT_HOTPLUG_EN));
794 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
795 I915_READ(VLV_DPFLIPSTAT));
796 seq_printf(m, "DPINVGTT:\t%08x\n",
797 I915_READ(DPINVGTT));
798
799 for (i = 0; i < 4; i++) {
800 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
801 i, I915_READ(GEN8_GT_IMR(i)));
802 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
803 i, I915_READ(GEN8_GT_IIR(i)));
804 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
805 i, I915_READ(GEN8_GT_IER(i)));
806 }
807
808 seq_printf(m, "PCU interrupt mask:\t%08x\n",
809 I915_READ(GEN8_PCU_IMR));
810 seq_printf(m, "PCU interrupt identity:\t%08x\n",
811 I915_READ(GEN8_PCU_IIR));
812 seq_printf(m, "PCU interrupt enable:\t%08x\n",
813 I915_READ(GEN8_PCU_IER));
814 } else if (INTEL_INFO(dev)->gen >= 8) {
a123f157
BW		 815 seq_printf(m, "Master Interrupt Control:\t%08x\n",
816 I915_READ(GEN8_MASTER_IRQ));
817
818 for (i = 0; i < 4; i++) {
819 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
820 i, I915_READ(GEN8_GT_IMR(i)));
821 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
822 i, I915_READ(GEN8_GT_IIR(i)));
823 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
824 i, I915_READ(GEN8_GT_IER(i)));
825 }
826
055e393f 827 for_each_pipe(dev_priv, pipe) {
f458ebbc 828 if (!intel_display_power_is_enabled(dev_priv,
22c59960
PZ		 829 POWER_DOMAIN_PIPE(pipe))) {
830 seq_printf(m, "Pipe %c power disabled\n",
831 pipe_name(pipe));
832 continue;
833 }
a123f157 834 seq_printf(m, "Pipe %c IMR:\t%08x\n",
07d27e20
DL		 835 pipe_name(pipe),
836 I915_READ(GEN8_DE_PIPE_IMR(pipe)));
a123f157 837 seq_printf(m, "Pipe %c IIR:\t%08x\n",
07d27e20
DL		 838 pipe_name(pipe),
839 I915_READ(GEN8_DE_PIPE_IIR(pipe)));
a123f157 840 seq_printf(m, "Pipe %c IER:\t%08x\n",
07d27e20
DL		 841 pipe_name(pipe),
842 I915_READ(GEN8_DE_PIPE_IER(pipe)));
a123f157
BW		 843 }
844
845 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
846 I915_READ(GEN8_DE_PORT_IMR));
847 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
848 I915_READ(GEN8_DE_PORT_IIR));
849 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
850 I915_READ(GEN8_DE_PORT_IER));
851
852 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
853 I915_READ(GEN8_DE_MISC_IMR));
854 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
855 I915_READ(GEN8_DE_MISC_IIR));
856 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
857 I915_READ(GEN8_DE_MISC_IER));
858
859 seq_printf(m, "PCU interrupt mask:\t%08x\n",
860 I915_READ(GEN8_PCU_IMR));
861 seq_printf(m, "PCU interrupt identity:\t%08x\n",
862 I915_READ(GEN8_PCU_IIR));
863 seq_printf(m, "PCU interrupt enable:\t%08x\n",
864 I915_READ(GEN8_PCU_IER));
865 } else if (IS_VALLEYVIEW(dev)) {
7e231dbe
JB		 866 seq_printf(m, "Display IER:\t%08x\n",
867 I915_READ(VLV_IER));
868 seq_printf(m, "Display IIR:\t%08x\n",
869 I915_READ(VLV_IIR));
870 seq_printf(m, "Display IIR_RW:\t%08x\n",
871 I915_READ(VLV_IIR_RW));
872 seq_printf(m, "Display IMR:\t%08x\n",
873 I915_READ(VLV_IMR));
055e393f 874 for_each_pipe(dev_priv, pipe)
7e231dbe
JB		 875 seq_printf(m, "Pipe %c stat:\t%08x\n",
876 pipe_name(pipe),
877 I915_READ(PIPESTAT(pipe)));
878
879 seq_printf(m, "Master IER:\t%08x\n",
880 I915_READ(VLV_MASTER_IER));
881
882 seq_printf(m, "Render IER:\t%08x\n",
883 I915_READ(GTIER));
884 seq_printf(m, "Render IIR:\t%08x\n",
885 I915_READ(GTIIR));
886 seq_printf(m, "Render IMR:\t%08x\n",
887 I915_READ(GTIMR));
888
889 seq_printf(m, "PM IER:\t\t%08x\n",
890 I915_READ(GEN6_PMIER));
891 seq_printf(m, "PM IIR:\t\t%08x\n",
892 I915_READ(GEN6_PMIIR));
893 seq_printf(m, "PM IMR:\t\t%08x\n",
894 I915_READ(GEN6_PMIMR));
895
896 seq_printf(m, "Port hotplug:\t%08x\n",
897 I915_READ(PORT_HOTPLUG_EN));
898 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
899 I915_READ(VLV_DPFLIPSTAT));
900 seq_printf(m, "DPINVGTT:\t%08x\n",
901 I915_READ(DPINVGTT));
902
903 } else if (!HAS_PCH_SPLIT(dev)) {
5f6a1695
ZW		 904 seq_printf(m, "Interrupt enable: %08x\n",
905 I915_READ(IER));
906 seq_printf(m, "Interrupt identity: %08x\n",
907 I915_READ(IIR));
908 seq_printf(m, "Interrupt mask: %08x\n",
909 I915_READ(IMR));
055e393f 910 for_each_pipe(dev_priv, pipe)
9db4a9c7
JB		 911 seq_printf(m, "Pipe %c stat: %08x\n",
912 pipe_name(pipe),
913 I915_READ(PIPESTAT(pipe)));
5f6a1695
ZW		 914 } else {
915 seq_printf(m, "North Display Interrupt enable: %08x\n",
916 I915_READ(DEIER));
917 seq_printf(m, "North Display Interrupt identity: %08x\n",
918 I915_READ(DEIIR));
919 seq_printf(m, "North Display Interrupt mask: %08x\n",
920 I915_READ(DEIMR));
921 seq_printf(m, "South Display Interrupt enable: %08x\n",
922 I915_READ(SDEIER));
923 seq_printf(m, "South Display Interrupt identity: %08x\n",
924 I915_READ(SDEIIR));
925 seq_printf(m, "South Display Interrupt mask: %08x\n",
926 I915_READ(SDEIMR));
927 seq_printf(m, "Graphics Interrupt enable: %08x\n",
928 I915_READ(GTIER));
929 seq_printf(m, "Graphics Interrupt identity: %08x\n",
930 I915_READ(GTIIR));
931 seq_printf(m, "Graphics Interrupt mask: %08x\n",
932 I915_READ(GTIMR));
933 }
a2c7f6fd 934 for_each_ring(ring, dev_priv, i) {
a123f157 935 if (INTEL_INFO(dev)->gen >= 6) {
a2c7f6fd
CW		 936 seq_printf(m,
937 "Graphics Interrupt mask (%s): %08x\n",
938 ring->name, I915_READ_IMR(ring));
9862e600 939 }
a2c7f6fd 940 i915_ring_seqno_info(m, ring);
9862e600 941 }
c8c8fb33 942 intel_runtime_pm_put(dev_priv);
de227ef0
CW		 943 mutex_unlock(&dev->struct_mutex);
944
2017263e
BG		 945 return 0;
946}
947
a6172a80
CW		 948static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
949{
9f25d007 950 struct drm_info_node *node = m->private;
a6172a80 951 struct drm_device *dev = node->minor->dev;
e277a1f8 952 struct drm_i915_private *dev_priv = dev->dev_private;
de227ef0
CW		 953 int i, ret;
954
955 ret = mutex_lock_interruptible(&dev->struct_mutex);
956 if (ret)
957 return ret;
a6172a80 958
a6172a80
CW		 959 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
960 for (i = 0; i < dev_priv->num_fence_regs; i++) {
05394f39 961 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
a6172a80 962
6c085a72
CW		 963 seq_printf(m, "Fence %d, pin count = %d, object = ",
964 i, dev_priv->fence_regs[i].pin_count);
c2c347a9 965 if (obj == NULL)
267f0c90 966 seq_puts(m, "unused");
c2c347a9 967 else
05394f39 968 describe_obj(m, obj);
267f0c90 969 seq_putc(m, '\n');
a6172a80
CW		 970 }
971
05394f39 972 mutex_unlock(&dev->struct_mutex);
a6172a80
CW		 973 return 0;
974}
975
2017263e
BG		 976static int i915_hws_info(struct seq_file *m, void *data)
977{
9f25d007 978 struct drm_info_node *node = m->private;
2017263e 979 struct drm_device *dev = node->minor->dev;
e277a1f8 980 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 981 struct intel_engine_cs *ring;
1a240d4d 982 const u32 *hws;
4066c0ae
CW		 983 int i;
984
1ec14ad3 985 ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
1a240d4d 986 hws = ring->status_page.page_addr;
2017263e
BG		 987 if (hws == NULL)
988 return 0;
989
990 for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
991 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
992 i * 4,
993 hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
994 }
995 return 0;
996}
997
d5442303
DV		 998static ssize_t
999i915_error_state_write(struct file *filp,
1000 const char __user *ubuf,
1001 size_t cnt,
1002 loff_t *ppos)
1003{
edc3d884 1004 struct i915_error_state_file_priv *error_priv = filp->private_data;
d5442303 1005 struct drm_device *dev = error_priv->dev;
22bcfc6a 1006 int ret;
d5442303
DV		 1007
1008 DRM_DEBUG_DRIVER("Resetting error state\n");
1009
22bcfc6a
DV		 1010 ret = mutex_lock_interruptible(&dev->struct_mutex);
1011 if (ret)
1012 return ret;
1013
d5442303
DV		 1014 i915_destroy_error_state(dev);
1015 mutex_unlock(&dev->struct_mutex);
1016
1017 return cnt;
1018}
1019
1020static int i915_error_state_open(struct inode *inode, struct file *file)
1021{
1022 struct drm_device *dev = inode->i_private;
d5442303 1023 struct i915_error_state_file_priv *error_priv;
d5442303
DV		 1024
1025 error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
1026 if (!error_priv)
1027 return -ENOMEM;
1028
1029 error_priv->dev = dev;
1030
95d5bfb3 1031 i915_error_state_get(dev, error_priv);
d5442303 1032
edc3d884
MK		 1033 file->private_data = error_priv;
1034
1035 return 0;
d5442303
DV		 1036}
1037
1038static int i915_error_state_release(struct inode *inode, struct file *file)
1039{
edc3d884 1040 struct i915_error_state_file_priv *error_priv = file->private_data;
d5442303 1041
95d5bfb3 1042 i915_error_state_put(error_priv);
d5442303
DV		 1043 kfree(error_priv);
1044
edc3d884
MK		 1045 return 0;
1046}
1047
4dc955f7
MK		 1048static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
1049 size_t count, loff_t *pos)
1050{
1051 struct i915_error_state_file_priv *error_priv = file->private_data;
1052 struct drm_i915_error_state_buf error_str;
1053 loff_t tmp_pos = 0;
1054 ssize_t ret_count = 0;
1055 int ret;
1056
0a4cd7c8 1057 ret = i915_error_state_buf_init(&error_str, to_i915(error_priv->dev), count, *pos);
4dc955f7
MK		 1058 if (ret)
1059 return ret;
edc3d884 1060
fc16b48b 1061 ret = i915_error_state_to_str(&error_str, error_priv);
edc3d884
MK		 1062 if (ret)
1063 goto out;
1064
edc3d884
MK		 1065 ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
1066 error_str.buf,
1067 error_str.bytes);
1068
1069 if (ret_count < 0)
1070 ret = ret_count;
1071 else
1072 *pos = error_str.start + ret_count;
1073out:
4dc955f7 1074 i915_error_state_buf_release(&error_str);
edc3d884 1075 return ret ?: ret_count;
d5442303
DV		 1076}
1077
1078static const struct file_operations i915_error_state_fops = {
1079 .owner = THIS_MODULE,
1080 .open = i915_error_state_open,
edc3d884 1081 .read = i915_error_state_read,
d5442303
DV		 1082 .write = i915_error_state_write,
1083 .llseek = default_llseek,
1084 .release = i915_error_state_release,
1085};
1086
647416f9
KC		 1087static int
1088i915_next_seqno_get(void *data, u64 *val)
40633219 1089{
647416f9 1090 struct drm_device *dev = data;
e277a1f8 1091 struct drm_i915_private *dev_priv = dev->dev_private;
40633219
MK		 1092 int ret;
1093
1094 ret = mutex_lock_interruptible(&dev->struct_mutex);
1095 if (ret)
1096 return ret;
1097
647416f9 1098 *val = dev_priv->next_seqno;
40633219
MK		 1099 mutex_unlock(&dev->struct_mutex);
1100
647416f9 1101 return 0;
40633219
MK		 1102}
1103
647416f9
KC		 1104static int
1105i915_next_seqno_set(void *data, u64 val)
1106{
1107 struct drm_device *dev = data;
40633219
MK		 1108 int ret;
1109
40633219
MK		 1110 ret = mutex_lock_interruptible(&dev->struct_mutex);
1111 if (ret)
1112 return ret;
1113
e94fbaa8 1114 ret = i915_gem_set_seqno(dev, val);
40633219
MK		 1115 mutex_unlock(&dev->struct_mutex);
1116
647416f9 1117 return ret;
40633219
MK		 1118}
1119
647416f9
KC		 1120DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
1121 i915_next_seqno_get, i915_next_seqno_set,
3a3b4f98 1122 "0x%llx\n");
40633219 1123
adb4bd12 1124static int i915_frequency_info(struct seq_file *m, void *unused)
f97108d1 1125{
9f25d007 1126 struct drm_info_node *node = m->private;
f97108d1 1127 struct drm_device *dev = node->minor->dev;
e277a1f8 1128 struct drm_i915_private *dev_priv = dev->dev_private;
c8c8fb33
PZ		 1129 int ret = 0;
1130
1131 intel_runtime_pm_get(dev_priv);
3b8d8d91 1132
5c9669ce
TR		 1133 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1134
3b8d8d91
JB		 1135 if (IS_GEN5(dev)) {
1136 u16 rgvswctl = I915_READ16(MEMSWCTL);
1137 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1138
1139 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1140 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1141 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1142 MEMSTAT_VID_SHIFT);
1143 seq_printf(m, "Current P-state: %d\n",
1144 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
666a4537
WB		 1145 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1146 u32 freq_sts;
1147
1148 mutex_lock(&dev_priv->rps.hw_lock);
1149 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
1150 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1151 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1152
1153 seq_printf(m, "actual GPU freq: %d MHz\n",
1154 intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
1155
1156 seq_printf(m, "current GPU freq: %d MHz\n",
1157 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1158
1159 seq_printf(m, "max GPU freq: %d MHz\n",
1160 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1161
1162 seq_printf(m, "min GPU freq: %d MHz\n",
1163 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1164
1165 seq_printf(m, "idle GPU freq: %d MHz\n",
1166 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1167
1168 seq_printf(m,
1169 "efficient (RPe) frequency: %d MHz\n",
1170 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1171 mutex_unlock(&dev_priv->rps.hw_lock);
1172 } else if (INTEL_INFO(dev)->gen >= 6) {
35040562
BP		 1173 u32 rp_state_limits;
1174 u32 gt_perf_status;
1175 u32 rp_state_cap;
0d8f9491 1176 u32 rpmodectl, rpinclimit, rpdeclimit;
8e8c06cd 1177 u32 rpstat, cagf, reqf;
ccab5c82
JB		 1178 u32 rpupei, rpcurup, rpprevup;
1179 u32 rpdownei, rpcurdown, rpprevdown;
9dd3c605 1180 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
3b8d8d91
JB		 1181 int max_freq;
1182
35040562
BP		 1183 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1184 if (IS_BROXTON(dev)) {
1185 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
1186 gt_perf_status = I915_READ(BXT_GT_PERF_STATUS);
1187 } else {
1188 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
1189 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1190 }
1191
3b8d8d91 1192 /* RPSTAT1 is in the GT power well */
d1ebd816
BW		 1193 ret = mutex_lock_interruptible(&dev->struct_mutex);
1194 if (ret)
c8c8fb33 1195 goto out;
d1ebd816 1196
59bad947 1197 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
3b8d8d91 1198
8e8c06cd 1199 reqf = I915_READ(GEN6_RPNSWREQ);
60260a5b
AG		 1200 if (IS_GEN9(dev))
1201 reqf >>= 23;
1202 else {
1203 reqf &= ~GEN6_TURBO_DISABLE;
1204 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1205 reqf >>= 24;
1206 else
1207 reqf >>= 25;
1208 }
7c59a9c1 1209 reqf = intel_gpu_freq(dev_priv, reqf);
8e8c06cd 1210
0d8f9491
CW		 1211 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1212 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1213 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1214
ccab5c82
JB		 1215 rpstat = I915_READ(GEN6_RPSTAT1);
1216 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
1217 rpcurup = I915_READ(GEN6_RP_CUR_UP);
1218 rpprevup = I915_READ(GEN6_RP_PREV_UP);
1219 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
1220 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
1221 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
60260a5b
AG		 1222 if (IS_GEN9(dev))
1223 cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
1224 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
f82855d3
BW		 1225 cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1226 else
1227 cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
7c59a9c1 1228 cagf = intel_gpu_freq(dev_priv, cagf);
ccab5c82 1229
59bad947 1230 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
d1ebd816
BW		 1231 mutex_unlock(&dev->struct_mutex);
1232
9dd3c605
PZ		 1233 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1234 pm_ier = I915_READ(GEN6_PMIER);
1235 pm_imr = I915_READ(GEN6_PMIMR);
1236 pm_isr = I915_READ(GEN6_PMISR);
1237 pm_iir = I915_READ(GEN6_PMIIR);
1238 pm_mask = I915_READ(GEN6_PMINTRMSK);
1239 } else {
1240 pm_ier = I915_READ(GEN8_GT_IER(2));
1241 pm_imr = I915_READ(GEN8_GT_IMR(2));
1242 pm_isr = I915_READ(GEN8_GT_ISR(2));
1243 pm_iir = I915_READ(GEN8_GT_IIR(2));
1244 pm_mask = I915_READ(GEN6_PMINTRMSK);
1245 }
0d8f9491 1246 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
9dd3c605 1247 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
3b8d8d91 1248 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
3b8d8d91 1249 seq_printf(m, "Render p-state ratio: %d\n",
60260a5b 1250 (gt_perf_status & (IS_GEN9(dev) ? 0x1ff00 : 0xff00)) >> 8);
3b8d8d91
JB		 1251 seq_printf(m, "Render p-state VID: %d\n",
1252 gt_perf_status & 0xff);
1253 seq_printf(m, "Render p-state limit: %d\n",
1254 rp_state_limits & 0xff);
0d8f9491
CW		 1255 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1256 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1257 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1258 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
8e8c06cd 1259 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
f82855d3 1260 seq_printf(m, "CAGF: %dMHz\n", cagf);
ccab5c82
JB		 1261 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
1262 GEN6_CURICONT_MASK);
1263 seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
1264 GEN6_CURBSYTAVG_MASK);
1265 seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
1266 GEN6_CURBSYTAVG_MASK);
d86ed34a
CW		 1267 seq_printf(m, "Up threshold: %d%%\n",
1268 dev_priv->rps.up_threshold);
1269
ccab5c82
JB		 1270 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
1271 GEN6_CURIAVG_MASK);
1272 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
1273 GEN6_CURBSYTAVG_MASK);
1274 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
1275 GEN6_CURBSYTAVG_MASK);
d86ed34a
CW		 1276 seq_printf(m, "Down threshold: %d%%\n",
1277 dev_priv->rps.down_threshold);
3b8d8d91 1278
35040562
BP		 1279 max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 0 :
1280 rp_state_cap >> 16) & 0xff;
ef11bdb3
RV		 1281 max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1282 GEN9_FREQ_SCALER : 1);
3b8d8d91 1283 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
7c59a9c1 1284 intel_gpu_freq(dev_priv, max_freq));
3b8d8d91
JB		 1285
1286 max_freq = (rp_state_cap & 0xff00) >> 8;
ef11bdb3
RV		 1287 max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1288 GEN9_FREQ_SCALER : 1);
3b8d8d91 1289 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
7c59a9c1 1290 intel_gpu_freq(dev_priv, max_freq));
3b8d8d91 1291
35040562
BP		 1292 max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 16 :
1293 rp_state_cap >> 0) & 0xff;
ef11bdb3
RV		 1294 max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1295 GEN9_FREQ_SCALER : 1);
3b8d8d91 1296 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
7c59a9c1 1297 intel_gpu_freq(dev_priv, max_freq));
31c77388 1298 seq_printf(m, "Max overclocked frequency: %dMHz\n",
7c59a9c1 1299 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
aed242ff 1300
d86ed34a
CW		 1301 seq_printf(m, "Current freq: %d MHz\n",
1302 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1303 seq_printf(m, "Actual freq: %d MHz\n", cagf);
aed242ff
CW		 1304 seq_printf(m, "Idle freq: %d MHz\n",
1305 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
d86ed34a
CW		 1306 seq_printf(m, "Min freq: %d MHz\n",
1307 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1308 seq_printf(m, "Max freq: %d MHz\n",
1309 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1310 seq_printf(m,
1311 "efficient (RPe) frequency: %d MHz\n",
1312 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
3b8d8d91 1313 } else {
267f0c90 1314 seq_puts(m, "no P-state info available\n");
3b8d8d91 1315 }
f97108d1 1316
1170f28c
MK		 1317 seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk_freq);
1318 seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq);
1319 seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq);
1320
c8c8fb33
PZ		 1321out:
1322 intel_runtime_pm_put(dev_priv);
1323 return ret;
f97108d1
JB		 1324}
1325
f654449a
CW		 1326static int i915_hangcheck_info(struct seq_file *m, void *unused)
1327{
1328 struct drm_info_node *node = m->private;
ebbc7546
MK		 1329 struct drm_device *dev = node->minor->dev;
1330 struct drm_i915_private *dev_priv = dev->dev_private;
f654449a 1331 struct intel_engine_cs *ring;
ebbc7546
MK		 1332 u64 acthd[I915_NUM_RINGS];
1333 u32 seqno[I915_NUM_RINGS];
61642ff0
MK		 1334 u32 instdone[I915_NUM_INSTDONE_REG];
1335 int i, j;
f654449a
CW		 1336
1337 if (!i915.enable_hangcheck) {
1338 seq_printf(m, "Hangcheck disabled\n");
1339 return 0;
1340 }
1341
ebbc7546
MK		 1342 intel_runtime_pm_get(dev_priv);
1343
1344 for_each_ring(ring, dev_priv, i) {
1345 seqno[i] = ring->get_seqno(ring, false);
1346 acthd[i] = intel_ring_get_active_head(ring);
1347 }
1348
61642ff0
MK		 1349 i915_get_extra_instdone(dev, instdone);
1350
ebbc7546
MK		 1351 intel_runtime_pm_put(dev_priv);
1352
f654449a
CW		 1353 if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) {
1354 seq_printf(m, "Hangcheck active, fires in %dms\n",
1355 jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires -
1356 jiffies));
1357 } else
1358 seq_printf(m, "Hangcheck inactive\n");
1359
1360 for_each_ring(ring, dev_priv, i) {
1361 seq_printf(m, "%s:\n", ring->name);
1362 seq_printf(m, "\tseqno = %x [current %x]\n",
ebbc7546 1363 ring->hangcheck.seqno, seqno[i]);
f654449a
CW		 1364 seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
1365 (long long)ring->hangcheck.acthd,
ebbc7546 1366 (long long)acthd[i]);
f654449a
CW		 1367 seq_printf(m, "\tmax ACTHD = 0x%08llx\n",
1368 (long long)ring->hangcheck.max_acthd);
ebbc7546
MK		 1369 seq_printf(m, "\tscore = %d\n", ring->hangcheck.score);
1370 seq_printf(m, "\taction = %d\n", ring->hangcheck.action);
61642ff0
MK		 1371
1372 if (ring->id == RCS) {
1373 seq_puts(m, "\tinstdone read =");
1374
1375 for (j = 0; j < I915_NUM_INSTDONE_REG; j++)
1376 seq_printf(m, " 0x%08x", instdone[j]);
1377
1378 seq_puts(m, "\n\tinstdone accu =");
1379
1380 for (j = 0; j < I915_NUM_INSTDONE_REG; j++)
1381 seq_printf(m, " 0x%08x",
1382 ring->hangcheck.instdone[j]);
1383
1384 seq_puts(m, "\n");
1385 }
f654449a
CW		 1386 }
1387
1388 return 0;
1389}
1390
4d85529d 1391static int ironlake_drpc_info(struct seq_file *m)
f97108d1 1392{
9f25d007 1393 struct drm_info_node *node = m->private;
f97108d1 1394 struct drm_device *dev = node->minor->dev;
e277a1f8 1395 struct drm_i915_private *dev_priv = dev->dev_private;
616fdb5a
BW		 1396 u32 rgvmodectl, rstdbyctl;
1397 u16 crstandvid;
1398 int ret;
1399
1400 ret = mutex_lock_interruptible(&dev->struct_mutex);
1401 if (ret)
1402 return ret;
c8c8fb33 1403 intel_runtime_pm_get(dev_priv);
616fdb5a
BW		 1404
1405 rgvmodectl = I915_READ(MEMMODECTL);
1406 rstdbyctl = I915_READ(RSTDBYCTL);
1407 crstandvid = I915_READ16(CRSTANDVID);
1408
c8c8fb33 1409 intel_runtime_pm_put(dev_priv);
616fdb5a 1410 mutex_unlock(&dev->struct_mutex);
f97108d1 1411
742f491d 1412 seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN));
f97108d1
JB		 1413 seq_printf(m, "Boost freq: %d\n",
1414 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1415 MEMMODE_BOOST_FREQ_SHIFT);
1416 seq_printf(m, "HW control enabled: %s\n",
742f491d 1417 yesno(rgvmodectl & MEMMODE_HWIDLE_EN));
f97108d1 1418 seq_printf(m, "SW control enabled: %s\n",
742f491d 1419 yesno(rgvmodectl & MEMMODE_SWMODE_EN));
f97108d1 1420 seq_printf(m, "Gated voltage change: %s\n",
742f491d 1421 yesno(rgvmodectl & MEMMODE_RCLK_GATE));
f97108d1
JB		 1422 seq_printf(m, "Starting frequency: P%d\n",
1423 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
7648fa99 1424 seq_printf(m, "Max P-state: P%d\n",
f97108d1 1425 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
7648fa99
JB		 1426 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1427 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1428 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1429 seq_printf(m, "Render standby enabled: %s\n",
742f491d 1430 yesno(!(rstdbyctl & RCX_SW_EXIT)));
267f0c90 1431 seq_puts(m, "Current RS state: ");
88271da3
JB		 1432 switch (rstdbyctl & RSX_STATUS_MASK) {
1433 case RSX_STATUS_ON:
267f0c90 1434 seq_puts(m, "on\n");
88271da3
JB		 1435 break;
1436 case RSX_STATUS_RC1:
267f0c90 1437 seq_puts(m, "RC1\n");
88271da3
JB		 1438 break;
1439 case RSX_STATUS_RC1E:
267f0c90 1440 seq_puts(m, "RC1E\n");
88271da3
JB		 1441 break;
1442 case RSX_STATUS_RS1:
267f0c90 1443 seq_puts(m, "RS1\n");
88271da3
JB		 1444 break;
1445 case RSX_STATUS_RS2:
267f0c90 1446 seq_puts(m, "RS2 (RC6)\n");
88271da3
JB		 1447 break;
1448 case RSX_STATUS_RS3:
267f0c90 1449 seq_puts(m, "RC3 (RC6+)\n");
88271da3
JB		 1450 break;
1451 default:
267f0c90 1452 seq_puts(m, "unknown\n");
88271da3
JB		 1453 break;
1454 }
f97108d1
JB		 1455
1456 return 0;
1457}
1458
f65367b5 1459static int i915_forcewake_domains(struct seq_file *m, void *data)
669ab5aa 1460{
b2cff0db
CW		 1461 struct drm_info_node *node = m->private;
1462 struct drm_device *dev = node->minor->dev;
1463 struct drm_i915_private *dev_priv = dev->dev_private;
1464 struct intel_uncore_forcewake_domain *fw_domain;
b2cff0db
CW		 1465 int i;
1466
1467 spin_lock_irq(&dev_priv->uncore.lock);
1468 for_each_fw_domain(fw_domain, dev_priv, i) {
1469 seq_printf(m, "%s.wake_count = %u\n",
05a2fb15 1470 intel_uncore_forcewake_domain_to_str(i),
b2cff0db
CW		 1471 fw_domain->wake_count);
1472 }
1473 spin_unlock_irq(&dev_priv->uncore.lock);
669ab5aa 1474
b2cff0db
CW		 1475 return 0;
1476}
1477
1478static int vlv_drpc_info(struct seq_file *m)
1479{
9f25d007 1480 struct drm_info_node *node = m->private;
669ab5aa
D		 1481 struct drm_device *dev = node->minor->dev;
1482 struct drm_i915_private *dev_priv = dev->dev_private;
6b312cd3 1483 u32 rpmodectl1, rcctl1, pw_status;
669ab5aa 1484
d46c0517
ID		 1485 intel_runtime_pm_get(dev_priv);
1486
6b312cd3 1487 pw_status = I915_READ(VLV_GTLC_PW_STATUS);
669ab5aa
D		 1488 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1489 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1490
d46c0517
ID		 1491 intel_runtime_pm_put(dev_priv);
1492
669ab5aa
D		 1493 seq_printf(m, "Video Turbo Mode: %s\n",
1494 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1495 seq_printf(m, "Turbo enabled: %s\n",
1496 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1497 seq_printf(m, "HW control enabled: %s\n",
1498 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1499 seq_printf(m, "SW control enabled: %s\n",
1500 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1501 GEN6_RP_MEDIA_SW_MODE));
1502 seq_printf(m, "RC6 Enabled: %s\n",
1503 yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1504 GEN6_RC_CTL_EI_MODE(1))));
1505 seq_printf(m, "Render Power Well: %s\n",
6b312cd3 1506 (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
669ab5aa 1507 seq_printf(m, "Media Power Well: %s\n",
6b312cd3 1508 (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
669ab5aa 1509
9cc19be5
ID		 1510 seq_printf(m, "Render RC6 residency since boot: %u\n",
1511 I915_READ(VLV_GT_RENDER_RC6));
1512 seq_printf(m, "Media RC6 residency since boot: %u\n",
1513 I915_READ(VLV_GT_MEDIA_RC6));
1514
f65367b5 1515 return i915_forcewake_domains(m, NULL);
669ab5aa
D		 1516}
1517
4d85529d
BW		 1518static int gen6_drpc_info(struct seq_file *m)
1519{
9f25d007 1520 struct drm_info_node *node = m->private;
4d85529d
BW		 1521 struct drm_device *dev = node->minor->dev;
1522 struct drm_i915_private *dev_priv = dev->dev_private;
ecd8faea 1523 u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
93b525dc 1524 unsigned forcewake_count;
aee56cff 1525 int count = 0, ret;
4d85529d
BW		 1526
1527 ret = mutex_lock_interruptible(&dev->struct_mutex);
1528 if (ret)
1529 return ret;
c8c8fb33 1530 intel_runtime_pm_get(dev_priv);
4d85529d 1531
907b28c5 1532 spin_lock_irq(&dev_priv->uncore.lock);
b2cff0db 1533 forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count;
907b28c5 1534 spin_unlock_irq(&dev_priv->uncore.lock);
93b525dc
DV		 1535
1536 if (forcewake_count) {
267f0c90
DL		 1537 seq_puts(m, "RC information inaccurate because somebody "
1538 "holds a forcewake reference \n");
4d85529d
BW		 1539 } else {
1540 /* NB: we cannot use forcewake, else we read the wrong values */
1541 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1542 udelay(10);
1543 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1544 }
1545
75aa3f63 1546 gt_core_status = I915_READ_FW(GEN6_GT_CORE_STATUS);
ed71f1b4 1547 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
4d85529d
BW		 1548
1549 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1550 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1551 mutex_unlock(&dev->struct_mutex);
44cbd338
BW		 1552 mutex_lock(&dev_priv->rps.hw_lock);
1553 sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1554 mutex_unlock(&dev_priv->rps.hw_lock);
4d85529d 1555
c8c8fb33
PZ		 1556 intel_runtime_pm_put(dev_priv);
1557
4d85529d
BW		 1558 seq_printf(m, "Video Turbo Mode: %s\n",
1559 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1560 seq_printf(m, "HW control enabled: %s\n",
1561 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1562 seq_printf(m, "SW control enabled: %s\n",
1563 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1564 GEN6_RP_MEDIA_SW_MODE));
fff24e21 1565 seq_printf(m, "RC1e Enabled: %s\n",
4d85529d
BW		 1566 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1567 seq_printf(m, "RC6 Enabled: %s\n",
1568 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1569 seq_printf(m, "Deep RC6 Enabled: %s\n",
1570 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1571 seq_printf(m, "Deepest RC6 Enabled: %s\n",
1572 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
267f0c90 1573 seq_puts(m, "Current RC state: ");
4d85529d
BW		 1574 switch (gt_core_status & GEN6_RCn_MASK) {
1575 case GEN6_RC0:
1576 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
267f0c90 1577 seq_puts(m, "Core Power Down\n");
4d85529d 1578 else
267f0c90 1579 seq_puts(m, "on\n");
4d85529d
BW		 1580 break;
1581 case GEN6_RC3:
267f0c90 1582 seq_puts(m, "RC3\n");
4d85529d
BW		 1583 break;
1584 case GEN6_RC6:
267f0c90 1585 seq_puts(m, "RC6\n");
4d85529d
BW		 1586 break;
1587 case GEN6_RC7:
267f0c90 1588 seq_puts(m, "RC7\n");
4d85529d
BW		 1589 break;
1590 default:
267f0c90 1591 seq_puts(m, "Unknown\n");
4d85529d
BW		 1592 break;
1593 }
1594
1595 seq_printf(m, "Core Power Down: %s\n",
1596 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
cce66a28
BW		 1597
1598 /* Not exactly sure what this is */
1599 seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1600 I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1601 seq_printf(m, "RC6 residency since boot: %u\n",
1602 I915_READ(GEN6_GT_GFX_RC6));
1603 seq_printf(m, "RC6+ residency since boot: %u\n",
1604 I915_READ(GEN6_GT_GFX_RC6p));
1605 seq_printf(m, "RC6++ residency since boot: %u\n",
1606 I915_READ(GEN6_GT_GFX_RC6pp));
1607
ecd8faea
BW		 1608 seq_printf(m, "RC6 voltage: %dmV\n",
1609 GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1610 seq_printf(m, "RC6+ voltage: %dmV\n",
1611 GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1612 seq_printf(m, "RC6++ voltage: %dmV\n",
1613 GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
4d85529d
BW		 1614 return 0;
1615}
1616
1617static int i915_drpc_info(struct seq_file *m, void *unused)
1618{
9f25d007 1619 struct drm_info_node *node = m->private;
4d85529d
BW		 1620 struct drm_device *dev = node->minor->dev;
1621
666a4537 1622 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
669ab5aa 1623 return vlv_drpc_info(m);
ac66cf4b 1624 else if (INTEL_INFO(dev)->gen >= 6)
4d85529d
BW		 1625 return gen6_drpc_info(m);
1626 else
1627 return ironlake_drpc_info(m);
1628}
1629
9a851789
DV		 1630static int i915_frontbuffer_tracking(struct seq_file *m, void *unused)
1631{
1632 struct drm_info_node *node = m->private;
1633 struct drm_device *dev = node->minor->dev;
1634 struct drm_i915_private *dev_priv = dev->dev_private;
1635
1636 seq_printf(m, "FB tracking busy bits: 0x%08x\n",
1637 dev_priv->fb_tracking.busy_bits);
1638
1639 seq_printf(m, "FB tracking flip bits: 0x%08x\n",
1640 dev_priv->fb_tracking.flip_bits);
1641
1642 return 0;
1643}
1644
b5e50c3f
JB		 1645static int i915_fbc_status(struct seq_file *m, void *unused)
1646{
9f25d007 1647 struct drm_info_node *node = m->private;
b5e50c3f 1648 struct drm_device *dev = node->minor->dev;
e277a1f8 1649 struct drm_i915_private *dev_priv = dev->dev_private;
b5e50c3f 1650
3a77c4c4 1651 if (!HAS_FBC(dev)) {
267f0c90 1652 seq_puts(m, "FBC unsupported on this chipset\n");
b5e50c3f
JB		 1653 return 0;
1654 }
1655
36623ef8 1656 intel_runtime_pm_get(dev_priv);
25ad93fd 1657 mutex_lock(&dev_priv->fbc.lock);
36623ef8 1658
0e631adc 1659 if (intel_fbc_is_active(dev_priv))
267f0c90 1660 seq_puts(m, "FBC enabled\n");
2e8144a5
PZ		 1661 else
1662 seq_printf(m, "FBC disabled: %s\n",
bf6189c6 1663 dev_priv->fbc.no_fbc_reason);
36623ef8 1664
31b9df10
PZ		 1665 if (INTEL_INFO(dev_priv)->gen >= 7)
1666 seq_printf(m, "Compressing: %s\n",
1667 yesno(I915_READ(FBC_STATUS2) &
1668 FBC_COMPRESSION_MASK));
1669
25ad93fd 1670 mutex_unlock(&dev_priv->fbc.lock);
36623ef8
PZ		 1671 intel_runtime_pm_put(dev_priv);
1672
b5e50c3f
JB		 1673 return 0;
1674}
1675
da46f936
RV		 1676static int i915_fbc_fc_get(void *data, u64 *val)
1677{
1678 struct drm_device *dev = data;
1679 struct drm_i915_private *dev_priv = dev->dev_private;
1680
1681 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1682 return -ENODEV;
1683
da46f936 1684 *val = dev_priv->fbc.false_color;
da46f936
RV		 1685
1686 return 0;
1687}
1688
1689static int i915_fbc_fc_set(void *data, u64 val)
1690{
1691 struct drm_device *dev = data;
1692 struct drm_i915_private *dev_priv = dev->dev_private;
1693 u32 reg;
1694
1695 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1696 return -ENODEV;
1697
25ad93fd 1698 mutex_lock(&dev_priv->fbc.lock);
da46f936
RV		 1699
1700 reg = I915_READ(ILK_DPFC_CONTROL);
1701 dev_priv->fbc.false_color = val;
1702
1703 I915_WRITE(ILK_DPFC_CONTROL, val ?
1704 (reg | FBC_CTL_FALSE_COLOR) :
1705 (reg & ~FBC_CTL_FALSE_COLOR));
1706
25ad93fd 1707 mutex_unlock(&dev_priv->fbc.lock);
da46f936
RV		 1708 return 0;
1709}
1710
1711DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops,
1712 i915_fbc_fc_get, i915_fbc_fc_set,
1713 "%llu\n");
1714
92d44621
PZ		 1715static int i915_ips_status(struct seq_file *m, void *unused)
1716{
9f25d007 1717 struct drm_info_node *node = m->private;
92d44621
PZ		 1718 struct drm_device *dev = node->minor->dev;
1719 struct drm_i915_private *dev_priv = dev->dev_private;
1720
f5adf94e 1721 if (!HAS_IPS(dev)) {
92d44621
PZ		 1722 seq_puts(m, "not supported\n");
1723 return 0;
1724 }
1725
36623ef8
PZ		 1726 intel_runtime_pm_get(dev_priv);
1727
0eaa53f0
RV		 1728 seq_printf(m, "Enabled by kernel parameter: %s\n",
1729 yesno(i915.enable_ips));
1730
1731 if (INTEL_INFO(dev)->gen >= 8) {
1732 seq_puts(m, "Currently: unknown\n");
1733 } else {
1734 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1735 seq_puts(m, "Currently: enabled\n");
1736 else
1737 seq_puts(m, "Currently: disabled\n");
1738 }
92d44621 1739
36623ef8
PZ		 1740 intel_runtime_pm_put(dev_priv);
1741
92d44621
PZ		 1742 return 0;
1743}
1744
4a9bef37
JB		 1745static int i915_sr_status(struct seq_file *m, void *unused)
1746{
9f25d007 1747 struct drm_info_node *node = m->private;
4a9bef37 1748 struct drm_device *dev = node->minor->dev;
e277a1f8 1749 struct drm_i915_private *dev_priv = dev->dev_private;
4a9bef37
JB		 1750 bool sr_enabled = false;
1751
36623ef8
PZ		 1752 intel_runtime_pm_get(dev_priv);
1753
1398261a 1754 if (HAS_PCH_SPLIT(dev))
5ba2aaaa 1755 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
77b64555
ACO		 1756 else if (IS_CRESTLINE(dev) || IS_G4X(dev) ||
1757 IS_I945G(dev) || IS_I945GM(dev))
4a9bef37
JB		 1758 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1759 else if (IS_I915GM(dev))
1760 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1761 else if (IS_PINEVIEW(dev))
1762 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
666a4537 1763 else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
77b64555 1764 sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
4a9bef37 1765
36623ef8
PZ		 1766 intel_runtime_pm_put(dev_priv);
1767
5ba2aaaa
CW		 1768 seq_printf(m, "self-refresh: %s\n",
1769 sr_enabled ? "enabled" : "disabled");
4a9bef37
JB		 1770
1771 return 0;
1772}
1773
7648fa99
JB		 1774static int i915_emon_status(struct seq_file *m, void *unused)
1775{
9f25d007 1776 struct drm_info_node *node = m->private;
7648fa99 1777 struct drm_device *dev = node->minor->dev;
e277a1f8 1778 struct drm_i915_private *dev_priv = dev->dev_private;
7648fa99 1779 unsigned long temp, chipset, gfx;
de227ef0
CW		 1780 int ret;
1781
582be6b4
CW		 1782 if (!IS_GEN5(dev))
1783 return -ENODEV;
1784
de227ef0
CW		 1785 ret = mutex_lock_interruptible(&dev->struct_mutex);
1786 if (ret)
1787 return ret;
7648fa99
JB		 1788
1789 temp = i915_mch_val(dev_priv);
1790 chipset = i915_chipset_val(dev_priv);
1791 gfx = i915_gfx_val(dev_priv);
de227ef0 1792 mutex_unlock(&dev->struct_mutex);
7648fa99
JB		 1793
1794 seq_printf(m, "GMCH temp: %ld\n", temp);
1795 seq_printf(m, "Chipset power: %ld\n", chipset);
1796 seq_printf(m, "GFX power: %ld\n", gfx);
1797 seq_printf(m, "Total power: %ld\n", chipset + gfx);
1798
1799 return 0;
1800}
1801
23b2f8bb
JB		 1802static int i915_ring_freq_table(struct seq_file *m, void *unused)
1803{
9f25d007 1804 struct drm_info_node *node = m->private;
23b2f8bb 1805 struct drm_device *dev = node->minor->dev;
e277a1f8 1806 struct drm_i915_private *dev_priv = dev->dev_private;
5bfa0199 1807 int ret = 0;
23b2f8bb 1808 int gpu_freq, ia_freq;
f936ec34 1809 unsigned int max_gpu_freq, min_gpu_freq;
23b2f8bb 1810
97d3308a 1811 if (!HAS_CORE_RING_FREQ(dev)) {
267f0c90 1812 seq_puts(m, "unsupported on this chipset\n");
23b2f8bb
JB		 1813 return 0;
1814 }
1815
5bfa0199
PZ		 1816 intel_runtime_pm_get(dev_priv);
1817
5c9669ce
TR		 1818 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1819
4fc688ce 1820 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
23b2f8bb 1821 if (ret)
5bfa0199 1822 goto out;
23b2f8bb 1823
ef11bdb3 1824 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
f936ec34
AG		 1825 /* Convert GT frequency to 50 HZ units */
1826 min_gpu_freq =
1827 dev_priv->rps.min_freq_softlimit / GEN9_FREQ_SCALER;
1828 max_gpu_freq =
1829 dev_priv->rps.max_freq_softlimit / GEN9_FREQ_SCALER;
1830 } else {
1831 min_gpu_freq = dev_priv->rps.min_freq_softlimit;
1832 max_gpu_freq = dev_priv->rps.max_freq_softlimit;
1833 }
1834
267f0c90 1835 seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
23b2f8bb 1836
f936ec34 1837 for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
42c0526c
BW		 1838 ia_freq = gpu_freq;
1839 sandybridge_pcode_read(dev_priv,
1840 GEN6_PCODE_READ_MIN_FREQ_TABLE,
1841 &ia_freq);
3ebecd07 1842 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
f936ec34 1843 intel_gpu_freq(dev_priv, (gpu_freq *
ef11bdb3
RV		 1844 (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1845 GEN9_FREQ_SCALER : 1))),
3ebecd07
CW		 1846 ((ia_freq >> 0) & 0xff) * 100,
1847 ((ia_freq >> 8) & 0xff) * 100);
23b2f8bb
JB		 1848 }
1849
4fc688ce 1850 mutex_unlock(&dev_priv->rps.hw_lock);
23b2f8bb 1851
5bfa0199
PZ		 1852out:
1853 intel_runtime_pm_put(dev_priv);
1854 return ret;
23b2f8bb
JB		 1855}
1856
44834a67
CW		 1857static int i915_opregion(struct seq_file *m, void *unused)
1858{
9f25d007 1859 struct drm_info_node *node = m->private;
44834a67 1860 struct drm_device *dev = node->minor->dev;
e277a1f8 1861 struct drm_i915_private *dev_priv = dev->dev_private;
44834a67
CW		 1862 struct intel_opregion *opregion = &dev_priv->opregion;
1863 int ret;
1864
1865 ret = mutex_lock_interruptible(&dev->struct_mutex);
1866 if (ret)
0d38f009 1867 goto out;
44834a67 1868
2455a8e4
JN		 1869 if (opregion->header)
1870 seq_write(m, opregion->header, OPREGION_SIZE);
44834a67
CW		 1871
1872 mutex_unlock(&dev->struct_mutex);
1873
0d38f009 1874out:
44834a67
CW		 1875 return 0;
1876}
1877
ada8f955
JN		 1878static int i915_vbt(struct seq_file *m, void *unused)
1879{
1880 struct drm_info_node *node = m->private;
1881 struct drm_device *dev = node->minor->dev;
1882 struct drm_i915_private *dev_priv = dev->dev_private;
1883 struct intel_opregion *opregion = &dev_priv->opregion;
1884
1885 if (opregion->vbt)
1886 seq_write(m, opregion->vbt, opregion->vbt_size);
1887
1888 return 0;
1889}
1890
37811fcc
CW		 1891static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1892{
9f25d007 1893 struct drm_info_node *node = m->private;
37811fcc 1894 struct drm_device *dev = node->minor->dev;
b13b8402 1895 struct intel_framebuffer *fbdev_fb = NULL;
3a58ee10 1896 struct drm_framebuffer *drm_fb;
37811fcc 1897
0695726e 1898#ifdef CONFIG_DRM_FBDEV_EMULATION
b13b8402
NS		 1899 if (to_i915(dev)->fbdev) {
1900 fbdev_fb = to_intel_framebuffer(to_i915(dev)->fbdev->helper.fb);
1901
1902 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1903 fbdev_fb->base.width,
1904 fbdev_fb->base.height,
1905 fbdev_fb->base.depth,
1906 fbdev_fb->base.bits_per_pixel,
1907 fbdev_fb->base.modifier[0],
1908 atomic_read(&fbdev_fb->base.refcount.refcount));
1909 describe_obj(m, fbdev_fb->obj);
1910 seq_putc(m, '\n');
1911 }
4520f53a 1912#endif
37811fcc 1913
4b096ac1 1914 mutex_lock(&dev->mode_config.fb_lock);
3a58ee10 1915 drm_for_each_fb(drm_fb, dev) {
b13b8402
NS		 1916 struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb);
1917 if (fb == fbdev_fb)
37811fcc
CW		 1918 continue;
1919
c1ca506d 1920 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
37811fcc
CW		 1921 fb->base.width,
1922 fb->base.height,
1923 fb->base.depth,
623f9783 1924 fb->base.bits_per_pixel,
c1ca506d 1925 fb->base.modifier[0],
623f9783 1926 atomic_read(&fb->base.refcount.refcount));
05394f39 1927 describe_obj(m, fb->obj);
267f0c90 1928 seq_putc(m, '\n');
37811fcc 1929 }
4b096ac1 1930 mutex_unlock(&dev->mode_config.fb_lock);
37811fcc
CW		 1931
1932 return 0;
1933}
1934
c9fe99bd
OM		 1935static void describe_ctx_ringbuf(struct seq_file *m,
1936 struct intel_ringbuffer *ringbuf)
1937{
1938 seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
1939 ringbuf->space, ringbuf->head, ringbuf->tail,
1940 ringbuf->last_retired_head);
1941}
1942
e76d3630
BW		 1943static int i915_context_status(struct seq_file *m, void *unused)
1944{
9f25d007 1945 struct drm_info_node *node = m->private;
e76d3630 1946 struct drm_device *dev = node->minor->dev;
e277a1f8 1947 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 1948 struct intel_engine_cs *ring;
273497e5 1949 struct intel_context *ctx;
a168c293 1950 int ret, i;
e76d3630 1951
f3d28878 1952 ret = mutex_lock_interruptible(&dev->struct_mutex);
e76d3630
BW		 1953 if (ret)
1954 return ret;
1955
a33afea5 1956 list_for_each_entry(ctx, &dev_priv->context_list, link) {
c9fe99bd
OM		 1957 if (!i915.enable_execlists &&
1958 ctx->legacy_hw_ctx.rcs_state == NULL)
b77f6997
CW		 1959 continue;
1960
a33afea5 1961 seq_puts(m, "HW context ");
3ccfd19d 1962 describe_ctx(m, ctx);
c9fe99bd 1963 for_each_ring(ring, dev_priv, i) {
ed54c1a1 1964 if (dev_priv->kernel_context == ctx)
c9fe99bd
OM		 1965 seq_printf(m, "(default context %s) ",
1966 ring->name);
1967 }
1968
1969 if (i915.enable_execlists) {
1970 seq_putc(m, '\n');
1971 for_each_ring(ring, dev_priv, i) {
1972 struct drm_i915_gem_object *ctx_obj =
1973 ctx->engine[i].state;
1974 struct intel_ringbuffer *ringbuf =
1975 ctx->engine[i].ringbuf;
1976
1977 seq_printf(m, "%s: ", ring->name);
1978 if (ctx_obj)
1979 describe_obj(m, ctx_obj);
1980 if (ringbuf)
1981 describe_ctx_ringbuf(m, ringbuf);
1982 seq_putc(m, '\n');
1983 }
1984 } else {
1985 describe_obj(m, ctx->legacy_hw_ctx.rcs_state);
1986 }
a33afea5 1987
a33afea5 1988 seq_putc(m, '\n');
a168c293
BW		 1989 }
1990
f3d28878 1991 mutex_unlock(&dev->struct_mutex);
e76d3630
BW		 1992
1993 return 0;
1994}
1995
064ca1d2 1996static void i915_dump_lrc_obj(struct seq_file *m,
ca82580c
TU		 1997 struct intel_context *ctx,
1998 struct intel_engine_cs *ring)
064ca1d2
TD		 1999{
2000 struct page *page;
2001 uint32_t *reg_state;
2002 int j;
ca82580c 2003 struct drm_i915_gem_object *ctx_obj = ctx->engine[ring->id].state;
064ca1d2
TD		 2004 unsigned long ggtt_offset = 0;
2005
2006 if (ctx_obj == NULL) {
2007 seq_printf(m, "Context on %s with no gem object\n",
2008 ring->name);
2009 return;
2010 }
2011
2012 seq_printf(m, "CONTEXT: %s %u\n", ring->name,
ca82580c 2013 intel_execlists_ctx_id(ctx, ring));
064ca1d2
TD		 2014
2015 if (!i915_gem_obj_ggtt_bound(ctx_obj))
2016 seq_puts(m, "\tNot bound in GGTT\n");
2017 else
2018 ggtt_offset = i915_gem_obj_ggtt_offset(ctx_obj);
2019
2020 if (i915_gem_object_get_pages(ctx_obj)) {
2021 seq_puts(m, "\tFailed to get pages for context object\n");
2022 return;
2023 }
2024
d1675198 2025 page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN);
064ca1d2
TD		 2026 if (!WARN_ON(page == NULL)) {
2027 reg_state = kmap_atomic(page);
2028
2029 for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
2030 seq_printf(m, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n",
2031 ggtt_offset + 4096 + (j * 4),
2032 reg_state[j], reg_state[j + 1],
2033 reg_state[j + 2], reg_state[j + 3]);
2034 }
2035 kunmap_atomic(reg_state);
2036 }
2037
2038 seq_putc(m, '\n');
2039}
2040
c0ab1ae9
BW		 2041static int i915_dump_lrc(struct seq_file *m, void *unused)
2042{
2043 struct drm_info_node *node = (struct drm_info_node *) m->private;
2044 struct drm_device *dev = node->minor->dev;
2045 struct drm_i915_private *dev_priv = dev->dev_private;
2046 struct intel_engine_cs *ring;
2047 struct intel_context *ctx;
2048 int ret, i;
2049
2050 if (!i915.enable_execlists) {
2051 seq_printf(m, "Logical Ring Contexts are disabled\n");
2052 return 0;
2053 }
2054
2055 ret = mutex_lock_interruptible(&dev->struct_mutex);
2056 if (ret)
2057 return ret;
2058
2059 list_for_each_entry(ctx, &dev_priv->context_list, link) {
2060 for_each_ring(ring, dev_priv, i) {
ed54c1a1 2061 if (dev_priv->kernel_context != ctx)
ca82580c 2062 i915_dump_lrc_obj(m, ctx, ring);
c0ab1ae9
BW		 2063 }
2064 }
2065
2066 mutex_unlock(&dev->struct_mutex);
2067
2068 return 0;
2069}
2070
4ba70e44
OM		 2071static int i915_execlists(struct seq_file *m, void *data)
2072{
2073 struct drm_info_node *node = (struct drm_info_node *)m->private;
2074 struct drm_device *dev = node->minor->dev;
2075 struct drm_i915_private *dev_priv = dev->dev_private;
2076 struct intel_engine_cs *ring;
2077 u32 status_pointer;
2078 u8 read_pointer;
2079 u8 write_pointer;
2080 u32 status;
2081 u32 ctx_id;
2082 struct list_head *cursor;
2083 int ring_id, i;
2084 int ret;
2085
2086 if (!i915.enable_execlists) {
2087 seq_puts(m, "Logical Ring Contexts are disabled\n");
2088 return 0;
2089 }
2090
2091 ret = mutex_lock_interruptible(&dev->struct_mutex);
2092 if (ret)
2093 return ret;
2094
fc0412ec
MT		 2095 intel_runtime_pm_get(dev_priv);
2096
4ba70e44 2097 for_each_ring(ring, dev_priv, ring_id) {
6d3d8274 2098 struct drm_i915_gem_request *head_req = NULL;
4ba70e44
OM		 2099 int count = 0;
2100 unsigned long flags;
2101
2102 seq_printf(m, "%s\n", ring->name);
2103
83843d84
VS		 2104 status = I915_READ(RING_EXECLIST_STATUS_LO(ring));
2105 ctx_id = I915_READ(RING_EXECLIST_STATUS_HI(ring));
4ba70e44
OM		 2106 seq_printf(m, "\tExeclist status: 0x%08X, context: %u\n",
2107 status, ctx_id);
2108
2109 status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(ring));
2110 seq_printf(m, "\tStatus pointer: 0x%08X\n", status_pointer);
2111
2112 read_pointer = ring->next_context_status_buffer;
5590a5f0 2113 write_pointer = GEN8_CSB_WRITE_PTR(status_pointer);
4ba70e44 2114 if (read_pointer > write_pointer)
5590a5f0 2115 write_pointer += GEN8_CSB_ENTRIES;
4ba70e44
OM		 2116 seq_printf(m, "\tRead pointer: 0x%08X, write pointer 0x%08X\n",
2117 read_pointer, write_pointer);
2118
5590a5f0 2119 for (i = 0; i < GEN8_CSB_ENTRIES; i++) {
83843d84
VS		 2120 status = I915_READ(RING_CONTEXT_STATUS_BUF_LO(ring, i));
2121 ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF_HI(ring, i));
4ba70e44
OM		 2122
2123 seq_printf(m, "\tStatus buffer %d: 0x%08X, context: %u\n",
2124 i, status, ctx_id);
2125 }
2126
2127 spin_lock_irqsave(&ring->execlist_lock, flags);
2128 list_for_each(cursor, &ring->execlist_queue)
2129 count++;
2130 head_req = list_first_entry_or_null(&ring->execlist_queue,
6d3d8274 2131 struct drm_i915_gem_request, execlist_link);
4ba70e44
OM		 2132 spin_unlock_irqrestore(&ring->execlist_lock, flags);
2133
2134 seq_printf(m, "\t%d requests in queue\n", count);
2135 if (head_req) {
4ba70e44 2136 seq_printf(m, "\tHead request id: %u\n",
ca82580c 2137 intel_execlists_ctx_id(head_req->ctx, ring));
4ba70e44 2138 seq_printf(m, "\tHead request tail: %u\n",
6d3d8274 2139 head_req->tail);
4ba70e44
OM		 2140 }
2141
2142 seq_putc(m, '\n');
2143 }
2144
fc0412ec 2145 intel_runtime_pm_put(dev_priv);
4ba70e44
OM		 2146 mutex_unlock(&dev->struct_mutex);
2147
2148 return 0;
2149}
2150
ea16a3cd
DV		 2151static const char *swizzle_string(unsigned swizzle)
2152{
aee56cff 2153 switch (swizzle) {
ea16a3cd
DV		 2154 case I915_BIT_6_SWIZZLE_NONE:
2155 return "none";
2156 case I915_BIT_6_SWIZZLE_9:
2157 return "bit9";
2158 case I915_BIT_6_SWIZZLE_9_10:
2159 return "bit9/bit10";
2160 case I915_BIT_6_SWIZZLE_9_11:
2161 return "bit9/bit11";
2162 case I915_BIT_6_SWIZZLE_9_10_11:
2163 return "bit9/bit10/bit11";
2164 case I915_BIT_6_SWIZZLE_9_17:
2165 return "bit9/bit17";
2166 case I915_BIT_6_SWIZZLE_9_10_17:
2167 return "bit9/bit10/bit17";
2168 case I915_BIT_6_SWIZZLE_UNKNOWN:
8a168ca7 2169 return "unknown";
ea16a3cd
DV		 2170 }
2171
2172 return "bug";
2173}
2174
2175static int i915_swizzle_info(struct seq_file *m, void *data)
2176{
9f25d007 2177 struct drm_info_node *node = m->private;
ea16a3cd
DV		 2178 struct drm_device *dev = node->minor->dev;
2179 struct drm_i915_private *dev_priv = dev->dev_private;
22bcfc6a
DV		 2180 int ret;
2181
2182 ret = mutex_lock_interruptible(&dev->struct_mutex);
2183 if (ret)
2184 return ret;
c8c8fb33 2185 intel_runtime_pm_get(dev_priv);
ea16a3cd 2186
ea16a3cd
DV		 2187 seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
2188 swizzle_string(dev_priv->mm.bit_6_swizzle_x));
2189 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
2190 swizzle_string(dev_priv->mm.bit_6_swizzle_y));
2191
2192 if (IS_GEN3(dev) || IS_GEN4(dev)) {
2193 seq_printf(m, "DDC = 0x%08x\n",
2194 I915_READ(DCC));
656bfa3a
DV		 2195 seq_printf(m, "DDC2 = 0x%08x\n",
2196 I915_READ(DCC2));
ea16a3cd
DV		 2197 seq_printf(m, "C0DRB3 = 0x%04x\n",
2198 I915_READ16(C0DRB3));
2199 seq_printf(m, "C1DRB3 = 0x%04x\n",
2200 I915_READ16(C1DRB3));
9d3203e1 2201 } else if (INTEL_INFO(dev)->gen >= 6) {
3fa7d235
DV		 2202 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
2203 I915_READ(MAD_DIMM_C0));
2204 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
2205 I915_READ(MAD_DIMM_C1));
2206 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
2207 I915_READ(MAD_DIMM_C2));
2208 seq_printf(m, "TILECTL = 0x%08x\n",
2209 I915_READ(TILECTL));
5907f5fb 2210 if (INTEL_INFO(dev)->gen >= 8)
9d3203e1
BW		 2211 seq_printf(m, "GAMTARBMODE = 0x%08x\n",
2212 I915_READ(GAMTARBMODE));
2213 else
2214 seq_printf(m, "ARB_MODE = 0x%08x\n",
2215 I915_READ(ARB_MODE));
3fa7d235
DV		 2216 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
2217 I915_READ(DISP_ARB_CTL));
ea16a3cd 2218 }
656bfa3a
DV		 2219
2220 if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2221 seq_puts(m, "L-shaped memory detected\n");
2222
c8c8fb33 2223 intel_runtime_pm_put(dev_priv);
ea16a3cd
DV		 2224 mutex_unlock(&dev->struct_mutex);
2225
2226 return 0;
2227}
2228
1c60fef5
BW		 2229static int per_file_ctx(int id, void *ptr, void *data)
2230{
273497e5 2231 struct intel_context *ctx = ptr;
1c60fef5 2232 struct seq_file *m = data;
ae6c4806
DV		 2233 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2234
2235 if (!ppgtt) {
2236 seq_printf(m, " no ppgtt for context %d\n",
2237 ctx->user_handle);
2238 return 0;
2239 }
1c60fef5 2240
f83d6518
OM		 2241 if (i915_gem_context_is_default(ctx))
2242 seq_puts(m, " default context:\n");
2243 else
821d66dd 2244 seq_printf(m, " context %d:\n", ctx->user_handle);
1c60fef5
BW		 2245 ppgtt->debug_dump(ppgtt, m);
2246
2247 return 0;
2248}
2249
77df6772 2250static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev)
3cf17fc5 2251{
3cf17fc5 2252 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2253 struct intel_engine_cs *ring;
77df6772
BW		 2254 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2255 int unused, i;
3cf17fc5 2256
77df6772
BW		 2257 if (!ppgtt)
2258 return;
2259
77df6772
BW		 2260 for_each_ring(ring, dev_priv, unused) {
2261 seq_printf(m, "%s\n", ring->name);
2262 for (i = 0; i < 4; i++) {
d3a93cbe 2263 u64 pdp = I915_READ(GEN8_RING_PDP_UDW(ring, i));
77df6772 2264 pdp <<= 32;
d3a93cbe 2265 pdp |= I915_READ(GEN8_RING_PDP_LDW(ring, i));
a2a5b15c 2266 seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
77df6772
BW		 2267 }
2268 }
2269}
2270
2271static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2272{
2273 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2274 struct intel_engine_cs *ring;
77df6772 2275 int i;
3cf17fc5 2276
3cf17fc5
DV		 2277 if (INTEL_INFO(dev)->gen == 6)
2278 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
2279
a2c7f6fd 2280 for_each_ring(ring, dev_priv, i) {
3cf17fc5
DV		 2281 seq_printf(m, "%s\n", ring->name);
2282 if (INTEL_INFO(dev)->gen == 7)
2283 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
2284 seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
2285 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
2286 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring)));
2287 }
2288 if (dev_priv->mm.aliasing_ppgtt) {
2289 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2290
267f0c90 2291 seq_puts(m, "aliasing PPGTT:\n");
44159ddb 2292 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.base.ggtt_offset);
1c60fef5 2293
87d60b63 2294 ppgtt->debug_dump(ppgtt, m);
ae6c4806 2295 }
1c60fef5 2296
3cf17fc5 2297 seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
77df6772
BW		 2298}
2299
2300static int i915_ppgtt_info(struct seq_file *m, void *data)
2301{
9f25d007 2302 struct drm_info_node *node = m->private;
77df6772 2303 struct drm_device *dev = node->minor->dev;
c8c8fb33 2304 struct drm_i915_private *dev_priv = dev->dev_private;
ea91e401 2305 struct drm_file *file;
77df6772
BW		 2306
2307 int ret = mutex_lock_interruptible(&dev->struct_mutex);
2308 if (ret)
2309 return ret;
c8c8fb33 2310 intel_runtime_pm_get(dev_priv);
77df6772
BW		 2311
2312 if (INTEL_INFO(dev)->gen >= 8)
2313 gen8_ppgtt_info(m, dev);
2314 else if (INTEL_INFO(dev)->gen >= 6)
2315 gen6_ppgtt_info(m, dev);
2316
ea91e401
MT		 2317 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2318 struct drm_i915_file_private *file_priv = file->driver_priv;
7cb5dff8 2319 struct task_struct *task;
ea91e401 2320
7cb5dff8 2321 task = get_pid_task(file->pid, PIDTYPE_PID);
06812760
DC		 2322 if (!task) {
2323 ret = -ESRCH;
2324 goto out_put;
2325 }
7cb5dff8
GT		 2326 seq_printf(m, "\nproc: %s\n", task->comm);
2327 put_task_struct(task);
ea91e401
MT		 2328 idr_for_each(&file_priv->context_idr, per_file_ctx,
2329 (void *)(unsigned long)m);
2330 }
2331
06812760 2332out_put:
c8c8fb33 2333 intel_runtime_pm_put(dev_priv);
3cf17fc5
DV		 2334 mutex_unlock(&dev->struct_mutex);
2335
06812760 2336 return ret;
3cf17fc5
DV		 2337}
2338
f5a4c67d
CW		 2339static int count_irq_waiters(struct drm_i915_private *i915)
2340{
2341 struct intel_engine_cs *ring;
2342 int count = 0;
2343 int i;
2344
2345 for_each_ring(ring, i915, i)
2346 count += ring->irq_refcount;
2347
2348 return count;
2349}
2350
1854d5ca
CW		 2351static int i915_rps_boost_info(struct seq_file *m, void *data)
2352{
2353 struct drm_info_node *node = m->private;
2354 struct drm_device *dev = node->minor->dev;
2355 struct drm_i915_private *dev_priv = dev->dev_private;
2356 struct drm_file *file;
1854d5ca 2357
f5a4c67d
CW		 2358 seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled);
2359 seq_printf(m, "GPU busy? %d\n", dev_priv->mm.busy);
2360 seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv));
2361 seq_printf(m, "Frequency requested %d; min hard:%d, soft:%d; max soft:%d, hard:%d\n",
2362 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
2363 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2364 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit),
2365 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit),
2366 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
8d3afd7d 2367 spin_lock(&dev_priv->rps.client_lock);
1854d5ca
CW		 2368 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2369 struct drm_i915_file_private *file_priv = file->driver_priv;
2370 struct task_struct *task;
2371
2372 rcu_read_lock();
2373 task = pid_task(file->pid, PIDTYPE_PID);
2374 seq_printf(m, "%s [%d]: %d boosts%s\n",
2375 task ? task->comm : "<unknown>",
2376 task ? task->pid : -1,
2e1b8730
CW		 2377 file_priv->rps.boosts,
2378 list_empty(&file_priv->rps.link) ? "" : ", active");
1854d5ca
CW		 2379 rcu_read_unlock();
2380 }
2e1b8730
CW		 2381 seq_printf(m, "Semaphore boosts: %d%s\n",
2382 dev_priv->rps.semaphores.boosts,
2383 list_empty(&dev_priv->rps.semaphores.link) ? "" : ", active");
2384 seq_printf(m, "MMIO flip boosts: %d%s\n",
2385 dev_priv->rps.mmioflips.boosts,
2386 list_empty(&dev_priv->rps.mmioflips.link) ? "" : ", active");
1854d5ca 2387 seq_printf(m, "Kernel boosts: %d\n", dev_priv->rps.boosts);
8d3afd7d 2388 spin_unlock(&dev_priv->rps.client_lock);
1854d5ca 2389
8d3afd7d 2390 return 0;
1854d5ca
CW		 2391}
2392
63573eb7
BW		 2393static int i915_llc(struct seq_file *m, void *data)
2394{
9f25d007 2395 struct drm_info_node *node = m->private;
63573eb7
BW		 2396 struct drm_device *dev = node->minor->dev;
2397 struct drm_i915_private *dev_priv = dev->dev_private;
2398
2399 /* Size calculation for LLC is a bit of a pain. Ignore for now. */
2400 seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
2401 seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size);
2402
2403 return 0;
2404}
2405
fdf5d357
AD		 2406static int i915_guc_load_status_info(struct seq_file *m, void *data)
2407{
2408 struct drm_info_node *node = m->private;
2409 struct drm_i915_private *dev_priv = node->minor->dev->dev_private;
2410 struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
2411 u32 tmp, i;
2412
2413 if (!HAS_GUC_UCODE(dev_priv->dev))
2414 return 0;
2415
2416 seq_printf(m, "GuC firmware status:\n");
2417 seq_printf(m, "\tpath: %s\n",
2418 guc_fw->guc_fw_path);
2419 seq_printf(m, "\tfetch: %s\n",
2420 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
2421 seq_printf(m, "\tload: %s\n",
2422 intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
2423 seq_printf(m, "\tversion wanted: %d.%d\n",
2424 guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
2425 seq_printf(m, "\tversion found: %d.%d\n",
2426 guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found);
feda33ef
AD		 2427 seq_printf(m, "\theader: offset is %d; size = %d\n",
2428 guc_fw->header_offset, guc_fw->header_size);
2429 seq_printf(m, "\tuCode: offset is %d; size = %d\n",
2430 guc_fw->ucode_offset, guc_fw->ucode_size);
2431 seq_printf(m, "\tRSA: offset is %d; size = %d\n",
2432 guc_fw->rsa_offset, guc_fw->rsa_size);
fdf5d357
AD		 2433
2434 tmp = I915_READ(GUC_STATUS);
2435
2436 seq_printf(m, "\nGuC status 0x%08x:\n", tmp);
2437 seq_printf(m, "\tBootrom status = 0x%x\n",
2438 (tmp & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT);
2439 seq_printf(m, "\tuKernel status = 0x%x\n",
2440 (tmp & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT);
2441 seq_printf(m, "\tMIA Core status = 0x%x\n",
2442 (tmp & GS_MIA_MASK) >> GS_MIA_SHIFT);
2443 seq_puts(m, "\nScratch registers:\n");
2444 for (i = 0; i < 16; i++)
2445 seq_printf(m, "\t%2d: \t0x%x\n", i, I915_READ(SOFT_SCRATCH(i)));
2446
2447 return 0;
2448}
2449
8b417c26
DG		 2450static void i915_guc_client_info(struct seq_file *m,
2451 struct drm_i915_private *dev_priv,
2452 struct i915_guc_client *client)
2453{
2454 struct intel_engine_cs *ring;
2455 uint64_t tot = 0;
2456 uint32_t i;
2457
2458 seq_printf(m, "\tPriority %d, GuC ctx index: %u, PD offset 0x%x\n",
2459 client->priority, client->ctx_index, client->proc_desc_offset);
2460 seq_printf(m, "\tDoorbell id %d, offset: 0x%x, cookie 0x%x\n",
2461 client->doorbell_id, client->doorbell_offset, client->cookie);
2462 seq_printf(m, "\tWQ size %d, offset: 0x%x, tail %d\n",
2463 client->wq_size, client->wq_offset, client->wq_tail);
2464
2465 seq_printf(m, "\tFailed to queue: %u\n", client->q_fail);
2466 seq_printf(m, "\tFailed doorbell: %u\n", client->b_fail);
2467 seq_printf(m, "\tLast submission result: %d\n", client->retcode);
2468
2469 for_each_ring(ring, dev_priv, i) {
2470 seq_printf(m, "\tSubmissions: %llu %s\n",
2471 client->submissions[i],
2472 ring->name);
2473 tot += client->submissions[i];
2474 }
2475 seq_printf(m, "\tTotal: %llu\n", tot);
2476}
2477
2478static int i915_guc_info(struct seq_file *m, void *data)
2479{
2480 struct drm_info_node *node = m->private;
2481 struct drm_device *dev = node->minor->dev;
2482 struct drm_i915_private *dev_priv = dev->dev_private;
2483 struct intel_guc guc;
0a0b457f 2484 struct i915_guc_client client = {};
8b417c26
DG		 2485 struct intel_engine_cs *ring;
2486 enum intel_ring_id i;
2487 u64 total = 0;
2488
2489 if (!HAS_GUC_SCHED(dev_priv->dev))
2490 return 0;
2491
5a843307
AD		 2492 if (mutex_lock_interruptible(&dev->struct_mutex))
2493 return 0;
2494
8b417c26 2495 /* Take a local copy of the GuC data, so we can dump it at leisure */
8b417c26 2496 guc = dev_priv->guc;
5a843307 2497 if (guc.execbuf_client)
8b417c26 2498 client = *guc.execbuf_client;
5a843307
AD		 2499
2500 mutex_unlock(&dev->struct_mutex);
8b417c26
DG		 2501
2502 seq_printf(m, "GuC total action count: %llu\n", guc.action_count);
2503 seq_printf(m, "GuC action failure count: %u\n", guc.action_fail);
2504 seq_printf(m, "GuC last action command: 0x%x\n", guc.action_cmd);
2505 seq_printf(m, "GuC last action status: 0x%x\n", guc.action_status);
2506 seq_printf(m, "GuC last action error code: %d\n", guc.action_err);
2507
2508 seq_printf(m, "\nGuC submissions:\n");
2509 for_each_ring(ring, dev_priv, i) {
2510 seq_printf(m, "\t%-24s: %10llu, last seqno 0x%08x %9d\n",
2511 ring->name, guc.submissions[i],
2512 guc.last_seqno[i], guc.last_seqno[i]);
2513 total += guc.submissions[i];
2514 }
2515 seq_printf(m, "\t%s: %llu\n", "Total", total);
2516
2517 seq_printf(m, "\nGuC execbuf client @ %p:\n", guc.execbuf_client);
2518 i915_guc_client_info(m, dev_priv, &client);
2519
2520 /* Add more as required ... */
2521
2522 return 0;
2523}
2524
4c7e77fc
AD		 2525static int i915_guc_log_dump(struct seq_file *m, void *data)
2526{
2527 struct drm_info_node *node = m->private;
2528 struct drm_device *dev = node->minor->dev;
2529 struct drm_i915_private *dev_priv = dev->dev_private;
2530 struct drm_i915_gem_object *log_obj = dev_priv->guc.log_obj;
2531 u32 *log;
2532 int i = 0, pg;
2533
2534 if (!log_obj)
2535 return 0;
2536
2537 for (pg = 0; pg < log_obj->base.size / PAGE_SIZE; pg++) {
2538 log = kmap_atomic(i915_gem_object_get_page(log_obj, pg));
2539
2540 for (i = 0; i < PAGE_SIZE / sizeof(u32); i += 4)
2541 seq_printf(m, "0x%08x 0x%08x 0x%08x 0x%08x\n",
2542 *(log + i), *(log + i + 1),
2543 *(log + i + 2), *(log + i + 3));
2544
2545 kunmap_atomic(log);
2546 }
2547
2548 seq_putc(m, '\n');
2549
2550 return 0;
2551}
2552
e91fd8c6
RV		 2553static int i915_edp_psr_status(struct seq_file *m, void *data)
2554{
2555 struct drm_info_node *node = m->private;
2556 struct drm_device *dev = node->minor->dev;
2557 struct drm_i915_private *dev_priv = dev->dev_private;
a031d709 2558 u32 psrperf = 0;
a6cbdb8e
RV		 2559 u32 stat[3];
2560 enum pipe pipe;
a031d709 2561 bool enabled = false;
e91fd8c6 2562
3553a8ea
DL		 2563 if (!HAS_PSR(dev)) {
2564 seq_puts(m, "PSR not supported\n");
2565 return 0;
2566 }
2567
c8c8fb33
PZ		 2568 intel_runtime_pm_get(dev_priv);
2569
fa128fa6 2570 mutex_lock(&dev_priv->psr.lock);
a031d709
RV		 2571 seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
2572 seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
2807cf69 2573 seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
5755c78f 2574 seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
fa128fa6
DV		 2575 seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
2576 dev_priv->psr.busy_frontbuffer_bits);
2577 seq_printf(m, "Re-enable work scheduled: %s\n",
2578 yesno(work_busy(&dev_priv->psr.work.work)));
e91fd8c6 2579
3553a8ea 2580 if (HAS_DDI(dev))
443a389f 2581 enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
3553a8ea
DL		 2582 else {
2583 for_each_pipe(dev_priv, pipe) {
2584 stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
2585 VLV_EDP_PSR_CURR_STATE_MASK;
2586 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2587 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2588 enabled = true;
a6cbdb8e
RV		 2589 }
2590 }
2591 seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));
2592
2593 if (!HAS_DDI(dev))
2594 for_each_pipe(dev_priv, pipe) {
2595 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2596 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2597 seq_printf(m, " pipe %c", pipe_name(pipe));
2598 }
2599 seq_puts(m, "\n");
e91fd8c6 2600
05eec3c2
RV		 2601 /*
2602 * VLV/CHV PSR has no kind of performance counter
2603 * SKL+ Perf counter is reset to 0 everytime DC state is entered
2604 */
2605 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
443a389f 2606 psrperf = I915_READ(EDP_PSR_PERF_CNT) &
a031d709 2607 EDP_PSR_PERF_CNT_MASK;
a6cbdb8e
RV		 2608
2609 seq_printf(m, "Performance_Counter: %u\n", psrperf);
2610 }
fa128fa6 2611 mutex_unlock(&dev_priv->psr.lock);
e91fd8c6 2612
c8c8fb33 2613 intel_runtime_pm_put(dev_priv);
e91fd8c6
RV		 2614 return 0;
2615}
2616
d2e216d0
RV		 2617static int i915_sink_crc(struct seq_file *m, void *data)
2618{
2619 struct drm_info_node *node = m->private;
2620 struct drm_device *dev = node->minor->dev;
2621 struct intel_encoder *encoder;
2622 struct intel_connector *connector;
2623 struct intel_dp *intel_dp = NULL;
2624 int ret;
2625 u8 crc[6];
2626
2627 drm_modeset_lock_all(dev);
aca5e361 2628 for_each_intel_connector(dev, connector) {
d2e216d0
RV		 2629
2630 if (connector->base.dpms != DRM_MODE_DPMS_ON)
2631 continue;
2632
b6ae3c7c
PZ		 2633 if (!connector->base.encoder)
2634 continue;
2635
d2e216d0
RV		 2636 encoder = to_intel_encoder(connector->base.encoder);
2637 if (encoder->type != INTEL_OUTPUT_EDP)
2638 continue;
2639
2640 intel_dp = enc_to_intel_dp(&encoder->base);
2641
2642 ret = intel_dp_sink_crc(intel_dp, crc);
2643 if (ret)
2644 goto out;
2645
2646 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2647 crc[0], crc[1], crc[2],
2648 crc[3], crc[4], crc[5]);
2649 goto out;
2650 }
2651 ret = -ENODEV;
2652out:
2653 drm_modeset_unlock_all(dev);
2654 return ret;
2655}
2656
ec013e7f
JB		 2657static int i915_energy_uJ(struct seq_file *m, void *data)
2658{
2659 struct drm_info_node *node = m->private;
2660 struct drm_device *dev = node->minor->dev;
2661 struct drm_i915_private *dev_priv = dev->dev_private;
2662 u64 power;
2663 u32 units;
2664
2665 if (INTEL_INFO(dev)->gen < 6)
2666 return -ENODEV;
2667
36623ef8
PZ		 2668 intel_runtime_pm_get(dev_priv);
2669
ec013e7f
JB		 2670 rdmsrl(MSR_RAPL_POWER_UNIT, power);
2671 power = (power & 0x1f00) >> 8;
2672 units = 1000000 / (1 << power); /* convert to uJ */
2673 power = I915_READ(MCH_SECP_NRG_STTS);
2674 power *= units;
2675
36623ef8
PZ		 2676 intel_runtime_pm_put(dev_priv);
2677
ec013e7f 2678 seq_printf(m, "%llu", (long long unsigned)power);
371db66a
PZ		 2679
2680 return 0;
2681}
2682
6455c870 2683static int i915_runtime_pm_status(struct seq_file *m, void *unused)
371db66a 2684{
9f25d007 2685 struct drm_info_node *node = m->private;
371db66a
PZ		 2686 struct drm_device *dev = node->minor->dev;
2687 struct drm_i915_private *dev_priv = dev->dev_private;
2688
6455c870 2689 if (!HAS_RUNTIME_PM(dev)) {
371db66a
PZ		 2690 seq_puts(m, "not supported\n");
2691 return 0;
2692 }
2693
86c4ec0d 2694 seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy));
371db66a 2695 seq_printf(m, "IRQs disabled: %s\n",
9df7575f 2696 yesno(!intel_irqs_enabled(dev_priv)));
0d804184 2697#ifdef CONFIG_PM
a6aaec8b
DL		 2698 seq_printf(m, "Usage count: %d\n",
2699 atomic_read(&dev->dev->power.usage_count));
0d804184
CW		 2700#else
2701 seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n");
2702#endif
371db66a 2703
ec013e7f
JB		 2704 return 0;
2705}
2706
1da51581
ID		 2707static int i915_power_domain_info(struct seq_file *m, void *unused)
2708{
9f25d007 2709 struct drm_info_node *node = m->private;
1da51581
ID		 2710 struct drm_device *dev = node->minor->dev;
2711 struct drm_i915_private *dev_priv = dev->dev_private;
2712 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2713 int i;
2714
2715 mutex_lock(&power_domains->lock);
2716
2717 seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2718 for (i = 0; i < power_domains->power_well_count; i++) {
2719 struct i915_power_well *power_well;
2720 enum intel_display_power_domain power_domain;
2721
2722 power_well = &power_domains->power_wells[i];
2723 seq_printf(m, "%-25s %d\n", power_well->name,
2724 power_well->count);
2725
2726 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
2727 power_domain++) {
2728 if (!(BIT(power_domain) & power_well->domains))
2729 continue;
2730
2731 seq_printf(m, " %-23s %d\n",
9895ad03 2732 intel_display_power_domain_str(power_domain),
1da51581
ID		 2733 power_domains->domain_use_count[power_domain]);
2734 }
2735 }
2736
2737 mutex_unlock(&power_domains->lock);
2738
2739 return 0;
2740}
2741
b7cec66d
DL		 2742static int i915_dmc_info(struct seq_file *m, void *unused)
2743{
2744 struct drm_info_node *node = m->private;
2745 struct drm_device *dev = node->minor->dev;
2746 struct drm_i915_private *dev_priv = dev->dev_private;
2747 struct intel_csr *csr;
2748
2749 if (!HAS_CSR(dev)) {
2750 seq_puts(m, "not supported\n");
2751 return 0;
2752 }
2753
2754 csr = &dev_priv->csr;
2755
6fb403de
MK		 2756 intel_runtime_pm_get(dev_priv);
2757
b7cec66d
DL		 2758 seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload != NULL));
2759 seq_printf(m, "path: %s\n", csr->fw_path);
2760
2761 if (!csr->dmc_payload)
6fb403de 2762 goto out;
b7cec66d
DL		 2763
2764 seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
2765 CSR_VERSION_MINOR(csr->version));
2766
8337206d
DL		 2767 if (IS_SKYLAKE(dev) && csr->version >= CSR_VERSION(1, 6)) {
2768 seq_printf(m, "DC3 -> DC5 count: %d\n",
2769 I915_READ(SKL_CSR_DC3_DC5_COUNT));
2770 seq_printf(m, "DC5 -> DC6 count: %d\n",
2771 I915_READ(SKL_CSR_DC5_DC6_COUNT));
16e11b99
MK		 2772 } else if (IS_BROXTON(dev) && csr->version >= CSR_VERSION(1, 4)) {
2773 seq_printf(m, "DC3 -> DC5 count: %d\n",
2774 I915_READ(BXT_CSR_DC3_DC5_COUNT));
8337206d
DL		 2775 }
2776
6fb403de
MK		 2777out:
2778 seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0)));
2779 seq_printf(m, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE));
2780 seq_printf(m, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL));
2781
8337206d
DL		 2782 intel_runtime_pm_put(dev_priv);
2783
b7cec66d
DL		 2784 return 0;
2785}
2786
53f5e3ca
JB		 2787static void intel_seq_print_mode(struct seq_file *m, int tabs,
2788 struct drm_display_mode *mode)
2789{
2790 int i;
2791
2792 for (i = 0; i < tabs; i++)
2793 seq_putc(m, '\t');
2794
2795 seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2796 mode->base.id, mode->name,
2797 mode->vrefresh, mode->clock,
2798 mode->hdisplay, mode->hsync_start,
2799 mode->hsync_end, mode->htotal,
2800 mode->vdisplay, mode->vsync_start,
2801 mode->vsync_end, mode->vtotal,
2802 mode->type, mode->flags);
2803}
2804
2805static void intel_encoder_info(struct seq_file *m,
2806 struct intel_crtc *intel_crtc,
2807 struct intel_encoder *intel_encoder)
2808{
9f25d007 2809 struct drm_info_node *node = m->private;
53f5e3ca
JB		 2810 struct drm_device *dev = node->minor->dev;
2811 struct drm_crtc *crtc = &intel_crtc->base;
2812 struct intel_connector *intel_connector;
2813 struct drm_encoder *encoder;
2814
2815 encoder = &intel_encoder->base;
2816 seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
8e329a03 2817 encoder->base.id, encoder->name);
53f5e3ca
JB		 2818 for_each_connector_on_encoder(dev, encoder, intel_connector) {
2819 struct drm_connector *connector = &intel_connector->base;
2820 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2821 connector->base.id,
c23cc417 2822 connector->name,
53f5e3ca
JB		 2823 drm_get_connector_status_name(connector->status));
2824 if (connector->status == connector_status_connected) {
2825 struct drm_display_mode *mode = &crtc->mode;
2826 seq_printf(m, ", mode:\n");
2827 intel_seq_print_mode(m, 2, mode);
2828 } else {
2829 seq_putc(m, '\n');
2830 }
2831 }
2832}
2833
2834static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2835{
9f25d007 2836 struct drm_info_node *node = m->private;
53f5e3ca
JB		 2837 struct drm_device *dev = node->minor->dev;
2838 struct drm_crtc *crtc = &intel_crtc->base;
2839 struct intel_encoder *intel_encoder;
23a48d53
ML		 2840 struct drm_plane_state *plane_state = crtc->primary->state;
2841 struct drm_framebuffer *fb = plane_state->fb;
53f5e3ca 2842
23a48d53 2843 if (fb)
5aa8a937 2844 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
23a48d53
ML		 2845 fb->base.id, plane_state->src_x >> 16,
2846 plane_state->src_y >> 16, fb->width, fb->height);
5aa8a937
MR		 2847 else
2848 seq_puts(m, "\tprimary plane disabled\n");
53f5e3ca
JB		 2849 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2850 intel_encoder_info(m, intel_crtc, intel_encoder);
2851}
2852
2853static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2854{
2855 struct drm_display_mode *mode = panel->fixed_mode;
2856
2857 seq_printf(m, "\tfixed mode:\n");
2858 intel_seq_print_mode(m, 2, mode);
2859}
2860
2861static void intel_dp_info(struct seq_file *m,
2862 struct intel_connector *intel_connector)
2863{
2864 struct intel_encoder *intel_encoder = intel_connector->encoder;
2865 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2866
2867 seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
742f491d 2868 seq_printf(m, "\taudio support: %s\n", yesno(intel_dp->has_audio));
53f5e3ca
JB		 2869 if (intel_encoder->type == INTEL_OUTPUT_EDP)
2870 intel_panel_info(m, &intel_connector->panel);
2871}
2872
3d52ccf5
LY		 2873static void intel_dp_mst_info(struct seq_file *m,
2874 struct intel_connector *intel_connector)
2875{
2876 struct intel_encoder *intel_encoder = intel_connector->encoder;
2877 struct intel_dp_mst_encoder *intel_mst =
2878 enc_to_mst(&intel_encoder->base);
2879 struct intel_digital_port *intel_dig_port = intel_mst->primary;
2880 struct intel_dp *intel_dp = &intel_dig_port->dp;
2881 bool has_audio = drm_dp_mst_port_has_audio(&intel_dp->mst_mgr,
2882 intel_connector->port);
2883
2884 seq_printf(m, "\taudio support: %s\n", yesno(has_audio));
2885}
2886
53f5e3ca
JB		 2887static void intel_hdmi_info(struct seq_file *m,
2888 struct intel_connector *intel_connector)
2889{
2890 struct intel_encoder *intel_encoder = intel_connector->encoder;
2891 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2892
742f491d 2893 seq_printf(m, "\taudio support: %s\n", yesno(intel_hdmi->has_audio));
53f5e3ca
JB		 2894}
2895
2896static void intel_lvds_info(struct seq_file *m,
2897 struct intel_connector *intel_connector)
2898{
2899 intel_panel_info(m, &intel_connector->panel);
2900}
2901
2902static void intel_connector_info(struct seq_file *m,
2903 struct drm_connector *connector)
2904{
2905 struct intel_connector *intel_connector = to_intel_connector(connector);
2906 struct intel_encoder *intel_encoder = intel_connector->encoder;
f103fc7d 2907 struct drm_display_mode *mode;
53f5e3ca
JB		 2908
2909 seq_printf(m, "connector %d: type %s, status: %s\n",
c23cc417 2910 connector->base.id, connector->name,
53f5e3ca
JB		 2911 drm_get_connector_status_name(connector->status));
2912 if (connector->status == connector_status_connected) {
2913 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2914 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2915 connector->display_info.width_mm,
2916 connector->display_info.height_mm);
2917 seq_printf(m, "\tsubpixel order: %s\n",
2918 drm_get_subpixel_order_name(connector->display_info.subpixel_order));
2919 seq_printf(m, "\tCEA rev: %d\n",
2920 connector->display_info.cea_rev);
2921 }
36cd7444
DA		 2922 if (intel_encoder) {
2923 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2924 intel_encoder->type == INTEL_OUTPUT_EDP)
2925 intel_dp_info(m, intel_connector);
2926 else if (intel_encoder->type == INTEL_OUTPUT_HDMI)
2927 intel_hdmi_info(m, intel_connector);
2928 else if (intel_encoder->type == INTEL_OUTPUT_LVDS)
2929 intel_lvds_info(m, intel_connector);
3d52ccf5
LY		 2930 else if (intel_encoder->type == INTEL_OUTPUT_DP_MST)
2931 intel_dp_mst_info(m, intel_connector);
36cd7444 2932 }
53f5e3ca 2933
f103fc7d
JB		 2934 seq_printf(m, "\tmodes:\n");
2935 list_for_each_entry(mode, &connector->modes, head)
2936 intel_seq_print_mode(m, 2, mode);
53f5e3ca
JB		 2937}
2938
065f2ec2
CW		 2939static bool cursor_active(struct drm_device *dev, int pipe)
2940{
2941 struct drm_i915_private *dev_priv = dev->dev_private;
2942 u32 state;
2943
2944 if (IS_845G(dev) || IS_I865G(dev))
0b87c24e 2945 state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
065f2ec2 2946 else
5efb3e28 2947 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
065f2ec2
CW		 2948
2949 return state;
2950}
2951
2952static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y)
2953{
2954 struct drm_i915_private *dev_priv = dev->dev_private;
2955 u32 pos;
2956
5efb3e28 2957 pos = I915_READ(CURPOS(pipe));
065f2ec2
CW		 2958
2959 *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
2960 if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
2961 *x = -*x;
2962
2963 *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
2964 if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
2965 *y = -*y;
2966
2967 return cursor_active(dev, pipe);
2968}
2969
3abc4e09
RF		 2970static const char *plane_type(enum drm_plane_type type)
2971{
2972 switch (type) {
2973 case DRM_PLANE_TYPE_OVERLAY:
2974 return "OVL";
2975 case DRM_PLANE_TYPE_PRIMARY:
2976 return "PRI";
2977 case DRM_PLANE_TYPE_CURSOR:
2978 return "CUR";
2979 /*
2980 * Deliberately omitting default: to generate compiler warnings
2981 * when a new drm_plane_type gets added.
2982 */
2983 }
2984
2985 return "unknown";
2986}
2987
2988static const char *plane_rotation(unsigned int rotation)
2989{
2990 static char buf[48];
2991 /*
2992 * According to doc only one DRM_ROTATE_ is allowed but this
2993 * will print them all to visualize if the values are misused
2994 */
2995 snprintf(buf, sizeof(buf),
2996 "%s%s%s%s%s%s(0x%08x)",
2997 (rotation & BIT(DRM_ROTATE_0)) ? "0 " : "",
2998 (rotation & BIT(DRM_ROTATE_90)) ? "90 " : "",
2999 (rotation & BIT(DRM_ROTATE_180)) ? "180 " : "",
3000 (rotation & BIT(DRM_ROTATE_270)) ? "270 " : "",
3001 (rotation & BIT(DRM_REFLECT_X)) ? "FLIPX " : "",
3002 (rotation & BIT(DRM_REFLECT_Y)) ? "FLIPY " : "",
3003 rotation);
3004
3005 return buf;
3006}
3007
3008static void intel_plane_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3009{
3010 struct drm_info_node *node = m->private;
3011 struct drm_device *dev = node->minor->dev;
3012 struct intel_plane *intel_plane;
3013
3014 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3015 struct drm_plane_state *state;
3016 struct drm_plane *plane = &intel_plane->base;
3017
3018 if (!plane->state) {
3019 seq_puts(m, "plane->state is NULL!\n");
3020 continue;
3021 }
3022
3023 state = plane->state;
3024
3025 seq_printf(m, "\t--Plane id %d: type=%s, crtc_pos=%4dx%4d, crtc_size=%4dx%4d, src_pos=%d.%04ux%d.%04u, src_size=%d.%04ux%d.%04u, format=%s, rotation=%s\n",
3026 plane->base.id,
3027 plane_type(intel_plane->base.type),
3028 state->crtc_x, state->crtc_y,
3029 state->crtc_w, state->crtc_h,
3030 (state->src_x >> 16),
3031 ((state->src_x & 0xffff) * 15625) >> 10,
3032 (state->src_y >> 16),
3033 ((state->src_y & 0xffff) * 15625) >> 10,
3034 (state->src_w >> 16),
3035 ((state->src_w & 0xffff) * 15625) >> 10,
3036 (state->src_h >> 16),
3037 ((state->src_h & 0xffff) * 15625) >> 10,
3038 state->fb ? drm_get_format_name(state->fb->pixel_format) : "N/A",
3039 plane_rotation(state->rotation));
3040 }
3041}
3042
3043static void intel_scaler_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3044{
3045 struct intel_crtc_state *pipe_config;
3046 int num_scalers = intel_crtc->num_scalers;
3047 int i;
3048
3049 pipe_config = to_intel_crtc_state(intel_crtc->base.state);
3050
3051 /* Not all platformas have a scaler */
3052 if (num_scalers) {
3053 seq_printf(m, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d",
3054 num_scalers,
3055 pipe_config->scaler_state.scaler_users,
3056 pipe_config->scaler_state.scaler_id);
3057
3058 for (i = 0; i < SKL_NUM_SCALERS; i++) {
3059 struct intel_scaler *sc =
3060 &pipe_config->scaler_state.scalers[i];
3061
3062 seq_printf(m, ", scalers[%d]: use=%s, mode=%x",
3063 i, yesno(sc->in_use), sc->mode);
3064 }
3065 seq_puts(m, "\n");
3066 } else {
3067 seq_puts(m, "\tNo scalers available on this platform\n");
3068 }
3069}
3070
53f5e3ca
JB		 3071static int i915_display_info(struct seq_file *m, void *unused)
3072{
9f25d007 3073 struct drm_info_node *node = m->private;
53f5e3ca 3074 struct drm_device *dev = node->minor->dev;
b0e5ddf3 3075 struct drm_i915_private *dev_priv = dev->dev_private;
065f2ec2 3076 struct intel_crtc *crtc;
53f5e3ca
JB		 3077 struct drm_connector *connector;
3078
b0e5ddf3 3079 intel_runtime_pm_get(dev_priv);
53f5e3ca
JB		 3080 drm_modeset_lock_all(dev);
3081 seq_printf(m, "CRTC info\n");
3082 seq_printf(m, "---------\n");
d3fcc808 3083 for_each_intel_crtc(dev, crtc) {
065f2ec2 3084 bool active;
f77076c9 3085 struct intel_crtc_state *pipe_config;
065f2ec2 3086 int x, y;
53f5e3ca 3087
f77076c9
ML		 3088 pipe_config = to_intel_crtc_state(crtc->base.state);
3089
3abc4e09 3090 seq_printf(m, "CRTC %d: pipe: %c, active=%s, (size=%dx%d), dither=%s, bpp=%d\n",
065f2ec2 3091 crtc->base.base.id, pipe_name(crtc->pipe),
f77076c9 3092 yesno(pipe_config->base.active),
3abc4e09
RF		 3093 pipe_config->pipe_src_w, pipe_config->pipe_src_h,
3094 yesno(pipe_config->dither), pipe_config->pipe_bpp);
3095
f77076c9 3096 if (pipe_config->base.active) {
065f2ec2
CW		 3097 intel_crtc_info(m, crtc);
3098
a23dc658 3099 active = cursor_position(dev, crtc->pipe, &x, &y);
57127efa 3100 seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
4b0e333e 3101 yesno(crtc->cursor_base),
3dd512fb
MR		 3102 x, y, crtc->base.cursor->state->crtc_w,
3103 crtc->base.cursor->state->crtc_h,
57127efa 3104 crtc->cursor_addr, yesno(active));
3abc4e09
RF		 3105 intel_scaler_info(m, crtc);
3106 intel_plane_info(m, crtc);
a23dc658 3107 }
cace841c
DV		 3108
3109 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
3110 yesno(!crtc->cpu_fifo_underrun_disabled),
3111 yesno(!crtc->pch_fifo_underrun_disabled));
53f5e3ca
JB		 3112 }
3113
3114 seq_printf(m, "\n");
3115 seq_printf(m, "Connector info\n");
3116 seq_printf(m, "--------------\n");
3117 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3118 intel_connector_info(m, connector);
3119 }
3120 drm_modeset_unlock_all(dev);
b0e5ddf3 3121 intel_runtime_pm_put(dev_priv);
53f5e3ca
JB		 3122
3123 return 0;
3124}
3125
e04934cf
BW		 3126static int i915_semaphore_status(struct seq_file *m, void *unused)
3127{
3128 struct drm_info_node *node = (struct drm_info_node *) m->private;
3129 struct drm_device *dev = node->minor->dev;
3130 struct drm_i915_private *dev_priv = dev->dev_private;
3131 struct intel_engine_cs *ring;
3132 int num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
3133 int i, j, ret;
3134
3135 if (!i915_semaphore_is_enabled(dev)) {
3136 seq_puts(m, "Semaphores are disabled\n");
3137 return 0;
3138 }
3139
3140 ret = mutex_lock_interruptible(&dev->struct_mutex);
3141 if (ret)
3142 return ret;
03872064 3143 intel_runtime_pm_get(dev_priv);
e04934cf
BW		 3144
3145 if (IS_BROADWELL(dev)) {
3146 struct page *page;
3147 uint64_t *seqno;
3148
3149 page = i915_gem_object_get_page(dev_priv->semaphore_obj, 0);
3150
3151 seqno = (uint64_t *)kmap_atomic(page);
3152 for_each_ring(ring, dev_priv, i) {
3153 uint64_t offset;
3154
3155 seq_printf(m, "%s\n", ring->name);
3156
3157 seq_puts(m, " Last signal:");
3158 for (j = 0; j < num_rings; j++) {
3159 offset = i * I915_NUM_RINGS + j;
3160 seq_printf(m, "0x%08llx (0x%02llx) ",
3161 seqno[offset], offset * 8);
3162 }
3163 seq_putc(m, '\n');
3164
3165 seq_puts(m, " Last wait: ");
3166 for (j = 0; j < num_rings; j++) {
3167 offset = i + (j * I915_NUM_RINGS);
3168 seq_printf(m, "0x%08llx (0x%02llx) ",
3169 seqno[offset], offset * 8);
3170 }
3171 seq_putc(m, '\n');
3172
3173 }
3174 kunmap_atomic(seqno);
3175 } else {
3176 seq_puts(m, " Last signal:");
3177 for_each_ring(ring, dev_priv, i)
3178 for (j = 0; j < num_rings; j++)
3179 seq_printf(m, "0x%08x\n",
3180 I915_READ(ring->semaphore.mbox.signal[j]));
3181 seq_putc(m, '\n');
3182 }
3183
3184 seq_puts(m, "\nSync seqno:\n");
3185 for_each_ring(ring, dev_priv, i) {
3186 for (j = 0; j < num_rings; j++) {
3187 seq_printf(m, " 0x%08x ", ring->semaphore.sync_seqno[j]);
3188 }
3189 seq_putc(m, '\n');
3190 }
3191 seq_putc(m, '\n');
3192
03872064 3193 intel_runtime_pm_put(dev_priv);
e04934cf
BW		 3194 mutex_unlock(&dev->struct_mutex);
3195 return 0;
3196}
3197
728e29d7
DV		 3198static int i915_shared_dplls_info(struct seq_file *m, void *unused)
3199{
3200 struct drm_info_node *node = (struct drm_info_node *) m->private;
3201 struct drm_device *dev = node->minor->dev;
3202 struct drm_i915_private *dev_priv = dev->dev_private;
3203 int i;
3204
3205 drm_modeset_lock_all(dev);
3206 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3207 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
3208
3209 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
1e6f2ddc 3210 seq_printf(m, " crtc_mask: 0x%08x, active: %d, on: %s\n",
3e369b76 3211 pll->config.crtc_mask, pll->active, yesno(pll->on));
728e29d7 3212 seq_printf(m, " tracked hardware state:\n");
3e369b76
ACO		 3213 seq_printf(m, " dpll: 0x%08x\n", pll->config.hw_state.dpll);
3214 seq_printf(m, " dpll_md: 0x%08x\n",
3215 pll->config.hw_state.dpll_md);
3216 seq_printf(m, " fp0: 0x%08x\n", pll->config.hw_state.fp0);
3217 seq_printf(m, " fp1: 0x%08x\n", pll->config.hw_state.fp1);
3218 seq_printf(m, " wrpll: 0x%08x\n", pll->config.hw_state.wrpll);
728e29d7
DV		 3219 }
3220 drm_modeset_unlock_all(dev);
3221
3222 return 0;
3223}
3224
1ed1ef9d 3225static int i915_wa_registers(struct seq_file *m, void *unused)
888b5995
AS		 3226{
3227 int i;
3228 int ret;
3229 struct drm_info_node *node = (struct drm_info_node *) m->private;
3230 struct drm_device *dev = node->minor->dev;
3231 struct drm_i915_private *dev_priv = dev->dev_private;
3232
888b5995
AS		 3233 ret = mutex_lock_interruptible(&dev->struct_mutex);
3234 if (ret)
3235 return ret;
3236
3237 intel_runtime_pm_get(dev_priv);
3238
7225342a
MK		 3239 seq_printf(m, "Workarounds applied: %d\n", dev_priv->workarounds.count);
3240 for (i = 0; i < dev_priv->workarounds.count; ++i) {
f0f59a00
VS		 3241 i915_reg_t addr;
3242 u32 mask, value, read;
2fa60f6d 3243 bool ok;
888b5995 3244
7225342a
MK		 3245 addr = dev_priv->workarounds.reg[i].addr;
3246 mask = dev_priv->workarounds.reg[i].mask;
2fa60f6d
MK		 3247 value = dev_priv->workarounds.reg[i].value;
3248 read = I915_READ(addr);
3249 ok = (value & mask) == (read & mask);
3250 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
f0f59a00 3251 i915_mmio_reg_offset(addr), value, mask, read, ok ? "OK" : "FAIL");
888b5995
AS		 3252 }
3253
3254 intel_runtime_pm_put(dev_priv);
3255 mutex_unlock(&dev->struct_mutex);
3256
3257 return 0;
3258}
3259
c5511e44
DL		 3260static int i915_ddb_info(struct seq_file *m, void *unused)
3261{
3262 struct drm_info_node *node = m->private;
3263 struct drm_device *dev = node->minor->dev;
3264 struct drm_i915_private *dev_priv = dev->dev_private;
3265 struct skl_ddb_allocation *ddb;
3266 struct skl_ddb_entry *entry;
3267 enum pipe pipe;
3268 int plane;
3269
2fcffe19
DL		 3270 if (INTEL_INFO(dev)->gen < 9)
3271 return 0;
3272
c5511e44
DL		 3273 drm_modeset_lock_all(dev);
3274
3275 ddb = &dev_priv->wm.skl_hw.ddb;
3276
3277 seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
3278
3279 for_each_pipe(dev_priv, pipe) {
3280 seq_printf(m, "Pipe %c\n", pipe_name(pipe));
3281
dd740780 3282 for_each_plane(dev_priv, pipe, plane) {
c5511e44
DL		 3283 entry = &ddb->plane[pipe][plane];
3284 seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane + 1,
3285 entry->start, entry->end,
3286 skl_ddb_entry_size(entry));
3287 }
3288
4969d33e 3289 entry = &ddb->plane[pipe][PLANE_CURSOR];
c5511e44
DL		 3290 seq_printf(m, " %-13s%8u%8u%8u\n", "Cursor", entry->start,
3291 entry->end, skl_ddb_entry_size(entry));
3292 }
3293
3294 drm_modeset_unlock_all(dev);
3295
3296 return 0;
3297}
3298
a54746e3
VK		 3299static void drrs_status_per_crtc(struct seq_file *m,
3300 struct drm_device *dev, struct intel_crtc *intel_crtc)
3301{
3302 struct intel_encoder *intel_encoder;
3303 struct drm_i915_private *dev_priv = dev->dev_private;
3304 struct i915_drrs *drrs = &dev_priv->drrs;
3305 int vrefresh = 0;
3306
3307 for_each_encoder_on_crtc(dev, &intel_crtc->base, intel_encoder) {
3308 /* Encoder connected on this CRTC */
3309 switch (intel_encoder->type) {
3310 case INTEL_OUTPUT_EDP:
3311 seq_puts(m, "eDP:\n");
3312 break;
3313 case INTEL_OUTPUT_DSI:
3314 seq_puts(m, "DSI:\n");
3315 break;
3316 case INTEL_OUTPUT_HDMI:
3317 seq_puts(m, "HDMI:\n");
3318 break;
3319 case INTEL_OUTPUT_DISPLAYPORT:
3320 seq_puts(m, "DP:\n");
3321 break;
3322 default:
3323 seq_printf(m, "Other encoder (id=%d).\n",
3324 intel_encoder->type);
3325 return;
3326 }
3327 }
3328
3329 if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT)
3330 seq_puts(m, "\tVBT: DRRS_type: Static");
3331 else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT)
3332 seq_puts(m, "\tVBT: DRRS_type: Seamless");
3333 else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED)
3334 seq_puts(m, "\tVBT: DRRS_type: None");
3335 else
3336 seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value");
3337
3338 seq_puts(m, "\n\n");
3339
f77076c9 3340 if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) {
a54746e3
VK		 3341 struct intel_panel *panel;
3342
3343 mutex_lock(&drrs->mutex);
3344 /* DRRS Supported */
3345 seq_puts(m, "\tDRRS Supported: Yes\n");
3346
3347 /* disable_drrs() will make drrs->dp NULL */
3348 if (!drrs->dp) {
3349 seq_puts(m, "Idleness DRRS: Disabled");
3350 mutex_unlock(&drrs->mutex);
3351 return;
3352 }
3353
3354 panel = &drrs->dp->attached_connector->panel;
3355 seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X",
3356 drrs->busy_frontbuffer_bits);
3357
3358 seq_puts(m, "\n\t\t");
3359 if (drrs->refresh_rate_type == DRRS_HIGH_RR) {
3360 seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n");
3361 vrefresh = panel->fixed_mode->vrefresh;
3362 } else if (drrs->refresh_rate_type == DRRS_LOW_RR) {
3363 seq_puts(m, "DRRS_State: DRRS_LOW_RR\n");
3364 vrefresh = panel->downclock_mode->vrefresh;
3365 } else {
3366 seq_printf(m, "DRRS_State: Unknown(%d)\n",
3367 drrs->refresh_rate_type);
3368 mutex_unlock(&drrs->mutex);
3369 return;
3370 }
3371 seq_printf(m, "\t\tVrefresh: %d", vrefresh);
3372
3373 seq_puts(m, "\n\t\t");
3374 mutex_unlock(&drrs->mutex);
3375 } else {
3376 /* DRRS not supported. Print the VBT parameter*/
3377 seq_puts(m, "\tDRRS Supported : No");
3378 }
3379 seq_puts(m, "\n");
3380}
3381
3382static int i915_drrs_status(struct seq_file *m, void *unused)
3383{
3384 struct drm_info_node *node = m->private;
3385 struct drm_device *dev = node->minor->dev;
3386 struct intel_crtc *intel_crtc;
3387 int active_crtc_cnt = 0;
3388
3389 for_each_intel_crtc(dev, intel_crtc) {
3390 drm_modeset_lock(&intel_crtc->base.mutex, NULL);
3391
f77076c9 3392 if (intel_crtc->base.state->active) {
a54746e3
VK		 3393 active_crtc_cnt++;
3394 seq_printf(m, "\nCRTC %d: ", active_crtc_cnt);
3395
3396 drrs_status_per_crtc(m, dev, intel_crtc);
3397 }
3398
3399 drm_modeset_unlock(&intel_crtc->base.mutex);
3400 }
3401
3402 if (!active_crtc_cnt)
3403 seq_puts(m, "No active crtc found\n");
3404
3405 return 0;
3406}
3407
07144428
DL		 3408struct pipe_crc_info {
3409 const char *name;
3410 struct drm_device *dev;
3411 enum pipe pipe;
3412};
3413
11bed958
DA		 3414static int i915_dp_mst_info(struct seq_file *m, void *unused)
3415{
3416 struct drm_info_node *node = (struct drm_info_node *) m->private;
3417 struct drm_device *dev = node->minor->dev;
3418 struct drm_encoder *encoder;
3419 struct intel_encoder *intel_encoder;
3420 struct intel_digital_port *intel_dig_port;
3421 drm_modeset_lock_all(dev);
3422 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3423 intel_encoder = to_intel_encoder(encoder);
3424 if (intel_encoder->type != INTEL_OUTPUT_DISPLAYPORT)
3425 continue;
3426 intel_dig_port = enc_to_dig_port(encoder);
3427 if (!intel_dig_port->dp.can_mst)
3428 continue;
3429
3430 drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr);
3431 }
3432 drm_modeset_unlock_all(dev);
3433 return 0;
3434}
3435
07144428
DL		 3436static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
3437{
be5c7a90
DL		 3438 struct pipe_crc_info *info = inode->i_private;
3439 struct drm_i915_private *dev_priv = info->dev->dev_private;
3440 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3441
7eb1c496
DV		 3442 if (info->pipe >= INTEL_INFO(info->dev)->num_pipes)
3443 return -ENODEV;
3444
d538bbdf
DL		 3445 spin_lock_irq(&pipe_crc->lock);
3446
3447 if (pipe_crc->opened) {
3448 spin_unlock_irq(&pipe_crc->lock);
be5c7a90
DL		 3449 return -EBUSY; /* already open */
3450 }
3451
d538bbdf 3452 pipe_crc->opened = true;
07144428
DL		 3453 filep->private_data = inode->i_private;
3454
d538bbdf
DL		 3455 spin_unlock_irq(&pipe_crc->lock);
3456
07144428
DL		 3457 return 0;
3458}
3459
3460static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
3461{
be5c7a90
DL		 3462 struct pipe_crc_info *info = inode->i_private;
3463 struct drm_i915_private *dev_priv = info->dev->dev_private;
3464 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3465
d538bbdf
DL		 3466 spin_lock_irq(&pipe_crc->lock);
3467 pipe_crc->opened = false;
3468 spin_unlock_irq(&pipe_crc->lock);
be5c7a90 3469
07144428
DL		 3470 return 0;
3471}
3472
3473/* (6 fields, 8 chars each, space separated (5) + '\n') */
3474#define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
3475/* account for \'0' */
3476#define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1)
3477
3478static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
8bf1e9f1 3479{
d538bbdf
DL		 3480 assert_spin_locked(&pipe_crc->lock);
3481 return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3482 INTEL_PIPE_CRC_ENTRIES_NR);
07144428
DL		 3483}
3484
3485static ssize_t
3486i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
3487 loff_t *pos)
3488{
3489 struct pipe_crc_info *info = filep->private_data;
3490 struct drm_device *dev = info->dev;
3491 struct drm_i915_private *dev_priv = dev->dev_private;
3492 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3493 char buf[PIPE_CRC_BUFFER_LEN];
9ad6d99f 3494 int n_entries;
07144428
DL		 3495 ssize_t bytes_read;
3496
3497 /*
3498 * Don't allow user space to provide buffers not big enough to hold
3499 * a line of data.
3500 */
3501 if (count < PIPE_CRC_LINE_LEN)
3502 return -EINVAL;
3503
3504 if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
8bf1e9f1 3505 return 0;
07144428
DL		 3506
3507 /* nothing to read */
d538bbdf 3508 spin_lock_irq(&pipe_crc->lock);
07144428 3509 while (pipe_crc_data_count(pipe_crc) == 0) {
d538bbdf
DL		 3510 int ret;
3511
3512 if (filep->f_flags & O_NONBLOCK) {
3513 spin_unlock_irq(&pipe_crc->lock);
07144428 3514 return -EAGAIN;
d538bbdf 3515 }
07144428 3516
d538bbdf
DL		 3517 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
3518 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
3519 if (ret) {
3520 spin_unlock_irq(&pipe_crc->lock);
3521 return ret;
3522 }
8bf1e9f1
SH		 3523 }
3524
07144428 3525 /* We now have one or more entries to read */
9ad6d99f 3526 n_entries = count / PIPE_CRC_LINE_LEN;
d538bbdf 3527
07144428 3528 bytes_read = 0;
9ad6d99f
VS		 3529 while (n_entries > 0) {
3530 struct intel_pipe_crc_entry *entry =
3531 &pipe_crc->entries[pipe_crc->tail];
07144428 3532 int ret;
8bf1e9f1 3533
9ad6d99f
VS		 3534 if (CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3535 INTEL_PIPE_CRC_ENTRIES_NR) < 1)
3536 break;
3537
3538 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
3539 pipe_crc->tail = (pipe_crc->tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
3540
07144428
DL		 3541 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
3542 "%8u %8x %8x %8x %8x %8x\n",
3543 entry->frame, entry->crc[0],
3544 entry->crc[1], entry->crc[2],
3545 entry->crc[3], entry->crc[4]);
3546
9ad6d99f
VS		 3547 spin_unlock_irq(&pipe_crc->lock);
3548
3549 ret = copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN);
07144428
DL		 3550 if (ret == PIPE_CRC_LINE_LEN)
3551 return -EFAULT;
b2c88f5b 3552
9ad6d99f
VS		 3553 user_buf += PIPE_CRC_LINE_LEN;
3554 n_entries--;
3555
3556 spin_lock_irq(&pipe_crc->lock);
3557 }
8bf1e9f1 3558
d538bbdf
DL		 3559 spin_unlock_irq(&pipe_crc->lock);
3560
07144428
DL		 3561 return bytes_read;
3562}
3563
3564static const struct file_operations i915_pipe_crc_fops = {
3565 .owner = THIS_MODULE,
3566 .open = i915_pipe_crc_open,
3567 .read = i915_pipe_crc_read,
3568 .release = i915_pipe_crc_release,
3569};
3570
3571static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
3572 {
3573 .name = "i915_pipe_A_crc",
3574 .pipe = PIPE_A,
3575 },
3576 {
3577 .name = "i915_pipe_B_crc",
3578 .pipe = PIPE_B,
3579 },
3580 {
3581 .name = "i915_pipe_C_crc",
3582 .pipe = PIPE_C,
3583 },
3584};
3585
3586static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
3587 enum pipe pipe)
3588{
3589 struct drm_device *dev = minor->dev;
3590 struct dentry *ent;
3591 struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
3592
3593 info->dev = dev;
3594 ent = debugfs_create_file(info->name, S_IRUGO, root, info,
3595 &i915_pipe_crc_fops);
f3c5fe97
WY		 3596 if (!ent)
3597 return -ENOMEM;
07144428
DL		 3598
3599 return drm_add_fake_info_node(minor, ent, info);
8bf1e9f1
SH		 3600}
3601
e8dfcf78 3602static const char * const pipe_crc_sources[] = {
926321d5
DV		 3603 "none",
3604 "plane1",
3605 "plane2",
3606 "pf",
5b3a856b 3607 "pipe",
3d099a05
DV		 3608 "TV",
3609 "DP-B",
3610 "DP-C",
3611 "DP-D",
46a19188 3612 "auto",
926321d5
DV		 3613};
3614
3615static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
3616{
3617 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
3618 return pipe_crc_sources[source];
3619}
3620
bd9db02f 3621static int display_crc_ctl_show(struct seq_file *m, void *data)
926321d5
DV		 3622{
3623 struct drm_device *dev = m->private;
3624 struct drm_i915_private *dev_priv = dev->dev_private;
3625 int i;
3626
3627 for (i = 0; i < I915_MAX_PIPES; i++)
3628 seq_printf(m, "%c %s\n", pipe_name(i),
3629 pipe_crc_source_name(dev_priv->pipe_crc[i].source));
3630
3631 return 0;
3632}
3633
bd9db02f 3634static int display_crc_ctl_open(struct inode *inode, struct file *file)
926321d5
DV		 3635{
3636 struct drm_device *dev = inode->i_private;
3637
bd9db02f 3638 return single_open(file, display_crc_ctl_show, dev);
926321d5
DV		 3639}
3640
46a19188 3641static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
52f843f6
DV		 3642 uint32_t *val)
3643{
46a19188
DV		 3644 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3645 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3646
3647 switch (*source) {
52f843f6
DV		 3648 case INTEL_PIPE_CRC_SOURCE_PIPE:
3649 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
3650 break;
3651 case INTEL_PIPE_CRC_SOURCE_NONE:
3652 *val = 0;
3653 break;
3654 default:
3655 return -EINVAL;
3656 }
3657
3658 return 0;
3659}
3660
46a19188
DV		 3661static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe,
3662 enum intel_pipe_crc_source *source)
3663{
3664 struct intel_encoder *encoder;
3665 struct intel_crtc *crtc;
26756809 3666 struct intel_digital_port *dig_port;
46a19188
DV		 3667 int ret = 0;
3668
3669 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3670
6e9f798d 3671 drm_modeset_lock_all(dev);
b2784e15 3672 for_each_intel_encoder(dev, encoder) {
46a19188
DV		 3673 if (!encoder->base.crtc)
3674 continue;
3675
3676 crtc = to_intel_crtc(encoder->base.crtc);
3677
3678 if (crtc->pipe != pipe)
3679 continue;
3680
3681 switch (encoder->type) {
3682 case INTEL_OUTPUT_TVOUT:
3683 *source = INTEL_PIPE_CRC_SOURCE_TV;
3684 break;
3685 case INTEL_OUTPUT_DISPLAYPORT:
3686 case INTEL_OUTPUT_EDP:
26756809
DV		 3687 dig_port = enc_to_dig_port(&encoder->base);
3688 switch (dig_port->port) {
3689 case PORT_B:
3690 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
3691 break;
3692 case PORT_C:
3693 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
3694 break;
3695 case PORT_D:
3696 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
3697 break;
3698 default:
3699 WARN(1, "nonexisting DP port %c\n",
3700 port_name(dig_port->port));
3701 break;
3702 }
46a19188 3703 break;
6847d71b
PZ		 3704 default:
3705 break;
46a19188
DV		 3706 }
3707 }
6e9f798d 3708 drm_modeset_unlock_all(dev);
46a19188
DV		 3709
3710 return ret;
3711}
3712
3713static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
3714 enum pipe pipe,
3715 enum intel_pipe_crc_source *source,
7ac0129b
DV		 3716 uint32_t *val)
3717{
8d2f24ca
DV		 3718 struct drm_i915_private *dev_priv = dev->dev_private;
3719 bool need_stable_symbols = false;
3720
46a19188
DV		 3721 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3722 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3723 if (ret)
3724 return ret;
3725 }
3726
3727 switch (*source) {
7ac0129b
DV		 3728 case INTEL_PIPE_CRC_SOURCE_PIPE:
3729 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
3730 break;
3731 case INTEL_PIPE_CRC_SOURCE_DP_B:
3732 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
8d2f24ca 3733 need_stable_symbols = true;
7ac0129b
DV		 3734 break;
3735 case INTEL_PIPE_CRC_SOURCE_DP_C:
3736 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
8d2f24ca 3737 need_stable_symbols = true;
7ac0129b 3738 break;
2be57922
VS		 3739 case INTEL_PIPE_CRC_SOURCE_DP_D:
3740 if (!IS_CHERRYVIEW(dev))
3741 return -EINVAL;
3742 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV;
3743 need_stable_symbols = true;
3744 break;
7ac0129b
DV		 3745 case INTEL_PIPE_CRC_SOURCE_NONE:
3746 *val = 0;
3747 break;
3748 default:
3749 return -EINVAL;
3750 }
3751
8d2f24ca
DV		 3752 /*
3753 * When the pipe CRC tap point is after the transcoders we need
3754 * to tweak symbol-level features to produce a deterministic series of
3755 * symbols for a given frame. We need to reset those features only once
3756 * a frame (instead of every nth symbol):
3757 * - DC-balance: used to ensure a better clock recovery from the data
3758 * link (SDVO)
3759 * - DisplayPort scrambling: used for EMI reduction
3760 */
3761 if (need_stable_symbols) {
3762 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3763
8d2f24ca 3764 tmp |= DC_BALANCE_RESET_VLV;
eb736679
VS		 3765 switch (pipe) {
3766 case PIPE_A:
8d2f24ca 3767 tmp |= PIPE_A_SCRAMBLE_RESET;
eb736679
VS		 3768 break;
3769 case PIPE_B:
8d2f24ca 3770 tmp |= PIPE_B_SCRAMBLE_RESET;
eb736679
VS		 3771 break;
3772 case PIPE_C:
3773 tmp |= PIPE_C_SCRAMBLE_RESET;
3774 break;
3775 default:
3776 return -EINVAL;
3777 }
8d2f24ca
DV		 3778 I915_WRITE(PORT_DFT2_G4X, tmp);
3779 }
3780
7ac0129b
DV		 3781 return 0;
3782}
3783
4b79ebf7 3784static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
46a19188
DV		 3785 enum pipe pipe,
3786 enum intel_pipe_crc_source *source,
4b79ebf7
DV		 3787 uint32_t *val)
3788{
84093603
DV		 3789 struct drm_i915_private *dev_priv = dev->dev_private;
3790 bool need_stable_symbols = false;
3791
46a19188
DV		 3792 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3793 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3794 if (ret)
3795 return ret;
3796 }
3797
3798 switch (*source) {
4b79ebf7
DV		 3799 case INTEL_PIPE_CRC_SOURCE_PIPE:
3800 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
3801 break;
3802 case INTEL_PIPE_CRC_SOURCE_TV:
3803 if (!SUPPORTS_TV(dev))
3804 return -EINVAL;
3805 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
3806 break;
3807 case INTEL_PIPE_CRC_SOURCE_DP_B:
3808 if (!IS_G4X(dev))
3809 return -EINVAL;
3810 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
84093603 3811 need_stable_symbols = true;
4b79ebf7
DV		 3812 break;
3813 case INTEL_PIPE_CRC_SOURCE_DP_C:
3814 if (!IS_G4X(dev))
3815 return -EINVAL;
3816 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
84093603 3817 need_stable_symbols = true;
4b79ebf7
DV		 3818 break;
3819 case INTEL_PIPE_CRC_SOURCE_DP_D:
3820 if (!IS_G4X(dev))
3821 return -EINVAL;
3822 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
84093603 3823 need_stable_symbols = true;
4b79ebf7
DV		 3824 break;
3825 case INTEL_PIPE_CRC_SOURCE_NONE:
3826 *val = 0;
3827 break;
3828 default:
3829 return -EINVAL;
3830 }
3831
84093603
DV		 3832 /*
3833 * When the pipe CRC tap point is after the transcoders we need
3834 * to tweak symbol-level features to produce a deterministic series of
3835 * symbols for a given frame. We need to reset those features only once
3836 * a frame (instead of every nth symbol):
3837 * - DC-balance: used to ensure a better clock recovery from the data
3838 * link (SDVO)
3839 * - DisplayPort scrambling: used for EMI reduction
3840 */
3841 if (need_stable_symbols) {
3842 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3843
3844 WARN_ON(!IS_G4X(dev));
3845
3846 I915_WRITE(PORT_DFT_I9XX,
3847 I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
3848
3849 if (pipe == PIPE_A)
3850 tmp |= PIPE_A_SCRAMBLE_RESET;
3851 else
3852 tmp |= PIPE_B_SCRAMBLE_RESET;
3853
3854 I915_WRITE(PORT_DFT2_G4X, tmp);
3855 }
3856
4b79ebf7
DV		 3857 return 0;
3858}
3859
8d2f24ca
DV		 3860static void vlv_undo_pipe_scramble_reset(struct drm_device *dev,
3861 enum pipe pipe)
3862{
3863 struct drm_i915_private *dev_priv = dev->dev_private;
3864 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3865
eb736679
VS		 3866 switch (pipe) {
3867 case PIPE_A:
8d2f24ca 3868 tmp &= ~PIPE_A_SCRAMBLE_RESET;
eb736679
VS		 3869 break;
3870 case PIPE_B:
8d2f24ca 3871 tmp &= ~PIPE_B_SCRAMBLE_RESET;
eb736679
VS		 3872 break;
3873 case PIPE_C:
3874 tmp &= ~PIPE_C_SCRAMBLE_RESET;
3875 break;
3876 default:
3877 return;
3878 }
8d2f24ca
DV		 3879 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
3880 tmp &= ~DC_BALANCE_RESET_VLV;
3881 I915_WRITE(PORT_DFT2_G4X, tmp);
3882
3883}
3884
84093603
DV		 3885static void g4x_undo_pipe_scramble_reset(struct drm_device *dev,
3886 enum pipe pipe)
3887{
3888 struct drm_i915_private *dev_priv = dev->dev_private;
3889 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3890
3891 if (pipe == PIPE_A)
3892 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3893 else
3894 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3895 I915_WRITE(PORT_DFT2_G4X, tmp);
3896
3897 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
3898 I915_WRITE(PORT_DFT_I9XX,
3899 I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
3900 }
3901}
3902
46a19188 3903static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
5b3a856b
DV		 3904 uint32_t *val)
3905{
46a19188
DV		 3906 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3907 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3908
3909 switch (*source) {
5b3a856b
DV		 3910 case INTEL_PIPE_CRC_SOURCE_PLANE1:
3911 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
3912 break;
3913 case INTEL_PIPE_CRC_SOURCE_PLANE2:
3914 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
3915 break;
5b3a856b
DV		 3916 case INTEL_PIPE_CRC_SOURCE_PIPE:
3917 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
3918 break;
3d099a05 3919 case INTEL_PIPE_CRC_SOURCE_NONE:
5b3a856b
DV		 3920 *val = 0;
3921 break;
3d099a05
DV		 3922 default:
3923 return -EINVAL;
5b3a856b
DV		 3924 }
3925
3926 return 0;
3927}
3928
c4e2d043 3929static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device *dev, bool enable)
fabf6e51
DV		 3930{
3931 struct drm_i915_private *dev_priv = dev->dev_private;
3932 struct intel_crtc *crtc =
3933 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
f77076c9 3934 struct intel_crtc_state *pipe_config;
c4e2d043
ML		 3935 struct drm_atomic_state *state;
3936 int ret = 0;
fabf6e51
DV		 3937
3938 drm_modeset_lock_all(dev);
c4e2d043
ML		 3939 state = drm_atomic_state_alloc(dev);
3940 if (!state) {
3941 ret = -ENOMEM;
3942 goto out;
fabf6e51 3943 }
fabf6e51 3944
c4e2d043
ML		 3945 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(&crtc->base);
3946 pipe_config = intel_atomic_get_crtc_state(state, crtc);
3947 if (IS_ERR(pipe_config)) {
3948 ret = PTR_ERR(pipe_config);
3949 goto out;
3950 }
fabf6e51 3951
c4e2d043
ML		 3952 pipe_config->pch_pfit.force_thru = enable;
3953 if (pipe_config->cpu_transcoder == TRANSCODER_EDP &&
3954 pipe_config->pch_pfit.enabled != enable)
3955 pipe_config->base.connectors_changed = true;
1b509259 3956
c4e2d043
ML		 3957 ret = drm_atomic_commit(state);
3958out:
fabf6e51 3959 drm_modeset_unlock_all(dev);
c4e2d043
ML		 3960 WARN(ret, "Toggling workaround to %i returns %i\n", enable, ret);
3961 if (ret)
3962 drm_atomic_state_free(state);
fabf6e51
DV		 3963}
3964
3965static int ivb_pipe_crc_ctl_reg(struct drm_device *dev,
3966 enum pipe pipe,
3967 enum intel_pipe_crc_source *source,
5b3a856b
DV		 3968 uint32_t *val)
3969{
46a19188
DV		 3970 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3971 *source = INTEL_PIPE_CRC_SOURCE_PF;
3972
3973 switch (*source) {
5b3a856b
DV		 3974 case INTEL_PIPE_CRC_SOURCE_PLANE1:
3975 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
3976 break;
3977 case INTEL_PIPE_CRC_SOURCE_PLANE2:
3978 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
3979 break;
3980 case INTEL_PIPE_CRC_SOURCE_PF:
fabf6e51 3981 if (IS_HASWELL(dev) && pipe == PIPE_A)
c4e2d043 3982 hsw_trans_edp_pipe_A_crc_wa(dev, true);
fabf6e51 3983
5b3a856b
DV		 3984 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
3985 break;
3d099a05 3986 case INTEL_PIPE_CRC_SOURCE_NONE:
5b3a856b
DV		 3987 *val = 0;
3988 break;
3d099a05
DV		 3989 default:
3990 return -EINVAL;
5b3a856b
DV		 3991 }
3992
3993 return 0;
3994}
3995
926321d5
DV		 3996static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
3997 enum intel_pipe_crc_source source)
3998{
3999 struct drm_i915_private *dev_priv = dev->dev_private;
cc3da175 4000 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
8c740dce
PZ		 4001 struct intel_crtc *crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev,
4002 pipe));
432f3342 4003 u32 val = 0; /* shut up gcc */
5b3a856b 4004 int ret;
926321d5 4005
cc3da175
DL		 4006 if (pipe_crc->source == source)
4007 return 0;
4008
ae676fcd
DL		 4009 /* forbid changing the source without going back to 'none' */
4010 if (pipe_crc->source && source)
4011 return -EINVAL;
4012
9d8b0588
DV		 4013 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PIPE(pipe))) {
4014 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
4015 return -EIO;
4016 }
4017
52f843f6 4018 if (IS_GEN2(dev))
46a19188 4019 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
52f843f6 4020 else if (INTEL_INFO(dev)->gen < 5)
46a19188 4021 ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
666a4537 4022 else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
fabf6e51 4023 ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val);
4b79ebf7 4024 else if (IS_GEN5(dev) || IS_GEN6(dev))
46a19188 4025 ret = ilk_pipe_crc_ctl_reg(&source, &val);
5b3a856b 4026 else
fabf6e51 4027 ret = ivb_pipe_crc_ctl_reg(dev, pipe, &source, &val);
5b3a856b
DV		 4028
4029 if (ret != 0)
4030 return ret;
4031
4b584369
DL		 4032 /* none -> real source transition */
4033 if (source) {
4252fbc3
VS		 4034 struct intel_pipe_crc_entry *entries;
4035
7cd6ccff
DL		 4036 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
4037 pipe_name(pipe), pipe_crc_source_name(source));
4038
3cf54b34
VS		 4039 entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR,
4040 sizeof(pipe_crc->entries[0]),
4252fbc3
VS		 4041 GFP_KERNEL);
4042 if (!entries)
e5f75aca
DL		 4043 return -ENOMEM;
4044
8c740dce
PZ		 4045 /*
4046 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
4047 * enabled and disabled dynamically based on package C states,
4048 * user space can't make reliable use of the CRCs, so let's just
4049 * completely disable it.
4050 */
4051 hsw_disable_ips(crtc);
4052
d538bbdf 4053 spin_lock_irq(&pipe_crc->lock);
64387b61 4054 kfree(pipe_crc->entries);
4252fbc3 4055 pipe_crc->entries = entries;
d538bbdf
DL		 4056 pipe_crc->head = 0;
4057 pipe_crc->tail = 0;
4058 spin_unlock_irq(&pipe_crc->lock);
4b584369
DL		 4059 }
4060
cc3da175 4061 pipe_crc->source = source;
926321d5 4062
926321d5
DV		 4063 I915_WRITE(PIPE_CRC_CTL(pipe), val);
4064 POSTING_READ(PIPE_CRC_CTL(pipe));
4065
e5f75aca
DL		 4066 /* real source -> none transition */
4067 if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
d538bbdf 4068 struct intel_pipe_crc_entry *entries;
a33d7105
DV		 4069 struct intel_crtc *crtc =
4070 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
d538bbdf 4071
7cd6ccff
DL		 4072 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
4073 pipe_name(pipe));
4074
a33d7105 4075 drm_modeset_lock(&crtc->base.mutex, NULL);
f77076c9 4076 if (crtc->base.state->active)
a33d7105
DV		 4077 intel_wait_for_vblank(dev, pipe);
4078 drm_modeset_unlock(&crtc->base.mutex);
bcf17ab2 4079
d538bbdf
DL		 4080 spin_lock_irq(&pipe_crc->lock);
4081 entries = pipe_crc->entries;
e5f75aca 4082 pipe_crc->entries = NULL;
9ad6d99f
VS		 4083 pipe_crc->head = 0;
4084 pipe_crc->tail = 0;
d538bbdf
DL		 4085 spin_unlock_irq(&pipe_crc->lock);
4086
4087 kfree(entries);
84093603
DV		 4088
4089 if (IS_G4X(dev))
4090 g4x_undo_pipe_scramble_reset(dev, pipe);
666a4537 4091 else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
8d2f24ca 4092 vlv_undo_pipe_scramble_reset(dev, pipe);
fabf6e51 4093 else if (IS_HASWELL(dev) && pipe == PIPE_A)
c4e2d043 4094 hsw_trans_edp_pipe_A_crc_wa(dev, false);
8c740dce
PZ		 4095
4096 hsw_enable_ips(crtc);
e5f75aca
DL		 4097 }
4098
926321d5
DV		 4099 return 0;
4100}
4101
4102/*
4103 * Parse pipe CRC command strings:
b94dec87
DL		 4104 * command: wsp* object wsp+ name wsp+ source wsp*
4105 * object: 'pipe'
4106 * name: (A | B | C)
926321d5
DV		 4107 * source: (none | plane1 | plane2 | pf)
4108 * wsp: (#0x20 | #0x9 | #0xA)+
4109 *
4110 * eg.:
b94dec87
DL		 4111 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A
4112 * "pipe A none" -> Stop CRC
926321d5 4113 */
bd9db02f 4114static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
926321d5
DV		 4115{
4116 int n_words = 0;
4117
4118 while (*buf) {
4119 char *end;
4120
4121 /* skip leading white space */
4122 buf = skip_spaces(buf);
4123 if (!*buf)
4124 break; /* end of buffer */
4125
4126 /* find end of word */
4127 for (end = buf; *end && !isspace(*end); end++)
4128 ;
4129
4130 if (n_words == max_words) {
4131 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
4132 max_words);
4133 return -EINVAL; /* ran out of words[] before bytes */
4134 }
4135
4136 if (*end)
4137 *end++ = '\0';
4138 words[n_words++] = buf;
4139 buf = end;
4140 }
4141
4142 return n_words;
4143}
4144
b94dec87
DL		 4145enum intel_pipe_crc_object {
4146 PIPE_CRC_OBJECT_PIPE,
4147};
4148
e8dfcf78 4149static const char * const pipe_crc_objects[] = {
b94dec87
DL		 4150 "pipe",
4151};
4152
4153static int
bd9db02f 4154display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
b94dec87
DL		 4155{
4156 int i;
4157
4158 for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
4159 if (!strcmp(buf, pipe_crc_objects[i])) {
bd9db02f 4160 *o = i;
b94dec87
DL		 4161 return 0;
4162 }
4163
4164 return -EINVAL;
4165}
4166
bd9db02f 4167static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
926321d5
DV		 4168{
4169 const char name = buf[0];
4170
4171 if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
4172 return -EINVAL;
4173
4174 *pipe = name - 'A';
4175
4176 return 0;
4177}
4178
4179static int
bd9db02f 4180display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
926321d5
DV		 4181{
4182 int i;
4183
4184 for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
4185 if (!strcmp(buf, pipe_crc_sources[i])) {
bd9db02f 4186 *s = i;
926321d5
DV		 4187 return 0;
4188 }
4189
4190 return -EINVAL;
4191}
4192
bd9db02f 4193static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len)
926321d5 4194{
b94dec87 4195#define N_WORDS 3
926321d5 4196 int n_words;
b94dec87 4197 char *words[N_WORDS];
926321d5 4198 enum pipe pipe;
b94dec87 4199 enum intel_pipe_crc_object object;
926321d5
DV		 4200 enum intel_pipe_crc_source source;
4201
bd9db02f 4202 n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
b94dec87
DL		 4203 if (n_words != N_WORDS) {
4204 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
4205 N_WORDS);
4206 return -EINVAL;
4207 }
4208
bd9db02f 4209 if (display_crc_ctl_parse_object(words[0], &object) < 0) {
b94dec87 4210 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
926321d5
DV		 4211 return -EINVAL;
4212 }
4213
bd9db02f 4214 if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
b94dec87 4215 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
926321d5
DV		 4216 return -EINVAL;
4217 }
4218
bd9db02f 4219 if (display_crc_ctl_parse_source(words[2], &source) < 0) {
b94dec87 4220 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
926321d5
DV		 4221 return -EINVAL;
4222 }
4223
4224 return pipe_crc_set_source(dev, pipe, source);
4225}
4226
bd9db02f
DL		 4227static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
4228 size_t len, loff_t *offp)
926321d5
DV		 4229{
4230 struct seq_file *m = file->private_data;
4231 struct drm_device *dev = m->private;
4232 char *tmpbuf;
4233 int ret;
4234
4235 if (len == 0)
4236 return 0;
4237
4238 if (len > PAGE_SIZE - 1) {
4239 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
4240 PAGE_SIZE);
4241 return -E2BIG;
4242 }
4243
4244 tmpbuf = kmalloc(len + 1, GFP_KERNEL);
4245 if (!tmpbuf)
4246 return -ENOMEM;
4247
4248 if (copy_from_user(tmpbuf, ubuf, len)) {
4249 ret = -EFAULT;
4250 goto out;
4251 }
4252 tmpbuf[len] = '\0';
4253
bd9db02f 4254 ret = display_crc_ctl_parse(dev, tmpbuf, len);
926321d5
DV		 4255
4256out:
4257 kfree(tmpbuf);
4258 if (ret < 0)
4259 return ret;
4260
4261 *offp += len;
4262 return len;
4263}
4264
bd9db02f 4265static const struct file_operations i915_display_crc_ctl_fops = {
926321d5 4266 .owner = THIS_MODULE,
bd9db02f 4267 .open = display_crc_ctl_open,
926321d5
DV		 4268 .read = seq_read,
4269 .llseek = seq_lseek,
4270 .release = single_release,
bd9db02f 4271 .write = display_crc_ctl_write
926321d5
DV		 4272};
4273
eb3394fa
TP		 4274static ssize_t i915_displayport_test_active_write(struct file *file,
4275 const char __user *ubuf,
4276 size_t len, loff_t *offp)
4277{
4278 char *input_buffer;
4279 int status = 0;
eb3394fa
TP		 4280 struct drm_device *dev;
4281 struct drm_connector *connector;
4282 struct list_head *connector_list;
4283 struct intel_dp *intel_dp;
4284 int val = 0;
4285
9aaffa34 4286 dev = ((struct seq_file *)file->private_data)->private;
eb3394fa 4287
eb3394fa
TP		 4288 connector_list = &dev->mode_config.connector_list;
4289
4290 if (len == 0)
4291 return 0;
4292
4293 input_buffer = kmalloc(len + 1, GFP_KERNEL);
4294 if (!input_buffer)
4295 return -ENOMEM;
4296
4297 if (copy_from_user(input_buffer, ubuf, len)) {
4298 status = -EFAULT;
4299 goto out;
4300 }
4301
4302 input_buffer[len] = '\0';
4303 DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len);
4304
4305 list_for_each_entry(connector, connector_list, head) {
4306
4307 if (connector->connector_type !=
4308 DRM_MODE_CONNECTOR_DisplayPort)
4309 continue;
4310
b8bb08ec 4311 if (connector->status == connector_status_connected &&
eb3394fa
TP		 4312 connector->encoder != NULL) {
4313 intel_dp = enc_to_intel_dp(connector->encoder);
4314 status = kstrtoint(input_buffer, 10, &val);
4315 if (status < 0)
4316 goto out;
4317 DRM_DEBUG_DRIVER("Got %d for test active\n", val);
4318 /* To prevent erroneous activation of the compliance
4319 * testing code, only accept an actual value of 1 here
4320 */
4321 if (val == 1)
4322 intel_dp->compliance_test_active = 1;
4323 else
4324 intel_dp->compliance_test_active = 0;
4325 }
4326 }
4327out:
4328 kfree(input_buffer);
4329 if (status < 0)
4330 return status;
4331
4332 *offp += len;
4333 return len;
4334}
4335
4336static int i915_displayport_test_active_show(struct seq_file *m, void *data)
4337{
4338 struct drm_device *dev = m->private;
4339 struct drm_connector *connector;
4340 struct list_head *connector_list = &dev->mode_config.connector_list;
4341 struct intel_dp *intel_dp;
4342
eb3394fa
TP		 4343 list_for_each_entry(connector, connector_list, head) {
4344
4345 if (connector->connector_type !=
4346 DRM_MODE_CONNECTOR_DisplayPort)
4347 continue;
4348
4349 if (connector->status == connector_status_connected &&
4350 connector->encoder != NULL) {
4351 intel_dp = enc_to_intel_dp(connector->encoder);
4352 if (intel_dp->compliance_test_active)
4353 seq_puts(m, "1");
4354 else
4355 seq_puts(m, "0");
4356 } else
4357 seq_puts(m, "0");
4358 }
4359
4360 return 0;
4361}
4362
4363static int i915_displayport_test_active_open(struct inode *inode,
4364 struct file *file)
4365{
4366 struct drm_device *dev = inode->i_private;
4367
4368 return single_open(file, i915_displayport_test_active_show, dev);
4369}
4370
4371static const struct file_operations i915_displayport_test_active_fops = {
4372 .owner = THIS_MODULE,
4373 .open = i915_displayport_test_active_open,
4374 .read = seq_read,
4375 .llseek = seq_lseek,
4376 .release = single_release,
4377 .write = i915_displayport_test_active_write
4378};
4379
4380static int i915_displayport_test_data_show(struct seq_file *m, void *data)
4381{
4382 struct drm_device *dev = m->private;
4383 struct drm_connector *connector;
4384 struct list_head *connector_list = &dev->mode_config.connector_list;
4385 struct intel_dp *intel_dp;
4386
eb3394fa
TP		 4387 list_for_each_entry(connector, connector_list, head) {
4388
4389 if (connector->connector_type !=
4390 DRM_MODE_CONNECTOR_DisplayPort)
4391 continue;
4392
4393 if (connector->status == connector_status_connected &&
4394 connector->encoder != NULL) {
4395 intel_dp = enc_to_intel_dp(connector->encoder);
4396 seq_printf(m, "%lx", intel_dp->compliance_test_data);
4397 } else
4398 seq_puts(m, "0");
4399 }
4400
4401 return 0;
4402}
4403static int i915_displayport_test_data_open(struct inode *inode,
4404 struct file *file)
4405{
4406 struct drm_device *dev = inode->i_private;
4407
4408 return single_open(file, i915_displayport_test_data_show, dev);
4409}
4410
4411static const struct file_operations i915_displayport_test_data_fops = {
4412 .owner = THIS_MODULE,
4413 .open = i915_displayport_test_data_open,
4414 .read = seq_read,
4415 .llseek = seq_lseek,
4416 .release = single_release
4417};
4418
4419static int i915_displayport_test_type_show(struct seq_file *m, void *data)
4420{
4421 struct drm_device *dev = m->private;
4422 struct drm_connector *connector;
4423 struct list_head *connector_list = &dev->mode_config.connector_list;
4424 struct intel_dp *intel_dp;
4425
eb3394fa
TP		 4426 list_for_each_entry(connector, connector_list, head) {
4427
4428 if (connector->connector_type !=
4429 DRM_MODE_CONNECTOR_DisplayPort)
4430 continue;
4431
4432 if (connector->status == connector_status_connected &&
4433 connector->encoder != NULL) {
4434 intel_dp = enc_to_intel_dp(connector->encoder);
4435 seq_printf(m, "%02lx", intel_dp->compliance_test_type);
4436 } else
4437 seq_puts(m, "0");
4438 }
4439
4440 return 0;
4441}
4442
4443static int i915_displayport_test_type_open(struct inode *inode,
4444 struct file *file)
4445{
4446 struct drm_device *dev = inode->i_private;
4447
4448 return single_open(file, i915_displayport_test_type_show, dev);
4449}
4450
4451static const struct file_operations i915_displayport_test_type_fops = {
4452 .owner = THIS_MODULE,
4453 .open = i915_displayport_test_type_open,
4454 .read = seq_read,
4455 .llseek = seq_lseek,
4456 .release = single_release
4457};
4458
97e94b22 4459static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
369a1342
VS		 4460{
4461 struct drm_device *dev = m->private;
369a1342 4462 int level;
de38b95c
VS		 4463 int num_levels;
4464
4465 if (IS_CHERRYVIEW(dev))
4466 num_levels = 3;
4467 else if (IS_VALLEYVIEW(dev))
4468 num_levels = 1;
4469 else
4470 num_levels = ilk_wm_max_level(dev) + 1;
369a1342
VS		 4471
4472 drm_modeset_lock_all(dev);
4473
4474 for (level = 0; level < num_levels; level++) {
4475 unsigned int latency = wm[level];
4476
97e94b22
DL		 4477 /*
4478 * - WM1+ latency values in 0.5us units
de38b95c 4479 * - latencies are in us on gen9/vlv/chv
97e94b22 4480 */
666a4537
WB		 4481 if (INTEL_INFO(dev)->gen >= 9 || IS_VALLEYVIEW(dev) ||
4482 IS_CHERRYVIEW(dev))
97e94b22
DL		 4483 latency *= 10;
4484 else if (level > 0)
369a1342
VS		 4485 latency *= 5;
4486
4487 seq_printf(m, "WM%d %u (%u.%u usec)\n",
97e94b22 4488 level, wm[level], latency / 10, latency % 10);
369a1342
VS		 4489 }
4490
4491 drm_modeset_unlock_all(dev);
4492}
4493
4494static int pri_wm_latency_show(struct seq_file *m, void *data)
4495{
4496 struct drm_device *dev = m->private;
97e94b22
DL		 4497 struct drm_i915_private *dev_priv = dev->dev_private;
4498 const uint16_t *latencies;
4499
4500 if (INTEL_INFO(dev)->gen >= 9)
4501 latencies = dev_priv->wm.skl_latency;
4502 else
4503 latencies = to_i915(dev)->wm.pri_latency;
369a1342 4504
97e94b22 4505 wm_latency_show(m, latencies);
369a1342
VS		 4506
4507 return 0;
4508}
4509
4510static int spr_wm_latency_show(struct seq_file *m, void *data)
4511{
4512 struct drm_device *dev = m->private;
97e94b22
DL		 4513 struct drm_i915_private *dev_priv = dev->dev_private;
4514 const uint16_t *latencies;
4515
4516 if (INTEL_INFO(dev)->gen >= 9)
4517 latencies = dev_priv->wm.skl_latency;
4518 else
4519 latencies = to_i915(dev)->wm.spr_latency;
369a1342 4520
97e94b22 4521 wm_latency_show(m, latencies);
369a1342
VS		 4522
4523 return 0;
4524}
4525
4526static int cur_wm_latency_show(struct seq_file *m, void *data)
4527{
4528 struct drm_device *dev = m->private;
97e94b22
DL		 4529 struct drm_i915_private *dev_priv = dev->dev_private;
4530 const uint16_t *latencies;
4531
4532 if (INTEL_INFO(dev)->gen >= 9)
4533 latencies = dev_priv->wm.skl_latency;
4534 else
4535 latencies = to_i915(dev)->wm.cur_latency;
369a1342 4536
97e94b22 4537 wm_latency_show(m, latencies);
369a1342
VS		 4538
4539 return 0;
4540}
4541
4542static int pri_wm_latency_open(struct inode *inode, struct file *file)
4543{
4544 struct drm_device *dev = inode->i_private;
4545
de38b95c 4546 if (INTEL_INFO(dev)->gen < 5)
369a1342
VS		 4547 return -ENODEV;
4548
4549 return single_open(file, pri_wm_latency_show, dev);
4550}
4551
4552static int spr_wm_latency_open(struct inode *inode, struct file *file)
4553{
4554 struct drm_device *dev = inode->i_private;
4555
9ad0257c 4556 if (HAS_GMCH_DISPLAY(dev))
369a1342
VS		 4557 return -ENODEV;
4558
4559 return single_open(file, spr_wm_latency_show, dev);
4560}
4561
4562static int cur_wm_latency_open(struct inode *inode, struct file *file)
4563{
4564 struct drm_device *dev = inode->i_private;
4565
9ad0257c 4566 if (HAS_GMCH_DISPLAY(dev))
369a1342
VS		 4567 return -ENODEV;
4568
4569 return single_open(file, cur_wm_latency_show, dev);
4570}
4571
4572static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
97e94b22 4573 size_t len, loff_t *offp, uint16_t wm[8])
369a1342
VS		 4574{
4575 struct seq_file *m = file->private_data;
4576 struct drm_device *dev = m->private;
97e94b22 4577 uint16_t new[8] = { 0 };
de38b95c 4578 int num_levels;
369a1342
VS		 4579 int level;
4580 int ret;
4581 char tmp[32];
4582
de38b95c
VS		 4583 if (IS_CHERRYVIEW(dev))
4584 num_levels = 3;
4585 else if (IS_VALLEYVIEW(dev))
4586 num_levels = 1;
4587 else
4588 num_levels = ilk_wm_max_level(dev) + 1;
4589
369a1342
VS		 4590 if (len >= sizeof(tmp))
4591 return -EINVAL;
4592
4593 if (copy_from_user(tmp, ubuf, len))
4594 return -EFAULT;
4595
4596 tmp[len] = '\0';
4597
97e94b22
DL		 4598 ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
4599 &new[0], &new[1], &new[2], &new[3],
4600 &new[4], &new[5], &new[6], &new[7]);
369a1342
VS		 4601 if (ret != num_levels)
4602 return -EINVAL;
4603
4604 drm_modeset_lock_all(dev);
4605
4606 for (level = 0; level < num_levels; level++)
4607 wm[level] = new[level];
4608
4609 drm_modeset_unlock_all(dev);
4610
4611 return len;
4612}
4613
4614
4615static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
4616 size_t len, loff_t *offp)
4617{
4618 struct seq_file *m = file->private_data;
4619 struct drm_device *dev = m->private;
97e94b22
DL		 4620 struct drm_i915_private *dev_priv = dev->dev_private;
4621 uint16_t *latencies;
369a1342 4622
97e94b22
DL		 4623 if (INTEL_INFO(dev)->gen >= 9)
4624 latencies = dev_priv->wm.skl_latency;
4625 else
4626 latencies = to_i915(dev)->wm.pri_latency;
4627
4628 return wm_latency_write(file, ubuf, len, offp, latencies);
369a1342
VS		 4629}
4630
4631static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
4632 size_t len, loff_t *offp)
4633{
4634 struct seq_file *m = file->private_data;
4635 struct drm_device *dev = m->private;
97e94b22
DL		 4636 struct drm_i915_private *dev_priv = dev->dev_private;
4637 uint16_t *latencies;
369a1342 4638
97e94b22
DL		 4639 if (INTEL_INFO(dev)->gen >= 9)
4640 latencies = dev_priv->wm.skl_latency;
4641 else
4642 latencies = to_i915(dev)->wm.spr_latency;
4643
4644 return wm_latency_write(file, ubuf, len, offp, latencies);
369a1342
VS		 4645}
4646
4647static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
4648 size_t len, loff_t *offp)
4649{
4650 struct seq_file *m = file->private_data;
4651 struct drm_device *dev = m->private;
97e94b22
DL		 4652 struct drm_i915_private *dev_priv = dev->dev_private;
4653 uint16_t *latencies;
4654
4655 if (INTEL_INFO(dev)->gen >= 9)
4656 latencies = dev_priv->wm.skl_latency;
4657 else
4658 latencies = to_i915(dev)->wm.cur_latency;
369a1342 4659
97e94b22 4660 return wm_latency_write(file, ubuf, len, offp, latencies);
369a1342
VS		 4661}
4662
4663static const struct file_operations i915_pri_wm_latency_fops = {
4664 .owner = THIS_MODULE,
4665 .open = pri_wm_latency_open,
4666 .read = seq_read,
4667 .llseek = seq_lseek,
4668 .release = single_release,
4669 .write = pri_wm_latency_write
4670};
4671
4672static const struct file_operations i915_spr_wm_latency_fops = {
4673 .owner = THIS_MODULE,
4674 .open = spr_wm_latency_open,
4675 .read = seq_read,
4676 .llseek = seq_lseek,
4677 .release = single_release,
4678 .write = spr_wm_latency_write
4679};
4680
4681static const struct file_operations i915_cur_wm_latency_fops = {
4682 .owner = THIS_MODULE,
4683 .open = cur_wm_latency_open,
4684 .read = seq_read,
4685 .llseek = seq_lseek,
4686 .release = single_release,
4687 .write = cur_wm_latency_write
4688};
4689
647416f9
KC		 4690static int
4691i915_wedged_get(void *data, u64 *val)
f3cd474b 4692{
647416f9 4693 struct drm_device *dev = data;
e277a1f8 4694 struct drm_i915_private *dev_priv = dev->dev_private;
f3cd474b 4695
647416f9 4696 *val = atomic_read(&dev_priv->gpu_error.reset_counter);
f3cd474b 4697
647416f9 4698 return 0;
f3cd474b
CW		 4699}
4700
647416f9
KC		 4701static int
4702i915_wedged_set(void *data, u64 val)
f3cd474b 4703{
647416f9 4704 struct drm_device *dev = data;
d46c0517
ID		 4705 struct drm_i915_private *dev_priv = dev->dev_private;
4706
b8d24a06
MK		 4707 /*
4708 * There is no safeguard against this debugfs entry colliding
4709 * with the hangcheck calling same i915_handle_error() in
4710 * parallel, causing an explosion. For now we assume that the
4711 * test harness is responsible enough not to inject gpu hangs
4712 * while it is writing to 'i915_wedged'
4713 */
4714
4715 if (i915_reset_in_progress(&dev_priv->gpu_error))
4716 return -EAGAIN;
4717
d46c0517 4718 intel_runtime_pm_get(dev_priv);
f3cd474b 4719
58174462
MK		 4720 i915_handle_error(dev, val,
4721 "Manually setting wedged to %llu", val);
d46c0517
ID		 4722
4723 intel_runtime_pm_put(dev_priv);
4724
647416f9 4725 return 0;
f3cd474b
CW		 4726}
4727
647416f9
KC		 4728DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
4729 i915_wedged_get, i915_wedged_set,
3a3b4f98 4730 "%llu\n");
f3cd474b 4731
647416f9
KC		 4732static int
4733i915_ring_stop_get(void *data, u64 *val)
e5eb3d63 4734{
647416f9 4735 struct drm_device *dev = data;
e277a1f8 4736 struct drm_i915_private *dev_priv = dev->dev_private;
e5eb3d63 4737
647416f9 4738 *val = dev_priv->gpu_error.stop_rings;
e5eb3d63 4739
647416f9 4740 return 0;
e5eb3d63
DV		 4741}
4742
647416f9
KC		 4743static int
4744i915_ring_stop_set(void *data, u64 val)
e5eb3d63 4745{
647416f9 4746 struct drm_device *dev = data;
e5eb3d63 4747 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 4748 int ret;
e5eb3d63 4749
647416f9 4750 DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val);
e5eb3d63 4751
22bcfc6a
DV		 4752 ret = mutex_lock_interruptible(&dev->struct_mutex);
4753 if (ret)
4754 return ret;
4755
99584db3 4756 dev_priv->gpu_error.stop_rings = val;
e5eb3d63
DV		 4757 mutex_unlock(&dev->struct_mutex);
4758
647416f9 4759 return 0;
e5eb3d63
DV		 4760}
4761
647416f9
KC		 4762DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops,
4763 i915_ring_stop_get, i915_ring_stop_set,
4764 "0x%08llx\n");
d5442303 4765
094f9a54
CW		 4766static int
4767i915_ring_missed_irq_get(void *data, u64 *val)
4768{
4769 struct drm_device *dev = data;
4770 struct drm_i915_private *dev_priv = dev->dev_private;
4771
4772 *val = dev_priv->gpu_error.missed_irq_rings;
4773 return 0;
4774}
4775
4776static int
4777i915_ring_missed_irq_set(void *data, u64 val)
4778{
4779 struct drm_device *dev = data;
4780 struct drm_i915_private *dev_priv = dev->dev_private;
4781 int ret;
4782
4783 /* Lock against concurrent debugfs callers */
4784 ret = mutex_lock_interruptible(&dev->struct_mutex);
4785 if (ret)
4786 return ret;
4787 dev_priv->gpu_error.missed_irq_rings = val;
4788 mutex_unlock(&dev->struct_mutex);
4789
4790 return 0;
4791}
4792
4793DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
4794 i915_ring_missed_irq_get, i915_ring_missed_irq_set,
4795 "0x%08llx\n");
4796
4797static int
4798i915_ring_test_irq_get(void *data, u64 *val)
4799{
4800 struct drm_device *dev = data;
4801 struct drm_i915_private *dev_priv = dev->dev_private;
4802
4803 *val = dev_priv->gpu_error.test_irq_rings;
4804
4805 return 0;
4806}
4807
4808static int
4809i915_ring_test_irq_set(void *data, u64 val)
4810{
4811 struct drm_device *dev = data;
4812 struct drm_i915_private *dev_priv = dev->dev_private;
4813 int ret;
4814
4815 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
4816
4817 /* Lock against concurrent debugfs callers */
4818 ret = mutex_lock_interruptible(&dev->struct_mutex);
4819 if (ret)
4820 return ret;
4821
4822 dev_priv->gpu_error.test_irq_rings = val;
4823 mutex_unlock(&dev->struct_mutex);
4824
4825 return 0;
4826}
4827
4828DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
4829 i915_ring_test_irq_get, i915_ring_test_irq_set,
4830 "0x%08llx\n");
4831
dd624afd
CW		 4832#define DROP_UNBOUND 0x1
4833#define DROP_BOUND 0x2
4834#define DROP_RETIRE 0x4
4835#define DROP_ACTIVE 0x8
4836#define DROP_ALL (DROP_UNBOUND | \
4837 DROP_BOUND | \
4838 DROP_RETIRE | \
4839 DROP_ACTIVE)
647416f9
KC		 4840static int
4841i915_drop_caches_get(void *data, u64 *val)
dd624afd 4842{
647416f9 4843 *val = DROP_ALL;
dd624afd 4844
647416f9 4845 return 0;
dd624afd
CW		 4846}
4847
647416f9
KC		 4848static int
4849i915_drop_caches_set(void *data, u64 val)
dd624afd 4850{
647416f9 4851 struct drm_device *dev = data;
dd624afd 4852 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 4853 int ret;
dd624afd 4854
2f9fe5ff 4855 DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
dd624afd
CW		 4856
4857 /* No need to check and wait for gpu resets, only libdrm auto-restarts
4858 * on ioctls on -EAGAIN. */
4859 ret = mutex_lock_interruptible(&dev->struct_mutex);
4860 if (ret)
4861 return ret;
4862
4863 if (val & DROP_ACTIVE) {
4864 ret = i915_gpu_idle(dev);
4865 if (ret)
4866 goto unlock;
4867 }
4868
4869 if (val & (DROP_RETIRE | DROP_ACTIVE))
4870 i915_gem_retire_requests(dev);
4871
21ab4e74
CW		 4872 if (val & DROP_BOUND)
4873 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND);
4ad72b7f 4874
21ab4e74
CW		 4875 if (val & DROP_UNBOUND)
4876 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND);
dd624afd
CW		 4877
4878unlock:
4879 mutex_unlock(&dev->struct_mutex);
4880
647416f9 4881 return ret;
dd624afd
CW		 4882}
4883
647416f9
KC		 4884DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
4885 i915_drop_caches_get, i915_drop_caches_set,
4886 "0x%08llx\n");
dd624afd 4887
647416f9
KC		 4888static int
4889i915_max_freq_get(void *data, u64 *val)
358733e9 4890{
647416f9 4891 struct drm_device *dev = data;
e277a1f8 4892 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 4893 int ret;
004777cb 4894
daa3afb2 4895 if (INTEL_INFO(dev)->gen < 6)
004777cb
DV		 4896 return -ENODEV;
4897
5c9669ce
TR		 4898 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4899
4fc688ce 4900 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 4901 if (ret)
4902 return ret;
358733e9 4903
7c59a9c1 4904 *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
4fc688ce 4905 mutex_unlock(&dev_priv->rps.hw_lock);
358733e9 4906
647416f9 4907 return 0;
358733e9
JB		 4908}
4909
647416f9
KC		 4910static int
4911i915_max_freq_set(void *data, u64 val)
358733e9 4912{
647416f9 4913 struct drm_device *dev = data;
358733e9 4914 struct drm_i915_private *dev_priv = dev->dev_private;
bc4d91f6 4915 u32 hw_max, hw_min;
647416f9 4916 int ret;
004777cb 4917
daa3afb2 4918 if (INTEL_INFO(dev)->gen < 6)
004777cb 4919 return -ENODEV;
358733e9 4920
5c9669ce
TR		 4921 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4922
647416f9 4923 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
358733e9 4924
4fc688ce 4925 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 4926 if (ret)
4927 return ret;
4928
358733e9
JB		 4929 /*
4930 * Turbo will still be enabled, but won't go above the set value.
4931 */
bc4d91f6 4932 val = intel_freq_opcode(dev_priv, val);
dd0a1aa1 4933
bc4d91f6
AG		 4934 hw_max = dev_priv->rps.max_freq;
4935 hw_min = dev_priv->rps.min_freq;
dd0a1aa1 4936
b39fb297 4937 if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
dd0a1aa1
JM		 4938 mutex_unlock(&dev_priv->rps.hw_lock);
4939 return -EINVAL;
0a073b84
JB		 4940 }
4941
b39fb297 4942 dev_priv->rps.max_freq_softlimit = val;
dd0a1aa1 4943
ffe02b40 4944 intel_set_rps(dev, val);
dd0a1aa1 4945
4fc688ce 4946 mutex_unlock(&dev_priv->rps.hw_lock);
358733e9 4947
647416f9 4948 return 0;
358733e9
JB		 4949}
4950
647416f9
KC		 4951DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
4952 i915_max_freq_get, i915_max_freq_set,
3a3b4f98 4953 "%llu\n");
358733e9 4954
647416f9
KC		 4955static int
4956i915_min_freq_get(void *data, u64 *val)
1523c310 4957{
647416f9 4958 struct drm_device *dev = data;
e277a1f8 4959 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 4960 int ret;
004777cb 4961
daa3afb2 4962 if (INTEL_INFO(dev)->gen < 6)
004777cb
DV		 4963 return -ENODEV;
4964
5c9669ce
TR		 4965 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4966
4fc688ce 4967 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 4968 if (ret)
4969 return ret;
1523c310 4970
7c59a9c1 4971 *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
4fc688ce 4972 mutex_unlock(&dev_priv->rps.hw_lock);
1523c310 4973
647416f9 4974 return 0;
1523c310
JB		 4975}
4976
647416f9
KC		 4977static int
4978i915_min_freq_set(void *data, u64 val)
1523c310 4979{
647416f9 4980 struct drm_device *dev = data;
1523c310 4981 struct drm_i915_private *dev_priv = dev->dev_private;
bc4d91f6 4982 u32 hw_max, hw_min;
647416f9 4983 int ret;
004777cb 4984
daa3afb2 4985 if (INTEL_INFO(dev)->gen < 6)
004777cb 4986 return -ENODEV;
1523c310 4987
5c9669ce
TR		 4988 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4989
647416f9 4990 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
1523c310 4991
4fc688ce 4992 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 4993 if (ret)
4994 return ret;
4995
1523c310
JB		 4996 /*
4997 * Turbo will still be enabled, but won't go below the set value.
4998 */
bc4d91f6 4999 val = intel_freq_opcode(dev_priv, val);
dd0a1aa1 5000
bc4d91f6
AG		 5001 hw_max = dev_priv->rps.max_freq;
5002 hw_min = dev_priv->rps.min_freq;
dd0a1aa1 5003
b39fb297 5004 if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
dd0a1aa1
JM		 5005 mutex_unlock(&dev_priv->rps.hw_lock);
5006 return -EINVAL;
0a073b84 5007 }
dd0a1aa1 5008
b39fb297 5009 dev_priv->rps.min_freq_softlimit = val;
dd0a1aa1 5010
ffe02b40 5011 intel_set_rps(dev, val);
dd0a1aa1 5012
4fc688ce 5013 mutex_unlock(&dev_priv->rps.hw_lock);
1523c310 5014
647416f9 5015 return 0;
1523c310
JB		 5016}
5017
647416f9
KC		 5018DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
5019 i915_min_freq_get, i915_min_freq_set,
3a3b4f98 5020 "%llu\n");
1523c310 5021
647416f9
KC		 5022static int
5023i915_cache_sharing_get(void *data, u64 *val)
07b7ddd9 5024{
647416f9 5025 struct drm_device *dev = data;
e277a1f8 5026 struct drm_i915_private *dev_priv = dev->dev_private;
07b7ddd9 5027 u32 snpcr;
647416f9 5028 int ret;
07b7ddd9 5029
004777cb
DV		 5030 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
5031 return -ENODEV;
5032
22bcfc6a
DV		 5033 ret = mutex_lock_interruptible(&dev->struct_mutex);
5034 if (ret)
5035 return ret;
c8c8fb33 5036 intel_runtime_pm_get(dev_priv);
22bcfc6a 5037
07b7ddd9 5038 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
c8c8fb33
PZ		 5039
5040 intel_runtime_pm_put(dev_priv);
07b7ddd9
JB		 5041 mutex_unlock(&dev_priv->dev->struct_mutex);
5042
647416f9 5043 *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
07b7ddd9 5044
647416f9 5045 return 0;
07b7ddd9
JB		 5046}
5047
647416f9
KC		 5048static int
5049i915_cache_sharing_set(void *data, u64 val)
07b7ddd9 5050{
647416f9 5051 struct drm_device *dev = data;
07b7ddd9 5052 struct drm_i915_private *dev_priv = dev->dev_private;
07b7ddd9 5053 u32 snpcr;
07b7ddd9 5054
004777cb
DV		 5055 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
5056 return -ENODEV;
5057
647416f9 5058 if (val > 3)
07b7ddd9
JB		 5059 return -EINVAL;
5060
c8c8fb33 5061 intel_runtime_pm_get(dev_priv);
647416f9 5062 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
07b7ddd9
JB		 5063
5064 /* Update the cache sharing policy here as well */
5065 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5066 snpcr &= ~GEN6_MBC_SNPCR_MASK;
5067 snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
5068 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
5069
c8c8fb33 5070 intel_runtime_pm_put(dev_priv);
647416f9 5071 return 0;
07b7ddd9
JB		 5072}
5073
647416f9
KC		 5074DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
5075 i915_cache_sharing_get, i915_cache_sharing_set,
5076 "%llu\n");
07b7ddd9 5077
5d39525a
JM		 5078struct sseu_dev_status {
5079 unsigned int slice_total;
5080 unsigned int subslice_total;
5081 unsigned int subslice_per_slice;
5082 unsigned int eu_total;
5083 unsigned int eu_per_subslice;
5084};
5085
5086static void cherryview_sseu_device_status(struct drm_device *dev,
5087 struct sseu_dev_status *stat)
5088{
5089 struct drm_i915_private *dev_priv = dev->dev_private;
0a0b457f 5090 int ss_max = 2;
5d39525a
JM		 5091 int ss;
5092 u32 sig1[ss_max], sig2[ss_max];
5093
5094 sig1[0] = I915_READ(CHV_POWER_SS0_SIG1);
5095 sig1[1] = I915_READ(CHV_POWER_SS1_SIG1);
5096 sig2[0] = I915_READ(CHV_POWER_SS0_SIG2);
5097 sig2[1] = I915_READ(CHV_POWER_SS1_SIG2);
5098
5099 for (ss = 0; ss < ss_max; ss++) {
5100 unsigned int eu_cnt;
5101
5102 if (sig1[ss] & CHV_SS_PG_ENABLE)
5103 /* skip disabled subslice */
5104 continue;
5105
5106 stat->slice_total = 1;
5107 stat->subslice_per_slice++;
5108 eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
5109 ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
5110 ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
5111 ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2);
5112 stat->eu_total += eu_cnt;
5113 stat->eu_per_subslice = max(stat->eu_per_subslice, eu_cnt);
5114 }
5115 stat->subslice_total = stat->subslice_per_slice;
5116}
5117
5118static void gen9_sseu_device_status(struct drm_device *dev,
5119 struct sseu_dev_status *stat)
5120{
5121 struct drm_i915_private *dev_priv = dev->dev_private;
1c046bc1 5122 int s_max = 3, ss_max = 4;
5d39525a
JM		 5123 int s, ss;
5124 u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
5125
1c046bc1
JM		 5126 /* BXT has a single slice and at most 3 subslices. */
5127 if (IS_BROXTON(dev)) {
5128 s_max = 1;
5129 ss_max = 3;
5130 }
5131
5132 for (s = 0; s < s_max; s++) {
5133 s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s));
5134 eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s));
5135 eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s));
5136 }
5137
5d39525a
JM		 5138 eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
5139 GEN9_PGCTL_SSA_EU19_ACK |
5140 GEN9_PGCTL_SSA_EU210_ACK |
5141 GEN9_PGCTL_SSA_EU311_ACK;
5142 eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
5143 GEN9_PGCTL_SSB_EU19_ACK |
5144 GEN9_PGCTL_SSB_EU210_ACK |
5145 GEN9_PGCTL_SSB_EU311_ACK;
5146
5147 for (s = 0; s < s_max; s++) {
1c046bc1
JM		 5148 unsigned int ss_cnt = 0;
5149
5d39525a
JM		 5150 if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
5151 /* skip disabled slice */
5152 continue;
5153
5154 stat->slice_total++;
1c046bc1 5155
ef11bdb3 5156 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
1c046bc1
JM		 5157 ss_cnt = INTEL_INFO(dev)->subslice_per_slice;
5158
5d39525a
JM		 5159 for (ss = 0; ss < ss_max; ss++) {
5160 unsigned int eu_cnt;
5161
1c046bc1
JM		 5162 if (IS_BROXTON(dev) &&
5163 !(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
5164 /* skip disabled subslice */
5165 continue;
5166
5167 if (IS_BROXTON(dev))
5168 ss_cnt++;
5169
5d39525a
JM		 5170 eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
5171 eu_mask[ss%2]);
5172 stat->eu_total += eu_cnt;
5173 stat->eu_per_subslice = max(stat->eu_per_subslice,
5174 eu_cnt);
5175 }
1c046bc1
JM		 5176
5177 stat->subslice_total += ss_cnt;
5178 stat->subslice_per_slice = max(stat->subslice_per_slice,
5179 ss_cnt);
5d39525a
JM		 5180 }
5181}
5182
91bedd34
ŁD		 5183static void broadwell_sseu_device_status(struct drm_device *dev,
5184 struct sseu_dev_status *stat)
5185{
5186 struct drm_i915_private *dev_priv = dev->dev_private;
5187 int s;
5188 u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO);
5189
5190 stat->slice_total = hweight32(slice_info & GEN8_LSLICESTAT_MASK);
5191
5192 if (stat->slice_total) {
5193 stat->subslice_per_slice = INTEL_INFO(dev)->subslice_per_slice;
5194 stat->subslice_total = stat->slice_total *
5195 stat->subslice_per_slice;
5196 stat->eu_per_subslice = INTEL_INFO(dev)->eu_per_subslice;
5197 stat->eu_total = stat->eu_per_subslice * stat->subslice_total;
5198
5199 /* subtract fused off EU(s) from enabled slice(s) */
5200 for (s = 0; s < stat->slice_total; s++) {
5201 u8 subslice_7eu = INTEL_INFO(dev)->subslice_7eu[s];
5202
5203 stat->eu_total -= hweight8(subslice_7eu);
5204 }
5205 }
5206}
5207
3873218f
JM		 5208static int i915_sseu_status(struct seq_file *m, void *unused)
5209{
5210 struct drm_info_node *node = (struct drm_info_node *) m->private;
5211 struct drm_device *dev = node->minor->dev;
5d39525a 5212 struct sseu_dev_status stat;
3873218f 5213
91bedd34 5214 if (INTEL_INFO(dev)->gen < 8)
3873218f
JM		 5215 return -ENODEV;
5216
5217 seq_puts(m, "SSEU Device Info\n");
5218 seq_printf(m, " Available Slice Total: %u\n",
5219 INTEL_INFO(dev)->slice_total);
5220 seq_printf(m, " Available Subslice Total: %u\n",
5221 INTEL_INFO(dev)->subslice_total);
5222 seq_printf(m, " Available Subslice Per Slice: %u\n",
5223 INTEL_INFO(dev)->subslice_per_slice);
5224 seq_printf(m, " Available EU Total: %u\n",
5225 INTEL_INFO(dev)->eu_total);
5226 seq_printf(m, " Available EU Per Subslice: %u\n",
5227 INTEL_INFO(dev)->eu_per_subslice);
5228 seq_printf(m, " Has Slice Power Gating: %s\n",
5229 yesno(INTEL_INFO(dev)->has_slice_pg));
5230 seq_printf(m, " Has Subslice Power Gating: %s\n",
5231 yesno(INTEL_INFO(dev)->has_subslice_pg));
5232 seq_printf(m, " Has EU Power Gating: %s\n",
5233 yesno(INTEL_INFO(dev)->has_eu_pg));
5234
7f992aba 5235 seq_puts(m, "SSEU Device Status\n");
5d39525a 5236 memset(&stat, 0, sizeof(stat));
5575f03a 5237 if (IS_CHERRYVIEW(dev)) {
5d39525a 5238 cherryview_sseu_device_status(dev, &stat);
91bedd34
ŁD		 5239 } else if (IS_BROADWELL(dev)) {
5240 broadwell_sseu_device_status(dev, &stat);
1c046bc1 5241 } else if (INTEL_INFO(dev)->gen >= 9) {
5d39525a 5242 gen9_sseu_device_status(dev, &stat);
7f992aba 5243 }
5d39525a
JM		 5244 seq_printf(m, " Enabled Slice Total: %u\n",
5245 stat.slice_total);
5246 seq_printf(m, " Enabled Subslice Total: %u\n",
5247 stat.subslice_total);
5248 seq_printf(m, " Enabled Subslice Per Slice: %u\n",
5249 stat.subslice_per_slice);
5250 seq_printf(m, " Enabled EU Total: %u\n",
5251 stat.eu_total);
5252 seq_printf(m, " Enabled EU Per Subslice: %u\n",
5253 stat.eu_per_subslice);
7f992aba 5254
3873218f
JM		 5255 return 0;
5256}
5257
6d794d42
BW		 5258static int i915_forcewake_open(struct inode *inode, struct file *file)
5259{
5260 struct drm_device *dev = inode->i_private;
5261 struct drm_i915_private *dev_priv = dev->dev_private;
6d794d42 5262
075edca4 5263 if (INTEL_INFO(dev)->gen < 6)
6d794d42
BW		 5264 return 0;
5265
6daccb0b 5266 intel_runtime_pm_get(dev_priv);
59bad947 5267 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6d794d42
BW		 5268
5269 return 0;
5270}
5271
c43b5634 5272static int i915_forcewake_release(struct inode *inode, struct file *file)
6d794d42
BW		 5273{
5274 struct drm_device *dev = inode->i_private;
5275 struct drm_i915_private *dev_priv = dev->dev_private;
5276
075edca4 5277 if (INTEL_INFO(dev)->gen < 6)
6d794d42
BW		 5278 return 0;
5279
59bad947 5280 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6daccb0b 5281 intel_runtime_pm_put(dev_priv);
6d794d42
BW		 5282
5283 return 0;
5284}
5285
5286static const struct file_operations i915_forcewake_fops = {
5287 .owner = THIS_MODULE,
5288 .open = i915_forcewake_open,
5289 .release = i915_forcewake_release,
5290};
5291
5292static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
5293{
5294 struct drm_device *dev = minor->dev;
5295 struct dentry *ent;
5296
5297 ent = debugfs_create_file("i915_forcewake_user",
8eb57294 5298 S_IRUSR,
6d794d42
BW		 5299 root, dev,
5300 &i915_forcewake_fops);
f3c5fe97
WY		 5301 if (!ent)
5302 return -ENOMEM;
6d794d42 5303
8eb57294 5304 return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
6d794d42
BW		 5305}
5306
6a9c308d
DV		 5307static int i915_debugfs_create(struct dentry *root,
5308 struct drm_minor *minor,
5309 const char *name,
5310 const struct file_operations *fops)
07b7ddd9
JB		 5311{
5312 struct drm_device *dev = minor->dev;
5313 struct dentry *ent;
5314
6a9c308d 5315 ent = debugfs_create_file(name,
07b7ddd9
JB		 5316 S_IRUGO | S_IWUSR,
5317 root, dev,
6a9c308d 5318 fops);
f3c5fe97
WY		 5319 if (!ent)
5320 return -ENOMEM;
07b7ddd9 5321
6a9c308d 5322 return drm_add_fake_info_node(minor, ent, fops);
07b7ddd9
JB		 5323}
5324
06c5bf8c 5325static const struct drm_info_list i915_debugfs_list[] = {
311bd68e 5326 {"i915_capabilities", i915_capabilities, 0},
73aa808f 5327 {"i915_gem_objects", i915_gem_object_info, 0},
08c18323 5328 {"i915_gem_gtt", i915_gem_gtt_info, 0},
1b50247a 5329 {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
433e12f7 5330 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
433e12f7 5331 {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
6d2b8885 5332 {"i915_gem_stolen", i915_gem_stolen_list_info },
4e5359cd 5333 {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
2017263e
BG		 5334 {"i915_gem_request", i915_gem_request_info, 0},
5335 {"i915_gem_seqno", i915_gem_seqno_info, 0},
a6172a80 5336 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
2017263e 5337 {"i915_gem_interrupt", i915_interrupt_info, 0},
1ec14ad3
CW		 5338 {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
5339 {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
5340 {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
9010ebfd 5341 {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
493018dc 5342 {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0},
8b417c26 5343 {"i915_guc_info", i915_guc_info, 0},
fdf5d357 5344 {"i915_guc_load_status", i915_guc_load_status_info, 0},
4c7e77fc 5345 {"i915_guc_log_dump", i915_guc_log_dump, 0},
adb4bd12 5346 {"i915_frequency_info", i915_frequency_info, 0},
f654449a 5347 {"i915_hangcheck_info", i915_hangcheck_info, 0},
f97108d1 5348 {"i915_drpc_info", i915_drpc_info, 0},
7648fa99 5349 {"i915_emon_status", i915_emon_status, 0},
23b2f8bb 5350 {"i915_ring_freq_table", i915_ring_freq_table, 0},
9a851789 5351 {"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0},
b5e50c3f 5352 {"i915_fbc_status", i915_fbc_status, 0},
92d44621 5353 {"i915_ips_status", i915_ips_status, 0},
4a9bef37 5354 {"i915_sr_status", i915_sr_status, 0},
44834a67 5355 {"i915_opregion", i915_opregion, 0},
ada8f955 5356 {"i915_vbt", i915_vbt, 0},
37811fcc 5357 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
e76d3630 5358 {"i915_context_status", i915_context_status, 0},
c0ab1ae9 5359 {"i915_dump_lrc", i915_dump_lrc, 0},
4ba70e44 5360 {"i915_execlists", i915_execlists, 0},
f65367b5 5361 {"i915_forcewake_domains", i915_forcewake_domains, 0},
ea16a3cd 5362 {"i915_swizzle_info", i915_swizzle_info, 0},
3cf17fc5 5363 {"i915_ppgtt_info", i915_ppgtt_info, 0},
63573eb7 5364 {"i915_llc", i915_llc, 0},
e91fd8c6 5365 {"i915_edp_psr_status", i915_edp_psr_status, 0},
d2e216d0 5366 {"i915_sink_crc_eDP1", i915_sink_crc, 0},
ec013e7f 5367 {"i915_energy_uJ", i915_energy_uJ, 0},
6455c870 5368 {"i915_runtime_pm_status", i915_runtime_pm_status, 0},
1da51581 5369 {"i915_power_domain_info", i915_power_domain_info, 0},
b7cec66d 5370 {"i915_dmc_info", i915_dmc_info, 0},
53f5e3ca 5371 {"i915_display_info", i915_display_info, 0},
e04934cf 5372 {"i915_semaphore_status", i915_semaphore_status, 0},
728e29d7 5373 {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
11bed958 5374 {"i915_dp_mst_info", i915_dp_mst_info, 0},
1ed1ef9d 5375 {"i915_wa_registers", i915_wa_registers, 0},
c5511e44 5376 {"i915_ddb_info", i915_ddb_info, 0},
3873218f 5377 {"i915_sseu_status", i915_sseu_status, 0},
a54746e3 5378 {"i915_drrs_status", i915_drrs_status, 0},
1854d5ca 5379 {"i915_rps_boost_info", i915_rps_boost_info, 0},
2017263e 5380};
27c202ad 5381#define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
2017263e 5382
06c5bf8c 5383static const struct i915_debugfs_files {
34b9674c
DV		 5384 const char *name;
5385 const struct file_operations *fops;
5386} i915_debugfs_files[] = {
5387 {"i915_wedged", &i915_wedged_fops},
5388 {"i915_max_freq", &i915_max_freq_fops},
5389 {"i915_min_freq", &i915_min_freq_fops},
5390 {"i915_cache_sharing", &i915_cache_sharing_fops},
5391 {"i915_ring_stop", &i915_ring_stop_fops},
094f9a54
CW		 5392 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
5393 {"i915_ring_test_irq", &i915_ring_test_irq_fops},
34b9674c
DV		 5394 {"i915_gem_drop_caches", &i915_drop_caches_fops},
5395 {"i915_error_state", &i915_error_state_fops},
5396 {"i915_next_seqno", &i915_next_seqno_fops},
bd9db02f 5397 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
369a1342
VS		 5398 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
5399 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
5400 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
da46f936 5401 {"i915_fbc_false_color", &i915_fbc_fc_fops},
eb3394fa
TP		 5402 {"i915_dp_test_data", &i915_displayport_test_data_fops},
5403 {"i915_dp_test_type", &i915_displayport_test_type_fops},
5404 {"i915_dp_test_active", &i915_displayport_test_active_fops}
34b9674c
DV		 5405};
5406
07144428
DL		 5407void intel_display_crc_init(struct drm_device *dev)
5408{
5409 struct drm_i915_private *dev_priv = dev->dev_private;
b378360e 5410 enum pipe pipe;
07144428 5411
055e393f 5412 for_each_pipe(dev_priv, pipe) {
b378360e 5413 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
07144428 5414
d538bbdf
DL		 5415 pipe_crc->opened = false;
5416 spin_lock_init(&pipe_crc->lock);
07144428
DL		 5417 init_waitqueue_head(&pipe_crc->wq);
5418 }
5419}
5420
27c202ad 5421int i915_debugfs_init(struct drm_minor *minor)
2017263e 5422{
34b9674c 5423 int ret, i;
f3cd474b 5424
6d794d42 5425 ret = i915_forcewake_create(minor->debugfs_root, minor);
358733e9
JB		 5426 if (ret)
5427 return ret;
6a9c308d 5428
07144428
DL		 5429 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5430 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
5431 if (ret)
5432 return ret;
5433 }
5434
34b9674c
DV		 5435 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5436 ret = i915_debugfs_create(minor->debugfs_root, minor,
5437 i915_debugfs_files[i].name,
5438 i915_debugfs_files[i].fops);
5439 if (ret)
5440 return ret;
5441 }
40633219 5442
27c202ad
BG		 5443 return drm_debugfs_create_files(i915_debugfs_list,
5444 I915_DEBUGFS_ENTRIES,
2017263e
BG		 5445 minor->debugfs_root, minor);
5446}
5447
27c202ad 5448void i915_debugfs_cleanup(struct drm_minor *minor)
2017263e 5449{
34b9674c
DV		 5450 int i;
5451
27c202ad
BG		 5452 drm_debugfs_remove_files(i915_debugfs_list,
5453 I915_DEBUGFS_ENTRIES, minor);
07144428 5454
6d794d42
BW		 5455 drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
5456 1, minor);
07144428 5457
e309a997 5458 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
07144428
DL		 5459 struct drm_info_list *info_list =
5460 (struct drm_info_list *)&i915_pipe_crc_data[i];
5461
5462 drm_debugfs_remove_files(info_list, 1, minor);
5463 }
5464
34b9674c
DV		 5465 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5466 struct drm_info_list *info_list =
5467 (struct drm_info_list *) i915_debugfs_files[i].fops;
5468
5469 drm_debugfs_remove_files(info_list, 1, minor);
5470 }
2017263e 5471}
aa7471d2
JN		 5472
5473struct dpcd_block {
5474 /* DPCD dump start address. */
5475 unsigned int offset;
5476 /* DPCD dump end address, inclusive. If unset, .size will be used. */
5477 unsigned int end;
5478 /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */
5479 size_t size;
5480 /* Only valid for eDP. */
5481 bool edp;
5482};
5483
5484static const struct dpcd_block i915_dpcd_debug[] = {
5485 { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE },
5486 { .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS },
5487 { .offset = DP_DOWNSTREAM_PORT_0, .size = 16 },
5488 { .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET },
5489 { .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 },
5490 { .offset = DP_SET_POWER },
5491 { .offset = DP_EDP_DPCD_REV },
5492 { .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 },
5493 { .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB },
5494 { .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET },
5495};
5496
5497static int i915_dpcd_show(struct seq_file *m, void *data)
5498{
5499 struct drm_connector *connector = m->private;
5500 struct intel_dp *intel_dp =
5501 enc_to_intel_dp(&intel_attached_encoder(connector)->base);
5502 uint8_t buf[16];
5503 ssize_t err;
5504 int i;
5505
5c1a8875
MK		 5506 if (connector->status != connector_status_connected)
5507 return -ENODEV;
5508
aa7471d2
JN		 5509 for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) {
5510 const struct dpcd_block *b = &i915_dpcd_debug[i];
5511 size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1);
5512
5513 if (b->edp &&
5514 connector->connector_type != DRM_MODE_CONNECTOR_eDP)
5515 continue;
5516
5517 /* low tech for now */
5518 if (WARN_ON(size > sizeof(buf)))
5519 continue;
5520
5521 err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size);
5522 if (err <= 0) {
5523 DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n",
5524 size, b->offset, err);
5525 continue;
5526 }
5527
5528 seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf);
b3f9d7d7 5529 }
aa7471d2
JN		 5530
5531 return 0;
5532}
5533
5534static int i915_dpcd_open(struct inode *inode, struct file *file)
5535{
5536 return single_open(file, i915_dpcd_show, inode->i_private);
5537}
5538
5539static const struct file_operations i915_dpcd_fops = {
5540 .owner = THIS_MODULE,
5541 .open = i915_dpcd_open,
5542 .read = seq_read,
5543 .llseek = seq_lseek,
5544 .release = single_release,
5545};
5546
5547/**
5548 * i915_debugfs_connector_add - add i915 specific connector debugfs files
5549 * @connector: pointer to a registered drm_connector
5550 *
5551 * Cleanup will be done by drm_connector_unregister() through a call to
5552 * drm_debugfs_connector_remove().
5553 *
5554 * Returns 0 on success, negative error codes on error.
5555 */
5556int i915_debugfs_connector_add(struct drm_connector *connector)
5557{
5558 struct dentry *root = connector->debugfs_entry;
5559
5560 /* The connector must have been registered beforehands. */
5561 if (!root)
5562 return -ENODEV;
5563
5564 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
5565 connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5566 debugfs_create_file("i915_dpcd", S_IRUGO, root, connector,
5567 &i915_dpcd_fops);
5568
5569 return 0;
5570}
Linux kernel - Deliverables
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