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Revert "drm/rockchip: Flip select/depends in Kconfig"
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_debugfs.c
CommitLineData
2017263e
BG		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 *
27 */
28
29#include <linux/seq_file.h>
b2c88f5b 30#include <linux/circ_buf.h>
926321d5 31#include <linux/ctype.h>
f3cd474b 32#include <linux/debugfs.h>
5a0e3ad6 33#include <linux/slab.h>
2d1a8a48 34#include <linux/export.h>
6d2b8885 35#include <linux/list_sort.h>
ec013e7f 36#include <asm/msr-index.h>
760285e7 37#include <drm/drmP.h>
4e5359cd 38#include "intel_drv.h"
e5c65260 39#include "intel_ringbuffer.h"
760285e7 40#include <drm/i915_drm.h>
2017263e
BG		 41#include "i915_drv.h"
42
f13d3f73 43enum {
69dc4987 44 ACTIVE_LIST,
f13d3f73 45 INACTIVE_LIST,
d21d5975 46 PINNED_LIST,
f13d3f73 47};
2017263e 48
70d39fe4
CW		 49static const char *yesno(int v)
50{
51 return v ? "yes" : "no";
52}
53
497666d8
DL		 54/* As the drm_debugfs_init() routines are called before dev->dev_private is
55 * allocated we need to hook into the minor for release. */
56static int
57drm_add_fake_info_node(struct drm_minor *minor,
58 struct dentry *ent,
59 const void *key)
60{
61 struct drm_info_node *node;
62
63 node = kmalloc(sizeof(*node), GFP_KERNEL);
64 if (node == NULL) {
65 debugfs_remove(ent);
66 return -ENOMEM;
67 }
68
69 node->minor = minor;
70 node->dent = ent;
71 node->info_ent = (void *) key;
72
73 mutex_lock(&minor->debugfs_lock);
74 list_add(&node->list, &minor->debugfs_list);
75 mutex_unlock(&minor->debugfs_lock);
76
77 return 0;
78}
79
70d39fe4
CW		 80static int i915_capabilities(struct seq_file *m, void *data)
81{
9f25d007 82 struct drm_info_node *node = m->private;
70d39fe4
CW		 83 struct drm_device *dev = node->minor->dev;
84 const struct intel_device_info *info = INTEL_INFO(dev);
85
86 seq_printf(m, "gen: %d\n", info->gen);
03d00ac5 87 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
79fc46df
DL		 88#define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
89#define SEP_SEMICOLON ;
90 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
91#undef PRINT_FLAG
92#undef SEP_SEMICOLON
70d39fe4
CW		 93
94 return 0;
95}
2017263e 96
05394f39 97static const char *get_pin_flag(struct drm_i915_gem_object *obj)
a6172a80 98{
4feb7659 99 if (i915_gem_obj_is_pinned(obj))
a6172a80
CW		 100 return "p";
101 else
102 return " ";
103}
104
05394f39 105static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
a6172a80 106{
0206e353
AJ		 107 switch (obj->tiling_mode) {
108 default:
109 case I915_TILING_NONE: return " ";
110 case I915_TILING_X: return "X";
111 case I915_TILING_Y: return "Y";
112 }
a6172a80
CW		 113}
114
1d693bcc
BW		 115static inline const char *get_global_flag(struct drm_i915_gem_object *obj)
116{
aff43766 117 return i915_gem_obj_to_ggtt(obj) ? "g" : " ";
1d693bcc
BW		 118}
119
37811fcc
CW		 120static void
121describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
122{
1d693bcc 123 struct i915_vma *vma;
d7f46fc4
BW		 124 int pin_count = 0;
125
20e28fba 126 seq_printf(m, "%pK: %s%s%s %8zdKiB %02x %02x %x %x %x%s%s%s",
37811fcc
CW		 127 &obj->base,
128 get_pin_flag(obj),
129 get_tiling_flag(obj),
1d693bcc 130 get_global_flag(obj),
a05a5862 131 obj->base.size / 1024,
37811fcc
CW		 132 obj->base.read_domains,
133 obj->base.write_domain,
97b2a6a1
JH		 134 i915_gem_request_get_seqno(obj->last_read_req),
135 i915_gem_request_get_seqno(obj->last_write_req),
136 i915_gem_request_get_seqno(obj->last_fenced_req),
0a4cd7c8 137 i915_cache_level_str(to_i915(obj->base.dev), obj->cache_level),
37811fcc
CW		 138 obj->dirty ? " dirty" : "",
139 obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
140 if (obj->base.name)
141 seq_printf(m, " (name: %d)", obj->base.name);
d7f46fc4
BW		 142 list_for_each_entry(vma, &obj->vma_list, vma_link)
143 if (vma->pin_count > 0)
144 pin_count++;
145 seq_printf(m, " (pinned x %d)", pin_count);
cc98b413
CW		 146 if (obj->pin_display)
147 seq_printf(m, " (display)");
37811fcc
CW		 148 if (obj->fence_reg != I915_FENCE_REG_NONE)
149 seq_printf(m, " (fence: %d)", obj->fence_reg);
1d693bcc
BW		 150 list_for_each_entry(vma, &obj->vma_list, vma_link) {
151 if (!i915_is_ggtt(vma->vm))
152 seq_puts(m, " (pp");
153 else
154 seq_puts(m, " (g");
fe14d5f4
TU		 155 seq_printf(m, "gtt offset: %08lx, size: %08lx, type: %u)",
156 vma->node.start, vma->node.size,
157 vma->ggtt_view.type);
1d693bcc 158 }
c1ad11fc
CW		 159 if (obj->stolen)
160 seq_printf(m, " (stolen: %08lx)", obj->stolen->start);
6299f992
CW		 161 if (obj->pin_mappable || obj->fault_mappable) {
162 char s[3], *t = s;
163 if (obj->pin_mappable)
164 *t++ = 'p';
165 if (obj->fault_mappable)
166 *t++ = 'f';
167 *t = '\0';
168 seq_printf(m, " (%s mappable)", s);
169 }
41c52415
JH		 170 if (obj->last_read_req != NULL)
171 seq_printf(m, " (%s)",
172 i915_gem_request_get_ring(obj->last_read_req)->name);
d5a81ef1
DV		 173 if (obj->frontbuffer_bits)
174 seq_printf(m, " (frontbuffer: 0x%03x)", obj->frontbuffer_bits);
37811fcc
CW		 175}
176
273497e5 177static void describe_ctx(struct seq_file *m, struct intel_context *ctx)
3ccfd19d 178{
ea0c76f8 179 seq_putc(m, ctx->legacy_hw_ctx.initialized ? 'I' : 'i');
3ccfd19d
BW		 180 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
181 seq_putc(m, ' ');
182}
183
433e12f7 184static int i915_gem_object_list_info(struct seq_file *m, void *data)
2017263e 185{
9f25d007 186 struct drm_info_node *node = m->private;
433e12f7
BG		 187 uintptr_t list = (uintptr_t) node->info_ent->data;
188 struct list_head *head;
2017263e 189 struct drm_device *dev = node->minor->dev;
5cef07e1
BW		 190 struct drm_i915_private *dev_priv = dev->dev_private;
191 struct i915_address_space *vm = &dev_priv->gtt.base;
ca191b13 192 struct i915_vma *vma;
8f2480fb
CW		 193 size_t total_obj_size, total_gtt_size;
194 int count, ret;
de227ef0
CW		 195
196 ret = mutex_lock_interruptible(&dev->struct_mutex);
197 if (ret)
198 return ret;
2017263e 199
ca191b13 200 /* FIXME: the user of this interface might want more than just GGTT */
433e12f7
BG		 201 switch (list) {
202 case ACTIVE_LIST:
267f0c90 203 seq_puts(m, "Active:\n");
5cef07e1 204 head = &vm->active_list;
433e12f7
BG		 205 break;
206 case INACTIVE_LIST:
267f0c90 207 seq_puts(m, "Inactive:\n");
5cef07e1 208 head = &vm->inactive_list;
433e12f7 209 break;
433e12f7 210 default:
de227ef0
CW		 211 mutex_unlock(&dev->struct_mutex);
212 return -EINVAL;
2017263e 213 }
2017263e 214
8f2480fb 215 total_obj_size = total_gtt_size = count = 0;
ca191b13
BW		 216 list_for_each_entry(vma, head, mm_list) {
217 seq_printf(m, " ");
218 describe_obj(m, vma->obj);
219 seq_printf(m, "\n");
220 total_obj_size += vma->obj->base.size;
221 total_gtt_size += vma->node.size;
8f2480fb 222 count++;
2017263e 223 }
de227ef0 224 mutex_unlock(&dev->struct_mutex);
5e118f41 225
8f2480fb
CW		 226 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
227 count, total_obj_size, total_gtt_size);
2017263e
BG		 228 return 0;
229}
230
6d2b8885
CW		 231static int obj_rank_by_stolen(void *priv,
232 struct list_head *A, struct list_head *B)
233{
234 struct drm_i915_gem_object *a =
b25cb2f8 235 container_of(A, struct drm_i915_gem_object, obj_exec_link);
6d2b8885 236 struct drm_i915_gem_object *b =
b25cb2f8 237 container_of(B, struct drm_i915_gem_object, obj_exec_link);
6d2b8885
CW		 238
239 return a->stolen->start - b->stolen->start;
240}
241
242static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
243{
9f25d007 244 struct drm_info_node *node = m->private;
6d2b8885
CW		 245 struct drm_device *dev = node->minor->dev;
246 struct drm_i915_private *dev_priv = dev->dev_private;
247 struct drm_i915_gem_object *obj;
248 size_t total_obj_size, total_gtt_size;
249 LIST_HEAD(stolen);
250 int count, ret;
251
252 ret = mutex_lock_interruptible(&dev->struct_mutex);
253 if (ret)
254 return ret;
255
256 total_obj_size = total_gtt_size = count = 0;
257 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
258 if (obj->stolen == NULL)
259 continue;
260
b25cb2f8 261 list_add(&obj->obj_exec_link, &stolen);
6d2b8885
CW		 262
263 total_obj_size += obj->base.size;
264 total_gtt_size += i915_gem_obj_ggtt_size(obj);
265 count++;
266 }
267 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
268 if (obj->stolen == NULL)
269 continue;
270
b25cb2f8 271 list_add(&obj->obj_exec_link, &stolen);
6d2b8885
CW		 272
273 total_obj_size += obj->base.size;
274 count++;
275 }
276 list_sort(NULL, &stolen, obj_rank_by_stolen);
277 seq_puts(m, "Stolen:\n");
278 while (!list_empty(&stolen)) {
b25cb2f8 279 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
6d2b8885
CW		 280 seq_puts(m, " ");
281 describe_obj(m, obj);
282 seq_putc(m, '\n');
b25cb2f8 283 list_del_init(&obj->obj_exec_link);
6d2b8885
CW		 284 }
285 mutex_unlock(&dev->struct_mutex);
286
287 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
288 count, total_obj_size, total_gtt_size);
289 return 0;
290}
291
6299f992
CW		 292#define count_objects(list, member) do { \
293 list_for_each_entry(obj, list, member) { \
f343c5f6 294 size += i915_gem_obj_ggtt_size(obj); \
6299f992
CW		 295 ++count; \
296 if (obj->map_and_fenceable) { \
f343c5f6 297 mappable_size += i915_gem_obj_ggtt_size(obj); \
6299f992
CW		 298 ++mappable_count; \
299 } \
300 } \
0206e353 301} while (0)
6299f992 302
2db8e9d6 303struct file_stats {
6313c204 304 struct drm_i915_file_private *file_priv;
2db8e9d6 305 int count;
c67a17e9
CW		 306 size_t total, unbound;
307 size_t global, shared;
308 size_t active, inactive;
2db8e9d6
CW		 309};
310
311static int per_file_stats(int id, void *ptr, void *data)
312{
313 struct drm_i915_gem_object *obj = ptr;
314 struct file_stats *stats = data;
6313c204 315 struct i915_vma *vma;
2db8e9d6
CW		 316
317 stats->count++;
318 stats->total += obj->base.size;
319
c67a17e9
CW		 320 if (obj->base.name || obj->base.dma_buf)
321 stats->shared += obj->base.size;
322
6313c204
CW		 323 if (USES_FULL_PPGTT(obj->base.dev)) {
324 list_for_each_entry(vma, &obj->vma_list, vma_link) {
325 struct i915_hw_ppgtt *ppgtt;
326
327 if (!drm_mm_node_allocated(&vma->node))
328 continue;
329
330 if (i915_is_ggtt(vma->vm)) {
331 stats->global += obj->base.size;
332 continue;
333 }
334
335 ppgtt = container_of(vma->vm, struct i915_hw_ppgtt, base);
4d884705 336 if (ppgtt->file_priv != stats->file_priv)
6313c204
CW		 337 continue;
338
41c52415 339 if (obj->active) /* XXX per-vma statistic */
6313c204
CW		 340 stats->active += obj->base.size;
341 else
342 stats->inactive += obj->base.size;
343
344 return 0;
345 }
2db8e9d6 346 } else {
6313c204
CW		 347 if (i915_gem_obj_ggtt_bound(obj)) {
348 stats->global += obj->base.size;
41c52415 349 if (obj->active)
6313c204
CW		 350 stats->active += obj->base.size;
351 else
352 stats->inactive += obj->base.size;
353 return 0;
354 }
2db8e9d6
CW		 355 }
356
6313c204
CW		 357 if (!list_empty(&obj->global_list))
358 stats->unbound += obj->base.size;
359
2db8e9d6
CW		 360 return 0;
361}
362
493018dc
BV		 363#define print_file_stats(m, name, stats) \
364 seq_printf(m, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu global, %zu shared, %zu unbound)\n", \
365 name, \
366 stats.count, \
367 stats.total, \
368 stats.active, \
369 stats.inactive, \
370 stats.global, \
371 stats.shared, \
372 stats.unbound)
373
374static void print_batch_pool_stats(struct seq_file *m,
375 struct drm_i915_private *dev_priv)
376{
377 struct drm_i915_gem_object *obj;
378 struct file_stats stats;
379
380 memset(&stats, 0, sizeof(stats));
381
382 list_for_each_entry(obj,
383 &dev_priv->mm.batch_pool.cache_list,
384 batch_pool_list)
385 per_file_stats(0, obj, &stats);
386
387 print_file_stats(m, "batch pool", stats);
388}
389
ca191b13
BW		 390#define count_vmas(list, member) do { \
391 list_for_each_entry(vma, list, member) { \
392 size += i915_gem_obj_ggtt_size(vma->obj); \
393 ++count; \
394 if (vma->obj->map_and_fenceable) { \
395 mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
396 ++mappable_count; \
397 } \
398 } \
399} while (0)
400
401static int i915_gem_object_info(struct seq_file *m, void* data)
73aa808f 402{
9f25d007 403 struct drm_info_node *node = m->private;
73aa808f
CW		 404 struct drm_device *dev = node->minor->dev;
405 struct drm_i915_private *dev_priv = dev->dev_private;
b7abb714
CW		 406 u32 count, mappable_count, purgeable_count;
407 size_t size, mappable_size, purgeable_size;
6299f992 408 struct drm_i915_gem_object *obj;
5cef07e1 409 struct i915_address_space *vm = &dev_priv->gtt.base;
2db8e9d6 410 struct drm_file *file;
ca191b13 411 struct i915_vma *vma;
73aa808f
CW		 412 int ret;
413
414 ret = mutex_lock_interruptible(&dev->struct_mutex);
415 if (ret)
416 return ret;
417
6299f992
CW		 418 seq_printf(m, "%u objects, %zu bytes\n",
419 dev_priv->mm.object_count,
420 dev_priv->mm.object_memory);
421
422 size = count = mappable_size = mappable_count = 0;
35c20a60 423 count_objects(&dev_priv->mm.bound_list, global_list);
6299f992
CW		 424 seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n",
425 count, mappable_count, size, mappable_size);
426
427 size = count = mappable_size = mappable_count = 0;
ca191b13 428 count_vmas(&vm->active_list, mm_list);
6299f992
CW		 429 seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n",
430 count, mappable_count, size, mappable_size);
431
6299f992 432 size = count = mappable_size = mappable_count = 0;
ca191b13 433 count_vmas(&vm->inactive_list, mm_list);
6299f992
CW		 434 seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n",
435 count, mappable_count, size, mappable_size);
436
b7abb714 437 size = count = purgeable_size = purgeable_count = 0;
35c20a60 438 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
6c085a72 439 size += obj->base.size, ++count;
b7abb714
CW		 440 if (obj->madv == I915_MADV_DONTNEED)
441 purgeable_size += obj->base.size, ++purgeable_count;
442 }
6c085a72
CW		 443 seq_printf(m, "%u unbound objects, %zu bytes\n", count, size);
444
6299f992 445 size = count = mappable_size = mappable_count = 0;
35c20a60 446 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
6299f992 447 if (obj->fault_mappable) {
f343c5f6 448 size += i915_gem_obj_ggtt_size(obj);
6299f992
CW		 449 ++count;
450 }
451 if (obj->pin_mappable) {
f343c5f6 452 mappable_size += i915_gem_obj_ggtt_size(obj);
6299f992
CW		 453 ++mappable_count;
454 }
b7abb714
CW		 455 if (obj->madv == I915_MADV_DONTNEED) {
456 purgeable_size += obj->base.size;
457 ++purgeable_count;
458 }
6299f992 459 }
b7abb714
CW		 460 seq_printf(m, "%u purgeable objects, %zu bytes\n",
461 purgeable_count, purgeable_size);
6299f992
CW		 462 seq_printf(m, "%u pinned mappable objects, %zu bytes\n",
463 mappable_count, mappable_size);
464 seq_printf(m, "%u fault mappable objects, %zu bytes\n",
465 count, size);
466
93d18799 467 seq_printf(m, "%zu [%lu] gtt total\n",
853ba5d2
BW		 468 dev_priv->gtt.base.total,
469 dev_priv->gtt.mappable_end - dev_priv->gtt.base.start);
73aa808f 470
493018dc
BV		 471 seq_putc(m, '\n');
472 print_batch_pool_stats(m, dev_priv);
473
267f0c90 474 seq_putc(m, '\n');
2db8e9d6
CW		 475 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
476 struct file_stats stats;
3ec2f427 477 struct task_struct *task;
2db8e9d6
CW		 478
479 memset(&stats, 0, sizeof(stats));
6313c204 480 stats.file_priv = file->driver_priv;
5b5ffff0 481 spin_lock(&file->table_lock);
2db8e9d6 482 idr_for_each(&file->object_idr, per_file_stats, &stats);
5b5ffff0 483 spin_unlock(&file->table_lock);
3ec2f427
TH		 484 /*
485 * Although we have a valid reference on file->pid, that does
486 * not guarantee that the task_struct who called get_pid() is
487 * still alive (e.g. get_pid(current) => fork() => exit()).
488 * Therefore, we need to protect this ->comm access using RCU.
489 */
490 rcu_read_lock();
491 task = pid_task(file->pid, PIDTYPE_PID);
493018dc 492 print_file_stats(m, task ? task->comm : "<unknown>", stats);
3ec2f427 493 rcu_read_unlock();
2db8e9d6
CW		 494 }
495
73aa808f
CW		 496 mutex_unlock(&dev->struct_mutex);
497
498 return 0;
499}
500
aee56cff 501static int i915_gem_gtt_info(struct seq_file *m, void *data)
08c18323 502{
9f25d007 503 struct drm_info_node *node = m->private;
08c18323 504 struct drm_device *dev = node->minor->dev;
1b50247a 505 uintptr_t list = (uintptr_t) node->info_ent->data;
08c18323
CW		 506 struct drm_i915_private *dev_priv = dev->dev_private;
507 struct drm_i915_gem_object *obj;
508 size_t total_obj_size, total_gtt_size;
509 int count, ret;
510
511 ret = mutex_lock_interruptible(&dev->struct_mutex);
512 if (ret)
513 return ret;
514
515 total_obj_size = total_gtt_size = count = 0;
35c20a60 516 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
d7f46fc4 517 if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj))
1b50247a
CW		 518 continue;
519
267f0c90 520 seq_puts(m, " ");
08c18323 521 describe_obj(m, obj);
267f0c90 522 seq_putc(m, '\n');
08c18323 523 total_obj_size += obj->base.size;
f343c5f6 524 total_gtt_size += i915_gem_obj_ggtt_size(obj);
08c18323
CW		 525 count++;
526 }
527
528 mutex_unlock(&dev->struct_mutex);
529
530 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
531 count, total_obj_size, total_gtt_size);
532
533 return 0;
534}
535
4e5359cd
SF		 536static int i915_gem_pageflip_info(struct seq_file *m, void *data)
537{
9f25d007 538 struct drm_info_node *node = m->private;
4e5359cd 539 struct drm_device *dev = node->minor->dev;
d6bbafa1 540 struct drm_i915_private *dev_priv = dev->dev_private;
4e5359cd 541 struct intel_crtc *crtc;
8a270ebf
DV		 542 int ret;
543
544 ret = mutex_lock_interruptible(&dev->struct_mutex);
545 if (ret)
546 return ret;
4e5359cd 547
d3fcc808 548 for_each_intel_crtc(dev, crtc) {
9db4a9c7
JB		 549 const char pipe = pipe_name(crtc->pipe);
550 const char plane = plane_name(crtc->plane);
4e5359cd
SF		 551 struct intel_unpin_work *work;
552
5e2d7afc 553 spin_lock_irq(&dev->event_lock);
4e5359cd
SF		 554 work = crtc->unpin_work;
555 if (work == NULL) {
9db4a9c7 556 seq_printf(m, "No flip due on pipe %c (plane %c)\n",
4e5359cd
SF		 557 pipe, plane);
558 } else {
d6bbafa1
CW		 559 u32 addr;
560
e7d841ca 561 if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9db4a9c7 562 seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
4e5359cd
SF		 563 pipe, plane);
564 } else {
9db4a9c7 565 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
4e5359cd
SF		 566 pipe, plane);
567 }
3a8a946e
DV		 568 if (work->flip_queued_req) {
569 struct intel_engine_cs *ring =
570 i915_gem_request_get_ring(work->flip_queued_req);
571
20e28fba 572 seq_printf(m, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n",
3a8a946e 573 ring->name,
f06cc1b9 574 i915_gem_request_get_seqno(work->flip_queued_req),
d6bbafa1 575 dev_priv->next_seqno,
3a8a946e 576 ring->get_seqno(ring, true),
1b5a433a 577 i915_gem_request_completed(work->flip_queued_req, true));
d6bbafa1
CW		 578 } else
579 seq_printf(m, "Flip not associated with any ring\n");
580 seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
581 work->flip_queued_vblank,
582 work->flip_ready_vblank,
583 drm_vblank_count(dev, crtc->pipe));
4e5359cd 584 if (work->enable_stall_check)
267f0c90 585 seq_puts(m, "Stall check enabled, ");
4e5359cd 586 else
267f0c90 587 seq_puts(m, "Stall check waiting for page flip ioctl, ");
e7d841ca 588 seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
4e5359cd 589
d6bbafa1
CW		 590 if (INTEL_INFO(dev)->gen >= 4)
591 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane)));
592 else
593 addr = I915_READ(DSPADDR(crtc->plane));
594 seq_printf(m, "Current scanout address 0x%08x\n", addr);
595
4e5359cd 596 if (work->pending_flip_obj) {
d6bbafa1
CW		 597 seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset);
598 seq_printf(m, "MMIO update completed? %d\n", addr == work->gtt_offset);
4e5359cd
SF		 599 }
600 }
5e2d7afc 601 spin_unlock_irq(&dev->event_lock);
4e5359cd
SF		 602 }
603
8a270ebf
DV		 604 mutex_unlock(&dev->struct_mutex);
605
4e5359cd
SF		 606 return 0;
607}
608
493018dc
BV		 609static int i915_gem_batch_pool_info(struct seq_file *m, void *data)
610{
611 struct drm_info_node *node = m->private;
612 struct drm_device *dev = node->minor->dev;
613 struct drm_i915_private *dev_priv = dev->dev_private;
614 struct drm_i915_gem_object *obj;
615 int count = 0;
616 int ret;
617
618 ret = mutex_lock_interruptible(&dev->struct_mutex);
619 if (ret)
620 return ret;
621
622 seq_puts(m, "cache:\n");
623 list_for_each_entry(obj,
624 &dev_priv->mm.batch_pool.cache_list,
625 batch_pool_list) {
626 seq_puts(m, " ");
627 describe_obj(m, obj);
628 seq_putc(m, '\n');
629 count++;
630 }
631
632 seq_printf(m, "total: %d\n", count);
633
634 mutex_unlock(&dev->struct_mutex);
635
636 return 0;
637}
638
2017263e
BG		 639static int i915_gem_request_info(struct seq_file *m, void *data)
640{
9f25d007 641 struct drm_info_node *node = m->private;
2017263e 642 struct drm_device *dev = node->minor->dev;
e277a1f8 643 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 644 struct intel_engine_cs *ring;
2017263e 645 struct drm_i915_gem_request *gem_request;
a2c7f6fd 646 int ret, count, i;
de227ef0
CW		 647
648 ret = mutex_lock_interruptible(&dev->struct_mutex);
649 if (ret)
650 return ret;
2017263e 651
c2c347a9 652 count = 0;
a2c7f6fd
CW		 653 for_each_ring(ring, dev_priv, i) {
654 if (list_empty(&ring->request_list))
655 continue;
656
657 seq_printf(m, "%s requests:\n", ring->name);
c2c347a9 658 list_for_each_entry(gem_request,
a2c7f6fd 659 &ring->request_list,
c2c347a9 660 list) {
20e28fba 661 seq_printf(m, " %x @ %d\n",
c2c347a9
CW		 662 gem_request->seqno,
663 (int) (jiffies - gem_request->emitted_jiffies));
664 }
665 count++;
2017263e 666 }
de227ef0
CW		 667 mutex_unlock(&dev->struct_mutex);
668
c2c347a9 669 if (count == 0)
267f0c90 670 seq_puts(m, "No requests\n");
c2c347a9 671
2017263e
BG		 672 return 0;
673}
674
b2223497 675static void i915_ring_seqno_info(struct seq_file *m,
a4872ba6 676 struct intel_engine_cs *ring)
b2223497
CW		 677{
678 if (ring->get_seqno) {
20e28fba 679 seq_printf(m, "Current sequence (%s): %x\n",
b2eadbc8 680 ring->name, ring->get_seqno(ring, false));
b2223497
CW		 681 }
682}
683
2017263e
BG		 684static int i915_gem_seqno_info(struct seq_file *m, void *data)
685{
9f25d007 686 struct drm_info_node *node = m->private;
2017263e 687 struct drm_device *dev = node->minor->dev;
e277a1f8 688 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 689 struct intel_engine_cs *ring;
1ec14ad3 690 int ret, i;
de227ef0
CW		 691
692 ret = mutex_lock_interruptible(&dev->struct_mutex);
693 if (ret)
694 return ret;
c8c8fb33 695 intel_runtime_pm_get(dev_priv);
2017263e 696
a2c7f6fd
CW		 697 for_each_ring(ring, dev_priv, i)
698 i915_ring_seqno_info(m, ring);
de227ef0 699
c8c8fb33 700 intel_runtime_pm_put(dev_priv);
de227ef0
CW		 701 mutex_unlock(&dev->struct_mutex);
702
2017263e
BG		 703 return 0;
704}
705
706
707static int i915_interrupt_info(struct seq_file *m, void *data)
708{
9f25d007 709 struct drm_info_node *node = m->private;
2017263e 710 struct drm_device *dev = node->minor->dev;
e277a1f8 711 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 712 struct intel_engine_cs *ring;
9db4a9c7 713 int ret, i, pipe;
de227ef0
CW		 714
715 ret = mutex_lock_interruptible(&dev->struct_mutex);
716 if (ret)
717 return ret;
c8c8fb33 718 intel_runtime_pm_get(dev_priv);
2017263e 719
74e1ca8c 720 if (IS_CHERRYVIEW(dev)) {
74e1ca8c
VS		 721 seq_printf(m, "Master Interrupt Control:\t%08x\n",
722 I915_READ(GEN8_MASTER_IRQ));
723
724 seq_printf(m, "Display IER:\t%08x\n",
725 I915_READ(VLV_IER));
726 seq_printf(m, "Display IIR:\t%08x\n",
727 I915_READ(VLV_IIR));
728 seq_printf(m, "Display IIR_RW:\t%08x\n",
729 I915_READ(VLV_IIR_RW));
730 seq_printf(m, "Display IMR:\t%08x\n",
731 I915_READ(VLV_IMR));
055e393f 732 for_each_pipe(dev_priv, pipe)
74e1ca8c
VS		 733 seq_printf(m, "Pipe %c stat:\t%08x\n",
734 pipe_name(pipe),
735 I915_READ(PIPESTAT(pipe)));
736
737 seq_printf(m, "Port hotplug:\t%08x\n",
738 I915_READ(PORT_HOTPLUG_EN));
739 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
740 I915_READ(VLV_DPFLIPSTAT));
741 seq_printf(m, "DPINVGTT:\t%08x\n",
742 I915_READ(DPINVGTT));
743
744 for (i = 0; i < 4; i++) {
745 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
746 i, I915_READ(GEN8_GT_IMR(i)));
747 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
748 i, I915_READ(GEN8_GT_IIR(i)));
749 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
750 i, I915_READ(GEN8_GT_IER(i)));
751 }
752
753 seq_printf(m, "PCU interrupt mask:\t%08x\n",
754 I915_READ(GEN8_PCU_IMR));
755 seq_printf(m, "PCU interrupt identity:\t%08x\n",
756 I915_READ(GEN8_PCU_IIR));
757 seq_printf(m, "PCU interrupt enable:\t%08x\n",
758 I915_READ(GEN8_PCU_IER));
759 } else if (INTEL_INFO(dev)->gen >= 8) {
a123f157
BW		 760 seq_printf(m, "Master Interrupt Control:\t%08x\n",
761 I915_READ(GEN8_MASTER_IRQ));
762
763 for (i = 0; i < 4; i++) {
764 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
765 i, I915_READ(GEN8_GT_IMR(i)));
766 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
767 i, I915_READ(GEN8_GT_IIR(i)));
768 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
769 i, I915_READ(GEN8_GT_IER(i)));
770 }
771
055e393f 772 for_each_pipe(dev_priv, pipe) {
f458ebbc 773 if (!intel_display_power_is_enabled(dev_priv,
22c59960
PZ		 774 POWER_DOMAIN_PIPE(pipe))) {
775 seq_printf(m, "Pipe %c power disabled\n",
776 pipe_name(pipe));
777 continue;
778 }
a123f157 779 seq_printf(m, "Pipe %c IMR:\t%08x\n",
07d27e20
DL		 780 pipe_name(pipe),
781 I915_READ(GEN8_DE_PIPE_IMR(pipe)));
a123f157 782 seq_printf(m, "Pipe %c IIR:\t%08x\n",
07d27e20
DL		 783 pipe_name(pipe),
784 I915_READ(GEN8_DE_PIPE_IIR(pipe)));
a123f157 785 seq_printf(m, "Pipe %c IER:\t%08x\n",
07d27e20
DL		 786 pipe_name(pipe),
787 I915_READ(GEN8_DE_PIPE_IER(pipe)));
a123f157
BW		 788 }
789
790 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
791 I915_READ(GEN8_DE_PORT_IMR));
792 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
793 I915_READ(GEN8_DE_PORT_IIR));
794 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
795 I915_READ(GEN8_DE_PORT_IER));
796
797 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
798 I915_READ(GEN8_DE_MISC_IMR));
799 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
800 I915_READ(GEN8_DE_MISC_IIR));
801 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
802 I915_READ(GEN8_DE_MISC_IER));
803
804 seq_printf(m, "PCU interrupt mask:\t%08x\n",
805 I915_READ(GEN8_PCU_IMR));
806 seq_printf(m, "PCU interrupt identity:\t%08x\n",
807 I915_READ(GEN8_PCU_IIR));
808 seq_printf(m, "PCU interrupt enable:\t%08x\n",
809 I915_READ(GEN8_PCU_IER));
810 } else if (IS_VALLEYVIEW(dev)) {
7e231dbe
JB		 811 seq_printf(m, "Display IER:\t%08x\n",
812 I915_READ(VLV_IER));
813 seq_printf(m, "Display IIR:\t%08x\n",
814 I915_READ(VLV_IIR));
815 seq_printf(m, "Display IIR_RW:\t%08x\n",
816 I915_READ(VLV_IIR_RW));
817 seq_printf(m, "Display IMR:\t%08x\n",
818 I915_READ(VLV_IMR));
055e393f 819 for_each_pipe(dev_priv, pipe)
7e231dbe
JB		 820 seq_printf(m, "Pipe %c stat:\t%08x\n",
821 pipe_name(pipe),
822 I915_READ(PIPESTAT(pipe)));
823
824 seq_printf(m, "Master IER:\t%08x\n",
825 I915_READ(VLV_MASTER_IER));
826
827 seq_printf(m, "Render IER:\t%08x\n",
828 I915_READ(GTIER));
829 seq_printf(m, "Render IIR:\t%08x\n",
830 I915_READ(GTIIR));
831 seq_printf(m, "Render IMR:\t%08x\n",
832 I915_READ(GTIMR));
833
834 seq_printf(m, "PM IER:\t\t%08x\n",
835 I915_READ(GEN6_PMIER));
836 seq_printf(m, "PM IIR:\t\t%08x\n",
837 I915_READ(GEN6_PMIIR));
838 seq_printf(m, "PM IMR:\t\t%08x\n",
839 I915_READ(GEN6_PMIMR));
840
841 seq_printf(m, "Port hotplug:\t%08x\n",
842 I915_READ(PORT_HOTPLUG_EN));
843 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
844 I915_READ(VLV_DPFLIPSTAT));
845 seq_printf(m, "DPINVGTT:\t%08x\n",
846 I915_READ(DPINVGTT));
847
848 } else if (!HAS_PCH_SPLIT(dev)) {
5f6a1695
ZW		 849 seq_printf(m, "Interrupt enable: %08x\n",
850 I915_READ(IER));
851 seq_printf(m, "Interrupt identity: %08x\n",
852 I915_READ(IIR));
853 seq_printf(m, "Interrupt mask: %08x\n",
854 I915_READ(IMR));
055e393f 855 for_each_pipe(dev_priv, pipe)
9db4a9c7
JB		 856 seq_printf(m, "Pipe %c stat: %08x\n",
857 pipe_name(pipe),
858 I915_READ(PIPESTAT(pipe)));
5f6a1695
ZW		 859 } else {
860 seq_printf(m, "North Display Interrupt enable: %08x\n",
861 I915_READ(DEIER));
862 seq_printf(m, "North Display Interrupt identity: %08x\n",
863 I915_READ(DEIIR));
864 seq_printf(m, "North Display Interrupt mask: %08x\n",
865 I915_READ(DEIMR));
866 seq_printf(m, "South Display Interrupt enable: %08x\n",
867 I915_READ(SDEIER));
868 seq_printf(m, "South Display Interrupt identity: %08x\n",
869 I915_READ(SDEIIR));
870 seq_printf(m, "South Display Interrupt mask: %08x\n",
871 I915_READ(SDEIMR));
872 seq_printf(m, "Graphics Interrupt enable: %08x\n",
873 I915_READ(GTIER));
874 seq_printf(m, "Graphics Interrupt identity: %08x\n",
875 I915_READ(GTIIR));
876 seq_printf(m, "Graphics Interrupt mask: %08x\n",
877 I915_READ(GTIMR));
878 }
a2c7f6fd 879 for_each_ring(ring, dev_priv, i) {
a123f157 880 if (INTEL_INFO(dev)->gen >= 6) {
a2c7f6fd
CW		 881 seq_printf(m,
882 "Graphics Interrupt mask (%s): %08x\n",
883 ring->name, I915_READ_IMR(ring));
9862e600 884 }
a2c7f6fd 885 i915_ring_seqno_info(m, ring);
9862e600 886 }
c8c8fb33 887 intel_runtime_pm_put(dev_priv);
de227ef0
CW		 888 mutex_unlock(&dev->struct_mutex);
889
2017263e
BG		 890 return 0;
891}
892
a6172a80
CW		 893static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
894{
9f25d007 895 struct drm_info_node *node = m->private;
a6172a80 896 struct drm_device *dev = node->minor->dev;
e277a1f8 897 struct drm_i915_private *dev_priv = dev->dev_private;
de227ef0
CW		 898 int i, ret;
899
900 ret = mutex_lock_interruptible(&dev->struct_mutex);
901 if (ret)
902 return ret;
a6172a80
CW		 903
904 seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
905 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
906 for (i = 0; i < dev_priv->num_fence_regs; i++) {
05394f39 907 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
a6172a80 908
6c085a72
CW		 909 seq_printf(m, "Fence %d, pin count = %d, object = ",
910 i, dev_priv->fence_regs[i].pin_count);
c2c347a9 911 if (obj == NULL)
267f0c90 912 seq_puts(m, "unused");
c2c347a9 913 else
05394f39 914 describe_obj(m, obj);
267f0c90 915 seq_putc(m, '\n');
a6172a80
CW		 916 }
917
05394f39 918 mutex_unlock(&dev->struct_mutex);
a6172a80
CW		 919 return 0;
920}
921
2017263e
BG		 922static int i915_hws_info(struct seq_file *m, void *data)
923{
9f25d007 924 struct drm_info_node *node = m->private;
2017263e 925 struct drm_device *dev = node->minor->dev;
e277a1f8 926 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 927 struct intel_engine_cs *ring;
1a240d4d 928 const u32 *hws;
4066c0ae
CW		 929 int i;
930
1ec14ad3 931 ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
1a240d4d 932 hws = ring->status_page.page_addr;
2017263e
BG		 933 if (hws == NULL)
934 return 0;
935
936 for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
937 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
938 i * 4,
939 hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
940 }
941 return 0;
942}
943
d5442303
DV		 944static ssize_t
945i915_error_state_write(struct file *filp,
946 const char __user *ubuf,
947 size_t cnt,
948 loff_t *ppos)
949{
edc3d884 950 struct i915_error_state_file_priv *error_priv = filp->private_data;
d5442303 951 struct drm_device *dev = error_priv->dev;
22bcfc6a 952 int ret;
d5442303
DV		 953
954 DRM_DEBUG_DRIVER("Resetting error state\n");
955
22bcfc6a
DV		 956 ret = mutex_lock_interruptible(&dev->struct_mutex);
957 if (ret)
958 return ret;
959
d5442303
DV		 960 i915_destroy_error_state(dev);
961 mutex_unlock(&dev->struct_mutex);
962
963 return cnt;
964}
965
966static int i915_error_state_open(struct inode *inode, struct file *file)
967{
968 struct drm_device *dev = inode->i_private;
d5442303 969 struct i915_error_state_file_priv *error_priv;
d5442303
DV		 970
971 error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
972 if (!error_priv)
973 return -ENOMEM;
974
975 error_priv->dev = dev;
976
95d5bfb3 977 i915_error_state_get(dev, error_priv);
d5442303 978
edc3d884
MK		 979 file->private_data = error_priv;
980
981 return 0;
d5442303
DV		 982}
983
984static int i915_error_state_release(struct inode *inode, struct file *file)
985{
edc3d884 986 struct i915_error_state_file_priv *error_priv = file->private_data;
d5442303 987
95d5bfb3 988 i915_error_state_put(error_priv);
d5442303
DV		 989 kfree(error_priv);
990
edc3d884
MK		 991 return 0;
992}
993
4dc955f7
MK		 994static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
995 size_t count, loff_t *pos)
996{
997 struct i915_error_state_file_priv *error_priv = file->private_data;
998 struct drm_i915_error_state_buf error_str;
999 loff_t tmp_pos = 0;
1000 ssize_t ret_count = 0;
1001 int ret;
1002
0a4cd7c8 1003 ret = i915_error_state_buf_init(&error_str, to_i915(error_priv->dev), count, *pos);
4dc955f7
MK		 1004 if (ret)
1005 return ret;
edc3d884 1006
fc16b48b 1007 ret = i915_error_state_to_str(&error_str, error_priv);
edc3d884
MK		 1008 if (ret)
1009 goto out;
1010
edc3d884
MK		 1011 ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
1012 error_str.buf,
1013 error_str.bytes);
1014
1015 if (ret_count < 0)
1016 ret = ret_count;
1017 else
1018 *pos = error_str.start + ret_count;
1019out:
4dc955f7 1020 i915_error_state_buf_release(&error_str);
edc3d884 1021 return ret ?: ret_count;
d5442303
DV		 1022}
1023
1024static const struct file_operations i915_error_state_fops = {
1025 .owner = THIS_MODULE,
1026 .open = i915_error_state_open,
edc3d884 1027 .read = i915_error_state_read,
d5442303
DV		 1028 .write = i915_error_state_write,
1029 .llseek = default_llseek,
1030 .release = i915_error_state_release,
1031};
1032
647416f9
KC		 1033static int
1034i915_next_seqno_get(void *data, u64 *val)
40633219 1035{
647416f9 1036 struct drm_device *dev = data;
e277a1f8 1037 struct drm_i915_private *dev_priv = dev->dev_private;
40633219
MK		 1038 int ret;
1039
1040 ret = mutex_lock_interruptible(&dev->struct_mutex);
1041 if (ret)
1042 return ret;
1043
647416f9 1044 *val = dev_priv->next_seqno;
40633219
MK		 1045 mutex_unlock(&dev->struct_mutex);
1046
647416f9 1047 return 0;
40633219
MK		 1048}
1049
647416f9
KC		 1050static int
1051i915_next_seqno_set(void *data, u64 val)
1052{
1053 struct drm_device *dev = data;
40633219
MK		 1054 int ret;
1055
40633219
MK		 1056 ret = mutex_lock_interruptible(&dev->struct_mutex);
1057 if (ret)
1058 return ret;
1059
e94fbaa8 1060 ret = i915_gem_set_seqno(dev, val);
40633219
MK		 1061 mutex_unlock(&dev->struct_mutex);
1062
647416f9 1063 return ret;
40633219
MK		 1064}
1065
647416f9
KC		 1066DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
1067 i915_next_seqno_get, i915_next_seqno_set,
3a3b4f98 1068 "0x%llx\n");
40633219 1069
adb4bd12 1070static int i915_frequency_info(struct seq_file *m, void *unused)
f97108d1 1071{
9f25d007 1072 struct drm_info_node *node = m->private;
f97108d1 1073 struct drm_device *dev = node->minor->dev;
e277a1f8 1074 struct drm_i915_private *dev_priv = dev->dev_private;
c8c8fb33
PZ		 1075 int ret = 0;
1076
1077 intel_runtime_pm_get(dev_priv);
3b8d8d91 1078
5c9669ce
TR		 1079 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1080
3b8d8d91
JB		 1081 if (IS_GEN5(dev)) {
1082 u16 rgvswctl = I915_READ16(MEMSWCTL);
1083 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1084
1085 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1086 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1087 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1088 MEMSTAT_VID_SHIFT);
1089 seq_printf(m, "Current P-state: %d\n",
1090 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
daa3afb2
TR		 1091 } else if (IS_GEN6(dev) || (IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) ||
1092 IS_BROADWELL(dev)) {
3b8d8d91
JB		 1093 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1094 u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1095 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
0d8f9491 1096 u32 rpmodectl, rpinclimit, rpdeclimit;
8e8c06cd 1097 u32 rpstat, cagf, reqf;
ccab5c82
JB		 1098 u32 rpupei, rpcurup, rpprevup;
1099 u32 rpdownei, rpcurdown, rpprevdown;
9dd3c605 1100 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
3b8d8d91
JB		 1101 int max_freq;
1102
1103 /* RPSTAT1 is in the GT power well */
d1ebd816
BW		 1104 ret = mutex_lock_interruptible(&dev->struct_mutex);
1105 if (ret)
c8c8fb33 1106 goto out;
d1ebd816 1107
59bad947 1108 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
3b8d8d91 1109
8e8c06cd
CW		 1110 reqf = I915_READ(GEN6_RPNSWREQ);
1111 reqf &= ~GEN6_TURBO_DISABLE;
daa3afb2 1112 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8e8c06cd
CW		 1113 reqf >>= 24;
1114 else
1115 reqf >>= 25;
7c59a9c1 1116 reqf = intel_gpu_freq(dev_priv, reqf);
8e8c06cd 1117
0d8f9491
CW		 1118 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1119 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1120 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1121
ccab5c82
JB		 1122 rpstat = I915_READ(GEN6_RPSTAT1);
1123 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
1124 rpcurup = I915_READ(GEN6_RP_CUR_UP);
1125 rpprevup = I915_READ(GEN6_RP_PREV_UP);
1126 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
1127 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
1128 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
daa3afb2 1129 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
f82855d3
BW		 1130 cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1131 else
1132 cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
7c59a9c1 1133 cagf = intel_gpu_freq(dev_priv, cagf);
ccab5c82 1134
59bad947 1135 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
d1ebd816
BW		 1136 mutex_unlock(&dev->struct_mutex);
1137
9dd3c605
PZ		 1138 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1139 pm_ier = I915_READ(GEN6_PMIER);
1140 pm_imr = I915_READ(GEN6_PMIMR);
1141 pm_isr = I915_READ(GEN6_PMISR);
1142 pm_iir = I915_READ(GEN6_PMIIR);
1143 pm_mask = I915_READ(GEN6_PMINTRMSK);
1144 } else {
1145 pm_ier = I915_READ(GEN8_GT_IER(2));
1146 pm_imr = I915_READ(GEN8_GT_IMR(2));
1147 pm_isr = I915_READ(GEN8_GT_ISR(2));
1148 pm_iir = I915_READ(GEN8_GT_IIR(2));
1149 pm_mask = I915_READ(GEN6_PMINTRMSK);
1150 }
0d8f9491 1151 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
9dd3c605 1152 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
3b8d8d91 1153 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
3b8d8d91
JB		 1154 seq_printf(m, "Render p-state ratio: %d\n",
1155 (gt_perf_status & 0xff00) >> 8);
1156 seq_printf(m, "Render p-state VID: %d\n",
1157 gt_perf_status & 0xff);
1158 seq_printf(m, "Render p-state limit: %d\n",
1159 rp_state_limits & 0xff);
0d8f9491
CW		 1160 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1161 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1162 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1163 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
8e8c06cd 1164 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
f82855d3 1165 seq_printf(m, "CAGF: %dMHz\n", cagf);
ccab5c82
JB		 1166 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
1167 GEN6_CURICONT_MASK);
1168 seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
1169 GEN6_CURBSYTAVG_MASK);
1170 seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
1171 GEN6_CURBSYTAVG_MASK);
1172 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
1173 GEN6_CURIAVG_MASK);
1174 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
1175 GEN6_CURBSYTAVG_MASK);
1176 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
1177 GEN6_CURBSYTAVG_MASK);
3b8d8d91
JB		 1178
1179 max_freq = (rp_state_cap & 0xff0000) >> 16;
1180 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
7c59a9c1 1181 intel_gpu_freq(dev_priv, max_freq));
3b8d8d91
JB		 1182
1183 max_freq = (rp_state_cap & 0xff00) >> 8;
1184 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
7c59a9c1 1185 intel_gpu_freq(dev_priv, max_freq));
3b8d8d91
JB		 1186
1187 max_freq = rp_state_cap & 0xff;
1188 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
7c59a9c1 1189 intel_gpu_freq(dev_priv, max_freq));
31c77388
BW		 1190
1191 seq_printf(m, "Max overclocked frequency: %dMHz\n",
7c59a9c1 1192 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
0a073b84 1193 } else if (IS_VALLEYVIEW(dev)) {
03af2045 1194 u32 freq_sts;
0a073b84 1195
259bd5d4 1196 mutex_lock(&dev_priv->rps.hw_lock);
64936258 1197 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
0a073b84
JB		 1198 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1199 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1200
0a073b84 1201 seq_printf(m, "max GPU freq: %d MHz\n",
7c59a9c1 1202 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
0a073b84 1203
0a073b84 1204 seq_printf(m, "min GPU freq: %d MHz\n",
7c59a9c1 1205 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
03af2045 1206
7c59a9c1
VS		 1207 seq_printf(m,
1208 "efficient (RPe) frequency: %d MHz\n",
1209 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
0a073b84
JB		 1210
1211 seq_printf(m, "current GPU freq: %d MHz\n",
7c59a9c1 1212 intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
259bd5d4 1213 mutex_unlock(&dev_priv->rps.hw_lock);
3b8d8d91 1214 } else {
267f0c90 1215 seq_puts(m, "no P-state info available\n");
3b8d8d91 1216 }
f97108d1 1217
c8c8fb33
PZ		 1218out:
1219 intel_runtime_pm_put(dev_priv);
1220 return ret;
f97108d1
JB		 1221}
1222
f654449a
CW		 1223static int i915_hangcheck_info(struct seq_file *m, void *unused)
1224{
1225 struct drm_info_node *node = m->private;
ebbc7546
MK		 1226 struct drm_device *dev = node->minor->dev;
1227 struct drm_i915_private *dev_priv = dev->dev_private;
f654449a 1228 struct intel_engine_cs *ring;
ebbc7546
MK		 1229 u64 acthd[I915_NUM_RINGS];
1230 u32 seqno[I915_NUM_RINGS];
f654449a
CW		 1231 int i;
1232
1233 if (!i915.enable_hangcheck) {
1234 seq_printf(m, "Hangcheck disabled\n");
1235 return 0;
1236 }
1237
ebbc7546
MK		 1238 intel_runtime_pm_get(dev_priv);
1239
1240 for_each_ring(ring, dev_priv, i) {
1241 seqno[i] = ring->get_seqno(ring, false);
1242 acthd[i] = intel_ring_get_active_head(ring);
1243 }
1244
1245 intel_runtime_pm_put(dev_priv);
1246
f654449a
CW		 1247 if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) {
1248 seq_printf(m, "Hangcheck active, fires in %dms\n",
1249 jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires -
1250 jiffies));
1251 } else
1252 seq_printf(m, "Hangcheck inactive\n");
1253
1254 for_each_ring(ring, dev_priv, i) {
1255 seq_printf(m, "%s:\n", ring->name);
1256 seq_printf(m, "\tseqno = %x [current %x]\n",
ebbc7546 1257 ring->hangcheck.seqno, seqno[i]);
f654449a
CW		 1258 seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
1259 (long long)ring->hangcheck.acthd,
ebbc7546 1260 (long long)acthd[i]);
f654449a
CW		 1261 seq_printf(m, "\tmax ACTHD = 0x%08llx\n",
1262 (long long)ring->hangcheck.max_acthd);
ebbc7546
MK		 1263 seq_printf(m, "\tscore = %d\n", ring->hangcheck.score);
1264 seq_printf(m, "\taction = %d\n", ring->hangcheck.action);
f654449a
CW		 1265 }
1266
1267 return 0;
1268}
1269
4d85529d 1270static int ironlake_drpc_info(struct seq_file *m)
f97108d1 1271{
9f25d007 1272 struct drm_info_node *node = m->private;
f97108d1 1273 struct drm_device *dev = node->minor->dev;
e277a1f8 1274 struct drm_i915_private *dev_priv = dev->dev_private;
616fdb5a
BW		 1275 u32 rgvmodectl, rstdbyctl;
1276 u16 crstandvid;
1277 int ret;
1278
1279 ret = mutex_lock_interruptible(&dev->struct_mutex);
1280 if (ret)
1281 return ret;
c8c8fb33 1282 intel_runtime_pm_get(dev_priv);
616fdb5a
BW		 1283
1284 rgvmodectl = I915_READ(MEMMODECTL);
1285 rstdbyctl = I915_READ(RSTDBYCTL);
1286 crstandvid = I915_READ16(CRSTANDVID);
1287
c8c8fb33 1288 intel_runtime_pm_put(dev_priv);
616fdb5a 1289 mutex_unlock(&dev->struct_mutex);
f97108d1
JB		 1290
1291 seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
1292 "yes" : "no");
1293 seq_printf(m, "Boost freq: %d\n",
1294 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1295 MEMMODE_BOOST_FREQ_SHIFT);
1296 seq_printf(m, "HW control enabled: %s\n",
1297 rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");
1298 seq_printf(m, "SW control enabled: %s\n",
1299 rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");
1300 seq_printf(m, "Gated voltage change: %s\n",
1301 rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");
1302 seq_printf(m, "Starting frequency: P%d\n",
1303 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
7648fa99 1304 seq_printf(m, "Max P-state: P%d\n",
f97108d1 1305 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
7648fa99
JB		 1306 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1307 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1308 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1309 seq_printf(m, "Render standby enabled: %s\n",
1310 (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes");
267f0c90 1311 seq_puts(m, "Current RS state: ");
88271da3
JB		 1312 switch (rstdbyctl & RSX_STATUS_MASK) {
1313 case RSX_STATUS_ON:
267f0c90 1314 seq_puts(m, "on\n");
88271da3
JB		 1315 break;
1316 case RSX_STATUS_RC1:
267f0c90 1317 seq_puts(m, "RC1\n");
88271da3
JB		 1318 break;
1319 case RSX_STATUS_RC1E:
267f0c90 1320 seq_puts(m, "RC1E\n");
88271da3
JB		 1321 break;
1322 case RSX_STATUS_RS1:
267f0c90 1323 seq_puts(m, "RS1\n");
88271da3
JB		 1324 break;
1325 case RSX_STATUS_RS2:
267f0c90 1326 seq_puts(m, "RS2 (RC6)\n");
88271da3
JB		 1327 break;
1328 case RSX_STATUS_RS3:
267f0c90 1329 seq_puts(m, "RC3 (RC6+)\n");
88271da3
JB		 1330 break;
1331 default:
267f0c90 1332 seq_puts(m, "unknown\n");
88271da3
JB		 1333 break;
1334 }
f97108d1
JB		 1335
1336 return 0;
1337}
1338
f65367b5 1339static int i915_forcewake_domains(struct seq_file *m, void *data)
669ab5aa 1340{
b2cff0db
CW		 1341 struct drm_info_node *node = m->private;
1342 struct drm_device *dev = node->minor->dev;
1343 struct drm_i915_private *dev_priv = dev->dev_private;
1344 struct intel_uncore_forcewake_domain *fw_domain;
b2cff0db
CW		 1345 int i;
1346
1347 spin_lock_irq(&dev_priv->uncore.lock);
1348 for_each_fw_domain(fw_domain, dev_priv, i) {
1349 seq_printf(m, "%s.wake_count = %u\n",
05a2fb15 1350 intel_uncore_forcewake_domain_to_str(i),
b2cff0db
CW		 1351 fw_domain->wake_count);
1352 }
1353 spin_unlock_irq(&dev_priv->uncore.lock);
669ab5aa 1354
b2cff0db
CW		 1355 return 0;
1356}
1357
1358static int vlv_drpc_info(struct seq_file *m)
1359{
9f25d007 1360 struct drm_info_node *node = m->private;
669ab5aa
D		 1361 struct drm_device *dev = node->minor->dev;
1362 struct drm_i915_private *dev_priv = dev->dev_private;
6b312cd3 1363 u32 rpmodectl1, rcctl1, pw_status;
669ab5aa 1364
d46c0517
ID		 1365 intel_runtime_pm_get(dev_priv);
1366
6b312cd3 1367 pw_status = I915_READ(VLV_GTLC_PW_STATUS);
669ab5aa
D		 1368 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1369 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1370
d46c0517
ID		 1371 intel_runtime_pm_put(dev_priv);
1372
669ab5aa
D		 1373 seq_printf(m, "Video Turbo Mode: %s\n",
1374 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1375 seq_printf(m, "Turbo enabled: %s\n",
1376 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1377 seq_printf(m, "HW control enabled: %s\n",
1378 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1379 seq_printf(m, "SW control enabled: %s\n",
1380 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1381 GEN6_RP_MEDIA_SW_MODE));
1382 seq_printf(m, "RC6 Enabled: %s\n",
1383 yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1384 GEN6_RC_CTL_EI_MODE(1))));
1385 seq_printf(m, "Render Power Well: %s\n",
6b312cd3 1386 (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
669ab5aa 1387 seq_printf(m, "Media Power Well: %s\n",
6b312cd3 1388 (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
669ab5aa 1389
9cc19be5
ID		 1390 seq_printf(m, "Render RC6 residency since boot: %u\n",
1391 I915_READ(VLV_GT_RENDER_RC6));
1392 seq_printf(m, "Media RC6 residency since boot: %u\n",
1393 I915_READ(VLV_GT_MEDIA_RC6));
1394
f65367b5 1395 return i915_forcewake_domains(m, NULL);
669ab5aa
D		 1396}
1397
4d85529d
BW		 1398static int gen6_drpc_info(struct seq_file *m)
1399{
9f25d007 1400 struct drm_info_node *node = m->private;
4d85529d
BW		 1401 struct drm_device *dev = node->minor->dev;
1402 struct drm_i915_private *dev_priv = dev->dev_private;
ecd8faea 1403 u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
93b525dc 1404 unsigned forcewake_count;
aee56cff 1405 int count = 0, ret;
4d85529d
BW		 1406
1407 ret = mutex_lock_interruptible(&dev->struct_mutex);
1408 if (ret)
1409 return ret;
c8c8fb33 1410 intel_runtime_pm_get(dev_priv);
4d85529d 1411
907b28c5 1412 spin_lock_irq(&dev_priv->uncore.lock);
b2cff0db 1413 forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count;
907b28c5 1414 spin_unlock_irq(&dev_priv->uncore.lock);
93b525dc
DV		 1415
1416 if (forcewake_count) {
267f0c90
DL		 1417 seq_puts(m, "RC information inaccurate because somebody "
1418 "holds a forcewake reference \n");
4d85529d
BW		 1419 } else {
1420 /* NB: we cannot use forcewake, else we read the wrong values */
1421 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1422 udelay(10);
1423 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1424 }
1425
1426 gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS);
ed71f1b4 1427 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
4d85529d
BW		 1428
1429 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1430 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1431 mutex_unlock(&dev->struct_mutex);
44cbd338
BW		 1432 mutex_lock(&dev_priv->rps.hw_lock);
1433 sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1434 mutex_unlock(&dev_priv->rps.hw_lock);
4d85529d 1435
c8c8fb33
PZ		 1436 intel_runtime_pm_put(dev_priv);
1437
4d85529d
BW		 1438 seq_printf(m, "Video Turbo Mode: %s\n",
1439 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1440 seq_printf(m, "HW control enabled: %s\n",
1441 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1442 seq_printf(m, "SW control enabled: %s\n",
1443 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1444 GEN6_RP_MEDIA_SW_MODE));
fff24e21 1445 seq_printf(m, "RC1e Enabled: %s\n",
4d85529d
BW		 1446 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1447 seq_printf(m, "RC6 Enabled: %s\n",
1448 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1449 seq_printf(m, "Deep RC6 Enabled: %s\n",
1450 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1451 seq_printf(m, "Deepest RC6 Enabled: %s\n",
1452 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
267f0c90 1453 seq_puts(m, "Current RC state: ");
4d85529d
BW		 1454 switch (gt_core_status & GEN6_RCn_MASK) {
1455 case GEN6_RC0:
1456 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
267f0c90 1457 seq_puts(m, "Core Power Down\n");
4d85529d 1458 else
267f0c90 1459 seq_puts(m, "on\n");
4d85529d
BW		 1460 break;
1461 case GEN6_RC3:
267f0c90 1462 seq_puts(m, "RC3\n");
4d85529d
BW		 1463 break;
1464 case GEN6_RC6:
267f0c90 1465 seq_puts(m, "RC6\n");
4d85529d
BW		 1466 break;
1467 case GEN6_RC7:
267f0c90 1468 seq_puts(m, "RC7\n");
4d85529d
BW		 1469 break;
1470 default:
267f0c90 1471 seq_puts(m, "Unknown\n");
4d85529d
BW		 1472 break;
1473 }
1474
1475 seq_printf(m, "Core Power Down: %s\n",
1476 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
cce66a28
BW		 1477
1478 /* Not exactly sure what this is */
1479 seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1480 I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1481 seq_printf(m, "RC6 residency since boot: %u\n",
1482 I915_READ(GEN6_GT_GFX_RC6));
1483 seq_printf(m, "RC6+ residency since boot: %u\n",
1484 I915_READ(GEN6_GT_GFX_RC6p));
1485 seq_printf(m, "RC6++ residency since boot: %u\n",
1486 I915_READ(GEN6_GT_GFX_RC6pp));
1487
ecd8faea
BW		 1488 seq_printf(m, "RC6 voltage: %dmV\n",
1489 GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1490 seq_printf(m, "RC6+ voltage: %dmV\n",
1491 GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1492 seq_printf(m, "RC6++ voltage: %dmV\n",
1493 GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
4d85529d
BW		 1494 return 0;
1495}
1496
1497static int i915_drpc_info(struct seq_file *m, void *unused)
1498{
9f25d007 1499 struct drm_info_node *node = m->private;
4d85529d
BW		 1500 struct drm_device *dev = node->minor->dev;
1501
669ab5aa
D		 1502 if (IS_VALLEYVIEW(dev))
1503 return vlv_drpc_info(m);
ac66cf4b 1504 else if (INTEL_INFO(dev)->gen >= 6)
4d85529d
BW		 1505 return gen6_drpc_info(m);
1506 else
1507 return ironlake_drpc_info(m);
1508}
1509
b5e50c3f
JB		 1510static int i915_fbc_status(struct seq_file *m, void *unused)
1511{
9f25d007 1512 struct drm_info_node *node = m->private;
b5e50c3f 1513 struct drm_device *dev = node->minor->dev;
e277a1f8 1514 struct drm_i915_private *dev_priv = dev->dev_private;
b5e50c3f 1515
3a77c4c4 1516 if (!HAS_FBC(dev)) {
267f0c90 1517 seq_puts(m, "FBC unsupported on this chipset\n");
b5e50c3f
JB		 1518 return 0;
1519 }
1520
36623ef8
PZ		 1521 intel_runtime_pm_get(dev_priv);
1522
ee5382ae 1523 if (intel_fbc_enabled(dev)) {
267f0c90 1524 seq_puts(m, "FBC enabled\n");
b5e50c3f 1525 } else {
267f0c90 1526 seq_puts(m, "FBC disabled: ");
5c3fe8b0 1527 switch (dev_priv->fbc.no_fbc_reason) {
29ebf90f
CW		 1528 case FBC_OK:
1529 seq_puts(m, "FBC actived, but currently disabled in hardware");
1530 break;
1531 case FBC_UNSUPPORTED:
1532 seq_puts(m, "unsupported by this chipset");
1533 break;
bed4a673 1534 case FBC_NO_OUTPUT:
267f0c90 1535 seq_puts(m, "no outputs");
bed4a673 1536 break;
b5e50c3f 1537 case FBC_STOLEN_TOO_SMALL:
267f0c90 1538 seq_puts(m, "not enough stolen memory");
b5e50c3f
JB		 1539 break;
1540 case FBC_UNSUPPORTED_MODE:
267f0c90 1541 seq_puts(m, "mode not supported");
b5e50c3f
JB		 1542 break;
1543 case FBC_MODE_TOO_LARGE:
267f0c90 1544 seq_puts(m, "mode too large");
b5e50c3f
JB		 1545 break;
1546 case FBC_BAD_PLANE:
267f0c90 1547 seq_puts(m, "FBC unsupported on plane");
b5e50c3f
JB		 1548 break;
1549 case FBC_NOT_TILED:
267f0c90 1550 seq_puts(m, "scanout buffer not tiled");
b5e50c3f 1551 break;
9c928d16 1552 case FBC_MULTIPLE_PIPES:
267f0c90 1553 seq_puts(m, "multiple pipes are enabled");
9c928d16 1554 break;
c1a9f047 1555 case FBC_MODULE_PARAM:
267f0c90 1556 seq_puts(m, "disabled per module param (default off)");
c1a9f047 1557 break;
8a5729a3 1558 case FBC_CHIP_DEFAULT:
267f0c90 1559 seq_puts(m, "disabled per chip default");
8a5729a3 1560 break;
b5e50c3f 1561 default:
267f0c90 1562 seq_puts(m, "unknown reason");
b5e50c3f 1563 }
267f0c90 1564 seq_putc(m, '\n');
b5e50c3f 1565 }
36623ef8
PZ		 1566
1567 intel_runtime_pm_put(dev_priv);
1568
b5e50c3f
JB		 1569 return 0;
1570}
1571
da46f936
RV		 1572static int i915_fbc_fc_get(void *data, u64 *val)
1573{
1574 struct drm_device *dev = data;
1575 struct drm_i915_private *dev_priv = dev->dev_private;
1576
1577 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1578 return -ENODEV;
1579
1580 drm_modeset_lock_all(dev);
1581 *val = dev_priv->fbc.false_color;
1582 drm_modeset_unlock_all(dev);
1583
1584 return 0;
1585}
1586
1587static int i915_fbc_fc_set(void *data, u64 val)
1588{
1589 struct drm_device *dev = data;
1590 struct drm_i915_private *dev_priv = dev->dev_private;
1591 u32 reg;
1592
1593 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1594 return -ENODEV;
1595
1596 drm_modeset_lock_all(dev);
1597
1598 reg = I915_READ(ILK_DPFC_CONTROL);
1599 dev_priv->fbc.false_color = val;
1600
1601 I915_WRITE(ILK_DPFC_CONTROL, val ?
1602 (reg | FBC_CTL_FALSE_COLOR) :
1603 (reg & ~FBC_CTL_FALSE_COLOR));
1604
1605 drm_modeset_unlock_all(dev);
1606 return 0;
1607}
1608
1609DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops,
1610 i915_fbc_fc_get, i915_fbc_fc_set,
1611 "%llu\n");
1612
92d44621
PZ		 1613static int i915_ips_status(struct seq_file *m, void *unused)
1614{
9f25d007 1615 struct drm_info_node *node = m->private;
92d44621
PZ		 1616 struct drm_device *dev = node->minor->dev;
1617 struct drm_i915_private *dev_priv = dev->dev_private;
1618
f5adf94e 1619 if (!HAS_IPS(dev)) {
92d44621
PZ		 1620 seq_puts(m, "not supported\n");
1621 return 0;
1622 }
1623
36623ef8
PZ		 1624 intel_runtime_pm_get(dev_priv);
1625
0eaa53f0
RV		 1626 seq_printf(m, "Enabled by kernel parameter: %s\n",
1627 yesno(i915.enable_ips));
1628
1629 if (INTEL_INFO(dev)->gen >= 8) {
1630 seq_puts(m, "Currently: unknown\n");
1631 } else {
1632 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1633 seq_puts(m, "Currently: enabled\n");
1634 else
1635 seq_puts(m, "Currently: disabled\n");
1636 }
92d44621 1637
36623ef8
PZ		 1638 intel_runtime_pm_put(dev_priv);
1639
92d44621
PZ		 1640 return 0;
1641}
1642
4a9bef37
JB		 1643static int i915_sr_status(struct seq_file *m, void *unused)
1644{
9f25d007 1645 struct drm_info_node *node = m->private;
4a9bef37 1646 struct drm_device *dev = node->minor->dev;
e277a1f8 1647 struct drm_i915_private *dev_priv = dev->dev_private;
4a9bef37
JB		 1648 bool sr_enabled = false;
1649
36623ef8
PZ		 1650 intel_runtime_pm_get(dev_priv);
1651
1398261a 1652 if (HAS_PCH_SPLIT(dev))
5ba2aaaa 1653 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
a6c45cf0 1654 else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))
4a9bef37
JB		 1655 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1656 else if (IS_I915GM(dev))
1657 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1658 else if (IS_PINEVIEW(dev))
1659 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1660
36623ef8
PZ		 1661 intel_runtime_pm_put(dev_priv);
1662
5ba2aaaa
CW		 1663 seq_printf(m, "self-refresh: %s\n",
1664 sr_enabled ? "enabled" : "disabled");
4a9bef37
JB		 1665
1666 return 0;
1667}
1668
7648fa99
JB		 1669static int i915_emon_status(struct seq_file *m, void *unused)
1670{
9f25d007 1671 struct drm_info_node *node = m->private;
7648fa99 1672 struct drm_device *dev = node->minor->dev;
e277a1f8 1673 struct drm_i915_private *dev_priv = dev->dev_private;
7648fa99 1674 unsigned long temp, chipset, gfx;
de227ef0
CW		 1675 int ret;
1676
582be6b4
CW		 1677 if (!IS_GEN5(dev))
1678 return -ENODEV;
1679
de227ef0
CW		 1680 ret = mutex_lock_interruptible(&dev->struct_mutex);
1681 if (ret)
1682 return ret;
7648fa99
JB		 1683
1684 temp = i915_mch_val(dev_priv);
1685 chipset = i915_chipset_val(dev_priv);
1686 gfx = i915_gfx_val(dev_priv);
de227ef0 1687 mutex_unlock(&dev->struct_mutex);
7648fa99
JB		 1688
1689 seq_printf(m, "GMCH temp: %ld\n", temp);
1690 seq_printf(m, "Chipset power: %ld\n", chipset);
1691 seq_printf(m, "GFX power: %ld\n", gfx);
1692 seq_printf(m, "Total power: %ld\n", chipset + gfx);
1693
1694 return 0;
1695}
1696
23b2f8bb
JB		 1697static int i915_ring_freq_table(struct seq_file *m, void *unused)
1698{
9f25d007 1699 struct drm_info_node *node = m->private;
23b2f8bb 1700 struct drm_device *dev = node->minor->dev;
e277a1f8 1701 struct drm_i915_private *dev_priv = dev->dev_private;
5bfa0199 1702 int ret = 0;
23b2f8bb
JB		 1703 int gpu_freq, ia_freq;
1704
1c70c0ce 1705 if (!(IS_GEN6(dev) || IS_GEN7(dev))) {
267f0c90 1706 seq_puts(m, "unsupported on this chipset\n");
23b2f8bb
JB		 1707 return 0;
1708 }
1709
5bfa0199
PZ		 1710 intel_runtime_pm_get(dev_priv);
1711
5c9669ce
TR		 1712 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1713
4fc688ce 1714 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
23b2f8bb 1715 if (ret)
5bfa0199 1716 goto out;
23b2f8bb 1717
267f0c90 1718 seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
23b2f8bb 1719
b39fb297
BW		 1720 for (gpu_freq = dev_priv->rps.min_freq_softlimit;
1721 gpu_freq <= dev_priv->rps.max_freq_softlimit;
23b2f8bb 1722 gpu_freq++) {
42c0526c
BW		 1723 ia_freq = gpu_freq;
1724 sandybridge_pcode_read(dev_priv,
1725 GEN6_PCODE_READ_MIN_FREQ_TABLE,
1726 &ia_freq);
3ebecd07 1727 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
7c59a9c1 1728 intel_gpu_freq(dev_priv, gpu_freq),
3ebecd07
CW		 1729 ((ia_freq >> 0) & 0xff) * 100,
1730 ((ia_freq >> 8) & 0xff) * 100);
23b2f8bb
JB		 1731 }
1732
4fc688ce 1733 mutex_unlock(&dev_priv->rps.hw_lock);
23b2f8bb 1734
5bfa0199
PZ		 1735out:
1736 intel_runtime_pm_put(dev_priv);
1737 return ret;
23b2f8bb
JB		 1738}
1739
44834a67
CW		 1740static int i915_opregion(struct seq_file *m, void *unused)
1741{
9f25d007 1742 struct drm_info_node *node = m->private;
44834a67 1743 struct drm_device *dev = node->minor->dev;
e277a1f8 1744 struct drm_i915_private *dev_priv = dev->dev_private;
44834a67 1745 struct intel_opregion *opregion = &dev_priv->opregion;
0d38f009 1746 void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL);
44834a67
CW		 1747 int ret;
1748
0d38f009
DV		 1749 if (data == NULL)
1750 return -ENOMEM;
1751
44834a67
CW		 1752 ret = mutex_lock_interruptible(&dev->struct_mutex);
1753 if (ret)
0d38f009 1754 goto out;
44834a67 1755
0d38f009
DV		 1756 if (opregion->header) {
1757 memcpy_fromio(data, opregion->header, OPREGION_SIZE);
1758 seq_write(m, data, OPREGION_SIZE);
1759 }
44834a67
CW		 1760
1761 mutex_unlock(&dev->struct_mutex);
1762
0d38f009
DV		 1763out:
1764 kfree(data);
44834a67
CW		 1765 return 0;
1766}
1767
37811fcc
CW		 1768static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1769{
9f25d007 1770 struct drm_info_node *node = m->private;
37811fcc 1771 struct drm_device *dev = node->minor->dev;
4520f53a 1772 struct intel_fbdev *ifbdev = NULL;
37811fcc 1773 struct intel_framebuffer *fb;
37811fcc 1774
4520f53a
DV		 1775#ifdef CONFIG_DRM_I915_FBDEV
1776 struct drm_i915_private *dev_priv = dev->dev_private;
37811fcc
CW		 1777
1778 ifbdev = dev_priv->fbdev;
1779 fb = to_intel_framebuffer(ifbdev->helper.fb);
1780
623f9783 1781 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
37811fcc
CW		 1782 fb->base.width,
1783 fb->base.height,
1784 fb->base.depth,
623f9783
DV		 1785 fb->base.bits_per_pixel,
1786 atomic_read(&fb->base.refcount.refcount));
05394f39 1787 describe_obj(m, fb->obj);
267f0c90 1788 seq_putc(m, '\n');
4520f53a 1789#endif
37811fcc 1790
4b096ac1 1791 mutex_lock(&dev->mode_config.fb_lock);
37811fcc 1792 list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) {
131a56dc 1793 if (ifbdev && &fb->base == ifbdev->helper.fb)
37811fcc
CW		 1794 continue;
1795
623f9783 1796 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
37811fcc
CW		 1797 fb->base.width,
1798 fb->base.height,
1799 fb->base.depth,
623f9783
DV		 1800 fb->base.bits_per_pixel,
1801 atomic_read(&fb->base.refcount.refcount));
05394f39 1802 describe_obj(m, fb->obj);
267f0c90 1803 seq_putc(m, '\n');
37811fcc 1804 }
4b096ac1 1805 mutex_unlock(&dev->mode_config.fb_lock);
37811fcc
CW		 1806
1807 return 0;
1808}
1809
c9fe99bd
OM		 1810static void describe_ctx_ringbuf(struct seq_file *m,
1811 struct intel_ringbuffer *ringbuf)
1812{
1813 seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
1814 ringbuf->space, ringbuf->head, ringbuf->tail,
1815 ringbuf->last_retired_head);
1816}
1817
e76d3630
BW		 1818static int i915_context_status(struct seq_file *m, void *unused)
1819{
9f25d007 1820 struct drm_info_node *node = m->private;
e76d3630 1821 struct drm_device *dev = node->minor->dev;
e277a1f8 1822 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 1823 struct intel_engine_cs *ring;
273497e5 1824 struct intel_context *ctx;
a168c293 1825 int ret, i;
e76d3630 1826
f3d28878 1827 ret = mutex_lock_interruptible(&dev->struct_mutex);
e76d3630
BW		 1828 if (ret)
1829 return ret;
1830
3e373948 1831 if (dev_priv->ips.pwrctx) {
267f0c90 1832 seq_puts(m, "power context ");
3e373948 1833 describe_obj(m, dev_priv->ips.pwrctx);
267f0c90 1834 seq_putc(m, '\n');
dc501fbc 1835 }
e76d3630 1836
3e373948 1837 if (dev_priv->ips.renderctx) {
267f0c90 1838 seq_puts(m, "render context ");
3e373948 1839 describe_obj(m, dev_priv->ips.renderctx);
267f0c90 1840 seq_putc(m, '\n');
dc501fbc 1841 }
e76d3630 1842
a33afea5 1843 list_for_each_entry(ctx, &dev_priv->context_list, link) {
c9fe99bd
OM		 1844 if (!i915.enable_execlists &&
1845 ctx->legacy_hw_ctx.rcs_state == NULL)
b77f6997
CW		 1846 continue;
1847
a33afea5 1848 seq_puts(m, "HW context ");
3ccfd19d 1849 describe_ctx(m, ctx);
c9fe99bd 1850 for_each_ring(ring, dev_priv, i) {
a33afea5 1851 if (ring->default_context == ctx)
c9fe99bd
OM		 1852 seq_printf(m, "(default context %s) ",
1853 ring->name);
1854 }
1855
1856 if (i915.enable_execlists) {
1857 seq_putc(m, '\n');
1858 for_each_ring(ring, dev_priv, i) {
1859 struct drm_i915_gem_object *ctx_obj =
1860 ctx->engine[i].state;
1861 struct intel_ringbuffer *ringbuf =
1862 ctx->engine[i].ringbuf;
1863
1864 seq_printf(m, "%s: ", ring->name);
1865 if (ctx_obj)
1866 describe_obj(m, ctx_obj);
1867 if (ringbuf)
1868 describe_ctx_ringbuf(m, ringbuf);
1869 seq_putc(m, '\n');
1870 }
1871 } else {
1872 describe_obj(m, ctx->legacy_hw_ctx.rcs_state);
1873 }
a33afea5 1874
a33afea5 1875 seq_putc(m, '\n');
a168c293
BW		 1876 }
1877
f3d28878 1878 mutex_unlock(&dev->struct_mutex);
e76d3630
BW		 1879
1880 return 0;
1881}
1882
064ca1d2
TD		 1883static void i915_dump_lrc_obj(struct seq_file *m,
1884 struct intel_engine_cs *ring,
1885 struct drm_i915_gem_object *ctx_obj)
1886{
1887 struct page *page;
1888 uint32_t *reg_state;
1889 int j;
1890 unsigned long ggtt_offset = 0;
1891
1892 if (ctx_obj == NULL) {
1893 seq_printf(m, "Context on %s with no gem object\n",
1894 ring->name);
1895 return;
1896 }
1897
1898 seq_printf(m, "CONTEXT: %s %u\n", ring->name,
1899 intel_execlists_ctx_id(ctx_obj));
1900
1901 if (!i915_gem_obj_ggtt_bound(ctx_obj))
1902 seq_puts(m, "\tNot bound in GGTT\n");
1903 else
1904 ggtt_offset = i915_gem_obj_ggtt_offset(ctx_obj);
1905
1906 if (i915_gem_object_get_pages(ctx_obj)) {
1907 seq_puts(m, "\tFailed to get pages for context object\n");
1908 return;
1909 }
1910
1911 page = i915_gem_object_get_page(ctx_obj, 1);
1912 if (!WARN_ON(page == NULL)) {
1913 reg_state = kmap_atomic(page);
1914
1915 for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
1916 seq_printf(m, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n",
1917 ggtt_offset + 4096 + (j * 4),
1918 reg_state[j], reg_state[j + 1],
1919 reg_state[j + 2], reg_state[j + 3]);
1920 }
1921 kunmap_atomic(reg_state);
1922 }
1923
1924 seq_putc(m, '\n');
1925}
1926
c0ab1ae9
BW		 1927static int i915_dump_lrc(struct seq_file *m, void *unused)
1928{
1929 struct drm_info_node *node = (struct drm_info_node *) m->private;
1930 struct drm_device *dev = node->minor->dev;
1931 struct drm_i915_private *dev_priv = dev->dev_private;
1932 struct intel_engine_cs *ring;
1933 struct intel_context *ctx;
1934 int ret, i;
1935
1936 if (!i915.enable_execlists) {
1937 seq_printf(m, "Logical Ring Contexts are disabled\n");
1938 return 0;
1939 }
1940
1941 ret = mutex_lock_interruptible(&dev->struct_mutex);
1942 if (ret)
1943 return ret;
1944
1945 list_for_each_entry(ctx, &dev_priv->context_list, link) {
1946 for_each_ring(ring, dev_priv, i) {
064ca1d2
TD		 1947 if (ring->default_context != ctx)
1948 i915_dump_lrc_obj(m, ring,
1949 ctx->engine[i].state);
c0ab1ae9
BW		 1950 }
1951 }
1952
1953 mutex_unlock(&dev->struct_mutex);
1954
1955 return 0;
1956}
1957
4ba70e44
OM		 1958static int i915_execlists(struct seq_file *m, void *data)
1959{
1960 struct drm_info_node *node = (struct drm_info_node *)m->private;
1961 struct drm_device *dev = node->minor->dev;
1962 struct drm_i915_private *dev_priv = dev->dev_private;
1963 struct intel_engine_cs *ring;
1964 u32 status_pointer;
1965 u8 read_pointer;
1966 u8 write_pointer;
1967 u32 status;
1968 u32 ctx_id;
1969 struct list_head *cursor;
1970 int ring_id, i;
1971 int ret;
1972
1973 if (!i915.enable_execlists) {
1974 seq_puts(m, "Logical Ring Contexts are disabled\n");
1975 return 0;
1976 }
1977
1978 ret = mutex_lock_interruptible(&dev->struct_mutex);
1979 if (ret)
1980 return ret;
1981
fc0412ec
MT		 1982 intel_runtime_pm_get(dev_priv);
1983
4ba70e44 1984 for_each_ring(ring, dev_priv, ring_id) {
6d3d8274 1985 struct drm_i915_gem_request *head_req = NULL;
4ba70e44
OM		 1986 int count = 0;
1987 unsigned long flags;
1988
1989 seq_printf(m, "%s\n", ring->name);
1990
1991 status = I915_READ(RING_EXECLIST_STATUS(ring));
1992 ctx_id = I915_READ(RING_EXECLIST_STATUS(ring) + 4);
1993 seq_printf(m, "\tExeclist status: 0x%08X, context: %u\n",
1994 status, ctx_id);
1995
1996 status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(ring));
1997 seq_printf(m, "\tStatus pointer: 0x%08X\n", status_pointer);
1998
1999 read_pointer = ring->next_context_status_buffer;
2000 write_pointer = status_pointer & 0x07;
2001 if (read_pointer > write_pointer)
2002 write_pointer += 6;
2003 seq_printf(m, "\tRead pointer: 0x%08X, write pointer 0x%08X\n",
2004 read_pointer, write_pointer);
2005
2006 for (i = 0; i < 6; i++) {
2007 status = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + 8*i);
2008 ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + 8*i + 4);
2009
2010 seq_printf(m, "\tStatus buffer %d: 0x%08X, context: %u\n",
2011 i, status, ctx_id);
2012 }
2013
2014 spin_lock_irqsave(&ring->execlist_lock, flags);
2015 list_for_each(cursor, &ring->execlist_queue)
2016 count++;
2017 head_req = list_first_entry_or_null(&ring->execlist_queue,
6d3d8274 2018 struct drm_i915_gem_request, execlist_link);
4ba70e44
OM		 2019 spin_unlock_irqrestore(&ring->execlist_lock, flags);
2020
2021 seq_printf(m, "\t%d requests in queue\n", count);
2022 if (head_req) {
2023 struct drm_i915_gem_object *ctx_obj;
2024
6d3d8274 2025 ctx_obj = head_req->ctx->engine[ring_id].state;
4ba70e44
OM		 2026 seq_printf(m, "\tHead request id: %u\n",
2027 intel_execlists_ctx_id(ctx_obj));
2028 seq_printf(m, "\tHead request tail: %u\n",
6d3d8274 2029 head_req->tail);
4ba70e44
OM		 2030 }
2031
2032 seq_putc(m, '\n');
2033 }
2034
fc0412ec 2035 intel_runtime_pm_put(dev_priv);
4ba70e44
OM		 2036 mutex_unlock(&dev->struct_mutex);
2037
2038 return 0;
2039}
2040
ea16a3cd
DV		 2041static const char *swizzle_string(unsigned swizzle)
2042{
aee56cff 2043 switch (swizzle) {
ea16a3cd
DV		 2044 case I915_BIT_6_SWIZZLE_NONE:
2045 return "none";
2046 case I915_BIT_6_SWIZZLE_9:
2047 return "bit9";
2048 case I915_BIT_6_SWIZZLE_9_10:
2049 return "bit9/bit10";
2050 case I915_BIT_6_SWIZZLE_9_11:
2051 return "bit9/bit11";
2052 case I915_BIT_6_SWIZZLE_9_10_11:
2053 return "bit9/bit10/bit11";
2054 case I915_BIT_6_SWIZZLE_9_17:
2055 return "bit9/bit17";
2056 case I915_BIT_6_SWIZZLE_9_10_17:
2057 return "bit9/bit10/bit17";
2058 case I915_BIT_6_SWIZZLE_UNKNOWN:
8a168ca7 2059 return "unknown";
ea16a3cd
DV		 2060 }
2061
2062 return "bug";
2063}
2064
2065static int i915_swizzle_info(struct seq_file *m, void *data)
2066{
9f25d007 2067 struct drm_info_node *node = m->private;
ea16a3cd
DV		 2068 struct drm_device *dev = node->minor->dev;
2069 struct drm_i915_private *dev_priv = dev->dev_private;
22bcfc6a
DV		 2070 int ret;
2071
2072 ret = mutex_lock_interruptible(&dev->struct_mutex);
2073 if (ret)
2074 return ret;
c8c8fb33 2075 intel_runtime_pm_get(dev_priv);
ea16a3cd 2076
ea16a3cd
DV		 2077 seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
2078 swizzle_string(dev_priv->mm.bit_6_swizzle_x));
2079 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
2080 swizzle_string(dev_priv->mm.bit_6_swizzle_y));
2081
2082 if (IS_GEN3(dev) || IS_GEN4(dev)) {
2083 seq_printf(m, "DDC = 0x%08x\n",
2084 I915_READ(DCC));
656bfa3a
DV		 2085 seq_printf(m, "DDC2 = 0x%08x\n",
2086 I915_READ(DCC2));
ea16a3cd
DV		 2087 seq_printf(m, "C0DRB3 = 0x%04x\n",
2088 I915_READ16(C0DRB3));
2089 seq_printf(m, "C1DRB3 = 0x%04x\n",
2090 I915_READ16(C1DRB3));
9d3203e1 2091 } else if (INTEL_INFO(dev)->gen >= 6) {
3fa7d235
DV		 2092 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
2093 I915_READ(MAD_DIMM_C0));
2094 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
2095 I915_READ(MAD_DIMM_C1));
2096 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
2097 I915_READ(MAD_DIMM_C2));
2098 seq_printf(m, "TILECTL = 0x%08x\n",
2099 I915_READ(TILECTL));
5907f5fb 2100 if (INTEL_INFO(dev)->gen >= 8)
9d3203e1
BW		 2101 seq_printf(m, "GAMTARBMODE = 0x%08x\n",
2102 I915_READ(GAMTARBMODE));
2103 else
2104 seq_printf(m, "ARB_MODE = 0x%08x\n",
2105 I915_READ(ARB_MODE));
3fa7d235
DV		 2106 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
2107 I915_READ(DISP_ARB_CTL));
ea16a3cd 2108 }
656bfa3a
DV		 2109
2110 if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2111 seq_puts(m, "L-shaped memory detected\n");
2112
c8c8fb33 2113 intel_runtime_pm_put(dev_priv);
ea16a3cd
DV		 2114 mutex_unlock(&dev->struct_mutex);
2115
2116 return 0;
2117}
2118
1c60fef5
BW		 2119static int per_file_ctx(int id, void *ptr, void *data)
2120{
273497e5 2121 struct intel_context *ctx = ptr;
1c60fef5 2122 struct seq_file *m = data;
ae6c4806
DV		 2123 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2124
2125 if (!ppgtt) {
2126 seq_printf(m, " no ppgtt for context %d\n",
2127 ctx->user_handle);
2128 return 0;
2129 }
1c60fef5 2130
f83d6518
OM		 2131 if (i915_gem_context_is_default(ctx))
2132 seq_puts(m, " default context:\n");
2133 else
821d66dd 2134 seq_printf(m, " context %d:\n", ctx->user_handle);
1c60fef5
BW		 2135 ppgtt->debug_dump(ppgtt, m);
2136
2137 return 0;
2138}
2139
77df6772 2140static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev)
3cf17fc5 2141{
3cf17fc5 2142 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2143 struct intel_engine_cs *ring;
77df6772
BW		 2144 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2145 int unused, i;
3cf17fc5 2146
77df6772
BW		 2147 if (!ppgtt)
2148 return;
2149
2150 seq_printf(m, "Page directories: %d\n", ppgtt->num_pd_pages);
5abbcca3 2151 seq_printf(m, "Page tables: %d\n", ppgtt->num_pd_entries);
77df6772
BW		 2152 for_each_ring(ring, dev_priv, unused) {
2153 seq_printf(m, "%s\n", ring->name);
2154 for (i = 0; i < 4; i++) {
2155 u32 offset = 0x270 + i * 8;
2156 u64 pdp = I915_READ(ring->mmio_base + offset + 4);
2157 pdp <<= 32;
2158 pdp |= I915_READ(ring->mmio_base + offset);
a2a5b15c 2159 seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
77df6772
BW		 2160 }
2161 }
2162}
2163
2164static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2165{
2166 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2167 struct intel_engine_cs *ring;
1c60fef5 2168 struct drm_file *file;
77df6772 2169 int i;
3cf17fc5 2170
3cf17fc5
DV		 2171 if (INTEL_INFO(dev)->gen == 6)
2172 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
2173
a2c7f6fd 2174 for_each_ring(ring, dev_priv, i) {
3cf17fc5
DV		 2175 seq_printf(m, "%s\n", ring->name);
2176 if (INTEL_INFO(dev)->gen == 7)
2177 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
2178 seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
2179 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
2180 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring)));
2181 }
2182 if (dev_priv->mm.aliasing_ppgtt) {
2183 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2184
267f0c90 2185 seq_puts(m, "aliasing PPGTT:\n");
3cf17fc5 2186 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset);
1c60fef5 2187
87d60b63 2188 ppgtt->debug_dump(ppgtt, m);
ae6c4806 2189 }
1c60fef5
BW		 2190
2191 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2192 struct drm_i915_file_private *file_priv = file->driver_priv;
1c60fef5 2193
1c60fef5
BW		 2194 seq_printf(m, "proc: %s\n",
2195 get_pid_task(file->pid, PIDTYPE_PID)->comm);
1c60fef5 2196 idr_for_each(&file_priv->context_idr, per_file_ctx, m);
3cf17fc5
DV		 2197 }
2198 seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
77df6772
BW		 2199}
2200
2201static int i915_ppgtt_info(struct seq_file *m, void *data)
2202{
9f25d007 2203 struct drm_info_node *node = m->private;
77df6772 2204 struct drm_device *dev = node->minor->dev;
c8c8fb33 2205 struct drm_i915_private *dev_priv = dev->dev_private;
77df6772
BW		 2206
2207 int ret = mutex_lock_interruptible(&dev->struct_mutex);
2208 if (ret)
2209 return ret;
c8c8fb33 2210 intel_runtime_pm_get(dev_priv);
77df6772
BW		 2211
2212 if (INTEL_INFO(dev)->gen >= 8)
2213 gen8_ppgtt_info(m, dev);
2214 else if (INTEL_INFO(dev)->gen >= 6)
2215 gen6_ppgtt_info(m, dev);
2216
c8c8fb33 2217 intel_runtime_pm_put(dev_priv);
3cf17fc5
DV		 2218 mutex_unlock(&dev->struct_mutex);
2219
2220 return 0;
2221}
2222
63573eb7
BW		 2223static int i915_llc(struct seq_file *m, void *data)
2224{
9f25d007 2225 struct drm_info_node *node = m->private;
63573eb7
BW		 2226 struct drm_device *dev = node->minor->dev;
2227 struct drm_i915_private *dev_priv = dev->dev_private;
2228
2229 /* Size calculation for LLC is a bit of a pain. Ignore for now. */
2230 seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
2231 seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size);
2232
2233 return 0;
2234}
2235
e91fd8c6
RV		 2236static int i915_edp_psr_status(struct seq_file *m, void *data)
2237{
2238 struct drm_info_node *node = m->private;
2239 struct drm_device *dev = node->minor->dev;
2240 struct drm_i915_private *dev_priv = dev->dev_private;
a031d709 2241 u32 psrperf = 0;
a6cbdb8e
RV		 2242 u32 stat[3];
2243 enum pipe pipe;
a031d709 2244 bool enabled = false;
e91fd8c6 2245
c8c8fb33
PZ		 2246 intel_runtime_pm_get(dev_priv);
2247
fa128fa6 2248 mutex_lock(&dev_priv->psr.lock);
a031d709
RV		 2249 seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
2250 seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
2807cf69 2251 seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
5755c78f 2252 seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
fa128fa6
DV		 2253 seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
2254 dev_priv->psr.busy_frontbuffer_bits);
2255 seq_printf(m, "Re-enable work scheduled: %s\n",
2256 yesno(work_busy(&dev_priv->psr.work.work)));
e91fd8c6 2257
a6cbdb8e
RV		 2258 if (HAS_PSR(dev)) {
2259 if (HAS_DDI(dev))
2260 enabled = I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
2261 else {
2262 for_each_pipe(dev_priv, pipe) {
2263 stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
2264 VLV_EDP_PSR_CURR_STATE_MASK;
2265 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2266 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2267 enabled = true;
2268 }
2269 }
2270 }
2271 seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));
2272
2273 if (!HAS_DDI(dev))
2274 for_each_pipe(dev_priv, pipe) {
2275 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2276 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2277 seq_printf(m, " pipe %c", pipe_name(pipe));
2278 }
2279 seq_puts(m, "\n");
e91fd8c6 2280
fb495814
RV		 2281 seq_printf(m, "Link standby: %s\n",
2282 yesno((bool)dev_priv->psr.link_standby));
2283
a6cbdb8e
RV		 2284 /* CHV PSR has no kind of performance counter */
2285 if (HAS_PSR(dev) && HAS_DDI(dev)) {
a031d709
RV		 2286 psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) &
2287 EDP_PSR_PERF_CNT_MASK;
a6cbdb8e
RV		 2288
2289 seq_printf(m, "Performance_Counter: %u\n", psrperf);
2290 }
fa128fa6 2291 mutex_unlock(&dev_priv->psr.lock);
e91fd8c6 2292
c8c8fb33 2293 intel_runtime_pm_put(dev_priv);
e91fd8c6
RV		 2294 return 0;
2295}
2296
d2e216d0
RV		 2297static int i915_sink_crc(struct seq_file *m, void *data)
2298{
2299 struct drm_info_node *node = m->private;
2300 struct drm_device *dev = node->minor->dev;
2301 struct intel_encoder *encoder;
2302 struct intel_connector *connector;
2303 struct intel_dp *intel_dp = NULL;
2304 int ret;
2305 u8 crc[6];
2306
2307 drm_modeset_lock_all(dev);
2308 list_for_each_entry(connector, &dev->mode_config.connector_list,
2309 base.head) {
2310
2311 if (connector->base.dpms != DRM_MODE_DPMS_ON)
2312 continue;
2313
b6ae3c7c
PZ		 2314 if (!connector->base.encoder)
2315 continue;
2316
d2e216d0
RV		 2317 encoder = to_intel_encoder(connector->base.encoder);
2318 if (encoder->type != INTEL_OUTPUT_EDP)
2319 continue;
2320
2321 intel_dp = enc_to_intel_dp(&encoder->base);
2322
2323 ret = intel_dp_sink_crc(intel_dp, crc);
2324 if (ret)
2325 goto out;
2326
2327 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2328 crc[0], crc[1], crc[2],
2329 crc[3], crc[4], crc[5]);
2330 goto out;
2331 }
2332 ret = -ENODEV;
2333out:
2334 drm_modeset_unlock_all(dev);
2335 return ret;
2336}
2337
ec013e7f
JB		 2338static int i915_energy_uJ(struct seq_file *m, void *data)
2339{
2340 struct drm_info_node *node = m->private;
2341 struct drm_device *dev = node->minor->dev;
2342 struct drm_i915_private *dev_priv = dev->dev_private;
2343 u64 power;
2344 u32 units;
2345
2346 if (INTEL_INFO(dev)->gen < 6)
2347 return -ENODEV;
2348
36623ef8
PZ		 2349 intel_runtime_pm_get(dev_priv);
2350
ec013e7f
JB		 2351 rdmsrl(MSR_RAPL_POWER_UNIT, power);
2352 power = (power & 0x1f00) >> 8;
2353 units = 1000000 / (1 << power); /* convert to uJ */
2354 power = I915_READ(MCH_SECP_NRG_STTS);
2355 power *= units;
2356
36623ef8
PZ		 2357 intel_runtime_pm_put(dev_priv);
2358
ec013e7f 2359 seq_printf(m, "%llu", (long long unsigned)power);
371db66a
PZ		 2360
2361 return 0;
2362}
2363
2364static int i915_pc8_status(struct seq_file *m, void *unused)
2365{
9f25d007 2366 struct drm_info_node *node = m->private;
371db66a
PZ		 2367 struct drm_device *dev = node->minor->dev;
2368 struct drm_i915_private *dev_priv = dev->dev_private;
2369
85b8d5c2 2370 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
371db66a
PZ		 2371 seq_puts(m, "not supported\n");
2372 return 0;
2373 }
2374
86c4ec0d 2375 seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy));
371db66a 2376 seq_printf(m, "IRQs disabled: %s\n",
9df7575f 2377 yesno(!intel_irqs_enabled(dev_priv)));
371db66a 2378
ec013e7f
JB		 2379 return 0;
2380}
2381
1da51581
ID		 2382static const char *power_domain_str(enum intel_display_power_domain domain)
2383{
2384 switch (domain) {
2385 case POWER_DOMAIN_PIPE_A:
2386 return "PIPE_A";
2387 case POWER_DOMAIN_PIPE_B:
2388 return "PIPE_B";
2389 case POWER_DOMAIN_PIPE_C:
2390 return "PIPE_C";
2391 case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
2392 return "PIPE_A_PANEL_FITTER";
2393 case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
2394 return "PIPE_B_PANEL_FITTER";
2395 case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
2396 return "PIPE_C_PANEL_FITTER";
2397 case POWER_DOMAIN_TRANSCODER_A:
2398 return "TRANSCODER_A";
2399 case POWER_DOMAIN_TRANSCODER_B:
2400 return "TRANSCODER_B";
2401 case POWER_DOMAIN_TRANSCODER_C:
2402 return "TRANSCODER_C";
2403 case POWER_DOMAIN_TRANSCODER_EDP:
2404 return "TRANSCODER_EDP";
319be8ae
ID		 2405 case POWER_DOMAIN_PORT_DDI_A_2_LANES:
2406 return "PORT_DDI_A_2_LANES";
2407 case POWER_DOMAIN_PORT_DDI_A_4_LANES:
2408 return "PORT_DDI_A_4_LANES";
2409 case POWER_DOMAIN_PORT_DDI_B_2_LANES:
2410 return "PORT_DDI_B_2_LANES";
2411 case POWER_DOMAIN_PORT_DDI_B_4_LANES:
2412 return "PORT_DDI_B_4_LANES";
2413 case POWER_DOMAIN_PORT_DDI_C_2_LANES:
2414 return "PORT_DDI_C_2_LANES";
2415 case POWER_DOMAIN_PORT_DDI_C_4_LANES:
2416 return "PORT_DDI_C_4_LANES";
2417 case POWER_DOMAIN_PORT_DDI_D_2_LANES:
2418 return "PORT_DDI_D_2_LANES";
2419 case POWER_DOMAIN_PORT_DDI_D_4_LANES:
2420 return "PORT_DDI_D_4_LANES";
2421 case POWER_DOMAIN_PORT_DSI:
2422 return "PORT_DSI";
2423 case POWER_DOMAIN_PORT_CRT:
2424 return "PORT_CRT";
2425 case POWER_DOMAIN_PORT_OTHER:
2426 return "PORT_OTHER";
1da51581
ID		 2427 case POWER_DOMAIN_VGA:
2428 return "VGA";
2429 case POWER_DOMAIN_AUDIO:
2430 return "AUDIO";
bd2bb1b9
PZ		 2431 case POWER_DOMAIN_PLLS:
2432 return "PLLS";
1407121a
S		 2433 case POWER_DOMAIN_AUX_A:
2434 return "AUX_A";
2435 case POWER_DOMAIN_AUX_B:
2436 return "AUX_B";
2437 case POWER_DOMAIN_AUX_C:
2438 return "AUX_C";
2439 case POWER_DOMAIN_AUX_D:
2440 return "AUX_D";
1da51581
ID		 2441 case POWER_DOMAIN_INIT:
2442 return "INIT";
2443 default:
5f77eeb0 2444 MISSING_CASE(domain);
1da51581
ID		 2445 return "?";
2446 }
2447}
2448
2449static int i915_power_domain_info(struct seq_file *m, void *unused)
2450{
9f25d007 2451 struct drm_info_node *node = m->private;
1da51581
ID		 2452 struct drm_device *dev = node->minor->dev;
2453 struct drm_i915_private *dev_priv = dev->dev_private;
2454 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2455 int i;
2456
2457 mutex_lock(&power_domains->lock);
2458
2459 seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2460 for (i = 0; i < power_domains->power_well_count; i++) {
2461 struct i915_power_well *power_well;
2462 enum intel_display_power_domain power_domain;
2463
2464 power_well = &power_domains->power_wells[i];
2465 seq_printf(m, "%-25s %d\n", power_well->name,
2466 power_well->count);
2467
2468 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
2469 power_domain++) {
2470 if (!(BIT(power_domain) & power_well->domains))
2471 continue;
2472
2473 seq_printf(m, " %-23s %d\n",
2474 power_domain_str(power_domain),
2475 power_domains->domain_use_count[power_domain]);
2476 }
2477 }
2478
2479 mutex_unlock(&power_domains->lock);
2480
2481 return 0;
2482}
2483
53f5e3ca
JB		 2484static void intel_seq_print_mode(struct seq_file *m, int tabs,
2485 struct drm_display_mode *mode)
2486{
2487 int i;
2488
2489 for (i = 0; i < tabs; i++)
2490 seq_putc(m, '\t');
2491
2492 seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2493 mode->base.id, mode->name,
2494 mode->vrefresh, mode->clock,
2495 mode->hdisplay, mode->hsync_start,
2496 mode->hsync_end, mode->htotal,
2497 mode->vdisplay, mode->vsync_start,
2498 mode->vsync_end, mode->vtotal,
2499 mode->type, mode->flags);
2500}
2501
2502static void intel_encoder_info(struct seq_file *m,
2503 struct intel_crtc *intel_crtc,
2504 struct intel_encoder *intel_encoder)
2505{
9f25d007 2506 struct drm_info_node *node = m->private;
53f5e3ca
JB		 2507 struct drm_device *dev = node->minor->dev;
2508 struct drm_crtc *crtc = &intel_crtc->base;
2509 struct intel_connector *intel_connector;
2510 struct drm_encoder *encoder;
2511
2512 encoder = &intel_encoder->base;
2513 seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
8e329a03 2514 encoder->base.id, encoder->name);
53f5e3ca
JB		 2515 for_each_connector_on_encoder(dev, encoder, intel_connector) {
2516 struct drm_connector *connector = &intel_connector->base;
2517 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2518 connector->base.id,
c23cc417 2519 connector->name,
53f5e3ca
JB		 2520 drm_get_connector_status_name(connector->status));
2521 if (connector->status == connector_status_connected) {
2522 struct drm_display_mode *mode = &crtc->mode;
2523 seq_printf(m, ", mode:\n");
2524 intel_seq_print_mode(m, 2, mode);
2525 } else {
2526 seq_putc(m, '\n');
2527 }
2528 }
2529}
2530
2531static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2532{
9f25d007 2533 struct drm_info_node *node = m->private;
53f5e3ca
JB		 2534 struct drm_device *dev = node->minor->dev;
2535 struct drm_crtc *crtc = &intel_crtc->base;
2536 struct intel_encoder *intel_encoder;
2537
5aa8a937
MR		 2538 if (crtc->primary->fb)
2539 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2540 crtc->primary->fb->base.id, crtc->x, crtc->y,
2541 crtc->primary->fb->width, crtc->primary->fb->height);
2542 else
2543 seq_puts(m, "\tprimary plane disabled\n");
53f5e3ca
JB		 2544 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2545 intel_encoder_info(m, intel_crtc, intel_encoder);
2546}
2547
2548static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2549{
2550 struct drm_display_mode *mode = panel->fixed_mode;
2551
2552 seq_printf(m, "\tfixed mode:\n");
2553 intel_seq_print_mode(m, 2, mode);
2554}
2555
2556static void intel_dp_info(struct seq_file *m,
2557 struct intel_connector *intel_connector)
2558{
2559 struct intel_encoder *intel_encoder = intel_connector->encoder;
2560 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2561
2562 seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2563 seq_printf(m, "\taudio support: %s\n", intel_dp->has_audio ? "yes" :
2564 "no");
2565 if (intel_encoder->type == INTEL_OUTPUT_EDP)
2566 intel_panel_info(m, &intel_connector->panel);
2567}
2568
2569static void intel_hdmi_info(struct seq_file *m,
2570 struct intel_connector *intel_connector)
2571{
2572 struct intel_encoder *intel_encoder = intel_connector->encoder;
2573 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2574
2575 seq_printf(m, "\taudio support: %s\n", intel_hdmi->has_audio ? "yes" :
2576 "no");
2577}
2578
2579static void intel_lvds_info(struct seq_file *m,
2580 struct intel_connector *intel_connector)
2581{
2582 intel_panel_info(m, &intel_connector->panel);
2583}
2584
2585static void intel_connector_info(struct seq_file *m,
2586 struct drm_connector *connector)
2587{
2588 struct intel_connector *intel_connector = to_intel_connector(connector);
2589 struct intel_encoder *intel_encoder = intel_connector->encoder;
f103fc7d 2590 struct drm_display_mode *mode;
53f5e3ca
JB		 2591
2592 seq_printf(m, "connector %d: type %s, status: %s\n",
c23cc417 2593 connector->base.id, connector->name,
53f5e3ca
JB		 2594 drm_get_connector_status_name(connector->status));
2595 if (connector->status == connector_status_connected) {
2596 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2597 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2598 connector->display_info.width_mm,
2599 connector->display_info.height_mm);
2600 seq_printf(m, "\tsubpixel order: %s\n",
2601 drm_get_subpixel_order_name(connector->display_info.subpixel_order));
2602 seq_printf(m, "\tCEA rev: %d\n",
2603 connector->display_info.cea_rev);
2604 }
36cd7444
DA		 2605 if (intel_encoder) {
2606 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2607 intel_encoder->type == INTEL_OUTPUT_EDP)
2608 intel_dp_info(m, intel_connector);
2609 else if (intel_encoder->type == INTEL_OUTPUT_HDMI)
2610 intel_hdmi_info(m, intel_connector);
2611 else if (intel_encoder->type == INTEL_OUTPUT_LVDS)
2612 intel_lvds_info(m, intel_connector);
2613 }
53f5e3ca 2614
f103fc7d
JB		 2615 seq_printf(m, "\tmodes:\n");
2616 list_for_each_entry(mode, &connector->modes, head)
2617 intel_seq_print_mode(m, 2, mode);
53f5e3ca
JB		 2618}
2619
065f2ec2
CW		 2620static bool cursor_active(struct drm_device *dev, int pipe)
2621{
2622 struct drm_i915_private *dev_priv = dev->dev_private;
2623 u32 state;
2624
2625 if (IS_845G(dev) || IS_I865G(dev))
2626 state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
065f2ec2 2627 else
5efb3e28 2628 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
065f2ec2
CW		 2629
2630 return state;
2631}
2632
2633static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y)
2634{
2635 struct drm_i915_private *dev_priv = dev->dev_private;
2636 u32 pos;
2637
5efb3e28 2638 pos = I915_READ(CURPOS(pipe));
065f2ec2
CW		 2639
2640 *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
2641 if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
2642 *x = -*x;
2643
2644 *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
2645 if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
2646 *y = -*y;
2647
2648 return cursor_active(dev, pipe);
2649}
2650
53f5e3ca
JB		 2651static int i915_display_info(struct seq_file *m, void *unused)
2652{
9f25d007 2653 struct drm_info_node *node = m->private;
53f5e3ca 2654 struct drm_device *dev = node->minor->dev;
b0e5ddf3 2655 struct drm_i915_private *dev_priv = dev->dev_private;
065f2ec2 2656 struct intel_crtc *crtc;
53f5e3ca
JB		 2657 struct drm_connector *connector;
2658
b0e5ddf3 2659 intel_runtime_pm_get(dev_priv);
53f5e3ca
JB		 2660 drm_modeset_lock_all(dev);
2661 seq_printf(m, "CRTC info\n");
2662 seq_printf(m, "---------\n");
d3fcc808 2663 for_each_intel_crtc(dev, crtc) {
065f2ec2
CW		 2664 bool active;
2665 int x, y;
53f5e3ca 2666
57127efa 2667 seq_printf(m, "CRTC %d: pipe: %c, active=%s (size=%dx%d)\n",
065f2ec2 2668 crtc->base.base.id, pipe_name(crtc->pipe),
6e3c9717
ACO		 2669 yesno(crtc->active), crtc->config->pipe_src_w,
2670 crtc->config->pipe_src_h);
a23dc658 2671 if (crtc->active) {
065f2ec2
CW		 2672 intel_crtc_info(m, crtc);
2673
a23dc658 2674 active = cursor_position(dev, crtc->pipe, &x, &y);
57127efa 2675 seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
4b0e333e 2676 yesno(crtc->cursor_base),
57127efa
CW		 2677 x, y, crtc->cursor_width, crtc->cursor_height,
2678 crtc->cursor_addr, yesno(active));
a23dc658 2679 }
cace841c
DV		 2680
2681 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
2682 yesno(!crtc->cpu_fifo_underrun_disabled),
2683 yesno(!crtc->pch_fifo_underrun_disabled));
53f5e3ca
JB		 2684 }
2685
2686 seq_printf(m, "\n");
2687 seq_printf(m, "Connector info\n");
2688 seq_printf(m, "--------------\n");
2689 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2690 intel_connector_info(m, connector);
2691 }
2692 drm_modeset_unlock_all(dev);
b0e5ddf3 2693 intel_runtime_pm_put(dev_priv);
53f5e3ca
JB		 2694
2695 return 0;
2696}
2697
e04934cf
BW		 2698static int i915_semaphore_status(struct seq_file *m, void *unused)
2699{
2700 struct drm_info_node *node = (struct drm_info_node *) m->private;
2701 struct drm_device *dev = node->minor->dev;
2702 struct drm_i915_private *dev_priv = dev->dev_private;
2703 struct intel_engine_cs *ring;
2704 int num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
2705 int i, j, ret;
2706
2707 if (!i915_semaphore_is_enabled(dev)) {
2708 seq_puts(m, "Semaphores are disabled\n");
2709 return 0;
2710 }
2711
2712 ret = mutex_lock_interruptible(&dev->struct_mutex);
2713 if (ret)
2714 return ret;
03872064 2715 intel_runtime_pm_get(dev_priv);
e04934cf
BW		 2716
2717 if (IS_BROADWELL(dev)) {
2718 struct page *page;
2719 uint64_t *seqno;
2720
2721 page = i915_gem_object_get_page(dev_priv->semaphore_obj, 0);
2722
2723 seqno = (uint64_t *)kmap_atomic(page);
2724 for_each_ring(ring, dev_priv, i) {
2725 uint64_t offset;
2726
2727 seq_printf(m, "%s\n", ring->name);
2728
2729 seq_puts(m, " Last signal:");
2730 for (j = 0; j < num_rings; j++) {
2731 offset = i * I915_NUM_RINGS + j;
2732 seq_printf(m, "0x%08llx (0x%02llx) ",
2733 seqno[offset], offset * 8);
2734 }
2735 seq_putc(m, '\n');
2736
2737 seq_puts(m, " Last wait: ");
2738 for (j = 0; j < num_rings; j++) {
2739 offset = i + (j * I915_NUM_RINGS);
2740 seq_printf(m, "0x%08llx (0x%02llx) ",
2741 seqno[offset], offset * 8);
2742 }
2743 seq_putc(m, '\n');
2744
2745 }
2746 kunmap_atomic(seqno);
2747 } else {
2748 seq_puts(m, " Last signal:");
2749 for_each_ring(ring, dev_priv, i)
2750 for (j = 0; j < num_rings; j++)
2751 seq_printf(m, "0x%08x\n",
2752 I915_READ(ring->semaphore.mbox.signal[j]));
2753 seq_putc(m, '\n');
2754 }
2755
2756 seq_puts(m, "\nSync seqno:\n");
2757 for_each_ring(ring, dev_priv, i) {
2758 for (j = 0; j < num_rings; j++) {
2759 seq_printf(m, " 0x%08x ", ring->semaphore.sync_seqno[j]);
2760 }
2761 seq_putc(m, '\n');
2762 }
2763 seq_putc(m, '\n');
2764
03872064 2765 intel_runtime_pm_put(dev_priv);
e04934cf
BW		 2766 mutex_unlock(&dev->struct_mutex);
2767 return 0;
2768}
2769
728e29d7
DV		 2770static int i915_shared_dplls_info(struct seq_file *m, void *unused)
2771{
2772 struct drm_info_node *node = (struct drm_info_node *) m->private;
2773 struct drm_device *dev = node->minor->dev;
2774 struct drm_i915_private *dev_priv = dev->dev_private;
2775 int i;
2776
2777 drm_modeset_lock_all(dev);
2778 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
2779 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
2780
2781 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
1e6f2ddc 2782 seq_printf(m, " crtc_mask: 0x%08x, active: %d, on: %s\n",
3e369b76 2783 pll->config.crtc_mask, pll->active, yesno(pll->on));
728e29d7 2784 seq_printf(m, " tracked hardware state:\n");
3e369b76
ACO		 2785 seq_printf(m, " dpll: 0x%08x\n", pll->config.hw_state.dpll);
2786 seq_printf(m, " dpll_md: 0x%08x\n",
2787 pll->config.hw_state.dpll_md);
2788 seq_printf(m, " fp0: 0x%08x\n", pll->config.hw_state.fp0);
2789 seq_printf(m, " fp1: 0x%08x\n", pll->config.hw_state.fp1);
2790 seq_printf(m, " wrpll: 0x%08x\n", pll->config.hw_state.wrpll);
728e29d7
DV		 2791 }
2792 drm_modeset_unlock_all(dev);
2793
2794 return 0;
2795}
2796
1ed1ef9d 2797static int i915_wa_registers(struct seq_file *m, void *unused)
888b5995
AS		 2798{
2799 int i;
2800 int ret;
2801 struct drm_info_node *node = (struct drm_info_node *) m->private;
2802 struct drm_device *dev = node->minor->dev;
2803 struct drm_i915_private *dev_priv = dev->dev_private;
2804
888b5995
AS		 2805 ret = mutex_lock_interruptible(&dev->struct_mutex);
2806 if (ret)
2807 return ret;
2808
2809 intel_runtime_pm_get(dev_priv);
2810
7225342a
MK		 2811 seq_printf(m, "Workarounds applied: %d\n", dev_priv->workarounds.count);
2812 for (i = 0; i < dev_priv->workarounds.count; ++i) {
2fa60f6d
MK		 2813 u32 addr, mask, value, read;
2814 bool ok;
888b5995 2815
7225342a
MK		 2816 addr = dev_priv->workarounds.reg[i].addr;
2817 mask = dev_priv->workarounds.reg[i].mask;
2fa60f6d
MK		 2818 value = dev_priv->workarounds.reg[i].value;
2819 read = I915_READ(addr);
2820 ok = (value & mask) == (read & mask);
2821 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
2822 addr, value, mask, read, ok ? "OK" : "FAIL");
888b5995
AS		 2823 }
2824
2825 intel_runtime_pm_put(dev_priv);
2826 mutex_unlock(&dev->struct_mutex);
2827
2828 return 0;
2829}
2830
c5511e44
DL		 2831static int i915_ddb_info(struct seq_file *m, void *unused)
2832{
2833 struct drm_info_node *node = m->private;
2834 struct drm_device *dev = node->minor->dev;
2835 struct drm_i915_private *dev_priv = dev->dev_private;
2836 struct skl_ddb_allocation *ddb;
2837 struct skl_ddb_entry *entry;
2838 enum pipe pipe;
2839 int plane;
2840
2fcffe19
DL		 2841 if (INTEL_INFO(dev)->gen < 9)
2842 return 0;
2843
c5511e44
DL		 2844 drm_modeset_lock_all(dev);
2845
2846 ddb = &dev_priv->wm.skl_hw.ddb;
2847
2848 seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
2849
2850 for_each_pipe(dev_priv, pipe) {
2851 seq_printf(m, "Pipe %c\n", pipe_name(pipe));
2852
2853 for_each_plane(pipe, plane) {
2854 entry = &ddb->plane[pipe][plane];
2855 seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane + 1,
2856 entry->start, entry->end,
2857 skl_ddb_entry_size(entry));
2858 }
2859
2860 entry = &ddb->cursor[pipe];
2861 seq_printf(m, " %-13s%8u%8u%8u\n", "Cursor", entry->start,
2862 entry->end, skl_ddb_entry_size(entry));
2863 }
2864
2865 drm_modeset_unlock_all(dev);
2866
2867 return 0;
2868}
2869
07144428
DL		 2870struct pipe_crc_info {
2871 const char *name;
2872 struct drm_device *dev;
2873 enum pipe pipe;
2874};
2875
11bed958
DA		 2876static int i915_dp_mst_info(struct seq_file *m, void *unused)
2877{
2878 struct drm_info_node *node = (struct drm_info_node *) m->private;
2879 struct drm_device *dev = node->minor->dev;
2880 struct drm_encoder *encoder;
2881 struct intel_encoder *intel_encoder;
2882 struct intel_digital_port *intel_dig_port;
2883 drm_modeset_lock_all(dev);
2884 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2885 intel_encoder = to_intel_encoder(encoder);
2886 if (intel_encoder->type != INTEL_OUTPUT_DISPLAYPORT)
2887 continue;
2888 intel_dig_port = enc_to_dig_port(encoder);
2889 if (!intel_dig_port->dp.can_mst)
2890 continue;
2891
2892 drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr);
2893 }
2894 drm_modeset_unlock_all(dev);
2895 return 0;
2896}
2897
07144428
DL		 2898static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
2899{
be5c7a90
DL		 2900 struct pipe_crc_info *info = inode->i_private;
2901 struct drm_i915_private *dev_priv = info->dev->dev_private;
2902 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2903
7eb1c496
DV		 2904 if (info->pipe >= INTEL_INFO(info->dev)->num_pipes)
2905 return -ENODEV;
2906
d538bbdf
DL		 2907 spin_lock_irq(&pipe_crc->lock);
2908
2909 if (pipe_crc->opened) {
2910 spin_unlock_irq(&pipe_crc->lock);
be5c7a90
DL		 2911 return -EBUSY; /* already open */
2912 }
2913
d538bbdf 2914 pipe_crc->opened = true;
07144428
DL		 2915 filep->private_data = inode->i_private;
2916
d538bbdf
DL		 2917 spin_unlock_irq(&pipe_crc->lock);
2918
07144428
DL		 2919 return 0;
2920}
2921
2922static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
2923{
be5c7a90
DL		 2924 struct pipe_crc_info *info = inode->i_private;
2925 struct drm_i915_private *dev_priv = info->dev->dev_private;
2926 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2927
d538bbdf
DL		 2928 spin_lock_irq(&pipe_crc->lock);
2929 pipe_crc->opened = false;
2930 spin_unlock_irq(&pipe_crc->lock);
be5c7a90 2931
07144428
DL		 2932 return 0;
2933}
2934
2935/* (6 fields, 8 chars each, space separated (5) + '\n') */
2936#define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
2937/* account for \'0' */
2938#define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1)
2939
2940static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
8bf1e9f1 2941{
d538bbdf
DL		 2942 assert_spin_locked(&pipe_crc->lock);
2943 return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
2944 INTEL_PIPE_CRC_ENTRIES_NR);
07144428
DL		 2945}
2946
2947static ssize_t
2948i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
2949 loff_t *pos)
2950{
2951 struct pipe_crc_info *info = filep->private_data;
2952 struct drm_device *dev = info->dev;
2953 struct drm_i915_private *dev_priv = dev->dev_private;
2954 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2955 char buf[PIPE_CRC_BUFFER_LEN];
9ad6d99f 2956 int n_entries;
07144428
DL		 2957 ssize_t bytes_read;
2958
2959 /*
2960 * Don't allow user space to provide buffers not big enough to hold
2961 * a line of data.
2962 */
2963 if (count < PIPE_CRC_LINE_LEN)
2964 return -EINVAL;
2965
2966 if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
8bf1e9f1 2967 return 0;
07144428
DL		 2968
2969 /* nothing to read */
d538bbdf 2970 spin_lock_irq(&pipe_crc->lock);
07144428 2971 while (pipe_crc_data_count(pipe_crc) == 0) {
d538bbdf
DL		 2972 int ret;
2973
2974 if (filep->f_flags & O_NONBLOCK) {
2975 spin_unlock_irq(&pipe_crc->lock);
07144428 2976 return -EAGAIN;
d538bbdf 2977 }
07144428 2978
d538bbdf
DL		 2979 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
2980 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
2981 if (ret) {
2982 spin_unlock_irq(&pipe_crc->lock);
2983 return ret;
2984 }
8bf1e9f1
SH		 2985 }
2986
07144428 2987 /* We now have one or more entries to read */
9ad6d99f 2988 n_entries = count / PIPE_CRC_LINE_LEN;
d538bbdf 2989
07144428 2990 bytes_read = 0;
9ad6d99f
VS		 2991 while (n_entries > 0) {
2992 struct intel_pipe_crc_entry *entry =
2993 &pipe_crc->entries[pipe_crc->tail];
07144428 2994 int ret;
8bf1e9f1 2995
9ad6d99f
VS		 2996 if (CIRC_CNT(pipe_crc->head, pipe_crc->tail,
2997 INTEL_PIPE_CRC_ENTRIES_NR) < 1)
2998 break;
2999
3000 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
3001 pipe_crc->tail = (pipe_crc->tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
3002
07144428
DL		 3003 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
3004 "%8u %8x %8x %8x %8x %8x\n",
3005 entry->frame, entry->crc[0],
3006 entry->crc[1], entry->crc[2],
3007 entry->crc[3], entry->crc[4]);
3008
9ad6d99f
VS		 3009 spin_unlock_irq(&pipe_crc->lock);
3010
3011 ret = copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN);
07144428
DL		 3012 if (ret == PIPE_CRC_LINE_LEN)
3013 return -EFAULT;
b2c88f5b 3014
9ad6d99f
VS		 3015 user_buf += PIPE_CRC_LINE_LEN;
3016 n_entries--;
3017
3018 spin_lock_irq(&pipe_crc->lock);
3019 }
8bf1e9f1 3020
d538bbdf
DL		 3021 spin_unlock_irq(&pipe_crc->lock);
3022
07144428
DL		 3023 return bytes_read;
3024}
3025
3026static const struct file_operations i915_pipe_crc_fops = {
3027 .owner = THIS_MODULE,
3028 .open = i915_pipe_crc_open,
3029 .read = i915_pipe_crc_read,
3030 .release = i915_pipe_crc_release,
3031};
3032
3033static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
3034 {
3035 .name = "i915_pipe_A_crc",
3036 .pipe = PIPE_A,
3037 },
3038 {
3039 .name = "i915_pipe_B_crc",
3040 .pipe = PIPE_B,
3041 },
3042 {
3043 .name = "i915_pipe_C_crc",
3044 .pipe = PIPE_C,
3045 },
3046};
3047
3048static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
3049 enum pipe pipe)
3050{
3051 struct drm_device *dev = minor->dev;
3052 struct dentry *ent;
3053 struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
3054
3055 info->dev = dev;
3056 ent = debugfs_create_file(info->name, S_IRUGO, root, info,
3057 &i915_pipe_crc_fops);
f3c5fe97
WY		 3058 if (!ent)
3059 return -ENOMEM;
07144428
DL		 3060
3061 return drm_add_fake_info_node(minor, ent, info);
8bf1e9f1
SH		 3062}
3063
e8dfcf78 3064static const char * const pipe_crc_sources[] = {
926321d5
DV		 3065 "none",
3066 "plane1",
3067 "plane2",
3068 "pf",
5b3a856b 3069 "pipe",
3d099a05
DV		 3070 "TV",
3071 "DP-B",
3072 "DP-C",
3073 "DP-D",
46a19188 3074 "auto",
926321d5
DV		 3075};
3076
3077static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
3078{
3079 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
3080 return pipe_crc_sources[source];
3081}
3082
bd9db02f 3083static int display_crc_ctl_show(struct seq_file *m, void *data)
926321d5
DV		 3084{
3085 struct drm_device *dev = m->private;
3086 struct drm_i915_private *dev_priv = dev->dev_private;
3087 int i;
3088
3089 for (i = 0; i < I915_MAX_PIPES; i++)
3090 seq_printf(m, "%c %s\n", pipe_name(i),
3091 pipe_crc_source_name(dev_priv->pipe_crc[i].source));
3092
3093 return 0;
3094}
3095
bd9db02f 3096static int display_crc_ctl_open(struct inode *inode, struct file *file)
926321d5
DV		 3097{
3098 struct drm_device *dev = inode->i_private;
3099
bd9db02f 3100 return single_open(file, display_crc_ctl_show, dev);
926321d5
DV		 3101}
3102
46a19188 3103static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
52f843f6
DV		 3104 uint32_t *val)
3105{
46a19188
DV		 3106 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3107 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3108
3109 switch (*source) {
52f843f6
DV		 3110 case INTEL_PIPE_CRC_SOURCE_PIPE:
3111 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
3112 break;
3113 case INTEL_PIPE_CRC_SOURCE_NONE:
3114 *val = 0;
3115 break;
3116 default:
3117 return -EINVAL;
3118 }
3119
3120 return 0;
3121}
3122
46a19188
DV		 3123static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe,
3124 enum intel_pipe_crc_source *source)
3125{
3126 struct intel_encoder *encoder;
3127 struct intel_crtc *crtc;
26756809 3128 struct intel_digital_port *dig_port;
46a19188
DV		 3129 int ret = 0;
3130
3131 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3132
6e9f798d 3133 drm_modeset_lock_all(dev);
b2784e15 3134 for_each_intel_encoder(dev, encoder) {
46a19188
DV		 3135 if (!encoder->base.crtc)
3136 continue;
3137
3138 crtc = to_intel_crtc(encoder->base.crtc);
3139
3140 if (crtc->pipe != pipe)
3141 continue;
3142
3143 switch (encoder->type) {
3144 case INTEL_OUTPUT_TVOUT:
3145 *source = INTEL_PIPE_CRC_SOURCE_TV;
3146 break;
3147 case INTEL_OUTPUT_DISPLAYPORT:
3148 case INTEL_OUTPUT_EDP:
26756809
DV		 3149 dig_port = enc_to_dig_port(&encoder->base);
3150 switch (dig_port->port) {
3151 case PORT_B:
3152 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
3153 break;
3154 case PORT_C:
3155 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
3156 break;
3157 case PORT_D:
3158 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
3159 break;
3160 default:
3161 WARN(1, "nonexisting DP port %c\n",
3162 port_name(dig_port->port));
3163 break;
3164 }
46a19188 3165 break;
6847d71b
PZ		 3166 default:
3167 break;
46a19188
DV		 3168 }
3169 }
6e9f798d 3170 drm_modeset_unlock_all(dev);
46a19188
DV		 3171
3172 return ret;
3173}
3174
3175static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
3176 enum pipe pipe,
3177 enum intel_pipe_crc_source *source,
7ac0129b
DV		 3178 uint32_t *val)
3179{
8d2f24ca
DV		 3180 struct drm_i915_private *dev_priv = dev->dev_private;
3181 bool need_stable_symbols = false;
3182
46a19188
DV		 3183 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3184 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3185 if (ret)
3186 return ret;
3187 }
3188
3189 switch (*source) {
7ac0129b
DV		 3190 case INTEL_PIPE_CRC_SOURCE_PIPE:
3191 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
3192 break;
3193 case INTEL_PIPE_CRC_SOURCE_DP_B:
3194 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
8d2f24ca 3195 need_stable_symbols = true;
7ac0129b
DV		 3196 break;
3197 case INTEL_PIPE_CRC_SOURCE_DP_C:
3198 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
8d2f24ca 3199 need_stable_symbols = true;
7ac0129b 3200 break;
2be57922
VS		 3201 case INTEL_PIPE_CRC_SOURCE_DP_D:
3202 if (!IS_CHERRYVIEW(dev))
3203 return -EINVAL;
3204 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV;
3205 need_stable_symbols = true;
3206 break;
7ac0129b
DV		 3207 case INTEL_PIPE_CRC_SOURCE_NONE:
3208 *val = 0;
3209 break;
3210 default:
3211 return -EINVAL;
3212 }
3213
8d2f24ca
DV		 3214 /*
3215 * When the pipe CRC tap point is after the transcoders we need
3216 * to tweak symbol-level features to produce a deterministic series of
3217 * symbols for a given frame. We need to reset those features only once
3218 * a frame (instead of every nth symbol):
3219 * - DC-balance: used to ensure a better clock recovery from the data
3220 * link (SDVO)
3221 * - DisplayPort scrambling: used for EMI reduction
3222 */
3223 if (need_stable_symbols) {
3224 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3225
8d2f24ca 3226 tmp |= DC_BALANCE_RESET_VLV;
eb736679
VS		 3227 switch (pipe) {
3228 case PIPE_A:
8d2f24ca 3229 tmp |= PIPE_A_SCRAMBLE_RESET;
eb736679
VS		 3230 break;
3231 case PIPE_B:
8d2f24ca 3232 tmp |= PIPE_B_SCRAMBLE_RESET;
eb736679
VS		 3233 break;
3234 case PIPE_C:
3235 tmp |= PIPE_C_SCRAMBLE_RESET;
3236 break;
3237 default:
3238 return -EINVAL;
3239 }
8d2f24ca
DV		 3240 I915_WRITE(PORT_DFT2_G4X, tmp);
3241 }
3242
7ac0129b
DV		 3243 return 0;
3244}
3245
4b79ebf7 3246static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
46a19188
DV		 3247 enum pipe pipe,
3248 enum intel_pipe_crc_source *source,
4b79ebf7
DV		 3249 uint32_t *val)
3250{
84093603
DV		 3251 struct drm_i915_private *dev_priv = dev->dev_private;
3252 bool need_stable_symbols = false;
3253
46a19188
DV		 3254 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3255 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3256 if (ret)
3257 return ret;
3258 }
3259
3260 switch (*source) {
4b79ebf7
DV		 3261 case INTEL_PIPE_CRC_SOURCE_PIPE:
3262 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
3263 break;
3264 case INTEL_PIPE_CRC_SOURCE_TV:
3265 if (!SUPPORTS_TV(dev))
3266 return -EINVAL;
3267 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
3268 break;
3269 case INTEL_PIPE_CRC_SOURCE_DP_B:
3270 if (!IS_G4X(dev))
3271 return -EINVAL;
3272 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
84093603 3273 need_stable_symbols = true;
4b79ebf7
DV		 3274 break;
3275 case INTEL_PIPE_CRC_SOURCE_DP_C:
3276 if (!IS_G4X(dev))
3277 return -EINVAL;
3278 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
84093603 3279 need_stable_symbols = true;
4b79ebf7
DV		 3280 break;
3281 case INTEL_PIPE_CRC_SOURCE_DP_D:
3282 if (!IS_G4X(dev))
3283 return -EINVAL;
3284 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
84093603 3285 need_stable_symbols = true;
4b79ebf7
DV		 3286 break;
3287 case INTEL_PIPE_CRC_SOURCE_NONE:
3288 *val = 0;
3289 break;
3290 default:
3291 return -EINVAL;
3292 }
3293
84093603
DV		 3294 /*
3295 * When the pipe CRC tap point is after the transcoders we need
3296 * to tweak symbol-level features to produce a deterministic series of
3297 * symbols for a given frame. We need to reset those features only once
3298 * a frame (instead of every nth symbol):
3299 * - DC-balance: used to ensure a better clock recovery from the data
3300 * link (SDVO)
3301 * - DisplayPort scrambling: used for EMI reduction
3302 */
3303 if (need_stable_symbols) {
3304 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3305
3306 WARN_ON(!IS_G4X(dev));
3307
3308 I915_WRITE(PORT_DFT_I9XX,
3309 I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
3310
3311 if (pipe == PIPE_A)
3312 tmp |= PIPE_A_SCRAMBLE_RESET;
3313 else
3314 tmp |= PIPE_B_SCRAMBLE_RESET;
3315
3316 I915_WRITE(PORT_DFT2_G4X, tmp);
3317 }
3318
4b79ebf7
DV		 3319 return 0;
3320}
3321
8d2f24ca
DV		 3322static void vlv_undo_pipe_scramble_reset(struct drm_device *dev,
3323 enum pipe pipe)
3324{
3325 struct drm_i915_private *dev_priv = dev->dev_private;
3326 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3327
eb736679
VS		 3328 switch (pipe) {
3329 case PIPE_A:
8d2f24ca 3330 tmp &= ~PIPE_A_SCRAMBLE_RESET;
eb736679
VS		 3331 break;
3332 case PIPE_B:
8d2f24ca 3333 tmp &= ~PIPE_B_SCRAMBLE_RESET;
eb736679
VS		 3334 break;
3335 case PIPE_C:
3336 tmp &= ~PIPE_C_SCRAMBLE_RESET;
3337 break;
3338 default:
3339 return;
3340 }
8d2f24ca
DV		 3341 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
3342 tmp &= ~DC_BALANCE_RESET_VLV;
3343 I915_WRITE(PORT_DFT2_G4X, tmp);
3344
3345}
3346
84093603
DV		 3347static void g4x_undo_pipe_scramble_reset(struct drm_device *dev,
3348 enum pipe pipe)
3349{
3350 struct drm_i915_private *dev_priv = dev->dev_private;
3351 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3352
3353 if (pipe == PIPE_A)
3354 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3355 else
3356 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3357 I915_WRITE(PORT_DFT2_G4X, tmp);
3358
3359 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
3360 I915_WRITE(PORT_DFT_I9XX,
3361 I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
3362 }
3363}
3364
46a19188 3365static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
5b3a856b
DV		 3366 uint32_t *val)
3367{
46a19188
DV		 3368 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3369 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3370
3371 switch (*source) {
5b3a856b
DV		 3372 case INTEL_PIPE_CRC_SOURCE_PLANE1:
3373 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
3374 break;
3375 case INTEL_PIPE_CRC_SOURCE_PLANE2:
3376 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
3377 break;
5b3a856b
DV		 3378 case INTEL_PIPE_CRC_SOURCE_PIPE:
3379 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
3380 break;
3d099a05 3381 case INTEL_PIPE_CRC_SOURCE_NONE:
5b3a856b
DV		 3382 *val = 0;
3383 break;
3d099a05
DV		 3384 default:
3385 return -EINVAL;
5b3a856b
DV		 3386 }
3387
3388 return 0;
3389}
3390
fabf6e51
DV		 3391static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device *dev)
3392{
3393 struct drm_i915_private *dev_priv = dev->dev_private;
3394 struct intel_crtc *crtc =
3395 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
3396
3397 drm_modeset_lock_all(dev);
3398 /*
3399 * If we use the eDP transcoder we need to make sure that we don't
3400 * bypass the pfit, since otherwise the pipe CRC source won't work. Only
3401 * relevant on hsw with pipe A when using the always-on power well
3402 * routing.
3403 */
6e3c9717
ACO		 3404 if (crtc->config->cpu_transcoder == TRANSCODER_EDP &&
3405 !crtc->config->pch_pfit.enabled) {
3406 crtc->config->pch_pfit.force_thru = true;
fabf6e51
DV		 3407
3408 intel_display_power_get(dev_priv,
3409 POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A));
3410
3411 dev_priv->display.crtc_disable(&crtc->base);
3412 dev_priv->display.crtc_enable(&crtc->base);
3413 }
3414 drm_modeset_unlock_all(dev);
3415}
3416
3417static void hsw_undo_trans_edp_pipe_A_crc_wa(struct drm_device *dev)
3418{
3419 struct drm_i915_private *dev_priv = dev->dev_private;
3420 struct intel_crtc *crtc =
3421 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
3422
3423 drm_modeset_lock_all(dev);
3424 /*
3425 * If we use the eDP transcoder we need to make sure that we don't
3426 * bypass the pfit, since otherwise the pipe CRC source won't work. Only
3427 * relevant on hsw with pipe A when using the always-on power well
3428 * routing.
3429 */
6e3c9717
ACO		 3430 if (crtc->config->pch_pfit.force_thru) {
3431 crtc->config->pch_pfit.force_thru = false;
fabf6e51
DV		 3432
3433 dev_priv->display.crtc_disable(&crtc->base);
3434 dev_priv->display.crtc_enable(&crtc->base);
3435
3436 intel_display_power_put(dev_priv,
3437 POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A));
3438 }
3439 drm_modeset_unlock_all(dev);
3440}
3441
3442static int ivb_pipe_crc_ctl_reg(struct drm_device *dev,
3443 enum pipe pipe,
3444 enum intel_pipe_crc_source *source,
5b3a856b
DV		 3445 uint32_t *val)
3446{
46a19188
DV		 3447 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3448 *source = INTEL_PIPE_CRC_SOURCE_PF;
3449
3450 switch (*source) {
5b3a856b
DV		 3451 case INTEL_PIPE_CRC_SOURCE_PLANE1:
3452 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
3453 break;
3454 case INTEL_PIPE_CRC_SOURCE_PLANE2:
3455 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
3456 break;
3457 case INTEL_PIPE_CRC_SOURCE_PF:
fabf6e51
DV		 3458 if (IS_HASWELL(dev) && pipe == PIPE_A)
3459 hsw_trans_edp_pipe_A_crc_wa(dev);
3460
5b3a856b
DV		 3461 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
3462 break;
3d099a05 3463 case INTEL_PIPE_CRC_SOURCE_NONE:
5b3a856b
DV		 3464 *val = 0;
3465 break;
3d099a05
DV		 3466 default:
3467 return -EINVAL;
5b3a856b
DV		 3468 }
3469
3470 return 0;
3471}
3472
926321d5
DV		 3473static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
3474 enum intel_pipe_crc_source source)
3475{
3476 struct drm_i915_private *dev_priv = dev->dev_private;
cc3da175 3477 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
8c740dce
PZ		 3478 struct intel_crtc *crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev,
3479 pipe));
432f3342 3480 u32 val = 0; /* shut up gcc */
5b3a856b 3481 int ret;
926321d5 3482
cc3da175
DL		 3483 if (pipe_crc->source == source)
3484 return 0;
3485
ae676fcd
DL		 3486 /* forbid changing the source without going back to 'none' */
3487 if (pipe_crc->source && source)
3488 return -EINVAL;
3489
9d8b0588
DV		 3490 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PIPE(pipe))) {
3491 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
3492 return -EIO;
3493 }
3494
52f843f6 3495 if (IS_GEN2(dev))
46a19188 3496 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
52f843f6 3497 else if (INTEL_INFO(dev)->gen < 5)
46a19188 3498 ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
7ac0129b 3499 else if (IS_VALLEYVIEW(dev))
fabf6e51 3500 ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val);
4b79ebf7 3501 else if (IS_GEN5(dev) || IS_GEN6(dev))
46a19188 3502 ret = ilk_pipe_crc_ctl_reg(&source, &val);
5b3a856b 3503 else
fabf6e51 3504 ret = ivb_pipe_crc_ctl_reg(dev, pipe, &source, &val);
5b3a856b
DV		 3505
3506 if (ret != 0)
3507 return ret;
3508
4b584369
DL		 3509 /* none -> real source transition */
3510 if (source) {
4252fbc3
VS		 3511 struct intel_pipe_crc_entry *entries;
3512
7cd6ccff
DL		 3513 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
3514 pipe_name(pipe), pipe_crc_source_name(source));
3515
3cf54b34
VS		 3516 entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR,
3517 sizeof(pipe_crc->entries[0]),
4252fbc3
VS		 3518 GFP_KERNEL);
3519 if (!entries)
e5f75aca
DL		 3520 return -ENOMEM;
3521
8c740dce
PZ		 3522 /*
3523 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
3524 * enabled and disabled dynamically based on package C states,
3525 * user space can't make reliable use of the CRCs, so let's just
3526 * completely disable it.
3527 */
3528 hsw_disable_ips(crtc);
3529
d538bbdf 3530 spin_lock_irq(&pipe_crc->lock);
64387b61 3531 kfree(pipe_crc->entries);
4252fbc3 3532 pipe_crc->entries = entries;
d538bbdf
DL		 3533 pipe_crc->head = 0;
3534 pipe_crc->tail = 0;
3535 spin_unlock_irq(&pipe_crc->lock);
4b584369
DL		 3536 }
3537
cc3da175 3538 pipe_crc->source = source;
926321d5 3539
926321d5
DV		 3540 I915_WRITE(PIPE_CRC_CTL(pipe), val);
3541 POSTING_READ(PIPE_CRC_CTL(pipe));
3542
e5f75aca
DL		 3543 /* real source -> none transition */
3544 if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
d538bbdf 3545 struct intel_pipe_crc_entry *entries;
a33d7105
DV		 3546 struct intel_crtc *crtc =
3547 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
d538bbdf 3548
7cd6ccff
DL		 3549 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
3550 pipe_name(pipe));
3551
a33d7105
DV		 3552 drm_modeset_lock(&crtc->base.mutex, NULL);
3553 if (crtc->active)
3554 intel_wait_for_vblank(dev, pipe);
3555 drm_modeset_unlock(&crtc->base.mutex);
bcf17ab2 3556
d538bbdf
DL		 3557 spin_lock_irq(&pipe_crc->lock);
3558 entries = pipe_crc->entries;
e5f75aca 3559 pipe_crc->entries = NULL;
9ad6d99f
VS		 3560 pipe_crc->head = 0;
3561 pipe_crc->tail = 0;
d538bbdf
DL		 3562 spin_unlock_irq(&pipe_crc->lock);
3563
3564 kfree(entries);
84093603
DV		 3565
3566 if (IS_G4X(dev))
3567 g4x_undo_pipe_scramble_reset(dev, pipe);
8d2f24ca
DV		 3568 else if (IS_VALLEYVIEW(dev))
3569 vlv_undo_pipe_scramble_reset(dev, pipe);
fabf6e51
DV		 3570 else if (IS_HASWELL(dev) && pipe == PIPE_A)
3571 hsw_undo_trans_edp_pipe_A_crc_wa(dev);
8c740dce
PZ		 3572
3573 hsw_enable_ips(crtc);
e5f75aca
DL		 3574 }
3575
926321d5
DV		 3576 return 0;
3577}
3578
3579/*
3580 * Parse pipe CRC command strings:
b94dec87
DL		 3581 * command: wsp* object wsp+ name wsp+ source wsp*
3582 * object: 'pipe'
3583 * name: (A | B | C)
926321d5
DV		 3584 * source: (none | plane1 | plane2 | pf)
3585 * wsp: (#0x20 | #0x9 | #0xA)+
3586 *
3587 * eg.:
b94dec87
DL		 3588 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A
3589 * "pipe A none" -> Stop CRC
926321d5 3590 */
bd9db02f 3591static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
926321d5
DV		 3592{
3593 int n_words = 0;
3594
3595 while (*buf) {
3596 char *end;
3597
3598 /* skip leading white space */
3599 buf = skip_spaces(buf);
3600 if (!*buf)
3601 break; /* end of buffer */
3602
3603 /* find end of word */
3604 for (end = buf; *end && !isspace(*end); end++)
3605 ;
3606
3607 if (n_words == max_words) {
3608 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
3609 max_words);
3610 return -EINVAL; /* ran out of words[] before bytes */
3611 }
3612
3613 if (*end)
3614 *end++ = '\0';
3615 words[n_words++] = buf;
3616 buf = end;
3617 }
3618
3619 return n_words;
3620}
3621
b94dec87
DL		 3622enum intel_pipe_crc_object {
3623 PIPE_CRC_OBJECT_PIPE,
3624};
3625
e8dfcf78 3626static const char * const pipe_crc_objects[] = {
b94dec87
DL		 3627 "pipe",
3628};
3629
3630static int
bd9db02f 3631display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
b94dec87
DL		 3632{
3633 int i;
3634
3635 for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
3636 if (!strcmp(buf, pipe_crc_objects[i])) {
bd9db02f 3637 *o = i;
b94dec87
DL		 3638 return 0;
3639 }
3640
3641 return -EINVAL;
3642}
3643
bd9db02f 3644static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
926321d5
DV		 3645{
3646 const char name = buf[0];
3647
3648 if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
3649 return -EINVAL;
3650
3651 *pipe = name - 'A';
3652
3653 return 0;
3654}
3655
3656static int
bd9db02f 3657display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
926321d5
DV		 3658{
3659 int i;
3660
3661 for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
3662 if (!strcmp(buf, pipe_crc_sources[i])) {
bd9db02f 3663 *s = i;
926321d5
DV		 3664 return 0;
3665 }
3666
3667 return -EINVAL;
3668}
3669
bd9db02f 3670static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len)
926321d5 3671{
b94dec87 3672#define N_WORDS 3
926321d5 3673 int n_words;
b94dec87 3674 char *words[N_WORDS];
926321d5 3675 enum pipe pipe;
b94dec87 3676 enum intel_pipe_crc_object object;
926321d5
DV		 3677 enum intel_pipe_crc_source source;
3678
bd9db02f 3679 n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
b94dec87
DL		 3680 if (n_words != N_WORDS) {
3681 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
3682 N_WORDS);
3683 return -EINVAL;
3684 }
3685
bd9db02f 3686 if (display_crc_ctl_parse_object(words[0], &object) < 0) {
b94dec87 3687 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
926321d5
DV		 3688 return -EINVAL;
3689 }
3690
bd9db02f 3691 if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
b94dec87 3692 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
926321d5
DV		 3693 return -EINVAL;
3694 }
3695
bd9db02f 3696 if (display_crc_ctl_parse_source(words[2], &source) < 0) {
b94dec87 3697 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
926321d5
DV		 3698 return -EINVAL;
3699 }
3700
3701 return pipe_crc_set_source(dev, pipe, source);
3702}
3703
bd9db02f
DL		 3704static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
3705 size_t len, loff_t *offp)
926321d5
DV		 3706{
3707 struct seq_file *m = file->private_data;
3708 struct drm_device *dev = m->private;
3709 char *tmpbuf;
3710 int ret;
3711
3712 if (len == 0)
3713 return 0;
3714
3715 if (len > PAGE_SIZE - 1) {
3716 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
3717 PAGE_SIZE);
3718 return -E2BIG;
3719 }
3720
3721 tmpbuf = kmalloc(len + 1, GFP_KERNEL);
3722 if (!tmpbuf)
3723 return -ENOMEM;
3724
3725 if (copy_from_user(tmpbuf, ubuf, len)) {
3726 ret = -EFAULT;
3727 goto out;
3728 }
3729 tmpbuf[len] = '\0';
3730
bd9db02f 3731 ret = display_crc_ctl_parse(dev, tmpbuf, len);
926321d5
DV		 3732
3733out:
3734 kfree(tmpbuf);
3735 if (ret < 0)
3736 return ret;
3737
3738 *offp += len;
3739 return len;
3740}
3741
bd9db02f 3742static const struct file_operations i915_display_crc_ctl_fops = {
926321d5 3743 .owner = THIS_MODULE,
bd9db02f 3744 .open = display_crc_ctl_open,
926321d5
DV		 3745 .read = seq_read,
3746 .llseek = seq_lseek,
3747 .release = single_release,
bd9db02f 3748 .write = display_crc_ctl_write
926321d5
DV		 3749};
3750
97e94b22 3751static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
369a1342
VS		 3752{
3753 struct drm_device *dev = m->private;
546c81fd 3754 int num_levels = ilk_wm_max_level(dev) + 1;
369a1342
VS		 3755 int level;
3756
3757 drm_modeset_lock_all(dev);
3758
3759 for (level = 0; level < num_levels; level++) {
3760 unsigned int latency = wm[level];
3761
97e94b22
DL		 3762 /*
3763 * - WM1+ latency values in 0.5us units
3764 * - latencies are in us on gen9
3765 */
3766 if (INTEL_INFO(dev)->gen >= 9)
3767 latency *= 10;
3768 else if (level > 0)
369a1342
VS		 3769 latency *= 5;
3770
3771 seq_printf(m, "WM%d %u (%u.%u usec)\n",
97e94b22 3772 level, wm[level], latency / 10, latency % 10);
369a1342
VS		 3773 }
3774
3775 drm_modeset_unlock_all(dev);
3776}
3777
3778static int pri_wm_latency_show(struct seq_file *m, void *data)
3779{
3780 struct drm_device *dev = m->private;
97e94b22
DL		 3781 struct drm_i915_private *dev_priv = dev->dev_private;
3782 const uint16_t *latencies;
3783
3784 if (INTEL_INFO(dev)->gen >= 9)
3785 latencies = dev_priv->wm.skl_latency;
3786 else
3787 latencies = to_i915(dev)->wm.pri_latency;
369a1342 3788
97e94b22 3789 wm_latency_show(m, latencies);
369a1342
VS		 3790
3791 return 0;
3792}
3793
3794static int spr_wm_latency_show(struct seq_file *m, void *data)
3795{
3796 struct drm_device *dev = m->private;
97e94b22
DL		 3797 struct drm_i915_private *dev_priv = dev->dev_private;
3798 const uint16_t *latencies;
3799
3800 if (INTEL_INFO(dev)->gen >= 9)
3801 latencies = dev_priv->wm.skl_latency;
3802 else
3803 latencies = to_i915(dev)->wm.spr_latency;
369a1342 3804
97e94b22 3805 wm_latency_show(m, latencies);
369a1342
VS		 3806
3807 return 0;
3808}
3809
3810static int cur_wm_latency_show(struct seq_file *m, void *data)
3811{
3812 struct drm_device *dev = m->private;
97e94b22
DL		 3813 struct drm_i915_private *dev_priv = dev->dev_private;
3814 const uint16_t *latencies;
3815
3816 if (INTEL_INFO(dev)->gen >= 9)
3817 latencies = dev_priv->wm.skl_latency;
3818 else
3819 latencies = to_i915(dev)->wm.cur_latency;
369a1342 3820
97e94b22 3821 wm_latency_show(m, latencies);
369a1342
VS		 3822
3823 return 0;
3824}
3825
3826static int pri_wm_latency_open(struct inode *inode, struct file *file)
3827{
3828 struct drm_device *dev = inode->i_private;
3829
9ad0257c 3830 if (HAS_GMCH_DISPLAY(dev))
369a1342
VS		 3831 return -ENODEV;
3832
3833 return single_open(file, pri_wm_latency_show, dev);
3834}
3835
3836static int spr_wm_latency_open(struct inode *inode, struct file *file)
3837{
3838 struct drm_device *dev = inode->i_private;
3839
9ad0257c 3840 if (HAS_GMCH_DISPLAY(dev))
369a1342
VS		 3841 return -ENODEV;
3842
3843 return single_open(file, spr_wm_latency_show, dev);
3844}
3845
3846static int cur_wm_latency_open(struct inode *inode, struct file *file)
3847{
3848 struct drm_device *dev = inode->i_private;
3849
9ad0257c 3850 if (HAS_GMCH_DISPLAY(dev))
369a1342
VS		 3851 return -ENODEV;
3852
3853 return single_open(file, cur_wm_latency_show, dev);
3854}
3855
3856static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
97e94b22 3857 size_t len, loff_t *offp, uint16_t wm[8])
369a1342
VS		 3858{
3859 struct seq_file *m = file->private_data;
3860 struct drm_device *dev = m->private;
97e94b22 3861 uint16_t new[8] = { 0 };
546c81fd 3862 int num_levels = ilk_wm_max_level(dev) + 1;
369a1342
VS		 3863 int level;
3864 int ret;
3865 char tmp[32];
3866
3867 if (len >= sizeof(tmp))
3868 return -EINVAL;
3869
3870 if (copy_from_user(tmp, ubuf, len))
3871 return -EFAULT;
3872
3873 tmp[len] = '\0';
3874
97e94b22
DL		 3875 ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
3876 &new[0], &new[1], &new[2], &new[3],
3877 &new[4], &new[5], &new[6], &new[7]);
369a1342
VS		 3878 if (ret != num_levels)
3879 return -EINVAL;
3880
3881 drm_modeset_lock_all(dev);
3882
3883 for (level = 0; level < num_levels; level++)
3884 wm[level] = new[level];
3885
3886 drm_modeset_unlock_all(dev);
3887
3888 return len;
3889}
3890
3891
3892static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
3893 size_t len, loff_t *offp)
3894{
3895 struct seq_file *m = file->private_data;
3896 struct drm_device *dev = m->private;
97e94b22
DL		 3897 struct drm_i915_private *dev_priv = dev->dev_private;
3898 uint16_t *latencies;
369a1342 3899
97e94b22
DL		 3900 if (INTEL_INFO(dev)->gen >= 9)
3901 latencies = dev_priv->wm.skl_latency;
3902 else
3903 latencies = to_i915(dev)->wm.pri_latency;
3904
3905 return wm_latency_write(file, ubuf, len, offp, latencies);
369a1342
VS		 3906}
3907
3908static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
3909 size_t len, loff_t *offp)
3910{
3911 struct seq_file *m = file->private_data;
3912 struct drm_device *dev = m->private;
97e94b22
DL		 3913 struct drm_i915_private *dev_priv = dev->dev_private;
3914 uint16_t *latencies;
369a1342 3915
97e94b22
DL		 3916 if (INTEL_INFO(dev)->gen >= 9)
3917 latencies = dev_priv->wm.skl_latency;
3918 else
3919 latencies = to_i915(dev)->wm.spr_latency;
3920
3921 return wm_latency_write(file, ubuf, len, offp, latencies);
369a1342
VS		 3922}
3923
3924static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
3925 size_t len, loff_t *offp)
3926{
3927 struct seq_file *m = file->private_data;
3928 struct drm_device *dev = m->private;
97e94b22
DL		 3929 struct drm_i915_private *dev_priv = dev->dev_private;
3930 uint16_t *latencies;
3931
3932 if (INTEL_INFO(dev)->gen >= 9)
3933 latencies = dev_priv->wm.skl_latency;
3934 else
3935 latencies = to_i915(dev)->wm.cur_latency;
369a1342 3936
97e94b22 3937 return wm_latency_write(file, ubuf, len, offp, latencies);
369a1342
VS		 3938}
3939
3940static const struct file_operations i915_pri_wm_latency_fops = {
3941 .owner = THIS_MODULE,
3942 .open = pri_wm_latency_open,
3943 .read = seq_read,
3944 .llseek = seq_lseek,
3945 .release = single_release,
3946 .write = pri_wm_latency_write
3947};
3948
3949static const struct file_operations i915_spr_wm_latency_fops = {
3950 .owner = THIS_MODULE,
3951 .open = spr_wm_latency_open,
3952 .read = seq_read,
3953 .llseek = seq_lseek,
3954 .release = single_release,
3955 .write = spr_wm_latency_write
3956};
3957
3958static const struct file_operations i915_cur_wm_latency_fops = {
3959 .owner = THIS_MODULE,
3960 .open = cur_wm_latency_open,
3961 .read = seq_read,
3962 .llseek = seq_lseek,
3963 .release = single_release,
3964 .write = cur_wm_latency_write
3965};
3966
647416f9
KC		 3967static int
3968i915_wedged_get(void *data, u64 *val)
f3cd474b 3969{
647416f9 3970 struct drm_device *dev = data;
e277a1f8 3971 struct drm_i915_private *dev_priv = dev->dev_private;
f3cd474b 3972
647416f9 3973 *val = atomic_read(&dev_priv->gpu_error.reset_counter);
f3cd474b 3974
647416f9 3975 return 0;
f3cd474b
CW		 3976}
3977
647416f9
KC		 3978static int
3979i915_wedged_set(void *data, u64 val)
f3cd474b 3980{
647416f9 3981 struct drm_device *dev = data;
d46c0517
ID		 3982 struct drm_i915_private *dev_priv = dev->dev_private;
3983
b8d24a06
MK		 3984 /*
3985 * There is no safeguard against this debugfs entry colliding
3986 * with the hangcheck calling same i915_handle_error() in
3987 * parallel, causing an explosion. For now we assume that the
3988 * test harness is responsible enough not to inject gpu hangs
3989 * while it is writing to 'i915_wedged'
3990 */
3991
3992 if (i915_reset_in_progress(&dev_priv->gpu_error))
3993 return -EAGAIN;
3994
d46c0517 3995 intel_runtime_pm_get(dev_priv);
f3cd474b 3996
58174462
MK		 3997 i915_handle_error(dev, val,
3998 "Manually setting wedged to %llu", val);
d46c0517
ID		 3999
4000 intel_runtime_pm_put(dev_priv);
4001
647416f9 4002 return 0;
f3cd474b
CW		 4003}
4004
647416f9
KC		 4005DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
4006 i915_wedged_get, i915_wedged_set,
3a3b4f98 4007 "%llu\n");
f3cd474b 4008
647416f9
KC		 4009static int
4010i915_ring_stop_get(void *data, u64 *val)
e5eb3d63 4011{
647416f9 4012 struct drm_device *dev = data;
e277a1f8 4013 struct drm_i915_private *dev_priv = dev->dev_private;
e5eb3d63 4014
647416f9 4015 *val = dev_priv->gpu_error.stop_rings;
e5eb3d63 4016
647416f9 4017 return 0;
e5eb3d63
DV		 4018}
4019
647416f9
KC		 4020static int
4021i915_ring_stop_set(void *data, u64 val)
e5eb3d63 4022{
647416f9 4023 struct drm_device *dev = data;
e5eb3d63 4024 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 4025 int ret;
e5eb3d63 4026
647416f9 4027 DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val);
e5eb3d63 4028
22bcfc6a
DV		 4029 ret = mutex_lock_interruptible(&dev->struct_mutex);
4030 if (ret)
4031 return ret;
4032
99584db3 4033 dev_priv->gpu_error.stop_rings = val;
e5eb3d63
DV		 4034 mutex_unlock(&dev->struct_mutex);
4035
647416f9 4036 return 0;
e5eb3d63
DV		 4037}
4038
647416f9
KC		 4039DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops,
4040 i915_ring_stop_get, i915_ring_stop_set,
4041 "0x%08llx\n");
d5442303 4042
094f9a54
CW		 4043static int
4044i915_ring_missed_irq_get(void *data, u64 *val)
4045{
4046 struct drm_device *dev = data;
4047 struct drm_i915_private *dev_priv = dev->dev_private;
4048
4049 *val = dev_priv->gpu_error.missed_irq_rings;
4050 return 0;
4051}
4052
4053static int
4054i915_ring_missed_irq_set(void *data, u64 val)
4055{
4056 struct drm_device *dev = data;
4057 struct drm_i915_private *dev_priv = dev->dev_private;
4058 int ret;
4059
4060 /* Lock against concurrent debugfs callers */
4061 ret = mutex_lock_interruptible(&dev->struct_mutex);
4062 if (ret)
4063 return ret;
4064 dev_priv->gpu_error.missed_irq_rings = val;
4065 mutex_unlock(&dev->struct_mutex);
4066
4067 return 0;
4068}
4069
4070DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
4071 i915_ring_missed_irq_get, i915_ring_missed_irq_set,
4072 "0x%08llx\n");
4073
4074static int
4075i915_ring_test_irq_get(void *data, u64 *val)
4076{
4077 struct drm_device *dev = data;
4078 struct drm_i915_private *dev_priv = dev->dev_private;
4079
4080 *val = dev_priv->gpu_error.test_irq_rings;
4081
4082 return 0;
4083}
4084
4085static int
4086i915_ring_test_irq_set(void *data, u64 val)
4087{
4088 struct drm_device *dev = data;
4089 struct drm_i915_private *dev_priv = dev->dev_private;
4090 int ret;
4091
4092 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
4093
4094 /* Lock against concurrent debugfs callers */
4095 ret = mutex_lock_interruptible(&dev->struct_mutex);
4096 if (ret)
4097 return ret;
4098
4099 dev_priv->gpu_error.test_irq_rings = val;
4100 mutex_unlock(&dev->struct_mutex);
4101
4102 return 0;
4103}
4104
4105DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
4106 i915_ring_test_irq_get, i915_ring_test_irq_set,
4107 "0x%08llx\n");
4108
dd624afd
CW		 4109#define DROP_UNBOUND 0x1
4110#define DROP_BOUND 0x2
4111#define DROP_RETIRE 0x4
4112#define DROP_ACTIVE 0x8
4113#define DROP_ALL (DROP_UNBOUND | \
4114 DROP_BOUND | \
4115 DROP_RETIRE | \
4116 DROP_ACTIVE)
647416f9
KC		 4117static int
4118i915_drop_caches_get(void *data, u64 *val)
dd624afd 4119{
647416f9 4120 *val = DROP_ALL;
dd624afd 4121
647416f9 4122 return 0;
dd624afd
CW		 4123}
4124
647416f9
KC		 4125static int
4126i915_drop_caches_set(void *data, u64 val)
dd624afd 4127{
647416f9 4128 struct drm_device *dev = data;
dd624afd 4129 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 4130 int ret;
dd624afd 4131
2f9fe5ff 4132 DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
dd624afd
CW		 4133
4134 /* No need to check and wait for gpu resets, only libdrm auto-restarts
4135 * on ioctls on -EAGAIN. */
4136 ret = mutex_lock_interruptible(&dev->struct_mutex);
4137 if (ret)
4138 return ret;
4139
4140 if (val & DROP_ACTIVE) {
4141 ret = i915_gpu_idle(dev);
4142 if (ret)
4143 goto unlock;
4144 }
4145
4146 if (val & (DROP_RETIRE | DROP_ACTIVE))
4147 i915_gem_retire_requests(dev);
4148
21ab4e74
CW		 4149 if (val & DROP_BOUND)
4150 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND);
4ad72b7f 4151
21ab4e74
CW		 4152 if (val & DROP_UNBOUND)
4153 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND);
dd624afd
CW		 4154
4155unlock:
4156 mutex_unlock(&dev->struct_mutex);
4157
647416f9 4158 return ret;
dd624afd
CW		 4159}
4160
647416f9
KC		 4161DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
4162 i915_drop_caches_get, i915_drop_caches_set,
4163 "0x%08llx\n");
dd624afd 4164
647416f9
KC		 4165static int
4166i915_max_freq_get(void *data, u64 *val)
358733e9 4167{
647416f9 4168 struct drm_device *dev = data;
e277a1f8 4169 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 4170 int ret;
004777cb 4171
daa3afb2 4172 if (INTEL_INFO(dev)->gen < 6)
004777cb
DV		 4173 return -ENODEV;
4174
5c9669ce
TR		 4175 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4176
4fc688ce 4177 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 4178 if (ret)
4179 return ret;
358733e9 4180
7c59a9c1 4181 *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
4fc688ce 4182 mutex_unlock(&dev_priv->rps.hw_lock);
358733e9 4183
647416f9 4184 return 0;
358733e9
JB		 4185}
4186
647416f9
KC		 4187static int
4188i915_max_freq_set(void *data, u64 val)
358733e9 4189{
647416f9 4190 struct drm_device *dev = data;
358733e9 4191 struct drm_i915_private *dev_priv = dev->dev_private;
dd0a1aa1 4192 u32 rp_state_cap, hw_max, hw_min;
647416f9 4193 int ret;
004777cb 4194
daa3afb2 4195 if (INTEL_INFO(dev)->gen < 6)
004777cb 4196 return -ENODEV;
358733e9 4197
5c9669ce
TR		 4198 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4199
647416f9 4200 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
358733e9 4201
4fc688ce 4202 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 4203 if (ret)
4204 return ret;
4205
358733e9
JB		 4206 /*
4207 * Turbo will still be enabled, but won't go above the set value.
4208 */
0a073b84 4209 if (IS_VALLEYVIEW(dev)) {
7c59a9c1 4210 val = intel_freq_opcode(dev_priv, val);
dd0a1aa1 4211
03af2045
VS		 4212 hw_max = dev_priv->rps.max_freq;
4213 hw_min = dev_priv->rps.min_freq;
0a073b84 4214 } else {
7c59a9c1 4215 val = intel_freq_opcode(dev_priv, val);
dd0a1aa1
JM		 4216
4217 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
b39fb297 4218 hw_max = dev_priv->rps.max_freq;
dd0a1aa1
JM		 4219 hw_min = (rp_state_cap >> 16) & 0xff;
4220 }
4221
b39fb297 4222 if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
dd0a1aa1
JM		 4223 mutex_unlock(&dev_priv->rps.hw_lock);
4224 return -EINVAL;
0a073b84
JB		 4225 }
4226
b39fb297 4227 dev_priv->rps.max_freq_softlimit = val;
dd0a1aa1
JM		 4228
4229 if (IS_VALLEYVIEW(dev))
4230 valleyview_set_rps(dev, val);
4231 else
4232 gen6_set_rps(dev, val);
4233
4fc688ce 4234 mutex_unlock(&dev_priv->rps.hw_lock);
358733e9 4235
647416f9 4236 return 0;
358733e9
JB		 4237}
4238
647416f9
KC		 4239DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
4240 i915_max_freq_get, i915_max_freq_set,
3a3b4f98 4241 "%llu\n");
358733e9 4242
647416f9
KC		 4243static int
4244i915_min_freq_get(void *data, u64 *val)
1523c310 4245{
647416f9 4246 struct drm_device *dev = data;
e277a1f8 4247 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 4248 int ret;
004777cb 4249
daa3afb2 4250 if (INTEL_INFO(dev)->gen < 6)
004777cb
DV		 4251 return -ENODEV;
4252
5c9669ce
TR		 4253 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4254
4fc688ce 4255 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 4256 if (ret)
4257 return ret;
1523c310 4258
7c59a9c1 4259 *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
4fc688ce 4260 mutex_unlock(&dev_priv->rps.hw_lock);
1523c310 4261
647416f9 4262 return 0;
1523c310
JB		 4263}
4264
647416f9
KC		 4265static int
4266i915_min_freq_set(void *data, u64 val)
1523c310 4267{
647416f9 4268 struct drm_device *dev = data;
1523c310 4269 struct drm_i915_private *dev_priv = dev->dev_private;
dd0a1aa1 4270 u32 rp_state_cap, hw_max, hw_min;
647416f9 4271 int ret;
004777cb 4272
daa3afb2 4273 if (INTEL_INFO(dev)->gen < 6)
004777cb 4274 return -ENODEV;
1523c310 4275
5c9669ce
TR		 4276 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4277
647416f9 4278 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
1523c310 4279
4fc688ce 4280 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 4281 if (ret)
4282 return ret;
4283
1523c310
JB		 4284 /*
4285 * Turbo will still be enabled, but won't go below the set value.
4286 */
0a073b84 4287 if (IS_VALLEYVIEW(dev)) {
7c59a9c1 4288 val = intel_freq_opcode(dev_priv, val);
dd0a1aa1 4289
03af2045
VS		 4290 hw_max = dev_priv->rps.max_freq;
4291 hw_min = dev_priv->rps.min_freq;
0a073b84 4292 } else {
7c59a9c1 4293 val = intel_freq_opcode(dev_priv, val);
dd0a1aa1
JM		 4294
4295 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
b39fb297 4296 hw_max = dev_priv->rps.max_freq;
dd0a1aa1
JM		 4297 hw_min = (rp_state_cap >> 16) & 0xff;
4298 }
4299
b39fb297 4300 if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
dd0a1aa1
JM		 4301 mutex_unlock(&dev_priv->rps.hw_lock);
4302 return -EINVAL;
0a073b84 4303 }
dd0a1aa1 4304
b39fb297 4305 dev_priv->rps.min_freq_softlimit = val;
dd0a1aa1
JM		 4306
4307 if (IS_VALLEYVIEW(dev))
4308 valleyview_set_rps(dev, val);
4309 else
4310 gen6_set_rps(dev, val);
4311
4fc688ce 4312 mutex_unlock(&dev_priv->rps.hw_lock);
1523c310 4313
647416f9 4314 return 0;
1523c310
JB		 4315}
4316
647416f9
KC		 4317DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
4318 i915_min_freq_get, i915_min_freq_set,
3a3b4f98 4319 "%llu\n");
1523c310 4320
647416f9
KC		 4321static int
4322i915_cache_sharing_get(void *data, u64 *val)
07b7ddd9 4323{
647416f9 4324 struct drm_device *dev = data;
e277a1f8 4325 struct drm_i915_private *dev_priv = dev->dev_private;
07b7ddd9 4326 u32 snpcr;
647416f9 4327 int ret;
07b7ddd9 4328
004777cb
DV		 4329 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
4330 return -ENODEV;
4331
22bcfc6a
DV		 4332 ret = mutex_lock_interruptible(&dev->struct_mutex);
4333 if (ret)
4334 return ret;
c8c8fb33 4335 intel_runtime_pm_get(dev_priv);
22bcfc6a 4336
07b7ddd9 4337 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
c8c8fb33
PZ		 4338
4339 intel_runtime_pm_put(dev_priv);
07b7ddd9
JB		 4340 mutex_unlock(&dev_priv->dev->struct_mutex);
4341
647416f9 4342 *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
07b7ddd9 4343
647416f9 4344 return 0;
07b7ddd9
JB		 4345}
4346
647416f9
KC		 4347static int
4348i915_cache_sharing_set(void *data, u64 val)
07b7ddd9 4349{
647416f9 4350 struct drm_device *dev = data;
07b7ddd9 4351 struct drm_i915_private *dev_priv = dev->dev_private;
07b7ddd9 4352 u32 snpcr;
07b7ddd9 4353
004777cb
DV		 4354 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
4355 return -ENODEV;
4356
647416f9 4357 if (val > 3)
07b7ddd9
JB		 4358 return -EINVAL;
4359
c8c8fb33 4360 intel_runtime_pm_get(dev_priv);
647416f9 4361 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
07b7ddd9
JB		 4362
4363 /* Update the cache sharing policy here as well */
4364 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4365 snpcr &= ~GEN6_MBC_SNPCR_MASK;
4366 snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
4367 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
4368
c8c8fb33 4369 intel_runtime_pm_put(dev_priv);
647416f9 4370 return 0;
07b7ddd9
JB		 4371}
4372
647416f9
KC		 4373DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
4374 i915_cache_sharing_get, i915_cache_sharing_set,
4375 "%llu\n");
07b7ddd9 4376
6d794d42
BW		 4377static int i915_forcewake_open(struct inode *inode, struct file *file)
4378{
4379 struct drm_device *dev = inode->i_private;
4380 struct drm_i915_private *dev_priv = dev->dev_private;
6d794d42 4381
075edca4 4382 if (INTEL_INFO(dev)->gen < 6)
6d794d42
BW		 4383 return 0;
4384
6daccb0b 4385 intel_runtime_pm_get(dev_priv);
59bad947 4386 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6d794d42
BW		 4387
4388 return 0;
4389}
4390
c43b5634 4391static int i915_forcewake_release(struct inode *inode, struct file *file)
6d794d42
BW		 4392{
4393 struct drm_device *dev = inode->i_private;
4394 struct drm_i915_private *dev_priv = dev->dev_private;
4395
075edca4 4396 if (INTEL_INFO(dev)->gen < 6)
6d794d42
BW		 4397 return 0;
4398
59bad947 4399 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6daccb0b 4400 intel_runtime_pm_put(dev_priv);
6d794d42
BW		 4401
4402 return 0;
4403}
4404
4405static const struct file_operations i915_forcewake_fops = {
4406 .owner = THIS_MODULE,
4407 .open = i915_forcewake_open,
4408 .release = i915_forcewake_release,
4409};
4410
4411static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
4412{
4413 struct drm_device *dev = minor->dev;
4414 struct dentry *ent;
4415
4416 ent = debugfs_create_file("i915_forcewake_user",
8eb57294 4417 S_IRUSR,
6d794d42
BW		 4418 root, dev,
4419 &i915_forcewake_fops);
f3c5fe97
WY		 4420 if (!ent)
4421 return -ENOMEM;
6d794d42 4422
8eb57294 4423 return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
6d794d42
BW		 4424}
4425
6a9c308d
DV		 4426static int i915_debugfs_create(struct dentry *root,
4427 struct drm_minor *minor,
4428 const char *name,
4429 const struct file_operations *fops)
07b7ddd9
JB		 4430{
4431 struct drm_device *dev = minor->dev;
4432 struct dentry *ent;
4433
6a9c308d 4434 ent = debugfs_create_file(name,
07b7ddd9
JB		 4435 S_IRUGO | S_IWUSR,
4436 root, dev,
6a9c308d 4437 fops);
f3c5fe97
WY		 4438 if (!ent)
4439 return -ENOMEM;
07b7ddd9 4440
6a9c308d 4441 return drm_add_fake_info_node(minor, ent, fops);
07b7ddd9
JB		 4442}
4443
06c5bf8c 4444static const struct drm_info_list i915_debugfs_list[] = {
311bd68e 4445 {"i915_capabilities", i915_capabilities, 0},
73aa808f 4446 {"i915_gem_objects", i915_gem_object_info, 0},
08c18323 4447 {"i915_gem_gtt", i915_gem_gtt_info, 0},
1b50247a 4448 {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
433e12f7 4449 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
433e12f7 4450 {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
6d2b8885 4451 {"i915_gem_stolen", i915_gem_stolen_list_info },
4e5359cd 4452 {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
2017263e
BG		 4453 {"i915_gem_request", i915_gem_request_info, 0},
4454 {"i915_gem_seqno", i915_gem_seqno_info, 0},
a6172a80 4455 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
2017263e 4456 {"i915_gem_interrupt", i915_interrupt_info, 0},
1ec14ad3
CW		 4457 {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
4458 {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
4459 {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
9010ebfd 4460 {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
493018dc 4461 {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0},
adb4bd12 4462 {"i915_frequency_info", i915_frequency_info, 0},
f654449a 4463 {"i915_hangcheck_info", i915_hangcheck_info, 0},
f97108d1 4464 {"i915_drpc_info", i915_drpc_info, 0},
7648fa99 4465 {"i915_emon_status", i915_emon_status, 0},
23b2f8bb 4466 {"i915_ring_freq_table", i915_ring_freq_table, 0},
b5e50c3f 4467 {"i915_fbc_status", i915_fbc_status, 0},
92d44621 4468 {"i915_ips_status", i915_ips_status, 0},
4a9bef37 4469 {"i915_sr_status", i915_sr_status, 0},
44834a67 4470 {"i915_opregion", i915_opregion, 0},
37811fcc 4471 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
e76d3630 4472 {"i915_context_status", i915_context_status, 0},
c0ab1ae9 4473 {"i915_dump_lrc", i915_dump_lrc, 0},
4ba70e44 4474 {"i915_execlists", i915_execlists, 0},
f65367b5 4475 {"i915_forcewake_domains", i915_forcewake_domains, 0},
ea16a3cd 4476 {"i915_swizzle_info", i915_swizzle_info, 0},
3cf17fc5 4477 {"i915_ppgtt_info", i915_ppgtt_info, 0},
63573eb7 4478 {"i915_llc", i915_llc, 0},
e91fd8c6 4479 {"i915_edp_psr_status", i915_edp_psr_status, 0},
d2e216d0 4480 {"i915_sink_crc_eDP1", i915_sink_crc, 0},
ec013e7f 4481 {"i915_energy_uJ", i915_energy_uJ, 0},
371db66a 4482 {"i915_pc8_status", i915_pc8_status, 0},
1da51581 4483 {"i915_power_domain_info", i915_power_domain_info, 0},
53f5e3ca 4484 {"i915_display_info", i915_display_info, 0},
e04934cf 4485 {"i915_semaphore_status", i915_semaphore_status, 0},
728e29d7 4486 {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
11bed958 4487 {"i915_dp_mst_info", i915_dp_mst_info, 0},
1ed1ef9d 4488 {"i915_wa_registers", i915_wa_registers, 0},
c5511e44 4489 {"i915_ddb_info", i915_ddb_info, 0},
2017263e 4490};
27c202ad 4491#define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
2017263e 4492
06c5bf8c 4493static const struct i915_debugfs_files {
34b9674c
DV		 4494 const char *name;
4495 const struct file_operations *fops;
4496} i915_debugfs_files[] = {
4497 {"i915_wedged", &i915_wedged_fops},
4498 {"i915_max_freq", &i915_max_freq_fops},
4499 {"i915_min_freq", &i915_min_freq_fops},
4500 {"i915_cache_sharing", &i915_cache_sharing_fops},
4501 {"i915_ring_stop", &i915_ring_stop_fops},
094f9a54
CW		 4502 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
4503 {"i915_ring_test_irq", &i915_ring_test_irq_fops},
34b9674c
DV		 4504 {"i915_gem_drop_caches", &i915_drop_caches_fops},
4505 {"i915_error_state", &i915_error_state_fops},
4506 {"i915_next_seqno", &i915_next_seqno_fops},
bd9db02f 4507 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
369a1342
VS		 4508 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
4509 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
4510 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
da46f936 4511 {"i915_fbc_false_color", &i915_fbc_fc_fops},
34b9674c
DV		 4512};
4513
07144428
DL		 4514void intel_display_crc_init(struct drm_device *dev)
4515{
4516 struct drm_i915_private *dev_priv = dev->dev_private;
b378360e 4517 enum pipe pipe;
07144428 4518
055e393f 4519 for_each_pipe(dev_priv, pipe) {
b378360e 4520 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
07144428 4521
d538bbdf
DL		 4522 pipe_crc->opened = false;
4523 spin_lock_init(&pipe_crc->lock);
07144428
DL		 4524 init_waitqueue_head(&pipe_crc->wq);
4525 }
4526}
4527
27c202ad 4528int i915_debugfs_init(struct drm_minor *minor)
2017263e 4529{
34b9674c 4530 int ret, i;
f3cd474b 4531
6d794d42 4532 ret = i915_forcewake_create(minor->debugfs_root, minor);
358733e9
JB		 4533 if (ret)
4534 return ret;
6a9c308d 4535
07144428
DL		 4536 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
4537 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
4538 if (ret)
4539 return ret;
4540 }
4541
34b9674c
DV		 4542 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
4543 ret = i915_debugfs_create(minor->debugfs_root, minor,
4544 i915_debugfs_files[i].name,
4545 i915_debugfs_files[i].fops);
4546 if (ret)
4547 return ret;
4548 }
40633219 4549
27c202ad
BG		 4550 return drm_debugfs_create_files(i915_debugfs_list,
4551 I915_DEBUGFS_ENTRIES,
2017263e
BG		 4552 minor->debugfs_root, minor);
4553}
4554
27c202ad 4555void i915_debugfs_cleanup(struct drm_minor *minor)
2017263e 4556{
34b9674c
DV		 4557 int i;
4558
27c202ad
BG		 4559 drm_debugfs_remove_files(i915_debugfs_list,
4560 I915_DEBUGFS_ENTRIES, minor);
07144428 4561
6d794d42
BW		 4562 drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
4563 1, minor);
07144428 4564
e309a997 4565 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
07144428
DL		 4566 struct drm_info_list *info_list =
4567 (struct drm_info_list *)&i915_pipe_crc_data[i];
4568
4569 drm_debugfs_remove_files(info_list, 1, minor);
4570 }
4571
34b9674c
DV		 4572 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
4573 struct drm_info_list *info_list =
4574 (struct drm_info_list *) i915_debugfs_files[i].fops;
4575
4576 drm_debugfs_remove_files(info_list, 1, minor);
4577 }
2017263e 4578}
Linux kernel - Deliverables
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