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drm/i915: s/\<rq\>/req/g
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_debugfs.c
CommitLineData
2017263e
BG		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 *
27 */
28
29#include <linux/seq_file.h>
b2c88f5b 30#include <linux/circ_buf.h>
926321d5 31#include <linux/ctype.h>
f3cd474b 32#include <linux/debugfs.h>
5a0e3ad6 33#include <linux/slab.h>
2d1a8a48 34#include <linux/export.h>
6d2b8885 35#include <linux/list_sort.h>
ec013e7f 36#include <asm/msr-index.h>
760285e7 37#include <drm/drmP.h>
4e5359cd 38#include "intel_drv.h"
e5c65260 39#include "intel_ringbuffer.h"
760285e7 40#include <drm/i915_drm.h>
2017263e
BG		 41#include "i915_drv.h"
42
f13d3f73 43enum {
69dc4987 44 ACTIVE_LIST,
f13d3f73 45 INACTIVE_LIST,
d21d5975 46 PINNED_LIST,
f13d3f73 47};
2017263e 48
70d39fe4
CW		 49static const char *yesno(int v)
50{
51 return v ? "yes" : "no";
52}
53
497666d8
DL		 54/* As the drm_debugfs_init() routines are called before dev->dev_private is
55 * allocated we need to hook into the minor for release. */
56static int
57drm_add_fake_info_node(struct drm_minor *minor,
58 struct dentry *ent,
59 const void *key)
60{
61 struct drm_info_node *node;
62
63 node = kmalloc(sizeof(*node), GFP_KERNEL);
64 if (node == NULL) {
65 debugfs_remove(ent);
66 return -ENOMEM;
67 }
68
69 node->minor = minor;
70 node->dent = ent;
71 node->info_ent = (void *) key;
72
73 mutex_lock(&minor->debugfs_lock);
74 list_add(&node->list, &minor->debugfs_list);
75 mutex_unlock(&minor->debugfs_lock);
76
77 return 0;
78}
79
70d39fe4
CW		 80static int i915_capabilities(struct seq_file *m, void *data)
81{
9f25d007 82 struct drm_info_node *node = m->private;
70d39fe4
CW		 83 struct drm_device *dev = node->minor->dev;
84 const struct intel_device_info *info = INTEL_INFO(dev);
85
86 seq_printf(m, "gen: %d\n", info->gen);
03d00ac5 87 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
79fc46df
DL		 88#define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
89#define SEP_SEMICOLON ;
90 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
91#undef PRINT_FLAG
92#undef SEP_SEMICOLON
70d39fe4
CW		 93
94 return 0;
95}
2017263e 96
05394f39 97static const char *get_pin_flag(struct drm_i915_gem_object *obj)
a6172a80 98{
baaa5cfb 99 if (obj->pin_display)
a6172a80
CW		 100 return "p";
101 else
102 return " ";
103}
104
05394f39 105static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
a6172a80 106{
0206e353
AJ		 107 switch (obj->tiling_mode) {
108 default:
109 case I915_TILING_NONE: return " ";
110 case I915_TILING_X: return "X";
111 case I915_TILING_Y: return "Y";
112 }
a6172a80
CW		 113}
114
1d693bcc
BW		 115static inline const char *get_global_flag(struct drm_i915_gem_object *obj)
116{
aff43766 117 return i915_gem_obj_to_ggtt(obj) ? "g" : " ";
1d693bcc
BW		 118}
119
37811fcc
CW		 120static void
121describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
122{
1d693bcc 123 struct i915_vma *vma;
d7f46fc4
BW		 124 int pin_count = 0;
125
481a3d43 126 seq_printf(m, "%pK: %s%s%s%s %8zdKiB %02x %02x %x %x %x%s%s%s",
37811fcc 127 &obj->base,
481a3d43 128 obj->active ? "*" : " ",
37811fcc
CW		 129 get_pin_flag(obj),
130 get_tiling_flag(obj),
1d693bcc 131 get_global_flag(obj),
a05a5862 132 obj->base.size / 1024,
37811fcc
CW		 133 obj->base.read_domains,
134 obj->base.write_domain,
97b2a6a1
JH		 135 i915_gem_request_get_seqno(obj->last_read_req),
136 i915_gem_request_get_seqno(obj->last_write_req),
137 i915_gem_request_get_seqno(obj->last_fenced_req),
0a4cd7c8 138 i915_cache_level_str(to_i915(obj->base.dev), obj->cache_level),
37811fcc
CW		 139 obj->dirty ? " dirty" : "",
140 obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
141 if (obj->base.name)
142 seq_printf(m, " (name: %d)", obj->base.name);
ba0635ff 143 list_for_each_entry(vma, &obj->vma_list, vma_link) {
d7f46fc4
BW		 144 if (vma->pin_count > 0)
145 pin_count++;
ba0635ff
DC		 146 }
147 seq_printf(m, " (pinned x %d)", pin_count);
cc98b413
CW		 148 if (obj->pin_display)
149 seq_printf(m, " (display)");
37811fcc
CW		 150 if (obj->fence_reg != I915_FENCE_REG_NONE)
151 seq_printf(m, " (fence: %d)", obj->fence_reg);
1d693bcc
BW		 152 list_for_each_entry(vma, &obj->vma_list, vma_link) {
153 if (!i915_is_ggtt(vma->vm))
154 seq_puts(m, " (pp");
155 else
156 seq_puts(m, " (g");
440fd528 157 seq_printf(m, "gtt offset: %08llx, size: %08llx, type: %u)",
fe14d5f4
TU		 158 vma->node.start, vma->node.size,
159 vma->ggtt_view.type);
1d693bcc 160 }
c1ad11fc 161 if (obj->stolen)
440fd528 162 seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
30154650 163 if (obj->pin_display || obj->fault_mappable) {
6299f992 164 char s[3], *t = s;
30154650 165 if (obj->pin_display)
6299f992
CW		 166 *t++ = 'p';
167 if (obj->fault_mappable)
168 *t++ = 'f';
169 *t = '\0';
170 seq_printf(m, " (%s mappable)", s);
171 }
41c52415
JH		 172 if (obj->last_read_req != NULL)
173 seq_printf(m, " (%s)",
174 i915_gem_request_get_ring(obj->last_read_req)->name);
d5a81ef1
DV		 175 if (obj->frontbuffer_bits)
176 seq_printf(m, " (frontbuffer: 0x%03x)", obj->frontbuffer_bits);
37811fcc
CW		 177}
178
273497e5 179static void describe_ctx(struct seq_file *m, struct intel_context *ctx)
3ccfd19d 180{
ea0c76f8 181 seq_putc(m, ctx->legacy_hw_ctx.initialized ? 'I' : 'i');
3ccfd19d
BW		 182 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
183 seq_putc(m, ' ');
184}
185
433e12f7 186static int i915_gem_object_list_info(struct seq_file *m, void *data)
2017263e 187{
9f25d007 188 struct drm_info_node *node = m->private;
433e12f7
BG		 189 uintptr_t list = (uintptr_t) node->info_ent->data;
190 struct list_head *head;
2017263e 191 struct drm_device *dev = node->minor->dev;
5cef07e1
BW		 192 struct drm_i915_private *dev_priv = dev->dev_private;
193 struct i915_address_space *vm = &dev_priv->gtt.base;
ca191b13 194 struct i915_vma *vma;
8f2480fb
CW		 195 size_t total_obj_size, total_gtt_size;
196 int count, ret;
de227ef0
CW		 197
198 ret = mutex_lock_interruptible(&dev->struct_mutex);
199 if (ret)
200 return ret;
2017263e 201
ca191b13 202 /* FIXME: the user of this interface might want more than just GGTT */
433e12f7
BG		 203 switch (list) {
204 case ACTIVE_LIST:
267f0c90 205 seq_puts(m, "Active:\n");
5cef07e1 206 head = &vm->active_list;
433e12f7
BG		 207 break;
208 case INACTIVE_LIST:
267f0c90 209 seq_puts(m, "Inactive:\n");
5cef07e1 210 head = &vm->inactive_list;
433e12f7 211 break;
433e12f7 212 default:
de227ef0
CW		 213 mutex_unlock(&dev->struct_mutex);
214 return -EINVAL;
2017263e 215 }
2017263e 216
8f2480fb 217 total_obj_size = total_gtt_size = count = 0;
ca191b13
BW		 218 list_for_each_entry(vma, head, mm_list) {
219 seq_printf(m, " ");
220 describe_obj(m, vma->obj);
221 seq_printf(m, "\n");
222 total_obj_size += vma->obj->base.size;
223 total_gtt_size += vma->node.size;
8f2480fb 224 count++;
2017263e 225 }
de227ef0 226 mutex_unlock(&dev->struct_mutex);
5e118f41 227
8f2480fb
CW		 228 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
229 count, total_obj_size, total_gtt_size);
2017263e
BG		 230 return 0;
231}
232
6d2b8885
CW		 233static int obj_rank_by_stolen(void *priv,
234 struct list_head *A, struct list_head *B)
235{
236 struct drm_i915_gem_object *a =
b25cb2f8 237 container_of(A, struct drm_i915_gem_object, obj_exec_link);
6d2b8885 238 struct drm_i915_gem_object *b =
b25cb2f8 239 container_of(B, struct drm_i915_gem_object, obj_exec_link);
6d2b8885
CW		 240
241 return a->stolen->start - b->stolen->start;
242}
243
244static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
245{
9f25d007 246 struct drm_info_node *node = m->private;
6d2b8885
CW		 247 struct drm_device *dev = node->minor->dev;
248 struct drm_i915_private *dev_priv = dev->dev_private;
249 struct drm_i915_gem_object *obj;
250 size_t total_obj_size, total_gtt_size;
251 LIST_HEAD(stolen);
252 int count, ret;
253
254 ret = mutex_lock_interruptible(&dev->struct_mutex);
255 if (ret)
256 return ret;
257
258 total_obj_size = total_gtt_size = count = 0;
259 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
260 if (obj->stolen == NULL)
261 continue;
262
b25cb2f8 263 list_add(&obj->obj_exec_link, &stolen);
6d2b8885
CW		 264
265 total_obj_size += obj->base.size;
266 total_gtt_size += i915_gem_obj_ggtt_size(obj);
267 count++;
268 }
269 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
270 if (obj->stolen == NULL)
271 continue;
272
b25cb2f8 273 list_add(&obj->obj_exec_link, &stolen);
6d2b8885
CW		 274
275 total_obj_size += obj->base.size;
276 count++;
277 }
278 list_sort(NULL, &stolen, obj_rank_by_stolen);
279 seq_puts(m, "Stolen:\n");
280 while (!list_empty(&stolen)) {
b25cb2f8 281 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
6d2b8885
CW		 282 seq_puts(m, " ");
283 describe_obj(m, obj);
284 seq_putc(m, '\n');
b25cb2f8 285 list_del_init(&obj->obj_exec_link);
6d2b8885
CW		 286 }
287 mutex_unlock(&dev->struct_mutex);
288
289 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
290 count, total_obj_size, total_gtt_size);
291 return 0;
292}
293
6299f992
CW		 294#define count_objects(list, member) do { \
295 list_for_each_entry(obj, list, member) { \
f343c5f6 296 size += i915_gem_obj_ggtt_size(obj); \
6299f992
CW		 297 ++count; \
298 if (obj->map_and_fenceable) { \
f343c5f6 299 mappable_size += i915_gem_obj_ggtt_size(obj); \
6299f992
CW		 300 ++mappable_count; \
301 } \
302 } \
0206e353 303} while (0)
6299f992 304
2db8e9d6 305struct file_stats {
6313c204 306 struct drm_i915_file_private *file_priv;
2db8e9d6 307 int count;
c67a17e9
CW		 308 size_t total, unbound;
309 size_t global, shared;
310 size_t active, inactive;
2db8e9d6
CW		 311};
312
313static int per_file_stats(int id, void *ptr, void *data)
314{
315 struct drm_i915_gem_object *obj = ptr;
316 struct file_stats *stats = data;
6313c204 317 struct i915_vma *vma;
2db8e9d6
CW		 318
319 stats->count++;
320 stats->total += obj->base.size;
321
c67a17e9
CW		 322 if (obj->base.name || obj->base.dma_buf)
323 stats->shared += obj->base.size;
324
6313c204
CW		 325 if (USES_FULL_PPGTT(obj->base.dev)) {
326 list_for_each_entry(vma, &obj->vma_list, vma_link) {
327 struct i915_hw_ppgtt *ppgtt;
328
329 if (!drm_mm_node_allocated(&vma->node))
330 continue;
331
332 if (i915_is_ggtt(vma->vm)) {
333 stats->global += obj->base.size;
334 continue;
335 }
336
337 ppgtt = container_of(vma->vm, struct i915_hw_ppgtt, base);
4d884705 338 if (ppgtt->file_priv != stats->file_priv)
6313c204
CW		 339 continue;
340
41c52415 341 if (obj->active) /* XXX per-vma statistic */
6313c204
CW		 342 stats->active += obj->base.size;
343 else
344 stats->inactive += obj->base.size;
345
346 return 0;
347 }
2db8e9d6 348 } else {
6313c204
CW		 349 if (i915_gem_obj_ggtt_bound(obj)) {
350 stats->global += obj->base.size;
41c52415 351 if (obj->active)
6313c204
CW		 352 stats->active += obj->base.size;
353 else
354 stats->inactive += obj->base.size;
355 return 0;
356 }
2db8e9d6
CW		 357 }
358
6313c204
CW		 359 if (!list_empty(&obj->global_list))
360 stats->unbound += obj->base.size;
361
2db8e9d6
CW		 362 return 0;
363}
364
b0da1b79
CW		 365#define print_file_stats(m, name, stats) do { \
366 if (stats.count) \
367 seq_printf(m, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu global, %zu shared, %zu unbound)\n", \
368 name, \
369 stats.count, \
370 stats.total, \
371 stats.active, \
372 stats.inactive, \
373 stats.global, \
374 stats.shared, \
375 stats.unbound); \
376} while (0)
493018dc
BV		 377
378static void print_batch_pool_stats(struct seq_file *m,
379 struct drm_i915_private *dev_priv)
380{
381 struct drm_i915_gem_object *obj;
382 struct file_stats stats;
06fbca71 383 struct intel_engine_cs *ring;
8d9d5744 384 int i, j;
493018dc
BV		 385
386 memset(&stats, 0, sizeof(stats));
387
06fbca71 388 for_each_ring(ring, dev_priv, i) {
8d9d5744
CW		 389 for (j = 0; j < ARRAY_SIZE(ring->batch_pool.cache_list); j++) {
390 list_for_each_entry(obj,
391 &ring->batch_pool.cache_list[j],
392 batch_pool_link)
393 per_file_stats(0, obj, &stats);
394 }
06fbca71 395 }
493018dc 396
b0da1b79 397 print_file_stats(m, "[k]batch pool", stats);
493018dc
BV		 398}
399
ca191b13
BW		 400#define count_vmas(list, member) do { \
401 list_for_each_entry(vma, list, member) { \
402 size += i915_gem_obj_ggtt_size(vma->obj); \
403 ++count; \
404 if (vma->obj->map_and_fenceable) { \
405 mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
406 ++mappable_count; \
407 } \
408 } \
409} while (0)
410
411static int i915_gem_object_info(struct seq_file *m, void* data)
73aa808f 412{
9f25d007 413 struct drm_info_node *node = m->private;
73aa808f
CW		 414 struct drm_device *dev = node->minor->dev;
415 struct drm_i915_private *dev_priv = dev->dev_private;
b7abb714
CW		 416 u32 count, mappable_count, purgeable_count;
417 size_t size, mappable_size, purgeable_size;
6299f992 418 struct drm_i915_gem_object *obj;
5cef07e1 419 struct i915_address_space *vm = &dev_priv->gtt.base;
2db8e9d6 420 struct drm_file *file;
ca191b13 421 struct i915_vma *vma;
73aa808f
CW		 422 int ret;
423
424 ret = mutex_lock_interruptible(&dev->struct_mutex);
425 if (ret)
426 return ret;
427
6299f992
CW		 428 seq_printf(m, "%u objects, %zu bytes\n",
429 dev_priv->mm.object_count,
430 dev_priv->mm.object_memory);
431
432 size = count = mappable_size = mappable_count = 0;
35c20a60 433 count_objects(&dev_priv->mm.bound_list, global_list);
6299f992
CW		 434 seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n",
435 count, mappable_count, size, mappable_size);
436
437 size = count = mappable_size = mappable_count = 0;
ca191b13 438 count_vmas(&vm->active_list, mm_list);
6299f992
CW		 439 seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n",
440 count, mappable_count, size, mappable_size);
441
6299f992 442 size = count = mappable_size = mappable_count = 0;
ca191b13 443 count_vmas(&vm->inactive_list, mm_list);
6299f992
CW		 444 seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n",
445 count, mappable_count, size, mappable_size);
446
b7abb714 447 size = count = purgeable_size = purgeable_count = 0;
35c20a60 448 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
6c085a72 449 size += obj->base.size, ++count;
b7abb714
CW		 450 if (obj->madv == I915_MADV_DONTNEED)
451 purgeable_size += obj->base.size, ++purgeable_count;
452 }
6c085a72
CW		 453 seq_printf(m, "%u unbound objects, %zu bytes\n", count, size);
454
6299f992 455 size = count = mappable_size = mappable_count = 0;
35c20a60 456 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
6299f992 457 if (obj->fault_mappable) {
f343c5f6 458 size += i915_gem_obj_ggtt_size(obj);
6299f992
CW		 459 ++count;
460 }
30154650 461 if (obj->pin_display) {
f343c5f6 462 mappable_size += i915_gem_obj_ggtt_size(obj);
6299f992
CW		 463 ++mappable_count;
464 }
b7abb714
CW		 465 if (obj->madv == I915_MADV_DONTNEED) {
466 purgeable_size += obj->base.size;
467 ++purgeable_count;
468 }
6299f992 469 }
b7abb714
CW		 470 seq_printf(m, "%u purgeable objects, %zu bytes\n",
471 purgeable_count, purgeable_size);
6299f992
CW		 472 seq_printf(m, "%u pinned mappable objects, %zu bytes\n",
473 mappable_count, mappable_size);
474 seq_printf(m, "%u fault mappable objects, %zu bytes\n",
475 count, size);
476
93d18799 477 seq_printf(m, "%zu [%lu] gtt total\n",
853ba5d2
BW		 478 dev_priv->gtt.base.total,
479 dev_priv->gtt.mappable_end - dev_priv->gtt.base.start);
73aa808f 480
493018dc
BV		 481 seq_putc(m, '\n');
482 print_batch_pool_stats(m, dev_priv);
2db8e9d6
CW		 483 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
484 struct file_stats stats;
3ec2f427 485 struct task_struct *task;
2db8e9d6
CW		 486
487 memset(&stats, 0, sizeof(stats));
6313c204 488 stats.file_priv = file->driver_priv;
5b5ffff0 489 spin_lock(&file->table_lock);
2db8e9d6 490 idr_for_each(&file->object_idr, per_file_stats, &stats);
5b5ffff0 491 spin_unlock(&file->table_lock);
3ec2f427
TH		 492 /*
493 * Although we have a valid reference on file->pid, that does
494 * not guarantee that the task_struct who called get_pid() is
495 * still alive (e.g. get_pid(current) => fork() => exit()).
496 * Therefore, we need to protect this ->comm access using RCU.
497 */
498 rcu_read_lock();
499 task = pid_task(file->pid, PIDTYPE_PID);
493018dc 500 print_file_stats(m, task ? task->comm : "<unknown>", stats);
3ec2f427 501 rcu_read_unlock();
2db8e9d6
CW		 502 }
503
73aa808f
CW		 504 mutex_unlock(&dev->struct_mutex);
505
506 return 0;
507}
508
aee56cff 509static int i915_gem_gtt_info(struct seq_file *m, void *data)
08c18323 510{
9f25d007 511 struct drm_info_node *node = m->private;
08c18323 512 struct drm_device *dev = node->minor->dev;
1b50247a 513 uintptr_t list = (uintptr_t) node->info_ent->data;
08c18323
CW		 514 struct drm_i915_private *dev_priv = dev->dev_private;
515 struct drm_i915_gem_object *obj;
516 size_t total_obj_size, total_gtt_size;
517 int count, ret;
518
519 ret = mutex_lock_interruptible(&dev->struct_mutex);
520 if (ret)
521 return ret;
522
523 total_obj_size = total_gtt_size = count = 0;
35c20a60 524 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
d7f46fc4 525 if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj))
1b50247a
CW		 526 continue;
527
267f0c90 528 seq_puts(m, " ");
08c18323 529 describe_obj(m, obj);
267f0c90 530 seq_putc(m, '\n');
08c18323 531 total_obj_size += obj->base.size;
f343c5f6 532 total_gtt_size += i915_gem_obj_ggtt_size(obj);
08c18323
CW		 533 count++;
534 }
535
536 mutex_unlock(&dev->struct_mutex);
537
538 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
539 count, total_obj_size, total_gtt_size);
540
541 return 0;
542}
543
4e5359cd
SF		 544static int i915_gem_pageflip_info(struct seq_file *m, void *data)
545{
9f25d007 546 struct drm_info_node *node = m->private;
4e5359cd 547 struct drm_device *dev = node->minor->dev;
d6bbafa1 548 struct drm_i915_private *dev_priv = dev->dev_private;
4e5359cd 549 struct intel_crtc *crtc;
8a270ebf
DV		 550 int ret;
551
552 ret = mutex_lock_interruptible(&dev->struct_mutex);
553 if (ret)
554 return ret;
4e5359cd 555
d3fcc808 556 for_each_intel_crtc(dev, crtc) {
9db4a9c7
JB		 557 const char pipe = pipe_name(crtc->pipe);
558 const char plane = plane_name(crtc->plane);
4e5359cd
SF		 559 struct intel_unpin_work *work;
560
5e2d7afc 561 spin_lock_irq(&dev->event_lock);
4e5359cd
SF		 562 work = crtc->unpin_work;
563 if (work == NULL) {
9db4a9c7 564 seq_printf(m, "No flip due on pipe %c (plane %c)\n",
4e5359cd
SF		 565 pipe, plane);
566 } else {
d6bbafa1
CW		 567 u32 addr;
568
e7d841ca 569 if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9db4a9c7 570 seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
4e5359cd
SF		 571 pipe, plane);
572 } else {
9db4a9c7 573 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
4e5359cd
SF		 574 pipe, plane);
575 }
3a8a946e
DV		 576 if (work->flip_queued_req) {
577 struct intel_engine_cs *ring =
578 i915_gem_request_get_ring(work->flip_queued_req);
579
20e28fba 580 seq_printf(m, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n",
3a8a946e 581 ring->name,
f06cc1b9 582 i915_gem_request_get_seqno(work->flip_queued_req),
d6bbafa1 583 dev_priv->next_seqno,
3a8a946e 584 ring->get_seqno(ring, true),
1b5a433a 585 i915_gem_request_completed(work->flip_queued_req, true));
d6bbafa1
CW		 586 } else
587 seq_printf(m, "Flip not associated with any ring\n");
588 seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
589 work->flip_queued_vblank,
590 work->flip_ready_vblank,
1e3feefd 591 drm_crtc_vblank_count(&crtc->base));
4e5359cd 592 if (work->enable_stall_check)
267f0c90 593 seq_puts(m, "Stall check enabled, ");
4e5359cd 594 else
267f0c90 595 seq_puts(m, "Stall check waiting for page flip ioctl, ");
e7d841ca 596 seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
4e5359cd 597
d6bbafa1
CW		 598 if (INTEL_INFO(dev)->gen >= 4)
599 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane)));
600 else
601 addr = I915_READ(DSPADDR(crtc->plane));
602 seq_printf(m, "Current scanout address 0x%08x\n", addr);
603
4e5359cd 604 if (work->pending_flip_obj) {
d6bbafa1
CW		 605 seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset);
606 seq_printf(m, "MMIO update completed? %d\n", addr == work->gtt_offset);
4e5359cd
SF		 607 }
608 }
5e2d7afc 609 spin_unlock_irq(&dev->event_lock);
4e5359cd
SF		 610 }
611
8a270ebf
DV		 612 mutex_unlock(&dev->struct_mutex);
613
4e5359cd
SF		 614 return 0;
615}
616
493018dc
BV		 617static int i915_gem_batch_pool_info(struct seq_file *m, void *data)
618{
619 struct drm_info_node *node = m->private;
620 struct drm_device *dev = node->minor->dev;
621 struct drm_i915_private *dev_priv = dev->dev_private;
622 struct drm_i915_gem_object *obj;
06fbca71 623 struct intel_engine_cs *ring;
8d9d5744
CW		 624 int total = 0;
625 int ret, i, j;
493018dc
BV		 626
627 ret = mutex_lock_interruptible(&dev->struct_mutex);
628 if (ret)
629 return ret;
630
06fbca71 631 for_each_ring(ring, dev_priv, i) {
8d9d5744
CW		 632 for (j = 0; j < ARRAY_SIZE(ring->batch_pool.cache_list); j++) {
633 int count;
634
635 count = 0;
636 list_for_each_entry(obj,
637 &ring->batch_pool.cache_list[j],
638 batch_pool_link)
639 count++;
640 seq_printf(m, "%s cache[%d]: %d objects\n",
641 ring->name, j, count);
642
643 list_for_each_entry(obj,
644 &ring->batch_pool.cache_list[j],
645 batch_pool_link) {
646 seq_puts(m, " ");
647 describe_obj(m, obj);
648 seq_putc(m, '\n');
649 }
650
651 total += count;
06fbca71 652 }
493018dc
BV		 653 }
654
8d9d5744 655 seq_printf(m, "total: %d\n", total);
493018dc
BV		 656
657 mutex_unlock(&dev->struct_mutex);
658
659 return 0;
660}
661
2017263e
BG		 662static int i915_gem_request_info(struct seq_file *m, void *data)
663{
9f25d007 664 struct drm_info_node *node = m->private;
2017263e 665 struct drm_device *dev = node->minor->dev;
e277a1f8 666 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 667 struct intel_engine_cs *ring;
eed29a5b 668 struct drm_i915_gem_request *req;
2d1070b2 669 int ret, any, i;
de227ef0
CW		 670
671 ret = mutex_lock_interruptible(&dev->struct_mutex);
672 if (ret)
673 return ret;
2017263e 674
2d1070b2 675 any = 0;
a2c7f6fd 676 for_each_ring(ring, dev_priv, i) {
2d1070b2
CW		 677 int count;
678
679 count = 0;
eed29a5b 680 list_for_each_entry(req, &ring->request_list, list)
2d1070b2
CW		 681 count++;
682 if (count == 0)
a2c7f6fd
CW		 683 continue;
684
2d1070b2 685 seq_printf(m, "%s requests: %d\n", ring->name, count);
eed29a5b 686 list_for_each_entry(req, &ring->request_list, list) {
2d1070b2
CW		 687 struct task_struct *task;
688
689 rcu_read_lock();
690 task = NULL;
eed29a5b
DV		 691 if (req->pid)
692 task = pid_task(req->pid, PIDTYPE_PID);
2d1070b2 693 seq_printf(m, " %x @ %d: %s [%d]\n",
eed29a5b
DV		 694 req->seqno,
695 (int) (jiffies - req->emitted_jiffies),
2d1070b2
CW		 696 task ? task->comm : "<unknown>",
697 task ? task->pid : -1);
698 rcu_read_unlock();
c2c347a9 699 }
2d1070b2
CW		 700
701 any++;
2017263e 702 }
de227ef0
CW		 703 mutex_unlock(&dev->struct_mutex);
704
2d1070b2 705 if (any == 0)
267f0c90 706 seq_puts(m, "No requests\n");
c2c347a9 707
2017263e
BG		 708 return 0;
709}
710
b2223497 711static void i915_ring_seqno_info(struct seq_file *m,
a4872ba6 712 struct intel_engine_cs *ring)
b2223497
CW		 713{
714 if (ring->get_seqno) {
20e28fba 715 seq_printf(m, "Current sequence (%s): %x\n",
b2eadbc8 716 ring->name, ring->get_seqno(ring, false));
b2223497
CW		 717 }
718}
719
2017263e
BG		 720static int i915_gem_seqno_info(struct seq_file *m, void *data)
721{
9f25d007 722 struct drm_info_node *node = m->private;
2017263e 723 struct drm_device *dev = node->minor->dev;
e277a1f8 724 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 725 struct intel_engine_cs *ring;
1ec14ad3 726 int ret, i;
de227ef0
CW		 727
728 ret = mutex_lock_interruptible(&dev->struct_mutex);
729 if (ret)
730 return ret;
c8c8fb33 731 intel_runtime_pm_get(dev_priv);
2017263e 732
a2c7f6fd
CW		 733 for_each_ring(ring, dev_priv, i)
734 i915_ring_seqno_info(m, ring);
de227ef0 735
c8c8fb33 736 intel_runtime_pm_put(dev_priv);
de227ef0
CW		 737 mutex_unlock(&dev->struct_mutex);
738
2017263e
BG		 739 return 0;
740}
741
742
743static int i915_interrupt_info(struct seq_file *m, void *data)
744{
9f25d007 745 struct drm_info_node *node = m->private;
2017263e 746 struct drm_device *dev = node->minor->dev;
e277a1f8 747 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 748 struct intel_engine_cs *ring;
9db4a9c7 749 int ret, i, pipe;
de227ef0
CW		 750
751 ret = mutex_lock_interruptible(&dev->struct_mutex);
752 if (ret)
753 return ret;
c8c8fb33 754 intel_runtime_pm_get(dev_priv);
2017263e 755
74e1ca8c 756 if (IS_CHERRYVIEW(dev)) {
74e1ca8c
VS		 757 seq_printf(m, "Master Interrupt Control:\t%08x\n",
758 I915_READ(GEN8_MASTER_IRQ));
759
760 seq_printf(m, "Display IER:\t%08x\n",
761 I915_READ(VLV_IER));
762 seq_printf(m, "Display IIR:\t%08x\n",
763 I915_READ(VLV_IIR));
764 seq_printf(m, "Display IIR_RW:\t%08x\n",
765 I915_READ(VLV_IIR_RW));
766 seq_printf(m, "Display IMR:\t%08x\n",
767 I915_READ(VLV_IMR));
055e393f 768 for_each_pipe(dev_priv, pipe)
74e1ca8c
VS		 769 seq_printf(m, "Pipe %c stat:\t%08x\n",
770 pipe_name(pipe),
771 I915_READ(PIPESTAT(pipe)));
772
773 seq_printf(m, "Port hotplug:\t%08x\n",
774 I915_READ(PORT_HOTPLUG_EN));
775 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
776 I915_READ(VLV_DPFLIPSTAT));
777 seq_printf(m, "DPINVGTT:\t%08x\n",
778 I915_READ(DPINVGTT));
779
780 for (i = 0; i < 4; i++) {
781 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
782 i, I915_READ(GEN8_GT_IMR(i)));
783 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
784 i, I915_READ(GEN8_GT_IIR(i)));
785 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
786 i, I915_READ(GEN8_GT_IER(i)));
787 }
788
789 seq_printf(m, "PCU interrupt mask:\t%08x\n",
790 I915_READ(GEN8_PCU_IMR));
791 seq_printf(m, "PCU interrupt identity:\t%08x\n",
792 I915_READ(GEN8_PCU_IIR));
793 seq_printf(m, "PCU interrupt enable:\t%08x\n",
794 I915_READ(GEN8_PCU_IER));
795 } else if (INTEL_INFO(dev)->gen >= 8) {
a123f157
BW		 796 seq_printf(m, "Master Interrupt Control:\t%08x\n",
797 I915_READ(GEN8_MASTER_IRQ));
798
799 for (i = 0; i < 4; i++) {
800 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
801 i, I915_READ(GEN8_GT_IMR(i)));
802 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
803 i, I915_READ(GEN8_GT_IIR(i)));
804 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
805 i, I915_READ(GEN8_GT_IER(i)));
806 }
807
055e393f 808 for_each_pipe(dev_priv, pipe) {
f458ebbc 809 if (!intel_display_power_is_enabled(dev_priv,
22c59960
PZ		 810 POWER_DOMAIN_PIPE(pipe))) {
811 seq_printf(m, "Pipe %c power disabled\n",
812 pipe_name(pipe));
813 continue;
814 }
a123f157 815 seq_printf(m, "Pipe %c IMR:\t%08x\n",
07d27e20
DL		 816 pipe_name(pipe),
817 I915_READ(GEN8_DE_PIPE_IMR(pipe)));
a123f157 818 seq_printf(m, "Pipe %c IIR:\t%08x\n",
07d27e20
DL		 819 pipe_name(pipe),
820 I915_READ(GEN8_DE_PIPE_IIR(pipe)));
a123f157 821 seq_printf(m, "Pipe %c IER:\t%08x\n",
07d27e20
DL		 822 pipe_name(pipe),
823 I915_READ(GEN8_DE_PIPE_IER(pipe)));
a123f157
BW		 824 }
825
826 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
827 I915_READ(GEN8_DE_PORT_IMR));
828 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
829 I915_READ(GEN8_DE_PORT_IIR));
830 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
831 I915_READ(GEN8_DE_PORT_IER));
832
833 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
834 I915_READ(GEN8_DE_MISC_IMR));
835 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
836 I915_READ(GEN8_DE_MISC_IIR));
837 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
838 I915_READ(GEN8_DE_MISC_IER));
839
840 seq_printf(m, "PCU interrupt mask:\t%08x\n",
841 I915_READ(GEN8_PCU_IMR));
842 seq_printf(m, "PCU interrupt identity:\t%08x\n",
843 I915_READ(GEN8_PCU_IIR));
844 seq_printf(m, "PCU interrupt enable:\t%08x\n",
845 I915_READ(GEN8_PCU_IER));
846 } else if (IS_VALLEYVIEW(dev)) {
7e231dbe
JB		 847 seq_printf(m, "Display IER:\t%08x\n",
848 I915_READ(VLV_IER));
849 seq_printf(m, "Display IIR:\t%08x\n",
850 I915_READ(VLV_IIR));
851 seq_printf(m, "Display IIR_RW:\t%08x\n",
852 I915_READ(VLV_IIR_RW));
853 seq_printf(m, "Display IMR:\t%08x\n",
854 I915_READ(VLV_IMR));
055e393f 855 for_each_pipe(dev_priv, pipe)
7e231dbe
JB		 856 seq_printf(m, "Pipe %c stat:\t%08x\n",
857 pipe_name(pipe),
858 I915_READ(PIPESTAT(pipe)));
859
860 seq_printf(m, "Master IER:\t%08x\n",
861 I915_READ(VLV_MASTER_IER));
862
863 seq_printf(m, "Render IER:\t%08x\n",
864 I915_READ(GTIER));
865 seq_printf(m, "Render IIR:\t%08x\n",
866 I915_READ(GTIIR));
867 seq_printf(m, "Render IMR:\t%08x\n",
868 I915_READ(GTIMR));
869
870 seq_printf(m, "PM IER:\t\t%08x\n",
871 I915_READ(GEN6_PMIER));
872 seq_printf(m, "PM IIR:\t\t%08x\n",
873 I915_READ(GEN6_PMIIR));
874 seq_printf(m, "PM IMR:\t\t%08x\n",
875 I915_READ(GEN6_PMIMR));
876
877 seq_printf(m, "Port hotplug:\t%08x\n",
878 I915_READ(PORT_HOTPLUG_EN));
879 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
880 I915_READ(VLV_DPFLIPSTAT));
881 seq_printf(m, "DPINVGTT:\t%08x\n",
882 I915_READ(DPINVGTT));
883
884 } else if (!HAS_PCH_SPLIT(dev)) {
5f6a1695
ZW		 885 seq_printf(m, "Interrupt enable: %08x\n",
886 I915_READ(IER));
887 seq_printf(m, "Interrupt identity: %08x\n",
888 I915_READ(IIR));
889 seq_printf(m, "Interrupt mask: %08x\n",
890 I915_READ(IMR));
055e393f 891 for_each_pipe(dev_priv, pipe)
9db4a9c7
JB		 892 seq_printf(m, "Pipe %c stat: %08x\n",
893 pipe_name(pipe),
894 I915_READ(PIPESTAT(pipe)));
5f6a1695
ZW		 895 } else {
896 seq_printf(m, "North Display Interrupt enable: %08x\n",
897 I915_READ(DEIER));
898 seq_printf(m, "North Display Interrupt identity: %08x\n",
899 I915_READ(DEIIR));
900 seq_printf(m, "North Display Interrupt mask: %08x\n",
901 I915_READ(DEIMR));
902 seq_printf(m, "South Display Interrupt enable: %08x\n",
903 I915_READ(SDEIER));
904 seq_printf(m, "South Display Interrupt identity: %08x\n",
905 I915_READ(SDEIIR));
906 seq_printf(m, "South Display Interrupt mask: %08x\n",
907 I915_READ(SDEIMR));
908 seq_printf(m, "Graphics Interrupt enable: %08x\n",
909 I915_READ(GTIER));
910 seq_printf(m, "Graphics Interrupt identity: %08x\n",
911 I915_READ(GTIIR));
912 seq_printf(m, "Graphics Interrupt mask: %08x\n",
913 I915_READ(GTIMR));
914 }
a2c7f6fd 915 for_each_ring(ring, dev_priv, i) {
a123f157 916 if (INTEL_INFO(dev)->gen >= 6) {
a2c7f6fd
CW		 917 seq_printf(m,
918 "Graphics Interrupt mask (%s): %08x\n",
919 ring->name, I915_READ_IMR(ring));
9862e600 920 }
a2c7f6fd 921 i915_ring_seqno_info(m, ring);
9862e600 922 }
c8c8fb33 923 intel_runtime_pm_put(dev_priv);
de227ef0
CW		 924 mutex_unlock(&dev->struct_mutex);
925
2017263e
BG		 926 return 0;
927}
928
a6172a80
CW		 929static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
930{
9f25d007 931 struct drm_info_node *node = m->private;
a6172a80 932 struct drm_device *dev = node->minor->dev;
e277a1f8 933 struct drm_i915_private *dev_priv = dev->dev_private;
de227ef0
CW		 934 int i, ret;
935
936 ret = mutex_lock_interruptible(&dev->struct_mutex);
937 if (ret)
938 return ret;
a6172a80
CW		 939
940 seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
941 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
942 for (i = 0; i < dev_priv->num_fence_regs; i++) {
05394f39 943 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
a6172a80 944
6c085a72
CW		 945 seq_printf(m, "Fence %d, pin count = %d, object = ",
946 i, dev_priv->fence_regs[i].pin_count);
c2c347a9 947 if (obj == NULL)
267f0c90 948 seq_puts(m, "unused");
c2c347a9 949 else
05394f39 950 describe_obj(m, obj);
267f0c90 951 seq_putc(m, '\n');
a6172a80
CW		 952 }
953
05394f39 954 mutex_unlock(&dev->struct_mutex);
a6172a80
CW		 955 return 0;
956}
957
2017263e
BG		 958static int i915_hws_info(struct seq_file *m, void *data)
959{
9f25d007 960 struct drm_info_node *node = m->private;
2017263e 961 struct drm_device *dev = node->minor->dev;
e277a1f8 962 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 963 struct intel_engine_cs *ring;
1a240d4d 964 const u32 *hws;
4066c0ae
CW		 965 int i;
966
1ec14ad3 967 ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
1a240d4d 968 hws = ring->status_page.page_addr;
2017263e
BG		 969 if (hws == NULL)
970 return 0;
971
972 for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
973 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
974 i * 4,
975 hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
976 }
977 return 0;
978}
979
d5442303
DV		 980static ssize_t
981i915_error_state_write(struct file *filp,
982 const char __user *ubuf,
983 size_t cnt,
984 loff_t *ppos)
985{
edc3d884 986 struct i915_error_state_file_priv *error_priv = filp->private_data;
d5442303 987 struct drm_device *dev = error_priv->dev;
22bcfc6a 988 int ret;
d5442303
DV		 989
990 DRM_DEBUG_DRIVER("Resetting error state\n");
991
22bcfc6a
DV		 992 ret = mutex_lock_interruptible(&dev->struct_mutex);
993 if (ret)
994 return ret;
995
d5442303
DV		 996 i915_destroy_error_state(dev);
997 mutex_unlock(&dev->struct_mutex);
998
999 return cnt;
1000}
1001
1002static int i915_error_state_open(struct inode *inode, struct file *file)
1003{
1004 struct drm_device *dev = inode->i_private;
d5442303 1005 struct i915_error_state_file_priv *error_priv;
d5442303
DV		 1006
1007 error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
1008 if (!error_priv)
1009 return -ENOMEM;
1010
1011 error_priv->dev = dev;
1012
95d5bfb3 1013 i915_error_state_get(dev, error_priv);
d5442303 1014
edc3d884
MK		 1015 file->private_data = error_priv;
1016
1017 return 0;
d5442303
DV		 1018}
1019
1020static int i915_error_state_release(struct inode *inode, struct file *file)
1021{
edc3d884 1022 struct i915_error_state_file_priv *error_priv = file->private_data;
d5442303 1023
95d5bfb3 1024 i915_error_state_put(error_priv);
d5442303
DV		 1025 kfree(error_priv);
1026
edc3d884
MK		 1027 return 0;
1028}
1029
4dc955f7
MK		 1030static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
1031 size_t count, loff_t *pos)
1032{
1033 struct i915_error_state_file_priv *error_priv = file->private_data;
1034 struct drm_i915_error_state_buf error_str;
1035 loff_t tmp_pos = 0;
1036 ssize_t ret_count = 0;
1037 int ret;
1038
0a4cd7c8 1039 ret = i915_error_state_buf_init(&error_str, to_i915(error_priv->dev), count, *pos);
4dc955f7
MK		 1040 if (ret)
1041 return ret;
edc3d884 1042
fc16b48b 1043 ret = i915_error_state_to_str(&error_str, error_priv);
edc3d884
MK		 1044 if (ret)
1045 goto out;
1046
edc3d884
MK		 1047 ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
1048 error_str.buf,
1049 error_str.bytes);
1050
1051 if (ret_count < 0)
1052 ret = ret_count;
1053 else
1054 *pos = error_str.start + ret_count;
1055out:
4dc955f7 1056 i915_error_state_buf_release(&error_str);
edc3d884 1057 return ret ?: ret_count;
d5442303
DV		 1058}
1059
1060static const struct file_operations i915_error_state_fops = {
1061 .owner = THIS_MODULE,
1062 .open = i915_error_state_open,
edc3d884 1063 .read = i915_error_state_read,
d5442303
DV		 1064 .write = i915_error_state_write,
1065 .llseek = default_llseek,
1066 .release = i915_error_state_release,
1067};
1068
647416f9
KC		 1069static int
1070i915_next_seqno_get(void *data, u64 *val)
40633219 1071{
647416f9 1072 struct drm_device *dev = data;
e277a1f8 1073 struct drm_i915_private *dev_priv = dev->dev_private;
40633219
MK		 1074 int ret;
1075
1076 ret = mutex_lock_interruptible(&dev->struct_mutex);
1077 if (ret)
1078 return ret;
1079
647416f9 1080 *val = dev_priv->next_seqno;
40633219
MK		 1081 mutex_unlock(&dev->struct_mutex);
1082
647416f9 1083 return 0;
40633219
MK		 1084}
1085
647416f9
KC		 1086static int
1087i915_next_seqno_set(void *data, u64 val)
1088{
1089 struct drm_device *dev = data;
40633219
MK		 1090 int ret;
1091
40633219
MK		 1092 ret = mutex_lock_interruptible(&dev->struct_mutex);
1093 if (ret)
1094 return ret;
1095
e94fbaa8 1096 ret = i915_gem_set_seqno(dev, val);
40633219
MK		 1097 mutex_unlock(&dev->struct_mutex);
1098
647416f9 1099 return ret;
40633219
MK		 1100}
1101
647416f9
KC		 1102DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
1103 i915_next_seqno_get, i915_next_seqno_set,
3a3b4f98 1104 "0x%llx\n");
40633219 1105
adb4bd12 1106static int i915_frequency_info(struct seq_file *m, void *unused)
f97108d1 1107{
9f25d007 1108 struct drm_info_node *node = m->private;
f97108d1 1109 struct drm_device *dev = node->minor->dev;
e277a1f8 1110 struct drm_i915_private *dev_priv = dev->dev_private;
c8c8fb33
PZ		 1111 int ret = 0;
1112
1113 intel_runtime_pm_get(dev_priv);
3b8d8d91 1114
5c9669ce
TR		 1115 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1116
3b8d8d91
JB		 1117 if (IS_GEN5(dev)) {
1118 u16 rgvswctl = I915_READ16(MEMSWCTL);
1119 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1120
1121 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1122 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1123 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1124 MEMSTAT_VID_SHIFT);
1125 seq_printf(m, "Current P-state: %d\n",
1126 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
daa3afb2 1127 } else if (IS_GEN6(dev) || (IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) ||
60260a5b 1128 IS_BROADWELL(dev) || IS_GEN9(dev)) {
3b8d8d91
JB		 1129 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1130 u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1131 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
0d8f9491 1132 u32 rpmodectl, rpinclimit, rpdeclimit;
8e8c06cd 1133 u32 rpstat, cagf, reqf;
ccab5c82
JB		 1134 u32 rpupei, rpcurup, rpprevup;
1135 u32 rpdownei, rpcurdown, rpprevdown;
9dd3c605 1136 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
3b8d8d91
JB		 1137 int max_freq;
1138
1139 /* RPSTAT1 is in the GT power well */
d1ebd816
BW		 1140 ret = mutex_lock_interruptible(&dev->struct_mutex);
1141 if (ret)
c8c8fb33 1142 goto out;
d1ebd816 1143
59bad947 1144 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
3b8d8d91 1145
8e8c06cd 1146 reqf = I915_READ(GEN6_RPNSWREQ);
60260a5b
AG		 1147 if (IS_GEN9(dev))
1148 reqf >>= 23;
1149 else {
1150 reqf &= ~GEN6_TURBO_DISABLE;
1151 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1152 reqf >>= 24;
1153 else
1154 reqf >>= 25;
1155 }
7c59a9c1 1156 reqf = intel_gpu_freq(dev_priv, reqf);
8e8c06cd 1157
0d8f9491
CW		 1158 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1159 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1160 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1161
ccab5c82
JB		 1162 rpstat = I915_READ(GEN6_RPSTAT1);
1163 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
1164 rpcurup = I915_READ(GEN6_RP_CUR_UP);
1165 rpprevup = I915_READ(GEN6_RP_PREV_UP);
1166 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
1167 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
1168 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
60260a5b
AG		 1169 if (IS_GEN9(dev))
1170 cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
1171 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
f82855d3
BW		 1172 cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1173 else
1174 cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
7c59a9c1 1175 cagf = intel_gpu_freq(dev_priv, cagf);
ccab5c82 1176
59bad947 1177 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
d1ebd816
BW		 1178 mutex_unlock(&dev->struct_mutex);
1179
9dd3c605
PZ		 1180 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1181 pm_ier = I915_READ(GEN6_PMIER);
1182 pm_imr = I915_READ(GEN6_PMIMR);
1183 pm_isr = I915_READ(GEN6_PMISR);
1184 pm_iir = I915_READ(GEN6_PMIIR);
1185 pm_mask = I915_READ(GEN6_PMINTRMSK);
1186 } else {
1187 pm_ier = I915_READ(GEN8_GT_IER(2));
1188 pm_imr = I915_READ(GEN8_GT_IMR(2));
1189 pm_isr = I915_READ(GEN8_GT_ISR(2));
1190 pm_iir = I915_READ(GEN8_GT_IIR(2));
1191 pm_mask = I915_READ(GEN6_PMINTRMSK);
1192 }
0d8f9491 1193 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
9dd3c605 1194 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
3b8d8d91 1195 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
3b8d8d91 1196 seq_printf(m, "Render p-state ratio: %d\n",
60260a5b 1197 (gt_perf_status & (IS_GEN9(dev) ? 0x1ff00 : 0xff00)) >> 8);
3b8d8d91
JB		 1198 seq_printf(m, "Render p-state VID: %d\n",
1199 gt_perf_status & 0xff);
1200 seq_printf(m, "Render p-state limit: %d\n",
1201 rp_state_limits & 0xff);
0d8f9491
CW		 1202 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1203 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1204 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1205 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
8e8c06cd 1206 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
f82855d3 1207 seq_printf(m, "CAGF: %dMHz\n", cagf);
ccab5c82
JB		 1208 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
1209 GEN6_CURICONT_MASK);
1210 seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
1211 GEN6_CURBSYTAVG_MASK);
1212 seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
1213 GEN6_CURBSYTAVG_MASK);
d86ed34a
CW		 1214 seq_printf(m, "Up threshold: %d%%\n",
1215 dev_priv->rps.up_threshold);
1216
ccab5c82
JB		 1217 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
1218 GEN6_CURIAVG_MASK);
1219 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
1220 GEN6_CURBSYTAVG_MASK);
1221 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
1222 GEN6_CURBSYTAVG_MASK);
d86ed34a
CW		 1223 seq_printf(m, "Down threshold: %d%%\n",
1224 dev_priv->rps.down_threshold);
3b8d8d91
JB		 1225
1226 max_freq = (rp_state_cap & 0xff0000) >> 16;
60260a5b 1227 max_freq *= (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1);
3b8d8d91 1228 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
7c59a9c1 1229 intel_gpu_freq(dev_priv, max_freq));
3b8d8d91
JB		 1230
1231 max_freq = (rp_state_cap & 0xff00) >> 8;
60260a5b 1232 max_freq *= (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1);
3b8d8d91 1233 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
7c59a9c1 1234 intel_gpu_freq(dev_priv, max_freq));
3b8d8d91
JB		 1235
1236 max_freq = rp_state_cap & 0xff;
60260a5b 1237 max_freq *= (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1);
3b8d8d91 1238 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
7c59a9c1 1239 intel_gpu_freq(dev_priv, max_freq));
31c77388 1240 seq_printf(m, "Max overclocked frequency: %dMHz\n",
7c59a9c1 1241 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
aed242ff 1242
d86ed34a
CW		 1243 seq_printf(m, "Current freq: %d MHz\n",
1244 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1245 seq_printf(m, "Actual freq: %d MHz\n", cagf);
aed242ff
CW		 1246 seq_printf(m, "Idle freq: %d MHz\n",
1247 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
d86ed34a
CW		 1248 seq_printf(m, "Min freq: %d MHz\n",
1249 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1250 seq_printf(m, "Max freq: %d MHz\n",
1251 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1252 seq_printf(m,
1253 "efficient (RPe) frequency: %d MHz\n",
1254 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
0a073b84 1255 } else if (IS_VALLEYVIEW(dev)) {
03af2045 1256 u32 freq_sts;
0a073b84 1257
259bd5d4 1258 mutex_lock(&dev_priv->rps.hw_lock);
64936258 1259 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
0a073b84
JB		 1260 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1261 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1262
d86ed34a
CW		 1263 seq_printf(m, "actual GPU freq: %d MHz\n",
1264 intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
1265
1266 seq_printf(m, "current GPU freq: %d MHz\n",
1267 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1268
0a073b84 1269 seq_printf(m, "max GPU freq: %d MHz\n",
7c59a9c1 1270 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
0a073b84 1271
0a073b84 1272 seq_printf(m, "min GPU freq: %d MHz\n",
7c59a9c1 1273 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
03af2045 1274
aed242ff
CW		 1275 seq_printf(m, "idle GPU freq: %d MHz\n",
1276 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1277
7c59a9c1
VS		 1278 seq_printf(m,
1279 "efficient (RPe) frequency: %d MHz\n",
1280 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
259bd5d4 1281 mutex_unlock(&dev_priv->rps.hw_lock);
3b8d8d91 1282 } else {
267f0c90 1283 seq_puts(m, "no P-state info available\n");
3b8d8d91 1284 }
f97108d1 1285
c8c8fb33
PZ		 1286out:
1287 intel_runtime_pm_put(dev_priv);
1288 return ret;
f97108d1
JB		 1289}
1290
f654449a
CW		 1291static int i915_hangcheck_info(struct seq_file *m, void *unused)
1292{
1293 struct drm_info_node *node = m->private;
ebbc7546
MK		 1294 struct drm_device *dev = node->minor->dev;
1295 struct drm_i915_private *dev_priv = dev->dev_private;
f654449a 1296 struct intel_engine_cs *ring;
ebbc7546
MK		 1297 u64 acthd[I915_NUM_RINGS];
1298 u32 seqno[I915_NUM_RINGS];
f654449a
CW		 1299 int i;
1300
1301 if (!i915.enable_hangcheck) {
1302 seq_printf(m, "Hangcheck disabled\n");
1303 return 0;
1304 }
1305
ebbc7546
MK		 1306 intel_runtime_pm_get(dev_priv);
1307
1308 for_each_ring(ring, dev_priv, i) {
1309 seqno[i] = ring->get_seqno(ring, false);
1310 acthd[i] = intel_ring_get_active_head(ring);
1311 }
1312
1313 intel_runtime_pm_put(dev_priv);
1314
f654449a
CW		 1315 if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) {
1316 seq_printf(m, "Hangcheck active, fires in %dms\n",
1317 jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires -
1318 jiffies));
1319 } else
1320 seq_printf(m, "Hangcheck inactive\n");
1321
1322 for_each_ring(ring, dev_priv, i) {
1323 seq_printf(m, "%s:\n", ring->name);
1324 seq_printf(m, "\tseqno = %x [current %x]\n",
ebbc7546 1325 ring->hangcheck.seqno, seqno[i]);
f654449a
CW		 1326 seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
1327 (long long)ring->hangcheck.acthd,
ebbc7546 1328 (long long)acthd[i]);
f654449a
CW		 1329 seq_printf(m, "\tmax ACTHD = 0x%08llx\n",
1330 (long long)ring->hangcheck.max_acthd);
ebbc7546
MK		 1331 seq_printf(m, "\tscore = %d\n", ring->hangcheck.score);
1332 seq_printf(m, "\taction = %d\n", ring->hangcheck.action);
f654449a
CW		 1333 }
1334
1335 return 0;
1336}
1337
4d85529d 1338static int ironlake_drpc_info(struct seq_file *m)
f97108d1 1339{
9f25d007 1340 struct drm_info_node *node = m->private;
f97108d1 1341 struct drm_device *dev = node->minor->dev;
e277a1f8 1342 struct drm_i915_private *dev_priv = dev->dev_private;
616fdb5a
BW		 1343 u32 rgvmodectl, rstdbyctl;
1344 u16 crstandvid;
1345 int ret;
1346
1347 ret = mutex_lock_interruptible(&dev->struct_mutex);
1348 if (ret)
1349 return ret;
c8c8fb33 1350 intel_runtime_pm_get(dev_priv);
616fdb5a
BW		 1351
1352 rgvmodectl = I915_READ(MEMMODECTL);
1353 rstdbyctl = I915_READ(RSTDBYCTL);
1354 crstandvid = I915_READ16(CRSTANDVID);
1355
c8c8fb33 1356 intel_runtime_pm_put(dev_priv);
616fdb5a 1357 mutex_unlock(&dev->struct_mutex);
f97108d1
JB		 1358
1359 seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
1360 "yes" : "no");
1361 seq_printf(m, "Boost freq: %d\n",
1362 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1363 MEMMODE_BOOST_FREQ_SHIFT);
1364 seq_printf(m, "HW control enabled: %s\n",
1365 rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");
1366 seq_printf(m, "SW control enabled: %s\n",
1367 rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");
1368 seq_printf(m, "Gated voltage change: %s\n",
1369 rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");
1370 seq_printf(m, "Starting frequency: P%d\n",
1371 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
7648fa99 1372 seq_printf(m, "Max P-state: P%d\n",
f97108d1 1373 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
7648fa99
JB		 1374 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1375 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1376 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1377 seq_printf(m, "Render standby enabled: %s\n",
1378 (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes");
267f0c90 1379 seq_puts(m, "Current RS state: ");
88271da3
JB		 1380 switch (rstdbyctl & RSX_STATUS_MASK) {
1381 case RSX_STATUS_ON:
267f0c90 1382 seq_puts(m, "on\n");
88271da3
JB		 1383 break;
1384 case RSX_STATUS_RC1:
267f0c90 1385 seq_puts(m, "RC1\n");
88271da3
JB		 1386 break;
1387 case RSX_STATUS_RC1E:
267f0c90 1388 seq_puts(m, "RC1E\n");
88271da3
JB		 1389 break;
1390 case RSX_STATUS_RS1:
267f0c90 1391 seq_puts(m, "RS1\n");
88271da3
JB		 1392 break;
1393 case RSX_STATUS_RS2:
267f0c90 1394 seq_puts(m, "RS2 (RC6)\n");
88271da3
JB		 1395 break;
1396 case RSX_STATUS_RS3:
267f0c90 1397 seq_puts(m, "RC3 (RC6+)\n");
88271da3
JB		 1398 break;
1399 default:
267f0c90 1400 seq_puts(m, "unknown\n");
88271da3
JB		 1401 break;
1402 }
f97108d1
JB		 1403
1404 return 0;
1405}
1406
f65367b5 1407static int i915_forcewake_domains(struct seq_file *m, void *data)
669ab5aa 1408{
b2cff0db
CW		 1409 struct drm_info_node *node = m->private;
1410 struct drm_device *dev = node->minor->dev;
1411 struct drm_i915_private *dev_priv = dev->dev_private;
1412 struct intel_uncore_forcewake_domain *fw_domain;
b2cff0db
CW		 1413 int i;
1414
1415 spin_lock_irq(&dev_priv->uncore.lock);
1416 for_each_fw_domain(fw_domain, dev_priv, i) {
1417 seq_printf(m, "%s.wake_count = %u\n",
05a2fb15 1418 intel_uncore_forcewake_domain_to_str(i),
b2cff0db
CW		 1419 fw_domain->wake_count);
1420 }
1421 spin_unlock_irq(&dev_priv->uncore.lock);
669ab5aa 1422
b2cff0db
CW		 1423 return 0;
1424}
1425
1426static int vlv_drpc_info(struct seq_file *m)
1427{
9f25d007 1428 struct drm_info_node *node = m->private;
669ab5aa
D		 1429 struct drm_device *dev = node->minor->dev;
1430 struct drm_i915_private *dev_priv = dev->dev_private;
6b312cd3 1431 u32 rpmodectl1, rcctl1, pw_status;
669ab5aa 1432
d46c0517
ID		 1433 intel_runtime_pm_get(dev_priv);
1434
6b312cd3 1435 pw_status = I915_READ(VLV_GTLC_PW_STATUS);
669ab5aa
D		 1436 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1437 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1438
d46c0517
ID		 1439 intel_runtime_pm_put(dev_priv);
1440
669ab5aa
D		 1441 seq_printf(m, "Video Turbo Mode: %s\n",
1442 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1443 seq_printf(m, "Turbo enabled: %s\n",
1444 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1445 seq_printf(m, "HW control enabled: %s\n",
1446 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1447 seq_printf(m, "SW control enabled: %s\n",
1448 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1449 GEN6_RP_MEDIA_SW_MODE));
1450 seq_printf(m, "RC6 Enabled: %s\n",
1451 yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1452 GEN6_RC_CTL_EI_MODE(1))));
1453 seq_printf(m, "Render Power Well: %s\n",
6b312cd3 1454 (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
669ab5aa 1455 seq_printf(m, "Media Power Well: %s\n",
6b312cd3 1456 (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
669ab5aa 1457
9cc19be5
ID		 1458 seq_printf(m, "Render RC6 residency since boot: %u\n",
1459 I915_READ(VLV_GT_RENDER_RC6));
1460 seq_printf(m, "Media RC6 residency since boot: %u\n",
1461 I915_READ(VLV_GT_MEDIA_RC6));
1462
f65367b5 1463 return i915_forcewake_domains(m, NULL);
669ab5aa
D		 1464}
1465
4d85529d
BW		 1466static int gen6_drpc_info(struct seq_file *m)
1467{
9f25d007 1468 struct drm_info_node *node = m->private;
4d85529d
BW		 1469 struct drm_device *dev = node->minor->dev;
1470 struct drm_i915_private *dev_priv = dev->dev_private;
ecd8faea 1471 u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
93b525dc 1472 unsigned forcewake_count;
aee56cff 1473 int count = 0, ret;
4d85529d
BW		 1474
1475 ret = mutex_lock_interruptible(&dev->struct_mutex);
1476 if (ret)
1477 return ret;
c8c8fb33 1478 intel_runtime_pm_get(dev_priv);
4d85529d 1479
907b28c5 1480 spin_lock_irq(&dev_priv->uncore.lock);
b2cff0db 1481 forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count;
907b28c5 1482 spin_unlock_irq(&dev_priv->uncore.lock);
93b525dc
DV		 1483
1484 if (forcewake_count) {
267f0c90
DL		 1485 seq_puts(m, "RC information inaccurate because somebody "
1486 "holds a forcewake reference \n");
4d85529d
BW		 1487 } else {
1488 /* NB: we cannot use forcewake, else we read the wrong values */
1489 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1490 udelay(10);
1491 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1492 }
1493
1494 gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS);
ed71f1b4 1495 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
4d85529d
BW		 1496
1497 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1498 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1499 mutex_unlock(&dev->struct_mutex);
44cbd338
BW		 1500 mutex_lock(&dev_priv->rps.hw_lock);
1501 sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1502 mutex_unlock(&dev_priv->rps.hw_lock);
4d85529d 1503
c8c8fb33
PZ		 1504 intel_runtime_pm_put(dev_priv);
1505
4d85529d
BW		 1506 seq_printf(m, "Video Turbo Mode: %s\n",
1507 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1508 seq_printf(m, "HW control enabled: %s\n",
1509 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1510 seq_printf(m, "SW control enabled: %s\n",
1511 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1512 GEN6_RP_MEDIA_SW_MODE));
fff24e21 1513 seq_printf(m, "RC1e Enabled: %s\n",
4d85529d
BW		 1514 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1515 seq_printf(m, "RC6 Enabled: %s\n",
1516 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1517 seq_printf(m, "Deep RC6 Enabled: %s\n",
1518 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1519 seq_printf(m, "Deepest RC6 Enabled: %s\n",
1520 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
267f0c90 1521 seq_puts(m, "Current RC state: ");
4d85529d
BW		 1522 switch (gt_core_status & GEN6_RCn_MASK) {
1523 case GEN6_RC0:
1524 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
267f0c90 1525 seq_puts(m, "Core Power Down\n");
4d85529d 1526 else
267f0c90 1527 seq_puts(m, "on\n");
4d85529d
BW		 1528 break;
1529 case GEN6_RC3:
267f0c90 1530 seq_puts(m, "RC3\n");
4d85529d
BW		 1531 break;
1532 case GEN6_RC6:
267f0c90 1533 seq_puts(m, "RC6\n");
4d85529d
BW		 1534 break;
1535 case GEN6_RC7:
267f0c90 1536 seq_puts(m, "RC7\n");
4d85529d
BW		 1537 break;
1538 default:
267f0c90 1539 seq_puts(m, "Unknown\n");
4d85529d
BW		 1540 break;
1541 }
1542
1543 seq_printf(m, "Core Power Down: %s\n",
1544 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
cce66a28
BW		 1545
1546 /* Not exactly sure what this is */
1547 seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1548 I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1549 seq_printf(m, "RC6 residency since boot: %u\n",
1550 I915_READ(GEN6_GT_GFX_RC6));
1551 seq_printf(m, "RC6+ residency since boot: %u\n",
1552 I915_READ(GEN6_GT_GFX_RC6p));
1553 seq_printf(m, "RC6++ residency since boot: %u\n",
1554 I915_READ(GEN6_GT_GFX_RC6pp));
1555
ecd8faea
BW		 1556 seq_printf(m, "RC6 voltage: %dmV\n",
1557 GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1558 seq_printf(m, "RC6+ voltage: %dmV\n",
1559 GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1560 seq_printf(m, "RC6++ voltage: %dmV\n",
1561 GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
4d85529d
BW		 1562 return 0;
1563}
1564
1565static int i915_drpc_info(struct seq_file *m, void *unused)
1566{
9f25d007 1567 struct drm_info_node *node = m->private;
4d85529d
BW		 1568 struct drm_device *dev = node->minor->dev;
1569
669ab5aa
D		 1570 if (IS_VALLEYVIEW(dev))
1571 return vlv_drpc_info(m);
ac66cf4b 1572 else if (INTEL_INFO(dev)->gen >= 6)
4d85529d
BW		 1573 return gen6_drpc_info(m);
1574 else
1575 return ironlake_drpc_info(m);
1576}
1577
b5e50c3f
JB		 1578static int i915_fbc_status(struct seq_file *m, void *unused)
1579{
9f25d007 1580 struct drm_info_node *node = m->private;
b5e50c3f 1581 struct drm_device *dev = node->minor->dev;
e277a1f8 1582 struct drm_i915_private *dev_priv = dev->dev_private;
b5e50c3f 1583
3a77c4c4 1584 if (!HAS_FBC(dev)) {
267f0c90 1585 seq_puts(m, "FBC unsupported on this chipset\n");
b5e50c3f
JB		 1586 return 0;
1587 }
1588
36623ef8
PZ		 1589 intel_runtime_pm_get(dev_priv);
1590
ee5382ae 1591 if (intel_fbc_enabled(dev)) {
267f0c90 1592 seq_puts(m, "FBC enabled\n");
b5e50c3f 1593 } else {
267f0c90 1594 seq_puts(m, "FBC disabled: ");
5c3fe8b0 1595 switch (dev_priv->fbc.no_fbc_reason) {
29ebf90f
CW		 1596 case FBC_OK:
1597 seq_puts(m, "FBC actived, but currently disabled in hardware");
1598 break;
1599 case FBC_UNSUPPORTED:
1600 seq_puts(m, "unsupported by this chipset");
1601 break;
bed4a673 1602 case FBC_NO_OUTPUT:
267f0c90 1603 seq_puts(m, "no outputs");
bed4a673 1604 break;
b5e50c3f 1605 case FBC_STOLEN_TOO_SMALL:
267f0c90 1606 seq_puts(m, "not enough stolen memory");
b5e50c3f
JB		 1607 break;
1608 case FBC_UNSUPPORTED_MODE:
267f0c90 1609 seq_puts(m, "mode not supported");
b5e50c3f
JB		 1610 break;
1611 case FBC_MODE_TOO_LARGE:
267f0c90 1612 seq_puts(m, "mode too large");
b5e50c3f
JB		 1613 break;
1614 case FBC_BAD_PLANE:
267f0c90 1615 seq_puts(m, "FBC unsupported on plane");
b5e50c3f
JB		 1616 break;
1617 case FBC_NOT_TILED:
267f0c90 1618 seq_puts(m, "scanout buffer not tiled");
b5e50c3f 1619 break;
9c928d16 1620 case FBC_MULTIPLE_PIPES:
267f0c90 1621 seq_puts(m, "multiple pipes are enabled");
9c928d16 1622 break;
c1a9f047 1623 case FBC_MODULE_PARAM:
267f0c90 1624 seq_puts(m, "disabled per module param (default off)");
c1a9f047 1625 break;
8a5729a3 1626 case FBC_CHIP_DEFAULT:
267f0c90 1627 seq_puts(m, "disabled per chip default");
8a5729a3 1628 break;
b5e50c3f 1629 default:
267f0c90 1630 seq_puts(m, "unknown reason");
b5e50c3f 1631 }
267f0c90 1632 seq_putc(m, '\n');
b5e50c3f 1633 }
36623ef8
PZ		 1634
1635 intel_runtime_pm_put(dev_priv);
1636
b5e50c3f
JB		 1637 return 0;
1638}
1639
da46f936
RV		 1640static int i915_fbc_fc_get(void *data, u64 *val)
1641{
1642 struct drm_device *dev = data;
1643 struct drm_i915_private *dev_priv = dev->dev_private;
1644
1645 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1646 return -ENODEV;
1647
1648 drm_modeset_lock_all(dev);
1649 *val = dev_priv->fbc.false_color;
1650 drm_modeset_unlock_all(dev);
1651
1652 return 0;
1653}
1654
1655static int i915_fbc_fc_set(void *data, u64 val)
1656{
1657 struct drm_device *dev = data;
1658 struct drm_i915_private *dev_priv = dev->dev_private;
1659 u32 reg;
1660
1661 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1662 return -ENODEV;
1663
1664 drm_modeset_lock_all(dev);
1665
1666 reg = I915_READ(ILK_DPFC_CONTROL);
1667 dev_priv->fbc.false_color = val;
1668
1669 I915_WRITE(ILK_DPFC_CONTROL, val ?
1670 (reg | FBC_CTL_FALSE_COLOR) :
1671 (reg & ~FBC_CTL_FALSE_COLOR));
1672
1673 drm_modeset_unlock_all(dev);
1674 return 0;
1675}
1676
1677DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops,
1678 i915_fbc_fc_get, i915_fbc_fc_set,
1679 "%llu\n");
1680
92d44621
PZ		 1681static int i915_ips_status(struct seq_file *m, void *unused)
1682{
9f25d007 1683 struct drm_info_node *node = m->private;
92d44621
PZ		 1684 struct drm_device *dev = node->minor->dev;
1685 struct drm_i915_private *dev_priv = dev->dev_private;
1686
f5adf94e 1687 if (!HAS_IPS(dev)) {
92d44621
PZ		 1688 seq_puts(m, "not supported\n");
1689 return 0;
1690 }
1691
36623ef8
PZ		 1692 intel_runtime_pm_get(dev_priv);
1693
0eaa53f0
RV		 1694 seq_printf(m, "Enabled by kernel parameter: %s\n",
1695 yesno(i915.enable_ips));
1696
1697 if (INTEL_INFO(dev)->gen >= 8) {
1698 seq_puts(m, "Currently: unknown\n");
1699 } else {
1700 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1701 seq_puts(m, "Currently: enabled\n");
1702 else
1703 seq_puts(m, "Currently: disabled\n");
1704 }
92d44621 1705
36623ef8
PZ		 1706 intel_runtime_pm_put(dev_priv);
1707
92d44621
PZ		 1708 return 0;
1709}
1710
4a9bef37
JB		 1711static int i915_sr_status(struct seq_file *m, void *unused)
1712{
9f25d007 1713 struct drm_info_node *node = m->private;
4a9bef37 1714 struct drm_device *dev = node->minor->dev;
e277a1f8 1715 struct drm_i915_private *dev_priv = dev->dev_private;
4a9bef37
JB		 1716 bool sr_enabled = false;
1717
36623ef8
PZ		 1718 intel_runtime_pm_get(dev_priv);
1719
1398261a 1720 if (HAS_PCH_SPLIT(dev))
5ba2aaaa 1721 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
a6c45cf0 1722 else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))
4a9bef37
JB		 1723 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1724 else if (IS_I915GM(dev))
1725 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1726 else if (IS_PINEVIEW(dev))
1727 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1728
36623ef8
PZ		 1729 intel_runtime_pm_put(dev_priv);
1730
5ba2aaaa
CW		 1731 seq_printf(m, "self-refresh: %s\n",
1732 sr_enabled ? "enabled" : "disabled");
4a9bef37
JB		 1733
1734 return 0;
1735}
1736
7648fa99
JB		 1737static int i915_emon_status(struct seq_file *m, void *unused)
1738{
9f25d007 1739 struct drm_info_node *node = m->private;
7648fa99 1740 struct drm_device *dev = node->minor->dev;
e277a1f8 1741 struct drm_i915_private *dev_priv = dev->dev_private;
7648fa99 1742 unsigned long temp, chipset, gfx;
de227ef0
CW		 1743 int ret;
1744
582be6b4
CW		 1745 if (!IS_GEN5(dev))
1746 return -ENODEV;
1747
de227ef0
CW		 1748 ret = mutex_lock_interruptible(&dev->struct_mutex);
1749 if (ret)
1750 return ret;
7648fa99
JB		 1751
1752 temp = i915_mch_val(dev_priv);
1753 chipset = i915_chipset_val(dev_priv);
1754 gfx = i915_gfx_val(dev_priv);
de227ef0 1755 mutex_unlock(&dev->struct_mutex);
7648fa99
JB		 1756
1757 seq_printf(m, "GMCH temp: %ld\n", temp);
1758 seq_printf(m, "Chipset power: %ld\n", chipset);
1759 seq_printf(m, "GFX power: %ld\n", gfx);
1760 seq_printf(m, "Total power: %ld\n", chipset + gfx);
1761
1762 return 0;
1763}
1764
23b2f8bb
JB		 1765static int i915_ring_freq_table(struct seq_file *m, void *unused)
1766{
9f25d007 1767 struct drm_info_node *node = m->private;
23b2f8bb 1768 struct drm_device *dev = node->minor->dev;
e277a1f8 1769 struct drm_i915_private *dev_priv = dev->dev_private;
5bfa0199 1770 int ret = 0;
23b2f8bb
JB		 1771 int gpu_freq, ia_freq;
1772
1c70c0ce 1773 if (!(IS_GEN6(dev) || IS_GEN7(dev))) {
267f0c90 1774 seq_puts(m, "unsupported on this chipset\n");
23b2f8bb
JB		 1775 return 0;
1776 }
1777
5bfa0199
PZ		 1778 intel_runtime_pm_get(dev_priv);
1779
5c9669ce
TR		 1780 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1781
4fc688ce 1782 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
23b2f8bb 1783 if (ret)
5bfa0199 1784 goto out;
23b2f8bb 1785
267f0c90 1786 seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
23b2f8bb 1787
b39fb297
BW		 1788 for (gpu_freq = dev_priv->rps.min_freq_softlimit;
1789 gpu_freq <= dev_priv->rps.max_freq_softlimit;
23b2f8bb 1790 gpu_freq++) {
42c0526c
BW		 1791 ia_freq = gpu_freq;
1792 sandybridge_pcode_read(dev_priv,
1793 GEN6_PCODE_READ_MIN_FREQ_TABLE,
1794 &ia_freq);
3ebecd07 1795 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
7c59a9c1 1796 intel_gpu_freq(dev_priv, gpu_freq),
3ebecd07
CW		 1797 ((ia_freq >> 0) & 0xff) * 100,
1798 ((ia_freq >> 8) & 0xff) * 100);
23b2f8bb
JB		 1799 }
1800
4fc688ce 1801 mutex_unlock(&dev_priv->rps.hw_lock);
23b2f8bb 1802
5bfa0199
PZ		 1803out:
1804 intel_runtime_pm_put(dev_priv);
1805 return ret;
23b2f8bb
JB		 1806}
1807
44834a67
CW		 1808static int i915_opregion(struct seq_file *m, void *unused)
1809{
9f25d007 1810 struct drm_info_node *node = m->private;
44834a67 1811 struct drm_device *dev = node->minor->dev;
e277a1f8 1812 struct drm_i915_private *dev_priv = dev->dev_private;
44834a67 1813 struct intel_opregion *opregion = &dev_priv->opregion;
0d38f009 1814 void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL);
44834a67
CW		 1815 int ret;
1816
0d38f009
DV		 1817 if (data == NULL)
1818 return -ENOMEM;
1819
44834a67
CW		 1820 ret = mutex_lock_interruptible(&dev->struct_mutex);
1821 if (ret)
0d38f009 1822 goto out;
44834a67 1823
0d38f009
DV		 1824 if (opregion->header) {
1825 memcpy_fromio(data, opregion->header, OPREGION_SIZE);
1826 seq_write(m, data, OPREGION_SIZE);
1827 }
44834a67
CW		 1828
1829 mutex_unlock(&dev->struct_mutex);
1830
0d38f009
DV		 1831out:
1832 kfree(data);
44834a67
CW		 1833 return 0;
1834}
1835
37811fcc
CW		 1836static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1837{
9f25d007 1838 struct drm_info_node *node = m->private;
37811fcc 1839 struct drm_device *dev = node->minor->dev;
4520f53a 1840 struct intel_fbdev *ifbdev = NULL;
37811fcc 1841 struct intel_framebuffer *fb;
37811fcc 1842
4520f53a
DV		 1843#ifdef CONFIG_DRM_I915_FBDEV
1844 struct drm_i915_private *dev_priv = dev->dev_private;
37811fcc
CW		 1845
1846 ifbdev = dev_priv->fbdev;
1847 fb = to_intel_framebuffer(ifbdev->helper.fb);
1848
c1ca506d 1849 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
37811fcc
CW		 1850 fb->base.width,
1851 fb->base.height,
1852 fb->base.depth,
623f9783 1853 fb->base.bits_per_pixel,
c1ca506d 1854 fb->base.modifier[0],
623f9783 1855 atomic_read(&fb->base.refcount.refcount));
05394f39 1856 describe_obj(m, fb->obj);
267f0c90 1857 seq_putc(m, '\n');
4520f53a 1858#endif
37811fcc 1859
4b096ac1 1860 mutex_lock(&dev->mode_config.fb_lock);
37811fcc 1861 list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) {
131a56dc 1862 if (ifbdev && &fb->base == ifbdev->helper.fb)
37811fcc
CW		 1863 continue;
1864
c1ca506d 1865 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
37811fcc
CW		 1866 fb->base.width,
1867 fb->base.height,
1868 fb->base.depth,
623f9783 1869 fb->base.bits_per_pixel,
c1ca506d 1870 fb->base.modifier[0],
623f9783 1871 atomic_read(&fb->base.refcount.refcount));
05394f39 1872 describe_obj(m, fb->obj);
267f0c90 1873 seq_putc(m, '\n');
37811fcc 1874 }
4b096ac1 1875 mutex_unlock(&dev->mode_config.fb_lock);
37811fcc
CW		 1876
1877 return 0;
1878}
1879
c9fe99bd
OM		 1880static void describe_ctx_ringbuf(struct seq_file *m,
1881 struct intel_ringbuffer *ringbuf)
1882{
1883 seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
1884 ringbuf->space, ringbuf->head, ringbuf->tail,
1885 ringbuf->last_retired_head);
1886}
1887
e76d3630
BW		 1888static int i915_context_status(struct seq_file *m, void *unused)
1889{
9f25d007 1890 struct drm_info_node *node = m->private;
e76d3630 1891 struct drm_device *dev = node->minor->dev;
e277a1f8 1892 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 1893 struct intel_engine_cs *ring;
273497e5 1894 struct intel_context *ctx;
a168c293 1895 int ret, i;
e76d3630 1896
f3d28878 1897 ret = mutex_lock_interruptible(&dev->struct_mutex);
e76d3630
BW		 1898 if (ret)
1899 return ret;
1900
a33afea5 1901 list_for_each_entry(ctx, &dev_priv->context_list, link) {
c9fe99bd
OM		 1902 if (!i915.enable_execlists &&
1903 ctx->legacy_hw_ctx.rcs_state == NULL)
b77f6997
CW		 1904 continue;
1905
a33afea5 1906 seq_puts(m, "HW context ");
3ccfd19d 1907 describe_ctx(m, ctx);
c9fe99bd 1908 for_each_ring(ring, dev_priv, i) {
a33afea5 1909 if (ring->default_context == ctx)
c9fe99bd
OM		 1910 seq_printf(m, "(default context %s) ",
1911 ring->name);
1912 }
1913
1914 if (i915.enable_execlists) {
1915 seq_putc(m, '\n');
1916 for_each_ring(ring, dev_priv, i) {
1917 struct drm_i915_gem_object *ctx_obj =
1918 ctx->engine[i].state;
1919 struct intel_ringbuffer *ringbuf =
1920 ctx->engine[i].ringbuf;
1921
1922 seq_printf(m, "%s: ", ring->name);
1923 if (ctx_obj)
1924 describe_obj(m, ctx_obj);
1925 if (ringbuf)
1926 describe_ctx_ringbuf(m, ringbuf);
1927 seq_putc(m, '\n');
1928 }
1929 } else {
1930 describe_obj(m, ctx->legacy_hw_ctx.rcs_state);
1931 }
a33afea5 1932
a33afea5 1933 seq_putc(m, '\n');
a168c293
BW		 1934 }
1935
f3d28878 1936 mutex_unlock(&dev->struct_mutex);
e76d3630
BW		 1937
1938 return 0;
1939}
1940
064ca1d2
TD		 1941static void i915_dump_lrc_obj(struct seq_file *m,
1942 struct intel_engine_cs *ring,
1943 struct drm_i915_gem_object *ctx_obj)
1944{
1945 struct page *page;
1946 uint32_t *reg_state;
1947 int j;
1948 unsigned long ggtt_offset = 0;
1949
1950 if (ctx_obj == NULL) {
1951 seq_printf(m, "Context on %s with no gem object\n",
1952 ring->name);
1953 return;
1954 }
1955
1956 seq_printf(m, "CONTEXT: %s %u\n", ring->name,
1957 intel_execlists_ctx_id(ctx_obj));
1958
1959 if (!i915_gem_obj_ggtt_bound(ctx_obj))
1960 seq_puts(m, "\tNot bound in GGTT\n");
1961 else
1962 ggtt_offset = i915_gem_obj_ggtt_offset(ctx_obj);
1963
1964 if (i915_gem_object_get_pages(ctx_obj)) {
1965 seq_puts(m, "\tFailed to get pages for context object\n");
1966 return;
1967 }
1968
1969 page = i915_gem_object_get_page(ctx_obj, 1);
1970 if (!WARN_ON(page == NULL)) {
1971 reg_state = kmap_atomic(page);
1972
1973 for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
1974 seq_printf(m, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n",
1975 ggtt_offset + 4096 + (j * 4),
1976 reg_state[j], reg_state[j + 1],
1977 reg_state[j + 2], reg_state[j + 3]);
1978 }
1979 kunmap_atomic(reg_state);
1980 }
1981
1982 seq_putc(m, '\n');
1983}
1984
c0ab1ae9
BW		 1985static int i915_dump_lrc(struct seq_file *m, void *unused)
1986{
1987 struct drm_info_node *node = (struct drm_info_node *) m->private;
1988 struct drm_device *dev = node->minor->dev;
1989 struct drm_i915_private *dev_priv = dev->dev_private;
1990 struct intel_engine_cs *ring;
1991 struct intel_context *ctx;
1992 int ret, i;
1993
1994 if (!i915.enable_execlists) {
1995 seq_printf(m, "Logical Ring Contexts are disabled\n");
1996 return 0;
1997 }
1998
1999 ret = mutex_lock_interruptible(&dev->struct_mutex);
2000 if (ret)
2001 return ret;
2002
2003 list_for_each_entry(ctx, &dev_priv->context_list, link) {
2004 for_each_ring(ring, dev_priv, i) {
064ca1d2
TD		 2005 if (ring->default_context != ctx)
2006 i915_dump_lrc_obj(m, ring,
2007 ctx->engine[i].state);
c0ab1ae9
BW		 2008 }
2009 }
2010
2011 mutex_unlock(&dev->struct_mutex);
2012
2013 return 0;
2014}
2015
4ba70e44
OM		 2016static int i915_execlists(struct seq_file *m, void *data)
2017{
2018 struct drm_info_node *node = (struct drm_info_node *)m->private;
2019 struct drm_device *dev = node->minor->dev;
2020 struct drm_i915_private *dev_priv = dev->dev_private;
2021 struct intel_engine_cs *ring;
2022 u32 status_pointer;
2023 u8 read_pointer;
2024 u8 write_pointer;
2025 u32 status;
2026 u32 ctx_id;
2027 struct list_head *cursor;
2028 int ring_id, i;
2029 int ret;
2030
2031 if (!i915.enable_execlists) {
2032 seq_puts(m, "Logical Ring Contexts are disabled\n");
2033 return 0;
2034 }
2035
2036 ret = mutex_lock_interruptible(&dev->struct_mutex);
2037 if (ret)
2038 return ret;
2039
fc0412ec
MT		 2040 intel_runtime_pm_get(dev_priv);
2041
4ba70e44 2042 for_each_ring(ring, dev_priv, ring_id) {
6d3d8274 2043 struct drm_i915_gem_request *head_req = NULL;
4ba70e44
OM		 2044 int count = 0;
2045 unsigned long flags;
2046
2047 seq_printf(m, "%s\n", ring->name);
2048
2049 status = I915_READ(RING_EXECLIST_STATUS(ring));
2050 ctx_id = I915_READ(RING_EXECLIST_STATUS(ring) + 4);
2051 seq_printf(m, "\tExeclist status: 0x%08X, context: %u\n",
2052 status, ctx_id);
2053
2054 status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(ring));
2055 seq_printf(m, "\tStatus pointer: 0x%08X\n", status_pointer);
2056
2057 read_pointer = ring->next_context_status_buffer;
2058 write_pointer = status_pointer & 0x07;
2059 if (read_pointer > write_pointer)
2060 write_pointer += 6;
2061 seq_printf(m, "\tRead pointer: 0x%08X, write pointer 0x%08X\n",
2062 read_pointer, write_pointer);
2063
2064 for (i = 0; i < 6; i++) {
2065 status = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + 8*i);
2066 ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + 8*i + 4);
2067
2068 seq_printf(m, "\tStatus buffer %d: 0x%08X, context: %u\n",
2069 i, status, ctx_id);
2070 }
2071
2072 spin_lock_irqsave(&ring->execlist_lock, flags);
2073 list_for_each(cursor, &ring->execlist_queue)
2074 count++;
2075 head_req = list_first_entry_or_null(&ring->execlist_queue,
6d3d8274 2076 struct drm_i915_gem_request, execlist_link);
4ba70e44
OM		 2077 spin_unlock_irqrestore(&ring->execlist_lock, flags);
2078
2079 seq_printf(m, "\t%d requests in queue\n", count);
2080 if (head_req) {
2081 struct drm_i915_gem_object *ctx_obj;
2082
6d3d8274 2083 ctx_obj = head_req->ctx->engine[ring_id].state;
4ba70e44
OM		 2084 seq_printf(m, "\tHead request id: %u\n",
2085 intel_execlists_ctx_id(ctx_obj));
2086 seq_printf(m, "\tHead request tail: %u\n",
6d3d8274 2087 head_req->tail);
4ba70e44
OM		 2088 }
2089
2090 seq_putc(m, '\n');
2091 }
2092
fc0412ec 2093 intel_runtime_pm_put(dev_priv);
4ba70e44
OM		 2094 mutex_unlock(&dev->struct_mutex);
2095
2096 return 0;
2097}
2098
ea16a3cd
DV		 2099static const char *swizzle_string(unsigned swizzle)
2100{
aee56cff 2101 switch (swizzle) {
ea16a3cd
DV		 2102 case I915_BIT_6_SWIZZLE_NONE:
2103 return "none";
2104 case I915_BIT_6_SWIZZLE_9:
2105 return "bit9";
2106 case I915_BIT_6_SWIZZLE_9_10:
2107 return "bit9/bit10";
2108 case I915_BIT_6_SWIZZLE_9_11:
2109 return "bit9/bit11";
2110 case I915_BIT_6_SWIZZLE_9_10_11:
2111 return "bit9/bit10/bit11";
2112 case I915_BIT_6_SWIZZLE_9_17:
2113 return "bit9/bit17";
2114 case I915_BIT_6_SWIZZLE_9_10_17:
2115 return "bit9/bit10/bit17";
2116 case I915_BIT_6_SWIZZLE_UNKNOWN:
8a168ca7 2117 return "unknown";
ea16a3cd
DV		 2118 }
2119
2120 return "bug";
2121}
2122
2123static int i915_swizzle_info(struct seq_file *m, void *data)
2124{
9f25d007 2125 struct drm_info_node *node = m->private;
ea16a3cd
DV		 2126 struct drm_device *dev = node->minor->dev;
2127 struct drm_i915_private *dev_priv = dev->dev_private;
22bcfc6a
DV		 2128 int ret;
2129
2130 ret = mutex_lock_interruptible(&dev->struct_mutex);
2131 if (ret)
2132 return ret;
c8c8fb33 2133 intel_runtime_pm_get(dev_priv);
ea16a3cd 2134
ea16a3cd
DV		 2135 seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
2136 swizzle_string(dev_priv->mm.bit_6_swizzle_x));
2137 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
2138 swizzle_string(dev_priv->mm.bit_6_swizzle_y));
2139
2140 if (IS_GEN3(dev) || IS_GEN4(dev)) {
2141 seq_printf(m, "DDC = 0x%08x\n",
2142 I915_READ(DCC));
656bfa3a
DV		 2143 seq_printf(m, "DDC2 = 0x%08x\n",
2144 I915_READ(DCC2));
ea16a3cd
DV		 2145 seq_printf(m, "C0DRB3 = 0x%04x\n",
2146 I915_READ16(C0DRB3));
2147 seq_printf(m, "C1DRB3 = 0x%04x\n",
2148 I915_READ16(C1DRB3));
9d3203e1 2149 } else if (INTEL_INFO(dev)->gen >= 6) {
3fa7d235
DV		 2150 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
2151 I915_READ(MAD_DIMM_C0));
2152 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
2153 I915_READ(MAD_DIMM_C1));
2154 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
2155 I915_READ(MAD_DIMM_C2));
2156 seq_printf(m, "TILECTL = 0x%08x\n",
2157 I915_READ(TILECTL));
5907f5fb 2158 if (INTEL_INFO(dev)->gen >= 8)
9d3203e1
BW		 2159 seq_printf(m, "GAMTARBMODE = 0x%08x\n",
2160 I915_READ(GAMTARBMODE));
2161 else
2162 seq_printf(m, "ARB_MODE = 0x%08x\n",
2163 I915_READ(ARB_MODE));
3fa7d235
DV		 2164 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
2165 I915_READ(DISP_ARB_CTL));
ea16a3cd 2166 }
656bfa3a
DV		 2167
2168 if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2169 seq_puts(m, "L-shaped memory detected\n");
2170
c8c8fb33 2171 intel_runtime_pm_put(dev_priv);
ea16a3cd
DV		 2172 mutex_unlock(&dev->struct_mutex);
2173
2174 return 0;
2175}
2176
1c60fef5
BW		 2177static int per_file_ctx(int id, void *ptr, void *data)
2178{
273497e5 2179 struct intel_context *ctx = ptr;
1c60fef5 2180 struct seq_file *m = data;
ae6c4806
DV		 2181 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2182
2183 if (!ppgtt) {
2184 seq_printf(m, " no ppgtt for context %d\n",
2185 ctx->user_handle);
2186 return 0;
2187 }
1c60fef5 2188
f83d6518
OM		 2189 if (i915_gem_context_is_default(ctx))
2190 seq_puts(m, " default context:\n");
2191 else
821d66dd 2192 seq_printf(m, " context %d:\n", ctx->user_handle);
1c60fef5
BW		 2193 ppgtt->debug_dump(ppgtt, m);
2194
2195 return 0;
2196}
2197
77df6772 2198static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev)
3cf17fc5 2199{
3cf17fc5 2200 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2201 struct intel_engine_cs *ring;
77df6772
BW		 2202 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2203 int unused, i;
3cf17fc5 2204
77df6772
BW		 2205 if (!ppgtt)
2206 return;
2207
77df6772
BW		 2208 for_each_ring(ring, dev_priv, unused) {
2209 seq_printf(m, "%s\n", ring->name);
2210 for (i = 0; i < 4; i++) {
2211 u32 offset = 0x270 + i * 8;
2212 u64 pdp = I915_READ(ring->mmio_base + offset + 4);
2213 pdp <<= 32;
2214 pdp |= I915_READ(ring->mmio_base + offset);
a2a5b15c 2215 seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
77df6772
BW		 2216 }
2217 }
2218}
2219
2220static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2221{
2222 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2223 struct intel_engine_cs *ring;
1c60fef5 2224 struct drm_file *file;
77df6772 2225 int i;
3cf17fc5 2226
3cf17fc5
DV		 2227 if (INTEL_INFO(dev)->gen == 6)
2228 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
2229
a2c7f6fd 2230 for_each_ring(ring, dev_priv, i) {
3cf17fc5
DV		 2231 seq_printf(m, "%s\n", ring->name);
2232 if (INTEL_INFO(dev)->gen == 7)
2233 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
2234 seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
2235 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
2236 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring)));
2237 }
2238 if (dev_priv->mm.aliasing_ppgtt) {
2239 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2240
267f0c90 2241 seq_puts(m, "aliasing PPGTT:\n");
7324cc04 2242 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.pd_offset);
1c60fef5 2243
87d60b63 2244 ppgtt->debug_dump(ppgtt, m);
ae6c4806 2245 }
1c60fef5
BW		 2246
2247 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2248 struct drm_i915_file_private *file_priv = file->driver_priv;
1c60fef5 2249
1c60fef5
BW		 2250 seq_printf(m, "proc: %s\n",
2251 get_pid_task(file->pid, PIDTYPE_PID)->comm);
1c60fef5 2252 idr_for_each(&file_priv->context_idr, per_file_ctx, m);
3cf17fc5
DV		 2253 }
2254 seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
77df6772
BW		 2255}
2256
2257static int i915_ppgtt_info(struct seq_file *m, void *data)
2258{
9f25d007 2259 struct drm_info_node *node = m->private;
77df6772 2260 struct drm_device *dev = node->minor->dev;
c8c8fb33 2261 struct drm_i915_private *dev_priv = dev->dev_private;
77df6772
BW		 2262
2263 int ret = mutex_lock_interruptible(&dev->struct_mutex);
2264 if (ret)
2265 return ret;
c8c8fb33 2266 intel_runtime_pm_get(dev_priv);
77df6772
BW		 2267
2268 if (INTEL_INFO(dev)->gen >= 8)
2269 gen8_ppgtt_info(m, dev);
2270 else if (INTEL_INFO(dev)->gen >= 6)
2271 gen6_ppgtt_info(m, dev);
2272
c8c8fb33 2273 intel_runtime_pm_put(dev_priv);
3cf17fc5
DV		 2274 mutex_unlock(&dev->struct_mutex);
2275
2276 return 0;
2277}
2278
1854d5ca
CW		 2279static int i915_rps_boost_info(struct seq_file *m, void *data)
2280{
2281 struct drm_info_node *node = m->private;
2282 struct drm_device *dev = node->minor->dev;
2283 struct drm_i915_private *dev_priv = dev->dev_private;
2284 struct drm_file *file;
2285 int ret;
2286
2287 ret = mutex_lock_interruptible(&dev->struct_mutex);
2288 if (ret)
2289 return ret;
2290
2291 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
2292 if (ret)
2293 goto unlock;
2294
2295 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2296 struct drm_i915_file_private *file_priv = file->driver_priv;
2297 struct task_struct *task;
2298
2299 rcu_read_lock();
2300 task = pid_task(file->pid, PIDTYPE_PID);
2301 seq_printf(m, "%s [%d]: %d boosts%s\n",
2302 task ? task->comm : "<unknown>",
2303 task ? task->pid : -1,
2304 file_priv->rps_boosts,
2305 list_empty(&file_priv->rps_boost) ? "" : ", active");
2306 rcu_read_unlock();
2307 }
2308 seq_printf(m, "Kernel boosts: %d\n", dev_priv->rps.boosts);
2309
2310 mutex_unlock(&dev_priv->rps.hw_lock);
2311unlock:
2312 mutex_unlock(&dev->struct_mutex);
2313
2314 return ret;
2315}
2316
63573eb7
BW		 2317static int i915_llc(struct seq_file *m, void *data)
2318{
9f25d007 2319 struct drm_info_node *node = m->private;
63573eb7
BW		 2320 struct drm_device *dev = node->minor->dev;
2321 struct drm_i915_private *dev_priv = dev->dev_private;
2322
2323 /* Size calculation for LLC is a bit of a pain. Ignore for now. */
2324 seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
2325 seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size);
2326
2327 return 0;
2328}
2329
e91fd8c6
RV		 2330static int i915_edp_psr_status(struct seq_file *m, void *data)
2331{
2332 struct drm_info_node *node = m->private;
2333 struct drm_device *dev = node->minor->dev;
2334 struct drm_i915_private *dev_priv = dev->dev_private;
a031d709 2335 u32 psrperf = 0;
a6cbdb8e
RV		 2336 u32 stat[3];
2337 enum pipe pipe;
a031d709 2338 bool enabled = false;
e91fd8c6 2339
3553a8ea
DL		 2340 if (!HAS_PSR(dev)) {
2341 seq_puts(m, "PSR not supported\n");
2342 return 0;
2343 }
2344
c8c8fb33
PZ		 2345 intel_runtime_pm_get(dev_priv);
2346
fa128fa6 2347 mutex_lock(&dev_priv->psr.lock);
a031d709
RV		 2348 seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
2349 seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
2807cf69 2350 seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
5755c78f 2351 seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
fa128fa6
DV		 2352 seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
2353 dev_priv->psr.busy_frontbuffer_bits);
2354 seq_printf(m, "Re-enable work scheduled: %s\n",
2355 yesno(work_busy(&dev_priv->psr.work.work)));
e91fd8c6 2356
3553a8ea
DL		 2357 if (HAS_DDI(dev))
2358 enabled = I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
2359 else {
2360 for_each_pipe(dev_priv, pipe) {
2361 stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
2362 VLV_EDP_PSR_CURR_STATE_MASK;
2363 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2364 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2365 enabled = true;
a6cbdb8e
RV		 2366 }
2367 }
2368 seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));
2369
2370 if (!HAS_DDI(dev))
2371 for_each_pipe(dev_priv, pipe) {
2372 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2373 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2374 seq_printf(m, " pipe %c", pipe_name(pipe));
2375 }
2376 seq_puts(m, "\n");
e91fd8c6 2377
a6cbdb8e 2378 /* CHV PSR has no kind of performance counter */
3553a8ea 2379 if (HAS_DDI(dev)) {
a031d709
RV		 2380 psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) &
2381 EDP_PSR_PERF_CNT_MASK;
a6cbdb8e
RV		 2382
2383 seq_printf(m, "Performance_Counter: %u\n", psrperf);
2384 }
fa128fa6 2385 mutex_unlock(&dev_priv->psr.lock);
e91fd8c6 2386
c8c8fb33 2387 intel_runtime_pm_put(dev_priv);
e91fd8c6
RV		 2388 return 0;
2389}
2390
d2e216d0
RV		 2391static int i915_sink_crc(struct seq_file *m, void *data)
2392{
2393 struct drm_info_node *node = m->private;
2394 struct drm_device *dev = node->minor->dev;
2395 struct intel_encoder *encoder;
2396 struct intel_connector *connector;
2397 struct intel_dp *intel_dp = NULL;
2398 int ret;
2399 u8 crc[6];
2400
2401 drm_modeset_lock_all(dev);
aca5e361 2402 for_each_intel_connector(dev, connector) {
d2e216d0
RV		 2403
2404 if (connector->base.dpms != DRM_MODE_DPMS_ON)
2405 continue;
2406
b6ae3c7c
PZ		 2407 if (!connector->base.encoder)
2408 continue;
2409
d2e216d0
RV		 2410 encoder = to_intel_encoder(connector->base.encoder);
2411 if (encoder->type != INTEL_OUTPUT_EDP)
2412 continue;
2413
2414 intel_dp = enc_to_intel_dp(&encoder->base);
2415
2416 ret = intel_dp_sink_crc(intel_dp, crc);
2417 if (ret)
2418 goto out;
2419
2420 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2421 crc[0], crc[1], crc[2],
2422 crc[3], crc[4], crc[5]);
2423 goto out;
2424 }
2425 ret = -ENODEV;
2426out:
2427 drm_modeset_unlock_all(dev);
2428 return ret;
2429}
2430
ec013e7f
JB		 2431static int i915_energy_uJ(struct seq_file *m, void *data)
2432{
2433 struct drm_info_node *node = m->private;
2434 struct drm_device *dev = node->minor->dev;
2435 struct drm_i915_private *dev_priv = dev->dev_private;
2436 u64 power;
2437 u32 units;
2438
2439 if (INTEL_INFO(dev)->gen < 6)
2440 return -ENODEV;
2441
36623ef8
PZ		 2442 intel_runtime_pm_get(dev_priv);
2443
ec013e7f
JB		 2444 rdmsrl(MSR_RAPL_POWER_UNIT, power);
2445 power = (power & 0x1f00) >> 8;
2446 units = 1000000 / (1 << power); /* convert to uJ */
2447 power = I915_READ(MCH_SECP_NRG_STTS);
2448 power *= units;
2449
36623ef8
PZ		 2450 intel_runtime_pm_put(dev_priv);
2451
ec013e7f 2452 seq_printf(m, "%llu", (long long unsigned)power);
371db66a
PZ		 2453
2454 return 0;
2455}
2456
2457static int i915_pc8_status(struct seq_file *m, void *unused)
2458{
9f25d007 2459 struct drm_info_node *node = m->private;
371db66a
PZ		 2460 struct drm_device *dev = node->minor->dev;
2461 struct drm_i915_private *dev_priv = dev->dev_private;
2462
85b8d5c2 2463 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
371db66a
PZ		 2464 seq_puts(m, "not supported\n");
2465 return 0;
2466 }
2467
86c4ec0d 2468 seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy));
371db66a 2469 seq_printf(m, "IRQs disabled: %s\n",
9df7575f 2470 yesno(!intel_irqs_enabled(dev_priv)));
371db66a 2471
ec013e7f
JB		 2472 return 0;
2473}
2474
1da51581
ID		 2475static const char *power_domain_str(enum intel_display_power_domain domain)
2476{
2477 switch (domain) {
2478 case POWER_DOMAIN_PIPE_A:
2479 return "PIPE_A";
2480 case POWER_DOMAIN_PIPE_B:
2481 return "PIPE_B";
2482 case POWER_DOMAIN_PIPE_C:
2483 return "PIPE_C";
2484 case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
2485 return "PIPE_A_PANEL_FITTER";
2486 case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
2487 return "PIPE_B_PANEL_FITTER";
2488 case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
2489 return "PIPE_C_PANEL_FITTER";
2490 case POWER_DOMAIN_TRANSCODER_A:
2491 return "TRANSCODER_A";
2492 case POWER_DOMAIN_TRANSCODER_B:
2493 return "TRANSCODER_B";
2494 case POWER_DOMAIN_TRANSCODER_C:
2495 return "TRANSCODER_C";
2496 case POWER_DOMAIN_TRANSCODER_EDP:
2497 return "TRANSCODER_EDP";
319be8ae
ID		 2498 case POWER_DOMAIN_PORT_DDI_A_2_LANES:
2499 return "PORT_DDI_A_2_LANES";
2500 case POWER_DOMAIN_PORT_DDI_A_4_LANES:
2501 return "PORT_DDI_A_4_LANES";
2502 case POWER_DOMAIN_PORT_DDI_B_2_LANES:
2503 return "PORT_DDI_B_2_LANES";
2504 case POWER_DOMAIN_PORT_DDI_B_4_LANES:
2505 return "PORT_DDI_B_4_LANES";
2506 case POWER_DOMAIN_PORT_DDI_C_2_LANES:
2507 return "PORT_DDI_C_2_LANES";
2508 case POWER_DOMAIN_PORT_DDI_C_4_LANES:
2509 return "PORT_DDI_C_4_LANES";
2510 case POWER_DOMAIN_PORT_DDI_D_2_LANES:
2511 return "PORT_DDI_D_2_LANES";
2512 case POWER_DOMAIN_PORT_DDI_D_4_LANES:
2513 return "PORT_DDI_D_4_LANES";
2514 case POWER_DOMAIN_PORT_DSI:
2515 return "PORT_DSI";
2516 case POWER_DOMAIN_PORT_CRT:
2517 return "PORT_CRT";
2518 case POWER_DOMAIN_PORT_OTHER:
2519 return "PORT_OTHER";
1da51581
ID		 2520 case POWER_DOMAIN_VGA:
2521 return "VGA";
2522 case POWER_DOMAIN_AUDIO:
2523 return "AUDIO";
bd2bb1b9
PZ		 2524 case POWER_DOMAIN_PLLS:
2525 return "PLLS";
1407121a
S		 2526 case POWER_DOMAIN_AUX_A:
2527 return "AUX_A";
2528 case POWER_DOMAIN_AUX_B:
2529 return "AUX_B";
2530 case POWER_DOMAIN_AUX_C:
2531 return "AUX_C";
2532 case POWER_DOMAIN_AUX_D:
2533 return "AUX_D";
1da51581
ID		 2534 case POWER_DOMAIN_INIT:
2535 return "INIT";
2536 default:
5f77eeb0 2537 MISSING_CASE(domain);
1da51581
ID		 2538 return "?";
2539 }
2540}
2541
2542static int i915_power_domain_info(struct seq_file *m, void *unused)
2543{
9f25d007 2544 struct drm_info_node *node = m->private;
1da51581
ID		 2545 struct drm_device *dev = node->minor->dev;
2546 struct drm_i915_private *dev_priv = dev->dev_private;
2547 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2548 int i;
2549
2550 mutex_lock(&power_domains->lock);
2551
2552 seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2553 for (i = 0; i < power_domains->power_well_count; i++) {
2554 struct i915_power_well *power_well;
2555 enum intel_display_power_domain power_domain;
2556
2557 power_well = &power_domains->power_wells[i];
2558 seq_printf(m, "%-25s %d\n", power_well->name,
2559 power_well->count);
2560
2561 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
2562 power_domain++) {
2563 if (!(BIT(power_domain) & power_well->domains))
2564 continue;
2565
2566 seq_printf(m, " %-23s %d\n",
2567 power_domain_str(power_domain),
2568 power_domains->domain_use_count[power_domain]);
2569 }
2570 }
2571
2572 mutex_unlock(&power_domains->lock);
2573
2574 return 0;
2575}
2576
53f5e3ca
JB		 2577static void intel_seq_print_mode(struct seq_file *m, int tabs,
2578 struct drm_display_mode *mode)
2579{
2580 int i;
2581
2582 for (i = 0; i < tabs; i++)
2583 seq_putc(m, '\t');
2584
2585 seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2586 mode->base.id, mode->name,
2587 mode->vrefresh, mode->clock,
2588 mode->hdisplay, mode->hsync_start,
2589 mode->hsync_end, mode->htotal,
2590 mode->vdisplay, mode->vsync_start,
2591 mode->vsync_end, mode->vtotal,
2592 mode->type, mode->flags);
2593}
2594
2595static void intel_encoder_info(struct seq_file *m,
2596 struct intel_crtc *intel_crtc,
2597 struct intel_encoder *intel_encoder)
2598{
9f25d007 2599 struct drm_info_node *node = m->private;
53f5e3ca
JB		 2600 struct drm_device *dev = node->minor->dev;
2601 struct drm_crtc *crtc = &intel_crtc->base;
2602 struct intel_connector *intel_connector;
2603 struct drm_encoder *encoder;
2604
2605 encoder = &intel_encoder->base;
2606 seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
8e329a03 2607 encoder->base.id, encoder->name);
53f5e3ca
JB		 2608 for_each_connector_on_encoder(dev, encoder, intel_connector) {
2609 struct drm_connector *connector = &intel_connector->base;
2610 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2611 connector->base.id,
c23cc417 2612 connector->name,
53f5e3ca
JB		 2613 drm_get_connector_status_name(connector->status));
2614 if (connector->status == connector_status_connected) {
2615 struct drm_display_mode *mode = &crtc->mode;
2616 seq_printf(m, ", mode:\n");
2617 intel_seq_print_mode(m, 2, mode);
2618 } else {
2619 seq_putc(m, '\n');
2620 }
2621 }
2622}
2623
2624static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2625{
9f25d007 2626 struct drm_info_node *node = m->private;
53f5e3ca
JB		 2627 struct drm_device *dev = node->minor->dev;
2628 struct drm_crtc *crtc = &intel_crtc->base;
2629 struct intel_encoder *intel_encoder;
2630
5aa8a937
MR		 2631 if (crtc->primary->fb)
2632 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2633 crtc->primary->fb->base.id, crtc->x, crtc->y,
2634 crtc->primary->fb->width, crtc->primary->fb->height);
2635 else
2636 seq_puts(m, "\tprimary plane disabled\n");
53f5e3ca
JB		 2637 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2638 intel_encoder_info(m, intel_crtc, intel_encoder);
2639}
2640
2641static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2642{
2643 struct drm_display_mode *mode = panel->fixed_mode;
2644
2645 seq_printf(m, "\tfixed mode:\n");
2646 intel_seq_print_mode(m, 2, mode);
2647}
2648
2649static void intel_dp_info(struct seq_file *m,
2650 struct intel_connector *intel_connector)
2651{
2652 struct intel_encoder *intel_encoder = intel_connector->encoder;
2653 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2654
2655 seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2656 seq_printf(m, "\taudio support: %s\n", intel_dp->has_audio ? "yes" :
2657 "no");
2658 if (intel_encoder->type == INTEL_OUTPUT_EDP)
2659 intel_panel_info(m, &intel_connector->panel);
2660}
2661
2662static void intel_hdmi_info(struct seq_file *m,
2663 struct intel_connector *intel_connector)
2664{
2665 struct intel_encoder *intel_encoder = intel_connector->encoder;
2666 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2667
2668 seq_printf(m, "\taudio support: %s\n", intel_hdmi->has_audio ? "yes" :
2669 "no");
2670}
2671
2672static void intel_lvds_info(struct seq_file *m,
2673 struct intel_connector *intel_connector)
2674{
2675 intel_panel_info(m, &intel_connector->panel);
2676}
2677
2678static void intel_connector_info(struct seq_file *m,
2679 struct drm_connector *connector)
2680{
2681 struct intel_connector *intel_connector = to_intel_connector(connector);
2682 struct intel_encoder *intel_encoder = intel_connector->encoder;
f103fc7d 2683 struct drm_display_mode *mode;
53f5e3ca
JB		 2684
2685 seq_printf(m, "connector %d: type %s, status: %s\n",
c23cc417 2686 connector->base.id, connector->name,
53f5e3ca
JB		 2687 drm_get_connector_status_name(connector->status));
2688 if (connector->status == connector_status_connected) {
2689 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2690 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2691 connector->display_info.width_mm,
2692 connector->display_info.height_mm);
2693 seq_printf(m, "\tsubpixel order: %s\n",
2694 drm_get_subpixel_order_name(connector->display_info.subpixel_order));
2695 seq_printf(m, "\tCEA rev: %d\n",
2696 connector->display_info.cea_rev);
2697 }
36cd7444
DA		 2698 if (intel_encoder) {
2699 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2700 intel_encoder->type == INTEL_OUTPUT_EDP)
2701 intel_dp_info(m, intel_connector);
2702 else if (intel_encoder->type == INTEL_OUTPUT_HDMI)
2703 intel_hdmi_info(m, intel_connector);
2704 else if (intel_encoder->type == INTEL_OUTPUT_LVDS)
2705 intel_lvds_info(m, intel_connector);
2706 }
53f5e3ca 2707
f103fc7d
JB		 2708 seq_printf(m, "\tmodes:\n");
2709 list_for_each_entry(mode, &connector->modes, head)
2710 intel_seq_print_mode(m, 2, mode);
53f5e3ca
JB		 2711}
2712
065f2ec2
CW		 2713static bool cursor_active(struct drm_device *dev, int pipe)
2714{
2715 struct drm_i915_private *dev_priv = dev->dev_private;
2716 u32 state;
2717
2718 if (IS_845G(dev) || IS_I865G(dev))
2719 state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
065f2ec2 2720 else
5efb3e28 2721 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
065f2ec2
CW		 2722
2723 return state;
2724}
2725
2726static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y)
2727{
2728 struct drm_i915_private *dev_priv = dev->dev_private;
2729 u32 pos;
2730
5efb3e28 2731 pos = I915_READ(CURPOS(pipe));
065f2ec2
CW		 2732
2733 *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
2734 if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
2735 *x = -*x;
2736
2737 *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
2738 if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
2739 *y = -*y;
2740
2741 return cursor_active(dev, pipe);
2742}
2743
53f5e3ca
JB		 2744static int i915_display_info(struct seq_file *m, void *unused)
2745{
9f25d007 2746 struct drm_info_node *node = m->private;
53f5e3ca 2747 struct drm_device *dev = node->minor->dev;
b0e5ddf3 2748 struct drm_i915_private *dev_priv = dev->dev_private;
065f2ec2 2749 struct intel_crtc *crtc;
53f5e3ca
JB		 2750 struct drm_connector *connector;
2751
b0e5ddf3 2752 intel_runtime_pm_get(dev_priv);
53f5e3ca
JB		 2753 drm_modeset_lock_all(dev);
2754 seq_printf(m, "CRTC info\n");
2755 seq_printf(m, "---------\n");
d3fcc808 2756 for_each_intel_crtc(dev, crtc) {
065f2ec2
CW		 2757 bool active;
2758 int x, y;
53f5e3ca 2759
57127efa 2760 seq_printf(m, "CRTC %d: pipe: %c, active=%s (size=%dx%d)\n",
065f2ec2 2761 crtc->base.base.id, pipe_name(crtc->pipe),
6e3c9717
ACO		 2762 yesno(crtc->active), crtc->config->pipe_src_w,
2763 crtc->config->pipe_src_h);
a23dc658 2764 if (crtc->active) {
065f2ec2
CW		 2765 intel_crtc_info(m, crtc);
2766
a23dc658 2767 active = cursor_position(dev, crtc->pipe, &x, &y);
57127efa 2768 seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
4b0e333e 2769 yesno(crtc->cursor_base),
3dd512fb
MR		 2770 x, y, crtc->base.cursor->state->crtc_w,
2771 crtc->base.cursor->state->crtc_h,
57127efa 2772 crtc->cursor_addr, yesno(active));
a23dc658 2773 }
cace841c
DV		 2774
2775 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
2776 yesno(!crtc->cpu_fifo_underrun_disabled),
2777 yesno(!crtc->pch_fifo_underrun_disabled));
53f5e3ca
JB		 2778 }
2779
2780 seq_printf(m, "\n");
2781 seq_printf(m, "Connector info\n");
2782 seq_printf(m, "--------------\n");
2783 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2784 intel_connector_info(m, connector);
2785 }
2786 drm_modeset_unlock_all(dev);
b0e5ddf3 2787 intel_runtime_pm_put(dev_priv);
53f5e3ca
JB		 2788
2789 return 0;
2790}
2791
e04934cf
BW		 2792static int i915_semaphore_status(struct seq_file *m, void *unused)
2793{
2794 struct drm_info_node *node = (struct drm_info_node *) m->private;
2795 struct drm_device *dev = node->minor->dev;
2796 struct drm_i915_private *dev_priv = dev->dev_private;
2797 struct intel_engine_cs *ring;
2798 int num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
2799 int i, j, ret;
2800
2801 if (!i915_semaphore_is_enabled(dev)) {
2802 seq_puts(m, "Semaphores are disabled\n");
2803 return 0;
2804 }
2805
2806 ret = mutex_lock_interruptible(&dev->struct_mutex);
2807 if (ret)
2808 return ret;
03872064 2809 intel_runtime_pm_get(dev_priv);
e04934cf
BW		 2810
2811 if (IS_BROADWELL(dev)) {
2812 struct page *page;
2813 uint64_t *seqno;
2814
2815 page = i915_gem_object_get_page(dev_priv->semaphore_obj, 0);
2816
2817 seqno = (uint64_t *)kmap_atomic(page);
2818 for_each_ring(ring, dev_priv, i) {
2819 uint64_t offset;
2820
2821 seq_printf(m, "%s\n", ring->name);
2822
2823 seq_puts(m, " Last signal:");
2824 for (j = 0; j < num_rings; j++) {
2825 offset = i * I915_NUM_RINGS + j;
2826 seq_printf(m, "0x%08llx (0x%02llx) ",
2827 seqno[offset], offset * 8);
2828 }
2829 seq_putc(m, '\n');
2830
2831 seq_puts(m, " Last wait: ");
2832 for (j = 0; j < num_rings; j++) {
2833 offset = i + (j * I915_NUM_RINGS);
2834 seq_printf(m, "0x%08llx (0x%02llx) ",
2835 seqno[offset], offset * 8);
2836 }
2837 seq_putc(m, '\n');
2838
2839 }
2840 kunmap_atomic(seqno);
2841 } else {
2842 seq_puts(m, " Last signal:");
2843 for_each_ring(ring, dev_priv, i)
2844 for (j = 0; j < num_rings; j++)
2845 seq_printf(m, "0x%08x\n",
2846 I915_READ(ring->semaphore.mbox.signal[j]));
2847 seq_putc(m, '\n');
2848 }
2849
2850 seq_puts(m, "\nSync seqno:\n");
2851 for_each_ring(ring, dev_priv, i) {
2852 for (j = 0; j < num_rings; j++) {
2853 seq_printf(m, " 0x%08x ", ring->semaphore.sync_seqno[j]);
2854 }
2855 seq_putc(m, '\n');
2856 }
2857 seq_putc(m, '\n');
2858
03872064 2859 intel_runtime_pm_put(dev_priv);
e04934cf
BW		 2860 mutex_unlock(&dev->struct_mutex);
2861 return 0;
2862}
2863
728e29d7
DV		 2864static int i915_shared_dplls_info(struct seq_file *m, void *unused)
2865{
2866 struct drm_info_node *node = (struct drm_info_node *) m->private;
2867 struct drm_device *dev = node->minor->dev;
2868 struct drm_i915_private *dev_priv = dev->dev_private;
2869 int i;
2870
2871 drm_modeset_lock_all(dev);
2872 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
2873 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
2874
2875 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
1e6f2ddc 2876 seq_printf(m, " crtc_mask: 0x%08x, active: %d, on: %s\n",
3e369b76 2877 pll->config.crtc_mask, pll->active, yesno(pll->on));
728e29d7 2878 seq_printf(m, " tracked hardware state:\n");
3e369b76
ACO		 2879 seq_printf(m, " dpll: 0x%08x\n", pll->config.hw_state.dpll);
2880 seq_printf(m, " dpll_md: 0x%08x\n",
2881 pll->config.hw_state.dpll_md);
2882 seq_printf(m, " fp0: 0x%08x\n", pll->config.hw_state.fp0);
2883 seq_printf(m, " fp1: 0x%08x\n", pll->config.hw_state.fp1);
2884 seq_printf(m, " wrpll: 0x%08x\n", pll->config.hw_state.wrpll);
728e29d7
DV		 2885 }
2886 drm_modeset_unlock_all(dev);
2887
2888 return 0;
2889}
2890
1ed1ef9d 2891static int i915_wa_registers(struct seq_file *m, void *unused)
888b5995
AS		 2892{
2893 int i;
2894 int ret;
2895 struct drm_info_node *node = (struct drm_info_node *) m->private;
2896 struct drm_device *dev = node->minor->dev;
2897 struct drm_i915_private *dev_priv = dev->dev_private;
2898
888b5995
AS		 2899 ret = mutex_lock_interruptible(&dev->struct_mutex);
2900 if (ret)
2901 return ret;
2902
2903 intel_runtime_pm_get(dev_priv);
2904
7225342a
MK		 2905 seq_printf(m, "Workarounds applied: %d\n", dev_priv->workarounds.count);
2906 for (i = 0; i < dev_priv->workarounds.count; ++i) {
2fa60f6d
MK		 2907 u32 addr, mask, value, read;
2908 bool ok;
888b5995 2909
7225342a
MK		 2910 addr = dev_priv->workarounds.reg[i].addr;
2911 mask = dev_priv->workarounds.reg[i].mask;
2fa60f6d
MK		 2912 value = dev_priv->workarounds.reg[i].value;
2913 read = I915_READ(addr);
2914 ok = (value & mask) == (read & mask);
2915 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
2916 addr, value, mask, read, ok ? "OK" : "FAIL");
888b5995
AS		 2917 }
2918
2919 intel_runtime_pm_put(dev_priv);
2920 mutex_unlock(&dev->struct_mutex);
2921
2922 return 0;
2923}
2924
c5511e44
DL		 2925static int i915_ddb_info(struct seq_file *m, void *unused)
2926{
2927 struct drm_info_node *node = m->private;
2928 struct drm_device *dev = node->minor->dev;
2929 struct drm_i915_private *dev_priv = dev->dev_private;
2930 struct skl_ddb_allocation *ddb;
2931 struct skl_ddb_entry *entry;
2932 enum pipe pipe;
2933 int plane;
2934
2fcffe19
DL		 2935 if (INTEL_INFO(dev)->gen < 9)
2936 return 0;
2937
c5511e44
DL		 2938 drm_modeset_lock_all(dev);
2939
2940 ddb = &dev_priv->wm.skl_hw.ddb;
2941
2942 seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
2943
2944 for_each_pipe(dev_priv, pipe) {
2945 seq_printf(m, "Pipe %c\n", pipe_name(pipe));
2946
dd740780 2947 for_each_plane(dev_priv, pipe, plane) {
c5511e44
DL		 2948 entry = &ddb->plane[pipe][plane];
2949 seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane + 1,
2950 entry->start, entry->end,
2951 skl_ddb_entry_size(entry));
2952 }
2953
2954 entry = &ddb->cursor[pipe];
2955 seq_printf(m, " %-13s%8u%8u%8u\n", "Cursor", entry->start,
2956 entry->end, skl_ddb_entry_size(entry));
2957 }
2958
2959 drm_modeset_unlock_all(dev);
2960
2961 return 0;
2962}
2963
a54746e3
VK		 2964static void drrs_status_per_crtc(struct seq_file *m,
2965 struct drm_device *dev, struct intel_crtc *intel_crtc)
2966{
2967 struct intel_encoder *intel_encoder;
2968 struct drm_i915_private *dev_priv = dev->dev_private;
2969 struct i915_drrs *drrs = &dev_priv->drrs;
2970 int vrefresh = 0;
2971
2972 for_each_encoder_on_crtc(dev, &intel_crtc->base, intel_encoder) {
2973 /* Encoder connected on this CRTC */
2974 switch (intel_encoder->type) {
2975 case INTEL_OUTPUT_EDP:
2976 seq_puts(m, "eDP:\n");
2977 break;
2978 case INTEL_OUTPUT_DSI:
2979 seq_puts(m, "DSI:\n");
2980 break;
2981 case INTEL_OUTPUT_HDMI:
2982 seq_puts(m, "HDMI:\n");
2983 break;
2984 case INTEL_OUTPUT_DISPLAYPORT:
2985 seq_puts(m, "DP:\n");
2986 break;
2987 default:
2988 seq_printf(m, "Other encoder (id=%d).\n",
2989 intel_encoder->type);
2990 return;
2991 }
2992 }
2993
2994 if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT)
2995 seq_puts(m, "\tVBT: DRRS_type: Static");
2996 else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT)
2997 seq_puts(m, "\tVBT: DRRS_type: Seamless");
2998 else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED)
2999 seq_puts(m, "\tVBT: DRRS_type: None");
3000 else
3001 seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value");
3002
3003 seq_puts(m, "\n\n");
3004
3005 if (intel_crtc->config->has_drrs) {
3006 struct intel_panel *panel;
3007
3008 mutex_lock(&drrs->mutex);
3009 /* DRRS Supported */
3010 seq_puts(m, "\tDRRS Supported: Yes\n");
3011
3012 /* disable_drrs() will make drrs->dp NULL */
3013 if (!drrs->dp) {
3014 seq_puts(m, "Idleness DRRS: Disabled");
3015 mutex_unlock(&drrs->mutex);
3016 return;
3017 }
3018
3019 panel = &drrs->dp->attached_connector->panel;
3020 seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X",
3021 drrs->busy_frontbuffer_bits);
3022
3023 seq_puts(m, "\n\t\t");
3024 if (drrs->refresh_rate_type == DRRS_HIGH_RR) {
3025 seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n");
3026 vrefresh = panel->fixed_mode->vrefresh;
3027 } else if (drrs->refresh_rate_type == DRRS_LOW_RR) {
3028 seq_puts(m, "DRRS_State: DRRS_LOW_RR\n");
3029 vrefresh = panel->downclock_mode->vrefresh;
3030 } else {
3031 seq_printf(m, "DRRS_State: Unknown(%d)\n",
3032 drrs->refresh_rate_type);
3033 mutex_unlock(&drrs->mutex);
3034 return;
3035 }
3036 seq_printf(m, "\t\tVrefresh: %d", vrefresh);
3037
3038 seq_puts(m, "\n\t\t");
3039 mutex_unlock(&drrs->mutex);
3040 } else {
3041 /* DRRS not supported. Print the VBT parameter*/
3042 seq_puts(m, "\tDRRS Supported : No");
3043 }
3044 seq_puts(m, "\n");
3045}
3046
3047static int i915_drrs_status(struct seq_file *m, void *unused)
3048{
3049 struct drm_info_node *node = m->private;
3050 struct drm_device *dev = node->minor->dev;
3051 struct intel_crtc *intel_crtc;
3052 int active_crtc_cnt = 0;
3053
3054 for_each_intel_crtc(dev, intel_crtc) {
3055 drm_modeset_lock(&intel_crtc->base.mutex, NULL);
3056
3057 if (intel_crtc->active) {
3058 active_crtc_cnt++;
3059 seq_printf(m, "\nCRTC %d: ", active_crtc_cnt);
3060
3061 drrs_status_per_crtc(m, dev, intel_crtc);
3062 }
3063
3064 drm_modeset_unlock(&intel_crtc->base.mutex);
3065 }
3066
3067 if (!active_crtc_cnt)
3068 seq_puts(m, "No active crtc found\n");
3069
3070 return 0;
3071}
3072
07144428
DL		 3073struct pipe_crc_info {
3074 const char *name;
3075 struct drm_device *dev;
3076 enum pipe pipe;
3077};
3078
11bed958
DA		 3079static int i915_dp_mst_info(struct seq_file *m, void *unused)
3080{
3081 struct drm_info_node *node = (struct drm_info_node *) m->private;
3082 struct drm_device *dev = node->minor->dev;
3083 struct drm_encoder *encoder;
3084 struct intel_encoder *intel_encoder;
3085 struct intel_digital_port *intel_dig_port;
3086 drm_modeset_lock_all(dev);
3087 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3088 intel_encoder = to_intel_encoder(encoder);
3089 if (intel_encoder->type != INTEL_OUTPUT_DISPLAYPORT)
3090 continue;
3091 intel_dig_port = enc_to_dig_port(encoder);
3092 if (!intel_dig_port->dp.can_mst)
3093 continue;
3094
3095 drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr);
3096 }
3097 drm_modeset_unlock_all(dev);
3098 return 0;
3099}
3100
07144428
DL		 3101static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
3102{
be5c7a90
DL		 3103 struct pipe_crc_info *info = inode->i_private;
3104 struct drm_i915_private *dev_priv = info->dev->dev_private;
3105 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3106
7eb1c496
DV		 3107 if (info->pipe >= INTEL_INFO(info->dev)->num_pipes)
3108 return -ENODEV;
3109
d538bbdf
DL		 3110 spin_lock_irq(&pipe_crc->lock);
3111
3112 if (pipe_crc->opened) {
3113 spin_unlock_irq(&pipe_crc->lock);
be5c7a90
DL		 3114 return -EBUSY; /* already open */
3115 }
3116
d538bbdf 3117 pipe_crc->opened = true;
07144428
DL		 3118 filep->private_data = inode->i_private;
3119
d538bbdf
DL		 3120 spin_unlock_irq(&pipe_crc->lock);
3121
07144428
DL		 3122 return 0;
3123}
3124
3125static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
3126{
be5c7a90
DL		 3127 struct pipe_crc_info *info = inode->i_private;
3128 struct drm_i915_private *dev_priv = info->dev->dev_private;
3129 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3130
d538bbdf
DL		 3131 spin_lock_irq(&pipe_crc->lock);
3132 pipe_crc->opened = false;
3133 spin_unlock_irq(&pipe_crc->lock);
be5c7a90 3134
07144428
DL		 3135 return 0;
3136}
3137
3138/* (6 fields, 8 chars each, space separated (5) + '\n') */
3139#define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
3140/* account for \'0' */
3141#define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1)
3142
3143static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
8bf1e9f1 3144{
d538bbdf
DL		 3145 assert_spin_locked(&pipe_crc->lock);
3146 return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3147 INTEL_PIPE_CRC_ENTRIES_NR);
07144428
DL		 3148}
3149
3150static ssize_t
3151i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
3152 loff_t *pos)
3153{
3154 struct pipe_crc_info *info = filep->private_data;
3155 struct drm_device *dev = info->dev;
3156 struct drm_i915_private *dev_priv = dev->dev_private;
3157 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3158 char buf[PIPE_CRC_BUFFER_LEN];
9ad6d99f 3159 int n_entries;
07144428
DL		 3160 ssize_t bytes_read;
3161
3162 /*
3163 * Don't allow user space to provide buffers not big enough to hold
3164 * a line of data.
3165 */
3166 if (count < PIPE_CRC_LINE_LEN)
3167 return -EINVAL;
3168
3169 if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
8bf1e9f1 3170 return 0;
07144428
DL		 3171
3172 /* nothing to read */
d538bbdf 3173 spin_lock_irq(&pipe_crc->lock);
07144428 3174 while (pipe_crc_data_count(pipe_crc) == 0) {
d538bbdf
DL		 3175 int ret;
3176
3177 if (filep->f_flags & O_NONBLOCK) {
3178 spin_unlock_irq(&pipe_crc->lock);
07144428 3179 return -EAGAIN;
d538bbdf 3180 }
07144428 3181
d538bbdf
DL		 3182 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
3183 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
3184 if (ret) {
3185 spin_unlock_irq(&pipe_crc->lock);
3186 return ret;
3187 }
8bf1e9f1
SH		 3188 }
3189
07144428 3190 /* We now have one or more entries to read */
9ad6d99f 3191 n_entries = count / PIPE_CRC_LINE_LEN;
d538bbdf 3192
07144428 3193 bytes_read = 0;
9ad6d99f
VS		 3194 while (n_entries > 0) {
3195 struct intel_pipe_crc_entry *entry =
3196 &pipe_crc->entries[pipe_crc->tail];
07144428 3197 int ret;
8bf1e9f1 3198
9ad6d99f
VS		 3199 if (CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3200 INTEL_PIPE_CRC_ENTRIES_NR) < 1)
3201 break;
3202
3203 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
3204 pipe_crc->tail = (pipe_crc->tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
3205
07144428
DL		 3206 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
3207 "%8u %8x %8x %8x %8x %8x\n",
3208 entry->frame, entry->crc[0],
3209 entry->crc[1], entry->crc[2],
3210 entry->crc[3], entry->crc[4]);
3211
9ad6d99f
VS		 3212 spin_unlock_irq(&pipe_crc->lock);
3213
3214 ret = copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN);
07144428
DL		 3215 if (ret == PIPE_CRC_LINE_LEN)
3216 return -EFAULT;
b2c88f5b 3217
9ad6d99f
VS		 3218 user_buf += PIPE_CRC_LINE_LEN;
3219 n_entries--;
3220
3221 spin_lock_irq(&pipe_crc->lock);
3222 }
8bf1e9f1 3223
d538bbdf
DL		 3224 spin_unlock_irq(&pipe_crc->lock);
3225
07144428
DL		 3226 return bytes_read;
3227}
3228
3229static const struct file_operations i915_pipe_crc_fops = {
3230 .owner = THIS_MODULE,
3231 .open = i915_pipe_crc_open,
3232 .read = i915_pipe_crc_read,
3233 .release = i915_pipe_crc_release,
3234};
3235
3236static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
3237 {
3238 .name = "i915_pipe_A_crc",
3239 .pipe = PIPE_A,
3240 },
3241 {
3242 .name = "i915_pipe_B_crc",
3243 .pipe = PIPE_B,
3244 },
3245 {
3246 .name = "i915_pipe_C_crc",
3247 .pipe = PIPE_C,
3248 },
3249};
3250
3251static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
3252 enum pipe pipe)
3253{
3254 struct drm_device *dev = minor->dev;
3255 struct dentry *ent;
3256 struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
3257
3258 info->dev = dev;
3259 ent = debugfs_create_file(info->name, S_IRUGO, root, info,
3260 &i915_pipe_crc_fops);
f3c5fe97
WY		 3261 if (!ent)
3262 return -ENOMEM;
07144428
DL		 3263
3264 return drm_add_fake_info_node(minor, ent, info);
8bf1e9f1
SH		 3265}
3266
e8dfcf78 3267static const char * const pipe_crc_sources[] = {
926321d5
DV		 3268 "none",
3269 "plane1",
3270 "plane2",
3271 "pf",
5b3a856b 3272 "pipe",
3d099a05
DV		 3273 "TV",
3274 "DP-B",
3275 "DP-C",
3276 "DP-D",
46a19188 3277 "auto",
926321d5
DV		 3278};
3279
3280static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
3281{
3282 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
3283 return pipe_crc_sources[source];
3284}
3285
bd9db02f 3286static int display_crc_ctl_show(struct seq_file *m, void *data)
926321d5
DV		 3287{
3288 struct drm_device *dev = m->private;
3289 struct drm_i915_private *dev_priv = dev->dev_private;
3290 int i;
3291
3292 for (i = 0; i < I915_MAX_PIPES; i++)
3293 seq_printf(m, "%c %s\n", pipe_name(i),
3294 pipe_crc_source_name(dev_priv->pipe_crc[i].source));
3295
3296 return 0;
3297}
3298
bd9db02f 3299static int display_crc_ctl_open(struct inode *inode, struct file *file)
926321d5
DV		 3300{
3301 struct drm_device *dev = inode->i_private;
3302
bd9db02f 3303 return single_open(file, display_crc_ctl_show, dev);
926321d5
DV		 3304}
3305
46a19188 3306static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
52f843f6
DV		 3307 uint32_t *val)
3308{
46a19188
DV		 3309 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3310 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3311
3312 switch (*source) {
52f843f6
DV		 3313 case INTEL_PIPE_CRC_SOURCE_PIPE:
3314 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
3315 break;
3316 case INTEL_PIPE_CRC_SOURCE_NONE:
3317 *val = 0;
3318 break;
3319 default:
3320 return -EINVAL;
3321 }
3322
3323 return 0;
3324}
3325
46a19188
DV		 3326static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe,
3327 enum intel_pipe_crc_source *source)
3328{
3329 struct intel_encoder *encoder;
3330 struct intel_crtc *crtc;
26756809 3331 struct intel_digital_port *dig_port;
46a19188
DV		 3332 int ret = 0;
3333
3334 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3335
6e9f798d 3336 drm_modeset_lock_all(dev);
b2784e15 3337 for_each_intel_encoder(dev, encoder) {
46a19188
DV		 3338 if (!encoder->base.crtc)
3339 continue;
3340
3341 crtc = to_intel_crtc(encoder->base.crtc);
3342
3343 if (crtc->pipe != pipe)
3344 continue;
3345
3346 switch (encoder->type) {
3347 case INTEL_OUTPUT_TVOUT:
3348 *source = INTEL_PIPE_CRC_SOURCE_TV;
3349 break;
3350 case INTEL_OUTPUT_DISPLAYPORT:
3351 case INTEL_OUTPUT_EDP:
26756809
DV		 3352 dig_port = enc_to_dig_port(&encoder->base);
3353 switch (dig_port->port) {
3354 case PORT_B:
3355 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
3356 break;
3357 case PORT_C:
3358 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
3359 break;
3360 case PORT_D:
3361 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
3362 break;
3363 default:
3364 WARN(1, "nonexisting DP port %c\n",
3365 port_name(dig_port->port));
3366 break;
3367 }
46a19188 3368 break;
6847d71b
PZ		 3369 default:
3370 break;
46a19188
DV		 3371 }
3372 }
6e9f798d 3373 drm_modeset_unlock_all(dev);
46a19188
DV		 3374
3375 return ret;
3376}
3377
3378static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
3379 enum pipe pipe,
3380 enum intel_pipe_crc_source *source,
7ac0129b
DV		 3381 uint32_t *val)
3382{
8d2f24ca
DV		 3383 struct drm_i915_private *dev_priv = dev->dev_private;
3384 bool need_stable_symbols = false;
3385
46a19188
DV		 3386 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3387 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3388 if (ret)
3389 return ret;
3390 }
3391
3392 switch (*source) {
7ac0129b
DV		 3393 case INTEL_PIPE_CRC_SOURCE_PIPE:
3394 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
3395 break;
3396 case INTEL_PIPE_CRC_SOURCE_DP_B:
3397 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
8d2f24ca 3398 need_stable_symbols = true;
7ac0129b
DV		 3399 break;
3400 case INTEL_PIPE_CRC_SOURCE_DP_C:
3401 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
8d2f24ca 3402 need_stable_symbols = true;
7ac0129b 3403 break;
2be57922
VS		 3404 case INTEL_PIPE_CRC_SOURCE_DP_D:
3405 if (!IS_CHERRYVIEW(dev))
3406 return -EINVAL;
3407 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV;
3408 need_stable_symbols = true;
3409 break;
7ac0129b
DV		 3410 case INTEL_PIPE_CRC_SOURCE_NONE:
3411 *val = 0;
3412 break;
3413 default:
3414 return -EINVAL;
3415 }
3416
8d2f24ca
DV		 3417 /*
3418 * When the pipe CRC tap point is after the transcoders we need
3419 * to tweak symbol-level features to produce a deterministic series of
3420 * symbols for a given frame. We need to reset those features only once
3421 * a frame (instead of every nth symbol):
3422 * - DC-balance: used to ensure a better clock recovery from the data
3423 * link (SDVO)
3424 * - DisplayPort scrambling: used for EMI reduction
3425 */
3426 if (need_stable_symbols) {
3427 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3428
8d2f24ca 3429 tmp |= DC_BALANCE_RESET_VLV;
eb736679
VS		 3430 switch (pipe) {
3431 case PIPE_A:
8d2f24ca 3432 tmp |= PIPE_A_SCRAMBLE_RESET;
eb736679
VS		 3433 break;
3434 case PIPE_B:
8d2f24ca 3435 tmp |= PIPE_B_SCRAMBLE_RESET;
eb736679
VS		 3436 break;
3437 case PIPE_C:
3438 tmp |= PIPE_C_SCRAMBLE_RESET;
3439 break;
3440 default:
3441 return -EINVAL;
3442 }
8d2f24ca
DV		 3443 I915_WRITE(PORT_DFT2_G4X, tmp);
3444 }
3445
7ac0129b
DV		 3446 return 0;
3447}
3448
4b79ebf7 3449static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
46a19188
DV		 3450 enum pipe pipe,
3451 enum intel_pipe_crc_source *source,
4b79ebf7
DV		 3452 uint32_t *val)
3453{
84093603
DV		 3454 struct drm_i915_private *dev_priv = dev->dev_private;
3455 bool need_stable_symbols = false;
3456
46a19188
DV		 3457 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3458 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3459 if (ret)
3460 return ret;
3461 }
3462
3463 switch (*source) {
4b79ebf7
DV		 3464 case INTEL_PIPE_CRC_SOURCE_PIPE:
3465 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
3466 break;
3467 case INTEL_PIPE_CRC_SOURCE_TV:
3468 if (!SUPPORTS_TV(dev))
3469 return -EINVAL;
3470 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
3471 break;
3472 case INTEL_PIPE_CRC_SOURCE_DP_B:
3473 if (!IS_G4X(dev))
3474 return -EINVAL;
3475 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
84093603 3476 need_stable_symbols = true;
4b79ebf7
DV		 3477 break;
3478 case INTEL_PIPE_CRC_SOURCE_DP_C:
3479 if (!IS_G4X(dev))
3480 return -EINVAL;
3481 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
84093603 3482 need_stable_symbols = true;
4b79ebf7
DV		 3483 break;
3484 case INTEL_PIPE_CRC_SOURCE_DP_D:
3485 if (!IS_G4X(dev))
3486 return -EINVAL;
3487 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
84093603 3488 need_stable_symbols = true;
4b79ebf7
DV		 3489 break;
3490 case INTEL_PIPE_CRC_SOURCE_NONE:
3491 *val = 0;
3492 break;
3493 default:
3494 return -EINVAL;
3495 }
3496
84093603
DV		 3497 /*
3498 * When the pipe CRC tap point is after the transcoders we need
3499 * to tweak symbol-level features to produce a deterministic series of
3500 * symbols for a given frame. We need to reset those features only once
3501 * a frame (instead of every nth symbol):
3502 * - DC-balance: used to ensure a better clock recovery from the data
3503 * link (SDVO)
3504 * - DisplayPort scrambling: used for EMI reduction
3505 */
3506 if (need_stable_symbols) {
3507 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3508
3509 WARN_ON(!IS_G4X(dev));
3510
3511 I915_WRITE(PORT_DFT_I9XX,
3512 I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
3513
3514 if (pipe == PIPE_A)
3515 tmp |= PIPE_A_SCRAMBLE_RESET;
3516 else
3517 tmp |= PIPE_B_SCRAMBLE_RESET;
3518
3519 I915_WRITE(PORT_DFT2_G4X, tmp);
3520 }
3521
4b79ebf7
DV		 3522 return 0;
3523}
3524
8d2f24ca
DV		 3525static void vlv_undo_pipe_scramble_reset(struct drm_device *dev,
3526 enum pipe pipe)
3527{
3528 struct drm_i915_private *dev_priv = dev->dev_private;
3529 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3530
eb736679
VS		 3531 switch (pipe) {
3532 case PIPE_A:
8d2f24ca 3533 tmp &= ~PIPE_A_SCRAMBLE_RESET;
eb736679
VS		 3534 break;
3535 case PIPE_B:
8d2f24ca 3536 tmp &= ~PIPE_B_SCRAMBLE_RESET;
eb736679
VS		 3537 break;
3538 case PIPE_C:
3539 tmp &= ~PIPE_C_SCRAMBLE_RESET;
3540 break;
3541 default:
3542 return;
3543 }
8d2f24ca
DV		 3544 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
3545 tmp &= ~DC_BALANCE_RESET_VLV;
3546 I915_WRITE(PORT_DFT2_G4X, tmp);
3547
3548}
3549
84093603
DV		 3550static void g4x_undo_pipe_scramble_reset(struct drm_device *dev,
3551 enum pipe pipe)
3552{
3553 struct drm_i915_private *dev_priv = dev->dev_private;
3554 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3555
3556 if (pipe == PIPE_A)
3557 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3558 else
3559 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3560 I915_WRITE(PORT_DFT2_G4X, tmp);
3561
3562 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
3563 I915_WRITE(PORT_DFT_I9XX,
3564 I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
3565 }
3566}
3567
46a19188 3568static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
5b3a856b
DV		 3569 uint32_t *val)
3570{
46a19188
DV		 3571 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3572 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3573
3574 switch (*source) {
5b3a856b
DV		 3575 case INTEL_PIPE_CRC_SOURCE_PLANE1:
3576 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
3577 break;
3578 case INTEL_PIPE_CRC_SOURCE_PLANE2:
3579 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
3580 break;
5b3a856b
DV		 3581 case INTEL_PIPE_CRC_SOURCE_PIPE:
3582 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
3583 break;
3d099a05 3584 case INTEL_PIPE_CRC_SOURCE_NONE:
5b3a856b
DV		 3585 *val = 0;
3586 break;
3d099a05
DV		 3587 default:
3588 return -EINVAL;
5b3a856b
DV		 3589 }
3590
3591 return 0;
3592}
3593
fabf6e51
DV		 3594static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device *dev)
3595{
3596 struct drm_i915_private *dev_priv = dev->dev_private;
3597 struct intel_crtc *crtc =
3598 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
3599
3600 drm_modeset_lock_all(dev);
3601 /*
3602 * If we use the eDP transcoder we need to make sure that we don't
3603 * bypass the pfit, since otherwise the pipe CRC source won't work. Only
3604 * relevant on hsw with pipe A when using the always-on power well
3605 * routing.
3606 */
6e3c9717
ACO		 3607 if (crtc->config->cpu_transcoder == TRANSCODER_EDP &&
3608 !crtc->config->pch_pfit.enabled) {
3609 crtc->config->pch_pfit.force_thru = true;
fabf6e51
DV		 3610
3611 intel_display_power_get(dev_priv,
3612 POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A));
3613
ce22dba9 3614 intel_crtc_reset(crtc);
fabf6e51
DV		 3615 }
3616 drm_modeset_unlock_all(dev);
3617}
3618
3619static void hsw_undo_trans_edp_pipe_A_crc_wa(struct drm_device *dev)
3620{
3621 struct drm_i915_private *dev_priv = dev->dev_private;
3622 struct intel_crtc *crtc =
3623 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
3624
3625 drm_modeset_lock_all(dev);
3626 /*
3627 * If we use the eDP transcoder we need to make sure that we don't
3628 * bypass the pfit, since otherwise the pipe CRC source won't work. Only
3629 * relevant on hsw with pipe A when using the always-on power well
3630 * routing.
3631 */
6e3c9717
ACO		 3632 if (crtc->config->pch_pfit.force_thru) {
3633 crtc->config->pch_pfit.force_thru = false;
fabf6e51 3634
ce22dba9 3635 intel_crtc_reset(crtc);
fabf6e51
DV		 3636
3637 intel_display_power_put(dev_priv,
3638 POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A));
3639 }
3640 drm_modeset_unlock_all(dev);
3641}
3642
3643static int ivb_pipe_crc_ctl_reg(struct drm_device *dev,
3644 enum pipe pipe,
3645 enum intel_pipe_crc_source *source,
5b3a856b
DV		 3646 uint32_t *val)
3647{
46a19188
DV		 3648 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3649 *source = INTEL_PIPE_CRC_SOURCE_PF;
3650
3651 switch (*source) {
5b3a856b
DV		 3652 case INTEL_PIPE_CRC_SOURCE_PLANE1:
3653 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
3654 break;
3655 case INTEL_PIPE_CRC_SOURCE_PLANE2:
3656 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
3657 break;
3658 case INTEL_PIPE_CRC_SOURCE_PF:
fabf6e51
DV		 3659 if (IS_HASWELL(dev) && pipe == PIPE_A)
3660 hsw_trans_edp_pipe_A_crc_wa(dev);
3661
5b3a856b
DV		 3662 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
3663 break;
3d099a05 3664 case INTEL_PIPE_CRC_SOURCE_NONE:
5b3a856b
DV		 3665 *val = 0;
3666 break;
3d099a05
DV		 3667 default:
3668 return -EINVAL;
5b3a856b
DV		 3669 }
3670
3671 return 0;
3672}
3673
926321d5
DV		 3674static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
3675 enum intel_pipe_crc_source source)
3676{
3677 struct drm_i915_private *dev_priv = dev->dev_private;
cc3da175 3678 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
8c740dce
PZ		 3679 struct intel_crtc *crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev,
3680 pipe));
432f3342 3681 u32 val = 0; /* shut up gcc */
5b3a856b 3682 int ret;
926321d5 3683
cc3da175
DL		 3684 if (pipe_crc->source == source)
3685 return 0;
3686
ae676fcd
DL		 3687 /* forbid changing the source without going back to 'none' */
3688 if (pipe_crc->source && source)
3689 return -EINVAL;
3690
9d8b0588
DV		 3691 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PIPE(pipe))) {
3692 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
3693 return -EIO;
3694 }
3695
52f843f6 3696 if (IS_GEN2(dev))
46a19188 3697 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
52f843f6 3698 else if (INTEL_INFO(dev)->gen < 5)
46a19188 3699 ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
7ac0129b 3700 else if (IS_VALLEYVIEW(dev))
fabf6e51 3701 ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val);
4b79ebf7 3702 else if (IS_GEN5(dev) || IS_GEN6(dev))
46a19188 3703 ret = ilk_pipe_crc_ctl_reg(&source, &val);
5b3a856b 3704 else
fabf6e51 3705 ret = ivb_pipe_crc_ctl_reg(dev, pipe, &source, &val);
5b3a856b
DV		 3706
3707 if (ret != 0)
3708 return ret;
3709
4b584369
DL		 3710 /* none -> real source transition */
3711 if (source) {
4252fbc3
VS		 3712 struct intel_pipe_crc_entry *entries;
3713
7cd6ccff
DL		 3714 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
3715 pipe_name(pipe), pipe_crc_source_name(source));
3716
3cf54b34
VS		 3717 entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR,
3718 sizeof(pipe_crc->entries[0]),
4252fbc3
VS		 3719 GFP_KERNEL);
3720 if (!entries)
e5f75aca
DL		 3721 return -ENOMEM;
3722
8c740dce
PZ		 3723 /*
3724 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
3725 * enabled and disabled dynamically based on package C states,
3726 * user space can't make reliable use of the CRCs, so let's just
3727 * completely disable it.
3728 */
3729 hsw_disable_ips(crtc);
3730
d538bbdf 3731 spin_lock_irq(&pipe_crc->lock);
64387b61 3732 kfree(pipe_crc->entries);
4252fbc3 3733 pipe_crc->entries = entries;
d538bbdf
DL		 3734 pipe_crc->head = 0;
3735 pipe_crc->tail = 0;
3736 spin_unlock_irq(&pipe_crc->lock);
4b584369
DL		 3737 }
3738
cc3da175 3739 pipe_crc->source = source;
926321d5 3740
926321d5
DV		 3741 I915_WRITE(PIPE_CRC_CTL(pipe), val);
3742 POSTING_READ(PIPE_CRC_CTL(pipe));
3743
e5f75aca
DL		 3744 /* real source -> none transition */
3745 if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
d538bbdf 3746 struct intel_pipe_crc_entry *entries;
a33d7105
DV		 3747 struct intel_crtc *crtc =
3748 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
d538bbdf 3749
7cd6ccff
DL		 3750 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
3751 pipe_name(pipe));
3752
a33d7105
DV		 3753 drm_modeset_lock(&crtc->base.mutex, NULL);
3754 if (crtc->active)
3755 intel_wait_for_vblank(dev, pipe);
3756 drm_modeset_unlock(&crtc->base.mutex);
bcf17ab2 3757
d538bbdf
DL		 3758 spin_lock_irq(&pipe_crc->lock);
3759 entries = pipe_crc->entries;
e5f75aca 3760 pipe_crc->entries = NULL;
9ad6d99f
VS		 3761 pipe_crc->head = 0;
3762 pipe_crc->tail = 0;
d538bbdf
DL		 3763 spin_unlock_irq(&pipe_crc->lock);
3764
3765 kfree(entries);
84093603
DV		 3766
3767 if (IS_G4X(dev))
3768 g4x_undo_pipe_scramble_reset(dev, pipe);
8d2f24ca
DV		 3769 else if (IS_VALLEYVIEW(dev))
3770 vlv_undo_pipe_scramble_reset(dev, pipe);
fabf6e51
DV		 3771 else if (IS_HASWELL(dev) && pipe == PIPE_A)
3772 hsw_undo_trans_edp_pipe_A_crc_wa(dev);
8c740dce
PZ		 3773
3774 hsw_enable_ips(crtc);
e5f75aca
DL		 3775 }
3776
926321d5
DV		 3777 return 0;
3778}
3779
3780/*
3781 * Parse pipe CRC command strings:
b94dec87
DL		 3782 * command: wsp* object wsp+ name wsp+ source wsp*
3783 * object: 'pipe'
3784 * name: (A | B | C)
926321d5
DV		 3785 * source: (none | plane1 | plane2 | pf)
3786 * wsp: (#0x20 | #0x9 | #0xA)+
3787 *
3788 * eg.:
b94dec87
DL		 3789 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A
3790 * "pipe A none" -> Stop CRC
926321d5 3791 */
bd9db02f 3792static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
926321d5
DV		 3793{
3794 int n_words = 0;
3795
3796 while (*buf) {
3797 char *end;
3798
3799 /* skip leading white space */
3800 buf = skip_spaces(buf);
3801 if (!*buf)
3802 break; /* end of buffer */
3803
3804 /* find end of word */
3805 for (end = buf; *end && !isspace(*end); end++)
3806 ;
3807
3808 if (n_words == max_words) {
3809 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
3810 max_words);
3811 return -EINVAL; /* ran out of words[] before bytes */
3812 }
3813
3814 if (*end)
3815 *end++ = '\0';
3816 words[n_words++] = buf;
3817 buf = end;
3818 }
3819
3820 return n_words;
3821}
3822
b94dec87
DL		 3823enum intel_pipe_crc_object {
3824 PIPE_CRC_OBJECT_PIPE,
3825};
3826
e8dfcf78 3827static const char * const pipe_crc_objects[] = {
b94dec87
DL		 3828 "pipe",
3829};
3830
3831static int
bd9db02f 3832display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
b94dec87
DL		 3833{
3834 int i;
3835
3836 for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
3837 if (!strcmp(buf, pipe_crc_objects[i])) {
bd9db02f 3838 *o = i;
b94dec87
DL		 3839 return 0;
3840 }
3841
3842 return -EINVAL;
3843}
3844
bd9db02f 3845static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
926321d5
DV		 3846{
3847 const char name = buf[0];
3848
3849 if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
3850 return -EINVAL;
3851
3852 *pipe = name - 'A';
3853
3854 return 0;
3855}
3856
3857static int
bd9db02f 3858display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
926321d5
DV		 3859{
3860 int i;
3861
3862 for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
3863 if (!strcmp(buf, pipe_crc_sources[i])) {
bd9db02f 3864 *s = i;
926321d5
DV		 3865 return 0;
3866 }
3867
3868 return -EINVAL;
3869}
3870
bd9db02f 3871static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len)
926321d5 3872{
b94dec87 3873#define N_WORDS 3
926321d5 3874 int n_words;
b94dec87 3875 char *words[N_WORDS];
926321d5 3876 enum pipe pipe;
b94dec87 3877 enum intel_pipe_crc_object object;
926321d5
DV		 3878 enum intel_pipe_crc_source source;
3879
bd9db02f 3880 n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
b94dec87
DL		 3881 if (n_words != N_WORDS) {
3882 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
3883 N_WORDS);
3884 return -EINVAL;
3885 }
3886
bd9db02f 3887 if (display_crc_ctl_parse_object(words[0], &object) < 0) {
b94dec87 3888 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
926321d5
DV		 3889 return -EINVAL;
3890 }
3891
bd9db02f 3892 if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
b94dec87 3893 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
926321d5
DV		 3894 return -EINVAL;
3895 }
3896
bd9db02f 3897 if (display_crc_ctl_parse_source(words[2], &source) < 0) {
b94dec87 3898 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
926321d5
DV		 3899 return -EINVAL;
3900 }
3901
3902 return pipe_crc_set_source(dev, pipe, source);
3903}
3904
bd9db02f
DL		 3905static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
3906 size_t len, loff_t *offp)
926321d5
DV		 3907{
3908 struct seq_file *m = file->private_data;
3909 struct drm_device *dev = m->private;
3910 char *tmpbuf;
3911 int ret;
3912
3913 if (len == 0)
3914 return 0;
3915
3916 if (len > PAGE_SIZE - 1) {
3917 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
3918 PAGE_SIZE);
3919 return -E2BIG;
3920 }
3921
3922 tmpbuf = kmalloc(len + 1, GFP_KERNEL);
3923 if (!tmpbuf)
3924 return -ENOMEM;
3925
3926 if (copy_from_user(tmpbuf, ubuf, len)) {
3927 ret = -EFAULT;
3928 goto out;
3929 }
3930 tmpbuf[len] = '\0';
3931
bd9db02f 3932 ret = display_crc_ctl_parse(dev, tmpbuf, len);
926321d5
DV		 3933
3934out:
3935 kfree(tmpbuf);
3936 if (ret < 0)
3937 return ret;
3938
3939 *offp += len;
3940 return len;
3941}
3942
bd9db02f 3943static const struct file_operations i915_display_crc_ctl_fops = {
926321d5 3944 .owner = THIS_MODULE,
bd9db02f 3945 .open = display_crc_ctl_open,
926321d5
DV		 3946 .read = seq_read,
3947 .llseek = seq_lseek,
3948 .release = single_release,
bd9db02f 3949 .write = display_crc_ctl_write
926321d5
DV		 3950};
3951
eb3394fa
TP		 3952static ssize_t i915_displayport_test_active_write(struct file *file,
3953 const char __user *ubuf,
3954 size_t len, loff_t *offp)
3955{
3956 char *input_buffer;
3957 int status = 0;
3958 struct seq_file *m;
3959 struct drm_device *dev;
3960 struct drm_connector *connector;
3961 struct list_head *connector_list;
3962 struct intel_dp *intel_dp;
3963 int val = 0;
3964
3965 m = file->private_data;
3966 if (!m) {
3967 status = -ENODEV;
3968 return status;
3969 }
3970 dev = m->private;
3971
3972 if (!dev) {
3973 status = -ENODEV;
3974 return status;
3975 }
3976 connector_list = &dev->mode_config.connector_list;
3977
3978 if (len == 0)
3979 return 0;
3980
3981 input_buffer = kmalloc(len + 1, GFP_KERNEL);
3982 if (!input_buffer)
3983 return -ENOMEM;
3984
3985 if (copy_from_user(input_buffer, ubuf, len)) {
3986 status = -EFAULT;
3987 goto out;
3988 }
3989
3990 input_buffer[len] = '\0';
3991 DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len);
3992
3993 list_for_each_entry(connector, connector_list, head) {
3994
3995 if (connector->connector_type !=
3996 DRM_MODE_CONNECTOR_DisplayPort)
3997 continue;
3998
3999 if (connector->connector_type ==
4000 DRM_MODE_CONNECTOR_DisplayPort &&
4001 connector->status == connector_status_connected &&
4002 connector->encoder != NULL) {
4003 intel_dp = enc_to_intel_dp(connector->encoder);
4004 status = kstrtoint(input_buffer, 10, &val);
4005 if (status < 0)
4006 goto out;
4007 DRM_DEBUG_DRIVER("Got %d for test active\n", val);
4008 /* To prevent erroneous activation of the compliance
4009 * testing code, only accept an actual value of 1 here
4010 */
4011 if (val == 1)
4012 intel_dp->compliance_test_active = 1;
4013 else
4014 intel_dp->compliance_test_active = 0;
4015 }
4016 }
4017out:
4018 kfree(input_buffer);
4019 if (status < 0)
4020 return status;
4021
4022 *offp += len;
4023 return len;
4024}
4025
4026static int i915_displayport_test_active_show(struct seq_file *m, void *data)
4027{
4028 struct drm_device *dev = m->private;
4029 struct drm_connector *connector;
4030 struct list_head *connector_list = &dev->mode_config.connector_list;
4031 struct intel_dp *intel_dp;
4032
4033 if (!dev)
4034 return -ENODEV;
4035
4036 list_for_each_entry(connector, connector_list, head) {
4037
4038 if (connector->connector_type !=
4039 DRM_MODE_CONNECTOR_DisplayPort)
4040 continue;
4041
4042 if (connector->status == connector_status_connected &&
4043 connector->encoder != NULL) {
4044 intel_dp = enc_to_intel_dp(connector->encoder);
4045 if (intel_dp->compliance_test_active)
4046 seq_puts(m, "1");
4047 else
4048 seq_puts(m, "0");
4049 } else
4050 seq_puts(m, "0");
4051 }
4052
4053 return 0;
4054}
4055
4056static int i915_displayport_test_active_open(struct inode *inode,
4057 struct file *file)
4058{
4059 struct drm_device *dev = inode->i_private;
4060
4061 return single_open(file, i915_displayport_test_active_show, dev);
4062}
4063
4064static const struct file_operations i915_displayport_test_active_fops = {
4065 .owner = THIS_MODULE,
4066 .open = i915_displayport_test_active_open,
4067 .read = seq_read,
4068 .llseek = seq_lseek,
4069 .release = single_release,
4070 .write = i915_displayport_test_active_write
4071};
4072
4073static int i915_displayport_test_data_show(struct seq_file *m, void *data)
4074{
4075 struct drm_device *dev = m->private;
4076 struct drm_connector *connector;
4077 struct list_head *connector_list = &dev->mode_config.connector_list;
4078 struct intel_dp *intel_dp;
4079
4080 if (!dev)
4081 return -ENODEV;
4082
4083 list_for_each_entry(connector, connector_list, head) {
4084
4085 if (connector->connector_type !=
4086 DRM_MODE_CONNECTOR_DisplayPort)
4087 continue;
4088
4089 if (connector->status == connector_status_connected &&
4090 connector->encoder != NULL) {
4091 intel_dp = enc_to_intel_dp(connector->encoder);
4092 seq_printf(m, "%lx", intel_dp->compliance_test_data);
4093 } else
4094 seq_puts(m, "0");
4095 }
4096
4097 return 0;
4098}
4099static int i915_displayport_test_data_open(struct inode *inode,
4100 struct file *file)
4101{
4102 struct drm_device *dev = inode->i_private;
4103
4104 return single_open(file, i915_displayport_test_data_show, dev);
4105}
4106
4107static const struct file_operations i915_displayport_test_data_fops = {
4108 .owner = THIS_MODULE,
4109 .open = i915_displayport_test_data_open,
4110 .read = seq_read,
4111 .llseek = seq_lseek,
4112 .release = single_release
4113};
4114
4115static int i915_displayport_test_type_show(struct seq_file *m, void *data)
4116{
4117 struct drm_device *dev = m->private;
4118 struct drm_connector *connector;
4119 struct list_head *connector_list = &dev->mode_config.connector_list;
4120 struct intel_dp *intel_dp;
4121
4122 if (!dev)
4123 return -ENODEV;
4124
4125 list_for_each_entry(connector, connector_list, head) {
4126
4127 if (connector->connector_type !=
4128 DRM_MODE_CONNECTOR_DisplayPort)
4129 continue;
4130
4131 if (connector->status == connector_status_connected &&
4132 connector->encoder != NULL) {
4133 intel_dp = enc_to_intel_dp(connector->encoder);
4134 seq_printf(m, "%02lx", intel_dp->compliance_test_type);
4135 } else
4136 seq_puts(m, "0");
4137 }
4138
4139 return 0;
4140}
4141
4142static int i915_displayport_test_type_open(struct inode *inode,
4143 struct file *file)
4144{
4145 struct drm_device *dev = inode->i_private;
4146
4147 return single_open(file, i915_displayport_test_type_show, dev);
4148}
4149
4150static const struct file_operations i915_displayport_test_type_fops = {
4151 .owner = THIS_MODULE,
4152 .open = i915_displayport_test_type_open,
4153 .read = seq_read,
4154 .llseek = seq_lseek,
4155 .release = single_release
4156};
4157
97e94b22 4158static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
369a1342
VS		 4159{
4160 struct drm_device *dev = m->private;
546c81fd 4161 int num_levels = ilk_wm_max_level(dev) + 1;
369a1342
VS		 4162 int level;
4163
4164 drm_modeset_lock_all(dev);
4165
4166 for (level = 0; level < num_levels; level++) {
4167 unsigned int latency = wm[level];
4168
97e94b22
DL		 4169 /*
4170 * - WM1+ latency values in 0.5us units
4171 * - latencies are in us on gen9
4172 */
4173 if (INTEL_INFO(dev)->gen >= 9)
4174 latency *= 10;
4175 else if (level > 0)
369a1342
VS		 4176 latency *= 5;
4177
4178 seq_printf(m, "WM%d %u (%u.%u usec)\n",
97e94b22 4179 level, wm[level], latency / 10, latency % 10);
369a1342
VS		 4180 }
4181
4182 drm_modeset_unlock_all(dev);
4183}
4184
4185static int pri_wm_latency_show(struct seq_file *m, void *data)
4186{
4187 struct drm_device *dev = m->private;
97e94b22
DL		 4188 struct drm_i915_private *dev_priv = dev->dev_private;
4189 const uint16_t *latencies;
4190
4191 if (INTEL_INFO(dev)->gen >= 9)
4192 latencies = dev_priv->wm.skl_latency;
4193 else
4194 latencies = to_i915(dev)->wm.pri_latency;
369a1342 4195
97e94b22 4196 wm_latency_show(m, latencies);
369a1342
VS		 4197
4198 return 0;
4199}
4200
4201static int spr_wm_latency_show(struct seq_file *m, void *data)
4202{
4203 struct drm_device *dev = m->private;
97e94b22
DL		 4204 struct drm_i915_private *dev_priv = dev->dev_private;
4205 const uint16_t *latencies;
4206
4207 if (INTEL_INFO(dev)->gen >= 9)
4208 latencies = dev_priv->wm.skl_latency;
4209 else
4210 latencies = to_i915(dev)->wm.spr_latency;
369a1342 4211
97e94b22 4212 wm_latency_show(m, latencies);
369a1342
VS		 4213
4214 return 0;
4215}
4216
4217static int cur_wm_latency_show(struct seq_file *m, void *data)
4218{
4219 struct drm_device *dev = m->private;
97e94b22
DL		 4220 struct drm_i915_private *dev_priv = dev->dev_private;
4221 const uint16_t *latencies;
4222
4223 if (INTEL_INFO(dev)->gen >= 9)
4224 latencies = dev_priv->wm.skl_latency;
4225 else
4226 latencies = to_i915(dev)->wm.cur_latency;
369a1342 4227
97e94b22 4228 wm_latency_show(m, latencies);
369a1342
VS		 4229
4230 return 0;
4231}
4232
4233static int pri_wm_latency_open(struct inode *inode, struct file *file)
4234{
4235 struct drm_device *dev = inode->i_private;
4236
9ad0257c 4237 if (HAS_GMCH_DISPLAY(dev))
369a1342
VS		 4238 return -ENODEV;
4239
4240 return single_open(file, pri_wm_latency_show, dev);
4241}
4242
4243static int spr_wm_latency_open(struct inode *inode, struct file *file)
4244{
4245 struct drm_device *dev = inode->i_private;
4246
9ad0257c 4247 if (HAS_GMCH_DISPLAY(dev))
369a1342
VS		 4248 return -ENODEV;
4249
4250 return single_open(file, spr_wm_latency_show, dev);
4251}
4252
4253static int cur_wm_latency_open(struct inode *inode, struct file *file)
4254{
4255 struct drm_device *dev = inode->i_private;
4256
9ad0257c 4257 if (HAS_GMCH_DISPLAY(dev))
369a1342
VS		 4258 return -ENODEV;
4259
4260 return single_open(file, cur_wm_latency_show, dev);
4261}
4262
4263static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
97e94b22 4264 size_t len, loff_t *offp, uint16_t wm[8])
369a1342
VS		 4265{
4266 struct seq_file *m = file->private_data;
4267 struct drm_device *dev = m->private;
97e94b22 4268 uint16_t new[8] = { 0 };
546c81fd 4269 int num_levels = ilk_wm_max_level(dev) + 1;
369a1342
VS		 4270 int level;
4271 int ret;
4272 char tmp[32];
4273
4274 if (len >= sizeof(tmp))
4275 return -EINVAL;
4276
4277 if (copy_from_user(tmp, ubuf, len))
4278 return -EFAULT;
4279
4280 tmp[len] = '\0';
4281
97e94b22
DL		 4282 ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
4283 &new[0], &new[1], &new[2], &new[3],
4284 &new[4], &new[5], &new[6], &new[7]);
369a1342
VS		 4285 if (ret != num_levels)
4286 return -EINVAL;
4287
4288 drm_modeset_lock_all(dev);
4289
4290 for (level = 0; level < num_levels; level++)
4291 wm[level] = new[level];
4292
4293 drm_modeset_unlock_all(dev);
4294
4295 return len;
4296}
4297
4298
4299static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
4300 size_t len, loff_t *offp)
4301{
4302 struct seq_file *m = file->private_data;
4303 struct drm_device *dev = m->private;
97e94b22
DL		 4304 struct drm_i915_private *dev_priv = dev->dev_private;
4305 uint16_t *latencies;
369a1342 4306
97e94b22
DL		 4307 if (INTEL_INFO(dev)->gen >= 9)
4308 latencies = dev_priv->wm.skl_latency;
4309 else
4310 latencies = to_i915(dev)->wm.pri_latency;
4311
4312 return wm_latency_write(file, ubuf, len, offp, latencies);
369a1342
VS		 4313}
4314
4315static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
4316 size_t len, loff_t *offp)
4317{
4318 struct seq_file *m = file->private_data;
4319 struct drm_device *dev = m->private;
97e94b22
DL		 4320 struct drm_i915_private *dev_priv = dev->dev_private;
4321 uint16_t *latencies;
369a1342 4322
97e94b22
DL		 4323 if (INTEL_INFO(dev)->gen >= 9)
4324 latencies = dev_priv->wm.skl_latency;
4325 else
4326 latencies = to_i915(dev)->wm.spr_latency;
4327
4328 return wm_latency_write(file, ubuf, len, offp, latencies);
369a1342
VS		 4329}
4330
4331static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
4332 size_t len, loff_t *offp)
4333{
4334 struct seq_file *m = file->private_data;
4335 struct drm_device *dev = m->private;
97e94b22
DL		 4336 struct drm_i915_private *dev_priv = dev->dev_private;
4337 uint16_t *latencies;
4338
4339 if (INTEL_INFO(dev)->gen >= 9)
4340 latencies = dev_priv->wm.skl_latency;
4341 else
4342 latencies = to_i915(dev)->wm.cur_latency;
369a1342 4343
97e94b22 4344 return wm_latency_write(file, ubuf, len, offp, latencies);
369a1342
VS		 4345}
4346
4347static const struct file_operations i915_pri_wm_latency_fops = {
4348 .owner = THIS_MODULE,
4349 .open = pri_wm_latency_open,
4350 .read = seq_read,
4351 .llseek = seq_lseek,
4352 .release = single_release,
4353 .write = pri_wm_latency_write
4354};
4355
4356static const struct file_operations i915_spr_wm_latency_fops = {
4357 .owner = THIS_MODULE,
4358 .open = spr_wm_latency_open,
4359 .read = seq_read,
4360 .llseek = seq_lseek,
4361 .release = single_release,
4362 .write = spr_wm_latency_write
4363};
4364
4365static const struct file_operations i915_cur_wm_latency_fops = {
4366 .owner = THIS_MODULE,
4367 .open = cur_wm_latency_open,
4368 .read = seq_read,
4369 .llseek = seq_lseek,
4370 .release = single_release,
4371 .write = cur_wm_latency_write
4372};
4373
647416f9
KC		 4374static int
4375i915_wedged_get(void *data, u64 *val)
f3cd474b 4376{
647416f9 4377 struct drm_device *dev = data;
e277a1f8 4378 struct drm_i915_private *dev_priv = dev->dev_private;
f3cd474b 4379
647416f9 4380 *val = atomic_read(&dev_priv->gpu_error.reset_counter);
f3cd474b 4381
647416f9 4382 return 0;
f3cd474b
CW		 4383}
4384
647416f9
KC		 4385static int
4386i915_wedged_set(void *data, u64 val)
f3cd474b 4387{
647416f9 4388 struct drm_device *dev = data;
d46c0517
ID		 4389 struct drm_i915_private *dev_priv = dev->dev_private;
4390
b8d24a06
MK		 4391 /*
4392 * There is no safeguard against this debugfs entry colliding
4393 * with the hangcheck calling same i915_handle_error() in
4394 * parallel, causing an explosion. For now we assume that the
4395 * test harness is responsible enough not to inject gpu hangs
4396 * while it is writing to 'i915_wedged'
4397 */
4398
4399 if (i915_reset_in_progress(&dev_priv->gpu_error))
4400 return -EAGAIN;
4401
d46c0517 4402 intel_runtime_pm_get(dev_priv);
f3cd474b 4403
58174462
MK		 4404 i915_handle_error(dev, val,
4405 "Manually setting wedged to %llu", val);
d46c0517
ID		 4406
4407 intel_runtime_pm_put(dev_priv);
4408
647416f9 4409 return 0;
f3cd474b
CW		 4410}
4411
647416f9
KC		 4412DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
4413 i915_wedged_get, i915_wedged_set,
3a3b4f98 4414 "%llu\n");
f3cd474b 4415
647416f9
KC		 4416static int
4417i915_ring_stop_get(void *data, u64 *val)
e5eb3d63 4418{
647416f9 4419 struct drm_device *dev = data;
e277a1f8 4420 struct drm_i915_private *dev_priv = dev->dev_private;
e5eb3d63 4421
647416f9 4422 *val = dev_priv->gpu_error.stop_rings;
e5eb3d63 4423
647416f9 4424 return 0;
e5eb3d63
DV		 4425}
4426
647416f9
KC		 4427static int
4428i915_ring_stop_set(void *data, u64 val)
e5eb3d63 4429{
647416f9 4430 struct drm_device *dev = data;
e5eb3d63 4431 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 4432 int ret;
e5eb3d63 4433
647416f9 4434 DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val);
e5eb3d63 4435
22bcfc6a
DV		 4436 ret = mutex_lock_interruptible(&dev->struct_mutex);
4437 if (ret)
4438 return ret;
4439
99584db3 4440 dev_priv->gpu_error.stop_rings = val;
e5eb3d63
DV		 4441 mutex_unlock(&dev->struct_mutex);
4442
647416f9 4443 return 0;
e5eb3d63
DV		 4444}
4445
647416f9
KC		 4446DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops,
4447 i915_ring_stop_get, i915_ring_stop_set,
4448 "0x%08llx\n");
d5442303 4449
094f9a54
CW		 4450static int
4451i915_ring_missed_irq_get(void *data, u64 *val)
4452{
4453 struct drm_device *dev = data;
4454 struct drm_i915_private *dev_priv = dev->dev_private;
4455
4456 *val = dev_priv->gpu_error.missed_irq_rings;
4457 return 0;
4458}
4459
4460static int
4461i915_ring_missed_irq_set(void *data, u64 val)
4462{
4463 struct drm_device *dev = data;
4464 struct drm_i915_private *dev_priv = dev->dev_private;
4465 int ret;
4466
4467 /* Lock against concurrent debugfs callers */
4468 ret = mutex_lock_interruptible(&dev->struct_mutex);
4469 if (ret)
4470 return ret;
4471 dev_priv->gpu_error.missed_irq_rings = val;
4472 mutex_unlock(&dev->struct_mutex);
4473
4474 return 0;
4475}
4476
4477DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
4478 i915_ring_missed_irq_get, i915_ring_missed_irq_set,
4479 "0x%08llx\n");
4480
4481static int
4482i915_ring_test_irq_get(void *data, u64 *val)
4483{
4484 struct drm_device *dev = data;
4485 struct drm_i915_private *dev_priv = dev->dev_private;
4486
4487 *val = dev_priv->gpu_error.test_irq_rings;
4488
4489 return 0;
4490}
4491
4492static int
4493i915_ring_test_irq_set(void *data, u64 val)
4494{
4495 struct drm_device *dev = data;
4496 struct drm_i915_private *dev_priv = dev->dev_private;
4497 int ret;
4498
4499 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
4500
4501 /* Lock against concurrent debugfs callers */
4502 ret = mutex_lock_interruptible(&dev->struct_mutex);
4503 if (ret)
4504 return ret;
4505
4506 dev_priv->gpu_error.test_irq_rings = val;
4507 mutex_unlock(&dev->struct_mutex);
4508
4509 return 0;
4510}
4511
4512DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
4513 i915_ring_test_irq_get, i915_ring_test_irq_set,
4514 "0x%08llx\n");
4515
dd624afd
CW		 4516#define DROP_UNBOUND 0x1
4517#define DROP_BOUND 0x2
4518#define DROP_RETIRE 0x4
4519#define DROP_ACTIVE 0x8
4520#define DROP_ALL (DROP_UNBOUND | \
4521 DROP_BOUND | \
4522 DROP_RETIRE | \
4523 DROP_ACTIVE)
647416f9
KC		 4524static int
4525i915_drop_caches_get(void *data, u64 *val)
dd624afd 4526{
647416f9 4527 *val = DROP_ALL;
dd624afd 4528
647416f9 4529 return 0;
dd624afd
CW		 4530}
4531
647416f9
KC		 4532static int
4533i915_drop_caches_set(void *data, u64 val)
dd624afd 4534{
647416f9 4535 struct drm_device *dev = data;
dd624afd 4536 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 4537 int ret;
dd624afd 4538
2f9fe5ff 4539 DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
dd624afd
CW		 4540
4541 /* No need to check and wait for gpu resets, only libdrm auto-restarts
4542 * on ioctls on -EAGAIN. */
4543 ret = mutex_lock_interruptible(&dev->struct_mutex);
4544 if (ret)
4545 return ret;
4546
4547 if (val & DROP_ACTIVE) {
4548 ret = i915_gpu_idle(dev);
4549 if (ret)
4550 goto unlock;
4551 }
4552
4553 if (val & (DROP_RETIRE | DROP_ACTIVE))
4554 i915_gem_retire_requests(dev);
4555
21ab4e74
CW		 4556 if (val & DROP_BOUND)
4557 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND);
4ad72b7f 4558
21ab4e74
CW		 4559 if (val & DROP_UNBOUND)
4560 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND);
dd624afd
CW		 4561
4562unlock:
4563 mutex_unlock(&dev->struct_mutex);
4564
647416f9 4565 return ret;
dd624afd
CW		 4566}
4567
647416f9
KC		 4568DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
4569 i915_drop_caches_get, i915_drop_caches_set,
4570 "0x%08llx\n");
dd624afd 4571
647416f9
KC		 4572static int
4573i915_max_freq_get(void *data, u64 *val)
358733e9 4574{
647416f9 4575 struct drm_device *dev = data;
e277a1f8 4576 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 4577 int ret;
004777cb 4578
daa3afb2 4579 if (INTEL_INFO(dev)->gen < 6)
004777cb
DV		 4580 return -ENODEV;
4581
5c9669ce
TR		 4582 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4583
4fc688ce 4584 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 4585 if (ret)
4586 return ret;
358733e9 4587
7c59a9c1 4588 *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
4fc688ce 4589 mutex_unlock(&dev_priv->rps.hw_lock);
358733e9 4590
647416f9 4591 return 0;
358733e9
JB		 4592}
4593
647416f9
KC		 4594static int
4595i915_max_freq_set(void *data, u64 val)
358733e9 4596{
647416f9 4597 struct drm_device *dev = data;
358733e9 4598 struct drm_i915_private *dev_priv = dev->dev_private;
bc4d91f6 4599 u32 hw_max, hw_min;
647416f9 4600 int ret;
004777cb 4601
daa3afb2 4602 if (INTEL_INFO(dev)->gen < 6)
004777cb 4603 return -ENODEV;
358733e9 4604
5c9669ce
TR		 4605 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4606
647416f9 4607 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
358733e9 4608
4fc688ce 4609 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 4610 if (ret)
4611 return ret;
4612
358733e9
JB		 4613 /*
4614 * Turbo will still be enabled, but won't go above the set value.
4615 */
bc4d91f6 4616 val = intel_freq_opcode(dev_priv, val);
dd0a1aa1 4617
bc4d91f6
AG		 4618 hw_max = dev_priv->rps.max_freq;
4619 hw_min = dev_priv->rps.min_freq;
dd0a1aa1 4620
b39fb297 4621 if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
dd0a1aa1
JM		 4622 mutex_unlock(&dev_priv->rps.hw_lock);
4623 return -EINVAL;
0a073b84
JB		 4624 }
4625
b39fb297 4626 dev_priv->rps.max_freq_softlimit = val;
dd0a1aa1 4627
ffe02b40 4628 intel_set_rps(dev, val);
dd0a1aa1 4629
4fc688ce 4630 mutex_unlock(&dev_priv->rps.hw_lock);
358733e9 4631
647416f9 4632 return 0;
358733e9
JB		 4633}
4634
647416f9
KC		 4635DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
4636 i915_max_freq_get, i915_max_freq_set,
3a3b4f98 4637 "%llu\n");
358733e9 4638
647416f9
KC		 4639static int
4640i915_min_freq_get(void *data, u64 *val)
1523c310 4641{
647416f9 4642 struct drm_device *dev = data;
e277a1f8 4643 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 4644 int ret;
004777cb 4645
daa3afb2 4646 if (INTEL_INFO(dev)->gen < 6)
004777cb
DV		 4647 return -ENODEV;
4648
5c9669ce
TR		 4649 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4650
4fc688ce 4651 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 4652 if (ret)
4653 return ret;
1523c310 4654
7c59a9c1 4655 *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
4fc688ce 4656 mutex_unlock(&dev_priv->rps.hw_lock);
1523c310 4657
647416f9 4658 return 0;
1523c310
JB		 4659}
4660
647416f9
KC		 4661static int
4662i915_min_freq_set(void *data, u64 val)
1523c310 4663{
647416f9 4664 struct drm_device *dev = data;
1523c310 4665 struct drm_i915_private *dev_priv = dev->dev_private;
bc4d91f6 4666 u32 hw_max, hw_min;
647416f9 4667 int ret;
004777cb 4668
daa3afb2 4669 if (INTEL_INFO(dev)->gen < 6)
004777cb 4670 return -ENODEV;
1523c310 4671
5c9669ce
TR		 4672 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4673
647416f9 4674 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
1523c310 4675
4fc688ce 4676 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 4677 if (ret)
4678 return ret;
4679
1523c310
JB		 4680 /*
4681 * Turbo will still be enabled, but won't go below the set value.
4682 */
bc4d91f6 4683 val = intel_freq_opcode(dev_priv, val);
dd0a1aa1 4684
bc4d91f6
AG		 4685 hw_max = dev_priv->rps.max_freq;
4686 hw_min = dev_priv->rps.min_freq;
dd0a1aa1 4687
b39fb297 4688 if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
dd0a1aa1
JM		 4689 mutex_unlock(&dev_priv->rps.hw_lock);
4690 return -EINVAL;
0a073b84 4691 }
dd0a1aa1 4692
b39fb297 4693 dev_priv->rps.min_freq_softlimit = val;
dd0a1aa1 4694
ffe02b40 4695 intel_set_rps(dev, val);
dd0a1aa1 4696
4fc688ce 4697 mutex_unlock(&dev_priv->rps.hw_lock);
1523c310 4698
647416f9 4699 return 0;
1523c310
JB		 4700}
4701
647416f9
KC		 4702DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
4703 i915_min_freq_get, i915_min_freq_set,
3a3b4f98 4704 "%llu\n");
1523c310 4705
647416f9
KC		 4706static int
4707i915_cache_sharing_get(void *data, u64 *val)
07b7ddd9 4708{
647416f9 4709 struct drm_device *dev = data;
e277a1f8 4710 struct drm_i915_private *dev_priv = dev->dev_private;
07b7ddd9 4711 u32 snpcr;
647416f9 4712 int ret;
07b7ddd9 4713
004777cb
DV		 4714 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
4715 return -ENODEV;
4716
22bcfc6a
DV		 4717 ret = mutex_lock_interruptible(&dev->struct_mutex);
4718 if (ret)
4719 return ret;
c8c8fb33 4720 intel_runtime_pm_get(dev_priv);
22bcfc6a 4721
07b7ddd9 4722 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
c8c8fb33
PZ		 4723
4724 intel_runtime_pm_put(dev_priv);
07b7ddd9
JB		 4725 mutex_unlock(&dev_priv->dev->struct_mutex);
4726
647416f9 4727 *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
07b7ddd9 4728
647416f9 4729 return 0;
07b7ddd9
JB		 4730}
4731
647416f9
KC		 4732static int
4733i915_cache_sharing_set(void *data, u64 val)
07b7ddd9 4734{
647416f9 4735 struct drm_device *dev = data;
07b7ddd9 4736 struct drm_i915_private *dev_priv = dev->dev_private;
07b7ddd9 4737 u32 snpcr;
07b7ddd9 4738
004777cb
DV		 4739 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
4740 return -ENODEV;
4741
647416f9 4742 if (val > 3)
07b7ddd9
JB		 4743 return -EINVAL;
4744
c8c8fb33 4745 intel_runtime_pm_get(dev_priv);
647416f9 4746 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
07b7ddd9
JB		 4747
4748 /* Update the cache sharing policy here as well */
4749 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4750 snpcr &= ~GEN6_MBC_SNPCR_MASK;
4751 snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
4752 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
4753
c8c8fb33 4754 intel_runtime_pm_put(dev_priv);
647416f9 4755 return 0;
07b7ddd9
JB		 4756}
4757
647416f9
KC		 4758DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
4759 i915_cache_sharing_get, i915_cache_sharing_set,
4760 "%llu\n");
07b7ddd9 4761
5d39525a
JM		 4762struct sseu_dev_status {
4763 unsigned int slice_total;
4764 unsigned int subslice_total;
4765 unsigned int subslice_per_slice;
4766 unsigned int eu_total;
4767 unsigned int eu_per_subslice;
4768};
4769
4770static void cherryview_sseu_device_status(struct drm_device *dev,
4771 struct sseu_dev_status *stat)
4772{
4773 struct drm_i915_private *dev_priv = dev->dev_private;
4774 const int ss_max = 2;
4775 int ss;
4776 u32 sig1[ss_max], sig2[ss_max];
4777
4778 sig1[0] = I915_READ(CHV_POWER_SS0_SIG1);
4779 sig1[1] = I915_READ(CHV_POWER_SS1_SIG1);
4780 sig2[0] = I915_READ(CHV_POWER_SS0_SIG2);
4781 sig2[1] = I915_READ(CHV_POWER_SS1_SIG2);
4782
4783 for (ss = 0; ss < ss_max; ss++) {
4784 unsigned int eu_cnt;
4785
4786 if (sig1[ss] & CHV_SS_PG_ENABLE)
4787 /* skip disabled subslice */
4788 continue;
4789
4790 stat->slice_total = 1;
4791 stat->subslice_per_slice++;
4792 eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
4793 ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
4794 ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
4795 ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2);
4796 stat->eu_total += eu_cnt;
4797 stat->eu_per_subslice = max(stat->eu_per_subslice, eu_cnt);
4798 }
4799 stat->subslice_total = stat->subslice_per_slice;
4800}
4801
4802static void gen9_sseu_device_status(struct drm_device *dev,
4803 struct sseu_dev_status *stat)
4804{
4805 struct drm_i915_private *dev_priv = dev->dev_private;
1c046bc1 4806 int s_max = 3, ss_max = 4;
5d39525a
JM		 4807 int s, ss;
4808 u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
4809
1c046bc1
JM		 4810 /* BXT has a single slice and at most 3 subslices. */
4811 if (IS_BROXTON(dev)) {
4812 s_max = 1;
4813 ss_max = 3;
4814 }
4815
4816 for (s = 0; s < s_max; s++) {
4817 s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s));
4818 eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s));
4819 eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s));
4820 }
4821
5d39525a
JM		 4822 eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
4823 GEN9_PGCTL_SSA_EU19_ACK |
4824 GEN9_PGCTL_SSA_EU210_ACK |
4825 GEN9_PGCTL_SSA_EU311_ACK;
4826 eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
4827 GEN9_PGCTL_SSB_EU19_ACK |
4828 GEN9_PGCTL_SSB_EU210_ACK |
4829 GEN9_PGCTL_SSB_EU311_ACK;
4830
4831 for (s = 0; s < s_max; s++) {
1c046bc1
JM		 4832 unsigned int ss_cnt = 0;
4833
5d39525a
JM		 4834 if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
4835 /* skip disabled slice */
4836 continue;
4837
4838 stat->slice_total++;
1c046bc1
JM		 4839
4840 if (IS_SKYLAKE(dev))
4841 ss_cnt = INTEL_INFO(dev)->subslice_per_slice;
4842
5d39525a
JM		 4843 for (ss = 0; ss < ss_max; ss++) {
4844 unsigned int eu_cnt;
4845
1c046bc1
JM		 4846 if (IS_BROXTON(dev) &&
4847 !(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
4848 /* skip disabled subslice */
4849 continue;
4850
4851 if (IS_BROXTON(dev))
4852 ss_cnt++;
4853
5d39525a
JM		 4854 eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
4855 eu_mask[ss%2]);
4856 stat->eu_total += eu_cnt;
4857 stat->eu_per_subslice = max(stat->eu_per_subslice,
4858 eu_cnt);
4859 }
1c046bc1
JM		 4860
4861 stat->subslice_total += ss_cnt;
4862 stat->subslice_per_slice = max(stat->subslice_per_slice,
4863 ss_cnt);
5d39525a
JM		 4864 }
4865}
4866
3873218f
JM		 4867static int i915_sseu_status(struct seq_file *m, void *unused)
4868{
4869 struct drm_info_node *node = (struct drm_info_node *) m->private;
4870 struct drm_device *dev = node->minor->dev;
5d39525a 4871 struct sseu_dev_status stat;
3873218f 4872
5575f03a 4873 if ((INTEL_INFO(dev)->gen < 8) || IS_BROADWELL(dev))
3873218f
JM		 4874 return -ENODEV;
4875
4876 seq_puts(m, "SSEU Device Info\n");
4877 seq_printf(m, " Available Slice Total: %u\n",
4878 INTEL_INFO(dev)->slice_total);
4879 seq_printf(m, " Available Subslice Total: %u\n",
4880 INTEL_INFO(dev)->subslice_total);
4881 seq_printf(m, " Available Subslice Per Slice: %u\n",
4882 INTEL_INFO(dev)->subslice_per_slice);
4883 seq_printf(m, " Available EU Total: %u\n",
4884 INTEL_INFO(dev)->eu_total);
4885 seq_printf(m, " Available EU Per Subslice: %u\n",
4886 INTEL_INFO(dev)->eu_per_subslice);
4887 seq_printf(m, " Has Slice Power Gating: %s\n",
4888 yesno(INTEL_INFO(dev)->has_slice_pg));
4889 seq_printf(m, " Has Subslice Power Gating: %s\n",
4890 yesno(INTEL_INFO(dev)->has_subslice_pg));
4891 seq_printf(m, " Has EU Power Gating: %s\n",
4892 yesno(INTEL_INFO(dev)->has_eu_pg));
4893
7f992aba 4894 seq_puts(m, "SSEU Device Status\n");
5d39525a 4895 memset(&stat, 0, sizeof(stat));
5575f03a 4896 if (IS_CHERRYVIEW(dev)) {
5d39525a 4897 cherryview_sseu_device_status(dev, &stat);
1c046bc1 4898 } else if (INTEL_INFO(dev)->gen >= 9) {
5d39525a 4899 gen9_sseu_device_status(dev, &stat);
7f992aba 4900 }
5d39525a
JM		 4901 seq_printf(m, " Enabled Slice Total: %u\n",
4902 stat.slice_total);
4903 seq_printf(m, " Enabled Subslice Total: %u\n",
4904 stat.subslice_total);
4905 seq_printf(m, " Enabled Subslice Per Slice: %u\n",
4906 stat.subslice_per_slice);
4907 seq_printf(m, " Enabled EU Total: %u\n",
4908 stat.eu_total);
4909 seq_printf(m, " Enabled EU Per Subslice: %u\n",
4910 stat.eu_per_subslice);
7f992aba 4911
3873218f
JM		 4912 return 0;
4913}
4914
6d794d42
BW		 4915static int i915_forcewake_open(struct inode *inode, struct file *file)
4916{
4917 struct drm_device *dev = inode->i_private;
4918 struct drm_i915_private *dev_priv = dev->dev_private;
6d794d42 4919
075edca4 4920 if (INTEL_INFO(dev)->gen < 6)
6d794d42
BW		 4921 return 0;
4922
6daccb0b 4923 intel_runtime_pm_get(dev_priv);
59bad947 4924 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6d794d42
BW		 4925
4926 return 0;
4927}
4928
c43b5634 4929static int i915_forcewake_release(struct inode *inode, struct file *file)
6d794d42
BW		 4930{
4931 struct drm_device *dev = inode->i_private;
4932 struct drm_i915_private *dev_priv = dev->dev_private;
4933
075edca4 4934 if (INTEL_INFO(dev)->gen < 6)
6d794d42
BW		 4935 return 0;
4936
59bad947 4937 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6daccb0b 4938 intel_runtime_pm_put(dev_priv);
6d794d42
BW		 4939
4940 return 0;
4941}
4942
4943static const struct file_operations i915_forcewake_fops = {
4944 .owner = THIS_MODULE,
4945 .open = i915_forcewake_open,
4946 .release = i915_forcewake_release,
4947};
4948
4949static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
4950{
4951 struct drm_device *dev = minor->dev;
4952 struct dentry *ent;
4953
4954 ent = debugfs_create_file("i915_forcewake_user",
8eb57294 4955 S_IRUSR,
6d794d42
BW		 4956 root, dev,
4957 &i915_forcewake_fops);
f3c5fe97
WY		 4958 if (!ent)
4959 return -ENOMEM;
6d794d42 4960
8eb57294 4961 return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
6d794d42
BW		 4962}
4963
6a9c308d
DV		 4964static int i915_debugfs_create(struct dentry *root,
4965 struct drm_minor *minor,
4966 const char *name,
4967 const struct file_operations *fops)
07b7ddd9
JB		 4968{
4969 struct drm_device *dev = minor->dev;
4970 struct dentry *ent;
4971
6a9c308d 4972 ent = debugfs_create_file(name,
07b7ddd9
JB		 4973 S_IRUGO | S_IWUSR,
4974 root, dev,
6a9c308d 4975 fops);
f3c5fe97
WY		 4976 if (!ent)
4977 return -ENOMEM;
07b7ddd9 4978
6a9c308d 4979 return drm_add_fake_info_node(minor, ent, fops);
07b7ddd9
JB		 4980}
4981
06c5bf8c 4982static const struct drm_info_list i915_debugfs_list[] = {
311bd68e 4983 {"i915_capabilities", i915_capabilities, 0},
73aa808f 4984 {"i915_gem_objects", i915_gem_object_info, 0},
08c18323 4985 {"i915_gem_gtt", i915_gem_gtt_info, 0},
1b50247a 4986 {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
433e12f7 4987 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
433e12f7 4988 {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
6d2b8885 4989 {"i915_gem_stolen", i915_gem_stolen_list_info },
4e5359cd 4990 {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
2017263e
BG		 4991 {"i915_gem_request", i915_gem_request_info, 0},
4992 {"i915_gem_seqno", i915_gem_seqno_info, 0},
a6172a80 4993 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
2017263e 4994 {"i915_gem_interrupt", i915_interrupt_info, 0},
1ec14ad3
CW		 4995 {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
4996 {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
4997 {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
9010ebfd 4998 {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
493018dc 4999 {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0},
adb4bd12 5000 {"i915_frequency_info", i915_frequency_info, 0},
f654449a 5001 {"i915_hangcheck_info", i915_hangcheck_info, 0},
f97108d1 5002 {"i915_drpc_info", i915_drpc_info, 0},
7648fa99 5003 {"i915_emon_status", i915_emon_status, 0},
23b2f8bb 5004 {"i915_ring_freq_table", i915_ring_freq_table, 0},
b5e50c3f 5005 {"i915_fbc_status", i915_fbc_status, 0},
92d44621 5006 {"i915_ips_status", i915_ips_status, 0},
4a9bef37 5007 {"i915_sr_status", i915_sr_status, 0},
44834a67 5008 {"i915_opregion", i915_opregion, 0},
37811fcc 5009 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
e76d3630 5010 {"i915_context_status", i915_context_status, 0},
c0ab1ae9 5011 {"i915_dump_lrc", i915_dump_lrc, 0},
4ba70e44 5012 {"i915_execlists", i915_execlists, 0},
f65367b5 5013 {"i915_forcewake_domains", i915_forcewake_domains, 0},
ea16a3cd 5014 {"i915_swizzle_info", i915_swizzle_info, 0},
3cf17fc5 5015 {"i915_ppgtt_info", i915_ppgtt_info, 0},
63573eb7 5016 {"i915_llc", i915_llc, 0},
e91fd8c6 5017 {"i915_edp_psr_status", i915_edp_psr_status, 0},
d2e216d0 5018 {"i915_sink_crc_eDP1", i915_sink_crc, 0},
ec013e7f 5019 {"i915_energy_uJ", i915_energy_uJ, 0},
371db66a 5020 {"i915_pc8_status", i915_pc8_status, 0},
1da51581 5021 {"i915_power_domain_info", i915_power_domain_info, 0},
53f5e3ca 5022 {"i915_display_info", i915_display_info, 0},
e04934cf 5023 {"i915_semaphore_status", i915_semaphore_status, 0},
728e29d7 5024 {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
11bed958 5025 {"i915_dp_mst_info", i915_dp_mst_info, 0},
1ed1ef9d 5026 {"i915_wa_registers", i915_wa_registers, 0},
c5511e44 5027 {"i915_ddb_info", i915_ddb_info, 0},
3873218f 5028 {"i915_sseu_status", i915_sseu_status, 0},
a54746e3 5029 {"i915_drrs_status", i915_drrs_status, 0},
1854d5ca 5030 {"i915_rps_boost_info", i915_rps_boost_info, 0},
2017263e 5031};
27c202ad 5032#define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
2017263e 5033
06c5bf8c 5034static const struct i915_debugfs_files {
34b9674c
DV		 5035 const char *name;
5036 const struct file_operations *fops;
5037} i915_debugfs_files[] = {
5038 {"i915_wedged", &i915_wedged_fops},
5039 {"i915_max_freq", &i915_max_freq_fops},
5040 {"i915_min_freq", &i915_min_freq_fops},
5041 {"i915_cache_sharing", &i915_cache_sharing_fops},
5042 {"i915_ring_stop", &i915_ring_stop_fops},
094f9a54
CW		 5043 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
5044 {"i915_ring_test_irq", &i915_ring_test_irq_fops},
34b9674c
DV		 5045 {"i915_gem_drop_caches", &i915_drop_caches_fops},
5046 {"i915_error_state", &i915_error_state_fops},
5047 {"i915_next_seqno", &i915_next_seqno_fops},
bd9db02f 5048 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
369a1342
VS		 5049 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
5050 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
5051 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
da46f936 5052 {"i915_fbc_false_color", &i915_fbc_fc_fops},
eb3394fa
TP		 5053 {"i915_dp_test_data", &i915_displayport_test_data_fops},
5054 {"i915_dp_test_type", &i915_displayport_test_type_fops},
5055 {"i915_dp_test_active", &i915_displayport_test_active_fops}
34b9674c
DV		 5056};
5057
07144428
DL		 5058void intel_display_crc_init(struct drm_device *dev)
5059{
5060 struct drm_i915_private *dev_priv = dev->dev_private;
b378360e 5061 enum pipe pipe;
07144428 5062
055e393f 5063 for_each_pipe(dev_priv, pipe) {
b378360e 5064 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
07144428 5065
d538bbdf
DL		 5066 pipe_crc->opened = false;
5067 spin_lock_init(&pipe_crc->lock);
07144428
DL		 5068 init_waitqueue_head(&pipe_crc->wq);
5069 }
5070}
5071
27c202ad 5072int i915_debugfs_init(struct drm_minor *minor)
2017263e 5073{
34b9674c 5074 int ret, i;
f3cd474b 5075
6d794d42 5076 ret = i915_forcewake_create(minor->debugfs_root, minor);
358733e9
JB		 5077 if (ret)
5078 return ret;
6a9c308d 5079
07144428
DL		 5080 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5081 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
5082 if (ret)
5083 return ret;
5084 }
5085
34b9674c
DV		 5086 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5087 ret = i915_debugfs_create(minor->debugfs_root, minor,
5088 i915_debugfs_files[i].name,
5089 i915_debugfs_files[i].fops);
5090 if (ret)
5091 return ret;
5092 }
40633219 5093
27c202ad
BG		 5094 return drm_debugfs_create_files(i915_debugfs_list,
5095 I915_DEBUGFS_ENTRIES,
2017263e
BG		 5096 minor->debugfs_root, minor);
5097}
5098
27c202ad 5099void i915_debugfs_cleanup(struct drm_minor *minor)
2017263e 5100{
34b9674c
DV		 5101 int i;
5102
27c202ad
BG		 5103 drm_debugfs_remove_files(i915_debugfs_list,
5104 I915_DEBUGFS_ENTRIES, minor);
07144428 5105
6d794d42
BW		 5106 drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
5107 1, minor);
07144428 5108
e309a997 5109 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
07144428
DL		 5110 struct drm_info_list *info_list =
5111 (struct drm_info_list *)&i915_pipe_crc_data[i];
5112
5113 drm_debugfs_remove_files(info_list, 1, minor);
5114 }
5115
34b9674c
DV		 5116 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5117 struct drm_info_list *info_list =
5118 (struct drm_info_list *) i915_debugfs_files[i].fops;
5119
5120 drm_debugfs_remove_files(info_list, 1, minor);
5121 }
2017263e 5122}
aa7471d2
JN		 5123
5124struct dpcd_block {
5125 /* DPCD dump start address. */
5126 unsigned int offset;
5127 /* DPCD dump end address, inclusive. If unset, .size will be used. */
5128 unsigned int end;
5129 /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */
5130 size_t size;
5131 /* Only valid for eDP. */
5132 bool edp;
5133};
5134
5135static const struct dpcd_block i915_dpcd_debug[] = {
5136 { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE },
5137 { .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS },
5138 { .offset = DP_DOWNSTREAM_PORT_0, .size = 16 },
5139 { .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET },
5140 { .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 },
5141 { .offset = DP_SET_POWER },
5142 { .offset = DP_EDP_DPCD_REV },
5143 { .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 },
5144 { .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB },
5145 { .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET },
5146};
5147
5148static int i915_dpcd_show(struct seq_file *m, void *data)
5149{
5150 struct drm_connector *connector = m->private;
5151 struct intel_dp *intel_dp =
5152 enc_to_intel_dp(&intel_attached_encoder(connector)->base);
5153 uint8_t buf[16];
5154 ssize_t err;
5155 int i;
5156
5c1a8875
MK		 5157 if (connector->status != connector_status_connected)
5158 return -ENODEV;
5159
aa7471d2
JN		 5160 for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) {
5161 const struct dpcd_block *b = &i915_dpcd_debug[i];
5162 size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1);
5163
5164 if (b->edp &&
5165 connector->connector_type != DRM_MODE_CONNECTOR_eDP)
5166 continue;
5167
5168 /* low tech for now */
5169 if (WARN_ON(size > sizeof(buf)))
5170 continue;
5171
5172 err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size);
5173 if (err <= 0) {
5174 DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n",
5175 size, b->offset, err);
5176 continue;
5177 }
5178
5179 seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf);
b3f9d7d7 5180 }
aa7471d2
JN		 5181
5182 return 0;
5183}
5184
5185static int i915_dpcd_open(struct inode *inode, struct file *file)
5186{
5187 return single_open(file, i915_dpcd_show, inode->i_private);
5188}
5189
5190static const struct file_operations i915_dpcd_fops = {
5191 .owner = THIS_MODULE,
5192 .open = i915_dpcd_open,
5193 .read = seq_read,
5194 .llseek = seq_lseek,
5195 .release = single_release,
5196};
5197
5198/**
5199 * i915_debugfs_connector_add - add i915 specific connector debugfs files
5200 * @connector: pointer to a registered drm_connector
5201 *
5202 * Cleanup will be done by drm_connector_unregister() through a call to
5203 * drm_debugfs_connector_remove().
5204 *
5205 * Returns 0 on success, negative error codes on error.
5206 */
5207int i915_debugfs_connector_add(struct drm_connector *connector)
5208{
5209 struct dentry *root = connector->debugfs_entry;
5210
5211 /* The connector must have been registered beforehands. */
5212 if (!root)
5213 return -ENODEV;
5214
5215 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
5216 connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5217 debugfs_create_file("i915_dpcd", S_IRUGO, root, connector,
5218 &i915_dpcd_fops);
5219
5220 return 0;
5221}
Linux kernel - Deliverables
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