Commit | Line | Data |
---|---|---|
2017263e BG |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Keith Packard <keithp@keithp.com> | |
26 | * | |
27 | */ | |
28 | ||
29 | #include <linux/seq_file.h> | |
f3cd474b | 30 | #include <linux/debugfs.h> |
5a0e3ad6 | 31 | #include <linux/slab.h> |
2d1a8a48 | 32 | #include <linux/export.h> |
2017263e BG |
33 | #include "drmP.h" |
34 | #include "drm.h" | |
4e5359cd | 35 | #include "intel_drv.h" |
e5c65260 | 36 | #include "intel_ringbuffer.h" |
2017263e BG |
37 | #include "i915_drm.h" |
38 | #include "i915_drv.h" | |
39 | ||
40 | #define DRM_I915_RING_DEBUG 1 | |
41 | ||
42 | ||
43 | #if defined(CONFIG_DEBUG_FS) | |
44 | ||
f13d3f73 | 45 | enum { |
69dc4987 | 46 | ACTIVE_LIST, |
f13d3f73 CW |
47 | FLUSHING_LIST, |
48 | INACTIVE_LIST, | |
d21d5975 CW |
49 | PINNED_LIST, |
50 | DEFERRED_FREE_LIST, | |
f13d3f73 | 51 | }; |
2017263e | 52 | |
70d39fe4 CW |
53 | static const char *yesno(int v) |
54 | { | |
55 | return v ? "yes" : "no"; | |
56 | } | |
57 | ||
58 | static int i915_capabilities(struct seq_file *m, void *data) | |
59 | { | |
60 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
61 | struct drm_device *dev = node->minor->dev; | |
62 | const struct intel_device_info *info = INTEL_INFO(dev); | |
63 | ||
64 | seq_printf(m, "gen: %d\n", info->gen); | |
03d00ac5 | 65 | seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev)); |
70d39fe4 CW |
66 | #define B(x) seq_printf(m, #x ": %s\n", yesno(info->x)) |
67 | B(is_mobile); | |
70d39fe4 CW |
68 | B(is_i85x); |
69 | B(is_i915g); | |
70d39fe4 | 70 | B(is_i945gm); |
70d39fe4 CW |
71 | B(is_g33); |
72 | B(need_gfx_hws); | |
73 | B(is_g4x); | |
74 | B(is_pineview); | |
75 | B(is_broadwater); | |
76 | B(is_crestline); | |
70d39fe4 | 77 | B(has_fbc); |
70d39fe4 CW |
78 | B(has_pipe_cxsr); |
79 | B(has_hotplug); | |
80 | B(cursor_needs_physical); | |
81 | B(has_overlay); | |
82 | B(overlay_needs_physical); | |
a6c45cf0 | 83 | B(supports_tv); |
549f7365 CW |
84 | B(has_bsd_ring); |
85 | B(has_blt_ring); | |
3d29b842 | 86 | B(has_llc); |
70d39fe4 CW |
87 | #undef B |
88 | ||
89 | return 0; | |
90 | } | |
2017263e | 91 | |
05394f39 | 92 | static const char *get_pin_flag(struct drm_i915_gem_object *obj) |
a6172a80 | 93 | { |
05394f39 | 94 | if (obj->user_pin_count > 0) |
a6172a80 | 95 | return "P"; |
05394f39 | 96 | else if (obj->pin_count > 0) |
a6172a80 CW |
97 | return "p"; |
98 | else | |
99 | return " "; | |
100 | } | |
101 | ||
05394f39 | 102 | static const char *get_tiling_flag(struct drm_i915_gem_object *obj) |
a6172a80 | 103 | { |
0206e353 AJ |
104 | switch (obj->tiling_mode) { |
105 | default: | |
106 | case I915_TILING_NONE: return " "; | |
107 | case I915_TILING_X: return "X"; | |
108 | case I915_TILING_Y: return "Y"; | |
109 | } | |
a6172a80 CW |
110 | } |
111 | ||
93dfb40c | 112 | static const char *cache_level_str(int type) |
08c18323 CW |
113 | { |
114 | switch (type) { | |
93dfb40c CW |
115 | case I915_CACHE_NONE: return " uncached"; |
116 | case I915_CACHE_LLC: return " snooped (LLC)"; | |
117 | case I915_CACHE_LLC_MLC: return " snooped (LLC+MLC)"; | |
08c18323 CW |
118 | default: return ""; |
119 | } | |
120 | } | |
121 | ||
37811fcc CW |
122 | static void |
123 | describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj) | |
124 | { | |
a05a5862 | 125 | seq_printf(m, "%p: %s%s %8zdKiB %04x %04x %d %d%s%s%s", |
37811fcc CW |
126 | &obj->base, |
127 | get_pin_flag(obj), | |
128 | get_tiling_flag(obj), | |
a05a5862 | 129 | obj->base.size / 1024, |
37811fcc CW |
130 | obj->base.read_domains, |
131 | obj->base.write_domain, | |
132 | obj->last_rendering_seqno, | |
caea7476 | 133 | obj->last_fenced_seqno, |
93dfb40c | 134 | cache_level_str(obj->cache_level), |
37811fcc CW |
135 | obj->dirty ? " dirty" : "", |
136 | obj->madv == I915_MADV_DONTNEED ? " purgeable" : ""); | |
137 | if (obj->base.name) | |
138 | seq_printf(m, " (name: %d)", obj->base.name); | |
139 | if (obj->fence_reg != I915_FENCE_REG_NONE) | |
140 | seq_printf(m, " (fence: %d)", obj->fence_reg); | |
141 | if (obj->gtt_space != NULL) | |
a00b10c3 CW |
142 | seq_printf(m, " (gtt offset: %08x, size: %08x)", |
143 | obj->gtt_offset, (unsigned int)obj->gtt_space->size); | |
6299f992 CW |
144 | if (obj->pin_mappable || obj->fault_mappable) { |
145 | char s[3], *t = s; | |
146 | if (obj->pin_mappable) | |
147 | *t++ = 'p'; | |
148 | if (obj->fault_mappable) | |
149 | *t++ = 'f'; | |
150 | *t = '\0'; | |
151 | seq_printf(m, " (%s mappable)", s); | |
152 | } | |
69dc4987 CW |
153 | if (obj->ring != NULL) |
154 | seq_printf(m, " (%s)", obj->ring->name); | |
37811fcc CW |
155 | } |
156 | ||
433e12f7 | 157 | static int i915_gem_object_list_info(struct seq_file *m, void *data) |
2017263e BG |
158 | { |
159 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
433e12f7 BG |
160 | uintptr_t list = (uintptr_t) node->info_ent->data; |
161 | struct list_head *head; | |
2017263e BG |
162 | struct drm_device *dev = node->minor->dev; |
163 | drm_i915_private_t *dev_priv = dev->dev_private; | |
05394f39 | 164 | struct drm_i915_gem_object *obj; |
8f2480fb CW |
165 | size_t total_obj_size, total_gtt_size; |
166 | int count, ret; | |
de227ef0 CW |
167 | |
168 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
169 | if (ret) | |
170 | return ret; | |
2017263e | 171 | |
433e12f7 BG |
172 | switch (list) { |
173 | case ACTIVE_LIST: | |
174 | seq_printf(m, "Active:\n"); | |
69dc4987 | 175 | head = &dev_priv->mm.active_list; |
433e12f7 BG |
176 | break; |
177 | case INACTIVE_LIST: | |
a17458fc | 178 | seq_printf(m, "Inactive:\n"); |
433e12f7 BG |
179 | head = &dev_priv->mm.inactive_list; |
180 | break; | |
f13d3f73 CW |
181 | case PINNED_LIST: |
182 | seq_printf(m, "Pinned:\n"); | |
183 | head = &dev_priv->mm.pinned_list; | |
184 | break; | |
433e12f7 BG |
185 | case FLUSHING_LIST: |
186 | seq_printf(m, "Flushing:\n"); | |
187 | head = &dev_priv->mm.flushing_list; | |
188 | break; | |
d21d5975 CW |
189 | case DEFERRED_FREE_LIST: |
190 | seq_printf(m, "Deferred free:\n"); | |
191 | head = &dev_priv->mm.deferred_free_list; | |
192 | break; | |
433e12f7 | 193 | default: |
de227ef0 CW |
194 | mutex_unlock(&dev->struct_mutex); |
195 | return -EINVAL; | |
2017263e | 196 | } |
2017263e | 197 | |
8f2480fb | 198 | total_obj_size = total_gtt_size = count = 0; |
05394f39 | 199 | list_for_each_entry(obj, head, mm_list) { |
37811fcc | 200 | seq_printf(m, " "); |
05394f39 | 201 | describe_obj(m, obj); |
f4ceda89 | 202 | seq_printf(m, "\n"); |
05394f39 CW |
203 | total_obj_size += obj->base.size; |
204 | total_gtt_size += obj->gtt_space->size; | |
8f2480fb | 205 | count++; |
2017263e | 206 | } |
de227ef0 | 207 | mutex_unlock(&dev->struct_mutex); |
5e118f41 | 208 | |
8f2480fb CW |
209 | seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n", |
210 | count, total_obj_size, total_gtt_size); | |
2017263e BG |
211 | return 0; |
212 | } | |
213 | ||
6299f992 CW |
214 | #define count_objects(list, member) do { \ |
215 | list_for_each_entry(obj, list, member) { \ | |
216 | size += obj->gtt_space->size; \ | |
217 | ++count; \ | |
218 | if (obj->map_and_fenceable) { \ | |
219 | mappable_size += obj->gtt_space->size; \ | |
220 | ++mappable_count; \ | |
221 | } \ | |
222 | } \ | |
0206e353 | 223 | } while (0) |
6299f992 | 224 | |
73aa808f CW |
225 | static int i915_gem_object_info(struct seq_file *m, void* data) |
226 | { | |
227 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
228 | struct drm_device *dev = node->minor->dev; | |
229 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6299f992 CW |
230 | u32 count, mappable_count; |
231 | size_t size, mappable_size; | |
232 | struct drm_i915_gem_object *obj; | |
73aa808f CW |
233 | int ret; |
234 | ||
235 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
236 | if (ret) | |
237 | return ret; | |
238 | ||
6299f992 CW |
239 | seq_printf(m, "%u objects, %zu bytes\n", |
240 | dev_priv->mm.object_count, | |
241 | dev_priv->mm.object_memory); | |
242 | ||
243 | size = count = mappable_size = mappable_count = 0; | |
244 | count_objects(&dev_priv->mm.gtt_list, gtt_list); | |
245 | seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n", | |
246 | count, mappable_count, size, mappable_size); | |
247 | ||
248 | size = count = mappable_size = mappable_count = 0; | |
249 | count_objects(&dev_priv->mm.active_list, mm_list); | |
250 | count_objects(&dev_priv->mm.flushing_list, mm_list); | |
251 | seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n", | |
252 | count, mappable_count, size, mappable_size); | |
253 | ||
254 | size = count = mappable_size = mappable_count = 0; | |
255 | count_objects(&dev_priv->mm.pinned_list, mm_list); | |
256 | seq_printf(m, " %u [%u] pinned objects, %zu [%zu] bytes\n", | |
257 | count, mappable_count, size, mappable_size); | |
258 | ||
259 | size = count = mappable_size = mappable_count = 0; | |
260 | count_objects(&dev_priv->mm.inactive_list, mm_list); | |
261 | seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n", | |
262 | count, mappable_count, size, mappable_size); | |
263 | ||
264 | size = count = mappable_size = mappable_count = 0; | |
265 | count_objects(&dev_priv->mm.deferred_free_list, mm_list); | |
266 | seq_printf(m, " %u [%u] freed objects, %zu [%zu] bytes\n", | |
267 | count, mappable_count, size, mappable_size); | |
268 | ||
269 | size = count = mappable_size = mappable_count = 0; | |
270 | list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) { | |
271 | if (obj->fault_mappable) { | |
272 | size += obj->gtt_space->size; | |
273 | ++count; | |
274 | } | |
275 | if (obj->pin_mappable) { | |
276 | mappable_size += obj->gtt_space->size; | |
277 | ++mappable_count; | |
278 | } | |
279 | } | |
280 | seq_printf(m, "%u pinned mappable objects, %zu bytes\n", | |
281 | mappable_count, mappable_size); | |
282 | seq_printf(m, "%u fault mappable objects, %zu bytes\n", | |
283 | count, size); | |
284 | ||
285 | seq_printf(m, "%zu [%zu] gtt total\n", | |
286 | dev_priv->mm.gtt_total, dev_priv->mm.mappable_gtt_total); | |
73aa808f CW |
287 | |
288 | mutex_unlock(&dev->struct_mutex); | |
289 | ||
290 | return 0; | |
291 | } | |
292 | ||
08c18323 CW |
293 | static int i915_gem_gtt_info(struct seq_file *m, void* data) |
294 | { | |
295 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
296 | struct drm_device *dev = node->minor->dev; | |
297 | struct drm_i915_private *dev_priv = dev->dev_private; | |
298 | struct drm_i915_gem_object *obj; | |
299 | size_t total_obj_size, total_gtt_size; | |
300 | int count, ret; | |
301 | ||
302 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
303 | if (ret) | |
304 | return ret; | |
305 | ||
306 | total_obj_size = total_gtt_size = count = 0; | |
307 | list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) { | |
308 | seq_printf(m, " "); | |
309 | describe_obj(m, obj); | |
310 | seq_printf(m, "\n"); | |
311 | total_obj_size += obj->base.size; | |
312 | total_gtt_size += obj->gtt_space->size; | |
313 | count++; | |
314 | } | |
315 | ||
316 | mutex_unlock(&dev->struct_mutex); | |
317 | ||
318 | seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n", | |
319 | count, total_obj_size, total_gtt_size); | |
320 | ||
321 | return 0; | |
322 | } | |
323 | ||
73aa808f | 324 | |
4e5359cd SF |
325 | static int i915_gem_pageflip_info(struct seq_file *m, void *data) |
326 | { | |
327 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
328 | struct drm_device *dev = node->minor->dev; | |
329 | unsigned long flags; | |
330 | struct intel_crtc *crtc; | |
331 | ||
332 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { | |
9db4a9c7 JB |
333 | const char pipe = pipe_name(crtc->pipe); |
334 | const char plane = plane_name(crtc->plane); | |
4e5359cd SF |
335 | struct intel_unpin_work *work; |
336 | ||
337 | spin_lock_irqsave(&dev->event_lock, flags); | |
338 | work = crtc->unpin_work; | |
339 | if (work == NULL) { | |
9db4a9c7 | 340 | seq_printf(m, "No flip due on pipe %c (plane %c)\n", |
4e5359cd SF |
341 | pipe, plane); |
342 | } else { | |
343 | if (!work->pending) { | |
9db4a9c7 | 344 | seq_printf(m, "Flip queued on pipe %c (plane %c)\n", |
4e5359cd SF |
345 | pipe, plane); |
346 | } else { | |
9db4a9c7 | 347 | seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n", |
4e5359cd SF |
348 | pipe, plane); |
349 | } | |
350 | if (work->enable_stall_check) | |
351 | seq_printf(m, "Stall check enabled, "); | |
352 | else | |
353 | seq_printf(m, "Stall check waiting for page flip ioctl, "); | |
354 | seq_printf(m, "%d prepares\n", work->pending); | |
355 | ||
356 | if (work->old_fb_obj) { | |
05394f39 CW |
357 | struct drm_i915_gem_object *obj = work->old_fb_obj; |
358 | if (obj) | |
359 | seq_printf(m, "Old framebuffer gtt_offset 0x%08x\n", obj->gtt_offset); | |
4e5359cd SF |
360 | } |
361 | if (work->pending_flip_obj) { | |
05394f39 CW |
362 | struct drm_i915_gem_object *obj = work->pending_flip_obj; |
363 | if (obj) | |
364 | seq_printf(m, "New framebuffer gtt_offset 0x%08x\n", obj->gtt_offset); | |
4e5359cd SF |
365 | } |
366 | } | |
367 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
368 | } | |
369 | ||
370 | return 0; | |
371 | } | |
372 | ||
2017263e BG |
373 | static int i915_gem_request_info(struct seq_file *m, void *data) |
374 | { | |
375 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
376 | struct drm_device *dev = node->minor->dev; | |
377 | drm_i915_private_t *dev_priv = dev->dev_private; | |
378 | struct drm_i915_gem_request *gem_request; | |
c2c347a9 | 379 | int ret, count; |
de227ef0 CW |
380 | |
381 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
382 | if (ret) | |
383 | return ret; | |
2017263e | 384 | |
c2c347a9 | 385 | count = 0; |
1ec14ad3 | 386 | if (!list_empty(&dev_priv->ring[RCS].request_list)) { |
c2c347a9 CW |
387 | seq_printf(m, "Render requests:\n"); |
388 | list_for_each_entry(gem_request, | |
1ec14ad3 | 389 | &dev_priv->ring[RCS].request_list, |
c2c347a9 CW |
390 | list) { |
391 | seq_printf(m, " %d @ %d\n", | |
392 | gem_request->seqno, | |
393 | (int) (jiffies - gem_request->emitted_jiffies)); | |
394 | } | |
395 | count++; | |
396 | } | |
1ec14ad3 | 397 | if (!list_empty(&dev_priv->ring[VCS].request_list)) { |
c2c347a9 CW |
398 | seq_printf(m, "BSD requests:\n"); |
399 | list_for_each_entry(gem_request, | |
1ec14ad3 | 400 | &dev_priv->ring[VCS].request_list, |
c2c347a9 CW |
401 | list) { |
402 | seq_printf(m, " %d @ %d\n", | |
403 | gem_request->seqno, | |
404 | (int) (jiffies - gem_request->emitted_jiffies)); | |
405 | } | |
406 | count++; | |
407 | } | |
1ec14ad3 | 408 | if (!list_empty(&dev_priv->ring[BCS].request_list)) { |
c2c347a9 CW |
409 | seq_printf(m, "BLT requests:\n"); |
410 | list_for_each_entry(gem_request, | |
1ec14ad3 | 411 | &dev_priv->ring[BCS].request_list, |
c2c347a9 CW |
412 | list) { |
413 | seq_printf(m, " %d @ %d\n", | |
414 | gem_request->seqno, | |
415 | (int) (jiffies - gem_request->emitted_jiffies)); | |
416 | } | |
417 | count++; | |
2017263e | 418 | } |
de227ef0 CW |
419 | mutex_unlock(&dev->struct_mutex); |
420 | ||
c2c347a9 CW |
421 | if (count == 0) |
422 | seq_printf(m, "No requests\n"); | |
423 | ||
2017263e BG |
424 | return 0; |
425 | } | |
426 | ||
b2223497 CW |
427 | static void i915_ring_seqno_info(struct seq_file *m, |
428 | struct intel_ring_buffer *ring) | |
429 | { | |
430 | if (ring->get_seqno) { | |
431 | seq_printf(m, "Current sequence (%s): %d\n", | |
432 | ring->name, ring->get_seqno(ring)); | |
433 | seq_printf(m, "Waiter sequence (%s): %d\n", | |
434 | ring->name, ring->waiting_seqno); | |
435 | seq_printf(m, "IRQ sequence (%s): %d\n", | |
436 | ring->name, ring->irq_seqno); | |
437 | } | |
438 | } | |
439 | ||
2017263e BG |
440 | static int i915_gem_seqno_info(struct seq_file *m, void *data) |
441 | { | |
442 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
443 | struct drm_device *dev = node->minor->dev; | |
444 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1ec14ad3 | 445 | int ret, i; |
de227ef0 CW |
446 | |
447 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
448 | if (ret) | |
449 | return ret; | |
2017263e | 450 | |
1ec14ad3 CW |
451 | for (i = 0; i < I915_NUM_RINGS; i++) |
452 | i915_ring_seqno_info(m, &dev_priv->ring[i]); | |
de227ef0 CW |
453 | |
454 | mutex_unlock(&dev->struct_mutex); | |
455 | ||
2017263e BG |
456 | return 0; |
457 | } | |
458 | ||
459 | ||
460 | static int i915_interrupt_info(struct seq_file *m, void *data) | |
461 | { | |
462 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
463 | struct drm_device *dev = node->minor->dev; | |
464 | drm_i915_private_t *dev_priv = dev->dev_private; | |
9db4a9c7 | 465 | int ret, i, pipe; |
de227ef0 CW |
466 | |
467 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
468 | if (ret) | |
469 | return ret; | |
2017263e | 470 | |
7e231dbe JB |
471 | if (IS_VALLEYVIEW(dev)) { |
472 | seq_printf(m, "Display IER:\t%08x\n", | |
473 | I915_READ(VLV_IER)); | |
474 | seq_printf(m, "Display IIR:\t%08x\n", | |
475 | I915_READ(VLV_IIR)); | |
476 | seq_printf(m, "Display IIR_RW:\t%08x\n", | |
477 | I915_READ(VLV_IIR_RW)); | |
478 | seq_printf(m, "Display IMR:\t%08x\n", | |
479 | I915_READ(VLV_IMR)); | |
480 | for_each_pipe(pipe) | |
481 | seq_printf(m, "Pipe %c stat:\t%08x\n", | |
482 | pipe_name(pipe), | |
483 | I915_READ(PIPESTAT(pipe))); | |
484 | ||
485 | seq_printf(m, "Master IER:\t%08x\n", | |
486 | I915_READ(VLV_MASTER_IER)); | |
487 | ||
488 | seq_printf(m, "Render IER:\t%08x\n", | |
489 | I915_READ(GTIER)); | |
490 | seq_printf(m, "Render IIR:\t%08x\n", | |
491 | I915_READ(GTIIR)); | |
492 | seq_printf(m, "Render IMR:\t%08x\n", | |
493 | I915_READ(GTIMR)); | |
494 | ||
495 | seq_printf(m, "PM IER:\t\t%08x\n", | |
496 | I915_READ(GEN6_PMIER)); | |
497 | seq_printf(m, "PM IIR:\t\t%08x\n", | |
498 | I915_READ(GEN6_PMIIR)); | |
499 | seq_printf(m, "PM IMR:\t\t%08x\n", | |
500 | I915_READ(GEN6_PMIMR)); | |
501 | ||
502 | seq_printf(m, "Port hotplug:\t%08x\n", | |
503 | I915_READ(PORT_HOTPLUG_EN)); | |
504 | seq_printf(m, "DPFLIPSTAT:\t%08x\n", | |
505 | I915_READ(VLV_DPFLIPSTAT)); | |
506 | seq_printf(m, "DPINVGTT:\t%08x\n", | |
507 | I915_READ(DPINVGTT)); | |
508 | ||
509 | } else if (!HAS_PCH_SPLIT(dev)) { | |
5f6a1695 ZW |
510 | seq_printf(m, "Interrupt enable: %08x\n", |
511 | I915_READ(IER)); | |
512 | seq_printf(m, "Interrupt identity: %08x\n", | |
513 | I915_READ(IIR)); | |
514 | seq_printf(m, "Interrupt mask: %08x\n", | |
515 | I915_READ(IMR)); | |
9db4a9c7 JB |
516 | for_each_pipe(pipe) |
517 | seq_printf(m, "Pipe %c stat: %08x\n", | |
518 | pipe_name(pipe), | |
519 | I915_READ(PIPESTAT(pipe))); | |
5f6a1695 ZW |
520 | } else { |
521 | seq_printf(m, "North Display Interrupt enable: %08x\n", | |
522 | I915_READ(DEIER)); | |
523 | seq_printf(m, "North Display Interrupt identity: %08x\n", | |
524 | I915_READ(DEIIR)); | |
525 | seq_printf(m, "North Display Interrupt mask: %08x\n", | |
526 | I915_READ(DEIMR)); | |
527 | seq_printf(m, "South Display Interrupt enable: %08x\n", | |
528 | I915_READ(SDEIER)); | |
529 | seq_printf(m, "South Display Interrupt identity: %08x\n", | |
530 | I915_READ(SDEIIR)); | |
531 | seq_printf(m, "South Display Interrupt mask: %08x\n", | |
532 | I915_READ(SDEIMR)); | |
533 | seq_printf(m, "Graphics Interrupt enable: %08x\n", | |
534 | I915_READ(GTIER)); | |
535 | seq_printf(m, "Graphics Interrupt identity: %08x\n", | |
536 | I915_READ(GTIIR)); | |
537 | seq_printf(m, "Graphics Interrupt mask: %08x\n", | |
538 | I915_READ(GTIMR)); | |
539 | } | |
2017263e BG |
540 | seq_printf(m, "Interrupts received: %d\n", |
541 | atomic_read(&dev_priv->irq_received)); | |
9862e600 | 542 | for (i = 0; i < I915_NUM_RINGS; i++) { |
da64c6fc | 543 | if (IS_GEN6(dev) || IS_GEN7(dev)) { |
9862e600 CW |
544 | seq_printf(m, "Graphics Interrupt mask (%s): %08x\n", |
545 | dev_priv->ring[i].name, | |
546 | I915_READ_IMR(&dev_priv->ring[i])); | |
547 | } | |
1ec14ad3 | 548 | i915_ring_seqno_info(m, &dev_priv->ring[i]); |
9862e600 | 549 | } |
de227ef0 CW |
550 | mutex_unlock(&dev->struct_mutex); |
551 | ||
2017263e BG |
552 | return 0; |
553 | } | |
554 | ||
a6172a80 CW |
555 | static int i915_gem_fence_regs_info(struct seq_file *m, void *data) |
556 | { | |
557 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
558 | struct drm_device *dev = node->minor->dev; | |
559 | drm_i915_private_t *dev_priv = dev->dev_private; | |
de227ef0 CW |
560 | int i, ret; |
561 | ||
562 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
563 | if (ret) | |
564 | return ret; | |
a6172a80 CW |
565 | |
566 | seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start); | |
567 | seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs); | |
568 | for (i = 0; i < dev_priv->num_fence_regs; i++) { | |
05394f39 | 569 | struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj; |
a6172a80 | 570 | |
c2c347a9 CW |
571 | seq_printf(m, "Fenced object[%2d] = ", i); |
572 | if (obj == NULL) | |
573 | seq_printf(m, "unused"); | |
574 | else | |
05394f39 | 575 | describe_obj(m, obj); |
c2c347a9 | 576 | seq_printf(m, "\n"); |
a6172a80 CW |
577 | } |
578 | ||
05394f39 | 579 | mutex_unlock(&dev->struct_mutex); |
a6172a80 CW |
580 | return 0; |
581 | } | |
582 | ||
2017263e BG |
583 | static int i915_hws_info(struct seq_file *m, void *data) |
584 | { | |
585 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
586 | struct drm_device *dev = node->minor->dev; | |
587 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4066c0ae | 588 | struct intel_ring_buffer *ring; |
311bd68e | 589 | const volatile u32 __iomem *hws; |
4066c0ae CW |
590 | int i; |
591 | ||
1ec14ad3 | 592 | ring = &dev_priv->ring[(uintptr_t)node->info_ent->data]; |
311bd68e | 593 | hws = (volatile u32 __iomem *)ring->status_page.page_addr; |
2017263e BG |
594 | if (hws == NULL) |
595 | return 0; | |
596 | ||
597 | for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) { | |
598 | seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n", | |
599 | i * 4, | |
600 | hws[i], hws[i + 1], hws[i + 2], hws[i + 3]); | |
601 | } | |
602 | return 0; | |
603 | } | |
604 | ||
6911a9b8 BG |
605 | static int i915_ringbuffer_data(struct seq_file *m, void *data) |
606 | { | |
607 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
608 | struct drm_device *dev = node->minor->dev; | |
609 | drm_i915_private_t *dev_priv = dev->dev_private; | |
c2c347a9 | 610 | struct intel_ring_buffer *ring; |
de227ef0 CW |
611 | int ret; |
612 | ||
613 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
614 | if (ret) | |
615 | return ret; | |
6911a9b8 | 616 | |
1ec14ad3 | 617 | ring = &dev_priv->ring[(uintptr_t)node->info_ent->data]; |
05394f39 | 618 | if (!ring->obj) { |
6911a9b8 | 619 | seq_printf(m, "No ringbuffer setup\n"); |
de227ef0 | 620 | } else { |
311bd68e | 621 | const u8 __iomem *virt = ring->virtual_start; |
de227ef0 | 622 | uint32_t off; |
6911a9b8 | 623 | |
c2c347a9 | 624 | for (off = 0; off < ring->size; off += 4) { |
de227ef0 CW |
625 | uint32_t *ptr = (uint32_t *)(virt + off); |
626 | seq_printf(m, "%08x : %08x\n", off, *ptr); | |
627 | } | |
6911a9b8 | 628 | } |
de227ef0 | 629 | mutex_unlock(&dev->struct_mutex); |
6911a9b8 BG |
630 | |
631 | return 0; | |
632 | } | |
633 | ||
634 | static int i915_ringbuffer_info(struct seq_file *m, void *data) | |
635 | { | |
636 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
637 | struct drm_device *dev = node->minor->dev; | |
638 | drm_i915_private_t *dev_priv = dev->dev_private; | |
c2c347a9 | 639 | struct intel_ring_buffer *ring; |
616fdb5a | 640 | int ret; |
c2c347a9 | 641 | |
1ec14ad3 | 642 | ring = &dev_priv->ring[(uintptr_t)node->info_ent->data]; |
c2c347a9 | 643 | if (ring->size == 0) |
1ec14ad3 | 644 | return 0; |
6911a9b8 | 645 | |
616fdb5a BW |
646 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
647 | if (ret) | |
648 | return ret; | |
649 | ||
c2c347a9 CW |
650 | seq_printf(m, "Ring %s:\n", ring->name); |
651 | seq_printf(m, " Head : %08x\n", I915_READ_HEAD(ring) & HEAD_ADDR); | |
652 | seq_printf(m, " Tail : %08x\n", I915_READ_TAIL(ring) & TAIL_ADDR); | |
653 | seq_printf(m, " Size : %08x\n", ring->size); | |
654 | seq_printf(m, " Active : %08x\n", intel_ring_get_active_head(ring)); | |
1ec14ad3 | 655 | seq_printf(m, " NOPID : %08x\n", I915_READ_NOPID(ring)); |
48467a92 | 656 | if (IS_GEN6(dev) || IS_GEN7(dev)) { |
1ec14ad3 CW |
657 | seq_printf(m, " Sync 0 : %08x\n", I915_READ_SYNC_0(ring)); |
658 | seq_printf(m, " Sync 1 : %08x\n", I915_READ_SYNC_1(ring)); | |
659 | } | |
c2c347a9 CW |
660 | seq_printf(m, " Control : %08x\n", I915_READ_CTL(ring)); |
661 | seq_printf(m, " Start : %08x\n", I915_READ_START(ring)); | |
6911a9b8 | 662 | |
616fdb5a BW |
663 | mutex_unlock(&dev->struct_mutex); |
664 | ||
6911a9b8 BG |
665 | return 0; |
666 | } | |
667 | ||
e5c65260 CW |
668 | static const char *ring_str(int ring) |
669 | { | |
670 | switch (ring) { | |
96154f2f DV |
671 | case RCS: return "render"; |
672 | case VCS: return "bsd"; | |
673 | case BCS: return "blt"; | |
e5c65260 CW |
674 | default: return ""; |
675 | } | |
676 | } | |
677 | ||
9df30794 CW |
678 | static const char *pin_flag(int pinned) |
679 | { | |
680 | if (pinned > 0) | |
681 | return " P"; | |
682 | else if (pinned < 0) | |
683 | return " p"; | |
684 | else | |
685 | return ""; | |
686 | } | |
687 | ||
688 | static const char *tiling_flag(int tiling) | |
689 | { | |
690 | switch (tiling) { | |
691 | default: | |
692 | case I915_TILING_NONE: return ""; | |
693 | case I915_TILING_X: return " X"; | |
694 | case I915_TILING_Y: return " Y"; | |
695 | } | |
696 | } | |
697 | ||
698 | static const char *dirty_flag(int dirty) | |
699 | { | |
700 | return dirty ? " dirty" : ""; | |
701 | } | |
702 | ||
703 | static const char *purgeable_flag(int purgeable) | |
704 | { | |
705 | return purgeable ? " purgeable" : ""; | |
706 | } | |
707 | ||
c724e8a9 CW |
708 | static void print_error_buffers(struct seq_file *m, |
709 | const char *name, | |
710 | struct drm_i915_error_buffer *err, | |
711 | int count) | |
712 | { | |
713 | seq_printf(m, "%s [%d]:\n", name, count); | |
714 | ||
715 | while (count--) { | |
96154f2f | 716 | seq_printf(m, " %08x %8u %04x %04x %08x%s%s%s%s%s%s%s", |
c724e8a9 CW |
717 | err->gtt_offset, |
718 | err->size, | |
719 | err->read_domains, | |
720 | err->write_domain, | |
721 | err->seqno, | |
722 | pin_flag(err->pinned), | |
723 | tiling_flag(err->tiling), | |
724 | dirty_flag(err->dirty), | |
725 | purgeable_flag(err->purgeable), | |
96154f2f | 726 | err->ring != -1 ? " " : "", |
a779e5ab | 727 | ring_str(err->ring), |
93dfb40c | 728 | cache_level_str(err->cache_level)); |
c724e8a9 CW |
729 | |
730 | if (err->name) | |
731 | seq_printf(m, " (name: %d)", err->name); | |
732 | if (err->fence_reg != I915_FENCE_REG_NONE) | |
733 | seq_printf(m, " (fence: %d)", err->fence_reg); | |
734 | ||
735 | seq_printf(m, "\n"); | |
736 | err++; | |
737 | } | |
738 | } | |
739 | ||
d27b1e0e DV |
740 | static void i915_ring_error_state(struct seq_file *m, |
741 | struct drm_device *dev, | |
742 | struct drm_i915_error_state *error, | |
743 | unsigned ring) | |
744 | { | |
ec34a01d | 745 | BUG_ON(ring >= I915_NUM_RINGS); /* shut up confused gcc */ |
d27b1e0e | 746 | seq_printf(m, "%s command stream:\n", ring_str(ring)); |
c1cd90ed DV |
747 | seq_printf(m, " HEAD: 0x%08x\n", error->head[ring]); |
748 | seq_printf(m, " TAIL: 0x%08x\n", error->tail[ring]); | |
d27b1e0e DV |
749 | seq_printf(m, " ACTHD: 0x%08x\n", error->acthd[ring]); |
750 | seq_printf(m, " IPEIR: 0x%08x\n", error->ipeir[ring]); | |
751 | seq_printf(m, " IPEHR: 0x%08x\n", error->ipehr[ring]); | |
752 | seq_printf(m, " INSTDONE: 0x%08x\n", error->instdone[ring]); | |
c1cd90ed DV |
753 | if (ring == RCS && INTEL_INFO(dev)->gen >= 4) { |
754 | seq_printf(m, " INSTDONE1: 0x%08x\n", error->instdone1); | |
755 | seq_printf(m, " BBADDR: 0x%08llx\n", error->bbaddr); | |
d27b1e0e | 756 | } |
c1cd90ed DV |
757 | if (INTEL_INFO(dev)->gen >= 4) |
758 | seq_printf(m, " INSTPS: 0x%08x\n", error->instps[ring]); | |
759 | seq_printf(m, " INSTPM: 0x%08x\n", error->instpm[ring]); | |
9d2f41fa | 760 | seq_printf(m, " FADDR: 0x%08x\n", error->faddr[ring]); |
33f3f518 | 761 | if (INTEL_INFO(dev)->gen >= 6) { |
33f3f518 | 762 | seq_printf(m, " FAULT_REG: 0x%08x\n", error->fault_reg[ring]); |
7e3b8737 DV |
763 | seq_printf(m, " SYNC_0: 0x%08x\n", |
764 | error->semaphore_mboxes[ring][0]); | |
765 | seq_printf(m, " SYNC_1: 0x%08x\n", | |
766 | error->semaphore_mboxes[ring][1]); | |
33f3f518 | 767 | } |
d27b1e0e | 768 | seq_printf(m, " seqno: 0x%08x\n", error->seqno[ring]); |
7e3b8737 DV |
769 | seq_printf(m, " ring->head: 0x%08x\n", error->cpu_ring_head[ring]); |
770 | seq_printf(m, " ring->tail: 0x%08x\n", error->cpu_ring_tail[ring]); | |
d27b1e0e DV |
771 | } |
772 | ||
63eeaf38 JB |
773 | static int i915_error_state(struct seq_file *m, void *unused) |
774 | { | |
775 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
776 | struct drm_device *dev = node->minor->dev; | |
777 | drm_i915_private_t *dev_priv = dev->dev_private; | |
778 | struct drm_i915_error_state *error; | |
779 | unsigned long flags; | |
52d39a21 | 780 | int i, j, page, offset, elt; |
63eeaf38 JB |
781 | |
782 | spin_lock_irqsave(&dev_priv->error_lock, flags); | |
783 | if (!dev_priv->first_error) { | |
784 | seq_printf(m, "no error state collected\n"); | |
785 | goto out; | |
786 | } | |
787 | ||
788 | error = dev_priv->first_error; | |
789 | ||
8a905236 JB |
790 | seq_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec, |
791 | error->time.tv_usec); | |
9df30794 | 792 | seq_printf(m, "PCI ID: 0x%04x\n", dev->pci_device); |
1d8f38f4 CW |
793 | seq_printf(m, "EIR: 0x%08x\n", error->eir); |
794 | seq_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er); | |
9df30794 | 795 | |
bf3301ab | 796 | for (i = 0; i < dev_priv->num_fence_regs; i++) |
748ebc60 CW |
797 | seq_printf(m, " fence[%d] = %08llx\n", i, error->fence[i]); |
798 | ||
33f3f518 | 799 | if (INTEL_INFO(dev)->gen >= 6) { |
d27b1e0e | 800 | seq_printf(m, "ERROR: 0x%08x\n", error->error); |
33f3f518 DV |
801 | seq_printf(m, "DONE_REG: 0x%08x\n", error->done_reg); |
802 | } | |
d27b1e0e DV |
803 | |
804 | i915_ring_error_state(m, dev, error, RCS); | |
805 | if (HAS_BLT(dev)) | |
806 | i915_ring_error_state(m, dev, error, BCS); | |
807 | if (HAS_BSD(dev)) | |
808 | i915_ring_error_state(m, dev, error, VCS); | |
809 | ||
c724e8a9 CW |
810 | if (error->active_bo) |
811 | print_error_buffers(m, "Active", | |
812 | error->active_bo, | |
813 | error->active_bo_count); | |
814 | ||
815 | if (error->pinned_bo) | |
816 | print_error_buffers(m, "Pinned", | |
817 | error->pinned_bo, | |
818 | error->pinned_bo_count); | |
9df30794 | 819 | |
52d39a21 CW |
820 | for (i = 0; i < ARRAY_SIZE(error->ring); i++) { |
821 | struct drm_i915_error_object *obj; | |
9df30794 | 822 | |
52d39a21 | 823 | if ((obj = error->ring[i].batchbuffer)) { |
bcfb2e28 CW |
824 | seq_printf(m, "%s --- gtt_offset = 0x%08x\n", |
825 | dev_priv->ring[i].name, | |
826 | obj->gtt_offset); | |
9df30794 CW |
827 | offset = 0; |
828 | for (page = 0; page < obj->page_count; page++) { | |
829 | for (elt = 0; elt < PAGE_SIZE/4; elt++) { | |
830 | seq_printf(m, "%08x : %08x\n", offset, obj->pages[page][elt]); | |
831 | offset += 4; | |
832 | } | |
833 | } | |
834 | } | |
9df30794 | 835 | |
52d39a21 CW |
836 | if (error->ring[i].num_requests) { |
837 | seq_printf(m, "%s --- %d requests\n", | |
838 | dev_priv->ring[i].name, | |
839 | error->ring[i].num_requests); | |
840 | for (j = 0; j < error->ring[i].num_requests; j++) { | |
ee4f42b1 | 841 | seq_printf(m, " seqno 0x%08x, emitted %ld, tail 0x%08x\n", |
52d39a21 | 842 | error->ring[i].requests[j].seqno, |
ee4f42b1 CW |
843 | error->ring[i].requests[j].jiffies, |
844 | error->ring[i].requests[j].tail); | |
52d39a21 CW |
845 | } |
846 | } | |
847 | ||
848 | if ((obj = error->ring[i].ringbuffer)) { | |
e2f973d5 CW |
849 | seq_printf(m, "%s --- ringbuffer = 0x%08x\n", |
850 | dev_priv->ring[i].name, | |
851 | obj->gtt_offset); | |
852 | offset = 0; | |
853 | for (page = 0; page < obj->page_count; page++) { | |
854 | for (elt = 0; elt < PAGE_SIZE/4; elt++) { | |
855 | seq_printf(m, "%08x : %08x\n", | |
856 | offset, | |
857 | obj->pages[page][elt]); | |
858 | offset += 4; | |
859 | } | |
9df30794 CW |
860 | } |
861 | } | |
862 | } | |
63eeaf38 | 863 | |
6ef3d427 CW |
864 | if (error->overlay) |
865 | intel_overlay_print_error_state(m, error->overlay); | |
866 | ||
c4a1d9e4 CW |
867 | if (error->display) |
868 | intel_display_print_error_state(m, dev, error->display); | |
869 | ||
63eeaf38 JB |
870 | out: |
871 | spin_unlock_irqrestore(&dev_priv->error_lock, flags); | |
872 | ||
873 | return 0; | |
874 | } | |
6911a9b8 | 875 | |
f97108d1 JB |
876 | static int i915_rstdby_delays(struct seq_file *m, void *unused) |
877 | { | |
878 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
879 | struct drm_device *dev = node->minor->dev; | |
880 | drm_i915_private_t *dev_priv = dev->dev_private; | |
616fdb5a BW |
881 | u16 crstanddelay; |
882 | int ret; | |
883 | ||
884 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
885 | if (ret) | |
886 | return ret; | |
887 | ||
888 | crstanddelay = I915_READ16(CRSTANDVID); | |
889 | ||
890 | mutex_unlock(&dev->struct_mutex); | |
f97108d1 JB |
891 | |
892 | seq_printf(m, "w/ctx: %d, w/o ctx: %d\n", (crstanddelay >> 8) & 0x3f, (crstanddelay & 0x3f)); | |
893 | ||
894 | return 0; | |
895 | } | |
896 | ||
897 | static int i915_cur_delayinfo(struct seq_file *m, void *unused) | |
898 | { | |
899 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
900 | struct drm_device *dev = node->minor->dev; | |
901 | drm_i915_private_t *dev_priv = dev->dev_private; | |
d1ebd816 | 902 | int ret; |
3b8d8d91 JB |
903 | |
904 | if (IS_GEN5(dev)) { | |
905 | u16 rgvswctl = I915_READ16(MEMSWCTL); | |
906 | u16 rgvstat = I915_READ16(MEMSTAT_ILK); | |
907 | ||
908 | seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf); | |
909 | seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f); | |
910 | seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >> | |
911 | MEMSTAT_VID_SHIFT); | |
912 | seq_printf(m, "Current P-state: %d\n", | |
913 | (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT); | |
1c70c0ce | 914 | } else if (IS_GEN6(dev) || IS_GEN7(dev)) { |
3b8d8d91 JB |
915 | u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS); |
916 | u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS); | |
917 | u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); | |
ccab5c82 JB |
918 | u32 rpstat; |
919 | u32 rpupei, rpcurup, rpprevup; | |
920 | u32 rpdownei, rpcurdown, rpprevdown; | |
3b8d8d91 JB |
921 | int max_freq; |
922 | ||
923 | /* RPSTAT1 is in the GT power well */ | |
d1ebd816 BW |
924 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
925 | if (ret) | |
926 | return ret; | |
927 | ||
fcca7926 | 928 | gen6_gt_force_wake_get(dev_priv); |
3b8d8d91 | 929 | |
ccab5c82 JB |
930 | rpstat = I915_READ(GEN6_RPSTAT1); |
931 | rpupei = I915_READ(GEN6_RP_CUR_UP_EI); | |
932 | rpcurup = I915_READ(GEN6_RP_CUR_UP); | |
933 | rpprevup = I915_READ(GEN6_RP_PREV_UP); | |
934 | rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI); | |
935 | rpcurdown = I915_READ(GEN6_RP_CUR_DOWN); | |
936 | rpprevdown = I915_READ(GEN6_RP_PREV_DOWN); | |
937 | ||
d1ebd816 BW |
938 | gen6_gt_force_wake_put(dev_priv); |
939 | mutex_unlock(&dev->struct_mutex); | |
940 | ||
3b8d8d91 | 941 | seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status); |
ccab5c82 | 942 | seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat); |
3b8d8d91 JB |
943 | seq_printf(m, "Render p-state ratio: %d\n", |
944 | (gt_perf_status & 0xff00) >> 8); | |
945 | seq_printf(m, "Render p-state VID: %d\n", | |
946 | gt_perf_status & 0xff); | |
947 | seq_printf(m, "Render p-state limit: %d\n", | |
948 | rp_state_limits & 0xff); | |
ccab5c82 | 949 | seq_printf(m, "CAGF: %dMHz\n", ((rpstat & GEN6_CAGF_MASK) >> |
e281fcaa | 950 | GEN6_CAGF_SHIFT) * 50); |
ccab5c82 JB |
951 | seq_printf(m, "RP CUR UP EI: %dus\n", rpupei & |
952 | GEN6_CURICONT_MASK); | |
953 | seq_printf(m, "RP CUR UP: %dus\n", rpcurup & | |
954 | GEN6_CURBSYTAVG_MASK); | |
955 | seq_printf(m, "RP PREV UP: %dus\n", rpprevup & | |
956 | GEN6_CURBSYTAVG_MASK); | |
957 | seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei & | |
958 | GEN6_CURIAVG_MASK); | |
959 | seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown & | |
960 | GEN6_CURBSYTAVG_MASK); | |
961 | seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown & | |
962 | GEN6_CURBSYTAVG_MASK); | |
3b8d8d91 JB |
963 | |
964 | max_freq = (rp_state_cap & 0xff0000) >> 16; | |
965 | seq_printf(m, "Lowest (RPN) frequency: %dMHz\n", | |
e281fcaa | 966 | max_freq * 50); |
3b8d8d91 JB |
967 | |
968 | max_freq = (rp_state_cap & 0xff00) >> 8; | |
969 | seq_printf(m, "Nominal (RP1) frequency: %dMHz\n", | |
e281fcaa | 970 | max_freq * 50); |
3b8d8d91 JB |
971 | |
972 | max_freq = rp_state_cap & 0xff; | |
973 | seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n", | |
e281fcaa | 974 | max_freq * 50); |
3b8d8d91 JB |
975 | } else { |
976 | seq_printf(m, "no P-state info available\n"); | |
977 | } | |
f97108d1 JB |
978 | |
979 | return 0; | |
980 | } | |
981 | ||
982 | static int i915_delayfreq_table(struct seq_file *m, void *unused) | |
983 | { | |
984 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
985 | struct drm_device *dev = node->minor->dev; | |
986 | drm_i915_private_t *dev_priv = dev->dev_private; | |
987 | u32 delayfreq; | |
616fdb5a BW |
988 | int ret, i; |
989 | ||
990 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
991 | if (ret) | |
992 | return ret; | |
f97108d1 JB |
993 | |
994 | for (i = 0; i < 16; i++) { | |
995 | delayfreq = I915_READ(PXVFREQ_BASE + i * 4); | |
7648fa99 JB |
996 | seq_printf(m, "P%02dVIDFREQ: 0x%08x (VID: %d)\n", i, delayfreq, |
997 | (delayfreq & PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT); | |
f97108d1 JB |
998 | } |
999 | ||
616fdb5a BW |
1000 | mutex_unlock(&dev->struct_mutex); |
1001 | ||
f97108d1 JB |
1002 | return 0; |
1003 | } | |
1004 | ||
1005 | static inline int MAP_TO_MV(int map) | |
1006 | { | |
1007 | return 1250 - (map * 25); | |
1008 | } | |
1009 | ||
1010 | static int i915_inttoext_table(struct seq_file *m, void *unused) | |
1011 | { | |
1012 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1013 | struct drm_device *dev = node->minor->dev; | |
1014 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1015 | u32 inttoext; | |
616fdb5a BW |
1016 | int ret, i; |
1017 | ||
1018 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1019 | if (ret) | |
1020 | return ret; | |
f97108d1 JB |
1021 | |
1022 | for (i = 1; i <= 32; i++) { | |
1023 | inttoext = I915_READ(INTTOEXT_BASE_ILK + i * 4); | |
1024 | seq_printf(m, "INTTOEXT%02d: 0x%08x\n", i, inttoext); | |
1025 | } | |
1026 | ||
616fdb5a BW |
1027 | mutex_unlock(&dev->struct_mutex); |
1028 | ||
f97108d1 JB |
1029 | return 0; |
1030 | } | |
1031 | ||
4d85529d | 1032 | static int ironlake_drpc_info(struct seq_file *m) |
f97108d1 JB |
1033 | { |
1034 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1035 | struct drm_device *dev = node->minor->dev; | |
1036 | drm_i915_private_t *dev_priv = dev->dev_private; | |
616fdb5a BW |
1037 | u32 rgvmodectl, rstdbyctl; |
1038 | u16 crstandvid; | |
1039 | int ret; | |
1040 | ||
1041 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1042 | if (ret) | |
1043 | return ret; | |
1044 | ||
1045 | rgvmodectl = I915_READ(MEMMODECTL); | |
1046 | rstdbyctl = I915_READ(RSTDBYCTL); | |
1047 | crstandvid = I915_READ16(CRSTANDVID); | |
1048 | ||
1049 | mutex_unlock(&dev->struct_mutex); | |
f97108d1 JB |
1050 | |
1051 | seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ? | |
1052 | "yes" : "no"); | |
1053 | seq_printf(m, "Boost freq: %d\n", | |
1054 | (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >> | |
1055 | MEMMODE_BOOST_FREQ_SHIFT); | |
1056 | seq_printf(m, "HW control enabled: %s\n", | |
1057 | rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no"); | |
1058 | seq_printf(m, "SW control enabled: %s\n", | |
1059 | rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no"); | |
1060 | seq_printf(m, "Gated voltage change: %s\n", | |
1061 | rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no"); | |
1062 | seq_printf(m, "Starting frequency: P%d\n", | |
1063 | (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT); | |
7648fa99 | 1064 | seq_printf(m, "Max P-state: P%d\n", |
f97108d1 | 1065 | (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT); |
7648fa99 JB |
1066 | seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK)); |
1067 | seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f)); | |
1068 | seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f)); | |
1069 | seq_printf(m, "Render standby enabled: %s\n", | |
1070 | (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes"); | |
88271da3 JB |
1071 | seq_printf(m, "Current RS state: "); |
1072 | switch (rstdbyctl & RSX_STATUS_MASK) { | |
1073 | case RSX_STATUS_ON: | |
1074 | seq_printf(m, "on\n"); | |
1075 | break; | |
1076 | case RSX_STATUS_RC1: | |
1077 | seq_printf(m, "RC1\n"); | |
1078 | break; | |
1079 | case RSX_STATUS_RC1E: | |
1080 | seq_printf(m, "RC1E\n"); | |
1081 | break; | |
1082 | case RSX_STATUS_RS1: | |
1083 | seq_printf(m, "RS1\n"); | |
1084 | break; | |
1085 | case RSX_STATUS_RS2: | |
1086 | seq_printf(m, "RS2 (RC6)\n"); | |
1087 | break; | |
1088 | case RSX_STATUS_RS3: | |
1089 | seq_printf(m, "RC3 (RC6+)\n"); | |
1090 | break; | |
1091 | default: | |
1092 | seq_printf(m, "unknown\n"); | |
1093 | break; | |
1094 | } | |
f97108d1 JB |
1095 | |
1096 | return 0; | |
1097 | } | |
1098 | ||
4d85529d BW |
1099 | static int gen6_drpc_info(struct seq_file *m) |
1100 | { | |
1101 | ||
1102 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1103 | struct drm_device *dev = node->minor->dev; | |
1104 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1105 | u32 rpmodectl1, gt_core_status, rcctl1; | |
93b525dc | 1106 | unsigned forcewake_count; |
4d85529d BW |
1107 | int count=0, ret; |
1108 | ||
1109 | ||
1110 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1111 | if (ret) | |
1112 | return ret; | |
1113 | ||
93b525dc DV |
1114 | spin_lock_irq(&dev_priv->gt_lock); |
1115 | forcewake_count = dev_priv->forcewake_count; | |
1116 | spin_unlock_irq(&dev_priv->gt_lock); | |
1117 | ||
1118 | if (forcewake_count) { | |
1119 | seq_printf(m, "RC information inaccurate because somebody " | |
1120 | "holds a forcewake reference \n"); | |
4d85529d BW |
1121 | } else { |
1122 | /* NB: we cannot use forcewake, else we read the wrong values */ | |
1123 | while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1)) | |
1124 | udelay(10); | |
1125 | seq_printf(m, "RC information accurate: %s\n", yesno(count < 51)); | |
1126 | } | |
1127 | ||
1128 | gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS); | |
1129 | trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4); | |
1130 | ||
1131 | rpmodectl1 = I915_READ(GEN6_RP_CONTROL); | |
1132 | rcctl1 = I915_READ(GEN6_RC_CONTROL); | |
1133 | mutex_unlock(&dev->struct_mutex); | |
1134 | ||
1135 | seq_printf(m, "Video Turbo Mode: %s\n", | |
1136 | yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO)); | |
1137 | seq_printf(m, "HW control enabled: %s\n", | |
1138 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); | |
1139 | seq_printf(m, "SW control enabled: %s\n", | |
1140 | yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) == | |
1141 | GEN6_RP_MEDIA_SW_MODE)); | |
fff24e21 | 1142 | seq_printf(m, "RC1e Enabled: %s\n", |
4d85529d BW |
1143 | yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE)); |
1144 | seq_printf(m, "RC6 Enabled: %s\n", | |
1145 | yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE)); | |
1146 | seq_printf(m, "Deep RC6 Enabled: %s\n", | |
1147 | yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE)); | |
1148 | seq_printf(m, "Deepest RC6 Enabled: %s\n", | |
1149 | yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE)); | |
1150 | seq_printf(m, "Current RC state: "); | |
1151 | switch (gt_core_status & GEN6_RCn_MASK) { | |
1152 | case GEN6_RC0: | |
1153 | if (gt_core_status & GEN6_CORE_CPD_STATE_MASK) | |
1154 | seq_printf(m, "Core Power Down\n"); | |
1155 | else | |
1156 | seq_printf(m, "on\n"); | |
1157 | break; | |
1158 | case GEN6_RC3: | |
1159 | seq_printf(m, "RC3\n"); | |
1160 | break; | |
1161 | case GEN6_RC6: | |
1162 | seq_printf(m, "RC6\n"); | |
1163 | break; | |
1164 | case GEN6_RC7: | |
1165 | seq_printf(m, "RC7\n"); | |
1166 | break; | |
1167 | default: | |
1168 | seq_printf(m, "Unknown\n"); | |
1169 | break; | |
1170 | } | |
1171 | ||
1172 | seq_printf(m, "Core Power Down: %s\n", | |
1173 | yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK)); | |
1174 | return 0; | |
1175 | } | |
1176 | ||
1177 | static int i915_drpc_info(struct seq_file *m, void *unused) | |
1178 | { | |
1179 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1180 | struct drm_device *dev = node->minor->dev; | |
1181 | ||
1182 | if (IS_GEN6(dev) || IS_GEN7(dev)) | |
1183 | return gen6_drpc_info(m); | |
1184 | else | |
1185 | return ironlake_drpc_info(m); | |
1186 | } | |
1187 | ||
b5e50c3f JB |
1188 | static int i915_fbc_status(struct seq_file *m, void *unused) |
1189 | { | |
1190 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1191 | struct drm_device *dev = node->minor->dev; | |
b5e50c3f | 1192 | drm_i915_private_t *dev_priv = dev->dev_private; |
b5e50c3f | 1193 | |
ee5382ae | 1194 | if (!I915_HAS_FBC(dev)) { |
b5e50c3f JB |
1195 | seq_printf(m, "FBC unsupported on this chipset\n"); |
1196 | return 0; | |
1197 | } | |
1198 | ||
ee5382ae | 1199 | if (intel_fbc_enabled(dev)) { |
b5e50c3f JB |
1200 | seq_printf(m, "FBC enabled\n"); |
1201 | } else { | |
1202 | seq_printf(m, "FBC disabled: "); | |
1203 | switch (dev_priv->no_fbc_reason) { | |
bed4a673 CW |
1204 | case FBC_NO_OUTPUT: |
1205 | seq_printf(m, "no outputs"); | |
1206 | break; | |
b5e50c3f JB |
1207 | case FBC_STOLEN_TOO_SMALL: |
1208 | seq_printf(m, "not enough stolen memory"); | |
1209 | break; | |
1210 | case FBC_UNSUPPORTED_MODE: | |
1211 | seq_printf(m, "mode not supported"); | |
1212 | break; | |
1213 | case FBC_MODE_TOO_LARGE: | |
1214 | seq_printf(m, "mode too large"); | |
1215 | break; | |
1216 | case FBC_BAD_PLANE: | |
1217 | seq_printf(m, "FBC unsupported on plane"); | |
1218 | break; | |
1219 | case FBC_NOT_TILED: | |
1220 | seq_printf(m, "scanout buffer not tiled"); | |
1221 | break; | |
9c928d16 JB |
1222 | case FBC_MULTIPLE_PIPES: |
1223 | seq_printf(m, "multiple pipes are enabled"); | |
1224 | break; | |
c1a9f047 JB |
1225 | case FBC_MODULE_PARAM: |
1226 | seq_printf(m, "disabled per module param (default off)"); | |
1227 | break; | |
b5e50c3f JB |
1228 | default: |
1229 | seq_printf(m, "unknown reason"); | |
1230 | } | |
1231 | seq_printf(m, "\n"); | |
1232 | } | |
1233 | return 0; | |
1234 | } | |
1235 | ||
4a9bef37 JB |
1236 | static int i915_sr_status(struct seq_file *m, void *unused) |
1237 | { | |
1238 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1239 | struct drm_device *dev = node->minor->dev; | |
1240 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1241 | bool sr_enabled = false; | |
1242 | ||
1398261a | 1243 | if (HAS_PCH_SPLIT(dev)) |
5ba2aaaa | 1244 | sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN; |
a6c45cf0 | 1245 | else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev)) |
4a9bef37 JB |
1246 | sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN; |
1247 | else if (IS_I915GM(dev)) | |
1248 | sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN; | |
1249 | else if (IS_PINEVIEW(dev)) | |
1250 | sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN; | |
1251 | ||
5ba2aaaa CW |
1252 | seq_printf(m, "self-refresh: %s\n", |
1253 | sr_enabled ? "enabled" : "disabled"); | |
4a9bef37 JB |
1254 | |
1255 | return 0; | |
1256 | } | |
1257 | ||
7648fa99 JB |
1258 | static int i915_emon_status(struct seq_file *m, void *unused) |
1259 | { | |
1260 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1261 | struct drm_device *dev = node->minor->dev; | |
1262 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1263 | unsigned long temp, chipset, gfx; | |
de227ef0 CW |
1264 | int ret; |
1265 | ||
1266 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1267 | if (ret) | |
1268 | return ret; | |
7648fa99 JB |
1269 | |
1270 | temp = i915_mch_val(dev_priv); | |
1271 | chipset = i915_chipset_val(dev_priv); | |
1272 | gfx = i915_gfx_val(dev_priv); | |
de227ef0 | 1273 | mutex_unlock(&dev->struct_mutex); |
7648fa99 JB |
1274 | |
1275 | seq_printf(m, "GMCH temp: %ld\n", temp); | |
1276 | seq_printf(m, "Chipset power: %ld\n", chipset); | |
1277 | seq_printf(m, "GFX power: %ld\n", gfx); | |
1278 | seq_printf(m, "Total power: %ld\n", chipset + gfx); | |
1279 | ||
1280 | return 0; | |
1281 | } | |
1282 | ||
23b2f8bb JB |
1283 | static int i915_ring_freq_table(struct seq_file *m, void *unused) |
1284 | { | |
1285 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1286 | struct drm_device *dev = node->minor->dev; | |
1287 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1288 | int ret; | |
1289 | int gpu_freq, ia_freq; | |
1290 | ||
1c70c0ce | 1291 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) { |
23b2f8bb JB |
1292 | seq_printf(m, "unsupported on this chipset\n"); |
1293 | return 0; | |
1294 | } | |
1295 | ||
1296 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1297 | if (ret) | |
1298 | return ret; | |
1299 | ||
1300 | seq_printf(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\n"); | |
1301 | ||
1302 | for (gpu_freq = dev_priv->min_delay; gpu_freq <= dev_priv->max_delay; | |
1303 | gpu_freq++) { | |
1304 | I915_WRITE(GEN6_PCODE_DATA, gpu_freq); | |
1305 | I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | | |
1306 | GEN6_PCODE_READ_MIN_FREQ_TABLE); | |
1307 | if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & | |
1308 | GEN6_PCODE_READY) == 0, 10)) { | |
1309 | DRM_ERROR("pcode read of freq table timed out\n"); | |
1310 | continue; | |
1311 | } | |
1312 | ia_freq = I915_READ(GEN6_PCODE_DATA); | |
1313 | seq_printf(m, "%d\t\t%d\n", gpu_freq * 50, ia_freq * 100); | |
1314 | } | |
1315 | ||
1316 | mutex_unlock(&dev->struct_mutex); | |
1317 | ||
1318 | return 0; | |
1319 | } | |
1320 | ||
7648fa99 JB |
1321 | static int i915_gfxec(struct seq_file *m, void *unused) |
1322 | { | |
1323 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1324 | struct drm_device *dev = node->minor->dev; | |
1325 | drm_i915_private_t *dev_priv = dev->dev_private; | |
616fdb5a BW |
1326 | int ret; |
1327 | ||
1328 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1329 | if (ret) | |
1330 | return ret; | |
7648fa99 JB |
1331 | |
1332 | seq_printf(m, "GFXEC: %ld\n", (unsigned long)I915_READ(0x112f4)); | |
1333 | ||
616fdb5a BW |
1334 | mutex_unlock(&dev->struct_mutex); |
1335 | ||
7648fa99 JB |
1336 | return 0; |
1337 | } | |
1338 | ||
44834a67 CW |
1339 | static int i915_opregion(struct seq_file *m, void *unused) |
1340 | { | |
1341 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1342 | struct drm_device *dev = node->minor->dev; | |
1343 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1344 | struct intel_opregion *opregion = &dev_priv->opregion; | |
1345 | int ret; | |
1346 | ||
1347 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1348 | if (ret) | |
1349 | return ret; | |
1350 | ||
1351 | if (opregion->header) | |
1352 | seq_write(m, opregion->header, OPREGION_SIZE); | |
1353 | ||
1354 | mutex_unlock(&dev->struct_mutex); | |
1355 | ||
1356 | return 0; | |
1357 | } | |
1358 | ||
37811fcc CW |
1359 | static int i915_gem_framebuffer_info(struct seq_file *m, void *data) |
1360 | { | |
1361 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1362 | struct drm_device *dev = node->minor->dev; | |
1363 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1364 | struct intel_fbdev *ifbdev; | |
1365 | struct intel_framebuffer *fb; | |
1366 | int ret; | |
1367 | ||
1368 | ret = mutex_lock_interruptible(&dev->mode_config.mutex); | |
1369 | if (ret) | |
1370 | return ret; | |
1371 | ||
1372 | ifbdev = dev_priv->fbdev; | |
1373 | fb = to_intel_framebuffer(ifbdev->helper.fb); | |
1374 | ||
1375 | seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, obj ", | |
1376 | fb->base.width, | |
1377 | fb->base.height, | |
1378 | fb->base.depth, | |
1379 | fb->base.bits_per_pixel); | |
05394f39 | 1380 | describe_obj(m, fb->obj); |
37811fcc CW |
1381 | seq_printf(m, "\n"); |
1382 | ||
1383 | list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) { | |
1384 | if (&fb->base == ifbdev->helper.fb) | |
1385 | continue; | |
1386 | ||
1387 | seq_printf(m, "user size: %d x %d, depth %d, %d bpp, obj ", | |
1388 | fb->base.width, | |
1389 | fb->base.height, | |
1390 | fb->base.depth, | |
1391 | fb->base.bits_per_pixel); | |
05394f39 | 1392 | describe_obj(m, fb->obj); |
37811fcc CW |
1393 | seq_printf(m, "\n"); |
1394 | } | |
1395 | ||
1396 | mutex_unlock(&dev->mode_config.mutex); | |
1397 | ||
1398 | return 0; | |
1399 | } | |
1400 | ||
e76d3630 BW |
1401 | static int i915_context_status(struct seq_file *m, void *unused) |
1402 | { | |
1403 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1404 | struct drm_device *dev = node->minor->dev; | |
1405 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1406 | int ret; | |
1407 | ||
1408 | ret = mutex_lock_interruptible(&dev->mode_config.mutex); | |
1409 | if (ret) | |
1410 | return ret; | |
1411 | ||
dc501fbc BW |
1412 | if (dev_priv->pwrctx) { |
1413 | seq_printf(m, "power context "); | |
1414 | describe_obj(m, dev_priv->pwrctx); | |
1415 | seq_printf(m, "\n"); | |
1416 | } | |
e76d3630 | 1417 | |
dc501fbc BW |
1418 | if (dev_priv->renderctx) { |
1419 | seq_printf(m, "render context "); | |
1420 | describe_obj(m, dev_priv->renderctx); | |
1421 | seq_printf(m, "\n"); | |
1422 | } | |
e76d3630 BW |
1423 | |
1424 | mutex_unlock(&dev->mode_config.mutex); | |
1425 | ||
1426 | return 0; | |
1427 | } | |
1428 | ||
6d794d42 BW |
1429 | static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data) |
1430 | { | |
1431 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1432 | struct drm_device *dev = node->minor->dev; | |
1433 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9f1f46a4 | 1434 | unsigned forcewake_count; |
6d794d42 | 1435 | |
9f1f46a4 DV |
1436 | spin_lock_irq(&dev_priv->gt_lock); |
1437 | forcewake_count = dev_priv->forcewake_count; | |
1438 | spin_unlock_irq(&dev_priv->gt_lock); | |
6d794d42 | 1439 | |
9f1f46a4 | 1440 | seq_printf(m, "forcewake count = %u\n", forcewake_count); |
6d794d42 BW |
1441 | |
1442 | return 0; | |
1443 | } | |
1444 | ||
ea16a3cd DV |
1445 | static const char *swizzle_string(unsigned swizzle) |
1446 | { | |
1447 | switch(swizzle) { | |
1448 | case I915_BIT_6_SWIZZLE_NONE: | |
1449 | return "none"; | |
1450 | case I915_BIT_6_SWIZZLE_9: | |
1451 | return "bit9"; | |
1452 | case I915_BIT_6_SWIZZLE_9_10: | |
1453 | return "bit9/bit10"; | |
1454 | case I915_BIT_6_SWIZZLE_9_11: | |
1455 | return "bit9/bit11"; | |
1456 | case I915_BIT_6_SWIZZLE_9_10_11: | |
1457 | return "bit9/bit10/bit11"; | |
1458 | case I915_BIT_6_SWIZZLE_9_17: | |
1459 | return "bit9/bit17"; | |
1460 | case I915_BIT_6_SWIZZLE_9_10_17: | |
1461 | return "bit9/bit10/bit17"; | |
1462 | case I915_BIT_6_SWIZZLE_UNKNOWN: | |
1463 | return "unkown"; | |
1464 | } | |
1465 | ||
1466 | return "bug"; | |
1467 | } | |
1468 | ||
1469 | static int i915_swizzle_info(struct seq_file *m, void *data) | |
1470 | { | |
1471 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1472 | struct drm_device *dev = node->minor->dev; | |
1473 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1474 | ||
1475 | mutex_lock(&dev->struct_mutex); | |
1476 | seq_printf(m, "bit6 swizzle for X-tiling = %s\n", | |
1477 | swizzle_string(dev_priv->mm.bit_6_swizzle_x)); | |
1478 | seq_printf(m, "bit6 swizzle for Y-tiling = %s\n", | |
1479 | swizzle_string(dev_priv->mm.bit_6_swizzle_y)); | |
1480 | ||
1481 | if (IS_GEN3(dev) || IS_GEN4(dev)) { | |
1482 | seq_printf(m, "DDC = 0x%08x\n", | |
1483 | I915_READ(DCC)); | |
1484 | seq_printf(m, "C0DRB3 = 0x%04x\n", | |
1485 | I915_READ16(C0DRB3)); | |
1486 | seq_printf(m, "C1DRB3 = 0x%04x\n", | |
1487 | I915_READ16(C1DRB3)); | |
3fa7d235 DV |
1488 | } else if (IS_GEN6(dev) || IS_GEN7(dev)) { |
1489 | seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n", | |
1490 | I915_READ(MAD_DIMM_C0)); | |
1491 | seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n", | |
1492 | I915_READ(MAD_DIMM_C1)); | |
1493 | seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n", | |
1494 | I915_READ(MAD_DIMM_C2)); | |
1495 | seq_printf(m, "TILECTL = 0x%08x\n", | |
1496 | I915_READ(TILECTL)); | |
1497 | seq_printf(m, "ARB_MODE = 0x%08x\n", | |
1498 | I915_READ(ARB_MODE)); | |
1499 | seq_printf(m, "DISP_ARB_CTL = 0x%08x\n", | |
1500 | I915_READ(DISP_ARB_CTL)); | |
ea16a3cd DV |
1501 | } |
1502 | mutex_unlock(&dev->struct_mutex); | |
1503 | ||
1504 | return 0; | |
1505 | } | |
1506 | ||
3cf17fc5 DV |
1507 | static int i915_ppgtt_info(struct seq_file *m, void *data) |
1508 | { | |
1509 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1510 | struct drm_device *dev = node->minor->dev; | |
1511 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1512 | struct intel_ring_buffer *ring; | |
1513 | int i, ret; | |
1514 | ||
1515 | ||
1516 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1517 | if (ret) | |
1518 | return ret; | |
1519 | if (INTEL_INFO(dev)->gen == 6) | |
1520 | seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE)); | |
1521 | ||
1522 | for (i = 0; i < I915_NUM_RINGS; i++) { | |
1523 | ring = &dev_priv->ring[i]; | |
1524 | ||
1525 | seq_printf(m, "%s\n", ring->name); | |
1526 | if (INTEL_INFO(dev)->gen == 7) | |
1527 | seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring))); | |
1528 | seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring))); | |
1529 | seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring))); | |
1530 | seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring))); | |
1531 | } | |
1532 | if (dev_priv->mm.aliasing_ppgtt) { | |
1533 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
1534 | ||
1535 | seq_printf(m, "aliasing PPGTT:\n"); | |
1536 | seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset); | |
1537 | } | |
1538 | seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK)); | |
1539 | mutex_unlock(&dev->struct_mutex); | |
1540 | ||
1541 | return 0; | |
1542 | } | |
1543 | ||
57f350b6 JB |
1544 | static int i915_dpio_info(struct seq_file *m, void *data) |
1545 | { | |
1546 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1547 | struct drm_device *dev = node->minor->dev; | |
1548 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1549 | int ret; | |
1550 | ||
1551 | ||
1552 | if (!IS_VALLEYVIEW(dev)) { | |
1553 | seq_printf(m, "unsupported\n"); | |
1554 | return 0; | |
1555 | } | |
1556 | ||
1557 | ret = mutex_lock_interruptible(&dev->mode_config.mutex); | |
1558 | if (ret) | |
1559 | return ret; | |
1560 | ||
1561 | seq_printf(m, "DPIO_CTL: 0x%08x\n", I915_READ(DPIO_CTL)); | |
1562 | ||
1563 | seq_printf(m, "DPIO_DIV_A: 0x%08x\n", | |
1564 | intel_dpio_read(dev_priv, _DPIO_DIV_A)); | |
1565 | seq_printf(m, "DPIO_DIV_B: 0x%08x\n", | |
1566 | intel_dpio_read(dev_priv, _DPIO_DIV_B)); | |
1567 | ||
1568 | seq_printf(m, "DPIO_REFSFR_A: 0x%08x\n", | |
1569 | intel_dpio_read(dev_priv, _DPIO_REFSFR_A)); | |
1570 | seq_printf(m, "DPIO_REFSFR_B: 0x%08x\n", | |
1571 | intel_dpio_read(dev_priv, _DPIO_REFSFR_B)); | |
1572 | ||
1573 | seq_printf(m, "DPIO_CORE_CLK_A: 0x%08x\n", | |
1574 | intel_dpio_read(dev_priv, _DPIO_CORE_CLK_A)); | |
1575 | seq_printf(m, "DPIO_CORE_CLK_B: 0x%08x\n", | |
1576 | intel_dpio_read(dev_priv, _DPIO_CORE_CLK_B)); | |
1577 | ||
1578 | seq_printf(m, "DPIO_LFP_COEFF_A: 0x%08x\n", | |
1579 | intel_dpio_read(dev_priv, _DPIO_LFP_COEFF_A)); | |
1580 | seq_printf(m, "DPIO_LFP_COEFF_B: 0x%08x\n", | |
1581 | intel_dpio_read(dev_priv, _DPIO_LFP_COEFF_B)); | |
1582 | ||
1583 | seq_printf(m, "DPIO_FASTCLK_DISABLE: 0x%08x\n", | |
1584 | intel_dpio_read(dev_priv, DPIO_FASTCLK_DISABLE)); | |
1585 | ||
1586 | mutex_unlock(&dev->mode_config.mutex); | |
1587 | ||
1588 | return 0; | |
1589 | } | |
1590 | ||
f3cd474b CW |
1591 | static ssize_t |
1592 | i915_wedged_read(struct file *filp, | |
1593 | char __user *ubuf, | |
1594 | size_t max, | |
1595 | loff_t *ppos) | |
1596 | { | |
1597 | struct drm_device *dev = filp->private_data; | |
1598 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1599 | char buf[80]; | |
1600 | int len; | |
1601 | ||
0206e353 | 1602 | len = snprintf(buf, sizeof(buf), |
f3cd474b CW |
1603 | "wedged : %d\n", |
1604 | atomic_read(&dev_priv->mm.wedged)); | |
1605 | ||
0206e353 AJ |
1606 | if (len > sizeof(buf)) |
1607 | len = sizeof(buf); | |
f4433a8d | 1608 | |
f3cd474b CW |
1609 | return simple_read_from_buffer(ubuf, max, ppos, buf, len); |
1610 | } | |
1611 | ||
1612 | static ssize_t | |
1613 | i915_wedged_write(struct file *filp, | |
1614 | const char __user *ubuf, | |
1615 | size_t cnt, | |
1616 | loff_t *ppos) | |
1617 | { | |
1618 | struct drm_device *dev = filp->private_data; | |
f3cd474b CW |
1619 | char buf[20]; |
1620 | int val = 1; | |
1621 | ||
1622 | if (cnt > 0) { | |
0206e353 | 1623 | if (cnt > sizeof(buf) - 1) |
f3cd474b CW |
1624 | return -EINVAL; |
1625 | ||
1626 | if (copy_from_user(buf, ubuf, cnt)) | |
1627 | return -EFAULT; | |
1628 | buf[cnt] = 0; | |
1629 | ||
1630 | val = simple_strtoul(buf, NULL, 0); | |
1631 | } | |
1632 | ||
1633 | DRM_INFO("Manually setting wedged to %d\n", val); | |
527f9e90 | 1634 | i915_handle_error(dev, val); |
f3cd474b CW |
1635 | |
1636 | return cnt; | |
1637 | } | |
1638 | ||
1639 | static const struct file_operations i915_wedged_fops = { | |
1640 | .owner = THIS_MODULE, | |
234e3405 | 1641 | .open = simple_open, |
f3cd474b CW |
1642 | .read = i915_wedged_read, |
1643 | .write = i915_wedged_write, | |
6038f373 | 1644 | .llseek = default_llseek, |
f3cd474b CW |
1645 | }; |
1646 | ||
358733e9 JB |
1647 | static ssize_t |
1648 | i915_max_freq_read(struct file *filp, | |
1649 | char __user *ubuf, | |
1650 | size_t max, | |
1651 | loff_t *ppos) | |
1652 | { | |
1653 | struct drm_device *dev = filp->private_data; | |
1654 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1655 | char buf[80]; | |
1656 | int len; | |
1657 | ||
0206e353 | 1658 | len = snprintf(buf, sizeof(buf), |
358733e9 JB |
1659 | "max freq: %d\n", dev_priv->max_delay * 50); |
1660 | ||
0206e353 AJ |
1661 | if (len > sizeof(buf)) |
1662 | len = sizeof(buf); | |
358733e9 JB |
1663 | |
1664 | return simple_read_from_buffer(ubuf, max, ppos, buf, len); | |
1665 | } | |
1666 | ||
1667 | static ssize_t | |
1668 | i915_max_freq_write(struct file *filp, | |
1669 | const char __user *ubuf, | |
1670 | size_t cnt, | |
1671 | loff_t *ppos) | |
1672 | { | |
1673 | struct drm_device *dev = filp->private_data; | |
1674 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1675 | char buf[20]; | |
1676 | int val = 1; | |
1677 | ||
1678 | if (cnt > 0) { | |
0206e353 | 1679 | if (cnt > sizeof(buf) - 1) |
358733e9 JB |
1680 | return -EINVAL; |
1681 | ||
1682 | if (copy_from_user(buf, ubuf, cnt)) | |
1683 | return -EFAULT; | |
1684 | buf[cnt] = 0; | |
1685 | ||
1686 | val = simple_strtoul(buf, NULL, 0); | |
1687 | } | |
1688 | ||
1689 | DRM_DEBUG_DRIVER("Manually setting max freq to %d\n", val); | |
1690 | ||
1691 | /* | |
1692 | * Turbo will still be enabled, but won't go above the set value. | |
1693 | */ | |
1694 | dev_priv->max_delay = val / 50; | |
1695 | ||
1696 | gen6_set_rps(dev, val / 50); | |
1697 | ||
1698 | return cnt; | |
1699 | } | |
1700 | ||
1701 | static const struct file_operations i915_max_freq_fops = { | |
1702 | .owner = THIS_MODULE, | |
234e3405 | 1703 | .open = simple_open, |
358733e9 JB |
1704 | .read = i915_max_freq_read, |
1705 | .write = i915_max_freq_write, | |
1706 | .llseek = default_llseek, | |
1707 | }; | |
1708 | ||
07b7ddd9 JB |
1709 | static ssize_t |
1710 | i915_cache_sharing_read(struct file *filp, | |
1711 | char __user *ubuf, | |
1712 | size_t max, | |
1713 | loff_t *ppos) | |
1714 | { | |
1715 | struct drm_device *dev = filp->private_data; | |
1716 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1717 | char buf[80]; | |
1718 | u32 snpcr; | |
1719 | int len; | |
1720 | ||
1721 | mutex_lock(&dev_priv->dev->struct_mutex); | |
1722 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); | |
1723 | mutex_unlock(&dev_priv->dev->struct_mutex); | |
1724 | ||
0206e353 | 1725 | len = snprintf(buf, sizeof(buf), |
07b7ddd9 JB |
1726 | "%d\n", (snpcr & GEN6_MBC_SNPCR_MASK) >> |
1727 | GEN6_MBC_SNPCR_SHIFT); | |
1728 | ||
0206e353 AJ |
1729 | if (len > sizeof(buf)) |
1730 | len = sizeof(buf); | |
07b7ddd9 JB |
1731 | |
1732 | return simple_read_from_buffer(ubuf, max, ppos, buf, len); | |
1733 | } | |
1734 | ||
1735 | static ssize_t | |
1736 | i915_cache_sharing_write(struct file *filp, | |
1737 | const char __user *ubuf, | |
1738 | size_t cnt, | |
1739 | loff_t *ppos) | |
1740 | { | |
1741 | struct drm_device *dev = filp->private_data; | |
1742 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1743 | char buf[20]; | |
1744 | u32 snpcr; | |
1745 | int val = 1; | |
1746 | ||
1747 | if (cnt > 0) { | |
0206e353 | 1748 | if (cnt > sizeof(buf) - 1) |
07b7ddd9 JB |
1749 | return -EINVAL; |
1750 | ||
1751 | if (copy_from_user(buf, ubuf, cnt)) | |
1752 | return -EFAULT; | |
1753 | buf[cnt] = 0; | |
1754 | ||
1755 | val = simple_strtoul(buf, NULL, 0); | |
1756 | } | |
1757 | ||
1758 | if (val < 0 || val > 3) | |
1759 | return -EINVAL; | |
1760 | ||
1761 | DRM_DEBUG_DRIVER("Manually setting uncore sharing to %d\n", val); | |
1762 | ||
1763 | /* Update the cache sharing policy here as well */ | |
1764 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); | |
1765 | snpcr &= ~GEN6_MBC_SNPCR_MASK; | |
1766 | snpcr |= (val << GEN6_MBC_SNPCR_SHIFT); | |
1767 | I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); | |
1768 | ||
1769 | return cnt; | |
1770 | } | |
1771 | ||
1772 | static const struct file_operations i915_cache_sharing_fops = { | |
1773 | .owner = THIS_MODULE, | |
234e3405 | 1774 | .open = simple_open, |
07b7ddd9 JB |
1775 | .read = i915_cache_sharing_read, |
1776 | .write = i915_cache_sharing_write, | |
1777 | .llseek = default_llseek, | |
1778 | }; | |
1779 | ||
f3cd474b CW |
1780 | /* As the drm_debugfs_init() routines are called before dev->dev_private is |
1781 | * allocated we need to hook into the minor for release. */ | |
1782 | static int | |
1783 | drm_add_fake_info_node(struct drm_minor *minor, | |
1784 | struct dentry *ent, | |
1785 | const void *key) | |
1786 | { | |
1787 | struct drm_info_node *node; | |
1788 | ||
1789 | node = kmalloc(sizeof(struct drm_info_node), GFP_KERNEL); | |
1790 | if (node == NULL) { | |
1791 | debugfs_remove(ent); | |
1792 | return -ENOMEM; | |
1793 | } | |
1794 | ||
1795 | node->minor = minor; | |
1796 | node->dent = ent; | |
1797 | node->info_ent = (void *) key; | |
b3e067c0 MS |
1798 | |
1799 | mutex_lock(&minor->debugfs_lock); | |
1800 | list_add(&node->list, &minor->debugfs_list); | |
1801 | mutex_unlock(&minor->debugfs_lock); | |
f3cd474b CW |
1802 | |
1803 | return 0; | |
1804 | } | |
1805 | ||
6d794d42 BW |
1806 | static int i915_forcewake_open(struct inode *inode, struct file *file) |
1807 | { | |
1808 | struct drm_device *dev = inode->i_private; | |
1809 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1810 | int ret; | |
1811 | ||
075edca4 | 1812 | if (INTEL_INFO(dev)->gen < 6) |
6d794d42 BW |
1813 | return 0; |
1814 | ||
1815 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1816 | if (ret) | |
1817 | return ret; | |
1818 | gen6_gt_force_wake_get(dev_priv); | |
1819 | mutex_unlock(&dev->struct_mutex); | |
1820 | ||
1821 | return 0; | |
1822 | } | |
1823 | ||
1824 | int i915_forcewake_release(struct inode *inode, struct file *file) | |
1825 | { | |
1826 | struct drm_device *dev = inode->i_private; | |
1827 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1828 | ||
075edca4 | 1829 | if (INTEL_INFO(dev)->gen < 6) |
6d794d42 BW |
1830 | return 0; |
1831 | ||
1832 | /* | |
1833 | * It's bad that we can potentially hang userspace if struct_mutex gets | |
1834 | * forever stuck. However, if we cannot acquire this lock it means that | |
1835 | * almost certainly the driver has hung, is not unload-able. Therefore | |
1836 | * hanging here is probably a minor inconvenience not to be seen my | |
1837 | * almost every user. | |
1838 | */ | |
1839 | mutex_lock(&dev->struct_mutex); | |
1840 | gen6_gt_force_wake_put(dev_priv); | |
1841 | mutex_unlock(&dev->struct_mutex); | |
1842 | ||
1843 | return 0; | |
1844 | } | |
1845 | ||
1846 | static const struct file_operations i915_forcewake_fops = { | |
1847 | .owner = THIS_MODULE, | |
1848 | .open = i915_forcewake_open, | |
1849 | .release = i915_forcewake_release, | |
1850 | }; | |
1851 | ||
1852 | static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor) | |
1853 | { | |
1854 | struct drm_device *dev = minor->dev; | |
1855 | struct dentry *ent; | |
1856 | ||
1857 | ent = debugfs_create_file("i915_forcewake_user", | |
8eb57294 | 1858 | S_IRUSR, |
6d794d42 BW |
1859 | root, dev, |
1860 | &i915_forcewake_fops); | |
1861 | if (IS_ERR(ent)) | |
1862 | return PTR_ERR(ent); | |
1863 | ||
8eb57294 | 1864 | return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops); |
6d794d42 BW |
1865 | } |
1866 | ||
6a9c308d DV |
1867 | static int i915_debugfs_create(struct dentry *root, |
1868 | struct drm_minor *minor, | |
1869 | const char *name, | |
1870 | const struct file_operations *fops) | |
07b7ddd9 JB |
1871 | { |
1872 | struct drm_device *dev = minor->dev; | |
1873 | struct dentry *ent; | |
1874 | ||
6a9c308d | 1875 | ent = debugfs_create_file(name, |
07b7ddd9 JB |
1876 | S_IRUGO | S_IWUSR, |
1877 | root, dev, | |
6a9c308d | 1878 | fops); |
07b7ddd9 JB |
1879 | if (IS_ERR(ent)) |
1880 | return PTR_ERR(ent); | |
1881 | ||
6a9c308d | 1882 | return drm_add_fake_info_node(minor, ent, fops); |
07b7ddd9 JB |
1883 | } |
1884 | ||
27c202ad | 1885 | static struct drm_info_list i915_debugfs_list[] = { |
311bd68e | 1886 | {"i915_capabilities", i915_capabilities, 0}, |
73aa808f | 1887 | {"i915_gem_objects", i915_gem_object_info, 0}, |
08c18323 | 1888 | {"i915_gem_gtt", i915_gem_gtt_info, 0}, |
433e12f7 BG |
1889 | {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST}, |
1890 | {"i915_gem_flushing", i915_gem_object_list_info, 0, (void *) FLUSHING_LIST}, | |
1891 | {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST}, | |
f13d3f73 | 1892 | {"i915_gem_pinned", i915_gem_object_list_info, 0, (void *) PINNED_LIST}, |
d21d5975 | 1893 | {"i915_gem_deferred_free", i915_gem_object_list_info, 0, (void *) DEFERRED_FREE_LIST}, |
4e5359cd | 1894 | {"i915_gem_pageflip", i915_gem_pageflip_info, 0}, |
2017263e BG |
1895 | {"i915_gem_request", i915_gem_request_info, 0}, |
1896 | {"i915_gem_seqno", i915_gem_seqno_info, 0}, | |
a6172a80 | 1897 | {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0}, |
2017263e | 1898 | {"i915_gem_interrupt", i915_interrupt_info, 0}, |
1ec14ad3 CW |
1899 | {"i915_gem_hws", i915_hws_info, 0, (void *)RCS}, |
1900 | {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS}, | |
1901 | {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS}, | |
1902 | {"i915_ringbuffer_data", i915_ringbuffer_data, 0, (void *)RCS}, | |
1903 | {"i915_ringbuffer_info", i915_ringbuffer_info, 0, (void *)RCS}, | |
1904 | {"i915_bsd_ringbuffer_data", i915_ringbuffer_data, 0, (void *)VCS}, | |
1905 | {"i915_bsd_ringbuffer_info", i915_ringbuffer_info, 0, (void *)VCS}, | |
1906 | {"i915_blt_ringbuffer_data", i915_ringbuffer_data, 0, (void *)BCS}, | |
1907 | {"i915_blt_ringbuffer_info", i915_ringbuffer_info, 0, (void *)BCS}, | |
63eeaf38 | 1908 | {"i915_error_state", i915_error_state, 0}, |
f97108d1 JB |
1909 | {"i915_rstdby_delays", i915_rstdby_delays, 0}, |
1910 | {"i915_cur_delayinfo", i915_cur_delayinfo, 0}, | |
1911 | {"i915_delayfreq_table", i915_delayfreq_table, 0}, | |
1912 | {"i915_inttoext_table", i915_inttoext_table, 0}, | |
1913 | {"i915_drpc_info", i915_drpc_info, 0}, | |
7648fa99 | 1914 | {"i915_emon_status", i915_emon_status, 0}, |
23b2f8bb | 1915 | {"i915_ring_freq_table", i915_ring_freq_table, 0}, |
7648fa99 | 1916 | {"i915_gfxec", i915_gfxec, 0}, |
b5e50c3f | 1917 | {"i915_fbc_status", i915_fbc_status, 0}, |
4a9bef37 | 1918 | {"i915_sr_status", i915_sr_status, 0}, |
44834a67 | 1919 | {"i915_opregion", i915_opregion, 0}, |
37811fcc | 1920 | {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0}, |
e76d3630 | 1921 | {"i915_context_status", i915_context_status, 0}, |
6d794d42 | 1922 | {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0}, |
ea16a3cd | 1923 | {"i915_swizzle_info", i915_swizzle_info, 0}, |
3cf17fc5 | 1924 | {"i915_ppgtt_info", i915_ppgtt_info, 0}, |
57f350b6 | 1925 | {"i915_dpio", i915_dpio_info, 0}, |
2017263e | 1926 | }; |
27c202ad | 1927 | #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list) |
2017263e | 1928 | |
27c202ad | 1929 | int i915_debugfs_init(struct drm_minor *minor) |
2017263e | 1930 | { |
f3cd474b CW |
1931 | int ret; |
1932 | ||
6a9c308d DV |
1933 | ret = i915_debugfs_create(minor->debugfs_root, minor, |
1934 | "i915_wedged", | |
1935 | &i915_wedged_fops); | |
f3cd474b CW |
1936 | if (ret) |
1937 | return ret; | |
1938 | ||
6d794d42 | 1939 | ret = i915_forcewake_create(minor->debugfs_root, minor); |
358733e9 JB |
1940 | if (ret) |
1941 | return ret; | |
6a9c308d DV |
1942 | |
1943 | ret = i915_debugfs_create(minor->debugfs_root, minor, | |
1944 | "i915_max_freq", | |
1945 | &i915_max_freq_fops); | |
07b7ddd9 JB |
1946 | if (ret) |
1947 | return ret; | |
6a9c308d DV |
1948 | |
1949 | ret = i915_debugfs_create(minor->debugfs_root, minor, | |
1950 | "i915_cache_sharing", | |
1951 | &i915_cache_sharing_fops); | |
6d794d42 BW |
1952 | if (ret) |
1953 | return ret; | |
1954 | ||
27c202ad BG |
1955 | return drm_debugfs_create_files(i915_debugfs_list, |
1956 | I915_DEBUGFS_ENTRIES, | |
2017263e BG |
1957 | minor->debugfs_root, minor); |
1958 | } | |
1959 | ||
27c202ad | 1960 | void i915_debugfs_cleanup(struct drm_minor *minor) |
2017263e | 1961 | { |
27c202ad BG |
1962 | drm_debugfs_remove_files(i915_debugfs_list, |
1963 | I915_DEBUGFS_ENTRIES, minor); | |
6d794d42 BW |
1964 | drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops, |
1965 | 1, minor); | |
33db679b KH |
1966 | drm_debugfs_remove_files((struct drm_info_list *) &i915_wedged_fops, |
1967 | 1, minor); | |
358733e9 JB |
1968 | drm_debugfs_remove_files((struct drm_info_list *) &i915_max_freq_fops, |
1969 | 1, minor); | |
07b7ddd9 JB |
1970 | drm_debugfs_remove_files((struct drm_info_list *) &i915_cache_sharing_fops, |
1971 | 1, minor); | |
2017263e BG |
1972 | } |
1973 | ||
1974 | #endif /* CONFIG_DEBUG_FS */ |