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drm/i915: Parametrize PALETTE and LGC_PALETTE
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_debugfs.c
CommitLineData
2017263e
BG		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 *
27 */
28
29#include <linux/seq_file.h>
b2c88f5b 30#include <linux/circ_buf.h>
926321d5 31#include <linux/ctype.h>
f3cd474b 32#include <linux/debugfs.h>
5a0e3ad6 33#include <linux/slab.h>
2d1a8a48 34#include <linux/export.h>
6d2b8885 35#include <linux/list_sort.h>
ec013e7f 36#include <asm/msr-index.h>
760285e7 37#include <drm/drmP.h>
4e5359cd 38#include "intel_drv.h"
e5c65260 39#include "intel_ringbuffer.h"
760285e7 40#include <drm/i915_drm.h>
2017263e
BG		 41#include "i915_drv.h"
42
f13d3f73 43enum {
69dc4987 44 ACTIVE_LIST,
f13d3f73 45 INACTIVE_LIST,
d21d5975 46 PINNED_LIST,
f13d3f73 47};
2017263e 48
497666d8
DL		 49/* As the drm_debugfs_init() routines are called before dev->dev_private is
50 * allocated we need to hook into the minor for release. */
51static int
52drm_add_fake_info_node(struct drm_minor *minor,
53 struct dentry *ent,
54 const void *key)
55{
56 struct drm_info_node *node;
57
58 node = kmalloc(sizeof(*node), GFP_KERNEL);
59 if (node == NULL) {
60 debugfs_remove(ent);
61 return -ENOMEM;
62 }
63
64 node->minor = minor;
65 node->dent = ent;
66 node->info_ent = (void *) key;
67
68 mutex_lock(&minor->debugfs_lock);
69 list_add(&node->list, &minor->debugfs_list);
70 mutex_unlock(&minor->debugfs_lock);
71
72 return 0;
73}
74
70d39fe4
CW		 75static int i915_capabilities(struct seq_file *m, void *data)
76{
9f25d007 77 struct drm_info_node *node = m->private;
70d39fe4
CW		 78 struct drm_device *dev = node->minor->dev;
79 const struct intel_device_info *info = INTEL_INFO(dev);
80
81 seq_printf(m, "gen: %d\n", info->gen);
03d00ac5 82 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
79fc46df
DL		 83#define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
84#define SEP_SEMICOLON ;
85 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
86#undef PRINT_FLAG
87#undef SEP_SEMICOLON
70d39fe4
CW		 88
89 return 0;
90}
2017263e 91
05394f39 92static const char *get_pin_flag(struct drm_i915_gem_object *obj)
a6172a80 93{
baaa5cfb 94 if (obj->pin_display)
a6172a80
CW		 95 return "p";
96 else
97 return " ";
98}
99
05394f39 100static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
a6172a80 101{
0206e353
AJ		 102 switch (obj->tiling_mode) {
103 default:
104 case I915_TILING_NONE: return " ";
105 case I915_TILING_X: return "X";
106 case I915_TILING_Y: return "Y";
107 }
a6172a80
CW		 108}
109
1d693bcc
BW		 110static inline const char *get_global_flag(struct drm_i915_gem_object *obj)
111{
aff43766 112 return i915_gem_obj_to_ggtt(obj) ? "g" : " ";
1d693bcc
BW		 113}
114
ca1543be
TU		 115static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj)
116{
117 u64 size = 0;
118 struct i915_vma *vma;
119
120 list_for_each_entry(vma, &obj->vma_list, vma_link) {
121 if (i915_is_ggtt(vma->vm) &&
122 drm_mm_node_allocated(&vma->node))
123 size += vma->node.size;
124 }
125
126 return size;
127}
128
37811fcc
CW		 129static void
130describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
131{
b4716185
CW		 132 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
133 struct intel_engine_cs *ring;
1d693bcc 134 struct i915_vma *vma;
d7f46fc4 135 int pin_count = 0;
b4716185 136 int i;
d7f46fc4 137
b4716185 138 seq_printf(m, "%pK: %s%s%s%s %8zdKiB %02x %02x [ ",
37811fcc 139 &obj->base,
481a3d43 140 obj->active ? "*" : " ",
37811fcc
CW		 141 get_pin_flag(obj),
142 get_tiling_flag(obj),
1d693bcc 143 get_global_flag(obj),
a05a5862 144 obj->base.size / 1024,
37811fcc 145 obj->base.read_domains,
b4716185
CW		 146 obj->base.write_domain);
147 for_each_ring(ring, dev_priv, i)
148 seq_printf(m, "%x ",
149 i915_gem_request_get_seqno(obj->last_read_req[i]));
150 seq_printf(m, "] %x %x%s%s%s",
97b2a6a1
JH		 151 i915_gem_request_get_seqno(obj->last_write_req),
152 i915_gem_request_get_seqno(obj->last_fenced_req),
0a4cd7c8 153 i915_cache_level_str(to_i915(obj->base.dev), obj->cache_level),
37811fcc
CW		 154 obj->dirty ? " dirty" : "",
155 obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
156 if (obj->base.name)
157 seq_printf(m, " (name: %d)", obj->base.name);
ba0635ff 158 list_for_each_entry(vma, &obj->vma_list, vma_link) {
d7f46fc4
BW		 159 if (vma->pin_count > 0)
160 pin_count++;
ba0635ff
DC		 161 }
162 seq_printf(m, " (pinned x %d)", pin_count);
cc98b413
CW		 163 if (obj->pin_display)
164 seq_printf(m, " (display)");
37811fcc
CW		 165 if (obj->fence_reg != I915_FENCE_REG_NONE)
166 seq_printf(m, " (fence: %d)", obj->fence_reg);
1d693bcc 167 list_for_each_entry(vma, &obj->vma_list, vma_link) {
8d2fdc3f
TU		 168 seq_printf(m, " (%sgtt offset: %08llx, size: %08llx",
169 i915_is_ggtt(vma->vm) ? "g" : "pp",
170 vma->node.start, vma->node.size);
171 if (i915_is_ggtt(vma->vm))
172 seq_printf(m, ", type: %u)", vma->ggtt_view.type);
1d693bcc 173 else
8d2fdc3f 174 seq_puts(m, ")");
1d693bcc 175 }
c1ad11fc 176 if (obj->stolen)
440fd528 177 seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
30154650 178 if (obj->pin_display || obj->fault_mappable) {
6299f992 179 char s[3], *t = s;
30154650 180 if (obj->pin_display)
6299f992
CW		 181 *t++ = 'p';
182 if (obj->fault_mappable)
183 *t++ = 'f';
184 *t = '\0';
185 seq_printf(m, " (%s mappable)", s);
186 }
b4716185 187 if (obj->last_write_req != NULL)
41c52415 188 seq_printf(m, " (%s)",
b4716185 189 i915_gem_request_get_ring(obj->last_write_req)->name);
d5a81ef1
DV		 190 if (obj->frontbuffer_bits)
191 seq_printf(m, " (frontbuffer: 0x%03x)", obj->frontbuffer_bits);
37811fcc
CW		 192}
193
273497e5 194static void describe_ctx(struct seq_file *m, struct intel_context *ctx)
3ccfd19d 195{
ea0c76f8 196 seq_putc(m, ctx->legacy_hw_ctx.initialized ? 'I' : 'i');
3ccfd19d
BW		 197 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
198 seq_putc(m, ' ');
199}
200
433e12f7 201static int i915_gem_object_list_info(struct seq_file *m, void *data)
2017263e 202{
9f25d007 203 struct drm_info_node *node = m->private;
433e12f7
BG		 204 uintptr_t list = (uintptr_t) node->info_ent->data;
205 struct list_head *head;
2017263e 206 struct drm_device *dev = node->minor->dev;
5cef07e1
BW		 207 struct drm_i915_private *dev_priv = dev->dev_private;
208 struct i915_address_space *vm = &dev_priv->gtt.base;
ca191b13 209 struct i915_vma *vma;
c44ef60e 210 u64 total_obj_size, total_gtt_size;
8f2480fb 211 int count, ret;
de227ef0
CW		 212
213 ret = mutex_lock_interruptible(&dev->struct_mutex);
214 if (ret)
215 return ret;
2017263e 216
ca191b13 217 /* FIXME: the user of this interface might want more than just GGTT */
433e12f7
BG		 218 switch (list) {
219 case ACTIVE_LIST:
267f0c90 220 seq_puts(m, "Active:\n");
5cef07e1 221 head = &vm->active_list;
433e12f7
BG		 222 break;
223 case INACTIVE_LIST:
267f0c90 224 seq_puts(m, "Inactive:\n");
5cef07e1 225 head = &vm->inactive_list;
433e12f7 226 break;
433e12f7 227 default:
de227ef0
CW		 228 mutex_unlock(&dev->struct_mutex);
229 return -EINVAL;
2017263e 230 }
2017263e 231
8f2480fb 232 total_obj_size = total_gtt_size = count = 0;
ca191b13
BW		 233 list_for_each_entry(vma, head, mm_list) {
234 seq_printf(m, " ");
235 describe_obj(m, vma->obj);
236 seq_printf(m, "\n");
237 total_obj_size += vma->obj->base.size;
238 total_gtt_size += vma->node.size;
8f2480fb 239 count++;
2017263e 240 }
de227ef0 241 mutex_unlock(&dev->struct_mutex);
5e118f41 242
c44ef60e 243 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
8f2480fb 244 count, total_obj_size, total_gtt_size);
2017263e
BG		 245 return 0;
246}
247
6d2b8885
CW		 248static int obj_rank_by_stolen(void *priv,
249 struct list_head *A, struct list_head *B)
250{
251 struct drm_i915_gem_object *a =
b25cb2f8 252 container_of(A, struct drm_i915_gem_object, obj_exec_link);
6d2b8885 253 struct drm_i915_gem_object *b =
b25cb2f8 254 container_of(B, struct drm_i915_gem_object, obj_exec_link);
6d2b8885
CW		 255
256 return a->stolen->start - b->stolen->start;
257}
258
259static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
260{
9f25d007 261 struct drm_info_node *node = m->private;
6d2b8885
CW		 262 struct drm_device *dev = node->minor->dev;
263 struct drm_i915_private *dev_priv = dev->dev_private;
264 struct drm_i915_gem_object *obj;
c44ef60e 265 u64 total_obj_size, total_gtt_size;
6d2b8885
CW		 266 LIST_HEAD(stolen);
267 int count, ret;
268
269 ret = mutex_lock_interruptible(&dev->struct_mutex);
270 if (ret)
271 return ret;
272
273 total_obj_size = total_gtt_size = count = 0;
274 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
275 if (obj->stolen == NULL)
276 continue;
277
b25cb2f8 278 list_add(&obj->obj_exec_link, &stolen);
6d2b8885
CW		 279
280 total_obj_size += obj->base.size;
ca1543be 281 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
6d2b8885
CW		 282 count++;
283 }
284 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
285 if (obj->stolen == NULL)
286 continue;
287
b25cb2f8 288 list_add(&obj->obj_exec_link, &stolen);
6d2b8885
CW		 289
290 total_obj_size += obj->base.size;
291 count++;
292 }
293 list_sort(NULL, &stolen, obj_rank_by_stolen);
294 seq_puts(m, "Stolen:\n");
295 while (!list_empty(&stolen)) {
b25cb2f8 296 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
6d2b8885
CW		 297 seq_puts(m, " ");
298 describe_obj(m, obj);
299 seq_putc(m, '\n');
b25cb2f8 300 list_del_init(&obj->obj_exec_link);
6d2b8885
CW		 301 }
302 mutex_unlock(&dev->struct_mutex);
303
c44ef60e 304 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
6d2b8885
CW		 305 count, total_obj_size, total_gtt_size);
306 return 0;
307}
308
6299f992
CW		 309#define count_objects(list, member) do { \
310 list_for_each_entry(obj, list, member) { \
ca1543be 311 size += i915_gem_obj_total_ggtt_size(obj); \
6299f992
CW		 312 ++count; \
313 if (obj->map_and_fenceable) { \
f343c5f6 314 mappable_size += i915_gem_obj_ggtt_size(obj); \
6299f992
CW		 315 ++mappable_count; \
316 } \
317 } \
0206e353 318} while (0)
6299f992 319
2db8e9d6 320struct file_stats {
6313c204 321 struct drm_i915_file_private *file_priv;
c44ef60e
MK		 322 unsigned long count;
323 u64 total, unbound;
324 u64 global, shared;
325 u64 active, inactive;
2db8e9d6
CW		 326};
327
328static int per_file_stats(int id, void *ptr, void *data)
329{
330 struct drm_i915_gem_object *obj = ptr;
331 struct file_stats *stats = data;
6313c204 332 struct i915_vma *vma;
2db8e9d6
CW		 333
334 stats->count++;
335 stats->total += obj->base.size;
336
c67a17e9
CW		 337 if (obj->base.name || obj->base.dma_buf)
338 stats->shared += obj->base.size;
339
6313c204
CW		 340 if (USES_FULL_PPGTT(obj->base.dev)) {
341 list_for_each_entry(vma, &obj->vma_list, vma_link) {
342 struct i915_hw_ppgtt *ppgtt;
343
344 if (!drm_mm_node_allocated(&vma->node))
345 continue;
346
347 if (i915_is_ggtt(vma->vm)) {
348 stats->global += obj->base.size;
349 continue;
350 }
351
352 ppgtt = container_of(vma->vm, struct i915_hw_ppgtt, base);
4d884705 353 if (ppgtt->file_priv != stats->file_priv)
6313c204
CW		 354 continue;
355
41c52415 356 if (obj->active) /* XXX per-vma statistic */
6313c204
CW		 357 stats->active += obj->base.size;
358 else
359 stats->inactive += obj->base.size;
360
361 return 0;
362 }
2db8e9d6 363 } else {
6313c204
CW		 364 if (i915_gem_obj_ggtt_bound(obj)) {
365 stats->global += obj->base.size;
41c52415 366 if (obj->active)
6313c204
CW		 367 stats->active += obj->base.size;
368 else
369 stats->inactive += obj->base.size;
370 return 0;
371 }
2db8e9d6
CW		 372 }
373
6313c204
CW		 374 if (!list_empty(&obj->global_list))
375 stats->unbound += obj->base.size;
376
2db8e9d6
CW		 377 return 0;
378}
379
b0da1b79
CW		 380#define print_file_stats(m, name, stats) do { \
381 if (stats.count) \
c44ef60e 382 seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \
b0da1b79
CW		 383 name, \
384 stats.count, \
385 stats.total, \
386 stats.active, \
387 stats.inactive, \
388 stats.global, \
389 stats.shared, \
390 stats.unbound); \
391} while (0)
493018dc
BV		 392
393static void print_batch_pool_stats(struct seq_file *m,
394 struct drm_i915_private *dev_priv)
395{
396 struct drm_i915_gem_object *obj;
397 struct file_stats stats;
06fbca71 398 struct intel_engine_cs *ring;
8d9d5744 399 int i, j;
493018dc
BV		 400
401 memset(&stats, 0, sizeof(stats));
402
06fbca71 403 for_each_ring(ring, dev_priv, i) {
8d9d5744
CW		 404 for (j = 0; j < ARRAY_SIZE(ring->batch_pool.cache_list); j++) {
405 list_for_each_entry(obj,
406 &ring->batch_pool.cache_list[j],
407 batch_pool_link)
408 per_file_stats(0, obj, &stats);
409 }
06fbca71 410 }
493018dc 411
b0da1b79 412 print_file_stats(m, "[k]batch pool", stats);
493018dc
BV		 413}
414
ca191b13
BW		 415#define count_vmas(list, member) do { \
416 list_for_each_entry(vma, list, member) { \
ca1543be 417 size += i915_gem_obj_total_ggtt_size(vma->obj); \
ca191b13
BW		 418 ++count; \
419 if (vma->obj->map_and_fenceable) { \
420 mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
421 ++mappable_count; \
422 } \
423 } \
424} while (0)
425
426static int i915_gem_object_info(struct seq_file *m, void* data)
73aa808f 427{
9f25d007 428 struct drm_info_node *node = m->private;
73aa808f
CW		 429 struct drm_device *dev = node->minor->dev;
430 struct drm_i915_private *dev_priv = dev->dev_private;
b7abb714 431 u32 count, mappable_count, purgeable_count;
c44ef60e 432 u64 size, mappable_size, purgeable_size;
6299f992 433 struct drm_i915_gem_object *obj;
5cef07e1 434 struct i915_address_space *vm = &dev_priv->gtt.base;
2db8e9d6 435 struct drm_file *file;
ca191b13 436 struct i915_vma *vma;
73aa808f
CW		 437 int ret;
438
439 ret = mutex_lock_interruptible(&dev->struct_mutex);
440 if (ret)
441 return ret;
442
6299f992
CW		 443 seq_printf(m, "%u objects, %zu bytes\n",
444 dev_priv->mm.object_count,
445 dev_priv->mm.object_memory);
446
447 size = count = mappable_size = mappable_count = 0;
35c20a60 448 count_objects(&dev_priv->mm.bound_list, global_list);
c44ef60e 449 seq_printf(m, "%u [%u] objects, %llu [%llu] bytes in gtt\n",
6299f992
CW		 450 count, mappable_count, size, mappable_size);
451
452 size = count = mappable_size = mappable_count = 0;
ca191b13 453 count_vmas(&vm->active_list, mm_list);
c44ef60e 454 seq_printf(m, " %u [%u] active objects, %llu [%llu] bytes\n",
6299f992
CW		 455 count, mappable_count, size, mappable_size);
456
6299f992 457 size = count = mappable_size = mappable_count = 0;
ca191b13 458 count_vmas(&vm->inactive_list, mm_list);
c44ef60e 459 seq_printf(m, " %u [%u] inactive objects, %llu [%llu] bytes\n",
6299f992
CW		 460 count, mappable_count, size, mappable_size);
461
b7abb714 462 size = count = purgeable_size = purgeable_count = 0;
35c20a60 463 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
6c085a72 464 size += obj->base.size, ++count;
b7abb714
CW		 465 if (obj->madv == I915_MADV_DONTNEED)
466 purgeable_size += obj->base.size, ++purgeable_count;
467 }
c44ef60e 468 seq_printf(m, "%u unbound objects, %llu bytes\n", count, size);
6c085a72 469
6299f992 470 size = count = mappable_size = mappable_count = 0;
35c20a60 471 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
6299f992 472 if (obj->fault_mappable) {
f343c5f6 473 size += i915_gem_obj_ggtt_size(obj);
6299f992
CW		 474 ++count;
475 }
30154650 476 if (obj->pin_display) {
f343c5f6 477 mappable_size += i915_gem_obj_ggtt_size(obj);
6299f992
CW		 478 ++mappable_count;
479 }
b7abb714
CW		 480 if (obj->madv == I915_MADV_DONTNEED) {
481 purgeable_size += obj->base.size;
482 ++purgeable_count;
483 }
6299f992 484 }
c44ef60e 485 seq_printf(m, "%u purgeable objects, %llu bytes\n",
b7abb714 486 purgeable_count, purgeable_size);
c44ef60e 487 seq_printf(m, "%u pinned mappable objects, %llu bytes\n",
6299f992 488 mappable_count, mappable_size);
c44ef60e 489 seq_printf(m, "%u fault mappable objects, %llu bytes\n",
6299f992
CW		 490 count, size);
491
c44ef60e 492 seq_printf(m, "%llu [%llu] gtt total\n",
853ba5d2 493 dev_priv->gtt.base.total,
c44ef60e 494 (u64)dev_priv->gtt.mappable_end - dev_priv->gtt.base.start);
73aa808f 495
493018dc
BV		 496 seq_putc(m, '\n');
497 print_batch_pool_stats(m, dev_priv);
2db8e9d6
CW		 498 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
499 struct file_stats stats;
3ec2f427 500 struct task_struct *task;
2db8e9d6
CW		 501
502 memset(&stats, 0, sizeof(stats));
6313c204 503 stats.file_priv = file->driver_priv;
5b5ffff0 504 spin_lock(&file->table_lock);
2db8e9d6 505 idr_for_each(&file->object_idr, per_file_stats, &stats);
5b5ffff0 506 spin_unlock(&file->table_lock);
3ec2f427
TH		 507 /*
508 * Although we have a valid reference on file->pid, that does
509 * not guarantee that the task_struct who called get_pid() is
510 * still alive (e.g. get_pid(current) => fork() => exit()).
511 * Therefore, we need to protect this ->comm access using RCU.
512 */
513 rcu_read_lock();
514 task = pid_task(file->pid, PIDTYPE_PID);
493018dc 515 print_file_stats(m, task ? task->comm : "<unknown>", stats);
3ec2f427 516 rcu_read_unlock();
2db8e9d6
CW		 517 }
518
73aa808f
CW		 519 mutex_unlock(&dev->struct_mutex);
520
521 return 0;
522}
523
aee56cff 524static int i915_gem_gtt_info(struct seq_file *m, void *data)
08c18323 525{
9f25d007 526 struct drm_info_node *node = m->private;
08c18323 527 struct drm_device *dev = node->minor->dev;
1b50247a 528 uintptr_t list = (uintptr_t) node->info_ent->data;
08c18323
CW		 529 struct drm_i915_private *dev_priv = dev->dev_private;
530 struct drm_i915_gem_object *obj;
c44ef60e 531 u64 total_obj_size, total_gtt_size;
08c18323
CW		 532 int count, ret;
533
534 ret = mutex_lock_interruptible(&dev->struct_mutex);
535 if (ret)
536 return ret;
537
538 total_obj_size = total_gtt_size = count = 0;
35c20a60 539 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
d7f46fc4 540 if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj))
1b50247a
CW		 541 continue;
542
267f0c90 543 seq_puts(m, " ");
08c18323 544 describe_obj(m, obj);
267f0c90 545 seq_putc(m, '\n');
08c18323 546 total_obj_size += obj->base.size;
ca1543be 547 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
08c18323
CW		 548 count++;
549 }
550
551 mutex_unlock(&dev->struct_mutex);
552
c44ef60e 553 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
08c18323
CW		 554 count, total_obj_size, total_gtt_size);
555
556 return 0;
557}
558
4e5359cd
SF		 559static int i915_gem_pageflip_info(struct seq_file *m, void *data)
560{
9f25d007 561 struct drm_info_node *node = m->private;
4e5359cd 562 struct drm_device *dev = node->minor->dev;
d6bbafa1 563 struct drm_i915_private *dev_priv = dev->dev_private;
4e5359cd 564 struct intel_crtc *crtc;
8a270ebf
DV		 565 int ret;
566
567 ret = mutex_lock_interruptible(&dev->struct_mutex);
568 if (ret)
569 return ret;
4e5359cd 570
d3fcc808 571 for_each_intel_crtc(dev, crtc) {
9db4a9c7
JB		 572 const char pipe = pipe_name(crtc->pipe);
573 const char plane = plane_name(crtc->plane);
4e5359cd
SF		 574 struct intel_unpin_work *work;
575
5e2d7afc 576 spin_lock_irq(&dev->event_lock);
4e5359cd
SF		 577 work = crtc->unpin_work;
578 if (work == NULL) {
9db4a9c7 579 seq_printf(m, "No flip due on pipe %c (plane %c)\n",
4e5359cd
SF		 580 pipe, plane);
581 } else {
d6bbafa1
CW		 582 u32 addr;
583
e7d841ca 584 if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9db4a9c7 585 seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
4e5359cd
SF		 586 pipe, plane);
587 } else {
9db4a9c7 588 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
4e5359cd
SF		 589 pipe, plane);
590 }
3a8a946e
DV		 591 if (work->flip_queued_req) {
592 struct intel_engine_cs *ring =
593 i915_gem_request_get_ring(work->flip_queued_req);
594
20e28fba 595 seq_printf(m, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n",
3a8a946e 596 ring->name,
f06cc1b9 597 i915_gem_request_get_seqno(work->flip_queued_req),
d6bbafa1 598 dev_priv->next_seqno,
3a8a946e 599 ring->get_seqno(ring, true),
1b5a433a 600 i915_gem_request_completed(work->flip_queued_req, true));
d6bbafa1
CW		 601 } else
602 seq_printf(m, "Flip not associated with any ring\n");
603 seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
604 work->flip_queued_vblank,
605 work->flip_ready_vblank,
1e3feefd 606 drm_crtc_vblank_count(&crtc->base));
4e5359cd 607 if (work->enable_stall_check)
267f0c90 608 seq_puts(m, "Stall check enabled, ");
4e5359cd 609 else
267f0c90 610 seq_puts(m, "Stall check waiting for page flip ioctl, ");
e7d841ca 611 seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
4e5359cd 612
d6bbafa1
CW		 613 if (INTEL_INFO(dev)->gen >= 4)
614 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane)));
615 else
616 addr = I915_READ(DSPADDR(crtc->plane));
617 seq_printf(m, "Current scanout address 0x%08x\n", addr);
618
4e5359cd 619 if (work->pending_flip_obj) {
d6bbafa1
CW		 620 seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset);
621 seq_printf(m, "MMIO update completed? %d\n", addr == work->gtt_offset);
4e5359cd
SF		 622 }
623 }
5e2d7afc 624 spin_unlock_irq(&dev->event_lock);
4e5359cd
SF		 625 }
626
8a270ebf
DV		 627 mutex_unlock(&dev->struct_mutex);
628
4e5359cd
SF		 629 return 0;
630}
631
493018dc
BV		 632static int i915_gem_batch_pool_info(struct seq_file *m, void *data)
633{
634 struct drm_info_node *node = m->private;
635 struct drm_device *dev = node->minor->dev;
636 struct drm_i915_private *dev_priv = dev->dev_private;
637 struct drm_i915_gem_object *obj;
06fbca71 638 struct intel_engine_cs *ring;
8d9d5744
CW		 639 int total = 0;
640 int ret, i, j;
493018dc
BV		 641
642 ret = mutex_lock_interruptible(&dev->struct_mutex);
643 if (ret)
644 return ret;
645
06fbca71 646 for_each_ring(ring, dev_priv, i) {
8d9d5744
CW		 647 for (j = 0; j < ARRAY_SIZE(ring->batch_pool.cache_list); j++) {
648 int count;
649
650 count = 0;
651 list_for_each_entry(obj,
652 &ring->batch_pool.cache_list[j],
653 batch_pool_link)
654 count++;
655 seq_printf(m, "%s cache[%d]: %d objects\n",
656 ring->name, j, count);
657
658 list_for_each_entry(obj,
659 &ring->batch_pool.cache_list[j],
660 batch_pool_link) {
661 seq_puts(m, " ");
662 describe_obj(m, obj);
663 seq_putc(m, '\n');
664 }
665
666 total += count;
06fbca71 667 }
493018dc
BV		 668 }
669
8d9d5744 670 seq_printf(m, "total: %d\n", total);
493018dc
BV		 671
672 mutex_unlock(&dev->struct_mutex);
673
674 return 0;
675}
676
2017263e
BG		 677static int i915_gem_request_info(struct seq_file *m, void *data)
678{
9f25d007 679 struct drm_info_node *node = m->private;
2017263e 680 struct drm_device *dev = node->minor->dev;
e277a1f8 681 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 682 struct intel_engine_cs *ring;
eed29a5b 683 struct drm_i915_gem_request *req;
2d1070b2 684 int ret, any, i;
de227ef0
CW		 685
686 ret = mutex_lock_interruptible(&dev->struct_mutex);
687 if (ret)
688 return ret;
2017263e 689
2d1070b2 690 any = 0;
a2c7f6fd 691 for_each_ring(ring, dev_priv, i) {
2d1070b2
CW		 692 int count;
693
694 count = 0;
eed29a5b 695 list_for_each_entry(req, &ring->request_list, list)
2d1070b2
CW		 696 count++;
697 if (count == 0)
a2c7f6fd
CW		 698 continue;
699
2d1070b2 700 seq_printf(m, "%s requests: %d\n", ring->name, count);
eed29a5b 701 list_for_each_entry(req, &ring->request_list, list) {
2d1070b2
CW		 702 struct task_struct *task;
703
704 rcu_read_lock();
705 task = NULL;
eed29a5b
DV		 706 if (req->pid)
707 task = pid_task(req->pid, PIDTYPE_PID);
2d1070b2 708 seq_printf(m, " %x @ %d: %s [%d]\n",
eed29a5b
DV		 709 req->seqno,
710 (int) (jiffies - req->emitted_jiffies),
2d1070b2
CW		 711 task ? task->comm : "<unknown>",
712 task ? task->pid : -1);
713 rcu_read_unlock();
c2c347a9 714 }
2d1070b2
CW		 715
716 any++;
2017263e 717 }
de227ef0
CW		 718 mutex_unlock(&dev->struct_mutex);
719
2d1070b2 720 if (any == 0)
267f0c90 721 seq_puts(m, "No requests\n");
c2c347a9 722
2017263e
BG		 723 return 0;
724}
725
b2223497 726static void i915_ring_seqno_info(struct seq_file *m,
a4872ba6 727 struct intel_engine_cs *ring)
b2223497
CW		 728{
729 if (ring->get_seqno) {
20e28fba 730 seq_printf(m, "Current sequence (%s): %x\n",
b2eadbc8 731 ring->name, ring->get_seqno(ring, false));
b2223497
CW		 732 }
733}
734
2017263e
BG		 735static int i915_gem_seqno_info(struct seq_file *m, void *data)
736{
9f25d007 737 struct drm_info_node *node = m->private;
2017263e 738 struct drm_device *dev = node->minor->dev;
e277a1f8 739 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 740 struct intel_engine_cs *ring;
1ec14ad3 741 int ret, i;
de227ef0
CW		 742
743 ret = mutex_lock_interruptible(&dev->struct_mutex);
744 if (ret)
745 return ret;
c8c8fb33 746 intel_runtime_pm_get(dev_priv);
2017263e 747
a2c7f6fd
CW		 748 for_each_ring(ring, dev_priv, i)
749 i915_ring_seqno_info(m, ring);
de227ef0 750
c8c8fb33 751 intel_runtime_pm_put(dev_priv);
de227ef0
CW		 752 mutex_unlock(&dev->struct_mutex);
753
2017263e
BG		 754 return 0;
755}
756
757
758static int i915_interrupt_info(struct seq_file *m, void *data)
759{
9f25d007 760 struct drm_info_node *node = m->private;
2017263e 761 struct drm_device *dev = node->minor->dev;
e277a1f8 762 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 763 struct intel_engine_cs *ring;
9db4a9c7 764 int ret, i, pipe;
de227ef0
CW		 765
766 ret = mutex_lock_interruptible(&dev->struct_mutex);
767 if (ret)
768 return ret;
c8c8fb33 769 intel_runtime_pm_get(dev_priv);
2017263e 770
74e1ca8c 771 if (IS_CHERRYVIEW(dev)) {
74e1ca8c
VS		 772 seq_printf(m, "Master Interrupt Control:\t%08x\n",
773 I915_READ(GEN8_MASTER_IRQ));
774
775 seq_printf(m, "Display IER:\t%08x\n",
776 I915_READ(VLV_IER));
777 seq_printf(m, "Display IIR:\t%08x\n",
778 I915_READ(VLV_IIR));
779 seq_printf(m, "Display IIR_RW:\t%08x\n",
780 I915_READ(VLV_IIR_RW));
781 seq_printf(m, "Display IMR:\t%08x\n",
782 I915_READ(VLV_IMR));
055e393f 783 for_each_pipe(dev_priv, pipe)
74e1ca8c
VS		 784 seq_printf(m, "Pipe %c stat:\t%08x\n",
785 pipe_name(pipe),
786 I915_READ(PIPESTAT(pipe)));
787
788 seq_printf(m, "Port hotplug:\t%08x\n",
789 I915_READ(PORT_HOTPLUG_EN));
790 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
791 I915_READ(VLV_DPFLIPSTAT));
792 seq_printf(m, "DPINVGTT:\t%08x\n",
793 I915_READ(DPINVGTT));
794
795 for (i = 0; i < 4; i++) {
796 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
797 i, I915_READ(GEN8_GT_IMR(i)));
798 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
799 i, I915_READ(GEN8_GT_IIR(i)));
800 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
801 i, I915_READ(GEN8_GT_IER(i)));
802 }
803
804 seq_printf(m, "PCU interrupt mask:\t%08x\n",
805 I915_READ(GEN8_PCU_IMR));
806 seq_printf(m, "PCU interrupt identity:\t%08x\n",
807 I915_READ(GEN8_PCU_IIR));
808 seq_printf(m, "PCU interrupt enable:\t%08x\n",
809 I915_READ(GEN8_PCU_IER));
810 } else if (INTEL_INFO(dev)->gen >= 8) {
a123f157
BW		 811 seq_printf(m, "Master Interrupt Control:\t%08x\n",
812 I915_READ(GEN8_MASTER_IRQ));
813
814 for (i = 0; i < 4; i++) {
815 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
816 i, I915_READ(GEN8_GT_IMR(i)));
817 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
818 i, I915_READ(GEN8_GT_IIR(i)));
819 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
820 i, I915_READ(GEN8_GT_IER(i)));
821 }
822
055e393f 823 for_each_pipe(dev_priv, pipe) {
f458ebbc 824 if (!intel_display_power_is_enabled(dev_priv,
22c59960
PZ		 825 POWER_DOMAIN_PIPE(pipe))) {
826 seq_printf(m, "Pipe %c power disabled\n",
827 pipe_name(pipe));
828 continue;
829 }
a123f157 830 seq_printf(m, "Pipe %c IMR:\t%08x\n",
07d27e20
DL		 831 pipe_name(pipe),
832 I915_READ(GEN8_DE_PIPE_IMR(pipe)));
a123f157 833 seq_printf(m, "Pipe %c IIR:\t%08x\n",
07d27e20
DL		 834 pipe_name(pipe),
835 I915_READ(GEN8_DE_PIPE_IIR(pipe)));
a123f157 836 seq_printf(m, "Pipe %c IER:\t%08x\n",
07d27e20
DL		 837 pipe_name(pipe),
838 I915_READ(GEN8_DE_PIPE_IER(pipe)));
a123f157
BW		 839 }
840
841 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
842 I915_READ(GEN8_DE_PORT_IMR));
843 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
844 I915_READ(GEN8_DE_PORT_IIR));
845 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
846 I915_READ(GEN8_DE_PORT_IER));
847
848 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
849 I915_READ(GEN8_DE_MISC_IMR));
850 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
851 I915_READ(GEN8_DE_MISC_IIR));
852 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
853 I915_READ(GEN8_DE_MISC_IER));
854
855 seq_printf(m, "PCU interrupt mask:\t%08x\n",
856 I915_READ(GEN8_PCU_IMR));
857 seq_printf(m, "PCU interrupt identity:\t%08x\n",
858 I915_READ(GEN8_PCU_IIR));
859 seq_printf(m, "PCU interrupt enable:\t%08x\n",
860 I915_READ(GEN8_PCU_IER));
861 } else if (IS_VALLEYVIEW(dev)) {
7e231dbe
JB		 862 seq_printf(m, "Display IER:\t%08x\n",
863 I915_READ(VLV_IER));
864 seq_printf(m, "Display IIR:\t%08x\n",
865 I915_READ(VLV_IIR));
866 seq_printf(m, "Display IIR_RW:\t%08x\n",
867 I915_READ(VLV_IIR_RW));
868 seq_printf(m, "Display IMR:\t%08x\n",
869 I915_READ(VLV_IMR));
055e393f 870 for_each_pipe(dev_priv, pipe)
7e231dbe
JB		 871 seq_printf(m, "Pipe %c stat:\t%08x\n",
872 pipe_name(pipe),
873 I915_READ(PIPESTAT(pipe)));
874
875 seq_printf(m, "Master IER:\t%08x\n",
876 I915_READ(VLV_MASTER_IER));
877
878 seq_printf(m, "Render IER:\t%08x\n",
879 I915_READ(GTIER));
880 seq_printf(m, "Render IIR:\t%08x\n",
881 I915_READ(GTIIR));
882 seq_printf(m, "Render IMR:\t%08x\n",
883 I915_READ(GTIMR));
884
885 seq_printf(m, "PM IER:\t\t%08x\n",
886 I915_READ(GEN6_PMIER));
887 seq_printf(m, "PM IIR:\t\t%08x\n",
888 I915_READ(GEN6_PMIIR));
889 seq_printf(m, "PM IMR:\t\t%08x\n",
890 I915_READ(GEN6_PMIMR));
891
892 seq_printf(m, "Port hotplug:\t%08x\n",
893 I915_READ(PORT_HOTPLUG_EN));
894 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
895 I915_READ(VLV_DPFLIPSTAT));
896 seq_printf(m, "DPINVGTT:\t%08x\n",
897 I915_READ(DPINVGTT));
898
899 } else if (!HAS_PCH_SPLIT(dev)) {
5f6a1695
ZW		 900 seq_printf(m, "Interrupt enable: %08x\n",
901 I915_READ(IER));
902 seq_printf(m, "Interrupt identity: %08x\n",
903 I915_READ(IIR));
904 seq_printf(m, "Interrupt mask: %08x\n",
905 I915_READ(IMR));
055e393f 906 for_each_pipe(dev_priv, pipe)
9db4a9c7
JB		 907 seq_printf(m, "Pipe %c stat: %08x\n",
908 pipe_name(pipe),
909 I915_READ(PIPESTAT(pipe)));
5f6a1695
ZW		 910 } else {
911 seq_printf(m, "North Display Interrupt enable: %08x\n",
912 I915_READ(DEIER));
913 seq_printf(m, "North Display Interrupt identity: %08x\n",
914 I915_READ(DEIIR));
915 seq_printf(m, "North Display Interrupt mask: %08x\n",
916 I915_READ(DEIMR));
917 seq_printf(m, "South Display Interrupt enable: %08x\n",
918 I915_READ(SDEIER));
919 seq_printf(m, "South Display Interrupt identity: %08x\n",
920 I915_READ(SDEIIR));
921 seq_printf(m, "South Display Interrupt mask: %08x\n",
922 I915_READ(SDEIMR));
923 seq_printf(m, "Graphics Interrupt enable: %08x\n",
924 I915_READ(GTIER));
925 seq_printf(m, "Graphics Interrupt identity: %08x\n",
926 I915_READ(GTIIR));
927 seq_printf(m, "Graphics Interrupt mask: %08x\n",
928 I915_READ(GTIMR));
929 }
a2c7f6fd 930 for_each_ring(ring, dev_priv, i) {
a123f157 931 if (INTEL_INFO(dev)->gen >= 6) {
a2c7f6fd
CW		 932 seq_printf(m,
933 "Graphics Interrupt mask (%s): %08x\n",
934 ring->name, I915_READ_IMR(ring));
9862e600 935 }
a2c7f6fd 936 i915_ring_seqno_info(m, ring);
9862e600 937 }
c8c8fb33 938 intel_runtime_pm_put(dev_priv);
de227ef0
CW		 939 mutex_unlock(&dev->struct_mutex);
940
2017263e
BG		 941 return 0;
942}
943
a6172a80
CW		 944static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
945{
9f25d007 946 struct drm_info_node *node = m->private;
a6172a80 947 struct drm_device *dev = node->minor->dev;
e277a1f8 948 struct drm_i915_private *dev_priv = dev->dev_private;
de227ef0
CW		 949 int i, ret;
950
951 ret = mutex_lock_interruptible(&dev->struct_mutex);
952 if (ret)
953 return ret;
a6172a80
CW		 954
955 seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
956 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
957 for (i = 0; i < dev_priv->num_fence_regs; i++) {
05394f39 958 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
a6172a80 959
6c085a72
CW		 960 seq_printf(m, "Fence %d, pin count = %d, object = ",
961 i, dev_priv->fence_regs[i].pin_count);
c2c347a9 962 if (obj == NULL)
267f0c90 963 seq_puts(m, "unused");
c2c347a9 964 else
05394f39 965 describe_obj(m, obj);
267f0c90 966 seq_putc(m, '\n');
a6172a80
CW		 967 }
968
05394f39 969 mutex_unlock(&dev->struct_mutex);
a6172a80
CW		 970 return 0;
971}
972
2017263e
BG		 973static int i915_hws_info(struct seq_file *m, void *data)
974{
9f25d007 975 struct drm_info_node *node = m->private;
2017263e 976 struct drm_device *dev = node->minor->dev;
e277a1f8 977 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 978 struct intel_engine_cs *ring;
1a240d4d 979 const u32 *hws;
4066c0ae
CW		 980 int i;
981
1ec14ad3 982 ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
1a240d4d 983 hws = ring->status_page.page_addr;
2017263e
BG		 984 if (hws == NULL)
985 return 0;
986
987 for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
988 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
989 i * 4,
990 hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
991 }
992 return 0;
993}
994
d5442303
DV		 995static ssize_t
996i915_error_state_write(struct file *filp,
997 const char __user *ubuf,
998 size_t cnt,
999 loff_t *ppos)
1000{
edc3d884 1001 struct i915_error_state_file_priv *error_priv = filp->private_data;
d5442303 1002 struct drm_device *dev = error_priv->dev;
22bcfc6a 1003 int ret;
d5442303
DV		 1004
1005 DRM_DEBUG_DRIVER("Resetting error state\n");
1006
22bcfc6a
DV		 1007 ret = mutex_lock_interruptible(&dev->struct_mutex);
1008 if (ret)
1009 return ret;
1010
d5442303
DV		 1011 i915_destroy_error_state(dev);
1012 mutex_unlock(&dev->struct_mutex);
1013
1014 return cnt;
1015}
1016
1017static int i915_error_state_open(struct inode *inode, struct file *file)
1018{
1019 struct drm_device *dev = inode->i_private;
d5442303 1020 struct i915_error_state_file_priv *error_priv;
d5442303
DV		 1021
1022 error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
1023 if (!error_priv)
1024 return -ENOMEM;
1025
1026 error_priv->dev = dev;
1027
95d5bfb3 1028 i915_error_state_get(dev, error_priv);
d5442303 1029
edc3d884
MK		 1030 file->private_data = error_priv;
1031
1032 return 0;
d5442303
DV		 1033}
1034
1035static int i915_error_state_release(struct inode *inode, struct file *file)
1036{
edc3d884 1037 struct i915_error_state_file_priv *error_priv = file->private_data;
d5442303 1038
95d5bfb3 1039 i915_error_state_put(error_priv);
d5442303
DV		 1040 kfree(error_priv);
1041
edc3d884
MK		 1042 return 0;
1043}
1044
4dc955f7
MK		 1045static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
1046 size_t count, loff_t *pos)
1047{
1048 struct i915_error_state_file_priv *error_priv = file->private_data;
1049 struct drm_i915_error_state_buf error_str;
1050 loff_t tmp_pos = 0;
1051 ssize_t ret_count = 0;
1052 int ret;
1053
0a4cd7c8 1054 ret = i915_error_state_buf_init(&error_str, to_i915(error_priv->dev), count, *pos);
4dc955f7
MK		 1055 if (ret)
1056 return ret;
edc3d884 1057
fc16b48b 1058 ret = i915_error_state_to_str(&error_str, error_priv);
edc3d884
MK		 1059 if (ret)
1060 goto out;
1061
edc3d884
MK		 1062 ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
1063 error_str.buf,
1064 error_str.bytes);
1065
1066 if (ret_count < 0)
1067 ret = ret_count;
1068 else
1069 *pos = error_str.start + ret_count;
1070out:
4dc955f7 1071 i915_error_state_buf_release(&error_str);
edc3d884 1072 return ret ?: ret_count;
d5442303
DV		 1073}
1074
1075static const struct file_operations i915_error_state_fops = {
1076 .owner = THIS_MODULE,
1077 .open = i915_error_state_open,
edc3d884 1078 .read = i915_error_state_read,
d5442303
DV		 1079 .write = i915_error_state_write,
1080 .llseek = default_llseek,
1081 .release = i915_error_state_release,
1082};
1083
647416f9
KC		 1084static int
1085i915_next_seqno_get(void *data, u64 *val)
40633219 1086{
647416f9 1087 struct drm_device *dev = data;
e277a1f8 1088 struct drm_i915_private *dev_priv = dev->dev_private;
40633219
MK		 1089 int ret;
1090
1091 ret = mutex_lock_interruptible(&dev->struct_mutex);
1092 if (ret)
1093 return ret;
1094
647416f9 1095 *val = dev_priv->next_seqno;
40633219
MK		 1096 mutex_unlock(&dev->struct_mutex);
1097
647416f9 1098 return 0;
40633219
MK		 1099}
1100
647416f9
KC		 1101static int
1102i915_next_seqno_set(void *data, u64 val)
1103{
1104 struct drm_device *dev = data;
40633219
MK		 1105 int ret;
1106
40633219
MK		 1107 ret = mutex_lock_interruptible(&dev->struct_mutex);
1108 if (ret)
1109 return ret;
1110
e94fbaa8 1111 ret = i915_gem_set_seqno(dev, val);
40633219
MK		 1112 mutex_unlock(&dev->struct_mutex);
1113
647416f9 1114 return ret;
40633219
MK		 1115}
1116
647416f9
KC		 1117DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
1118 i915_next_seqno_get, i915_next_seqno_set,
3a3b4f98 1119 "0x%llx\n");
40633219 1120
adb4bd12 1121static int i915_frequency_info(struct seq_file *m, void *unused)
f97108d1 1122{
9f25d007 1123 struct drm_info_node *node = m->private;
f97108d1 1124 struct drm_device *dev = node->minor->dev;
e277a1f8 1125 struct drm_i915_private *dev_priv = dev->dev_private;
c8c8fb33
PZ		 1126 int ret = 0;
1127
1128 intel_runtime_pm_get(dev_priv);
3b8d8d91 1129
5c9669ce
TR		 1130 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1131
3b8d8d91
JB		 1132 if (IS_GEN5(dev)) {
1133 u16 rgvswctl = I915_READ16(MEMSWCTL);
1134 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1135
1136 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1137 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1138 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1139 MEMSTAT_VID_SHIFT);
1140 seq_printf(m, "Current P-state: %d\n",
1141 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
daa3afb2 1142 } else if (IS_GEN6(dev) || (IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) ||
60260a5b 1143 IS_BROADWELL(dev) || IS_GEN9(dev)) {
35040562
BP		 1144 u32 rp_state_limits;
1145 u32 gt_perf_status;
1146 u32 rp_state_cap;
0d8f9491 1147 u32 rpmodectl, rpinclimit, rpdeclimit;
8e8c06cd 1148 u32 rpstat, cagf, reqf;
ccab5c82
JB		 1149 u32 rpupei, rpcurup, rpprevup;
1150 u32 rpdownei, rpcurdown, rpprevdown;
9dd3c605 1151 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
3b8d8d91
JB		 1152 int max_freq;
1153
35040562
BP		 1154 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1155 if (IS_BROXTON(dev)) {
1156 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
1157 gt_perf_status = I915_READ(BXT_GT_PERF_STATUS);
1158 } else {
1159 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
1160 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1161 }
1162
3b8d8d91 1163 /* RPSTAT1 is in the GT power well */
d1ebd816
BW		 1164 ret = mutex_lock_interruptible(&dev->struct_mutex);
1165 if (ret)
c8c8fb33 1166 goto out;
d1ebd816 1167
59bad947 1168 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
3b8d8d91 1169
8e8c06cd 1170 reqf = I915_READ(GEN6_RPNSWREQ);
60260a5b
AG		 1171 if (IS_GEN9(dev))
1172 reqf >>= 23;
1173 else {
1174 reqf &= ~GEN6_TURBO_DISABLE;
1175 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1176 reqf >>= 24;
1177 else
1178 reqf >>= 25;
1179 }
7c59a9c1 1180 reqf = intel_gpu_freq(dev_priv, reqf);
8e8c06cd 1181
0d8f9491
CW		 1182 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1183 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1184 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1185
ccab5c82
JB		 1186 rpstat = I915_READ(GEN6_RPSTAT1);
1187 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
1188 rpcurup = I915_READ(GEN6_RP_CUR_UP);
1189 rpprevup = I915_READ(GEN6_RP_PREV_UP);
1190 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
1191 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
1192 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
60260a5b
AG		 1193 if (IS_GEN9(dev))
1194 cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
1195 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
f82855d3
BW		 1196 cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1197 else
1198 cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
7c59a9c1 1199 cagf = intel_gpu_freq(dev_priv, cagf);
ccab5c82 1200
59bad947 1201 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
d1ebd816
BW		 1202 mutex_unlock(&dev->struct_mutex);
1203
9dd3c605
PZ		 1204 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1205 pm_ier = I915_READ(GEN6_PMIER);
1206 pm_imr = I915_READ(GEN6_PMIMR);
1207 pm_isr = I915_READ(GEN6_PMISR);
1208 pm_iir = I915_READ(GEN6_PMIIR);
1209 pm_mask = I915_READ(GEN6_PMINTRMSK);
1210 } else {
1211 pm_ier = I915_READ(GEN8_GT_IER(2));
1212 pm_imr = I915_READ(GEN8_GT_IMR(2));
1213 pm_isr = I915_READ(GEN8_GT_ISR(2));
1214 pm_iir = I915_READ(GEN8_GT_IIR(2));
1215 pm_mask = I915_READ(GEN6_PMINTRMSK);
1216 }
0d8f9491 1217 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
9dd3c605 1218 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
3b8d8d91 1219 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
3b8d8d91 1220 seq_printf(m, "Render p-state ratio: %d\n",
60260a5b 1221 (gt_perf_status & (IS_GEN9(dev) ? 0x1ff00 : 0xff00)) >> 8);
3b8d8d91
JB		 1222 seq_printf(m, "Render p-state VID: %d\n",
1223 gt_perf_status & 0xff);
1224 seq_printf(m, "Render p-state limit: %d\n",
1225 rp_state_limits & 0xff);
0d8f9491
CW		 1226 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1227 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1228 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1229 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
8e8c06cd 1230 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
f82855d3 1231 seq_printf(m, "CAGF: %dMHz\n", cagf);
ccab5c82
JB		 1232 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
1233 GEN6_CURICONT_MASK);
1234 seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
1235 GEN6_CURBSYTAVG_MASK);
1236 seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
1237 GEN6_CURBSYTAVG_MASK);
d86ed34a
CW		 1238 seq_printf(m, "Up threshold: %d%%\n",
1239 dev_priv->rps.up_threshold);
1240
ccab5c82
JB		 1241 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
1242 GEN6_CURIAVG_MASK);
1243 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
1244 GEN6_CURBSYTAVG_MASK);
1245 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
1246 GEN6_CURBSYTAVG_MASK);
d86ed34a
CW		 1247 seq_printf(m, "Down threshold: %d%%\n",
1248 dev_priv->rps.down_threshold);
3b8d8d91 1249
35040562
BP		 1250 max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 0 :
1251 rp_state_cap >> 16) & 0xff;
60260a5b 1252 max_freq *= (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1);
3b8d8d91 1253 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
7c59a9c1 1254 intel_gpu_freq(dev_priv, max_freq));
3b8d8d91
JB		 1255
1256 max_freq = (rp_state_cap & 0xff00) >> 8;
60260a5b 1257 max_freq *= (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1);
3b8d8d91 1258 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
7c59a9c1 1259 intel_gpu_freq(dev_priv, max_freq));
3b8d8d91 1260
35040562
BP		 1261 max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 16 :
1262 rp_state_cap >> 0) & 0xff;
60260a5b 1263 max_freq *= (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1);
3b8d8d91 1264 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
7c59a9c1 1265 intel_gpu_freq(dev_priv, max_freq));
31c77388 1266 seq_printf(m, "Max overclocked frequency: %dMHz\n",
7c59a9c1 1267 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
aed242ff 1268
d86ed34a
CW		 1269 seq_printf(m, "Current freq: %d MHz\n",
1270 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1271 seq_printf(m, "Actual freq: %d MHz\n", cagf);
aed242ff
CW		 1272 seq_printf(m, "Idle freq: %d MHz\n",
1273 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
d86ed34a
CW		 1274 seq_printf(m, "Min freq: %d MHz\n",
1275 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1276 seq_printf(m, "Max freq: %d MHz\n",
1277 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1278 seq_printf(m,
1279 "efficient (RPe) frequency: %d MHz\n",
1280 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
0a073b84 1281 } else if (IS_VALLEYVIEW(dev)) {
03af2045 1282 u32 freq_sts;
0a073b84 1283
259bd5d4 1284 mutex_lock(&dev_priv->rps.hw_lock);
64936258 1285 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
0a073b84
JB		 1286 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1287 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1288
d86ed34a
CW		 1289 seq_printf(m, "actual GPU freq: %d MHz\n",
1290 intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
1291
1292 seq_printf(m, "current GPU freq: %d MHz\n",
1293 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1294
0a073b84 1295 seq_printf(m, "max GPU freq: %d MHz\n",
7c59a9c1 1296 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
0a073b84 1297
0a073b84 1298 seq_printf(m, "min GPU freq: %d MHz\n",
7c59a9c1 1299 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
03af2045 1300
aed242ff
CW		 1301 seq_printf(m, "idle GPU freq: %d MHz\n",
1302 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1303
7c59a9c1
VS		 1304 seq_printf(m,
1305 "efficient (RPe) frequency: %d MHz\n",
1306 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
259bd5d4 1307 mutex_unlock(&dev_priv->rps.hw_lock);
3b8d8d91 1308 } else {
267f0c90 1309 seq_puts(m, "no P-state info available\n");
3b8d8d91 1310 }
f97108d1 1311
c8c8fb33
PZ		 1312out:
1313 intel_runtime_pm_put(dev_priv);
1314 return ret;
f97108d1
JB		 1315}
1316
f654449a
CW		 1317static int i915_hangcheck_info(struct seq_file *m, void *unused)
1318{
1319 struct drm_info_node *node = m->private;
ebbc7546
MK		 1320 struct drm_device *dev = node->minor->dev;
1321 struct drm_i915_private *dev_priv = dev->dev_private;
f654449a 1322 struct intel_engine_cs *ring;
ebbc7546
MK		 1323 u64 acthd[I915_NUM_RINGS];
1324 u32 seqno[I915_NUM_RINGS];
f654449a
CW		 1325 int i;
1326
1327 if (!i915.enable_hangcheck) {
1328 seq_printf(m, "Hangcheck disabled\n");
1329 return 0;
1330 }
1331
ebbc7546
MK		 1332 intel_runtime_pm_get(dev_priv);
1333
1334 for_each_ring(ring, dev_priv, i) {
1335 seqno[i] = ring->get_seqno(ring, false);
1336 acthd[i] = intel_ring_get_active_head(ring);
1337 }
1338
1339 intel_runtime_pm_put(dev_priv);
1340
f654449a
CW		 1341 if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) {
1342 seq_printf(m, "Hangcheck active, fires in %dms\n",
1343 jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires -
1344 jiffies));
1345 } else
1346 seq_printf(m, "Hangcheck inactive\n");
1347
1348 for_each_ring(ring, dev_priv, i) {
1349 seq_printf(m, "%s:\n", ring->name);
1350 seq_printf(m, "\tseqno = %x [current %x]\n",
ebbc7546 1351 ring->hangcheck.seqno, seqno[i]);
f654449a
CW		 1352 seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
1353 (long long)ring->hangcheck.acthd,
ebbc7546 1354 (long long)acthd[i]);
f654449a
CW		 1355 seq_printf(m, "\tmax ACTHD = 0x%08llx\n",
1356 (long long)ring->hangcheck.max_acthd);
ebbc7546
MK		 1357 seq_printf(m, "\tscore = %d\n", ring->hangcheck.score);
1358 seq_printf(m, "\taction = %d\n", ring->hangcheck.action);
f654449a
CW		 1359 }
1360
1361 return 0;
1362}
1363
4d85529d 1364static int ironlake_drpc_info(struct seq_file *m)
f97108d1 1365{
9f25d007 1366 struct drm_info_node *node = m->private;
f97108d1 1367 struct drm_device *dev = node->minor->dev;
e277a1f8 1368 struct drm_i915_private *dev_priv = dev->dev_private;
616fdb5a
BW		 1369 u32 rgvmodectl, rstdbyctl;
1370 u16 crstandvid;
1371 int ret;
1372
1373 ret = mutex_lock_interruptible(&dev->struct_mutex);
1374 if (ret)
1375 return ret;
c8c8fb33 1376 intel_runtime_pm_get(dev_priv);
616fdb5a
BW		 1377
1378 rgvmodectl = I915_READ(MEMMODECTL);
1379 rstdbyctl = I915_READ(RSTDBYCTL);
1380 crstandvid = I915_READ16(CRSTANDVID);
1381
c8c8fb33 1382 intel_runtime_pm_put(dev_priv);
616fdb5a 1383 mutex_unlock(&dev->struct_mutex);
f97108d1 1384
742f491d 1385 seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN));
f97108d1
JB		 1386 seq_printf(m, "Boost freq: %d\n",
1387 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1388 MEMMODE_BOOST_FREQ_SHIFT);
1389 seq_printf(m, "HW control enabled: %s\n",
742f491d 1390 yesno(rgvmodectl & MEMMODE_HWIDLE_EN));
f97108d1 1391 seq_printf(m, "SW control enabled: %s\n",
742f491d 1392 yesno(rgvmodectl & MEMMODE_SWMODE_EN));
f97108d1 1393 seq_printf(m, "Gated voltage change: %s\n",
742f491d 1394 yesno(rgvmodectl & MEMMODE_RCLK_GATE));
f97108d1
JB		 1395 seq_printf(m, "Starting frequency: P%d\n",
1396 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
7648fa99 1397 seq_printf(m, "Max P-state: P%d\n",
f97108d1 1398 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
7648fa99
JB		 1399 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1400 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1401 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1402 seq_printf(m, "Render standby enabled: %s\n",
742f491d 1403 yesno(!(rstdbyctl & RCX_SW_EXIT)));
267f0c90 1404 seq_puts(m, "Current RS state: ");
88271da3
JB		 1405 switch (rstdbyctl & RSX_STATUS_MASK) {
1406 case RSX_STATUS_ON:
267f0c90 1407 seq_puts(m, "on\n");
88271da3
JB		 1408 break;
1409 case RSX_STATUS_RC1:
267f0c90 1410 seq_puts(m, "RC1\n");
88271da3
JB		 1411 break;
1412 case RSX_STATUS_RC1E:
267f0c90 1413 seq_puts(m, "RC1E\n");
88271da3
JB		 1414 break;
1415 case RSX_STATUS_RS1:
267f0c90 1416 seq_puts(m, "RS1\n");
88271da3
JB		 1417 break;
1418 case RSX_STATUS_RS2:
267f0c90 1419 seq_puts(m, "RS2 (RC6)\n");
88271da3
JB		 1420 break;
1421 case RSX_STATUS_RS3:
267f0c90 1422 seq_puts(m, "RC3 (RC6+)\n");
88271da3
JB		 1423 break;
1424 default:
267f0c90 1425 seq_puts(m, "unknown\n");
88271da3
JB		 1426 break;
1427 }
f97108d1
JB		 1428
1429 return 0;
1430}
1431
f65367b5 1432static int i915_forcewake_domains(struct seq_file *m, void *data)
669ab5aa 1433{
b2cff0db
CW		 1434 struct drm_info_node *node = m->private;
1435 struct drm_device *dev = node->minor->dev;
1436 struct drm_i915_private *dev_priv = dev->dev_private;
1437 struct intel_uncore_forcewake_domain *fw_domain;
b2cff0db
CW		 1438 int i;
1439
1440 spin_lock_irq(&dev_priv->uncore.lock);
1441 for_each_fw_domain(fw_domain, dev_priv, i) {
1442 seq_printf(m, "%s.wake_count = %u\n",
05a2fb15 1443 intel_uncore_forcewake_domain_to_str(i),
b2cff0db
CW		 1444 fw_domain->wake_count);
1445 }
1446 spin_unlock_irq(&dev_priv->uncore.lock);
669ab5aa 1447
b2cff0db
CW		 1448 return 0;
1449}
1450
1451static int vlv_drpc_info(struct seq_file *m)
1452{
9f25d007 1453 struct drm_info_node *node = m->private;
669ab5aa
D		 1454 struct drm_device *dev = node->minor->dev;
1455 struct drm_i915_private *dev_priv = dev->dev_private;
6b312cd3 1456 u32 rpmodectl1, rcctl1, pw_status;
669ab5aa 1457
d46c0517
ID		 1458 intel_runtime_pm_get(dev_priv);
1459
6b312cd3 1460 pw_status = I915_READ(VLV_GTLC_PW_STATUS);
669ab5aa
D		 1461 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1462 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1463
d46c0517
ID		 1464 intel_runtime_pm_put(dev_priv);
1465
669ab5aa
D		 1466 seq_printf(m, "Video Turbo Mode: %s\n",
1467 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1468 seq_printf(m, "Turbo enabled: %s\n",
1469 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1470 seq_printf(m, "HW control enabled: %s\n",
1471 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1472 seq_printf(m, "SW control enabled: %s\n",
1473 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1474 GEN6_RP_MEDIA_SW_MODE));
1475 seq_printf(m, "RC6 Enabled: %s\n",
1476 yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1477 GEN6_RC_CTL_EI_MODE(1))));
1478 seq_printf(m, "Render Power Well: %s\n",
6b312cd3 1479 (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
669ab5aa 1480 seq_printf(m, "Media Power Well: %s\n",
6b312cd3 1481 (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
669ab5aa 1482
9cc19be5
ID		 1483 seq_printf(m, "Render RC6 residency since boot: %u\n",
1484 I915_READ(VLV_GT_RENDER_RC6));
1485 seq_printf(m, "Media RC6 residency since boot: %u\n",
1486 I915_READ(VLV_GT_MEDIA_RC6));
1487
f65367b5 1488 return i915_forcewake_domains(m, NULL);
669ab5aa
D		 1489}
1490
4d85529d
BW		 1491static int gen6_drpc_info(struct seq_file *m)
1492{
9f25d007 1493 struct drm_info_node *node = m->private;
4d85529d
BW		 1494 struct drm_device *dev = node->minor->dev;
1495 struct drm_i915_private *dev_priv = dev->dev_private;
ecd8faea 1496 u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
93b525dc 1497 unsigned forcewake_count;
aee56cff 1498 int count = 0, ret;
4d85529d
BW		 1499
1500 ret = mutex_lock_interruptible(&dev->struct_mutex);
1501 if (ret)
1502 return ret;
c8c8fb33 1503 intel_runtime_pm_get(dev_priv);
4d85529d 1504
907b28c5 1505 spin_lock_irq(&dev_priv->uncore.lock);
b2cff0db 1506 forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count;
907b28c5 1507 spin_unlock_irq(&dev_priv->uncore.lock);
93b525dc
DV		 1508
1509 if (forcewake_count) {
267f0c90
DL		 1510 seq_puts(m, "RC information inaccurate because somebody "
1511 "holds a forcewake reference \n");
4d85529d
BW		 1512 } else {
1513 /* NB: we cannot use forcewake, else we read the wrong values */
1514 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1515 udelay(10);
1516 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1517 }
1518
1519 gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS);
ed71f1b4 1520 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
4d85529d
BW		 1521
1522 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1523 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1524 mutex_unlock(&dev->struct_mutex);
44cbd338
BW		 1525 mutex_lock(&dev_priv->rps.hw_lock);
1526 sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1527 mutex_unlock(&dev_priv->rps.hw_lock);
4d85529d 1528
c8c8fb33
PZ		 1529 intel_runtime_pm_put(dev_priv);
1530
4d85529d
BW		 1531 seq_printf(m, "Video Turbo Mode: %s\n",
1532 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1533 seq_printf(m, "HW control enabled: %s\n",
1534 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1535 seq_printf(m, "SW control enabled: %s\n",
1536 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1537 GEN6_RP_MEDIA_SW_MODE));
fff24e21 1538 seq_printf(m, "RC1e Enabled: %s\n",
4d85529d
BW		 1539 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1540 seq_printf(m, "RC6 Enabled: %s\n",
1541 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1542 seq_printf(m, "Deep RC6 Enabled: %s\n",
1543 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1544 seq_printf(m, "Deepest RC6 Enabled: %s\n",
1545 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
267f0c90 1546 seq_puts(m, "Current RC state: ");
4d85529d
BW		 1547 switch (gt_core_status & GEN6_RCn_MASK) {
1548 case GEN6_RC0:
1549 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
267f0c90 1550 seq_puts(m, "Core Power Down\n");
4d85529d 1551 else
267f0c90 1552 seq_puts(m, "on\n");
4d85529d
BW		 1553 break;
1554 case GEN6_RC3:
267f0c90 1555 seq_puts(m, "RC3\n");
4d85529d
BW		 1556 break;
1557 case GEN6_RC6:
267f0c90 1558 seq_puts(m, "RC6\n");
4d85529d
BW		 1559 break;
1560 case GEN6_RC7:
267f0c90 1561 seq_puts(m, "RC7\n");
4d85529d
BW		 1562 break;
1563 default:
267f0c90 1564 seq_puts(m, "Unknown\n");
4d85529d
BW		 1565 break;
1566 }
1567
1568 seq_printf(m, "Core Power Down: %s\n",
1569 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
cce66a28
BW		 1570
1571 /* Not exactly sure what this is */
1572 seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1573 I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1574 seq_printf(m, "RC6 residency since boot: %u\n",
1575 I915_READ(GEN6_GT_GFX_RC6));
1576 seq_printf(m, "RC6+ residency since boot: %u\n",
1577 I915_READ(GEN6_GT_GFX_RC6p));
1578 seq_printf(m, "RC6++ residency since boot: %u\n",
1579 I915_READ(GEN6_GT_GFX_RC6pp));
1580
ecd8faea
BW		 1581 seq_printf(m, "RC6 voltage: %dmV\n",
1582 GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1583 seq_printf(m, "RC6+ voltage: %dmV\n",
1584 GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1585 seq_printf(m, "RC6++ voltage: %dmV\n",
1586 GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
4d85529d
BW		 1587 return 0;
1588}
1589
1590static int i915_drpc_info(struct seq_file *m, void *unused)
1591{
9f25d007 1592 struct drm_info_node *node = m->private;
4d85529d
BW		 1593 struct drm_device *dev = node->minor->dev;
1594
669ab5aa
D		 1595 if (IS_VALLEYVIEW(dev))
1596 return vlv_drpc_info(m);
ac66cf4b 1597 else if (INTEL_INFO(dev)->gen >= 6)
4d85529d
BW		 1598 return gen6_drpc_info(m);
1599 else
1600 return ironlake_drpc_info(m);
1601}
1602
9a851789
DV		 1603static int i915_frontbuffer_tracking(struct seq_file *m, void *unused)
1604{
1605 struct drm_info_node *node = m->private;
1606 struct drm_device *dev = node->minor->dev;
1607 struct drm_i915_private *dev_priv = dev->dev_private;
1608
1609 seq_printf(m, "FB tracking busy bits: 0x%08x\n",
1610 dev_priv->fb_tracking.busy_bits);
1611
1612 seq_printf(m, "FB tracking flip bits: 0x%08x\n",
1613 dev_priv->fb_tracking.flip_bits);
1614
1615 return 0;
1616}
1617
b5e50c3f
JB		 1618static int i915_fbc_status(struct seq_file *m, void *unused)
1619{
9f25d007 1620 struct drm_info_node *node = m->private;
b5e50c3f 1621 struct drm_device *dev = node->minor->dev;
e277a1f8 1622 struct drm_i915_private *dev_priv = dev->dev_private;
b5e50c3f 1623
3a77c4c4 1624 if (!HAS_FBC(dev)) {
267f0c90 1625 seq_puts(m, "FBC unsupported on this chipset\n");
b5e50c3f
JB		 1626 return 0;
1627 }
1628
36623ef8 1629 intel_runtime_pm_get(dev_priv);
25ad93fd 1630 mutex_lock(&dev_priv->fbc.lock);
36623ef8 1631
7733b49b 1632 if (intel_fbc_enabled(dev_priv))
267f0c90 1633 seq_puts(m, "FBC enabled\n");
2e8144a5
PZ		 1634 else
1635 seq_printf(m, "FBC disabled: %s\n",
1636 intel_no_fbc_reason_str(dev_priv->fbc.no_fbc_reason));
36623ef8 1637
31b9df10
PZ		 1638 if (INTEL_INFO(dev_priv)->gen >= 7)
1639 seq_printf(m, "Compressing: %s\n",
1640 yesno(I915_READ(FBC_STATUS2) &
1641 FBC_COMPRESSION_MASK));
1642
25ad93fd 1643 mutex_unlock(&dev_priv->fbc.lock);
36623ef8
PZ		 1644 intel_runtime_pm_put(dev_priv);
1645
b5e50c3f
JB		 1646 return 0;
1647}
1648
da46f936
RV		 1649static int i915_fbc_fc_get(void *data, u64 *val)
1650{
1651 struct drm_device *dev = data;
1652 struct drm_i915_private *dev_priv = dev->dev_private;
1653
1654 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1655 return -ENODEV;
1656
da46f936 1657 *val = dev_priv->fbc.false_color;
da46f936
RV		 1658
1659 return 0;
1660}
1661
1662static int i915_fbc_fc_set(void *data, u64 val)
1663{
1664 struct drm_device *dev = data;
1665 struct drm_i915_private *dev_priv = dev->dev_private;
1666 u32 reg;
1667
1668 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1669 return -ENODEV;
1670
25ad93fd 1671 mutex_lock(&dev_priv->fbc.lock);
da46f936
RV		 1672
1673 reg = I915_READ(ILK_DPFC_CONTROL);
1674 dev_priv->fbc.false_color = val;
1675
1676 I915_WRITE(ILK_DPFC_CONTROL, val ?
1677 (reg | FBC_CTL_FALSE_COLOR) :
1678 (reg & ~FBC_CTL_FALSE_COLOR));
1679
25ad93fd 1680 mutex_unlock(&dev_priv->fbc.lock);
da46f936
RV		 1681 return 0;
1682}
1683
1684DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops,
1685 i915_fbc_fc_get, i915_fbc_fc_set,
1686 "%llu\n");
1687
92d44621
PZ		 1688static int i915_ips_status(struct seq_file *m, void *unused)
1689{
9f25d007 1690 struct drm_info_node *node = m->private;
92d44621
PZ		 1691 struct drm_device *dev = node->minor->dev;
1692 struct drm_i915_private *dev_priv = dev->dev_private;
1693
f5adf94e 1694 if (!HAS_IPS(dev)) {
92d44621
PZ		 1695 seq_puts(m, "not supported\n");
1696 return 0;
1697 }
1698
36623ef8
PZ		 1699 intel_runtime_pm_get(dev_priv);
1700
0eaa53f0
RV		 1701 seq_printf(m, "Enabled by kernel parameter: %s\n",
1702 yesno(i915.enable_ips));
1703
1704 if (INTEL_INFO(dev)->gen >= 8) {
1705 seq_puts(m, "Currently: unknown\n");
1706 } else {
1707 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1708 seq_puts(m, "Currently: enabled\n");
1709 else
1710 seq_puts(m, "Currently: disabled\n");
1711 }
92d44621 1712
36623ef8
PZ		 1713 intel_runtime_pm_put(dev_priv);
1714
92d44621
PZ		 1715 return 0;
1716}
1717
4a9bef37
JB		 1718static int i915_sr_status(struct seq_file *m, void *unused)
1719{
9f25d007 1720 struct drm_info_node *node = m->private;
4a9bef37 1721 struct drm_device *dev = node->minor->dev;
e277a1f8 1722 struct drm_i915_private *dev_priv = dev->dev_private;
4a9bef37
JB		 1723 bool sr_enabled = false;
1724
36623ef8
PZ		 1725 intel_runtime_pm_get(dev_priv);
1726
1398261a 1727 if (HAS_PCH_SPLIT(dev))
5ba2aaaa 1728 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
77b64555
ACO		 1729 else if (IS_CRESTLINE(dev) || IS_G4X(dev) ||
1730 IS_I945G(dev) || IS_I945GM(dev))
4a9bef37
JB		 1731 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1732 else if (IS_I915GM(dev))
1733 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1734 else if (IS_PINEVIEW(dev))
1735 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
77b64555
ACO		 1736 else if (IS_VALLEYVIEW(dev))
1737 sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
4a9bef37 1738
36623ef8
PZ		 1739 intel_runtime_pm_put(dev_priv);
1740
5ba2aaaa
CW		 1741 seq_printf(m, "self-refresh: %s\n",
1742 sr_enabled ? "enabled" : "disabled");
4a9bef37
JB		 1743
1744 return 0;
1745}
1746
7648fa99
JB		 1747static int i915_emon_status(struct seq_file *m, void *unused)
1748{
9f25d007 1749 struct drm_info_node *node = m->private;
7648fa99 1750 struct drm_device *dev = node->minor->dev;
e277a1f8 1751 struct drm_i915_private *dev_priv = dev->dev_private;
7648fa99 1752 unsigned long temp, chipset, gfx;
de227ef0
CW		 1753 int ret;
1754
582be6b4
CW		 1755 if (!IS_GEN5(dev))
1756 return -ENODEV;
1757
de227ef0
CW		 1758 ret = mutex_lock_interruptible(&dev->struct_mutex);
1759 if (ret)
1760 return ret;
7648fa99
JB		 1761
1762 temp = i915_mch_val(dev_priv);
1763 chipset = i915_chipset_val(dev_priv);
1764 gfx = i915_gfx_val(dev_priv);
de227ef0 1765 mutex_unlock(&dev->struct_mutex);
7648fa99
JB		 1766
1767 seq_printf(m, "GMCH temp: %ld\n", temp);
1768 seq_printf(m, "Chipset power: %ld\n", chipset);
1769 seq_printf(m, "GFX power: %ld\n", gfx);
1770 seq_printf(m, "Total power: %ld\n", chipset + gfx);
1771
1772 return 0;
1773}
1774
23b2f8bb
JB		 1775static int i915_ring_freq_table(struct seq_file *m, void *unused)
1776{
9f25d007 1777 struct drm_info_node *node = m->private;
23b2f8bb 1778 struct drm_device *dev = node->minor->dev;
e277a1f8 1779 struct drm_i915_private *dev_priv = dev->dev_private;
5bfa0199 1780 int ret = 0;
23b2f8bb 1781 int gpu_freq, ia_freq;
f936ec34 1782 unsigned int max_gpu_freq, min_gpu_freq;
23b2f8bb 1783
97d3308a 1784 if (!HAS_CORE_RING_FREQ(dev)) {
267f0c90 1785 seq_puts(m, "unsupported on this chipset\n");
23b2f8bb
JB		 1786 return 0;
1787 }
1788
5bfa0199
PZ		 1789 intel_runtime_pm_get(dev_priv);
1790
5c9669ce
TR		 1791 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1792
4fc688ce 1793 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
23b2f8bb 1794 if (ret)
5bfa0199 1795 goto out;
23b2f8bb 1796
f936ec34
AG		 1797 if (IS_SKYLAKE(dev)) {
1798 /* Convert GT frequency to 50 HZ units */
1799 min_gpu_freq =
1800 dev_priv->rps.min_freq_softlimit / GEN9_FREQ_SCALER;
1801 max_gpu_freq =
1802 dev_priv->rps.max_freq_softlimit / GEN9_FREQ_SCALER;
1803 } else {
1804 min_gpu_freq = dev_priv->rps.min_freq_softlimit;
1805 max_gpu_freq = dev_priv->rps.max_freq_softlimit;
1806 }
1807
267f0c90 1808 seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
23b2f8bb 1809
f936ec34 1810 for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
42c0526c
BW		 1811 ia_freq = gpu_freq;
1812 sandybridge_pcode_read(dev_priv,
1813 GEN6_PCODE_READ_MIN_FREQ_TABLE,
1814 &ia_freq);
3ebecd07 1815 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
f936ec34
AG		 1816 intel_gpu_freq(dev_priv, (gpu_freq *
1817 (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1))),
3ebecd07
CW		 1818 ((ia_freq >> 0) & 0xff) * 100,
1819 ((ia_freq >> 8) & 0xff) * 100);
23b2f8bb
JB		 1820 }
1821
4fc688ce 1822 mutex_unlock(&dev_priv->rps.hw_lock);
23b2f8bb 1823
5bfa0199
PZ		 1824out:
1825 intel_runtime_pm_put(dev_priv);
1826 return ret;
23b2f8bb
JB		 1827}
1828
44834a67
CW		 1829static int i915_opregion(struct seq_file *m, void *unused)
1830{
9f25d007 1831 struct drm_info_node *node = m->private;
44834a67 1832 struct drm_device *dev = node->minor->dev;
e277a1f8 1833 struct drm_i915_private *dev_priv = dev->dev_private;
44834a67 1834 struct intel_opregion *opregion = &dev_priv->opregion;
0d38f009 1835 void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL);
44834a67
CW		 1836 int ret;
1837
0d38f009
DV		 1838 if (data == NULL)
1839 return -ENOMEM;
1840
44834a67
CW		 1841 ret = mutex_lock_interruptible(&dev->struct_mutex);
1842 if (ret)
0d38f009 1843 goto out;
44834a67 1844
0d38f009
DV		 1845 if (opregion->header) {
1846 memcpy_fromio(data, opregion->header, OPREGION_SIZE);
1847 seq_write(m, data, OPREGION_SIZE);
1848 }
44834a67
CW		 1849
1850 mutex_unlock(&dev->struct_mutex);
1851
0d38f009
DV		 1852out:
1853 kfree(data);
44834a67
CW		 1854 return 0;
1855}
1856
37811fcc
CW		 1857static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1858{
9f25d007 1859 struct drm_info_node *node = m->private;
37811fcc 1860 struct drm_device *dev = node->minor->dev;
4520f53a 1861 struct intel_fbdev *ifbdev = NULL;
37811fcc 1862 struct intel_framebuffer *fb;
3a58ee10 1863 struct drm_framebuffer *drm_fb;
37811fcc 1864
0695726e 1865#ifdef CONFIG_DRM_FBDEV_EMULATION
4520f53a 1866 struct drm_i915_private *dev_priv = dev->dev_private;
37811fcc
CW		 1867
1868 ifbdev = dev_priv->fbdev;
1869 fb = to_intel_framebuffer(ifbdev->helper.fb);
1870
c1ca506d 1871 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
37811fcc
CW		 1872 fb->base.width,
1873 fb->base.height,
1874 fb->base.depth,
623f9783 1875 fb->base.bits_per_pixel,
c1ca506d 1876 fb->base.modifier[0],
623f9783 1877 atomic_read(&fb->base.refcount.refcount));
05394f39 1878 describe_obj(m, fb->obj);
267f0c90 1879 seq_putc(m, '\n');
4520f53a 1880#endif
37811fcc 1881
4b096ac1 1882 mutex_lock(&dev->mode_config.fb_lock);
3a58ee10
DV		 1883 drm_for_each_fb(drm_fb, dev) {
1884 fb = to_intel_framebuffer(drm_fb);
131a56dc 1885 if (ifbdev && &fb->base == ifbdev->helper.fb)
37811fcc
CW		 1886 continue;
1887
c1ca506d 1888 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
37811fcc
CW		 1889 fb->base.width,
1890 fb->base.height,
1891 fb->base.depth,
623f9783 1892 fb->base.bits_per_pixel,
c1ca506d 1893 fb->base.modifier[0],
623f9783 1894 atomic_read(&fb->base.refcount.refcount));
05394f39 1895 describe_obj(m, fb->obj);
267f0c90 1896 seq_putc(m, '\n');
37811fcc 1897 }
4b096ac1 1898 mutex_unlock(&dev->mode_config.fb_lock);
37811fcc
CW		 1899
1900 return 0;
1901}
1902
c9fe99bd
OM		 1903static void describe_ctx_ringbuf(struct seq_file *m,
1904 struct intel_ringbuffer *ringbuf)
1905{
1906 seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
1907 ringbuf->space, ringbuf->head, ringbuf->tail,
1908 ringbuf->last_retired_head);
1909}
1910
e76d3630
BW		 1911static int i915_context_status(struct seq_file *m, void *unused)
1912{
9f25d007 1913 struct drm_info_node *node = m->private;
e76d3630 1914 struct drm_device *dev = node->minor->dev;
e277a1f8 1915 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 1916 struct intel_engine_cs *ring;
273497e5 1917 struct intel_context *ctx;
a168c293 1918 int ret, i;
e76d3630 1919
f3d28878 1920 ret = mutex_lock_interruptible(&dev->struct_mutex);
e76d3630
BW		 1921 if (ret)
1922 return ret;
1923
a33afea5 1924 list_for_each_entry(ctx, &dev_priv->context_list, link) {
c9fe99bd
OM		 1925 if (!i915.enable_execlists &&
1926 ctx->legacy_hw_ctx.rcs_state == NULL)
b77f6997
CW		 1927 continue;
1928
a33afea5 1929 seq_puts(m, "HW context ");
3ccfd19d 1930 describe_ctx(m, ctx);
c9fe99bd 1931 for_each_ring(ring, dev_priv, i) {
a33afea5 1932 if (ring->default_context == ctx)
c9fe99bd
OM		 1933 seq_printf(m, "(default context %s) ",
1934 ring->name);
1935 }
1936
1937 if (i915.enable_execlists) {
1938 seq_putc(m, '\n');
1939 for_each_ring(ring, dev_priv, i) {
1940 struct drm_i915_gem_object *ctx_obj =
1941 ctx->engine[i].state;
1942 struct intel_ringbuffer *ringbuf =
1943 ctx->engine[i].ringbuf;
1944
1945 seq_printf(m, "%s: ", ring->name);
1946 if (ctx_obj)
1947 describe_obj(m, ctx_obj);
1948 if (ringbuf)
1949 describe_ctx_ringbuf(m, ringbuf);
1950 seq_putc(m, '\n');
1951 }
1952 } else {
1953 describe_obj(m, ctx->legacy_hw_ctx.rcs_state);
1954 }
a33afea5 1955
a33afea5 1956 seq_putc(m, '\n');
a168c293
BW		 1957 }
1958
f3d28878 1959 mutex_unlock(&dev->struct_mutex);
e76d3630
BW		 1960
1961 return 0;
1962}
1963
064ca1d2
TD		 1964static void i915_dump_lrc_obj(struct seq_file *m,
1965 struct intel_engine_cs *ring,
1966 struct drm_i915_gem_object *ctx_obj)
1967{
1968 struct page *page;
1969 uint32_t *reg_state;
1970 int j;
1971 unsigned long ggtt_offset = 0;
1972
1973 if (ctx_obj == NULL) {
1974 seq_printf(m, "Context on %s with no gem object\n",
1975 ring->name);
1976 return;
1977 }
1978
1979 seq_printf(m, "CONTEXT: %s %u\n", ring->name,
1980 intel_execlists_ctx_id(ctx_obj));
1981
1982 if (!i915_gem_obj_ggtt_bound(ctx_obj))
1983 seq_puts(m, "\tNot bound in GGTT\n");
1984 else
1985 ggtt_offset = i915_gem_obj_ggtt_offset(ctx_obj);
1986
1987 if (i915_gem_object_get_pages(ctx_obj)) {
1988 seq_puts(m, "\tFailed to get pages for context object\n");
1989 return;
1990 }
1991
d1675198 1992 page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN);
064ca1d2
TD		 1993 if (!WARN_ON(page == NULL)) {
1994 reg_state = kmap_atomic(page);
1995
1996 for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
1997 seq_printf(m, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n",
1998 ggtt_offset + 4096 + (j * 4),
1999 reg_state[j], reg_state[j + 1],
2000 reg_state[j + 2], reg_state[j + 3]);
2001 }
2002 kunmap_atomic(reg_state);
2003 }
2004
2005 seq_putc(m, '\n');
2006}
2007
c0ab1ae9
BW		 2008static int i915_dump_lrc(struct seq_file *m, void *unused)
2009{
2010 struct drm_info_node *node = (struct drm_info_node *) m->private;
2011 struct drm_device *dev = node->minor->dev;
2012 struct drm_i915_private *dev_priv = dev->dev_private;
2013 struct intel_engine_cs *ring;
2014 struct intel_context *ctx;
2015 int ret, i;
2016
2017 if (!i915.enable_execlists) {
2018 seq_printf(m, "Logical Ring Contexts are disabled\n");
2019 return 0;
2020 }
2021
2022 ret = mutex_lock_interruptible(&dev->struct_mutex);
2023 if (ret)
2024 return ret;
2025
2026 list_for_each_entry(ctx, &dev_priv->context_list, link) {
2027 for_each_ring(ring, dev_priv, i) {
064ca1d2
TD		 2028 if (ring->default_context != ctx)
2029 i915_dump_lrc_obj(m, ring,
2030 ctx->engine[i].state);
c0ab1ae9
BW		 2031 }
2032 }
2033
2034 mutex_unlock(&dev->struct_mutex);
2035
2036 return 0;
2037}
2038
4ba70e44
OM		 2039static int i915_execlists(struct seq_file *m, void *data)
2040{
2041 struct drm_info_node *node = (struct drm_info_node *)m->private;
2042 struct drm_device *dev = node->minor->dev;
2043 struct drm_i915_private *dev_priv = dev->dev_private;
2044 struct intel_engine_cs *ring;
2045 u32 status_pointer;
2046 u8 read_pointer;
2047 u8 write_pointer;
2048 u32 status;
2049 u32 ctx_id;
2050 struct list_head *cursor;
2051 int ring_id, i;
2052 int ret;
2053
2054 if (!i915.enable_execlists) {
2055 seq_puts(m, "Logical Ring Contexts are disabled\n");
2056 return 0;
2057 }
2058
2059 ret = mutex_lock_interruptible(&dev->struct_mutex);
2060 if (ret)
2061 return ret;
2062
fc0412ec
MT		 2063 intel_runtime_pm_get(dev_priv);
2064
4ba70e44 2065 for_each_ring(ring, dev_priv, ring_id) {
6d3d8274 2066 struct drm_i915_gem_request *head_req = NULL;
4ba70e44
OM		 2067 int count = 0;
2068 unsigned long flags;
2069
2070 seq_printf(m, "%s\n", ring->name);
2071
83843d84
VS		 2072 status = I915_READ(RING_EXECLIST_STATUS_LO(ring));
2073 ctx_id = I915_READ(RING_EXECLIST_STATUS_HI(ring));
4ba70e44
OM		 2074 seq_printf(m, "\tExeclist status: 0x%08X, context: %u\n",
2075 status, ctx_id);
2076
2077 status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(ring));
2078 seq_printf(m, "\tStatus pointer: 0x%08X\n", status_pointer);
2079
2080 read_pointer = ring->next_context_status_buffer;
2081 write_pointer = status_pointer & 0x07;
2082 if (read_pointer > write_pointer)
2083 write_pointer += 6;
2084 seq_printf(m, "\tRead pointer: 0x%08X, write pointer 0x%08X\n",
2085 read_pointer, write_pointer);
2086
2087 for (i = 0; i < 6; i++) {
83843d84
VS		 2088 status = I915_READ(RING_CONTEXT_STATUS_BUF_LO(ring, i));
2089 ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF_HI(ring, i));
4ba70e44
OM		 2090
2091 seq_printf(m, "\tStatus buffer %d: 0x%08X, context: %u\n",
2092 i, status, ctx_id);
2093 }
2094
2095 spin_lock_irqsave(&ring->execlist_lock, flags);
2096 list_for_each(cursor, &ring->execlist_queue)
2097 count++;
2098 head_req = list_first_entry_or_null(&ring->execlist_queue,
6d3d8274 2099 struct drm_i915_gem_request, execlist_link);
4ba70e44
OM		 2100 spin_unlock_irqrestore(&ring->execlist_lock, flags);
2101
2102 seq_printf(m, "\t%d requests in queue\n", count);
2103 if (head_req) {
2104 struct drm_i915_gem_object *ctx_obj;
2105
6d3d8274 2106 ctx_obj = head_req->ctx->engine[ring_id].state;
4ba70e44
OM		 2107 seq_printf(m, "\tHead request id: %u\n",
2108 intel_execlists_ctx_id(ctx_obj));
2109 seq_printf(m, "\tHead request tail: %u\n",
6d3d8274 2110 head_req->tail);
4ba70e44
OM		 2111 }
2112
2113 seq_putc(m, '\n');
2114 }
2115
fc0412ec 2116 intel_runtime_pm_put(dev_priv);
4ba70e44
OM		 2117 mutex_unlock(&dev->struct_mutex);
2118
2119 return 0;
2120}
2121
ea16a3cd
DV		 2122static const char *swizzle_string(unsigned swizzle)
2123{
aee56cff 2124 switch (swizzle) {
ea16a3cd
DV		 2125 case I915_BIT_6_SWIZZLE_NONE:
2126 return "none";
2127 case I915_BIT_6_SWIZZLE_9:
2128 return "bit9";
2129 case I915_BIT_6_SWIZZLE_9_10:
2130 return "bit9/bit10";
2131 case I915_BIT_6_SWIZZLE_9_11:
2132 return "bit9/bit11";
2133 case I915_BIT_6_SWIZZLE_9_10_11:
2134 return "bit9/bit10/bit11";
2135 case I915_BIT_6_SWIZZLE_9_17:
2136 return "bit9/bit17";
2137 case I915_BIT_6_SWIZZLE_9_10_17:
2138 return "bit9/bit10/bit17";
2139 case I915_BIT_6_SWIZZLE_UNKNOWN:
8a168ca7 2140 return "unknown";
ea16a3cd
DV		 2141 }
2142
2143 return "bug";
2144}
2145
2146static int i915_swizzle_info(struct seq_file *m, void *data)
2147{
9f25d007 2148 struct drm_info_node *node = m->private;
ea16a3cd
DV		 2149 struct drm_device *dev = node->minor->dev;
2150 struct drm_i915_private *dev_priv = dev->dev_private;
22bcfc6a
DV		 2151 int ret;
2152
2153 ret = mutex_lock_interruptible(&dev->struct_mutex);
2154 if (ret)
2155 return ret;
c8c8fb33 2156 intel_runtime_pm_get(dev_priv);
ea16a3cd 2157
ea16a3cd
DV		 2158 seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
2159 swizzle_string(dev_priv->mm.bit_6_swizzle_x));
2160 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
2161 swizzle_string(dev_priv->mm.bit_6_swizzle_y));
2162
2163 if (IS_GEN3(dev) || IS_GEN4(dev)) {
2164 seq_printf(m, "DDC = 0x%08x\n",
2165 I915_READ(DCC));
656bfa3a
DV		 2166 seq_printf(m, "DDC2 = 0x%08x\n",
2167 I915_READ(DCC2));
ea16a3cd
DV		 2168 seq_printf(m, "C0DRB3 = 0x%04x\n",
2169 I915_READ16(C0DRB3));
2170 seq_printf(m, "C1DRB3 = 0x%04x\n",
2171 I915_READ16(C1DRB3));
9d3203e1 2172 } else if (INTEL_INFO(dev)->gen >= 6) {
3fa7d235
DV		 2173 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
2174 I915_READ(MAD_DIMM_C0));
2175 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
2176 I915_READ(MAD_DIMM_C1));
2177 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
2178 I915_READ(MAD_DIMM_C2));
2179 seq_printf(m, "TILECTL = 0x%08x\n",
2180 I915_READ(TILECTL));
5907f5fb 2181 if (INTEL_INFO(dev)->gen >= 8)
9d3203e1
BW		 2182 seq_printf(m, "GAMTARBMODE = 0x%08x\n",
2183 I915_READ(GAMTARBMODE));
2184 else
2185 seq_printf(m, "ARB_MODE = 0x%08x\n",
2186 I915_READ(ARB_MODE));
3fa7d235
DV		 2187 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
2188 I915_READ(DISP_ARB_CTL));
ea16a3cd 2189 }
656bfa3a
DV		 2190
2191 if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2192 seq_puts(m, "L-shaped memory detected\n");
2193
c8c8fb33 2194 intel_runtime_pm_put(dev_priv);
ea16a3cd
DV		 2195 mutex_unlock(&dev->struct_mutex);
2196
2197 return 0;
2198}
2199
1c60fef5
BW		 2200static int per_file_ctx(int id, void *ptr, void *data)
2201{
273497e5 2202 struct intel_context *ctx = ptr;
1c60fef5 2203 struct seq_file *m = data;
ae6c4806
DV		 2204 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2205
2206 if (!ppgtt) {
2207 seq_printf(m, " no ppgtt for context %d\n",
2208 ctx->user_handle);
2209 return 0;
2210 }
1c60fef5 2211
f83d6518
OM		 2212 if (i915_gem_context_is_default(ctx))
2213 seq_puts(m, " default context:\n");
2214 else
821d66dd 2215 seq_printf(m, " context %d:\n", ctx->user_handle);
1c60fef5
BW		 2216 ppgtt->debug_dump(ppgtt, m);
2217
2218 return 0;
2219}
2220
77df6772 2221static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev)
3cf17fc5 2222{
3cf17fc5 2223 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2224 struct intel_engine_cs *ring;
77df6772
BW		 2225 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2226 int unused, i;
3cf17fc5 2227
77df6772
BW		 2228 if (!ppgtt)
2229 return;
2230
77df6772
BW		 2231 for_each_ring(ring, dev_priv, unused) {
2232 seq_printf(m, "%s\n", ring->name);
2233 for (i = 0; i < 4; i++) {
d3a93cbe 2234 u64 pdp = I915_READ(GEN8_RING_PDP_UDW(ring, i));
77df6772 2235 pdp <<= 32;
d3a93cbe 2236 pdp |= I915_READ(GEN8_RING_PDP_LDW(ring, i));
a2a5b15c 2237 seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
77df6772
BW		 2238 }
2239 }
2240}
2241
2242static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2243{
2244 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2245 struct intel_engine_cs *ring;
77df6772 2246 int i;
3cf17fc5 2247
3cf17fc5
DV		 2248 if (INTEL_INFO(dev)->gen == 6)
2249 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
2250
a2c7f6fd 2251 for_each_ring(ring, dev_priv, i) {
3cf17fc5
DV		 2252 seq_printf(m, "%s\n", ring->name);
2253 if (INTEL_INFO(dev)->gen == 7)
2254 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
2255 seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
2256 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
2257 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring)));
2258 }
2259 if (dev_priv->mm.aliasing_ppgtt) {
2260 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2261
267f0c90 2262 seq_puts(m, "aliasing PPGTT:\n");
44159ddb 2263 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.base.ggtt_offset);
1c60fef5 2264
87d60b63 2265 ppgtt->debug_dump(ppgtt, m);
ae6c4806 2266 }
1c60fef5 2267
3cf17fc5 2268 seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
77df6772
BW		 2269}
2270
2271static int i915_ppgtt_info(struct seq_file *m, void *data)
2272{
9f25d007 2273 struct drm_info_node *node = m->private;
77df6772 2274 struct drm_device *dev = node->minor->dev;
c8c8fb33 2275 struct drm_i915_private *dev_priv = dev->dev_private;
ea91e401 2276 struct drm_file *file;
77df6772
BW		 2277
2278 int ret = mutex_lock_interruptible(&dev->struct_mutex);
2279 if (ret)
2280 return ret;
c8c8fb33 2281 intel_runtime_pm_get(dev_priv);
77df6772
BW		 2282
2283 if (INTEL_INFO(dev)->gen >= 8)
2284 gen8_ppgtt_info(m, dev);
2285 else if (INTEL_INFO(dev)->gen >= 6)
2286 gen6_ppgtt_info(m, dev);
2287
ea91e401
MT		 2288 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2289 struct drm_i915_file_private *file_priv = file->driver_priv;
7cb5dff8 2290 struct task_struct *task;
ea91e401 2291
7cb5dff8
GT		 2292 task = get_pid_task(file->pid, PIDTYPE_PID);
2293 if (!task)
2294 return -ESRCH;
2295 seq_printf(m, "\nproc: %s\n", task->comm);
2296 put_task_struct(task);
ea91e401
MT		 2297 idr_for_each(&file_priv->context_idr, per_file_ctx,
2298 (void *)(unsigned long)m);
2299 }
2300
c8c8fb33 2301 intel_runtime_pm_put(dev_priv);
3cf17fc5
DV		 2302 mutex_unlock(&dev->struct_mutex);
2303
2304 return 0;
2305}
2306
f5a4c67d
CW		 2307static int count_irq_waiters(struct drm_i915_private *i915)
2308{
2309 struct intel_engine_cs *ring;
2310 int count = 0;
2311 int i;
2312
2313 for_each_ring(ring, i915, i)
2314 count += ring->irq_refcount;
2315
2316 return count;
2317}
2318
1854d5ca
CW		 2319static int i915_rps_boost_info(struct seq_file *m, void *data)
2320{
2321 struct drm_info_node *node = m->private;
2322 struct drm_device *dev = node->minor->dev;
2323 struct drm_i915_private *dev_priv = dev->dev_private;
2324 struct drm_file *file;
1854d5ca 2325
f5a4c67d
CW		 2326 seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled);
2327 seq_printf(m, "GPU busy? %d\n", dev_priv->mm.busy);
2328 seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv));
2329 seq_printf(m, "Frequency requested %d; min hard:%d, soft:%d; max soft:%d, hard:%d\n",
2330 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
2331 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2332 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit),
2333 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit),
2334 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
8d3afd7d 2335 spin_lock(&dev_priv->rps.client_lock);
1854d5ca
CW		 2336 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2337 struct drm_i915_file_private *file_priv = file->driver_priv;
2338 struct task_struct *task;
2339
2340 rcu_read_lock();
2341 task = pid_task(file->pid, PIDTYPE_PID);
2342 seq_printf(m, "%s [%d]: %d boosts%s\n",
2343 task ? task->comm : "<unknown>",
2344 task ? task->pid : -1,
2e1b8730
CW		 2345 file_priv->rps.boosts,
2346 list_empty(&file_priv->rps.link) ? "" : ", active");
1854d5ca
CW		 2347 rcu_read_unlock();
2348 }
2e1b8730
CW		 2349 seq_printf(m, "Semaphore boosts: %d%s\n",
2350 dev_priv->rps.semaphores.boosts,
2351 list_empty(&dev_priv->rps.semaphores.link) ? "" : ", active");
2352 seq_printf(m, "MMIO flip boosts: %d%s\n",
2353 dev_priv->rps.mmioflips.boosts,
2354 list_empty(&dev_priv->rps.mmioflips.link) ? "" : ", active");
1854d5ca 2355 seq_printf(m, "Kernel boosts: %d\n", dev_priv->rps.boosts);
8d3afd7d 2356 spin_unlock(&dev_priv->rps.client_lock);
1854d5ca 2357
8d3afd7d 2358 return 0;
1854d5ca
CW		 2359}
2360
63573eb7
BW		 2361static int i915_llc(struct seq_file *m, void *data)
2362{
9f25d007 2363 struct drm_info_node *node = m->private;
63573eb7
BW		 2364 struct drm_device *dev = node->minor->dev;
2365 struct drm_i915_private *dev_priv = dev->dev_private;
2366
2367 /* Size calculation for LLC is a bit of a pain. Ignore for now. */
2368 seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
2369 seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size);
2370
2371 return 0;
2372}
2373
fdf5d357
AD		 2374static int i915_guc_load_status_info(struct seq_file *m, void *data)
2375{
2376 struct drm_info_node *node = m->private;
2377 struct drm_i915_private *dev_priv = node->minor->dev->dev_private;
2378 struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
2379 u32 tmp, i;
2380
2381 if (!HAS_GUC_UCODE(dev_priv->dev))
2382 return 0;
2383
2384 seq_printf(m, "GuC firmware status:\n");
2385 seq_printf(m, "\tpath: %s\n",
2386 guc_fw->guc_fw_path);
2387 seq_printf(m, "\tfetch: %s\n",
2388 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
2389 seq_printf(m, "\tload: %s\n",
2390 intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
2391 seq_printf(m, "\tversion wanted: %d.%d\n",
2392 guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
2393 seq_printf(m, "\tversion found: %d.%d\n",
2394 guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found);
2395
2396 tmp = I915_READ(GUC_STATUS);
2397
2398 seq_printf(m, "\nGuC status 0x%08x:\n", tmp);
2399 seq_printf(m, "\tBootrom status = 0x%x\n",
2400 (tmp & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT);
2401 seq_printf(m, "\tuKernel status = 0x%x\n",
2402 (tmp & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT);
2403 seq_printf(m, "\tMIA Core status = 0x%x\n",
2404 (tmp & GS_MIA_MASK) >> GS_MIA_SHIFT);
2405 seq_puts(m, "\nScratch registers:\n");
2406 for (i = 0; i < 16; i++)
2407 seq_printf(m, "\t%2d: \t0x%x\n", i, I915_READ(SOFT_SCRATCH(i)));
2408
2409 return 0;
2410}
2411
8b417c26
DG		 2412static void i915_guc_client_info(struct seq_file *m,
2413 struct drm_i915_private *dev_priv,
2414 struct i915_guc_client *client)
2415{
2416 struct intel_engine_cs *ring;
2417 uint64_t tot = 0;
2418 uint32_t i;
2419
2420 seq_printf(m, "\tPriority %d, GuC ctx index: %u, PD offset 0x%x\n",
2421 client->priority, client->ctx_index, client->proc_desc_offset);
2422 seq_printf(m, "\tDoorbell id %d, offset: 0x%x, cookie 0x%x\n",
2423 client->doorbell_id, client->doorbell_offset, client->cookie);
2424 seq_printf(m, "\tWQ size %d, offset: 0x%x, tail %d\n",
2425 client->wq_size, client->wq_offset, client->wq_tail);
2426
2427 seq_printf(m, "\tFailed to queue: %u\n", client->q_fail);
2428 seq_printf(m, "\tFailed doorbell: %u\n", client->b_fail);
2429 seq_printf(m, "\tLast submission result: %d\n", client->retcode);
2430
2431 for_each_ring(ring, dev_priv, i) {
2432 seq_printf(m, "\tSubmissions: %llu %s\n",
2433 client->submissions[i],
2434 ring->name);
2435 tot += client->submissions[i];
2436 }
2437 seq_printf(m, "\tTotal: %llu\n", tot);
2438}
2439
2440static int i915_guc_info(struct seq_file *m, void *data)
2441{
2442 struct drm_info_node *node = m->private;
2443 struct drm_device *dev = node->minor->dev;
2444 struct drm_i915_private *dev_priv = dev->dev_private;
2445 struct intel_guc guc;
0a0b457f 2446 struct i915_guc_client client = {};
8b417c26
DG		 2447 struct intel_engine_cs *ring;
2448 enum intel_ring_id i;
2449 u64 total = 0;
2450
2451 if (!HAS_GUC_SCHED(dev_priv->dev))
2452 return 0;
2453
2454 /* Take a local copy of the GuC data, so we can dump it at leisure */
2455 spin_lock(&dev_priv->guc.host2guc_lock);
2456 guc = dev_priv->guc;
2457 if (guc.execbuf_client) {
2458 spin_lock(&guc.execbuf_client->wq_lock);
2459 client = *guc.execbuf_client;
2460 spin_unlock(&guc.execbuf_client->wq_lock);
2461 }
2462 spin_unlock(&dev_priv->guc.host2guc_lock);
2463
2464 seq_printf(m, "GuC total action count: %llu\n", guc.action_count);
2465 seq_printf(m, "GuC action failure count: %u\n", guc.action_fail);
2466 seq_printf(m, "GuC last action command: 0x%x\n", guc.action_cmd);
2467 seq_printf(m, "GuC last action status: 0x%x\n", guc.action_status);
2468 seq_printf(m, "GuC last action error code: %d\n", guc.action_err);
2469
2470 seq_printf(m, "\nGuC submissions:\n");
2471 for_each_ring(ring, dev_priv, i) {
2472 seq_printf(m, "\t%-24s: %10llu, last seqno 0x%08x %9d\n",
2473 ring->name, guc.submissions[i],
2474 guc.last_seqno[i], guc.last_seqno[i]);
2475 total += guc.submissions[i];
2476 }
2477 seq_printf(m, "\t%s: %llu\n", "Total", total);
2478
2479 seq_printf(m, "\nGuC execbuf client @ %p:\n", guc.execbuf_client);
2480 i915_guc_client_info(m, dev_priv, &client);
2481
2482 /* Add more as required ... */
2483
2484 return 0;
2485}
2486
4c7e77fc
AD		 2487static int i915_guc_log_dump(struct seq_file *m, void *data)
2488{
2489 struct drm_info_node *node = m->private;
2490 struct drm_device *dev = node->minor->dev;
2491 struct drm_i915_private *dev_priv = dev->dev_private;
2492 struct drm_i915_gem_object *log_obj = dev_priv->guc.log_obj;
2493 u32 *log;
2494 int i = 0, pg;
2495
2496 if (!log_obj)
2497 return 0;
2498
2499 for (pg = 0; pg < log_obj->base.size / PAGE_SIZE; pg++) {
2500 log = kmap_atomic(i915_gem_object_get_page(log_obj, pg));
2501
2502 for (i = 0; i < PAGE_SIZE / sizeof(u32); i += 4)
2503 seq_printf(m, "0x%08x 0x%08x 0x%08x 0x%08x\n",
2504 *(log + i), *(log + i + 1),
2505 *(log + i + 2), *(log + i + 3));
2506
2507 kunmap_atomic(log);
2508 }
2509
2510 seq_putc(m, '\n');
2511
2512 return 0;
2513}
2514
e91fd8c6
RV		 2515static int i915_edp_psr_status(struct seq_file *m, void *data)
2516{
2517 struct drm_info_node *node = m->private;
2518 struct drm_device *dev = node->minor->dev;
2519 struct drm_i915_private *dev_priv = dev->dev_private;
a031d709 2520 u32 psrperf = 0;
a6cbdb8e
RV		 2521 u32 stat[3];
2522 enum pipe pipe;
a031d709 2523 bool enabled = false;
e91fd8c6 2524
3553a8ea
DL		 2525 if (!HAS_PSR(dev)) {
2526 seq_puts(m, "PSR not supported\n");
2527 return 0;
2528 }
2529
c8c8fb33
PZ		 2530 intel_runtime_pm_get(dev_priv);
2531
fa128fa6 2532 mutex_lock(&dev_priv->psr.lock);
a031d709
RV		 2533 seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
2534 seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
2807cf69 2535 seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
5755c78f 2536 seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
fa128fa6
DV		 2537 seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
2538 dev_priv->psr.busy_frontbuffer_bits);
2539 seq_printf(m, "Re-enable work scheduled: %s\n",
2540 yesno(work_busy(&dev_priv->psr.work.work)));
e91fd8c6 2541
3553a8ea
DL		 2542 if (HAS_DDI(dev))
2543 enabled = I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
2544 else {
2545 for_each_pipe(dev_priv, pipe) {
2546 stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
2547 VLV_EDP_PSR_CURR_STATE_MASK;
2548 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2549 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2550 enabled = true;
a6cbdb8e
RV		 2551 }
2552 }
2553 seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));
2554
2555 if (!HAS_DDI(dev))
2556 for_each_pipe(dev_priv, pipe) {
2557 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2558 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2559 seq_printf(m, " pipe %c", pipe_name(pipe));
2560 }
2561 seq_puts(m, "\n");
e91fd8c6 2562
a6cbdb8e 2563 /* CHV PSR has no kind of performance counter */
3553a8ea 2564 if (HAS_DDI(dev)) {
a031d709
RV		 2565 psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) &
2566 EDP_PSR_PERF_CNT_MASK;
a6cbdb8e
RV		 2567
2568 seq_printf(m, "Performance_Counter: %u\n", psrperf);
2569 }
fa128fa6 2570 mutex_unlock(&dev_priv->psr.lock);
e91fd8c6 2571
c8c8fb33 2572 intel_runtime_pm_put(dev_priv);
e91fd8c6
RV		 2573 return 0;
2574}
2575
d2e216d0
RV		 2576static int i915_sink_crc(struct seq_file *m, void *data)
2577{
2578 struct drm_info_node *node = m->private;
2579 struct drm_device *dev = node->minor->dev;
2580 struct intel_encoder *encoder;
2581 struct intel_connector *connector;
2582 struct intel_dp *intel_dp = NULL;
2583 int ret;
2584 u8 crc[6];
2585
2586 drm_modeset_lock_all(dev);
aca5e361 2587 for_each_intel_connector(dev, connector) {
d2e216d0
RV		 2588
2589 if (connector->base.dpms != DRM_MODE_DPMS_ON)
2590 continue;
2591
b6ae3c7c
PZ		 2592 if (!connector->base.encoder)
2593 continue;
2594
d2e216d0
RV		 2595 encoder = to_intel_encoder(connector->base.encoder);
2596 if (encoder->type != INTEL_OUTPUT_EDP)
2597 continue;
2598
2599 intel_dp = enc_to_intel_dp(&encoder->base);
2600
2601 ret = intel_dp_sink_crc(intel_dp, crc);
2602 if (ret)
2603 goto out;
2604
2605 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2606 crc[0], crc[1], crc[2],
2607 crc[3], crc[4], crc[5]);
2608 goto out;
2609 }
2610 ret = -ENODEV;
2611out:
2612 drm_modeset_unlock_all(dev);
2613 return ret;
2614}
2615
ec013e7f
JB		 2616static int i915_energy_uJ(struct seq_file *m, void *data)
2617{
2618 struct drm_info_node *node = m->private;
2619 struct drm_device *dev = node->minor->dev;
2620 struct drm_i915_private *dev_priv = dev->dev_private;
2621 u64 power;
2622 u32 units;
2623
2624 if (INTEL_INFO(dev)->gen < 6)
2625 return -ENODEV;
2626
36623ef8
PZ		 2627 intel_runtime_pm_get(dev_priv);
2628
ec013e7f
JB		 2629 rdmsrl(MSR_RAPL_POWER_UNIT, power);
2630 power = (power & 0x1f00) >> 8;
2631 units = 1000000 / (1 << power); /* convert to uJ */
2632 power = I915_READ(MCH_SECP_NRG_STTS);
2633 power *= units;
2634
36623ef8
PZ		 2635 intel_runtime_pm_put(dev_priv);
2636
ec013e7f 2637 seq_printf(m, "%llu", (long long unsigned)power);
371db66a
PZ		 2638
2639 return 0;
2640}
2641
6455c870 2642static int i915_runtime_pm_status(struct seq_file *m, void *unused)
371db66a 2643{
9f25d007 2644 struct drm_info_node *node = m->private;
371db66a
PZ		 2645 struct drm_device *dev = node->minor->dev;
2646 struct drm_i915_private *dev_priv = dev->dev_private;
2647
6455c870 2648 if (!HAS_RUNTIME_PM(dev)) {
371db66a
PZ		 2649 seq_puts(m, "not supported\n");
2650 return 0;
2651 }
2652
86c4ec0d 2653 seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy));
371db66a 2654 seq_printf(m, "IRQs disabled: %s\n",
9df7575f 2655 yesno(!intel_irqs_enabled(dev_priv)));
0d804184 2656#ifdef CONFIG_PM
a6aaec8b
DL		 2657 seq_printf(m, "Usage count: %d\n",
2658 atomic_read(&dev->dev->power.usage_count));
0d804184
CW		 2659#else
2660 seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n");
2661#endif
371db66a 2662
ec013e7f
JB		 2663 return 0;
2664}
2665
1da51581
ID		 2666static const char *power_domain_str(enum intel_display_power_domain domain)
2667{
2668 switch (domain) {
2669 case POWER_DOMAIN_PIPE_A:
2670 return "PIPE_A";
2671 case POWER_DOMAIN_PIPE_B:
2672 return "PIPE_B";
2673 case POWER_DOMAIN_PIPE_C:
2674 return "PIPE_C";
2675 case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
2676 return "PIPE_A_PANEL_FITTER";
2677 case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
2678 return "PIPE_B_PANEL_FITTER";
2679 case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
2680 return "PIPE_C_PANEL_FITTER";
2681 case POWER_DOMAIN_TRANSCODER_A:
2682 return "TRANSCODER_A";
2683 case POWER_DOMAIN_TRANSCODER_B:
2684 return "TRANSCODER_B";
2685 case POWER_DOMAIN_TRANSCODER_C:
2686 return "TRANSCODER_C";
2687 case POWER_DOMAIN_TRANSCODER_EDP:
2688 return "TRANSCODER_EDP";
319be8ae
ID		 2689 case POWER_DOMAIN_PORT_DDI_A_2_LANES:
2690 return "PORT_DDI_A_2_LANES";
2691 case POWER_DOMAIN_PORT_DDI_A_4_LANES:
2692 return "PORT_DDI_A_4_LANES";
2693 case POWER_DOMAIN_PORT_DDI_B_2_LANES:
2694 return "PORT_DDI_B_2_LANES";
2695 case POWER_DOMAIN_PORT_DDI_B_4_LANES:
2696 return "PORT_DDI_B_4_LANES";
2697 case POWER_DOMAIN_PORT_DDI_C_2_LANES:
2698 return "PORT_DDI_C_2_LANES";
2699 case POWER_DOMAIN_PORT_DDI_C_4_LANES:
2700 return "PORT_DDI_C_4_LANES";
2701 case POWER_DOMAIN_PORT_DDI_D_2_LANES:
2702 return "PORT_DDI_D_2_LANES";
2703 case POWER_DOMAIN_PORT_DDI_D_4_LANES:
2704 return "PORT_DDI_D_4_LANES";
d8e19f99
XZ		 2705 case POWER_DOMAIN_PORT_DDI_E_2_LANES:
2706 return "PORT_DDI_E_2_LANES";
319be8ae
ID		 2707 case POWER_DOMAIN_PORT_DSI:
2708 return "PORT_DSI";
2709 case POWER_DOMAIN_PORT_CRT:
2710 return "PORT_CRT";
2711 case POWER_DOMAIN_PORT_OTHER:
2712 return "PORT_OTHER";
1da51581
ID		 2713 case POWER_DOMAIN_VGA:
2714 return "VGA";
2715 case POWER_DOMAIN_AUDIO:
2716 return "AUDIO";
bd2bb1b9
PZ		 2717 case POWER_DOMAIN_PLLS:
2718 return "PLLS";
1407121a
S		 2719 case POWER_DOMAIN_AUX_A:
2720 return "AUX_A";
2721 case POWER_DOMAIN_AUX_B:
2722 return "AUX_B";
2723 case POWER_DOMAIN_AUX_C:
2724 return "AUX_C";
2725 case POWER_DOMAIN_AUX_D:
2726 return "AUX_D";
1da51581
ID		 2727 case POWER_DOMAIN_INIT:
2728 return "INIT";
2729 default:
5f77eeb0 2730 MISSING_CASE(domain);
1da51581
ID		 2731 return "?";
2732 }
2733}
2734
2735static int i915_power_domain_info(struct seq_file *m, void *unused)
2736{
9f25d007 2737 struct drm_info_node *node = m->private;
1da51581
ID		 2738 struct drm_device *dev = node->minor->dev;
2739 struct drm_i915_private *dev_priv = dev->dev_private;
2740 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2741 int i;
2742
2743 mutex_lock(&power_domains->lock);
2744
2745 seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2746 for (i = 0; i < power_domains->power_well_count; i++) {
2747 struct i915_power_well *power_well;
2748 enum intel_display_power_domain power_domain;
2749
2750 power_well = &power_domains->power_wells[i];
2751 seq_printf(m, "%-25s %d\n", power_well->name,
2752 power_well->count);
2753
2754 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
2755 power_domain++) {
2756 if (!(BIT(power_domain) & power_well->domains))
2757 continue;
2758
2759 seq_printf(m, " %-23s %d\n",
2760 power_domain_str(power_domain),
2761 power_domains->domain_use_count[power_domain]);
2762 }
2763 }
2764
2765 mutex_unlock(&power_domains->lock);
2766
2767 return 0;
2768}
2769
53f5e3ca
JB		 2770static void intel_seq_print_mode(struct seq_file *m, int tabs,
2771 struct drm_display_mode *mode)
2772{
2773 int i;
2774
2775 for (i = 0; i < tabs; i++)
2776 seq_putc(m, '\t');
2777
2778 seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2779 mode->base.id, mode->name,
2780 mode->vrefresh, mode->clock,
2781 mode->hdisplay, mode->hsync_start,
2782 mode->hsync_end, mode->htotal,
2783 mode->vdisplay, mode->vsync_start,
2784 mode->vsync_end, mode->vtotal,
2785 mode->type, mode->flags);
2786}
2787
2788static void intel_encoder_info(struct seq_file *m,
2789 struct intel_crtc *intel_crtc,
2790 struct intel_encoder *intel_encoder)
2791{
9f25d007 2792 struct drm_info_node *node = m->private;
53f5e3ca
JB		 2793 struct drm_device *dev = node->minor->dev;
2794 struct drm_crtc *crtc = &intel_crtc->base;
2795 struct intel_connector *intel_connector;
2796 struct drm_encoder *encoder;
2797
2798 encoder = &intel_encoder->base;
2799 seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
8e329a03 2800 encoder->base.id, encoder->name);
53f5e3ca
JB		 2801 for_each_connector_on_encoder(dev, encoder, intel_connector) {
2802 struct drm_connector *connector = &intel_connector->base;
2803 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2804 connector->base.id,
c23cc417 2805 connector->name,
53f5e3ca
JB		 2806 drm_get_connector_status_name(connector->status));
2807 if (connector->status == connector_status_connected) {
2808 struct drm_display_mode *mode = &crtc->mode;
2809 seq_printf(m, ", mode:\n");
2810 intel_seq_print_mode(m, 2, mode);
2811 } else {
2812 seq_putc(m, '\n');
2813 }
2814 }
2815}
2816
2817static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2818{
9f25d007 2819 struct drm_info_node *node = m->private;
53f5e3ca
JB		 2820 struct drm_device *dev = node->minor->dev;
2821 struct drm_crtc *crtc = &intel_crtc->base;
2822 struct intel_encoder *intel_encoder;
23a48d53
ML		 2823 struct drm_plane_state *plane_state = crtc->primary->state;
2824 struct drm_framebuffer *fb = plane_state->fb;
53f5e3ca 2825
23a48d53 2826 if (fb)
5aa8a937 2827 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
23a48d53
ML		 2828 fb->base.id, plane_state->src_x >> 16,
2829 plane_state->src_y >> 16, fb->width, fb->height);
5aa8a937
MR		 2830 else
2831 seq_puts(m, "\tprimary plane disabled\n");
53f5e3ca
JB		 2832 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2833 intel_encoder_info(m, intel_crtc, intel_encoder);
2834}
2835
2836static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2837{
2838 struct drm_display_mode *mode = panel->fixed_mode;
2839
2840 seq_printf(m, "\tfixed mode:\n");
2841 intel_seq_print_mode(m, 2, mode);
2842}
2843
2844static void intel_dp_info(struct seq_file *m,
2845 struct intel_connector *intel_connector)
2846{
2847 struct intel_encoder *intel_encoder = intel_connector->encoder;
2848 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2849
2850 seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
742f491d 2851 seq_printf(m, "\taudio support: %s\n", yesno(intel_dp->has_audio));
53f5e3ca
JB		 2852 if (intel_encoder->type == INTEL_OUTPUT_EDP)
2853 intel_panel_info(m, &intel_connector->panel);
2854}
2855
2856static void intel_hdmi_info(struct seq_file *m,
2857 struct intel_connector *intel_connector)
2858{
2859 struct intel_encoder *intel_encoder = intel_connector->encoder;
2860 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2861
742f491d 2862 seq_printf(m, "\taudio support: %s\n", yesno(intel_hdmi->has_audio));
53f5e3ca
JB		 2863}
2864
2865static void intel_lvds_info(struct seq_file *m,
2866 struct intel_connector *intel_connector)
2867{
2868 intel_panel_info(m, &intel_connector->panel);
2869}
2870
2871static void intel_connector_info(struct seq_file *m,
2872 struct drm_connector *connector)
2873{
2874 struct intel_connector *intel_connector = to_intel_connector(connector);
2875 struct intel_encoder *intel_encoder = intel_connector->encoder;
f103fc7d 2876 struct drm_display_mode *mode;
53f5e3ca
JB		 2877
2878 seq_printf(m, "connector %d: type %s, status: %s\n",
c23cc417 2879 connector->base.id, connector->name,
53f5e3ca
JB		 2880 drm_get_connector_status_name(connector->status));
2881 if (connector->status == connector_status_connected) {
2882 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2883 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2884 connector->display_info.width_mm,
2885 connector->display_info.height_mm);
2886 seq_printf(m, "\tsubpixel order: %s\n",
2887 drm_get_subpixel_order_name(connector->display_info.subpixel_order));
2888 seq_printf(m, "\tCEA rev: %d\n",
2889 connector->display_info.cea_rev);
2890 }
36cd7444
DA		 2891 if (intel_encoder) {
2892 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2893 intel_encoder->type == INTEL_OUTPUT_EDP)
2894 intel_dp_info(m, intel_connector);
2895 else if (intel_encoder->type == INTEL_OUTPUT_HDMI)
2896 intel_hdmi_info(m, intel_connector);
2897 else if (intel_encoder->type == INTEL_OUTPUT_LVDS)
2898 intel_lvds_info(m, intel_connector);
2899 }
53f5e3ca 2900
f103fc7d
JB		 2901 seq_printf(m, "\tmodes:\n");
2902 list_for_each_entry(mode, &connector->modes, head)
2903 intel_seq_print_mode(m, 2, mode);
53f5e3ca
JB		 2904}
2905
065f2ec2
CW		 2906static bool cursor_active(struct drm_device *dev, int pipe)
2907{
2908 struct drm_i915_private *dev_priv = dev->dev_private;
2909 u32 state;
2910
2911 if (IS_845G(dev) || IS_I865G(dev))
2912 state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
065f2ec2 2913 else
5efb3e28 2914 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
065f2ec2
CW		 2915
2916 return state;
2917}
2918
2919static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y)
2920{
2921 struct drm_i915_private *dev_priv = dev->dev_private;
2922 u32 pos;
2923
5efb3e28 2924 pos = I915_READ(CURPOS(pipe));
065f2ec2
CW		 2925
2926 *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
2927 if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
2928 *x = -*x;
2929
2930 *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
2931 if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
2932 *y = -*y;
2933
2934 return cursor_active(dev, pipe);
2935}
2936
53f5e3ca
JB		 2937static int i915_display_info(struct seq_file *m, void *unused)
2938{
9f25d007 2939 struct drm_info_node *node = m->private;
53f5e3ca 2940 struct drm_device *dev = node->minor->dev;
b0e5ddf3 2941 struct drm_i915_private *dev_priv = dev->dev_private;
065f2ec2 2942 struct intel_crtc *crtc;
53f5e3ca
JB		 2943 struct drm_connector *connector;
2944
b0e5ddf3 2945 intel_runtime_pm_get(dev_priv);
53f5e3ca
JB		 2946 drm_modeset_lock_all(dev);
2947 seq_printf(m, "CRTC info\n");
2948 seq_printf(m, "---------\n");
d3fcc808 2949 for_each_intel_crtc(dev, crtc) {
065f2ec2 2950 bool active;
f77076c9 2951 struct intel_crtc_state *pipe_config;
065f2ec2 2952 int x, y;
53f5e3ca 2953
f77076c9
ML		 2954 pipe_config = to_intel_crtc_state(crtc->base.state);
2955
57127efa 2956 seq_printf(m, "CRTC %d: pipe: %c, active=%s (size=%dx%d)\n",
065f2ec2 2957 crtc->base.base.id, pipe_name(crtc->pipe),
f77076c9
ML		 2958 yesno(pipe_config->base.active),
2959 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
2960 if (pipe_config->base.active) {
065f2ec2
CW		 2961 intel_crtc_info(m, crtc);
2962
a23dc658 2963 active = cursor_position(dev, crtc->pipe, &x, &y);
57127efa 2964 seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
4b0e333e 2965 yesno(crtc->cursor_base),
3dd512fb
MR		 2966 x, y, crtc->base.cursor->state->crtc_w,
2967 crtc->base.cursor->state->crtc_h,
57127efa 2968 crtc->cursor_addr, yesno(active));
a23dc658 2969 }
cace841c
DV		 2970
2971 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
2972 yesno(!crtc->cpu_fifo_underrun_disabled),
2973 yesno(!crtc->pch_fifo_underrun_disabled));
53f5e3ca
JB		 2974 }
2975
2976 seq_printf(m, "\n");
2977 seq_printf(m, "Connector info\n");
2978 seq_printf(m, "--------------\n");
2979 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2980 intel_connector_info(m, connector);
2981 }
2982 drm_modeset_unlock_all(dev);
b0e5ddf3 2983 intel_runtime_pm_put(dev_priv);
53f5e3ca
JB		 2984
2985 return 0;
2986}
2987
e04934cf
BW		 2988static int i915_semaphore_status(struct seq_file *m, void *unused)
2989{
2990 struct drm_info_node *node = (struct drm_info_node *) m->private;
2991 struct drm_device *dev = node->minor->dev;
2992 struct drm_i915_private *dev_priv = dev->dev_private;
2993 struct intel_engine_cs *ring;
2994 int num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
2995 int i, j, ret;
2996
2997 if (!i915_semaphore_is_enabled(dev)) {
2998 seq_puts(m, "Semaphores are disabled\n");
2999 return 0;
3000 }
3001
3002 ret = mutex_lock_interruptible(&dev->struct_mutex);
3003 if (ret)
3004 return ret;
03872064 3005 intel_runtime_pm_get(dev_priv);
e04934cf
BW		 3006
3007 if (IS_BROADWELL(dev)) {
3008 struct page *page;
3009 uint64_t *seqno;
3010
3011 page = i915_gem_object_get_page(dev_priv->semaphore_obj, 0);
3012
3013 seqno = (uint64_t *)kmap_atomic(page);
3014 for_each_ring(ring, dev_priv, i) {
3015 uint64_t offset;
3016
3017 seq_printf(m, "%s\n", ring->name);
3018
3019 seq_puts(m, " Last signal:");
3020 for (j = 0; j < num_rings; j++) {
3021 offset = i * I915_NUM_RINGS + j;
3022 seq_printf(m, "0x%08llx (0x%02llx) ",
3023 seqno[offset], offset * 8);
3024 }
3025 seq_putc(m, '\n');
3026
3027 seq_puts(m, " Last wait: ");
3028 for (j = 0; j < num_rings; j++) {
3029 offset = i + (j * I915_NUM_RINGS);
3030 seq_printf(m, "0x%08llx (0x%02llx) ",
3031 seqno[offset], offset * 8);
3032 }
3033 seq_putc(m, '\n');
3034
3035 }
3036 kunmap_atomic(seqno);
3037 } else {
3038 seq_puts(m, " Last signal:");
3039 for_each_ring(ring, dev_priv, i)
3040 for (j = 0; j < num_rings; j++)
3041 seq_printf(m, "0x%08x\n",
3042 I915_READ(ring->semaphore.mbox.signal[j]));
3043 seq_putc(m, '\n');
3044 }
3045
3046 seq_puts(m, "\nSync seqno:\n");
3047 for_each_ring(ring, dev_priv, i) {
3048 for (j = 0; j < num_rings; j++) {
3049 seq_printf(m, " 0x%08x ", ring->semaphore.sync_seqno[j]);
3050 }
3051 seq_putc(m, '\n');
3052 }
3053 seq_putc(m, '\n');
3054
03872064 3055 intel_runtime_pm_put(dev_priv);
e04934cf
BW		 3056 mutex_unlock(&dev->struct_mutex);
3057 return 0;
3058}
3059
728e29d7
DV		 3060static int i915_shared_dplls_info(struct seq_file *m, void *unused)
3061{
3062 struct drm_info_node *node = (struct drm_info_node *) m->private;
3063 struct drm_device *dev = node->minor->dev;
3064 struct drm_i915_private *dev_priv = dev->dev_private;
3065 int i;
3066
3067 drm_modeset_lock_all(dev);
3068 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3069 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
3070
3071 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
1e6f2ddc 3072 seq_printf(m, " crtc_mask: 0x%08x, active: %d, on: %s\n",
3e369b76 3073 pll->config.crtc_mask, pll->active, yesno(pll->on));
728e29d7 3074 seq_printf(m, " tracked hardware state:\n");
3e369b76
ACO		 3075 seq_printf(m, " dpll: 0x%08x\n", pll->config.hw_state.dpll);
3076 seq_printf(m, " dpll_md: 0x%08x\n",
3077 pll->config.hw_state.dpll_md);
3078 seq_printf(m, " fp0: 0x%08x\n", pll->config.hw_state.fp0);
3079 seq_printf(m, " fp1: 0x%08x\n", pll->config.hw_state.fp1);
3080 seq_printf(m, " wrpll: 0x%08x\n", pll->config.hw_state.wrpll);
728e29d7
DV		 3081 }
3082 drm_modeset_unlock_all(dev);
3083
3084 return 0;
3085}
3086
1ed1ef9d 3087static int i915_wa_registers(struct seq_file *m, void *unused)
888b5995
AS		 3088{
3089 int i;
3090 int ret;
3091 struct drm_info_node *node = (struct drm_info_node *) m->private;
3092 struct drm_device *dev = node->minor->dev;
3093 struct drm_i915_private *dev_priv = dev->dev_private;
3094
888b5995
AS		 3095 ret = mutex_lock_interruptible(&dev->struct_mutex);
3096 if (ret)
3097 return ret;
3098
3099 intel_runtime_pm_get(dev_priv);
3100
7225342a
MK		 3101 seq_printf(m, "Workarounds applied: %d\n", dev_priv->workarounds.count);
3102 for (i = 0; i < dev_priv->workarounds.count; ++i) {
2fa60f6d
MK		 3103 u32 addr, mask, value, read;
3104 bool ok;
888b5995 3105
7225342a
MK		 3106 addr = dev_priv->workarounds.reg[i].addr;
3107 mask = dev_priv->workarounds.reg[i].mask;
2fa60f6d
MK		 3108 value = dev_priv->workarounds.reg[i].value;
3109 read = I915_READ(addr);
3110 ok = (value & mask) == (read & mask);
3111 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
3112 addr, value, mask, read, ok ? "OK" : "FAIL");
888b5995
AS		 3113 }
3114
3115 intel_runtime_pm_put(dev_priv);
3116 mutex_unlock(&dev->struct_mutex);
3117
3118 return 0;
3119}
3120
c5511e44
DL		 3121static int i915_ddb_info(struct seq_file *m, void *unused)
3122{
3123 struct drm_info_node *node = m->private;
3124 struct drm_device *dev = node->minor->dev;
3125 struct drm_i915_private *dev_priv = dev->dev_private;
3126 struct skl_ddb_allocation *ddb;
3127 struct skl_ddb_entry *entry;
3128 enum pipe pipe;
3129 int plane;
3130
2fcffe19
DL		 3131 if (INTEL_INFO(dev)->gen < 9)
3132 return 0;
3133
c5511e44
DL		 3134 drm_modeset_lock_all(dev);
3135
3136 ddb = &dev_priv->wm.skl_hw.ddb;
3137
3138 seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
3139
3140 for_each_pipe(dev_priv, pipe) {
3141 seq_printf(m, "Pipe %c\n", pipe_name(pipe));
3142
dd740780 3143 for_each_plane(dev_priv, pipe, plane) {
c5511e44
DL		 3144 entry = &ddb->plane[pipe][plane];
3145 seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane + 1,
3146 entry->start, entry->end,
3147 skl_ddb_entry_size(entry));
3148 }
3149
3150 entry = &ddb->cursor[pipe];
3151 seq_printf(m, " %-13s%8u%8u%8u\n", "Cursor", entry->start,
3152 entry->end, skl_ddb_entry_size(entry));
3153 }
3154
3155 drm_modeset_unlock_all(dev);
3156
3157 return 0;
3158}
3159
a54746e3
VK		 3160static void drrs_status_per_crtc(struct seq_file *m,
3161 struct drm_device *dev, struct intel_crtc *intel_crtc)
3162{
3163 struct intel_encoder *intel_encoder;
3164 struct drm_i915_private *dev_priv = dev->dev_private;
3165 struct i915_drrs *drrs = &dev_priv->drrs;
3166 int vrefresh = 0;
3167
3168 for_each_encoder_on_crtc(dev, &intel_crtc->base, intel_encoder) {
3169 /* Encoder connected on this CRTC */
3170 switch (intel_encoder->type) {
3171 case INTEL_OUTPUT_EDP:
3172 seq_puts(m, "eDP:\n");
3173 break;
3174 case INTEL_OUTPUT_DSI:
3175 seq_puts(m, "DSI:\n");
3176 break;
3177 case INTEL_OUTPUT_HDMI:
3178 seq_puts(m, "HDMI:\n");
3179 break;
3180 case INTEL_OUTPUT_DISPLAYPORT:
3181 seq_puts(m, "DP:\n");
3182 break;
3183 default:
3184 seq_printf(m, "Other encoder (id=%d).\n",
3185 intel_encoder->type);
3186 return;
3187 }
3188 }
3189
3190 if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT)
3191 seq_puts(m, "\tVBT: DRRS_type: Static");
3192 else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT)
3193 seq_puts(m, "\tVBT: DRRS_type: Seamless");
3194 else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED)
3195 seq_puts(m, "\tVBT: DRRS_type: None");
3196 else
3197 seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value");
3198
3199 seq_puts(m, "\n\n");
3200
f77076c9 3201 if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) {
a54746e3
VK		 3202 struct intel_panel *panel;
3203
3204 mutex_lock(&drrs->mutex);
3205 /* DRRS Supported */
3206 seq_puts(m, "\tDRRS Supported: Yes\n");
3207
3208 /* disable_drrs() will make drrs->dp NULL */
3209 if (!drrs->dp) {
3210 seq_puts(m, "Idleness DRRS: Disabled");
3211 mutex_unlock(&drrs->mutex);
3212 return;
3213 }
3214
3215 panel = &drrs->dp->attached_connector->panel;
3216 seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X",
3217 drrs->busy_frontbuffer_bits);
3218
3219 seq_puts(m, "\n\t\t");
3220 if (drrs->refresh_rate_type == DRRS_HIGH_RR) {
3221 seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n");
3222 vrefresh = panel->fixed_mode->vrefresh;
3223 } else if (drrs->refresh_rate_type == DRRS_LOW_RR) {
3224 seq_puts(m, "DRRS_State: DRRS_LOW_RR\n");
3225 vrefresh = panel->downclock_mode->vrefresh;
3226 } else {
3227 seq_printf(m, "DRRS_State: Unknown(%d)\n",
3228 drrs->refresh_rate_type);
3229 mutex_unlock(&drrs->mutex);
3230 return;
3231 }
3232 seq_printf(m, "\t\tVrefresh: %d", vrefresh);
3233
3234 seq_puts(m, "\n\t\t");
3235 mutex_unlock(&drrs->mutex);
3236 } else {
3237 /* DRRS not supported. Print the VBT parameter*/
3238 seq_puts(m, "\tDRRS Supported : No");
3239 }
3240 seq_puts(m, "\n");
3241}
3242
3243static int i915_drrs_status(struct seq_file *m, void *unused)
3244{
3245 struct drm_info_node *node = m->private;
3246 struct drm_device *dev = node->minor->dev;
3247 struct intel_crtc *intel_crtc;
3248 int active_crtc_cnt = 0;
3249
3250 for_each_intel_crtc(dev, intel_crtc) {
3251 drm_modeset_lock(&intel_crtc->base.mutex, NULL);
3252
f77076c9 3253 if (intel_crtc->base.state->active) {
a54746e3
VK		 3254 active_crtc_cnt++;
3255 seq_printf(m, "\nCRTC %d: ", active_crtc_cnt);
3256
3257 drrs_status_per_crtc(m, dev, intel_crtc);
3258 }
3259
3260 drm_modeset_unlock(&intel_crtc->base.mutex);
3261 }
3262
3263 if (!active_crtc_cnt)
3264 seq_puts(m, "No active crtc found\n");
3265
3266 return 0;
3267}
3268
07144428
DL		 3269struct pipe_crc_info {
3270 const char *name;
3271 struct drm_device *dev;
3272 enum pipe pipe;
3273};
3274
11bed958
DA		 3275static int i915_dp_mst_info(struct seq_file *m, void *unused)
3276{
3277 struct drm_info_node *node = (struct drm_info_node *) m->private;
3278 struct drm_device *dev = node->minor->dev;
3279 struct drm_encoder *encoder;
3280 struct intel_encoder *intel_encoder;
3281 struct intel_digital_port *intel_dig_port;
3282 drm_modeset_lock_all(dev);
3283 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3284 intel_encoder = to_intel_encoder(encoder);
3285 if (intel_encoder->type != INTEL_OUTPUT_DISPLAYPORT)
3286 continue;
3287 intel_dig_port = enc_to_dig_port(encoder);
3288 if (!intel_dig_port->dp.can_mst)
3289 continue;
3290
3291 drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr);
3292 }
3293 drm_modeset_unlock_all(dev);
3294 return 0;
3295}
3296
07144428
DL		 3297static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
3298{
be5c7a90
DL		 3299 struct pipe_crc_info *info = inode->i_private;
3300 struct drm_i915_private *dev_priv = info->dev->dev_private;
3301 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3302
7eb1c496
DV		 3303 if (info->pipe >= INTEL_INFO(info->dev)->num_pipes)
3304 return -ENODEV;
3305
d538bbdf
DL		 3306 spin_lock_irq(&pipe_crc->lock);
3307
3308 if (pipe_crc->opened) {
3309 spin_unlock_irq(&pipe_crc->lock);
be5c7a90
DL		 3310 return -EBUSY; /* already open */
3311 }
3312
d538bbdf 3313 pipe_crc->opened = true;
07144428
DL		 3314 filep->private_data = inode->i_private;
3315
d538bbdf
DL		 3316 spin_unlock_irq(&pipe_crc->lock);
3317
07144428
DL		 3318 return 0;
3319}
3320
3321static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
3322{
be5c7a90
DL		 3323 struct pipe_crc_info *info = inode->i_private;
3324 struct drm_i915_private *dev_priv = info->dev->dev_private;
3325 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3326
d538bbdf
DL		 3327 spin_lock_irq(&pipe_crc->lock);
3328 pipe_crc->opened = false;
3329 spin_unlock_irq(&pipe_crc->lock);
be5c7a90 3330
07144428
DL		 3331 return 0;
3332}
3333
3334/* (6 fields, 8 chars each, space separated (5) + '\n') */
3335#define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
3336/* account for \'0' */
3337#define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1)
3338
3339static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
8bf1e9f1 3340{
d538bbdf
DL		 3341 assert_spin_locked(&pipe_crc->lock);
3342 return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3343 INTEL_PIPE_CRC_ENTRIES_NR);
07144428
DL		 3344}
3345
3346static ssize_t
3347i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
3348 loff_t *pos)
3349{
3350 struct pipe_crc_info *info = filep->private_data;
3351 struct drm_device *dev = info->dev;
3352 struct drm_i915_private *dev_priv = dev->dev_private;
3353 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3354 char buf[PIPE_CRC_BUFFER_LEN];
9ad6d99f 3355 int n_entries;
07144428
DL		 3356 ssize_t bytes_read;
3357
3358 /*
3359 * Don't allow user space to provide buffers not big enough to hold
3360 * a line of data.
3361 */
3362 if (count < PIPE_CRC_LINE_LEN)
3363 return -EINVAL;
3364
3365 if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
8bf1e9f1 3366 return 0;
07144428
DL		 3367
3368 /* nothing to read */
d538bbdf 3369 spin_lock_irq(&pipe_crc->lock);
07144428 3370 while (pipe_crc_data_count(pipe_crc) == 0) {
d538bbdf
DL		 3371 int ret;
3372
3373 if (filep->f_flags & O_NONBLOCK) {
3374 spin_unlock_irq(&pipe_crc->lock);
07144428 3375 return -EAGAIN;
d538bbdf 3376 }
07144428 3377
d538bbdf
DL		 3378 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
3379 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
3380 if (ret) {
3381 spin_unlock_irq(&pipe_crc->lock);
3382 return ret;
3383 }
8bf1e9f1
SH		 3384 }
3385
07144428 3386 /* We now have one or more entries to read */
9ad6d99f 3387 n_entries = count / PIPE_CRC_LINE_LEN;
d538bbdf 3388
07144428 3389 bytes_read = 0;
9ad6d99f
VS		 3390 while (n_entries > 0) {
3391 struct intel_pipe_crc_entry *entry =
3392 &pipe_crc->entries[pipe_crc->tail];
07144428 3393 int ret;
8bf1e9f1 3394
9ad6d99f
VS		 3395 if (CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3396 INTEL_PIPE_CRC_ENTRIES_NR) < 1)
3397 break;
3398
3399 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
3400 pipe_crc->tail = (pipe_crc->tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
3401
07144428
DL		 3402 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
3403 "%8u %8x %8x %8x %8x %8x\n",
3404 entry->frame, entry->crc[0],
3405 entry->crc[1], entry->crc[2],
3406 entry->crc[3], entry->crc[4]);
3407
9ad6d99f
VS		 3408 spin_unlock_irq(&pipe_crc->lock);
3409
3410 ret = copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN);
07144428
DL		 3411 if (ret == PIPE_CRC_LINE_LEN)
3412 return -EFAULT;
b2c88f5b 3413
9ad6d99f
VS		 3414 user_buf += PIPE_CRC_LINE_LEN;
3415 n_entries--;
3416
3417 spin_lock_irq(&pipe_crc->lock);
3418 }
8bf1e9f1 3419
d538bbdf
DL		 3420 spin_unlock_irq(&pipe_crc->lock);
3421
07144428
DL		 3422 return bytes_read;
3423}
3424
3425static const struct file_operations i915_pipe_crc_fops = {
3426 .owner = THIS_MODULE,
3427 .open = i915_pipe_crc_open,
3428 .read = i915_pipe_crc_read,
3429 .release = i915_pipe_crc_release,
3430};
3431
3432static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
3433 {
3434 .name = "i915_pipe_A_crc",
3435 .pipe = PIPE_A,
3436 },
3437 {
3438 .name = "i915_pipe_B_crc",
3439 .pipe = PIPE_B,
3440 },
3441 {
3442 .name = "i915_pipe_C_crc",
3443 .pipe = PIPE_C,
3444 },
3445};
3446
3447static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
3448 enum pipe pipe)
3449{
3450 struct drm_device *dev = minor->dev;
3451 struct dentry *ent;
3452 struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
3453
3454 info->dev = dev;
3455 ent = debugfs_create_file(info->name, S_IRUGO, root, info,
3456 &i915_pipe_crc_fops);
f3c5fe97
WY		 3457 if (!ent)
3458 return -ENOMEM;
07144428
DL		 3459
3460 return drm_add_fake_info_node(minor, ent, info);
8bf1e9f1
SH		 3461}
3462
e8dfcf78 3463static const char * const pipe_crc_sources[] = {
926321d5
DV		 3464 "none",
3465 "plane1",
3466 "plane2",
3467 "pf",
5b3a856b 3468 "pipe",
3d099a05
DV		 3469 "TV",
3470 "DP-B",
3471 "DP-C",
3472 "DP-D",
46a19188 3473 "auto",
926321d5
DV		 3474};
3475
3476static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
3477{
3478 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
3479 return pipe_crc_sources[source];
3480}
3481
bd9db02f 3482static int display_crc_ctl_show(struct seq_file *m, void *data)
926321d5
DV		 3483{
3484 struct drm_device *dev = m->private;
3485 struct drm_i915_private *dev_priv = dev->dev_private;
3486 int i;
3487
3488 for (i = 0; i < I915_MAX_PIPES; i++)
3489 seq_printf(m, "%c %s\n", pipe_name(i),
3490 pipe_crc_source_name(dev_priv->pipe_crc[i].source));
3491
3492 return 0;
3493}
3494
bd9db02f 3495static int display_crc_ctl_open(struct inode *inode, struct file *file)
926321d5
DV		 3496{
3497 struct drm_device *dev = inode->i_private;
3498
bd9db02f 3499 return single_open(file, display_crc_ctl_show, dev);
926321d5
DV		 3500}
3501
46a19188 3502static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
52f843f6
DV		 3503 uint32_t *val)
3504{
46a19188
DV		 3505 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3506 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3507
3508 switch (*source) {
52f843f6
DV		 3509 case INTEL_PIPE_CRC_SOURCE_PIPE:
3510 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
3511 break;
3512 case INTEL_PIPE_CRC_SOURCE_NONE:
3513 *val = 0;
3514 break;
3515 default:
3516 return -EINVAL;
3517 }
3518
3519 return 0;
3520}
3521
46a19188
DV		 3522static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe,
3523 enum intel_pipe_crc_source *source)
3524{
3525 struct intel_encoder *encoder;
3526 struct intel_crtc *crtc;
26756809 3527 struct intel_digital_port *dig_port;
46a19188
DV		 3528 int ret = 0;
3529
3530 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3531
6e9f798d 3532 drm_modeset_lock_all(dev);
b2784e15 3533 for_each_intel_encoder(dev, encoder) {
46a19188
DV		 3534 if (!encoder->base.crtc)
3535 continue;
3536
3537 crtc = to_intel_crtc(encoder->base.crtc);
3538
3539 if (crtc->pipe != pipe)
3540 continue;
3541
3542 switch (encoder->type) {
3543 case INTEL_OUTPUT_TVOUT:
3544 *source = INTEL_PIPE_CRC_SOURCE_TV;
3545 break;
3546 case INTEL_OUTPUT_DISPLAYPORT:
3547 case INTEL_OUTPUT_EDP:
26756809
DV		 3548 dig_port = enc_to_dig_port(&encoder->base);
3549 switch (dig_port->port) {
3550 case PORT_B:
3551 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
3552 break;
3553 case PORT_C:
3554 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
3555 break;
3556 case PORT_D:
3557 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
3558 break;
3559 default:
3560 WARN(1, "nonexisting DP port %c\n",
3561 port_name(dig_port->port));
3562 break;
3563 }
46a19188 3564 break;
6847d71b
PZ		 3565 default:
3566 break;
46a19188
DV		 3567 }
3568 }
6e9f798d 3569 drm_modeset_unlock_all(dev);
46a19188
DV		 3570
3571 return ret;
3572}
3573
3574static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
3575 enum pipe pipe,
3576 enum intel_pipe_crc_source *source,
7ac0129b
DV		 3577 uint32_t *val)
3578{
8d2f24ca
DV		 3579 struct drm_i915_private *dev_priv = dev->dev_private;
3580 bool need_stable_symbols = false;
3581
46a19188
DV		 3582 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3583 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3584 if (ret)
3585 return ret;
3586 }
3587
3588 switch (*source) {
7ac0129b
DV		 3589 case INTEL_PIPE_CRC_SOURCE_PIPE:
3590 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
3591 break;
3592 case INTEL_PIPE_CRC_SOURCE_DP_B:
3593 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
8d2f24ca 3594 need_stable_symbols = true;
7ac0129b
DV		 3595 break;
3596 case INTEL_PIPE_CRC_SOURCE_DP_C:
3597 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
8d2f24ca 3598 need_stable_symbols = true;
7ac0129b 3599 break;
2be57922
VS		 3600 case INTEL_PIPE_CRC_SOURCE_DP_D:
3601 if (!IS_CHERRYVIEW(dev))
3602 return -EINVAL;
3603 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV;
3604 need_stable_symbols = true;
3605 break;
7ac0129b
DV		 3606 case INTEL_PIPE_CRC_SOURCE_NONE:
3607 *val = 0;
3608 break;
3609 default:
3610 return -EINVAL;
3611 }
3612
8d2f24ca
DV		 3613 /*
3614 * When the pipe CRC tap point is after the transcoders we need
3615 * to tweak symbol-level features to produce a deterministic series of
3616 * symbols for a given frame. We need to reset those features only once
3617 * a frame (instead of every nth symbol):
3618 * - DC-balance: used to ensure a better clock recovery from the data
3619 * link (SDVO)
3620 * - DisplayPort scrambling: used for EMI reduction
3621 */
3622 if (need_stable_symbols) {
3623 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3624
8d2f24ca 3625 tmp |= DC_BALANCE_RESET_VLV;
eb736679
VS		 3626 switch (pipe) {
3627 case PIPE_A:
8d2f24ca 3628 tmp |= PIPE_A_SCRAMBLE_RESET;
eb736679
VS		 3629 break;
3630 case PIPE_B:
8d2f24ca 3631 tmp |= PIPE_B_SCRAMBLE_RESET;
eb736679
VS		 3632 break;
3633 case PIPE_C:
3634 tmp |= PIPE_C_SCRAMBLE_RESET;
3635 break;
3636 default:
3637 return -EINVAL;
3638 }
8d2f24ca
DV		 3639 I915_WRITE(PORT_DFT2_G4X, tmp);
3640 }
3641
7ac0129b
DV		 3642 return 0;
3643}
3644
4b79ebf7 3645static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
46a19188
DV		 3646 enum pipe pipe,
3647 enum intel_pipe_crc_source *source,
4b79ebf7
DV		 3648 uint32_t *val)
3649{
84093603
DV		 3650 struct drm_i915_private *dev_priv = dev->dev_private;
3651 bool need_stable_symbols = false;
3652
46a19188
DV		 3653 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3654 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3655 if (ret)
3656 return ret;
3657 }
3658
3659 switch (*source) {
4b79ebf7
DV		 3660 case INTEL_PIPE_CRC_SOURCE_PIPE:
3661 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
3662 break;
3663 case INTEL_PIPE_CRC_SOURCE_TV:
3664 if (!SUPPORTS_TV(dev))
3665 return -EINVAL;
3666 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
3667 break;
3668 case INTEL_PIPE_CRC_SOURCE_DP_B:
3669 if (!IS_G4X(dev))
3670 return -EINVAL;
3671 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
84093603 3672 need_stable_symbols = true;
4b79ebf7
DV		 3673 break;
3674 case INTEL_PIPE_CRC_SOURCE_DP_C:
3675 if (!IS_G4X(dev))
3676 return -EINVAL;
3677 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
84093603 3678 need_stable_symbols = true;
4b79ebf7
DV		 3679 break;
3680 case INTEL_PIPE_CRC_SOURCE_DP_D:
3681 if (!IS_G4X(dev))
3682 return -EINVAL;
3683 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
84093603 3684 need_stable_symbols = true;
4b79ebf7
DV		 3685 break;
3686 case INTEL_PIPE_CRC_SOURCE_NONE:
3687 *val = 0;
3688 break;
3689 default:
3690 return -EINVAL;
3691 }
3692
84093603
DV		 3693 /*
3694 * When the pipe CRC tap point is after the transcoders we need
3695 * to tweak symbol-level features to produce a deterministic series of
3696 * symbols for a given frame. We need to reset those features only once
3697 * a frame (instead of every nth symbol):
3698 * - DC-balance: used to ensure a better clock recovery from the data
3699 * link (SDVO)
3700 * - DisplayPort scrambling: used for EMI reduction
3701 */
3702 if (need_stable_symbols) {
3703 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3704
3705 WARN_ON(!IS_G4X(dev));
3706
3707 I915_WRITE(PORT_DFT_I9XX,
3708 I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
3709
3710 if (pipe == PIPE_A)
3711 tmp |= PIPE_A_SCRAMBLE_RESET;
3712 else
3713 tmp |= PIPE_B_SCRAMBLE_RESET;
3714
3715 I915_WRITE(PORT_DFT2_G4X, tmp);
3716 }
3717
4b79ebf7
DV		 3718 return 0;
3719}
3720
8d2f24ca
DV		 3721static void vlv_undo_pipe_scramble_reset(struct drm_device *dev,
3722 enum pipe pipe)
3723{
3724 struct drm_i915_private *dev_priv = dev->dev_private;
3725 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3726
eb736679
VS		 3727 switch (pipe) {
3728 case PIPE_A:
8d2f24ca 3729 tmp &= ~PIPE_A_SCRAMBLE_RESET;
eb736679
VS		 3730 break;
3731 case PIPE_B:
8d2f24ca 3732 tmp &= ~PIPE_B_SCRAMBLE_RESET;
eb736679
VS		 3733 break;
3734 case PIPE_C:
3735 tmp &= ~PIPE_C_SCRAMBLE_RESET;
3736 break;
3737 default:
3738 return;
3739 }
8d2f24ca
DV		 3740 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
3741 tmp &= ~DC_BALANCE_RESET_VLV;
3742 I915_WRITE(PORT_DFT2_G4X, tmp);
3743
3744}
3745
84093603
DV		 3746static void g4x_undo_pipe_scramble_reset(struct drm_device *dev,
3747 enum pipe pipe)
3748{
3749 struct drm_i915_private *dev_priv = dev->dev_private;
3750 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3751
3752 if (pipe == PIPE_A)
3753 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3754 else
3755 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3756 I915_WRITE(PORT_DFT2_G4X, tmp);
3757
3758 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
3759 I915_WRITE(PORT_DFT_I9XX,
3760 I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
3761 }
3762}
3763
46a19188 3764static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
5b3a856b
DV		 3765 uint32_t *val)
3766{
46a19188
DV		 3767 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3768 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3769
3770 switch (*source) {
5b3a856b
DV		 3771 case INTEL_PIPE_CRC_SOURCE_PLANE1:
3772 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
3773 break;
3774 case INTEL_PIPE_CRC_SOURCE_PLANE2:
3775 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
3776 break;
5b3a856b
DV		 3777 case INTEL_PIPE_CRC_SOURCE_PIPE:
3778 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
3779 break;
3d099a05 3780 case INTEL_PIPE_CRC_SOURCE_NONE:
5b3a856b
DV		 3781 *val = 0;
3782 break;
3d099a05
DV		 3783 default:
3784 return -EINVAL;
5b3a856b
DV		 3785 }
3786
3787 return 0;
3788}
3789
c4e2d043 3790static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device *dev, bool enable)
fabf6e51
DV		 3791{
3792 struct drm_i915_private *dev_priv = dev->dev_private;
3793 struct intel_crtc *crtc =
3794 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
f77076c9 3795 struct intel_crtc_state *pipe_config;
c4e2d043
ML		 3796 struct drm_atomic_state *state;
3797 int ret = 0;
fabf6e51
DV		 3798
3799 drm_modeset_lock_all(dev);
c4e2d043
ML		 3800 state = drm_atomic_state_alloc(dev);
3801 if (!state) {
3802 ret = -ENOMEM;
3803 goto out;
fabf6e51 3804 }
fabf6e51 3805
c4e2d043
ML		 3806 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(&crtc->base);
3807 pipe_config = intel_atomic_get_crtc_state(state, crtc);
3808 if (IS_ERR(pipe_config)) {
3809 ret = PTR_ERR(pipe_config);
3810 goto out;
3811 }
fabf6e51 3812
c4e2d043
ML		 3813 pipe_config->pch_pfit.force_thru = enable;
3814 if (pipe_config->cpu_transcoder == TRANSCODER_EDP &&
3815 pipe_config->pch_pfit.enabled != enable)
3816 pipe_config->base.connectors_changed = true;
1b509259 3817
c4e2d043
ML		 3818 ret = drm_atomic_commit(state);
3819out:
fabf6e51 3820 drm_modeset_unlock_all(dev);
c4e2d043
ML		 3821 WARN(ret, "Toggling workaround to %i returns %i\n", enable, ret);
3822 if (ret)
3823 drm_atomic_state_free(state);
fabf6e51
DV		 3824}
3825
3826static int ivb_pipe_crc_ctl_reg(struct drm_device *dev,
3827 enum pipe pipe,
3828 enum intel_pipe_crc_source *source,
5b3a856b
DV		 3829 uint32_t *val)
3830{
46a19188
DV		 3831 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3832 *source = INTEL_PIPE_CRC_SOURCE_PF;
3833
3834 switch (*source) {
5b3a856b
DV		 3835 case INTEL_PIPE_CRC_SOURCE_PLANE1:
3836 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
3837 break;
3838 case INTEL_PIPE_CRC_SOURCE_PLANE2:
3839 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
3840 break;
3841 case INTEL_PIPE_CRC_SOURCE_PF:
fabf6e51 3842 if (IS_HASWELL(dev) && pipe == PIPE_A)
c4e2d043 3843 hsw_trans_edp_pipe_A_crc_wa(dev, true);
fabf6e51 3844
5b3a856b
DV		 3845 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
3846 break;
3d099a05 3847 case INTEL_PIPE_CRC_SOURCE_NONE:
5b3a856b
DV		 3848 *val = 0;
3849 break;
3d099a05
DV		 3850 default:
3851 return -EINVAL;
5b3a856b
DV		 3852 }
3853
3854 return 0;
3855}
3856
926321d5
DV		 3857static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
3858 enum intel_pipe_crc_source source)
3859{
3860 struct drm_i915_private *dev_priv = dev->dev_private;
cc3da175 3861 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
8c740dce
PZ		 3862 struct intel_crtc *crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev,
3863 pipe));
432f3342 3864 u32 val = 0; /* shut up gcc */
5b3a856b 3865 int ret;
926321d5 3866
cc3da175
DL		 3867 if (pipe_crc->source == source)
3868 return 0;
3869
ae676fcd
DL		 3870 /* forbid changing the source without going back to 'none' */
3871 if (pipe_crc->source && source)
3872 return -EINVAL;
3873
9d8b0588
DV		 3874 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PIPE(pipe))) {
3875 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
3876 return -EIO;
3877 }
3878
52f843f6 3879 if (IS_GEN2(dev))
46a19188 3880 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
52f843f6 3881 else if (INTEL_INFO(dev)->gen < 5)
46a19188 3882 ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
7ac0129b 3883 else if (IS_VALLEYVIEW(dev))
fabf6e51 3884 ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val);
4b79ebf7 3885 else if (IS_GEN5(dev) || IS_GEN6(dev))
46a19188 3886 ret = ilk_pipe_crc_ctl_reg(&source, &val);
5b3a856b 3887 else
fabf6e51 3888 ret = ivb_pipe_crc_ctl_reg(dev, pipe, &source, &val);
5b3a856b
DV		 3889
3890 if (ret != 0)
3891 return ret;
3892
4b584369
DL		 3893 /* none -> real source transition */
3894 if (source) {
4252fbc3
VS		 3895 struct intel_pipe_crc_entry *entries;
3896
7cd6ccff
DL		 3897 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
3898 pipe_name(pipe), pipe_crc_source_name(source));
3899
3cf54b34
VS		 3900 entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR,
3901 sizeof(pipe_crc->entries[0]),
4252fbc3
VS		 3902 GFP_KERNEL);
3903 if (!entries)
e5f75aca
DL		 3904 return -ENOMEM;
3905
8c740dce
PZ		 3906 /*
3907 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
3908 * enabled and disabled dynamically based on package C states,
3909 * user space can't make reliable use of the CRCs, so let's just
3910 * completely disable it.
3911 */
3912 hsw_disable_ips(crtc);
3913
d538bbdf 3914 spin_lock_irq(&pipe_crc->lock);
64387b61 3915 kfree(pipe_crc->entries);
4252fbc3 3916 pipe_crc->entries = entries;
d538bbdf
DL		 3917 pipe_crc->head = 0;
3918 pipe_crc->tail = 0;
3919 spin_unlock_irq(&pipe_crc->lock);
4b584369
DL		 3920 }
3921
cc3da175 3922 pipe_crc->source = source;
926321d5 3923
926321d5
DV		 3924 I915_WRITE(PIPE_CRC_CTL(pipe), val);
3925 POSTING_READ(PIPE_CRC_CTL(pipe));
3926
e5f75aca
DL		 3927 /* real source -> none transition */
3928 if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
d538bbdf 3929 struct intel_pipe_crc_entry *entries;
a33d7105
DV		 3930 struct intel_crtc *crtc =
3931 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
d538bbdf 3932
7cd6ccff
DL		 3933 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
3934 pipe_name(pipe));
3935
a33d7105 3936 drm_modeset_lock(&crtc->base.mutex, NULL);
f77076c9 3937 if (crtc->base.state->active)
a33d7105
DV		 3938 intel_wait_for_vblank(dev, pipe);
3939 drm_modeset_unlock(&crtc->base.mutex);
bcf17ab2 3940
d538bbdf
DL		 3941 spin_lock_irq(&pipe_crc->lock);
3942 entries = pipe_crc->entries;
e5f75aca 3943 pipe_crc->entries = NULL;
9ad6d99f
VS		 3944 pipe_crc->head = 0;
3945 pipe_crc->tail = 0;
d538bbdf
DL		 3946 spin_unlock_irq(&pipe_crc->lock);
3947
3948 kfree(entries);
84093603
DV		 3949
3950 if (IS_G4X(dev))
3951 g4x_undo_pipe_scramble_reset(dev, pipe);
8d2f24ca
DV		 3952 else if (IS_VALLEYVIEW(dev))
3953 vlv_undo_pipe_scramble_reset(dev, pipe);
fabf6e51 3954 else if (IS_HASWELL(dev) && pipe == PIPE_A)
c4e2d043 3955 hsw_trans_edp_pipe_A_crc_wa(dev, false);
8c740dce
PZ		 3956
3957 hsw_enable_ips(crtc);
e5f75aca
DL		 3958 }
3959
926321d5
DV		 3960 return 0;
3961}
3962
3963/*
3964 * Parse pipe CRC command strings:
b94dec87
DL		 3965 * command: wsp* object wsp+ name wsp+ source wsp*
3966 * object: 'pipe'
3967 * name: (A | B | C)
926321d5
DV		 3968 * source: (none | plane1 | plane2 | pf)
3969 * wsp: (#0x20 | #0x9 | #0xA)+
3970 *
3971 * eg.:
b94dec87
DL		 3972 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A
3973 * "pipe A none" -> Stop CRC
926321d5 3974 */
bd9db02f 3975static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
926321d5
DV		 3976{
3977 int n_words = 0;
3978
3979 while (*buf) {
3980 char *end;
3981
3982 /* skip leading white space */
3983 buf = skip_spaces(buf);
3984 if (!*buf)
3985 break; /* end of buffer */
3986
3987 /* find end of word */
3988 for (end = buf; *end && !isspace(*end); end++)
3989 ;
3990
3991 if (n_words == max_words) {
3992 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
3993 max_words);
3994 return -EINVAL; /* ran out of words[] before bytes */
3995 }
3996
3997 if (*end)
3998 *end++ = '\0';
3999 words[n_words++] = buf;
4000 buf = end;
4001 }
4002
4003 return n_words;
4004}
4005
b94dec87
DL		 4006enum intel_pipe_crc_object {
4007 PIPE_CRC_OBJECT_PIPE,
4008};
4009
e8dfcf78 4010static const char * const pipe_crc_objects[] = {
b94dec87
DL		 4011 "pipe",
4012};
4013
4014static int
bd9db02f 4015display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
b94dec87
DL		 4016{
4017 int i;
4018
4019 for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
4020 if (!strcmp(buf, pipe_crc_objects[i])) {
bd9db02f 4021 *o = i;
b94dec87
DL		 4022 return 0;
4023 }
4024
4025 return -EINVAL;
4026}
4027
bd9db02f 4028static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
926321d5
DV		 4029{
4030 const char name = buf[0];
4031
4032 if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
4033 return -EINVAL;
4034
4035 *pipe = name - 'A';
4036
4037 return 0;
4038}
4039
4040static int
bd9db02f 4041display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
926321d5
DV		 4042{
4043 int i;
4044
4045 for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
4046 if (!strcmp(buf, pipe_crc_sources[i])) {
bd9db02f 4047 *s = i;
926321d5
DV		 4048 return 0;
4049 }
4050
4051 return -EINVAL;
4052}
4053
bd9db02f 4054static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len)
926321d5 4055{
b94dec87 4056#define N_WORDS 3
926321d5 4057 int n_words;
b94dec87 4058 char *words[N_WORDS];
926321d5 4059 enum pipe pipe;
b94dec87 4060 enum intel_pipe_crc_object object;
926321d5
DV		 4061 enum intel_pipe_crc_source source;
4062
bd9db02f 4063 n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
b94dec87
DL		 4064 if (n_words != N_WORDS) {
4065 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
4066 N_WORDS);
4067 return -EINVAL;
4068 }
4069
bd9db02f 4070 if (display_crc_ctl_parse_object(words[0], &object) < 0) {
b94dec87 4071 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
926321d5
DV		 4072 return -EINVAL;
4073 }
4074
bd9db02f 4075 if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
b94dec87 4076 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
926321d5
DV		 4077 return -EINVAL;
4078 }
4079
bd9db02f 4080 if (display_crc_ctl_parse_source(words[2], &source) < 0) {
b94dec87 4081 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
926321d5
DV		 4082 return -EINVAL;
4083 }
4084
4085 return pipe_crc_set_source(dev, pipe, source);
4086}
4087
bd9db02f
DL		 4088static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
4089 size_t len, loff_t *offp)
926321d5
DV		 4090{
4091 struct seq_file *m = file->private_data;
4092 struct drm_device *dev = m->private;
4093 char *tmpbuf;
4094 int ret;
4095
4096 if (len == 0)
4097 return 0;
4098
4099 if (len > PAGE_SIZE - 1) {
4100 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
4101 PAGE_SIZE);
4102 return -E2BIG;
4103 }
4104
4105 tmpbuf = kmalloc(len + 1, GFP_KERNEL);
4106 if (!tmpbuf)
4107 return -ENOMEM;
4108
4109 if (copy_from_user(tmpbuf, ubuf, len)) {
4110 ret = -EFAULT;
4111 goto out;
4112 }
4113 tmpbuf[len] = '\0';
4114
bd9db02f 4115 ret = display_crc_ctl_parse(dev, tmpbuf, len);
926321d5
DV		 4116
4117out:
4118 kfree(tmpbuf);
4119 if (ret < 0)
4120 return ret;
4121
4122 *offp += len;
4123 return len;
4124}
4125
bd9db02f 4126static const struct file_operations i915_display_crc_ctl_fops = {
926321d5 4127 .owner = THIS_MODULE,
bd9db02f 4128 .open = display_crc_ctl_open,
926321d5
DV		 4129 .read = seq_read,
4130 .llseek = seq_lseek,
4131 .release = single_release,
bd9db02f 4132 .write = display_crc_ctl_write
926321d5
DV		 4133};
4134
eb3394fa
TP		 4135static ssize_t i915_displayport_test_active_write(struct file *file,
4136 const char __user *ubuf,
4137 size_t len, loff_t *offp)
4138{
4139 char *input_buffer;
4140 int status = 0;
eb3394fa
TP		 4141 struct drm_device *dev;
4142 struct drm_connector *connector;
4143 struct list_head *connector_list;
4144 struct intel_dp *intel_dp;
4145 int val = 0;
4146
9aaffa34 4147 dev = ((struct seq_file *)file->private_data)->private;
eb3394fa 4148
eb3394fa
TP		 4149 connector_list = &dev->mode_config.connector_list;
4150
4151 if (len == 0)
4152 return 0;
4153
4154 input_buffer = kmalloc(len + 1, GFP_KERNEL);
4155 if (!input_buffer)
4156 return -ENOMEM;
4157
4158 if (copy_from_user(input_buffer, ubuf, len)) {
4159 status = -EFAULT;
4160 goto out;
4161 }
4162
4163 input_buffer[len] = '\0';
4164 DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len);
4165
4166 list_for_each_entry(connector, connector_list, head) {
4167
4168 if (connector->connector_type !=
4169 DRM_MODE_CONNECTOR_DisplayPort)
4170 continue;
4171
b8bb08ec 4172 if (connector->status == connector_status_connected &&
eb3394fa
TP		 4173 connector->encoder != NULL) {
4174 intel_dp = enc_to_intel_dp(connector->encoder);
4175 status = kstrtoint(input_buffer, 10, &val);
4176 if (status < 0)
4177 goto out;
4178 DRM_DEBUG_DRIVER("Got %d for test active\n", val);
4179 /* To prevent erroneous activation of the compliance
4180 * testing code, only accept an actual value of 1 here
4181 */
4182 if (val == 1)
4183 intel_dp->compliance_test_active = 1;
4184 else
4185 intel_dp->compliance_test_active = 0;
4186 }
4187 }
4188out:
4189 kfree(input_buffer);
4190 if (status < 0)
4191 return status;
4192
4193 *offp += len;
4194 return len;
4195}
4196
4197static int i915_displayport_test_active_show(struct seq_file *m, void *data)
4198{
4199 struct drm_device *dev = m->private;
4200 struct drm_connector *connector;
4201 struct list_head *connector_list = &dev->mode_config.connector_list;
4202 struct intel_dp *intel_dp;
4203
eb3394fa
TP		 4204 list_for_each_entry(connector, connector_list, head) {
4205
4206 if (connector->connector_type !=
4207 DRM_MODE_CONNECTOR_DisplayPort)
4208 continue;
4209
4210 if (connector->status == connector_status_connected &&
4211 connector->encoder != NULL) {
4212 intel_dp = enc_to_intel_dp(connector->encoder);
4213 if (intel_dp->compliance_test_active)
4214 seq_puts(m, "1");
4215 else
4216 seq_puts(m, "0");
4217 } else
4218 seq_puts(m, "0");
4219 }
4220
4221 return 0;
4222}
4223
4224static int i915_displayport_test_active_open(struct inode *inode,
4225 struct file *file)
4226{
4227 struct drm_device *dev = inode->i_private;
4228
4229 return single_open(file, i915_displayport_test_active_show, dev);
4230}
4231
4232static const struct file_operations i915_displayport_test_active_fops = {
4233 .owner = THIS_MODULE,
4234 .open = i915_displayport_test_active_open,
4235 .read = seq_read,
4236 .llseek = seq_lseek,
4237 .release = single_release,
4238 .write = i915_displayport_test_active_write
4239};
4240
4241static int i915_displayport_test_data_show(struct seq_file *m, void *data)
4242{
4243 struct drm_device *dev = m->private;
4244 struct drm_connector *connector;
4245 struct list_head *connector_list = &dev->mode_config.connector_list;
4246 struct intel_dp *intel_dp;
4247
eb3394fa
TP		 4248 list_for_each_entry(connector, connector_list, head) {
4249
4250 if (connector->connector_type !=
4251 DRM_MODE_CONNECTOR_DisplayPort)
4252 continue;
4253
4254 if (connector->status == connector_status_connected &&
4255 connector->encoder != NULL) {
4256 intel_dp = enc_to_intel_dp(connector->encoder);
4257 seq_printf(m, "%lx", intel_dp->compliance_test_data);
4258 } else
4259 seq_puts(m, "0");
4260 }
4261
4262 return 0;
4263}
4264static int i915_displayport_test_data_open(struct inode *inode,
4265 struct file *file)
4266{
4267 struct drm_device *dev = inode->i_private;
4268
4269 return single_open(file, i915_displayport_test_data_show, dev);
4270}
4271
4272static const struct file_operations i915_displayport_test_data_fops = {
4273 .owner = THIS_MODULE,
4274 .open = i915_displayport_test_data_open,
4275 .read = seq_read,
4276 .llseek = seq_lseek,
4277 .release = single_release
4278};
4279
4280static int i915_displayport_test_type_show(struct seq_file *m, void *data)
4281{
4282 struct drm_device *dev = m->private;
4283 struct drm_connector *connector;
4284 struct list_head *connector_list = &dev->mode_config.connector_list;
4285 struct intel_dp *intel_dp;
4286
eb3394fa
TP		 4287 list_for_each_entry(connector, connector_list, head) {
4288
4289 if (connector->connector_type !=
4290 DRM_MODE_CONNECTOR_DisplayPort)
4291 continue;
4292
4293 if (connector->status == connector_status_connected &&
4294 connector->encoder != NULL) {
4295 intel_dp = enc_to_intel_dp(connector->encoder);
4296 seq_printf(m, "%02lx", intel_dp->compliance_test_type);
4297 } else
4298 seq_puts(m, "0");
4299 }
4300
4301 return 0;
4302}
4303
4304static int i915_displayport_test_type_open(struct inode *inode,
4305 struct file *file)
4306{
4307 struct drm_device *dev = inode->i_private;
4308
4309 return single_open(file, i915_displayport_test_type_show, dev);
4310}
4311
4312static const struct file_operations i915_displayport_test_type_fops = {
4313 .owner = THIS_MODULE,
4314 .open = i915_displayport_test_type_open,
4315 .read = seq_read,
4316 .llseek = seq_lseek,
4317 .release = single_release
4318};
4319
97e94b22 4320static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
369a1342
VS		 4321{
4322 struct drm_device *dev = m->private;
369a1342 4323 int level;
de38b95c
VS		 4324 int num_levels;
4325
4326 if (IS_CHERRYVIEW(dev))
4327 num_levels = 3;
4328 else if (IS_VALLEYVIEW(dev))
4329 num_levels = 1;
4330 else
4331 num_levels = ilk_wm_max_level(dev) + 1;
369a1342
VS		 4332
4333 drm_modeset_lock_all(dev);
4334
4335 for (level = 0; level < num_levels; level++) {
4336 unsigned int latency = wm[level];
4337
97e94b22
DL		 4338 /*
4339 * - WM1+ latency values in 0.5us units
de38b95c 4340 * - latencies are in us on gen9/vlv/chv
97e94b22 4341 */
de38b95c 4342 if (INTEL_INFO(dev)->gen >= 9 || IS_VALLEYVIEW(dev))
97e94b22
DL		 4343 latency *= 10;
4344 else if (level > 0)
369a1342
VS		 4345 latency *= 5;
4346
4347 seq_printf(m, "WM%d %u (%u.%u usec)\n",
97e94b22 4348 level, wm[level], latency / 10, latency % 10);
369a1342
VS		 4349 }
4350
4351 drm_modeset_unlock_all(dev);
4352}
4353
4354static int pri_wm_latency_show(struct seq_file *m, void *data)
4355{
4356 struct drm_device *dev = m->private;
97e94b22
DL		 4357 struct drm_i915_private *dev_priv = dev->dev_private;
4358 const uint16_t *latencies;
4359
4360 if (INTEL_INFO(dev)->gen >= 9)
4361 latencies = dev_priv->wm.skl_latency;
4362 else
4363 latencies = to_i915(dev)->wm.pri_latency;
369a1342 4364
97e94b22 4365 wm_latency_show(m, latencies);
369a1342
VS		 4366
4367 return 0;
4368}
4369
4370static int spr_wm_latency_show(struct seq_file *m, void *data)
4371{
4372 struct drm_device *dev = m->private;
97e94b22
DL		 4373 struct drm_i915_private *dev_priv = dev->dev_private;
4374 const uint16_t *latencies;
4375
4376 if (INTEL_INFO(dev)->gen >= 9)
4377 latencies = dev_priv->wm.skl_latency;
4378 else
4379 latencies = to_i915(dev)->wm.spr_latency;
369a1342 4380
97e94b22 4381 wm_latency_show(m, latencies);
369a1342
VS		 4382
4383 return 0;
4384}
4385
4386static int cur_wm_latency_show(struct seq_file *m, void *data)
4387{
4388 struct drm_device *dev = m->private;
97e94b22
DL		 4389 struct drm_i915_private *dev_priv = dev->dev_private;
4390 const uint16_t *latencies;
4391
4392 if (INTEL_INFO(dev)->gen >= 9)
4393 latencies = dev_priv->wm.skl_latency;
4394 else
4395 latencies = to_i915(dev)->wm.cur_latency;
369a1342 4396
97e94b22 4397 wm_latency_show(m, latencies);
369a1342
VS		 4398
4399 return 0;
4400}
4401
4402static int pri_wm_latency_open(struct inode *inode, struct file *file)
4403{
4404 struct drm_device *dev = inode->i_private;
4405
de38b95c 4406 if (INTEL_INFO(dev)->gen < 5)
369a1342
VS		 4407 return -ENODEV;
4408
4409 return single_open(file, pri_wm_latency_show, dev);
4410}
4411
4412static int spr_wm_latency_open(struct inode *inode, struct file *file)
4413{
4414 struct drm_device *dev = inode->i_private;
4415
9ad0257c 4416 if (HAS_GMCH_DISPLAY(dev))
369a1342
VS		 4417 return -ENODEV;
4418
4419 return single_open(file, spr_wm_latency_show, dev);
4420}
4421
4422static int cur_wm_latency_open(struct inode *inode, struct file *file)
4423{
4424 struct drm_device *dev = inode->i_private;
4425
9ad0257c 4426 if (HAS_GMCH_DISPLAY(dev))
369a1342
VS		 4427 return -ENODEV;
4428
4429 return single_open(file, cur_wm_latency_show, dev);
4430}
4431
4432static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
97e94b22 4433 size_t len, loff_t *offp, uint16_t wm[8])
369a1342
VS		 4434{
4435 struct seq_file *m = file->private_data;
4436 struct drm_device *dev = m->private;
97e94b22 4437 uint16_t new[8] = { 0 };
de38b95c 4438 int num_levels;
369a1342
VS		 4439 int level;
4440 int ret;
4441 char tmp[32];
4442
de38b95c
VS		 4443 if (IS_CHERRYVIEW(dev))
4444 num_levels = 3;
4445 else if (IS_VALLEYVIEW(dev))
4446 num_levels = 1;
4447 else
4448 num_levels = ilk_wm_max_level(dev) + 1;
4449
369a1342
VS		 4450 if (len >= sizeof(tmp))
4451 return -EINVAL;
4452
4453 if (copy_from_user(tmp, ubuf, len))
4454 return -EFAULT;
4455
4456 tmp[len] = '\0';
4457
97e94b22
DL		 4458 ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
4459 &new[0], &new[1], &new[2], &new[3],
4460 &new[4], &new[5], &new[6], &new[7]);
369a1342
VS		 4461 if (ret != num_levels)
4462 return -EINVAL;
4463
4464 drm_modeset_lock_all(dev);
4465
4466 for (level = 0; level < num_levels; level++)
4467 wm[level] = new[level];
4468
4469 drm_modeset_unlock_all(dev);
4470
4471 return len;
4472}
4473
4474
4475static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
4476 size_t len, loff_t *offp)
4477{
4478 struct seq_file *m = file->private_data;
4479 struct drm_device *dev = m->private;
97e94b22
DL		 4480 struct drm_i915_private *dev_priv = dev->dev_private;
4481 uint16_t *latencies;
369a1342 4482
97e94b22
DL		 4483 if (INTEL_INFO(dev)->gen >= 9)
4484 latencies = dev_priv->wm.skl_latency;
4485 else
4486 latencies = to_i915(dev)->wm.pri_latency;
4487
4488 return wm_latency_write(file, ubuf, len, offp, latencies);
369a1342
VS		 4489}
4490
4491static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
4492 size_t len, loff_t *offp)
4493{
4494 struct seq_file *m = file->private_data;
4495 struct drm_device *dev = m->private;
97e94b22
DL		 4496 struct drm_i915_private *dev_priv = dev->dev_private;
4497 uint16_t *latencies;
369a1342 4498
97e94b22
DL		 4499 if (INTEL_INFO(dev)->gen >= 9)
4500 latencies = dev_priv->wm.skl_latency;
4501 else
4502 latencies = to_i915(dev)->wm.spr_latency;
4503
4504 return wm_latency_write(file, ubuf, len, offp, latencies);
369a1342
VS		 4505}
4506
4507static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
4508 size_t len, loff_t *offp)
4509{
4510 struct seq_file *m = file->private_data;
4511 struct drm_device *dev = m->private;
97e94b22
DL		 4512 struct drm_i915_private *dev_priv = dev->dev_private;
4513 uint16_t *latencies;
4514
4515 if (INTEL_INFO(dev)->gen >= 9)
4516 latencies = dev_priv->wm.skl_latency;
4517 else
4518 latencies = to_i915(dev)->wm.cur_latency;
369a1342 4519
97e94b22 4520 return wm_latency_write(file, ubuf, len, offp, latencies);
369a1342
VS		 4521}
4522
4523static const struct file_operations i915_pri_wm_latency_fops = {
4524 .owner = THIS_MODULE,
4525 .open = pri_wm_latency_open,
4526 .read = seq_read,
4527 .llseek = seq_lseek,
4528 .release = single_release,
4529 .write = pri_wm_latency_write
4530};
4531
4532static const struct file_operations i915_spr_wm_latency_fops = {
4533 .owner = THIS_MODULE,
4534 .open = spr_wm_latency_open,
4535 .read = seq_read,
4536 .llseek = seq_lseek,
4537 .release = single_release,
4538 .write = spr_wm_latency_write
4539};
4540
4541static const struct file_operations i915_cur_wm_latency_fops = {
4542 .owner = THIS_MODULE,
4543 .open = cur_wm_latency_open,
4544 .read = seq_read,
4545 .llseek = seq_lseek,
4546 .release = single_release,
4547 .write = cur_wm_latency_write
4548};
4549
647416f9
KC		 4550static int
4551i915_wedged_get(void *data, u64 *val)
f3cd474b 4552{
647416f9 4553 struct drm_device *dev = data;
e277a1f8 4554 struct drm_i915_private *dev_priv = dev->dev_private;
f3cd474b 4555
647416f9 4556 *val = atomic_read(&dev_priv->gpu_error.reset_counter);
f3cd474b 4557
647416f9 4558 return 0;
f3cd474b
CW		 4559}
4560
647416f9
KC		 4561static int
4562i915_wedged_set(void *data, u64 val)
f3cd474b 4563{
647416f9 4564 struct drm_device *dev = data;
d46c0517
ID		 4565 struct drm_i915_private *dev_priv = dev->dev_private;
4566
b8d24a06
MK		 4567 /*
4568 * There is no safeguard against this debugfs entry colliding
4569 * with the hangcheck calling same i915_handle_error() in
4570 * parallel, causing an explosion. For now we assume that the
4571 * test harness is responsible enough not to inject gpu hangs
4572 * while it is writing to 'i915_wedged'
4573 */
4574
4575 if (i915_reset_in_progress(&dev_priv->gpu_error))
4576 return -EAGAIN;
4577
d46c0517 4578 intel_runtime_pm_get(dev_priv);
f3cd474b 4579
58174462
MK		 4580 i915_handle_error(dev, val,
4581 "Manually setting wedged to %llu", val);
d46c0517
ID		 4582
4583 intel_runtime_pm_put(dev_priv);
4584
647416f9 4585 return 0;
f3cd474b
CW		 4586}
4587
647416f9
KC		 4588DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
4589 i915_wedged_get, i915_wedged_set,
3a3b4f98 4590 "%llu\n");
f3cd474b 4591
647416f9
KC		 4592static int
4593i915_ring_stop_get(void *data, u64 *val)
e5eb3d63 4594{
647416f9 4595 struct drm_device *dev = data;
e277a1f8 4596 struct drm_i915_private *dev_priv = dev->dev_private;
e5eb3d63 4597
647416f9 4598 *val = dev_priv->gpu_error.stop_rings;
e5eb3d63 4599
647416f9 4600 return 0;
e5eb3d63
DV		 4601}
4602
647416f9
KC		 4603static int
4604i915_ring_stop_set(void *data, u64 val)
e5eb3d63 4605{
647416f9 4606 struct drm_device *dev = data;
e5eb3d63 4607 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 4608 int ret;
e5eb3d63 4609
647416f9 4610 DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val);
e5eb3d63 4611
22bcfc6a
DV		 4612 ret = mutex_lock_interruptible(&dev->struct_mutex);
4613 if (ret)
4614 return ret;
4615
99584db3 4616 dev_priv->gpu_error.stop_rings = val;
e5eb3d63
DV		 4617 mutex_unlock(&dev->struct_mutex);
4618
647416f9 4619 return 0;
e5eb3d63
DV		 4620}
4621
647416f9
KC		 4622DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops,
4623 i915_ring_stop_get, i915_ring_stop_set,
4624 "0x%08llx\n");
d5442303 4625
094f9a54
CW		 4626static int
4627i915_ring_missed_irq_get(void *data, u64 *val)
4628{
4629 struct drm_device *dev = data;
4630 struct drm_i915_private *dev_priv = dev->dev_private;
4631
4632 *val = dev_priv->gpu_error.missed_irq_rings;
4633 return 0;
4634}
4635
4636static int
4637i915_ring_missed_irq_set(void *data, u64 val)
4638{
4639 struct drm_device *dev = data;
4640 struct drm_i915_private *dev_priv = dev->dev_private;
4641 int ret;
4642
4643 /* Lock against concurrent debugfs callers */
4644 ret = mutex_lock_interruptible(&dev->struct_mutex);
4645 if (ret)
4646 return ret;
4647 dev_priv->gpu_error.missed_irq_rings = val;
4648 mutex_unlock(&dev->struct_mutex);
4649
4650 return 0;
4651}
4652
4653DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
4654 i915_ring_missed_irq_get, i915_ring_missed_irq_set,
4655 "0x%08llx\n");
4656
4657static int
4658i915_ring_test_irq_get(void *data, u64 *val)
4659{
4660 struct drm_device *dev = data;
4661 struct drm_i915_private *dev_priv = dev->dev_private;
4662
4663 *val = dev_priv->gpu_error.test_irq_rings;
4664
4665 return 0;
4666}
4667
4668static int
4669i915_ring_test_irq_set(void *data, u64 val)
4670{
4671 struct drm_device *dev = data;
4672 struct drm_i915_private *dev_priv = dev->dev_private;
4673 int ret;
4674
4675 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
4676
4677 /* Lock against concurrent debugfs callers */
4678 ret = mutex_lock_interruptible(&dev->struct_mutex);
4679 if (ret)
4680 return ret;
4681
4682 dev_priv->gpu_error.test_irq_rings = val;
4683 mutex_unlock(&dev->struct_mutex);
4684
4685 return 0;
4686}
4687
4688DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
4689 i915_ring_test_irq_get, i915_ring_test_irq_set,
4690 "0x%08llx\n");
4691
dd624afd
CW		 4692#define DROP_UNBOUND 0x1
4693#define DROP_BOUND 0x2
4694#define DROP_RETIRE 0x4
4695#define DROP_ACTIVE 0x8
4696#define DROP_ALL (DROP_UNBOUND | \
4697 DROP_BOUND | \
4698 DROP_RETIRE | \
4699 DROP_ACTIVE)
647416f9
KC		 4700static int
4701i915_drop_caches_get(void *data, u64 *val)
dd624afd 4702{
647416f9 4703 *val = DROP_ALL;
dd624afd 4704
647416f9 4705 return 0;
dd624afd
CW		 4706}
4707
647416f9
KC		 4708static int
4709i915_drop_caches_set(void *data, u64 val)
dd624afd 4710{
647416f9 4711 struct drm_device *dev = data;
dd624afd 4712 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 4713 int ret;
dd624afd 4714
2f9fe5ff 4715 DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
dd624afd
CW		 4716
4717 /* No need to check and wait for gpu resets, only libdrm auto-restarts
4718 * on ioctls on -EAGAIN. */
4719 ret = mutex_lock_interruptible(&dev->struct_mutex);
4720 if (ret)
4721 return ret;
4722
4723 if (val & DROP_ACTIVE) {
4724 ret = i915_gpu_idle(dev);
4725 if (ret)
4726 goto unlock;
4727 }
4728
4729 if (val & (DROP_RETIRE | DROP_ACTIVE))
4730 i915_gem_retire_requests(dev);
4731
21ab4e74
CW		 4732 if (val & DROP_BOUND)
4733 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND);
4ad72b7f 4734
21ab4e74
CW		 4735 if (val & DROP_UNBOUND)
4736 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND);
dd624afd
CW		 4737
4738unlock:
4739 mutex_unlock(&dev->struct_mutex);
4740
647416f9 4741 return ret;
dd624afd
CW		 4742}
4743
647416f9
KC		 4744DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
4745 i915_drop_caches_get, i915_drop_caches_set,
4746 "0x%08llx\n");
dd624afd 4747
647416f9
KC		 4748static int
4749i915_max_freq_get(void *data, u64 *val)
358733e9 4750{
647416f9 4751 struct drm_device *dev = data;
e277a1f8 4752 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 4753 int ret;
004777cb 4754
daa3afb2 4755 if (INTEL_INFO(dev)->gen < 6)
004777cb
DV		 4756 return -ENODEV;
4757
5c9669ce
TR		 4758 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4759
4fc688ce 4760 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 4761 if (ret)
4762 return ret;
358733e9 4763
7c59a9c1 4764 *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
4fc688ce 4765 mutex_unlock(&dev_priv->rps.hw_lock);
358733e9 4766
647416f9 4767 return 0;
358733e9
JB		 4768}
4769
647416f9
KC		 4770static int
4771i915_max_freq_set(void *data, u64 val)
358733e9 4772{
647416f9 4773 struct drm_device *dev = data;
358733e9 4774 struct drm_i915_private *dev_priv = dev->dev_private;
bc4d91f6 4775 u32 hw_max, hw_min;
647416f9 4776 int ret;
004777cb 4777
daa3afb2 4778 if (INTEL_INFO(dev)->gen < 6)
004777cb 4779 return -ENODEV;
358733e9 4780
5c9669ce
TR		 4781 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4782
647416f9 4783 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
358733e9 4784
4fc688ce 4785 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 4786 if (ret)
4787 return ret;
4788
358733e9
JB		 4789 /*
4790 * Turbo will still be enabled, but won't go above the set value.
4791 */
bc4d91f6 4792 val = intel_freq_opcode(dev_priv, val);
dd0a1aa1 4793
bc4d91f6
AG		 4794 hw_max = dev_priv->rps.max_freq;
4795 hw_min = dev_priv->rps.min_freq;
dd0a1aa1 4796
b39fb297 4797 if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
dd0a1aa1
JM		 4798 mutex_unlock(&dev_priv->rps.hw_lock);
4799 return -EINVAL;
0a073b84
JB		 4800 }
4801
b39fb297 4802 dev_priv->rps.max_freq_softlimit = val;
dd0a1aa1 4803
ffe02b40 4804 intel_set_rps(dev, val);
dd0a1aa1 4805
4fc688ce 4806 mutex_unlock(&dev_priv->rps.hw_lock);
358733e9 4807
647416f9 4808 return 0;
358733e9
JB		 4809}
4810
647416f9
KC		 4811DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
4812 i915_max_freq_get, i915_max_freq_set,
3a3b4f98 4813 "%llu\n");
358733e9 4814
647416f9
KC		 4815static int
4816i915_min_freq_get(void *data, u64 *val)
1523c310 4817{
647416f9 4818 struct drm_device *dev = data;
e277a1f8 4819 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 4820 int ret;
004777cb 4821
daa3afb2 4822 if (INTEL_INFO(dev)->gen < 6)
004777cb
DV		 4823 return -ENODEV;
4824
5c9669ce
TR		 4825 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4826
4fc688ce 4827 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 4828 if (ret)
4829 return ret;
1523c310 4830
7c59a9c1 4831 *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
4fc688ce 4832 mutex_unlock(&dev_priv->rps.hw_lock);
1523c310 4833
647416f9 4834 return 0;
1523c310
JB		 4835}
4836
647416f9
KC		 4837static int
4838i915_min_freq_set(void *data, u64 val)
1523c310 4839{
647416f9 4840 struct drm_device *dev = data;
1523c310 4841 struct drm_i915_private *dev_priv = dev->dev_private;
bc4d91f6 4842 u32 hw_max, hw_min;
647416f9 4843 int ret;
004777cb 4844
daa3afb2 4845 if (INTEL_INFO(dev)->gen < 6)
004777cb 4846 return -ENODEV;
1523c310 4847
5c9669ce
TR		 4848 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4849
647416f9 4850 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
1523c310 4851
4fc688ce 4852 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 4853 if (ret)
4854 return ret;
4855
1523c310
JB		 4856 /*
4857 * Turbo will still be enabled, but won't go below the set value.
4858 */
bc4d91f6 4859 val = intel_freq_opcode(dev_priv, val);
dd0a1aa1 4860
bc4d91f6
AG		 4861 hw_max = dev_priv->rps.max_freq;
4862 hw_min = dev_priv->rps.min_freq;
dd0a1aa1 4863
b39fb297 4864 if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
dd0a1aa1
JM		 4865 mutex_unlock(&dev_priv->rps.hw_lock);
4866 return -EINVAL;
0a073b84 4867 }
dd0a1aa1 4868
b39fb297 4869 dev_priv->rps.min_freq_softlimit = val;
dd0a1aa1 4870
ffe02b40 4871 intel_set_rps(dev, val);
dd0a1aa1 4872
4fc688ce 4873 mutex_unlock(&dev_priv->rps.hw_lock);
1523c310 4874
647416f9 4875 return 0;
1523c310
JB		 4876}
4877
647416f9
KC		 4878DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
4879 i915_min_freq_get, i915_min_freq_set,
3a3b4f98 4880 "%llu\n");
1523c310 4881
647416f9
KC		 4882static int
4883i915_cache_sharing_get(void *data, u64 *val)
07b7ddd9 4884{
647416f9 4885 struct drm_device *dev = data;
e277a1f8 4886 struct drm_i915_private *dev_priv = dev->dev_private;
07b7ddd9 4887 u32 snpcr;
647416f9 4888 int ret;
07b7ddd9 4889
004777cb
DV		 4890 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
4891 return -ENODEV;
4892
22bcfc6a
DV		 4893 ret = mutex_lock_interruptible(&dev->struct_mutex);
4894 if (ret)
4895 return ret;
c8c8fb33 4896 intel_runtime_pm_get(dev_priv);
22bcfc6a 4897
07b7ddd9 4898 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
c8c8fb33
PZ		 4899
4900 intel_runtime_pm_put(dev_priv);
07b7ddd9
JB		 4901 mutex_unlock(&dev_priv->dev->struct_mutex);
4902
647416f9 4903 *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
07b7ddd9 4904
647416f9 4905 return 0;
07b7ddd9
JB		 4906}
4907
647416f9
KC		 4908static int
4909i915_cache_sharing_set(void *data, u64 val)
07b7ddd9 4910{
647416f9 4911 struct drm_device *dev = data;
07b7ddd9 4912 struct drm_i915_private *dev_priv = dev->dev_private;
07b7ddd9 4913 u32 snpcr;
07b7ddd9 4914
004777cb
DV		 4915 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
4916 return -ENODEV;
4917
647416f9 4918 if (val > 3)
07b7ddd9
JB		 4919 return -EINVAL;
4920
c8c8fb33 4921 intel_runtime_pm_get(dev_priv);
647416f9 4922 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
07b7ddd9
JB		 4923
4924 /* Update the cache sharing policy here as well */
4925 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4926 snpcr &= ~GEN6_MBC_SNPCR_MASK;
4927 snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
4928 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
4929
c8c8fb33 4930 intel_runtime_pm_put(dev_priv);
647416f9 4931 return 0;
07b7ddd9
JB		 4932}
4933
647416f9
KC		 4934DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
4935 i915_cache_sharing_get, i915_cache_sharing_set,
4936 "%llu\n");
07b7ddd9 4937
5d39525a
JM		 4938struct sseu_dev_status {
4939 unsigned int slice_total;
4940 unsigned int subslice_total;
4941 unsigned int subslice_per_slice;
4942 unsigned int eu_total;
4943 unsigned int eu_per_subslice;
4944};
4945
4946static void cherryview_sseu_device_status(struct drm_device *dev,
4947 struct sseu_dev_status *stat)
4948{
4949 struct drm_i915_private *dev_priv = dev->dev_private;
0a0b457f 4950 int ss_max = 2;
5d39525a
JM		 4951 int ss;
4952 u32 sig1[ss_max], sig2[ss_max];
4953
4954 sig1[0] = I915_READ(CHV_POWER_SS0_SIG1);
4955 sig1[1] = I915_READ(CHV_POWER_SS1_SIG1);
4956 sig2[0] = I915_READ(CHV_POWER_SS0_SIG2);
4957 sig2[1] = I915_READ(CHV_POWER_SS1_SIG2);
4958
4959 for (ss = 0; ss < ss_max; ss++) {
4960 unsigned int eu_cnt;
4961
4962 if (sig1[ss] & CHV_SS_PG_ENABLE)
4963 /* skip disabled subslice */
4964 continue;
4965
4966 stat->slice_total = 1;
4967 stat->subslice_per_slice++;
4968 eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
4969 ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
4970 ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
4971 ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2);
4972 stat->eu_total += eu_cnt;
4973 stat->eu_per_subslice = max(stat->eu_per_subslice, eu_cnt);
4974 }
4975 stat->subslice_total = stat->subslice_per_slice;
4976}
4977
4978static void gen9_sseu_device_status(struct drm_device *dev,
4979 struct sseu_dev_status *stat)
4980{
4981 struct drm_i915_private *dev_priv = dev->dev_private;
1c046bc1 4982 int s_max = 3, ss_max = 4;
5d39525a
JM		 4983 int s, ss;
4984 u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
4985
1c046bc1
JM		 4986 /* BXT has a single slice and at most 3 subslices. */
4987 if (IS_BROXTON(dev)) {
4988 s_max = 1;
4989 ss_max = 3;
4990 }
4991
4992 for (s = 0; s < s_max; s++) {
4993 s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s));
4994 eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s));
4995 eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s));
4996 }
4997
5d39525a
JM		 4998 eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
4999 GEN9_PGCTL_SSA_EU19_ACK |
5000 GEN9_PGCTL_SSA_EU210_ACK |
5001 GEN9_PGCTL_SSA_EU311_ACK;
5002 eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
5003 GEN9_PGCTL_SSB_EU19_ACK |
5004 GEN9_PGCTL_SSB_EU210_ACK |
5005 GEN9_PGCTL_SSB_EU311_ACK;
5006
5007 for (s = 0; s < s_max; s++) {
1c046bc1
JM		 5008 unsigned int ss_cnt = 0;
5009
5d39525a
JM		 5010 if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
5011 /* skip disabled slice */
5012 continue;
5013
5014 stat->slice_total++;
1c046bc1
JM		 5015
5016 if (IS_SKYLAKE(dev))
5017 ss_cnt = INTEL_INFO(dev)->subslice_per_slice;
5018
5d39525a
JM		 5019 for (ss = 0; ss < ss_max; ss++) {
5020 unsigned int eu_cnt;
5021
1c046bc1
JM		 5022 if (IS_BROXTON(dev) &&
5023 !(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
5024 /* skip disabled subslice */
5025 continue;
5026
5027 if (IS_BROXTON(dev))
5028 ss_cnt++;
5029
5d39525a
JM		 5030 eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
5031 eu_mask[ss%2]);
5032 stat->eu_total += eu_cnt;
5033 stat->eu_per_subslice = max(stat->eu_per_subslice,
5034 eu_cnt);
5035 }
1c046bc1
JM		 5036
5037 stat->subslice_total += ss_cnt;
5038 stat->subslice_per_slice = max(stat->subslice_per_slice,
5039 ss_cnt);
5d39525a
JM		 5040 }
5041}
5042
3873218f
JM		 5043static int i915_sseu_status(struct seq_file *m, void *unused)
5044{
5045 struct drm_info_node *node = (struct drm_info_node *) m->private;
5046 struct drm_device *dev = node->minor->dev;
5d39525a 5047 struct sseu_dev_status stat;
3873218f 5048
5575f03a 5049 if ((INTEL_INFO(dev)->gen < 8) || IS_BROADWELL(dev))
3873218f
JM		 5050 return -ENODEV;
5051
5052 seq_puts(m, "SSEU Device Info\n");
5053 seq_printf(m, " Available Slice Total: %u\n",
5054 INTEL_INFO(dev)->slice_total);
5055 seq_printf(m, " Available Subslice Total: %u\n",
5056 INTEL_INFO(dev)->subslice_total);
5057 seq_printf(m, " Available Subslice Per Slice: %u\n",
5058 INTEL_INFO(dev)->subslice_per_slice);
5059 seq_printf(m, " Available EU Total: %u\n",
5060 INTEL_INFO(dev)->eu_total);
5061 seq_printf(m, " Available EU Per Subslice: %u\n",
5062 INTEL_INFO(dev)->eu_per_subslice);
5063 seq_printf(m, " Has Slice Power Gating: %s\n",
5064 yesno(INTEL_INFO(dev)->has_slice_pg));
5065 seq_printf(m, " Has Subslice Power Gating: %s\n",
5066 yesno(INTEL_INFO(dev)->has_subslice_pg));
5067 seq_printf(m, " Has EU Power Gating: %s\n",
5068 yesno(INTEL_INFO(dev)->has_eu_pg));
5069
7f992aba 5070 seq_puts(m, "SSEU Device Status\n");
5d39525a 5071 memset(&stat, 0, sizeof(stat));
5575f03a 5072 if (IS_CHERRYVIEW(dev)) {
5d39525a 5073 cherryview_sseu_device_status(dev, &stat);
1c046bc1 5074 } else if (INTEL_INFO(dev)->gen >= 9) {
5d39525a 5075 gen9_sseu_device_status(dev, &stat);
7f992aba 5076 }
5d39525a
JM		 5077 seq_printf(m, " Enabled Slice Total: %u\n",
5078 stat.slice_total);
5079 seq_printf(m, " Enabled Subslice Total: %u\n",
5080 stat.subslice_total);
5081 seq_printf(m, " Enabled Subslice Per Slice: %u\n",
5082 stat.subslice_per_slice);
5083 seq_printf(m, " Enabled EU Total: %u\n",
5084 stat.eu_total);
5085 seq_printf(m, " Enabled EU Per Subslice: %u\n",
5086 stat.eu_per_subslice);
7f992aba 5087
3873218f
JM		 5088 return 0;
5089}
5090
6d794d42
BW		 5091static int i915_forcewake_open(struct inode *inode, struct file *file)
5092{
5093 struct drm_device *dev = inode->i_private;
5094 struct drm_i915_private *dev_priv = dev->dev_private;
6d794d42 5095
075edca4 5096 if (INTEL_INFO(dev)->gen < 6)
6d794d42
BW		 5097 return 0;
5098
6daccb0b 5099 intel_runtime_pm_get(dev_priv);
59bad947 5100 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6d794d42
BW		 5101
5102 return 0;
5103}
5104
c43b5634 5105static int i915_forcewake_release(struct inode *inode, struct file *file)
6d794d42
BW		 5106{
5107 struct drm_device *dev = inode->i_private;
5108 struct drm_i915_private *dev_priv = dev->dev_private;
5109
075edca4 5110 if (INTEL_INFO(dev)->gen < 6)
6d794d42
BW		 5111 return 0;
5112
59bad947 5113 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6daccb0b 5114 intel_runtime_pm_put(dev_priv);
6d794d42
BW		 5115
5116 return 0;
5117}
5118
5119static const struct file_operations i915_forcewake_fops = {
5120 .owner = THIS_MODULE,
5121 .open = i915_forcewake_open,
5122 .release = i915_forcewake_release,
5123};
5124
5125static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
5126{
5127 struct drm_device *dev = minor->dev;
5128 struct dentry *ent;
5129
5130 ent = debugfs_create_file("i915_forcewake_user",
8eb57294 5131 S_IRUSR,
6d794d42
BW		 5132 root, dev,
5133 &i915_forcewake_fops);
f3c5fe97
WY		 5134 if (!ent)
5135 return -ENOMEM;
6d794d42 5136
8eb57294 5137 return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
6d794d42
BW		 5138}
5139
6a9c308d
DV		 5140static int i915_debugfs_create(struct dentry *root,
5141 struct drm_minor *minor,
5142 const char *name,
5143 const struct file_operations *fops)
07b7ddd9
JB		 5144{
5145 struct drm_device *dev = minor->dev;
5146 struct dentry *ent;
5147
6a9c308d 5148 ent = debugfs_create_file(name,
07b7ddd9
JB		 5149 S_IRUGO | S_IWUSR,
5150 root, dev,
6a9c308d 5151 fops);
f3c5fe97
WY		 5152 if (!ent)
5153 return -ENOMEM;
07b7ddd9 5154
6a9c308d 5155 return drm_add_fake_info_node(minor, ent, fops);
07b7ddd9
JB		 5156}
5157
06c5bf8c 5158static const struct drm_info_list i915_debugfs_list[] = {
311bd68e 5159 {"i915_capabilities", i915_capabilities, 0},
73aa808f 5160 {"i915_gem_objects", i915_gem_object_info, 0},
08c18323 5161 {"i915_gem_gtt", i915_gem_gtt_info, 0},
1b50247a 5162 {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
433e12f7 5163 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
433e12f7 5164 {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
6d2b8885 5165 {"i915_gem_stolen", i915_gem_stolen_list_info },
4e5359cd 5166 {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
2017263e
BG		 5167 {"i915_gem_request", i915_gem_request_info, 0},
5168 {"i915_gem_seqno", i915_gem_seqno_info, 0},
a6172a80 5169 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
2017263e 5170 {"i915_gem_interrupt", i915_interrupt_info, 0},
1ec14ad3
CW		 5171 {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
5172 {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
5173 {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
9010ebfd 5174 {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
493018dc 5175 {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0},
8b417c26 5176 {"i915_guc_info", i915_guc_info, 0},
fdf5d357 5177 {"i915_guc_load_status", i915_guc_load_status_info, 0},
4c7e77fc 5178 {"i915_guc_log_dump", i915_guc_log_dump, 0},
adb4bd12 5179 {"i915_frequency_info", i915_frequency_info, 0},
f654449a 5180 {"i915_hangcheck_info", i915_hangcheck_info, 0},
f97108d1 5181 {"i915_drpc_info", i915_drpc_info, 0},
7648fa99 5182 {"i915_emon_status", i915_emon_status, 0},
23b2f8bb 5183 {"i915_ring_freq_table", i915_ring_freq_table, 0},
9a851789 5184 {"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0},
b5e50c3f 5185 {"i915_fbc_status", i915_fbc_status, 0},
92d44621 5186 {"i915_ips_status", i915_ips_status, 0},
4a9bef37 5187 {"i915_sr_status", i915_sr_status, 0},
44834a67 5188 {"i915_opregion", i915_opregion, 0},
37811fcc 5189 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
e76d3630 5190 {"i915_context_status", i915_context_status, 0},
c0ab1ae9 5191 {"i915_dump_lrc", i915_dump_lrc, 0},
4ba70e44 5192 {"i915_execlists", i915_execlists, 0},
f65367b5 5193 {"i915_forcewake_domains", i915_forcewake_domains, 0},
ea16a3cd 5194 {"i915_swizzle_info", i915_swizzle_info, 0},
3cf17fc5 5195 {"i915_ppgtt_info", i915_ppgtt_info, 0},
63573eb7 5196 {"i915_llc", i915_llc, 0},
e91fd8c6 5197 {"i915_edp_psr_status", i915_edp_psr_status, 0},
d2e216d0 5198 {"i915_sink_crc_eDP1", i915_sink_crc, 0},
ec013e7f 5199 {"i915_energy_uJ", i915_energy_uJ, 0},
6455c870 5200 {"i915_runtime_pm_status", i915_runtime_pm_status, 0},
1da51581 5201 {"i915_power_domain_info", i915_power_domain_info, 0},
53f5e3ca 5202 {"i915_display_info", i915_display_info, 0},
e04934cf 5203 {"i915_semaphore_status", i915_semaphore_status, 0},
728e29d7 5204 {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
11bed958 5205 {"i915_dp_mst_info", i915_dp_mst_info, 0},
1ed1ef9d 5206 {"i915_wa_registers", i915_wa_registers, 0},
c5511e44 5207 {"i915_ddb_info", i915_ddb_info, 0},
3873218f 5208 {"i915_sseu_status", i915_sseu_status, 0},
a54746e3 5209 {"i915_drrs_status", i915_drrs_status, 0},
1854d5ca 5210 {"i915_rps_boost_info", i915_rps_boost_info, 0},
2017263e 5211};
27c202ad 5212#define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
2017263e 5213
06c5bf8c 5214static const struct i915_debugfs_files {
34b9674c
DV		 5215 const char *name;
5216 const struct file_operations *fops;
5217} i915_debugfs_files[] = {
5218 {"i915_wedged", &i915_wedged_fops},
5219 {"i915_max_freq", &i915_max_freq_fops},
5220 {"i915_min_freq", &i915_min_freq_fops},
5221 {"i915_cache_sharing", &i915_cache_sharing_fops},
5222 {"i915_ring_stop", &i915_ring_stop_fops},
094f9a54
CW		 5223 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
5224 {"i915_ring_test_irq", &i915_ring_test_irq_fops},
34b9674c
DV		 5225 {"i915_gem_drop_caches", &i915_drop_caches_fops},
5226 {"i915_error_state", &i915_error_state_fops},
5227 {"i915_next_seqno", &i915_next_seqno_fops},
bd9db02f 5228 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
369a1342
VS		 5229 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
5230 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
5231 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
da46f936 5232 {"i915_fbc_false_color", &i915_fbc_fc_fops},
eb3394fa
TP		 5233 {"i915_dp_test_data", &i915_displayport_test_data_fops},
5234 {"i915_dp_test_type", &i915_displayport_test_type_fops},
5235 {"i915_dp_test_active", &i915_displayport_test_active_fops}
34b9674c
DV		 5236};
5237
07144428
DL		 5238void intel_display_crc_init(struct drm_device *dev)
5239{
5240 struct drm_i915_private *dev_priv = dev->dev_private;
b378360e 5241 enum pipe pipe;
07144428 5242
055e393f 5243 for_each_pipe(dev_priv, pipe) {
b378360e 5244 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
07144428 5245
d538bbdf
DL		 5246 pipe_crc->opened = false;
5247 spin_lock_init(&pipe_crc->lock);
07144428
DL		 5248 init_waitqueue_head(&pipe_crc->wq);
5249 }
5250}
5251
27c202ad 5252int i915_debugfs_init(struct drm_minor *minor)
2017263e 5253{
34b9674c 5254 int ret, i;
f3cd474b 5255
6d794d42 5256 ret = i915_forcewake_create(minor->debugfs_root, minor);
358733e9
JB		 5257 if (ret)
5258 return ret;
6a9c308d 5259
07144428
DL		 5260 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5261 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
5262 if (ret)
5263 return ret;
5264 }
5265
34b9674c
DV		 5266 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5267 ret = i915_debugfs_create(minor->debugfs_root, minor,
5268 i915_debugfs_files[i].name,
5269 i915_debugfs_files[i].fops);
5270 if (ret)
5271 return ret;
5272 }
40633219 5273
27c202ad
BG		 5274 return drm_debugfs_create_files(i915_debugfs_list,
5275 I915_DEBUGFS_ENTRIES,
2017263e
BG		 5276 minor->debugfs_root, minor);
5277}
5278
27c202ad 5279void i915_debugfs_cleanup(struct drm_minor *minor)
2017263e 5280{
34b9674c
DV		 5281 int i;
5282
27c202ad
BG		 5283 drm_debugfs_remove_files(i915_debugfs_list,
5284 I915_DEBUGFS_ENTRIES, minor);
07144428 5285
6d794d42
BW		 5286 drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
5287 1, minor);
07144428 5288
e309a997 5289 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
07144428
DL		 5290 struct drm_info_list *info_list =
5291 (struct drm_info_list *)&i915_pipe_crc_data[i];
5292
5293 drm_debugfs_remove_files(info_list, 1, minor);
5294 }
5295
34b9674c
DV		 5296 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5297 struct drm_info_list *info_list =
5298 (struct drm_info_list *) i915_debugfs_files[i].fops;
5299
5300 drm_debugfs_remove_files(info_list, 1, minor);
5301 }
2017263e 5302}
aa7471d2
JN		 5303
5304struct dpcd_block {
5305 /* DPCD dump start address. */
5306 unsigned int offset;
5307 /* DPCD dump end address, inclusive. If unset, .size will be used. */
5308 unsigned int end;
5309 /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */
5310 size_t size;
5311 /* Only valid for eDP. */
5312 bool edp;
5313};
5314
5315static const struct dpcd_block i915_dpcd_debug[] = {
5316 { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE },
5317 { .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS },
5318 { .offset = DP_DOWNSTREAM_PORT_0, .size = 16 },
5319 { .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET },
5320 { .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 },
5321 { .offset = DP_SET_POWER },
5322 { .offset = DP_EDP_DPCD_REV },
5323 { .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 },
5324 { .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB },
5325 { .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET },
5326};
5327
5328static int i915_dpcd_show(struct seq_file *m, void *data)
5329{
5330 struct drm_connector *connector = m->private;
5331 struct intel_dp *intel_dp =
5332 enc_to_intel_dp(&intel_attached_encoder(connector)->base);
5333 uint8_t buf[16];
5334 ssize_t err;
5335 int i;
5336
5c1a8875
MK		 5337 if (connector->status != connector_status_connected)
5338 return -ENODEV;
5339
aa7471d2
JN		 5340 for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) {
5341 const struct dpcd_block *b = &i915_dpcd_debug[i];
5342 size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1);
5343
5344 if (b->edp &&
5345 connector->connector_type != DRM_MODE_CONNECTOR_eDP)
5346 continue;
5347
5348 /* low tech for now */
5349 if (WARN_ON(size > sizeof(buf)))
5350 continue;
5351
5352 err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size);
5353 if (err <= 0) {
5354 DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n",
5355 size, b->offset, err);
5356 continue;
5357 }
5358
5359 seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf);
b3f9d7d7 5360 }
aa7471d2
JN		 5361
5362 return 0;
5363}
5364
5365static int i915_dpcd_open(struct inode *inode, struct file *file)
5366{
5367 return single_open(file, i915_dpcd_show, inode->i_private);
5368}
5369
5370static const struct file_operations i915_dpcd_fops = {
5371 .owner = THIS_MODULE,
5372 .open = i915_dpcd_open,
5373 .read = seq_read,
5374 .llseek = seq_lseek,
5375 .release = single_release,
5376};
5377
5378/**
5379 * i915_debugfs_connector_add - add i915 specific connector debugfs files
5380 * @connector: pointer to a registered drm_connector
5381 *
5382 * Cleanup will be done by drm_connector_unregister() through a call to
5383 * drm_debugfs_connector_remove().
5384 *
5385 * Returns 0 on success, negative error codes on error.
5386 */
5387int i915_debugfs_connector_add(struct drm_connector *connector)
5388{
5389 struct dentry *root = connector->debugfs_entry;
5390
5391 /* The connector must have been registered beforehands. */
5392 if (!root)
5393 return -ENODEV;
5394
5395 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
5396 connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5397 debugfs_create_file("i915_dpcd", S_IRUGO, root, connector,
5398 &i915_dpcd_fops);
5399
5400 return 0;
5401}
Linux kernel - Deliverables
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