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drm/i915: Introduce i915_gem_set_seqno()
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_debugfs.c
CommitLineData
2017263e
BG		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 *
27 */
28
29#include <linux/seq_file.h>
f3cd474b 30#include <linux/debugfs.h>
5a0e3ad6 31#include <linux/slab.h>
2d1a8a48 32#include <linux/export.h>
760285e7 33#include <drm/drmP.h>
4e5359cd 34#include "intel_drv.h"
e5c65260 35#include "intel_ringbuffer.h"
760285e7 36#include <drm/i915_drm.h>
2017263e
BG		 37#include "i915_drv.h"
38
39#define DRM_I915_RING_DEBUG 1
40
41
42#if defined(CONFIG_DEBUG_FS)
43
f13d3f73 44enum {
69dc4987 45 ACTIVE_LIST,
f13d3f73 46 INACTIVE_LIST,
d21d5975 47 PINNED_LIST,
f13d3f73 48};
2017263e 49
70d39fe4
CW		 50static const char *yesno(int v)
51{
52 return v ? "yes" : "no";
53}
54
55static int i915_capabilities(struct seq_file *m, void *data)
56{
57 struct drm_info_node *node = (struct drm_info_node *) m->private;
58 struct drm_device *dev = node->minor->dev;
59 const struct intel_device_info *info = INTEL_INFO(dev);
60
61 seq_printf(m, "gen: %d\n", info->gen);
03d00ac5 62 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
c96ea64e
DV		 63#define DEV_INFO_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
64#define DEV_INFO_SEP ;
65 DEV_INFO_FLAGS;
66#undef DEV_INFO_FLAG
67#undef DEV_INFO_SEP
70d39fe4
CW		 68
69 return 0;
70}
2017263e 71
05394f39 72static const char *get_pin_flag(struct drm_i915_gem_object *obj)
a6172a80 73{
05394f39 74 if (obj->user_pin_count > 0)
a6172a80 75 return "P";
05394f39 76 else if (obj->pin_count > 0)
a6172a80
CW		 77 return "p";
78 else
79 return " ";
80}
81
05394f39 82static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
a6172a80 83{
0206e353
AJ		 84 switch (obj->tiling_mode) {
85 default:
86 case I915_TILING_NONE: return " ";
87 case I915_TILING_X: return "X";
88 case I915_TILING_Y: return "Y";
89 }
a6172a80
CW		 90}
91
93dfb40c 92static const char *cache_level_str(int type)
08c18323
CW		 93{
94 switch (type) {
93dfb40c
CW		 95 case I915_CACHE_NONE: return " uncached";
96 case I915_CACHE_LLC: return " snooped (LLC)";
97 case I915_CACHE_LLC_MLC: return " snooped (LLC+MLC)";
08c18323
CW		 98 default: return "";
99 }
100}
101
37811fcc
CW		 102static void
103describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
104{
04b97b34 105 seq_printf(m, "%p: %s%s %8zdKiB %02x %02x %d %d %d%s%s%s",
37811fcc
CW		 106 &obj->base,
107 get_pin_flag(obj),
108 get_tiling_flag(obj),
a05a5862 109 obj->base.size / 1024,
37811fcc
CW		 110 obj->base.read_domains,
111 obj->base.write_domain,
0201f1ec
CW		 112 obj->last_read_seqno,
113 obj->last_write_seqno,
caea7476 114 obj->last_fenced_seqno,
93dfb40c 115 cache_level_str(obj->cache_level),
37811fcc
CW		 116 obj->dirty ? " dirty" : "",
117 obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
118 if (obj->base.name)
119 seq_printf(m, " (name: %d)", obj->base.name);
c110a6d7
CW		 120 if (obj->pin_count)
121 seq_printf(m, " (pinned x %d)", obj->pin_count);
37811fcc
CW		 122 if (obj->fence_reg != I915_FENCE_REG_NONE)
123 seq_printf(m, " (fence: %d)", obj->fence_reg);
124 if (obj->gtt_space != NULL)
a00b10c3
CW		 125 seq_printf(m, " (gtt offset: %08x, size: %08x)",
126 obj->gtt_offset, (unsigned int)obj->gtt_space->size);
c1ad11fc
CW		 127 if (obj->stolen)
128 seq_printf(m, " (stolen: %08lx)", obj->stolen->start);
6299f992
CW		 129 if (obj->pin_mappable || obj->fault_mappable) {
130 char s[3], *t = s;
131 if (obj->pin_mappable)
132 *t++ = 'p';
133 if (obj->fault_mappable)
134 *t++ = 'f';
135 *t = '\0';
136 seq_printf(m, " (%s mappable)", s);
137 }
69dc4987
CW		 138 if (obj->ring != NULL)
139 seq_printf(m, " (%s)", obj->ring->name);
37811fcc
CW		 140}
141
433e12f7 142static int i915_gem_object_list_info(struct seq_file *m, void *data)
2017263e
BG		 143{
144 struct drm_info_node *node = (struct drm_info_node *) m->private;
433e12f7
BG		 145 uintptr_t list = (uintptr_t) node->info_ent->data;
146 struct list_head *head;
2017263e
BG		 147 struct drm_device *dev = node->minor->dev;
148 drm_i915_private_t *dev_priv = dev->dev_private;
05394f39 149 struct drm_i915_gem_object *obj;
8f2480fb
CW		 150 size_t total_obj_size, total_gtt_size;
151 int count, ret;
de227ef0
CW		 152
153 ret = mutex_lock_interruptible(&dev->struct_mutex);
154 if (ret)
155 return ret;
2017263e 156
433e12f7
BG		 157 switch (list) {
158 case ACTIVE_LIST:
159 seq_printf(m, "Active:\n");
69dc4987 160 head = &dev_priv->mm.active_list;
433e12f7
BG		 161 break;
162 case INACTIVE_LIST:
a17458fc 163 seq_printf(m, "Inactive:\n");
433e12f7
BG		 164 head = &dev_priv->mm.inactive_list;
165 break;
433e12f7 166 default:
de227ef0
CW		 167 mutex_unlock(&dev->struct_mutex);
168 return -EINVAL;
2017263e 169 }
2017263e 170
8f2480fb 171 total_obj_size = total_gtt_size = count = 0;
05394f39 172 list_for_each_entry(obj, head, mm_list) {
37811fcc 173 seq_printf(m, " ");
05394f39 174 describe_obj(m, obj);
f4ceda89 175 seq_printf(m, "\n");
05394f39
CW		 176 total_obj_size += obj->base.size;
177 total_gtt_size += obj->gtt_space->size;
8f2480fb 178 count++;
2017263e 179 }
de227ef0 180 mutex_unlock(&dev->struct_mutex);
5e118f41 181
8f2480fb
CW		 182 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
183 count, total_obj_size, total_gtt_size);
2017263e
BG		 184 return 0;
185}
186
6299f992
CW		 187#define count_objects(list, member) do { \
188 list_for_each_entry(obj, list, member) { \
189 size += obj->gtt_space->size; \
190 ++count; \
191 if (obj->map_and_fenceable) { \
192 mappable_size += obj->gtt_space->size; \
193 ++mappable_count; \
194 } \
195 } \
0206e353 196} while (0)
6299f992 197
73aa808f
CW		 198static int i915_gem_object_info(struct seq_file *m, void* data)
199{
200 struct drm_info_node *node = (struct drm_info_node *) m->private;
201 struct drm_device *dev = node->minor->dev;
202 struct drm_i915_private *dev_priv = dev->dev_private;
b7abb714
CW		 203 u32 count, mappable_count, purgeable_count;
204 size_t size, mappable_size, purgeable_size;
6299f992 205 struct drm_i915_gem_object *obj;
73aa808f
CW		 206 int ret;
207
208 ret = mutex_lock_interruptible(&dev->struct_mutex);
209 if (ret)
210 return ret;
211
6299f992
CW		 212 seq_printf(m, "%u objects, %zu bytes\n",
213 dev_priv->mm.object_count,
214 dev_priv->mm.object_memory);
215
216 size = count = mappable_size = mappable_count = 0;
6c085a72 217 count_objects(&dev_priv->mm.bound_list, gtt_list);
6299f992
CW		 218 seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n",
219 count, mappable_count, size, mappable_size);
220
221 size = count = mappable_size = mappable_count = 0;
222 count_objects(&dev_priv->mm.active_list, mm_list);
6299f992
CW		 223 seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n",
224 count, mappable_count, size, mappable_size);
225
6299f992
CW		 226 size = count = mappable_size = mappable_count = 0;
227 count_objects(&dev_priv->mm.inactive_list, mm_list);
228 seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n",
229 count, mappable_count, size, mappable_size);
230
b7abb714
CW		 231 size = count = purgeable_size = purgeable_count = 0;
232 list_for_each_entry(obj, &dev_priv->mm.unbound_list, gtt_list) {
6c085a72 233 size += obj->base.size, ++count;
b7abb714
CW		 234 if (obj->madv == I915_MADV_DONTNEED)
235 purgeable_size += obj->base.size, ++purgeable_count;
236 }
6c085a72
CW		 237 seq_printf(m, "%u unbound objects, %zu bytes\n", count, size);
238
6299f992 239 size = count = mappable_size = mappable_count = 0;
6c085a72 240 list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) {
6299f992
CW		 241 if (obj->fault_mappable) {
242 size += obj->gtt_space->size;
243 ++count;
244 }
245 if (obj->pin_mappable) {
246 mappable_size += obj->gtt_space->size;
247 ++mappable_count;
248 }
b7abb714
CW		 249 if (obj->madv == I915_MADV_DONTNEED) {
250 purgeable_size += obj->base.size;
251 ++purgeable_count;
252 }
6299f992 253 }
b7abb714
CW		 254 seq_printf(m, "%u purgeable objects, %zu bytes\n",
255 purgeable_count, purgeable_size);
6299f992
CW		 256 seq_printf(m, "%u pinned mappable objects, %zu bytes\n",
257 mappable_count, mappable_size);
258 seq_printf(m, "%u fault mappable objects, %zu bytes\n",
259 count, size);
260
261 seq_printf(m, "%zu [%zu] gtt total\n",
262 dev_priv->mm.gtt_total, dev_priv->mm.mappable_gtt_total);
73aa808f
CW		 263
264 mutex_unlock(&dev->struct_mutex);
265
266 return 0;
267}
268
08c18323
CW		 269static int i915_gem_gtt_info(struct seq_file *m, void* data)
270{
271 struct drm_info_node *node = (struct drm_info_node *) m->private;
272 struct drm_device *dev = node->minor->dev;
1b50247a 273 uintptr_t list = (uintptr_t) node->info_ent->data;
08c18323
CW		 274 struct drm_i915_private *dev_priv = dev->dev_private;
275 struct drm_i915_gem_object *obj;
276 size_t total_obj_size, total_gtt_size;
277 int count, ret;
278
279 ret = mutex_lock_interruptible(&dev->struct_mutex);
280 if (ret)
281 return ret;
282
283 total_obj_size = total_gtt_size = count = 0;
6c085a72 284 list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) {
1b50247a
CW		 285 if (list == PINNED_LIST && obj->pin_count == 0)
286 continue;
287
08c18323
CW		 288 seq_printf(m, " ");
289 describe_obj(m, obj);
290 seq_printf(m, "\n");
291 total_obj_size += obj->base.size;
292 total_gtt_size += obj->gtt_space->size;
293 count++;
294 }
295
296 mutex_unlock(&dev->struct_mutex);
297
298 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
299 count, total_obj_size, total_gtt_size);
300
301 return 0;
302}
303
4e5359cd
SF		 304static int i915_gem_pageflip_info(struct seq_file *m, void *data)
305{
306 struct drm_info_node *node = (struct drm_info_node *) m->private;
307 struct drm_device *dev = node->minor->dev;
308 unsigned long flags;
309 struct intel_crtc *crtc;
310
311 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
9db4a9c7
JB		 312 const char pipe = pipe_name(crtc->pipe);
313 const char plane = plane_name(crtc->plane);
4e5359cd
SF		 314 struct intel_unpin_work *work;
315
316 spin_lock_irqsave(&dev->event_lock, flags);
317 work = crtc->unpin_work;
318 if (work == NULL) {
9db4a9c7 319 seq_printf(m, "No flip due on pipe %c (plane %c)\n",
4e5359cd
SF		 320 pipe, plane);
321 } else {
322 if (!work->pending) {
9db4a9c7 323 seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
4e5359cd
SF		 324 pipe, plane);
325 } else {
9db4a9c7 326 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
4e5359cd
SF		 327 pipe, plane);
328 }
329 if (work->enable_stall_check)
330 seq_printf(m, "Stall check enabled, ");
331 else
332 seq_printf(m, "Stall check waiting for page flip ioctl, ");
333 seq_printf(m, "%d prepares\n", work->pending);
334
335 if (work->old_fb_obj) {
05394f39
CW		 336 struct drm_i915_gem_object *obj = work->old_fb_obj;
337 if (obj)
338 seq_printf(m, "Old framebuffer gtt_offset 0x%08x\n", obj->gtt_offset);
4e5359cd
SF		 339 }
340 if (work->pending_flip_obj) {
05394f39
CW		 341 struct drm_i915_gem_object *obj = work->pending_flip_obj;
342 if (obj)
343 seq_printf(m, "New framebuffer gtt_offset 0x%08x\n", obj->gtt_offset);
4e5359cd
SF		 344 }
345 }
346 spin_unlock_irqrestore(&dev->event_lock, flags);
347 }
348
349 return 0;
350}
351
2017263e
BG		 352static int i915_gem_request_info(struct seq_file *m, void *data)
353{
354 struct drm_info_node *node = (struct drm_info_node *) m->private;
355 struct drm_device *dev = node->minor->dev;
356 drm_i915_private_t *dev_priv = dev->dev_private;
a2c7f6fd 357 struct intel_ring_buffer *ring;
2017263e 358 struct drm_i915_gem_request *gem_request;
a2c7f6fd 359 int ret, count, i;
de227ef0
CW		 360
361 ret = mutex_lock_interruptible(&dev->struct_mutex);
362 if (ret)
363 return ret;
2017263e 364
c2c347a9 365 count = 0;
a2c7f6fd
CW		 366 for_each_ring(ring, dev_priv, i) {
367 if (list_empty(&ring->request_list))
368 continue;
369
370 seq_printf(m, "%s requests:\n", ring->name);
c2c347a9 371 list_for_each_entry(gem_request,
a2c7f6fd 372 &ring->request_list,
c2c347a9
CW		 373 list) {
374 seq_printf(m, " %d @ %d\n",
375 gem_request->seqno,
376 (int) (jiffies - gem_request->emitted_jiffies));
377 }
378 count++;
2017263e 379 }
de227ef0
CW		 380 mutex_unlock(&dev->struct_mutex);
381
c2c347a9
CW		 382 if (count == 0)
383 seq_printf(m, "No requests\n");
384
2017263e
BG		 385 return 0;
386}
387
b2223497
CW		 388static void i915_ring_seqno_info(struct seq_file *m,
389 struct intel_ring_buffer *ring)
390{
391 if (ring->get_seqno) {
43a7b924 392 seq_printf(m, "Current sequence (%s): %u\n",
b2eadbc8 393 ring->name, ring->get_seqno(ring, false));
b2223497
CW		 394 }
395}
396
2017263e
BG		 397static int i915_gem_seqno_info(struct seq_file *m, void *data)
398{
399 struct drm_info_node *node = (struct drm_info_node *) m->private;
400 struct drm_device *dev = node->minor->dev;
401 drm_i915_private_t *dev_priv = dev->dev_private;
a2c7f6fd 402 struct intel_ring_buffer *ring;
1ec14ad3 403 int ret, i;
de227ef0
CW		 404
405 ret = mutex_lock_interruptible(&dev->struct_mutex);
406 if (ret)
407 return ret;
2017263e 408
a2c7f6fd
CW		 409 for_each_ring(ring, dev_priv, i)
410 i915_ring_seqno_info(m, ring);
de227ef0
CW		 411
412 mutex_unlock(&dev->struct_mutex);
413
2017263e
BG		 414 return 0;
415}
416
417
418static int i915_interrupt_info(struct seq_file *m, void *data)
419{
420 struct drm_info_node *node = (struct drm_info_node *) m->private;
421 struct drm_device *dev = node->minor->dev;
422 drm_i915_private_t *dev_priv = dev->dev_private;
a2c7f6fd 423 struct intel_ring_buffer *ring;
9db4a9c7 424 int ret, i, pipe;
de227ef0
CW		 425
426 ret = mutex_lock_interruptible(&dev->struct_mutex);
427 if (ret)
428 return ret;
2017263e 429
7e231dbe
JB		 430 if (IS_VALLEYVIEW(dev)) {
431 seq_printf(m, "Display IER:\t%08x\n",
432 I915_READ(VLV_IER));
433 seq_printf(m, "Display IIR:\t%08x\n",
434 I915_READ(VLV_IIR));
435 seq_printf(m, "Display IIR_RW:\t%08x\n",
436 I915_READ(VLV_IIR_RW));
437 seq_printf(m, "Display IMR:\t%08x\n",
438 I915_READ(VLV_IMR));
439 for_each_pipe(pipe)
440 seq_printf(m, "Pipe %c stat:\t%08x\n",
441 pipe_name(pipe),
442 I915_READ(PIPESTAT(pipe)));
443
444 seq_printf(m, "Master IER:\t%08x\n",
445 I915_READ(VLV_MASTER_IER));
446
447 seq_printf(m, "Render IER:\t%08x\n",
448 I915_READ(GTIER));
449 seq_printf(m, "Render IIR:\t%08x\n",
450 I915_READ(GTIIR));
451 seq_printf(m, "Render IMR:\t%08x\n",
452 I915_READ(GTIMR));
453
454 seq_printf(m, "PM IER:\t\t%08x\n",
455 I915_READ(GEN6_PMIER));
456 seq_printf(m, "PM IIR:\t\t%08x\n",
457 I915_READ(GEN6_PMIIR));
458 seq_printf(m, "PM IMR:\t\t%08x\n",
459 I915_READ(GEN6_PMIMR));
460
461 seq_printf(m, "Port hotplug:\t%08x\n",
462 I915_READ(PORT_HOTPLUG_EN));
463 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
464 I915_READ(VLV_DPFLIPSTAT));
465 seq_printf(m, "DPINVGTT:\t%08x\n",
466 I915_READ(DPINVGTT));
467
468 } else if (!HAS_PCH_SPLIT(dev)) {
5f6a1695
ZW		 469 seq_printf(m, "Interrupt enable: %08x\n",
470 I915_READ(IER));
471 seq_printf(m, "Interrupt identity: %08x\n",
472 I915_READ(IIR));
473 seq_printf(m, "Interrupt mask: %08x\n",
474 I915_READ(IMR));
9db4a9c7
JB		 475 for_each_pipe(pipe)
476 seq_printf(m, "Pipe %c stat: %08x\n",
477 pipe_name(pipe),
478 I915_READ(PIPESTAT(pipe)));
5f6a1695
ZW		 479 } else {
480 seq_printf(m, "North Display Interrupt enable: %08x\n",
481 I915_READ(DEIER));
482 seq_printf(m, "North Display Interrupt identity: %08x\n",
483 I915_READ(DEIIR));
484 seq_printf(m, "North Display Interrupt mask: %08x\n",
485 I915_READ(DEIMR));
486 seq_printf(m, "South Display Interrupt enable: %08x\n",
487 I915_READ(SDEIER));
488 seq_printf(m, "South Display Interrupt identity: %08x\n",
489 I915_READ(SDEIIR));
490 seq_printf(m, "South Display Interrupt mask: %08x\n",
491 I915_READ(SDEIMR));
492 seq_printf(m, "Graphics Interrupt enable: %08x\n",
493 I915_READ(GTIER));
494 seq_printf(m, "Graphics Interrupt identity: %08x\n",
495 I915_READ(GTIIR));
496 seq_printf(m, "Graphics Interrupt mask: %08x\n",
497 I915_READ(GTIMR));
498 }
2017263e
BG		 499 seq_printf(m, "Interrupts received: %d\n",
500 atomic_read(&dev_priv->irq_received));
a2c7f6fd 501 for_each_ring(ring, dev_priv, i) {
da64c6fc 502 if (IS_GEN6(dev) || IS_GEN7(dev)) {
a2c7f6fd
CW		 503 seq_printf(m,
504 "Graphics Interrupt mask (%s): %08x\n",
505 ring->name, I915_READ_IMR(ring));
9862e600 506 }
a2c7f6fd 507 i915_ring_seqno_info(m, ring);
9862e600 508 }
de227ef0
CW		 509 mutex_unlock(&dev->struct_mutex);
510
2017263e
BG		 511 return 0;
512}
513
a6172a80
CW		 514static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
515{
516 struct drm_info_node *node = (struct drm_info_node *) m->private;
517 struct drm_device *dev = node->minor->dev;
518 drm_i915_private_t *dev_priv = dev->dev_private;
de227ef0
CW		 519 int i, ret;
520
521 ret = mutex_lock_interruptible(&dev->struct_mutex);
522 if (ret)
523 return ret;
a6172a80
CW		 524
525 seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
526 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
527 for (i = 0; i < dev_priv->num_fence_regs; i++) {
05394f39 528 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
a6172a80 529
6c085a72
CW		 530 seq_printf(m, "Fence %d, pin count = %d, object = ",
531 i, dev_priv->fence_regs[i].pin_count);
c2c347a9
CW		 532 if (obj == NULL)
533 seq_printf(m, "unused");
534 else
05394f39 535 describe_obj(m, obj);
c2c347a9 536 seq_printf(m, "\n");
a6172a80
CW		 537 }
538
05394f39 539 mutex_unlock(&dev->struct_mutex);
a6172a80
CW		 540 return 0;
541}
542
2017263e
BG		 543static int i915_hws_info(struct seq_file *m, void *data)
544{
545 struct drm_info_node *node = (struct drm_info_node *) m->private;
546 struct drm_device *dev = node->minor->dev;
547 drm_i915_private_t *dev_priv = dev->dev_private;
4066c0ae 548 struct intel_ring_buffer *ring;
1a240d4d 549 const u32 *hws;
4066c0ae
CW		 550 int i;
551
1ec14ad3 552 ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
1a240d4d 553 hws = ring->status_page.page_addr;
2017263e
BG		 554 if (hws == NULL)
555 return 0;
556
557 for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
558 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
559 i * 4,
560 hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
561 }
562 return 0;
563}
564
e5c65260
CW		 565static const char *ring_str(int ring)
566{
567 switch (ring) {
96154f2f
DV		 568 case RCS: return "render";
569 case VCS: return "bsd";
570 case BCS: return "blt";
e5c65260
CW		 571 default: return "";
572 }
573}
574
9df30794
CW		 575static const char *pin_flag(int pinned)
576{
577 if (pinned > 0)
578 return " P";
579 else if (pinned < 0)
580 return " p";
581 else
582 return "";
583}
584
585static const char *tiling_flag(int tiling)
586{
587 switch (tiling) {
588 default:
589 case I915_TILING_NONE: return "";
590 case I915_TILING_X: return " X";
591 case I915_TILING_Y: return " Y";
592 }
593}
594
595static const char *dirty_flag(int dirty)
596{
597 return dirty ? " dirty" : "";
598}
599
600static const char *purgeable_flag(int purgeable)
601{
602 return purgeable ? " purgeable" : "";
603}
604
c724e8a9
CW		 605static void print_error_buffers(struct seq_file *m,
606 const char *name,
607 struct drm_i915_error_buffer *err,
608 int count)
609{
610 seq_printf(m, "%s [%d]:\n", name, count);
611
612 while (count--) {
04b97b34 613 seq_printf(m, " %08x %8u %02x %02x %x %x%s%s%s%s%s%s%s",
c724e8a9
CW		 614 err->gtt_offset,
615 err->size,
616 err->read_domains,
617 err->write_domain,
0201f1ec 618 err->rseqno, err->wseqno,
c724e8a9
CW		 619 pin_flag(err->pinned),
620 tiling_flag(err->tiling),
621 dirty_flag(err->dirty),
622 purgeable_flag(err->purgeable),
96154f2f 623 err->ring != -1 ? " " : "",
a779e5ab 624 ring_str(err->ring),
93dfb40c 625 cache_level_str(err->cache_level));
c724e8a9
CW		 626
627 if (err->name)
628 seq_printf(m, " (name: %d)", err->name);
629 if (err->fence_reg != I915_FENCE_REG_NONE)
630 seq_printf(m, " (fence: %d)", err->fence_reg);
631
632 seq_printf(m, "\n");
633 err++;
634 }
635}
636
d27b1e0e
DV		 637static void i915_ring_error_state(struct seq_file *m,
638 struct drm_device *dev,
639 struct drm_i915_error_state *error,
640 unsigned ring)
641{
ec34a01d 642 BUG_ON(ring >= I915_NUM_RINGS); /* shut up confused gcc */
d27b1e0e 643 seq_printf(m, "%s command stream:\n", ring_str(ring));
c1cd90ed
DV		 644 seq_printf(m, " HEAD: 0x%08x\n", error->head[ring]);
645 seq_printf(m, " TAIL: 0x%08x\n", error->tail[ring]);
d27b1e0e
DV		 646 seq_printf(m, " ACTHD: 0x%08x\n", error->acthd[ring]);
647 seq_printf(m, " IPEIR: 0x%08x\n", error->ipeir[ring]);
648 seq_printf(m, " IPEHR: 0x%08x\n", error->ipehr[ring]);
649 seq_printf(m, " INSTDONE: 0x%08x\n", error->instdone[ring]);
050ee91f 650 if (ring == RCS && INTEL_INFO(dev)->gen >= 4)
c1cd90ed 651 seq_printf(m, " BBADDR: 0x%08llx\n", error->bbaddr);
050ee91f 652
c1cd90ed
DV		 653 if (INTEL_INFO(dev)->gen >= 4)
654 seq_printf(m, " INSTPS: 0x%08x\n", error->instps[ring]);
655 seq_printf(m, " INSTPM: 0x%08x\n", error->instpm[ring]);
9d2f41fa 656 seq_printf(m, " FADDR: 0x%08x\n", error->faddr[ring]);
33f3f518 657 if (INTEL_INFO(dev)->gen >= 6) {
12f55818 658 seq_printf(m, " RC PSMI: 0x%08x\n", error->rc_psmi[ring]);
33f3f518 659 seq_printf(m, " FAULT_REG: 0x%08x\n", error->fault_reg[ring]);
df2b23d9
CW		 660 seq_printf(m, " SYNC_0: 0x%08x [last synced 0x%08x]\n",
661 error->semaphore_mboxes[ring][0],
662 error->semaphore_seqno[ring][0]);
663 seq_printf(m, " SYNC_1: 0x%08x [last synced 0x%08x]\n",
664 error->semaphore_mboxes[ring][1],
665 error->semaphore_seqno[ring][1]);
33f3f518 666 }
d27b1e0e 667 seq_printf(m, " seqno: 0x%08x\n", error->seqno[ring]);
9574b3fe 668 seq_printf(m, " waiting: %s\n", yesno(error->waiting[ring]));
7e3b8737
DV		 669 seq_printf(m, " ring->head: 0x%08x\n", error->cpu_ring_head[ring]);
670 seq_printf(m, " ring->tail: 0x%08x\n", error->cpu_ring_tail[ring]);
d27b1e0e
DV		 671}
672
d5442303
DV		 673struct i915_error_state_file_priv {
674 struct drm_device *dev;
675 struct drm_i915_error_state *error;
676};
677
63eeaf38
JB		 678static int i915_error_state(struct seq_file *m, void *unused)
679{
d5442303
DV		 680 struct i915_error_state_file_priv *error_priv = m->private;
681 struct drm_device *dev = error_priv->dev;
63eeaf38 682 drm_i915_private_t *dev_priv = dev->dev_private;
d5442303 683 struct drm_i915_error_state *error = error_priv->error;
b4519513 684 struct intel_ring_buffer *ring;
52d39a21 685 int i, j, page, offset, elt;
63eeaf38 686
742cbee8 687 if (!error) {
63eeaf38 688 seq_printf(m, "no error state collected\n");
742cbee8 689 return 0;
63eeaf38
JB		 690 }
691
8a905236
JB		 692 seq_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec,
693 error->time.tv_usec);
9df30794 694 seq_printf(m, "PCI ID: 0x%04x\n", dev->pci_device);
1d8f38f4 695 seq_printf(m, "EIR: 0x%08x\n", error->eir);
be998e2e 696 seq_printf(m, "IER: 0x%08x\n", error->ier);
1d8f38f4 697 seq_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er);
b9a3906b 698 seq_printf(m, "CCID: 0x%08x\n", error->ccid);
9df30794 699
bf3301ab 700 for (i = 0; i < dev_priv->num_fence_regs; i++)
748ebc60
CW		 701 seq_printf(m, " fence[%d] = %08llx\n", i, error->fence[i]);
702
050ee91f
BW		 703 for (i = 0; i < ARRAY_SIZE(error->extra_instdone); i++)
704 seq_printf(m, " INSTDONE_%d: 0x%08x\n", i, error->extra_instdone[i]);
705
33f3f518 706 if (INTEL_INFO(dev)->gen >= 6) {
d27b1e0e 707 seq_printf(m, "ERROR: 0x%08x\n", error->error);
33f3f518
DV		 708 seq_printf(m, "DONE_REG: 0x%08x\n", error->done_reg);
709 }
d27b1e0e 710
71e172e8
BW		 711 if (INTEL_INFO(dev)->gen == 7)
712 seq_printf(m, "ERR_INT: 0x%08x\n", error->err_int);
713
b4519513
CW		 714 for_each_ring(ring, dev_priv, i)
715 i915_ring_error_state(m, dev, error, i);
d27b1e0e 716
c724e8a9
CW		 717 if (error->active_bo)
718 print_error_buffers(m, "Active",
719 error->active_bo,
720 error->active_bo_count);
721
722 if (error->pinned_bo)
723 print_error_buffers(m, "Pinned",
724 error->pinned_bo,
725 error->pinned_bo_count);
9df30794 726
52d39a21
CW		 727 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
728 struct drm_i915_error_object *obj;
9df30794 729
52d39a21 730 if ((obj = error->ring[i].batchbuffer)) {
bcfb2e28
CW		 731 seq_printf(m, "%s --- gtt_offset = 0x%08x\n",
732 dev_priv->ring[i].name,
733 obj->gtt_offset);
9df30794
CW		 734 offset = 0;
735 for (page = 0; page < obj->page_count; page++) {
736 for (elt = 0; elt < PAGE_SIZE/4; elt++) {
737 seq_printf(m, "%08x : %08x\n", offset, obj->pages[page][elt]);
738 offset += 4;
739 }
740 }
741 }
9df30794 742
52d39a21
CW		 743 if (error->ring[i].num_requests) {
744 seq_printf(m, "%s --- %d requests\n",
745 dev_priv->ring[i].name,
746 error->ring[i].num_requests);
747 for (j = 0; j < error->ring[i].num_requests; j++) {
ee4f42b1 748 seq_printf(m, " seqno 0x%08x, emitted %ld, tail 0x%08x\n",
52d39a21 749 error->ring[i].requests[j].seqno,
ee4f42b1
CW		 750 error->ring[i].requests[j].jiffies,
751 error->ring[i].requests[j].tail);
52d39a21
CW		 752 }
753 }
754
755 if ((obj = error->ring[i].ringbuffer)) {
e2f973d5
CW		 756 seq_printf(m, "%s --- ringbuffer = 0x%08x\n",
757 dev_priv->ring[i].name,
758 obj->gtt_offset);
759 offset = 0;
760 for (page = 0; page < obj->page_count; page++) {
761 for (elt = 0; elt < PAGE_SIZE/4; elt++) {
762 seq_printf(m, "%08x : %08x\n",
763 offset,
764 obj->pages[page][elt]);
765 offset += 4;
766 }
9df30794
CW		 767 }
768 }
769 }
63eeaf38 770
6ef3d427
CW		 771 if (error->overlay)
772 intel_overlay_print_error_state(m, error->overlay);
773
c4a1d9e4
CW		 774 if (error->display)
775 intel_display_print_error_state(m, dev, error->display);
776
63eeaf38
JB		 777 return 0;
778}
6911a9b8 779
d5442303
DV		 780static ssize_t
781i915_error_state_write(struct file *filp,
782 const char __user *ubuf,
783 size_t cnt,
784 loff_t *ppos)
785{
786 struct seq_file *m = filp->private_data;
787 struct i915_error_state_file_priv *error_priv = m->private;
788 struct drm_device *dev = error_priv->dev;
22bcfc6a 789 int ret;
d5442303
DV		 790
791 DRM_DEBUG_DRIVER("Resetting error state\n");
792
22bcfc6a
DV		 793 ret = mutex_lock_interruptible(&dev->struct_mutex);
794 if (ret)
795 return ret;
796
d5442303
DV		 797 i915_destroy_error_state(dev);
798 mutex_unlock(&dev->struct_mutex);
799
800 return cnt;
801}
802
803static int i915_error_state_open(struct inode *inode, struct file *file)
804{
805 struct drm_device *dev = inode->i_private;
806 drm_i915_private_t *dev_priv = dev->dev_private;
807 struct i915_error_state_file_priv *error_priv;
808 unsigned long flags;
809
810 error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
811 if (!error_priv)
812 return -ENOMEM;
813
814 error_priv->dev = dev;
815
816 spin_lock_irqsave(&dev_priv->error_lock, flags);
817 error_priv->error = dev_priv->first_error;
818 if (error_priv->error)
819 kref_get(&error_priv->error->ref);
820 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
821
822 return single_open(file, i915_error_state, error_priv);
823}
824
825static int i915_error_state_release(struct inode *inode, struct file *file)
826{
827 struct seq_file *m = file->private_data;
828 struct i915_error_state_file_priv *error_priv = m->private;
829
830 if (error_priv->error)
831 kref_put(&error_priv->error->ref, i915_error_state_free);
832 kfree(error_priv);
833
834 return single_release(inode, file);
835}
836
837static const struct file_operations i915_error_state_fops = {
838 .owner = THIS_MODULE,
839 .open = i915_error_state_open,
840 .read = seq_read,
841 .write = i915_error_state_write,
842 .llseek = default_llseek,
843 .release = i915_error_state_release,
844};
845
40633219
MK		 846static ssize_t
847i915_next_seqno_read(struct file *filp,
848 char __user *ubuf,
849 size_t max,
850 loff_t *ppos)
851{
852 struct drm_device *dev = filp->private_data;
853 drm_i915_private_t *dev_priv = dev->dev_private;
854 char buf[80];
855 int len;
856 int ret;
857
858 ret = mutex_lock_interruptible(&dev->struct_mutex);
859 if (ret)
860 return ret;
861
862 len = snprintf(buf, sizeof(buf),
863 "next_seqno : 0x%x\n",
864 dev_priv->next_seqno);
865
866 mutex_unlock(&dev->struct_mutex);
867
868 if (len > sizeof(buf))
869 len = sizeof(buf);
870
871 return simple_read_from_buffer(ubuf, max, ppos, buf, len);
872}
873
874static ssize_t
875i915_next_seqno_write(struct file *filp,
876 const char __user *ubuf,
877 size_t cnt,
878 loff_t *ppos)
879{
880 struct drm_device *dev = filp->private_data;
881 drm_i915_private_t *dev_priv = dev->dev_private;
882 char buf[20];
883 u32 val = 1;
884 int ret;
885
886 if (cnt > 0) {
887 if (cnt > sizeof(buf) - 1)
888 return -EINVAL;
889
890 if (copy_from_user(buf, ubuf, cnt))
891 return -EFAULT;
892 buf[cnt] = 0;
893
894 ret = kstrtouint(buf, 0, &val);
895 if (ret < 0)
896 return ret;
897 }
898
899 if (val == 0)
900 return -EINVAL;
901
902 ret = mutex_lock_interruptible(&dev->struct_mutex);
903 if (ret)
904 return ret;
905
906 if (i915_seqno_passed(val, dev_priv->next_seqno)) {
907 dev_priv->next_seqno = val;
908 DRM_DEBUG_DRIVER("Advancing seqno to %u\n", val);
909 } else {
910 ret = -EINVAL;
911 }
912
913 mutex_unlock(&dev->struct_mutex);
914
915 return ret ?: cnt;
916}
917
918static const struct file_operations i915_next_seqno_fops = {
919 .owner = THIS_MODULE,
920 .open = simple_open,
921 .read = i915_next_seqno_read,
922 .write = i915_next_seqno_write,
923 .llseek = default_llseek,
924};
925
f97108d1
JB		 926static int i915_rstdby_delays(struct seq_file *m, void *unused)
927{
928 struct drm_info_node *node = (struct drm_info_node *) m->private;
929 struct drm_device *dev = node->minor->dev;
930 drm_i915_private_t *dev_priv = dev->dev_private;
616fdb5a
BW		 931 u16 crstanddelay;
932 int ret;
933
934 ret = mutex_lock_interruptible(&dev->struct_mutex);
935 if (ret)
936 return ret;
937
938 crstanddelay = I915_READ16(CRSTANDVID);
939
940 mutex_unlock(&dev->struct_mutex);
f97108d1
JB		 941
942 seq_printf(m, "w/ctx: %d, w/o ctx: %d\n", (crstanddelay >> 8) & 0x3f, (crstanddelay & 0x3f));
943
944 return 0;
945}
946
947static int i915_cur_delayinfo(struct seq_file *m, void *unused)
948{
949 struct drm_info_node *node = (struct drm_info_node *) m->private;
950 struct drm_device *dev = node->minor->dev;
951 drm_i915_private_t *dev_priv = dev->dev_private;
d1ebd816 952 int ret;
3b8d8d91
JB		 953
954 if (IS_GEN5(dev)) {
955 u16 rgvswctl = I915_READ16(MEMSWCTL);
956 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
957
958 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
959 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
960 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
961 MEMSTAT_VID_SHIFT);
962 seq_printf(m, "Current P-state: %d\n",
963 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
1c70c0ce 964 } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
3b8d8d91
JB		 965 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
966 u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
967 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
ccab5c82
JB		 968 u32 rpstat;
969 u32 rpupei, rpcurup, rpprevup;
970 u32 rpdownei, rpcurdown, rpprevdown;
3b8d8d91
JB		 971 int max_freq;
972
973 /* RPSTAT1 is in the GT power well */
d1ebd816
BW		 974 ret = mutex_lock_interruptible(&dev->struct_mutex);
975 if (ret)
976 return ret;
977
fcca7926 978 gen6_gt_force_wake_get(dev_priv);
3b8d8d91 979
ccab5c82
JB		 980 rpstat = I915_READ(GEN6_RPSTAT1);
981 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
982 rpcurup = I915_READ(GEN6_RP_CUR_UP);
983 rpprevup = I915_READ(GEN6_RP_PREV_UP);
984 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
985 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
986 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
987
d1ebd816
BW		 988 gen6_gt_force_wake_put(dev_priv);
989 mutex_unlock(&dev->struct_mutex);
990
3b8d8d91 991 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
ccab5c82 992 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
3b8d8d91
JB		 993 seq_printf(m, "Render p-state ratio: %d\n",
994 (gt_perf_status & 0xff00) >> 8);
995 seq_printf(m, "Render p-state VID: %d\n",
996 gt_perf_status & 0xff);
997 seq_printf(m, "Render p-state limit: %d\n",
998 rp_state_limits & 0xff);
ccab5c82 999 seq_printf(m, "CAGF: %dMHz\n", ((rpstat & GEN6_CAGF_MASK) >>
c8735b0c 1000 GEN6_CAGF_SHIFT) * GT_FREQUENCY_MULTIPLIER);
ccab5c82
JB		 1001 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
1002 GEN6_CURICONT_MASK);
1003 seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
1004 GEN6_CURBSYTAVG_MASK);
1005 seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
1006 GEN6_CURBSYTAVG_MASK);
1007 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
1008 GEN6_CURIAVG_MASK);
1009 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
1010 GEN6_CURBSYTAVG_MASK);
1011 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
1012 GEN6_CURBSYTAVG_MASK);
3b8d8d91
JB		 1013
1014 max_freq = (rp_state_cap & 0xff0000) >> 16;
1015 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
c8735b0c 1016 max_freq * GT_FREQUENCY_MULTIPLIER);
3b8d8d91
JB		 1017
1018 max_freq = (rp_state_cap & 0xff00) >> 8;
1019 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
c8735b0c 1020 max_freq * GT_FREQUENCY_MULTIPLIER);
3b8d8d91
JB		 1021
1022 max_freq = rp_state_cap & 0xff;
1023 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
c8735b0c 1024 max_freq * GT_FREQUENCY_MULTIPLIER);
3b8d8d91
JB		 1025 } else {
1026 seq_printf(m, "no P-state info available\n");
1027 }
f97108d1
JB		 1028
1029 return 0;
1030}
1031
1032static int i915_delayfreq_table(struct seq_file *m, void *unused)
1033{
1034 struct drm_info_node *node = (struct drm_info_node *) m->private;
1035 struct drm_device *dev = node->minor->dev;
1036 drm_i915_private_t *dev_priv = dev->dev_private;
1037 u32 delayfreq;
616fdb5a
BW		 1038 int ret, i;
1039
1040 ret = mutex_lock_interruptible(&dev->struct_mutex);
1041 if (ret)
1042 return ret;
f97108d1
JB		 1043
1044 for (i = 0; i < 16; i++) {
1045 delayfreq = I915_READ(PXVFREQ_BASE + i * 4);
7648fa99
JB		 1046 seq_printf(m, "P%02dVIDFREQ: 0x%08x (VID: %d)\n", i, delayfreq,
1047 (delayfreq & PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT);
f97108d1
JB		 1048 }
1049
616fdb5a
BW		 1050 mutex_unlock(&dev->struct_mutex);
1051
f97108d1
JB		 1052 return 0;
1053}
1054
1055static inline int MAP_TO_MV(int map)
1056{
1057 return 1250 - (map * 25);
1058}
1059
1060static int i915_inttoext_table(struct seq_file *m, void *unused)
1061{
1062 struct drm_info_node *node = (struct drm_info_node *) m->private;
1063 struct drm_device *dev = node->minor->dev;
1064 drm_i915_private_t *dev_priv = dev->dev_private;
1065 u32 inttoext;
616fdb5a
BW		 1066 int ret, i;
1067
1068 ret = mutex_lock_interruptible(&dev->struct_mutex);
1069 if (ret)
1070 return ret;
f97108d1
JB		 1071
1072 for (i = 1; i <= 32; i++) {
1073 inttoext = I915_READ(INTTOEXT_BASE_ILK + i * 4);
1074 seq_printf(m, "INTTOEXT%02d: 0x%08x\n", i, inttoext);
1075 }
1076
616fdb5a
BW		 1077 mutex_unlock(&dev->struct_mutex);
1078
f97108d1
JB		 1079 return 0;
1080}
1081
4d85529d 1082static int ironlake_drpc_info(struct seq_file *m)
f97108d1
JB		 1083{
1084 struct drm_info_node *node = (struct drm_info_node *) m->private;
1085 struct drm_device *dev = node->minor->dev;
1086 drm_i915_private_t *dev_priv = dev->dev_private;
616fdb5a
BW		 1087 u32 rgvmodectl, rstdbyctl;
1088 u16 crstandvid;
1089 int ret;
1090
1091 ret = mutex_lock_interruptible(&dev->struct_mutex);
1092 if (ret)
1093 return ret;
1094
1095 rgvmodectl = I915_READ(MEMMODECTL);
1096 rstdbyctl = I915_READ(RSTDBYCTL);
1097 crstandvid = I915_READ16(CRSTANDVID);
1098
1099 mutex_unlock(&dev->struct_mutex);
f97108d1
JB		 1100
1101 seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
1102 "yes" : "no");
1103 seq_printf(m, "Boost freq: %d\n",
1104 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1105 MEMMODE_BOOST_FREQ_SHIFT);
1106 seq_printf(m, "HW control enabled: %s\n",
1107 rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");
1108 seq_printf(m, "SW control enabled: %s\n",
1109 rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");
1110 seq_printf(m, "Gated voltage change: %s\n",
1111 rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");
1112 seq_printf(m, "Starting frequency: P%d\n",
1113 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
7648fa99 1114 seq_printf(m, "Max P-state: P%d\n",
f97108d1 1115 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
7648fa99
JB		 1116 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1117 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1118 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1119 seq_printf(m, "Render standby enabled: %s\n",
1120 (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes");
88271da3
JB		 1121 seq_printf(m, "Current RS state: ");
1122 switch (rstdbyctl & RSX_STATUS_MASK) {
1123 case RSX_STATUS_ON:
1124 seq_printf(m, "on\n");
1125 break;
1126 case RSX_STATUS_RC1:
1127 seq_printf(m, "RC1\n");
1128 break;
1129 case RSX_STATUS_RC1E:
1130 seq_printf(m, "RC1E\n");
1131 break;
1132 case RSX_STATUS_RS1:
1133 seq_printf(m, "RS1\n");
1134 break;
1135 case RSX_STATUS_RS2:
1136 seq_printf(m, "RS2 (RC6)\n");
1137 break;
1138 case RSX_STATUS_RS3:
1139 seq_printf(m, "RC3 (RC6+)\n");
1140 break;
1141 default:
1142 seq_printf(m, "unknown\n");
1143 break;
1144 }
f97108d1
JB		 1145
1146 return 0;
1147}
1148
4d85529d
BW		 1149static int gen6_drpc_info(struct seq_file *m)
1150{
1151
1152 struct drm_info_node *node = (struct drm_info_node *) m->private;
1153 struct drm_device *dev = node->minor->dev;
1154 struct drm_i915_private *dev_priv = dev->dev_private;
ecd8faea 1155 u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
93b525dc 1156 unsigned forcewake_count;
4d85529d
BW		 1157 int count=0, ret;
1158
1159
1160 ret = mutex_lock_interruptible(&dev->struct_mutex);
1161 if (ret)
1162 return ret;
1163
93b525dc
DV		 1164 spin_lock_irq(&dev_priv->gt_lock);
1165 forcewake_count = dev_priv->forcewake_count;
1166 spin_unlock_irq(&dev_priv->gt_lock);
1167
1168 if (forcewake_count) {
1169 seq_printf(m, "RC information inaccurate because somebody "
1170 "holds a forcewake reference \n");
4d85529d
BW		 1171 } else {
1172 /* NB: we cannot use forcewake, else we read the wrong values */
1173 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1174 udelay(10);
1175 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1176 }
1177
1178 gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS);
1179 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4);
1180
1181 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1182 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1183 mutex_unlock(&dev->struct_mutex);
44cbd338
BW		 1184 mutex_lock(&dev_priv->rps.hw_lock);
1185 sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1186 mutex_unlock(&dev_priv->rps.hw_lock);
4d85529d
BW		 1187
1188 seq_printf(m, "Video Turbo Mode: %s\n",
1189 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1190 seq_printf(m, "HW control enabled: %s\n",
1191 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1192 seq_printf(m, "SW control enabled: %s\n",
1193 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1194 GEN6_RP_MEDIA_SW_MODE));
fff24e21 1195 seq_printf(m, "RC1e Enabled: %s\n",
4d85529d
BW		 1196 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1197 seq_printf(m, "RC6 Enabled: %s\n",
1198 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1199 seq_printf(m, "Deep RC6 Enabled: %s\n",
1200 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1201 seq_printf(m, "Deepest RC6 Enabled: %s\n",
1202 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1203 seq_printf(m, "Current RC state: ");
1204 switch (gt_core_status & GEN6_RCn_MASK) {
1205 case GEN6_RC0:
1206 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1207 seq_printf(m, "Core Power Down\n");
1208 else
1209 seq_printf(m, "on\n");
1210 break;
1211 case GEN6_RC3:
1212 seq_printf(m, "RC3\n");
1213 break;
1214 case GEN6_RC6:
1215 seq_printf(m, "RC6\n");
1216 break;
1217 case GEN6_RC7:
1218 seq_printf(m, "RC7\n");
1219 break;
1220 default:
1221 seq_printf(m, "Unknown\n");
1222 break;
1223 }
1224
1225 seq_printf(m, "Core Power Down: %s\n",
1226 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
cce66a28
BW		 1227
1228 /* Not exactly sure what this is */
1229 seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1230 I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1231 seq_printf(m, "RC6 residency since boot: %u\n",
1232 I915_READ(GEN6_GT_GFX_RC6));
1233 seq_printf(m, "RC6+ residency since boot: %u\n",
1234 I915_READ(GEN6_GT_GFX_RC6p));
1235 seq_printf(m, "RC6++ residency since boot: %u\n",
1236 I915_READ(GEN6_GT_GFX_RC6pp));
1237
ecd8faea
BW		 1238 seq_printf(m, "RC6 voltage: %dmV\n",
1239 GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1240 seq_printf(m, "RC6+ voltage: %dmV\n",
1241 GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1242 seq_printf(m, "RC6++ voltage: %dmV\n",
1243 GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
4d85529d
BW		 1244 return 0;
1245}
1246
1247static int i915_drpc_info(struct seq_file *m, void *unused)
1248{
1249 struct drm_info_node *node = (struct drm_info_node *) m->private;
1250 struct drm_device *dev = node->minor->dev;
1251
1252 if (IS_GEN6(dev) || IS_GEN7(dev))
1253 return gen6_drpc_info(m);
1254 else
1255 return ironlake_drpc_info(m);
1256}
1257
b5e50c3f
JB		 1258static int i915_fbc_status(struct seq_file *m, void *unused)
1259{
1260 struct drm_info_node *node = (struct drm_info_node *) m->private;
1261 struct drm_device *dev = node->minor->dev;
b5e50c3f 1262 drm_i915_private_t *dev_priv = dev->dev_private;
b5e50c3f 1263
ee5382ae 1264 if (!I915_HAS_FBC(dev)) {
b5e50c3f
JB		 1265 seq_printf(m, "FBC unsupported on this chipset\n");
1266 return 0;
1267 }
1268
ee5382ae 1269 if (intel_fbc_enabled(dev)) {
b5e50c3f
JB		 1270 seq_printf(m, "FBC enabled\n");
1271 } else {
1272 seq_printf(m, "FBC disabled: ");
1273 switch (dev_priv->no_fbc_reason) {
bed4a673
CW		 1274 case FBC_NO_OUTPUT:
1275 seq_printf(m, "no outputs");
1276 break;
b5e50c3f
JB		 1277 case FBC_STOLEN_TOO_SMALL:
1278 seq_printf(m, "not enough stolen memory");
1279 break;
1280 case FBC_UNSUPPORTED_MODE:
1281 seq_printf(m, "mode not supported");
1282 break;
1283 case FBC_MODE_TOO_LARGE:
1284 seq_printf(m, "mode too large");
1285 break;
1286 case FBC_BAD_PLANE:
1287 seq_printf(m, "FBC unsupported on plane");
1288 break;
1289 case FBC_NOT_TILED:
1290 seq_printf(m, "scanout buffer not tiled");
1291 break;
9c928d16
JB		 1292 case FBC_MULTIPLE_PIPES:
1293 seq_printf(m, "multiple pipes are enabled");
1294 break;
c1a9f047
JB		 1295 case FBC_MODULE_PARAM:
1296 seq_printf(m, "disabled per module param (default off)");
1297 break;
b5e50c3f
JB		 1298 default:
1299 seq_printf(m, "unknown reason");
1300 }
1301 seq_printf(m, "\n");
1302 }
1303 return 0;
1304}
1305
4a9bef37
JB		 1306static int i915_sr_status(struct seq_file *m, void *unused)
1307{
1308 struct drm_info_node *node = (struct drm_info_node *) m->private;
1309 struct drm_device *dev = node->minor->dev;
1310 drm_i915_private_t *dev_priv = dev->dev_private;
1311 bool sr_enabled = false;
1312
1398261a 1313 if (HAS_PCH_SPLIT(dev))
5ba2aaaa 1314 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
a6c45cf0 1315 else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))
4a9bef37
JB		 1316 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1317 else if (IS_I915GM(dev))
1318 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1319 else if (IS_PINEVIEW(dev))
1320 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1321
5ba2aaaa
CW		 1322 seq_printf(m, "self-refresh: %s\n",
1323 sr_enabled ? "enabled" : "disabled");
4a9bef37
JB		 1324
1325 return 0;
1326}
1327
7648fa99
JB		 1328static int i915_emon_status(struct seq_file *m, void *unused)
1329{
1330 struct drm_info_node *node = (struct drm_info_node *) m->private;
1331 struct drm_device *dev = node->minor->dev;
1332 drm_i915_private_t *dev_priv = dev->dev_private;
1333 unsigned long temp, chipset, gfx;
de227ef0
CW		 1334 int ret;
1335
582be6b4
CW		 1336 if (!IS_GEN5(dev))
1337 return -ENODEV;
1338
de227ef0
CW		 1339 ret = mutex_lock_interruptible(&dev->struct_mutex);
1340 if (ret)
1341 return ret;
7648fa99
JB		 1342
1343 temp = i915_mch_val(dev_priv);
1344 chipset = i915_chipset_val(dev_priv);
1345 gfx = i915_gfx_val(dev_priv);
de227ef0 1346 mutex_unlock(&dev->struct_mutex);
7648fa99
JB		 1347
1348 seq_printf(m, "GMCH temp: %ld\n", temp);
1349 seq_printf(m, "Chipset power: %ld\n", chipset);
1350 seq_printf(m, "GFX power: %ld\n", gfx);
1351 seq_printf(m, "Total power: %ld\n", chipset + gfx);
1352
1353 return 0;
1354}
1355
23b2f8bb
JB		 1356static int i915_ring_freq_table(struct seq_file *m, void *unused)
1357{
1358 struct drm_info_node *node = (struct drm_info_node *) m->private;
1359 struct drm_device *dev = node->minor->dev;
1360 drm_i915_private_t *dev_priv = dev->dev_private;
1361 int ret;
1362 int gpu_freq, ia_freq;
1363
1c70c0ce 1364 if (!(IS_GEN6(dev) || IS_GEN7(dev))) {
23b2f8bb
JB		 1365 seq_printf(m, "unsupported on this chipset\n");
1366 return 0;
1367 }
1368
4fc688ce 1369 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
23b2f8bb
JB		 1370 if (ret)
1371 return ret;
1372
1373 seq_printf(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\n");
1374
c6a828d3
DV		 1375 for (gpu_freq = dev_priv->rps.min_delay;
1376 gpu_freq <= dev_priv->rps.max_delay;
23b2f8bb 1377 gpu_freq++) {
42c0526c
BW		 1378 ia_freq = gpu_freq;
1379 sandybridge_pcode_read(dev_priv,
1380 GEN6_PCODE_READ_MIN_FREQ_TABLE,
1381 &ia_freq);
c8735b0c 1382 seq_printf(m, "%d\t\t%d\n", gpu_freq * GT_FREQUENCY_MULTIPLIER, ia_freq * 100);
23b2f8bb
JB		 1383 }
1384
4fc688ce 1385 mutex_unlock(&dev_priv->rps.hw_lock);
23b2f8bb
JB		 1386
1387 return 0;
1388}
1389
7648fa99
JB		 1390static int i915_gfxec(struct seq_file *m, void *unused)
1391{
1392 struct drm_info_node *node = (struct drm_info_node *) m->private;
1393 struct drm_device *dev = node->minor->dev;
1394 drm_i915_private_t *dev_priv = dev->dev_private;
616fdb5a
BW		 1395 int ret;
1396
1397 ret = mutex_lock_interruptible(&dev->struct_mutex);
1398 if (ret)
1399 return ret;
7648fa99
JB		 1400
1401 seq_printf(m, "GFXEC: %ld\n", (unsigned long)I915_READ(0x112f4));
1402
616fdb5a
BW		 1403 mutex_unlock(&dev->struct_mutex);
1404
7648fa99
JB		 1405 return 0;
1406}
1407
44834a67
CW		 1408static int i915_opregion(struct seq_file *m, void *unused)
1409{
1410 struct drm_info_node *node = (struct drm_info_node *) m->private;
1411 struct drm_device *dev = node->minor->dev;
1412 drm_i915_private_t *dev_priv = dev->dev_private;
1413 struct intel_opregion *opregion = &dev_priv->opregion;
0d38f009 1414 void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL);
44834a67
CW		 1415 int ret;
1416
0d38f009
DV		 1417 if (data == NULL)
1418 return -ENOMEM;
1419
44834a67
CW		 1420 ret = mutex_lock_interruptible(&dev->struct_mutex);
1421 if (ret)
0d38f009 1422 goto out;
44834a67 1423
0d38f009
DV		 1424 if (opregion->header) {
1425 memcpy_fromio(data, opregion->header, OPREGION_SIZE);
1426 seq_write(m, data, OPREGION_SIZE);
1427 }
44834a67
CW		 1428
1429 mutex_unlock(&dev->struct_mutex);
1430
0d38f009
DV		 1431out:
1432 kfree(data);
44834a67
CW		 1433 return 0;
1434}
1435
37811fcc
CW		 1436static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1437{
1438 struct drm_info_node *node = (struct drm_info_node *) m->private;
1439 struct drm_device *dev = node->minor->dev;
1440 drm_i915_private_t *dev_priv = dev->dev_private;
1441 struct intel_fbdev *ifbdev;
1442 struct intel_framebuffer *fb;
1443 int ret;
1444
1445 ret = mutex_lock_interruptible(&dev->mode_config.mutex);
1446 if (ret)
1447 return ret;
1448
1449 ifbdev = dev_priv->fbdev;
1450 fb = to_intel_framebuffer(ifbdev->helper.fb);
1451
1452 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, obj ",
1453 fb->base.width,
1454 fb->base.height,
1455 fb->base.depth,
1456 fb->base.bits_per_pixel);
05394f39 1457 describe_obj(m, fb->obj);
37811fcc
CW		 1458 seq_printf(m, "\n");
1459
1460 list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) {
1461 if (&fb->base == ifbdev->helper.fb)
1462 continue;
1463
1464 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, obj ",
1465 fb->base.width,
1466 fb->base.height,
1467 fb->base.depth,
1468 fb->base.bits_per_pixel);
05394f39 1469 describe_obj(m, fb->obj);
37811fcc
CW		 1470 seq_printf(m, "\n");
1471 }
1472
1473 mutex_unlock(&dev->mode_config.mutex);
1474
1475 return 0;
1476}
1477
e76d3630
BW		 1478static int i915_context_status(struct seq_file *m, void *unused)
1479{
1480 struct drm_info_node *node = (struct drm_info_node *) m->private;
1481 struct drm_device *dev = node->minor->dev;
1482 drm_i915_private_t *dev_priv = dev->dev_private;
1483 int ret;
1484
1485 ret = mutex_lock_interruptible(&dev->mode_config.mutex);
1486 if (ret)
1487 return ret;
1488
3e373948 1489 if (dev_priv->ips.pwrctx) {
dc501fbc 1490 seq_printf(m, "power context ");
3e373948 1491 describe_obj(m, dev_priv->ips.pwrctx);
dc501fbc
BW		 1492 seq_printf(m, "\n");
1493 }
e76d3630 1494
3e373948 1495 if (dev_priv->ips.renderctx) {
dc501fbc 1496 seq_printf(m, "render context ");
3e373948 1497 describe_obj(m, dev_priv->ips.renderctx);
dc501fbc
BW		 1498 seq_printf(m, "\n");
1499 }
e76d3630
BW		 1500
1501 mutex_unlock(&dev->mode_config.mutex);
1502
1503 return 0;
1504}
1505
6d794d42
BW		 1506static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data)
1507{
1508 struct drm_info_node *node = (struct drm_info_node *) m->private;
1509 struct drm_device *dev = node->minor->dev;
1510 struct drm_i915_private *dev_priv = dev->dev_private;
9f1f46a4 1511 unsigned forcewake_count;
6d794d42 1512
9f1f46a4
DV		 1513 spin_lock_irq(&dev_priv->gt_lock);
1514 forcewake_count = dev_priv->forcewake_count;
1515 spin_unlock_irq(&dev_priv->gt_lock);
6d794d42 1516
9f1f46a4 1517 seq_printf(m, "forcewake count = %u\n", forcewake_count);
6d794d42
BW		 1518
1519 return 0;
1520}
1521
ea16a3cd
DV		 1522static const char *swizzle_string(unsigned swizzle)
1523{
1524 switch(swizzle) {
1525 case I915_BIT_6_SWIZZLE_NONE:
1526 return "none";
1527 case I915_BIT_6_SWIZZLE_9:
1528 return "bit9";
1529 case I915_BIT_6_SWIZZLE_9_10:
1530 return "bit9/bit10";
1531 case I915_BIT_6_SWIZZLE_9_11:
1532 return "bit9/bit11";
1533 case I915_BIT_6_SWIZZLE_9_10_11:
1534 return "bit9/bit10/bit11";
1535 case I915_BIT_6_SWIZZLE_9_17:
1536 return "bit9/bit17";
1537 case I915_BIT_6_SWIZZLE_9_10_17:
1538 return "bit9/bit10/bit17";
1539 case I915_BIT_6_SWIZZLE_UNKNOWN:
1540 return "unkown";
1541 }
1542
1543 return "bug";
1544}
1545
1546static int i915_swizzle_info(struct seq_file *m, void *data)
1547{
1548 struct drm_info_node *node = (struct drm_info_node *) m->private;
1549 struct drm_device *dev = node->minor->dev;
1550 struct drm_i915_private *dev_priv = dev->dev_private;
22bcfc6a
DV		 1551 int ret;
1552
1553 ret = mutex_lock_interruptible(&dev->struct_mutex);
1554 if (ret)
1555 return ret;
ea16a3cd 1556
ea16a3cd
DV		 1557 seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
1558 swizzle_string(dev_priv->mm.bit_6_swizzle_x));
1559 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
1560 swizzle_string(dev_priv->mm.bit_6_swizzle_y));
1561
1562 if (IS_GEN3(dev) || IS_GEN4(dev)) {
1563 seq_printf(m, "DDC = 0x%08x\n",
1564 I915_READ(DCC));
1565 seq_printf(m, "C0DRB3 = 0x%04x\n",
1566 I915_READ16(C0DRB3));
1567 seq_printf(m, "C1DRB3 = 0x%04x\n",
1568 I915_READ16(C1DRB3));
3fa7d235
DV		 1569 } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
1570 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
1571 I915_READ(MAD_DIMM_C0));
1572 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
1573 I915_READ(MAD_DIMM_C1));
1574 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
1575 I915_READ(MAD_DIMM_C2));
1576 seq_printf(m, "TILECTL = 0x%08x\n",
1577 I915_READ(TILECTL));
1578 seq_printf(m, "ARB_MODE = 0x%08x\n",
1579 I915_READ(ARB_MODE));
1580 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
1581 I915_READ(DISP_ARB_CTL));
ea16a3cd
DV		 1582 }
1583 mutex_unlock(&dev->struct_mutex);
1584
1585 return 0;
1586}
1587
3cf17fc5
DV		 1588static int i915_ppgtt_info(struct seq_file *m, void *data)
1589{
1590 struct drm_info_node *node = (struct drm_info_node *) m->private;
1591 struct drm_device *dev = node->minor->dev;
1592 struct drm_i915_private *dev_priv = dev->dev_private;
1593 struct intel_ring_buffer *ring;
1594 int i, ret;
1595
1596
1597 ret = mutex_lock_interruptible(&dev->struct_mutex);
1598 if (ret)
1599 return ret;
1600 if (INTEL_INFO(dev)->gen == 6)
1601 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
1602
a2c7f6fd 1603 for_each_ring(ring, dev_priv, i) {
3cf17fc5
DV		 1604 seq_printf(m, "%s\n", ring->name);
1605 if (INTEL_INFO(dev)->gen == 7)
1606 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
1607 seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
1608 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
1609 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring)));
1610 }
1611 if (dev_priv->mm.aliasing_ppgtt) {
1612 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
1613
1614 seq_printf(m, "aliasing PPGTT:\n");
1615 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset);
1616 }
1617 seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
1618 mutex_unlock(&dev->struct_mutex);
1619
1620 return 0;
1621}
1622
57f350b6
JB		 1623static int i915_dpio_info(struct seq_file *m, void *data)
1624{
1625 struct drm_info_node *node = (struct drm_info_node *) m->private;
1626 struct drm_device *dev = node->minor->dev;
1627 struct drm_i915_private *dev_priv = dev->dev_private;
1628 int ret;
1629
1630
1631 if (!IS_VALLEYVIEW(dev)) {
1632 seq_printf(m, "unsupported\n");
1633 return 0;
1634 }
1635
09153000 1636 ret = mutex_lock_interruptible(&dev_priv->dpio_lock);
57f350b6
JB		 1637 if (ret)
1638 return ret;
1639
1640 seq_printf(m, "DPIO_CTL: 0x%08x\n", I915_READ(DPIO_CTL));
1641
1642 seq_printf(m, "DPIO_DIV_A: 0x%08x\n",
1643 intel_dpio_read(dev_priv, _DPIO_DIV_A));
1644 seq_printf(m, "DPIO_DIV_B: 0x%08x\n",
1645 intel_dpio_read(dev_priv, _DPIO_DIV_B));
1646
1647 seq_printf(m, "DPIO_REFSFR_A: 0x%08x\n",
1648 intel_dpio_read(dev_priv, _DPIO_REFSFR_A));
1649 seq_printf(m, "DPIO_REFSFR_B: 0x%08x\n",
1650 intel_dpio_read(dev_priv, _DPIO_REFSFR_B));
1651
1652 seq_printf(m, "DPIO_CORE_CLK_A: 0x%08x\n",
1653 intel_dpio_read(dev_priv, _DPIO_CORE_CLK_A));
1654 seq_printf(m, "DPIO_CORE_CLK_B: 0x%08x\n",
1655 intel_dpio_read(dev_priv, _DPIO_CORE_CLK_B));
1656
1657 seq_printf(m, "DPIO_LFP_COEFF_A: 0x%08x\n",
1658 intel_dpio_read(dev_priv, _DPIO_LFP_COEFF_A));
1659 seq_printf(m, "DPIO_LFP_COEFF_B: 0x%08x\n",
1660 intel_dpio_read(dev_priv, _DPIO_LFP_COEFF_B));
1661
1662 seq_printf(m, "DPIO_FASTCLK_DISABLE: 0x%08x\n",
1663 intel_dpio_read(dev_priv, DPIO_FASTCLK_DISABLE));
1664
09153000 1665 mutex_unlock(&dev_priv->dpio_lock);
57f350b6
JB		 1666
1667 return 0;
1668}
1669
f3cd474b
CW		 1670static ssize_t
1671i915_wedged_read(struct file *filp,
1672 char __user *ubuf,
1673 size_t max,
1674 loff_t *ppos)
1675{
1676 struct drm_device *dev = filp->private_data;
1677 drm_i915_private_t *dev_priv = dev->dev_private;
1678 char buf[80];
1679 int len;
1680
0206e353 1681 len = snprintf(buf, sizeof(buf),
f3cd474b
CW		 1682 "wedged : %d\n",
1683 atomic_read(&dev_priv->mm.wedged));
1684
0206e353
AJ		 1685 if (len > sizeof(buf))
1686 len = sizeof(buf);
f4433a8d 1687
f3cd474b
CW		 1688 return simple_read_from_buffer(ubuf, max, ppos, buf, len);
1689}
1690
1691static ssize_t
1692i915_wedged_write(struct file *filp,
1693 const char __user *ubuf,
1694 size_t cnt,
1695 loff_t *ppos)
1696{
1697 struct drm_device *dev = filp->private_data;
f3cd474b
CW		 1698 char buf[20];
1699 int val = 1;
1700
1701 if (cnt > 0) {
0206e353 1702 if (cnt > sizeof(buf) - 1)
f3cd474b
CW		 1703 return -EINVAL;
1704
1705 if (copy_from_user(buf, ubuf, cnt))
1706 return -EFAULT;
1707 buf[cnt] = 0;
1708
1709 val = simple_strtoul(buf, NULL, 0);
1710 }
1711
1712 DRM_INFO("Manually setting wedged to %d\n", val);
527f9e90 1713 i915_handle_error(dev, val);
f3cd474b
CW		 1714
1715 return cnt;
1716}
1717
1718static const struct file_operations i915_wedged_fops = {
1719 .owner = THIS_MODULE,
234e3405 1720 .open = simple_open,
f3cd474b
CW		 1721 .read = i915_wedged_read,
1722 .write = i915_wedged_write,
6038f373 1723 .llseek = default_llseek,
f3cd474b
CW		 1724};
1725
e5eb3d63
DV		 1726static ssize_t
1727i915_ring_stop_read(struct file *filp,
1728 char __user *ubuf,
1729 size_t max,
1730 loff_t *ppos)
1731{
1732 struct drm_device *dev = filp->private_data;
1733 drm_i915_private_t *dev_priv = dev->dev_private;
1734 char buf[20];
1735 int len;
1736
1737 len = snprintf(buf, sizeof(buf),
1738 "0x%08x\n", dev_priv->stop_rings);
1739
1740 if (len > sizeof(buf))
1741 len = sizeof(buf);
1742
1743 return simple_read_from_buffer(ubuf, max, ppos, buf, len);
1744}
1745
1746static ssize_t
1747i915_ring_stop_write(struct file *filp,
1748 const char __user *ubuf,
1749 size_t cnt,
1750 loff_t *ppos)
1751{
1752 struct drm_device *dev = filp->private_data;
1753 struct drm_i915_private *dev_priv = dev->dev_private;
1754 char buf[20];
22bcfc6a 1755 int val = 0, ret;
e5eb3d63
DV		 1756
1757 if (cnt > 0) {
1758 if (cnt > sizeof(buf) - 1)
1759 return -EINVAL;
1760
1761 if (copy_from_user(buf, ubuf, cnt))
1762 return -EFAULT;
1763 buf[cnt] = 0;
1764
1765 val = simple_strtoul(buf, NULL, 0);
1766 }
1767
1768 DRM_DEBUG_DRIVER("Stopping rings 0x%08x\n", val);
1769
22bcfc6a
DV		 1770 ret = mutex_lock_interruptible(&dev->struct_mutex);
1771 if (ret)
1772 return ret;
1773
e5eb3d63
DV		 1774 dev_priv->stop_rings = val;
1775 mutex_unlock(&dev->struct_mutex);
1776
1777 return cnt;
1778}
1779
1780static const struct file_operations i915_ring_stop_fops = {
1781 .owner = THIS_MODULE,
1782 .open = simple_open,
1783 .read = i915_ring_stop_read,
1784 .write = i915_ring_stop_write,
1785 .llseek = default_llseek,
1786};
d5442303 1787
358733e9
JB		 1788static ssize_t
1789i915_max_freq_read(struct file *filp,
1790 char __user *ubuf,
1791 size_t max,
1792 loff_t *ppos)
1793{
1794 struct drm_device *dev = filp->private_data;
1795 drm_i915_private_t *dev_priv = dev->dev_private;
1796 char buf[80];
004777cb
DV		 1797 int len, ret;
1798
1799 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
1800 return -ENODEV;
1801
4fc688ce 1802 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 1803 if (ret)
1804 return ret;
358733e9 1805
0206e353 1806 len = snprintf(buf, sizeof(buf),
c8735b0c 1807 "max freq: %d\n", dev_priv->rps.max_delay * GT_FREQUENCY_MULTIPLIER);
4fc688ce 1808 mutex_unlock(&dev_priv->rps.hw_lock);
358733e9 1809
0206e353
AJ		 1810 if (len > sizeof(buf))
1811 len = sizeof(buf);
358733e9
JB		 1812
1813 return simple_read_from_buffer(ubuf, max, ppos, buf, len);
1814}
1815
1816static ssize_t
1817i915_max_freq_write(struct file *filp,
1818 const char __user *ubuf,
1819 size_t cnt,
1820 loff_t *ppos)
1821{
1822 struct drm_device *dev = filp->private_data;
1823 struct drm_i915_private *dev_priv = dev->dev_private;
1824 char buf[20];
004777cb
DV		 1825 int val = 1, ret;
1826
1827 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
1828 return -ENODEV;
358733e9
JB		 1829
1830 if (cnt > 0) {
0206e353 1831 if (cnt > sizeof(buf) - 1)
358733e9
JB		 1832 return -EINVAL;
1833
1834 if (copy_from_user(buf, ubuf, cnt))
1835 return -EFAULT;
1836 buf[cnt] = 0;
1837
1838 val = simple_strtoul(buf, NULL, 0);
1839 }
1840
1841 DRM_DEBUG_DRIVER("Manually setting max freq to %d\n", val);
1842
4fc688ce 1843 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 1844 if (ret)
1845 return ret;
1846
358733e9
JB		 1847 /*
1848 * Turbo will still be enabled, but won't go above the set value.
1849 */
c8735b0c 1850 dev_priv->rps.max_delay = val / GT_FREQUENCY_MULTIPLIER;
358733e9 1851
c8735b0c 1852 gen6_set_rps(dev, val / GT_FREQUENCY_MULTIPLIER);
4fc688ce 1853 mutex_unlock(&dev_priv->rps.hw_lock);
358733e9
JB		 1854
1855 return cnt;
1856}
1857
1858static const struct file_operations i915_max_freq_fops = {
1859 .owner = THIS_MODULE,
234e3405 1860 .open = simple_open,
358733e9
JB		 1861 .read = i915_max_freq_read,
1862 .write = i915_max_freq_write,
1863 .llseek = default_llseek,
1864};
1865
1523c310
JB		 1866static ssize_t
1867i915_min_freq_read(struct file *filp, char __user *ubuf, size_t max,
1868 loff_t *ppos)
1869{
1870 struct drm_device *dev = filp->private_data;
1871 drm_i915_private_t *dev_priv = dev->dev_private;
1872 char buf[80];
004777cb
DV		 1873 int len, ret;
1874
1875 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
1876 return -ENODEV;
1877
4fc688ce 1878 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 1879 if (ret)
1880 return ret;
1523c310
JB		 1881
1882 len = snprintf(buf, sizeof(buf),
c8735b0c 1883 "min freq: %d\n", dev_priv->rps.min_delay * GT_FREQUENCY_MULTIPLIER);
4fc688ce 1884 mutex_unlock(&dev_priv->rps.hw_lock);
1523c310
JB		 1885
1886 if (len > sizeof(buf))
1887 len = sizeof(buf);
1888
1889 return simple_read_from_buffer(ubuf, max, ppos, buf, len);
1890}
1891
1892static ssize_t
1893i915_min_freq_write(struct file *filp, const char __user *ubuf, size_t cnt,
1894 loff_t *ppos)
1895{
1896 struct drm_device *dev = filp->private_data;
1897 struct drm_i915_private *dev_priv = dev->dev_private;
1898 char buf[20];
004777cb
DV		 1899 int val = 1, ret;
1900
1901 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
1902 return -ENODEV;
1523c310
JB		 1903
1904 if (cnt > 0) {
1905 if (cnt > sizeof(buf) - 1)
1906 return -EINVAL;
1907
1908 if (copy_from_user(buf, ubuf, cnt))
1909 return -EFAULT;
1910 buf[cnt] = 0;
1911
1912 val = simple_strtoul(buf, NULL, 0);
1913 }
1914
1915 DRM_DEBUG_DRIVER("Manually setting min freq to %d\n", val);
1916
4fc688ce 1917 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 1918 if (ret)
1919 return ret;
1920
1523c310
JB		 1921 /*
1922 * Turbo will still be enabled, but won't go below the set value.
1923 */
c8735b0c 1924 dev_priv->rps.min_delay = val / GT_FREQUENCY_MULTIPLIER;
1523c310 1925
c8735b0c 1926 gen6_set_rps(dev, val / GT_FREQUENCY_MULTIPLIER);
4fc688ce 1927 mutex_unlock(&dev_priv->rps.hw_lock);
1523c310
JB		 1928
1929 return cnt;
1930}
1931
1932static const struct file_operations i915_min_freq_fops = {
1933 .owner = THIS_MODULE,
1934 .open = simple_open,
1935 .read = i915_min_freq_read,
1936 .write = i915_min_freq_write,
1937 .llseek = default_llseek,
1938};
1939
07b7ddd9
JB		 1940static ssize_t
1941i915_cache_sharing_read(struct file *filp,
1942 char __user *ubuf,
1943 size_t max,
1944 loff_t *ppos)
1945{
1946 struct drm_device *dev = filp->private_data;
1947 drm_i915_private_t *dev_priv = dev->dev_private;
1948 char buf[80];
1949 u32 snpcr;
22bcfc6a 1950 int len, ret;
07b7ddd9 1951
004777cb
DV		 1952 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
1953 return -ENODEV;
1954
22bcfc6a
DV		 1955 ret = mutex_lock_interruptible(&dev->struct_mutex);
1956 if (ret)
1957 return ret;
1958
07b7ddd9
JB		 1959 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
1960 mutex_unlock(&dev_priv->dev->struct_mutex);
1961
0206e353 1962 len = snprintf(buf, sizeof(buf),
07b7ddd9
JB		 1963 "%d\n", (snpcr & GEN6_MBC_SNPCR_MASK) >>
1964 GEN6_MBC_SNPCR_SHIFT);
1965
0206e353
AJ		 1966 if (len > sizeof(buf))
1967 len = sizeof(buf);
07b7ddd9
JB		 1968
1969 return simple_read_from_buffer(ubuf, max, ppos, buf, len);
1970}
1971
1972static ssize_t
1973i915_cache_sharing_write(struct file *filp,
1974 const char __user *ubuf,
1975 size_t cnt,
1976 loff_t *ppos)
1977{
1978 struct drm_device *dev = filp->private_data;
1979 struct drm_i915_private *dev_priv = dev->dev_private;
1980 char buf[20];
1981 u32 snpcr;
1982 int val = 1;
1983
004777cb
DV		 1984 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
1985 return -ENODEV;
1986
07b7ddd9 1987 if (cnt > 0) {
0206e353 1988 if (cnt > sizeof(buf) - 1)
07b7ddd9
JB		 1989 return -EINVAL;
1990
1991 if (copy_from_user(buf, ubuf, cnt))
1992 return -EFAULT;
1993 buf[cnt] = 0;
1994
1995 val = simple_strtoul(buf, NULL, 0);
1996 }
1997
1998 if (val < 0 || val > 3)
1999 return -EINVAL;
2000
2001 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %d\n", val);
2002
2003 /* Update the cache sharing policy here as well */
2004 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
2005 snpcr &= ~GEN6_MBC_SNPCR_MASK;
2006 snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
2007 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
2008
2009 return cnt;
2010}
2011
2012static const struct file_operations i915_cache_sharing_fops = {
2013 .owner = THIS_MODULE,
234e3405 2014 .open = simple_open,
07b7ddd9
JB		 2015 .read = i915_cache_sharing_read,
2016 .write = i915_cache_sharing_write,
2017 .llseek = default_llseek,
2018};
2019
f3cd474b
CW		 2020/* As the drm_debugfs_init() routines are called before dev->dev_private is
2021 * allocated we need to hook into the minor for release. */
2022static int
2023drm_add_fake_info_node(struct drm_minor *minor,
2024 struct dentry *ent,
2025 const void *key)
2026{
2027 struct drm_info_node *node;
2028
2029 node = kmalloc(sizeof(struct drm_info_node), GFP_KERNEL);
2030 if (node == NULL) {
2031 debugfs_remove(ent);
2032 return -ENOMEM;
2033 }
2034
2035 node->minor = minor;
2036 node->dent = ent;
2037 node->info_ent = (void *) key;
b3e067c0
MS		 2038
2039 mutex_lock(&minor->debugfs_lock);
2040 list_add(&node->list, &minor->debugfs_list);
2041 mutex_unlock(&minor->debugfs_lock);
f3cd474b
CW		 2042
2043 return 0;
2044}
2045
6d794d42
BW		 2046static int i915_forcewake_open(struct inode *inode, struct file *file)
2047{
2048 struct drm_device *dev = inode->i_private;
2049 struct drm_i915_private *dev_priv = dev->dev_private;
6d794d42 2050
075edca4 2051 if (INTEL_INFO(dev)->gen < 6)
6d794d42
BW		 2052 return 0;
2053
6d794d42 2054 gen6_gt_force_wake_get(dev_priv);
6d794d42
BW		 2055
2056 return 0;
2057}
2058
c43b5634 2059static int i915_forcewake_release(struct inode *inode, struct file *file)
6d794d42
BW		 2060{
2061 struct drm_device *dev = inode->i_private;
2062 struct drm_i915_private *dev_priv = dev->dev_private;
2063
075edca4 2064 if (INTEL_INFO(dev)->gen < 6)
6d794d42
BW		 2065 return 0;
2066
6d794d42 2067 gen6_gt_force_wake_put(dev_priv);
6d794d42
BW		 2068
2069 return 0;
2070}
2071
2072static const struct file_operations i915_forcewake_fops = {
2073 .owner = THIS_MODULE,
2074 .open = i915_forcewake_open,
2075 .release = i915_forcewake_release,
2076};
2077
2078static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
2079{
2080 struct drm_device *dev = minor->dev;
2081 struct dentry *ent;
2082
2083 ent = debugfs_create_file("i915_forcewake_user",
8eb57294 2084 S_IRUSR,
6d794d42
BW		 2085 root, dev,
2086 &i915_forcewake_fops);
2087 if (IS_ERR(ent))
2088 return PTR_ERR(ent);
2089
8eb57294 2090 return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
6d794d42
BW		 2091}
2092
6a9c308d
DV		 2093static int i915_debugfs_create(struct dentry *root,
2094 struct drm_minor *minor,
2095 const char *name,
2096 const struct file_operations *fops)
07b7ddd9
JB		 2097{
2098 struct drm_device *dev = minor->dev;
2099 struct dentry *ent;
2100
6a9c308d 2101 ent = debugfs_create_file(name,
07b7ddd9
JB		 2102 S_IRUGO | S_IWUSR,
2103 root, dev,
6a9c308d 2104 fops);
07b7ddd9
JB		 2105 if (IS_ERR(ent))
2106 return PTR_ERR(ent);
2107
6a9c308d 2108 return drm_add_fake_info_node(minor, ent, fops);
07b7ddd9
JB		 2109}
2110
27c202ad 2111static struct drm_info_list i915_debugfs_list[] = {
311bd68e 2112 {"i915_capabilities", i915_capabilities, 0},
73aa808f 2113 {"i915_gem_objects", i915_gem_object_info, 0},
08c18323 2114 {"i915_gem_gtt", i915_gem_gtt_info, 0},
1b50247a 2115 {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
433e12f7 2116 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
433e12f7 2117 {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
4e5359cd 2118 {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
2017263e
BG		 2119 {"i915_gem_request", i915_gem_request_info, 0},
2120 {"i915_gem_seqno", i915_gem_seqno_info, 0},
a6172a80 2121 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
2017263e 2122 {"i915_gem_interrupt", i915_interrupt_info, 0},
1ec14ad3
CW		 2123 {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
2124 {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
2125 {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
f97108d1
JB		 2126 {"i915_rstdby_delays", i915_rstdby_delays, 0},
2127 {"i915_cur_delayinfo", i915_cur_delayinfo, 0},
2128 {"i915_delayfreq_table", i915_delayfreq_table, 0},
2129 {"i915_inttoext_table", i915_inttoext_table, 0},
2130 {"i915_drpc_info", i915_drpc_info, 0},
7648fa99 2131 {"i915_emon_status", i915_emon_status, 0},
23b2f8bb 2132 {"i915_ring_freq_table", i915_ring_freq_table, 0},
7648fa99 2133 {"i915_gfxec", i915_gfxec, 0},
b5e50c3f 2134 {"i915_fbc_status", i915_fbc_status, 0},
4a9bef37 2135 {"i915_sr_status", i915_sr_status, 0},
44834a67 2136 {"i915_opregion", i915_opregion, 0},
37811fcc 2137 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
e76d3630 2138 {"i915_context_status", i915_context_status, 0},
6d794d42 2139 {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0},
ea16a3cd 2140 {"i915_swizzle_info", i915_swizzle_info, 0},
3cf17fc5 2141 {"i915_ppgtt_info", i915_ppgtt_info, 0},
57f350b6 2142 {"i915_dpio", i915_dpio_info, 0},
2017263e 2143};
27c202ad 2144#define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
2017263e 2145
27c202ad 2146int i915_debugfs_init(struct drm_minor *minor)
2017263e 2147{
f3cd474b
CW		 2148 int ret;
2149
6a9c308d
DV		 2150 ret = i915_debugfs_create(minor->debugfs_root, minor,
2151 "i915_wedged",
2152 &i915_wedged_fops);
f3cd474b
CW		 2153 if (ret)
2154 return ret;
2155
6d794d42 2156 ret = i915_forcewake_create(minor->debugfs_root, minor);
358733e9
JB		 2157 if (ret)
2158 return ret;
6a9c308d
DV		 2159
2160 ret = i915_debugfs_create(minor->debugfs_root, minor,
2161 "i915_max_freq",
2162 &i915_max_freq_fops);
07b7ddd9
JB		 2163 if (ret)
2164 return ret;
6a9c308d 2165
1523c310
JB		 2166 ret = i915_debugfs_create(minor->debugfs_root, minor,
2167 "i915_min_freq",
2168 &i915_min_freq_fops);
2169 if (ret)
2170 return ret;
2171
6a9c308d
DV		 2172 ret = i915_debugfs_create(minor->debugfs_root, minor,
2173 "i915_cache_sharing",
2174 &i915_cache_sharing_fops);
6d794d42
BW		 2175 if (ret)
2176 return ret;
004777cb 2177
e5eb3d63
DV		 2178 ret = i915_debugfs_create(minor->debugfs_root, minor,
2179 "i915_ring_stop",
2180 &i915_ring_stop_fops);
2181 if (ret)
2182 return ret;
6d794d42 2183
d5442303
DV		 2184 ret = i915_debugfs_create(minor->debugfs_root, minor,
2185 "i915_error_state",
2186 &i915_error_state_fops);
2187 if (ret)
2188 return ret;
2189
40633219
MK		 2190 ret = i915_debugfs_create(minor->debugfs_root, minor,
2191 "i915_next_seqno",
2192 &i915_next_seqno_fops);
2193 if (ret)
2194 return ret;
2195
27c202ad
BG		 2196 return drm_debugfs_create_files(i915_debugfs_list,
2197 I915_DEBUGFS_ENTRIES,
2017263e
BG		 2198 minor->debugfs_root, minor);
2199}
2200
27c202ad 2201void i915_debugfs_cleanup(struct drm_minor *minor)
2017263e 2202{
27c202ad
BG		 2203 drm_debugfs_remove_files(i915_debugfs_list,
2204 I915_DEBUGFS_ENTRIES, minor);
6d794d42
BW		 2205 drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
2206 1, minor);
33db679b
KH		 2207 drm_debugfs_remove_files((struct drm_info_list *) &i915_wedged_fops,
2208 1, minor);
358733e9
JB		 2209 drm_debugfs_remove_files((struct drm_info_list *) &i915_max_freq_fops,
2210 1, minor);
1523c310
JB		 2211 drm_debugfs_remove_files((struct drm_info_list *) &i915_min_freq_fops,
2212 1, minor);
07b7ddd9
JB		 2213 drm_debugfs_remove_files((struct drm_info_list *) &i915_cache_sharing_fops,
2214 1, minor);
e5eb3d63
DV		 2215 drm_debugfs_remove_files((struct drm_info_list *) &i915_ring_stop_fops,
2216 1, minor);
6bd459df
DV		 2217 drm_debugfs_remove_files((struct drm_info_list *) &i915_error_state_fops,
2218 1, minor);
40633219
MK		 2219 drm_debugfs_remove_files((struct drm_info_list *) &i915_next_seqno_fops,
2220 1, minor);
2017263e
BG		 2221}
2222
2223#endif /* CONFIG_DEBUG_FS */
Linux kernel - Deliverables
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