Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* i915_dma.c -- DMA support for the I915 -*- linux-c -*- |
2 | */ | |
0d6aa60b | 3 | /* |
1da177e4 LT |
4 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
5 | * All Rights Reserved. | |
bc54fd1a DA |
6 | * |
7 | * Permission is hereby granted, free of charge, to any person obtaining a | |
8 | * copy of this software and associated documentation files (the | |
9 | * "Software"), to deal in the Software without restriction, including | |
10 | * without limitation the rights to use, copy, modify, merge, publish, | |
11 | * distribute, sub license, and/or sell copies of the Software, and to | |
12 | * permit persons to whom the Software is furnished to do so, subject to | |
13 | * the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice (including the | |
16 | * next paragraph) shall be included in all copies or substantial portions | |
17 | * of the Software. | |
18 | * | |
19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
20 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
21 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
22 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
23 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
24 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
25 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
26 | * | |
0d6aa60b | 27 | */ |
1da177e4 | 28 | |
a70491cc JP |
29 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
30 | ||
d1d70677 | 31 | #include <linux/async.h> |
760285e7 DH |
32 | #include <drm/drmP.h> |
33 | #include <drm/drm_crtc_helper.h> | |
34 | #include <drm/drm_fb_helper.h> | |
4f03b1fc | 35 | #include <drm/drm_legacy.h> |
79e53945 | 36 | #include "intel_drv.h" |
760285e7 | 37 | #include <drm/i915_drm.h> |
1da177e4 | 38 | #include "i915_drv.h" |
1c5d22f7 | 39 | #include "i915_trace.h" |
dcdb1674 | 40 | #include <linux/pci.h> |
a4de0526 DV |
41 | #include <linux/console.h> |
42 | #include <linux/vt.h> | |
28d52043 | 43 | #include <linux/vgaarb.h> |
c4804411 ZW |
44 | #include <linux/acpi.h> |
45 | #include <linux/pnp.h> | |
6a9ee8af | 46 | #include <linux/vga_switcheroo.h> |
5a0e3ad6 | 47 | #include <linux/slab.h> |
44834a67 | 48 | #include <acpi/video.h> |
8a187455 PZ |
49 | #include <linux/pm.h> |
50 | #include <linux/pm_runtime.h> | |
4bdc7293 | 51 | #include <linux/oom.h> |
1da177e4 | 52 | |
1da177e4 | 53 | |
c153f45f EA |
54 | static int i915_getparam(struct drm_device *dev, void *data, |
55 | struct drm_file *file_priv) | |
1da177e4 | 56 | { |
4c8a4be9 | 57 | struct drm_i915_private *dev_priv = dev->dev_private; |
c153f45f | 58 | drm_i915_getparam_t *param = data; |
1da177e4 LT |
59 | int value; |
60 | ||
c153f45f | 61 | switch (param->param) { |
1da177e4 | 62 | case I915_PARAM_IRQ_ACTIVE: |
1da177e4 | 63 | case I915_PARAM_ALLOW_BATCHBUFFER: |
0d6aa60b | 64 | case I915_PARAM_LAST_DISPATCH: |
ac883c84 | 65 | /* Reject all old ums/dri params. */ |
5c6c6003 | 66 | return -ENODEV; |
ed4c9c4a | 67 | case I915_PARAM_CHIPSET_ID: |
ffbab09b | 68 | value = dev->pdev->device; |
ed4c9c4a | 69 | break; |
673a394b | 70 | case I915_PARAM_HAS_GEM: |
2e895b17 | 71 | value = 1; |
673a394b | 72 | break; |
0f973f27 JB |
73 | case I915_PARAM_NUM_FENCES_AVAIL: |
74 | value = dev_priv->num_fence_regs - dev_priv->fence_reg_start; | |
75 | break; | |
02e792fb DV |
76 | case I915_PARAM_HAS_OVERLAY: |
77 | value = dev_priv->overlay ? 1 : 0; | |
78 | break; | |
e9560f7c JB |
79 | case I915_PARAM_HAS_PAGEFLIPPING: |
80 | value = 1; | |
81 | break; | |
76446cac JB |
82 | case I915_PARAM_HAS_EXECBUF2: |
83 | /* depends on GEM */ | |
2e895b17 | 84 | value = 1; |
76446cac | 85 | break; |
e3a815fc | 86 | case I915_PARAM_HAS_BSD: |
edc912f5 | 87 | value = intel_ring_initialized(&dev_priv->ring[VCS]); |
e3a815fc | 88 | break; |
549f7365 | 89 | case I915_PARAM_HAS_BLT: |
edc912f5 | 90 | value = intel_ring_initialized(&dev_priv->ring[BCS]); |
549f7365 | 91 | break; |
a1f2cc73 XH |
92 | case I915_PARAM_HAS_VEBOX: |
93 | value = intel_ring_initialized(&dev_priv->ring[VECS]); | |
94 | break; | |
08e16dc8 ZG |
95 | case I915_PARAM_HAS_BSD2: |
96 | value = intel_ring_initialized(&dev_priv->ring[VCS2]); | |
97 | break; | |
a00b10c3 CW |
98 | case I915_PARAM_HAS_RELAXED_FENCING: |
99 | value = 1; | |
100 | break; | |
bbf0c6b3 DV |
101 | case I915_PARAM_HAS_COHERENT_RINGS: |
102 | value = 1; | |
103 | break; | |
72bfa19c CW |
104 | case I915_PARAM_HAS_EXEC_CONSTANTS: |
105 | value = INTEL_INFO(dev)->gen >= 4; | |
106 | break; | |
271d81b8 CW |
107 | case I915_PARAM_HAS_RELAXED_DELTA: |
108 | value = 1; | |
109 | break; | |
ae662d31 EA |
110 | case I915_PARAM_HAS_GEN7_SOL_RESET: |
111 | value = 1; | |
112 | break; | |
3d29b842 ED |
113 | case I915_PARAM_HAS_LLC: |
114 | value = HAS_LLC(dev); | |
115 | break; | |
651d794f CW |
116 | case I915_PARAM_HAS_WT: |
117 | value = HAS_WT(dev); | |
118 | break; | |
777ee96f | 119 | case I915_PARAM_HAS_ALIASING_PPGTT: |
896ab1a5 | 120 | value = USES_PPGTT(dev); |
777ee96f | 121 | break; |
172cf15d BW |
122 | case I915_PARAM_HAS_WAIT_TIMEOUT: |
123 | value = 1; | |
124 | break; | |
2fedbff9 CW |
125 | case I915_PARAM_HAS_SEMAPHORES: |
126 | value = i915_semaphore_is_enabled(dev); | |
127 | break; | |
ec6f1bb9 DA |
128 | case I915_PARAM_HAS_PRIME_VMAP_FLUSH: |
129 | value = 1; | |
130 | break; | |
d7d4eedd CW |
131 | case I915_PARAM_HAS_SECURE_BATCHES: |
132 | value = capable(CAP_SYS_ADMIN); | |
133 | break; | |
b45305fc DV |
134 | case I915_PARAM_HAS_PINNED_BATCHES: |
135 | value = 1; | |
136 | break; | |
ed5982e6 DV |
137 | case I915_PARAM_HAS_EXEC_NO_RELOC: |
138 | value = 1; | |
139 | break; | |
eef90ccb CW |
140 | case I915_PARAM_HAS_EXEC_HANDLE_LUT: |
141 | value = 1; | |
142 | break; | |
d728c8ef BV |
143 | case I915_PARAM_CMD_PARSER_VERSION: |
144 | value = i915_cmd_parser_get_version(); | |
145 | break; | |
6a2c4232 CW |
146 | case I915_PARAM_HAS_COHERENT_PHYS_GTT: |
147 | value = 1; | |
1816f923 AG |
148 | break; |
149 | case I915_PARAM_MMAP_VERSION: | |
150 | value = 1; | |
6a2c4232 | 151 | break; |
1da177e4 | 152 | default: |
e29c32da | 153 | DRM_DEBUG("Unknown parameter %d\n", param->param); |
20caafa6 | 154 | return -EINVAL; |
1da177e4 LT |
155 | } |
156 | ||
1d6ac185 DV |
157 | if (copy_to_user(param->value, &value, sizeof(int))) { |
158 | DRM_ERROR("copy_to_user failed\n"); | |
20caafa6 | 159 | return -EFAULT; |
1da177e4 LT |
160 | } |
161 | ||
162 | return 0; | |
163 | } | |
164 | ||
c153f45f EA |
165 | static int i915_setparam(struct drm_device *dev, void *data, |
166 | struct drm_file *file_priv) | |
1da177e4 | 167 | { |
4c8a4be9 | 168 | struct drm_i915_private *dev_priv = dev->dev_private; |
c153f45f | 169 | drm_i915_setparam_t *param = data; |
1da177e4 | 170 | |
c153f45f | 171 | switch (param->param) { |
1da177e4 | 172 | case I915_SETPARAM_USE_MI_BATCHBUFFER_START: |
1da177e4 | 173 | case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY: |
1da177e4 | 174 | case I915_SETPARAM_ALLOW_BATCHBUFFER: |
ac883c84 | 175 | /* Reject all old ums/dri params. */ |
5c6c6003 CW |
176 | return -ENODEV; |
177 | ||
0f973f27 JB |
178 | case I915_SETPARAM_NUM_USED_FENCES: |
179 | if (param->value > dev_priv->num_fence_regs || | |
180 | param->value < 0) | |
181 | return -EINVAL; | |
182 | /* Userspace can use first N regs */ | |
183 | dev_priv->fence_reg_start = param->value; | |
184 | break; | |
1da177e4 | 185 | default: |
8a4c47f3 | 186 | DRM_DEBUG_DRIVER("unknown parameter %d\n", |
be25ed9c | 187 | param->param); |
20caafa6 | 188 | return -EINVAL; |
1da177e4 LT |
189 | } |
190 | ||
191 | return 0; | |
192 | } | |
193 | ||
ec2a4c3f DA |
194 | static int i915_get_bridge_dev(struct drm_device *dev) |
195 | { | |
196 | struct drm_i915_private *dev_priv = dev->dev_private; | |
197 | ||
0206e353 | 198 | dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0)); |
ec2a4c3f DA |
199 | if (!dev_priv->bridge_dev) { |
200 | DRM_ERROR("bridge device not found\n"); | |
201 | return -1; | |
202 | } | |
203 | return 0; | |
204 | } | |
205 | ||
c4804411 ZW |
206 | #define MCHBAR_I915 0x44 |
207 | #define MCHBAR_I965 0x48 | |
208 | #define MCHBAR_SIZE (4*4096) | |
209 | ||
210 | #define DEVEN_REG 0x54 | |
211 | #define DEVEN_MCHBAR_EN (1 << 28) | |
212 | ||
213 | /* Allocate space for the MCH regs if needed, return nonzero on error */ | |
214 | static int | |
215 | intel_alloc_mchbar_resource(struct drm_device *dev) | |
216 | { | |
4c8a4be9 | 217 | struct drm_i915_private *dev_priv = dev->dev_private; |
a6c45cf0 | 218 | int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915; |
c4804411 ZW |
219 | u32 temp_lo, temp_hi = 0; |
220 | u64 mchbar_addr; | |
a25c25c2 | 221 | int ret; |
c4804411 | 222 | |
a6c45cf0 | 223 | if (INTEL_INFO(dev)->gen >= 4) |
c4804411 ZW |
224 | pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi); |
225 | pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo); | |
226 | mchbar_addr = ((u64)temp_hi << 32) | temp_lo; | |
227 | ||
228 | /* If ACPI doesn't have it, assume we need to allocate it ourselves */ | |
229 | #ifdef CONFIG_PNP | |
230 | if (mchbar_addr && | |
a25c25c2 CW |
231 | pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE)) |
232 | return 0; | |
c4804411 ZW |
233 | #endif |
234 | ||
235 | /* Get some space for it */ | |
a25c25c2 CW |
236 | dev_priv->mch_res.name = "i915 MCHBAR"; |
237 | dev_priv->mch_res.flags = IORESOURCE_MEM; | |
238 | ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus, | |
239 | &dev_priv->mch_res, | |
c4804411 ZW |
240 | MCHBAR_SIZE, MCHBAR_SIZE, |
241 | PCIBIOS_MIN_MEM, | |
a25c25c2 | 242 | 0, pcibios_align_resource, |
c4804411 ZW |
243 | dev_priv->bridge_dev); |
244 | if (ret) { | |
245 | DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret); | |
246 | dev_priv->mch_res.start = 0; | |
a25c25c2 | 247 | return ret; |
c4804411 ZW |
248 | } |
249 | ||
a6c45cf0 | 250 | if (INTEL_INFO(dev)->gen >= 4) |
c4804411 ZW |
251 | pci_write_config_dword(dev_priv->bridge_dev, reg + 4, |
252 | upper_32_bits(dev_priv->mch_res.start)); | |
253 | ||
254 | pci_write_config_dword(dev_priv->bridge_dev, reg, | |
255 | lower_32_bits(dev_priv->mch_res.start)); | |
a25c25c2 | 256 | return 0; |
c4804411 ZW |
257 | } |
258 | ||
259 | /* Setup MCHBAR if possible, return true if we should disable it again */ | |
260 | static void | |
261 | intel_setup_mchbar(struct drm_device *dev) | |
262 | { | |
4c8a4be9 | 263 | struct drm_i915_private *dev_priv = dev->dev_private; |
a6c45cf0 | 264 | int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915; |
c4804411 ZW |
265 | u32 temp; |
266 | bool enabled; | |
267 | ||
11ea8b7d JB |
268 | if (IS_VALLEYVIEW(dev)) |
269 | return; | |
270 | ||
c4804411 ZW |
271 | dev_priv->mchbar_need_disable = false; |
272 | ||
273 | if (IS_I915G(dev) || IS_I915GM(dev)) { | |
274 | pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp); | |
275 | enabled = !!(temp & DEVEN_MCHBAR_EN); | |
276 | } else { | |
277 | pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); | |
278 | enabled = temp & 1; | |
279 | } | |
280 | ||
281 | /* If it's already enabled, don't have to do anything */ | |
282 | if (enabled) | |
283 | return; | |
284 | ||
285 | if (intel_alloc_mchbar_resource(dev)) | |
286 | return; | |
287 | ||
288 | dev_priv->mchbar_need_disable = true; | |
289 | ||
290 | /* Space is allocated or reserved, so enable it. */ | |
291 | if (IS_I915G(dev) || IS_I915GM(dev)) { | |
292 | pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, | |
293 | temp | DEVEN_MCHBAR_EN); | |
294 | } else { | |
295 | pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); | |
296 | pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1); | |
297 | } | |
298 | } | |
299 | ||
300 | static void | |
301 | intel_teardown_mchbar(struct drm_device *dev) | |
302 | { | |
4c8a4be9 | 303 | struct drm_i915_private *dev_priv = dev->dev_private; |
a6c45cf0 | 304 | int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915; |
c4804411 ZW |
305 | u32 temp; |
306 | ||
307 | if (dev_priv->mchbar_need_disable) { | |
308 | if (IS_I915G(dev) || IS_I915GM(dev)) { | |
309 | pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp); | |
310 | temp &= ~DEVEN_MCHBAR_EN; | |
311 | pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp); | |
312 | } else { | |
313 | pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); | |
314 | temp &= ~1; | |
315 | pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp); | |
316 | } | |
317 | } | |
318 | ||
319 | if (dev_priv->mch_res.start) | |
320 | release_resource(&dev_priv->mch_res); | |
321 | } | |
322 | ||
28d52043 DA |
323 | /* true = enable decode, false = disable decoder */ |
324 | static unsigned int i915_vga_set_decode(void *cookie, bool state) | |
325 | { | |
326 | struct drm_device *dev = cookie; | |
327 | ||
328 | intel_modeset_vga_set_state(dev, state); | |
329 | if (state) | |
330 | return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | | |
331 | VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
332 | else | |
333 | return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
334 | } | |
335 | ||
6a9ee8af DA |
336 | static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state) |
337 | { | |
338 | struct drm_device *dev = pci_get_drvdata(pdev); | |
339 | pm_message_t pmm = { .event = PM_EVENT_SUSPEND }; | |
1a5036bf | 340 | |
6a9ee8af | 341 | if (state == VGA_SWITCHEROO_ON) { |
a70491cc | 342 | pr_info("switched on\n"); |
5bcf719b | 343 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; |
6a9ee8af DA |
344 | /* i915 resume handler doesn't set to D0 */ |
345 | pci_set_power_state(dev->pdev, PCI_D0); | |
fc49b3da | 346 | i915_resume_legacy(dev); |
5bcf719b | 347 | dev->switch_power_state = DRM_SWITCH_POWER_ON; |
6a9ee8af | 348 | } else { |
a70491cc | 349 | pr_err("switched off\n"); |
5bcf719b | 350 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; |
fc49b3da | 351 | i915_suspend_legacy(dev, pmm); |
5bcf719b | 352 | dev->switch_power_state = DRM_SWITCH_POWER_OFF; |
6a9ee8af DA |
353 | } |
354 | } | |
355 | ||
356 | static bool i915_switcheroo_can_switch(struct pci_dev *pdev) | |
357 | { | |
358 | struct drm_device *dev = pci_get_drvdata(pdev); | |
6a9ee8af | 359 | |
fc8fd40e DV |
360 | /* |
361 | * FIXME: open_count is protected by drm_global_mutex but that would lead to | |
362 | * locking inversion with the driver load path. And the access here is | |
363 | * completely racy anyway. So don't bother with locking for now. | |
364 | */ | |
365 | return dev->open_count == 0; | |
6a9ee8af DA |
366 | } |
367 | ||
26ec685f TI |
368 | static const struct vga_switcheroo_client_ops i915_switcheroo_ops = { |
369 | .set_gpu_state = i915_switcheroo_set_state, | |
370 | .reprobe = NULL, | |
371 | .can_switch = i915_switcheroo_can_switch, | |
372 | }; | |
373 | ||
2c7111db CW |
374 | static int i915_load_modeset_init(struct drm_device *dev) |
375 | { | |
376 | struct drm_i915_private *dev_priv = dev->dev_private; | |
377 | int ret; | |
79e53945 | 378 | |
6d139a87 | 379 | ret = intel_parse_bios(dev); |
79e53945 JB |
380 | if (ret) |
381 | DRM_INFO("failed to find VBIOS tables\n"); | |
382 | ||
934f992c CW |
383 | /* If we have > 1 VGA cards, then we need to arbitrate access |
384 | * to the common VGA resources. | |
385 | * | |
386 | * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA), | |
387 | * then we do not take part in VGA arbitration and the | |
388 | * vga_client_register() fails with -ENODEV. | |
389 | */ | |
ebff5fa9 DA |
390 | ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode); |
391 | if (ret && ret != -ENODEV) | |
392 | goto out; | |
28d52043 | 393 | |
723bfd70 JB |
394 | intel_register_dsm_handler(); |
395 | ||
0d69704a | 396 | ret = vga_switcheroo_register_client(dev->pdev, &i915_switcheroo_ops, false); |
6a9ee8af | 397 | if (ret) |
5a79395b | 398 | goto cleanup_vga_client; |
6a9ee8af | 399 | |
9797fbfb CW |
400 | /* Initialise stolen first so that we may reserve preallocated |
401 | * objects for the BIOS to KMS transition. | |
402 | */ | |
403 | ret = i915_gem_init_stolen(dev); | |
404 | if (ret) | |
405 | goto cleanup_vga_switcheroo; | |
406 | ||
e13192f6 ID |
407 | intel_power_domains_init_hw(dev_priv); |
408 | ||
2aeb7d3a | 409 | ret = intel_irq_install(dev_priv); |
52d7eced DV |
410 | if (ret) |
411 | goto cleanup_gem_stolen; | |
412 | ||
413 | /* Important: The output setup functions called by modeset_init need | |
414 | * working irqs for e.g. gmbus and dp aux transfers. */ | |
b01f2c3a JB |
415 | intel_modeset_init(dev); |
416 | ||
1070a42b | 417 | ret = i915_gem_init(dev); |
79e53945 | 418 | if (ret) |
713028b3 | 419 | goto cleanup_irq; |
2c7111db | 420 | |
52d7eced | 421 | intel_modeset_gem_init(dev); |
2c7111db | 422 | |
79e53945 JB |
423 | /* Always safe in the mode setting case. */ |
424 | /* FIXME: do pre/post-mode set stuff in core KMS code */ | |
ba0bf120 | 425 | dev->vblank_disable_allowed = true; |
713028b3 | 426 | if (INTEL_INFO(dev)->num_pipes == 0) |
e3c74757 | 427 | return 0; |
79e53945 | 428 | |
5a79395b CW |
429 | ret = intel_fbdev_init(dev); |
430 | if (ret) | |
52d7eced DV |
431 | goto cleanup_gem; |
432 | ||
20afbda2 | 433 | /* Only enable hotplug handling once the fbdev is fully set up. */ |
b963291c | 434 | intel_hpd_init(dev_priv); |
20afbda2 DV |
435 | |
436 | /* | |
437 | * Some ports require correctly set-up hpd registers for detection to | |
438 | * work properly (leading to ghost connected connector status), e.g. VGA | |
439 | * on gm45. Hence we can only set up the initial fbdev config after hpd | |
440 | * irqs are fully enabled. Now we should scan for the initial config | |
441 | * only once hotplug handling is enabled, but due to screwed-up locking | |
442 | * around kms/fbdev init we can't protect the fdbev initial config | |
443 | * scanning against hotplug events. Hence do this first and ignore the | |
444 | * tiny window where we will loose hotplug notifactions. | |
445 | */ | |
d1d70677 | 446 | async_schedule(intel_fbdev_initial_config, dev_priv); |
20afbda2 | 447 | |
eb1f8e4f | 448 | drm_kms_helper_poll_init(dev); |
87acb0a5 | 449 | |
79e53945 JB |
450 | return 0; |
451 | ||
2c7111db CW |
452 | cleanup_gem: |
453 | mutex_lock(&dev->struct_mutex); | |
454 | i915_gem_cleanup_ringbuffer(dev); | |
55d23285 | 455 | i915_gem_context_fini(dev); |
2c7111db | 456 | mutex_unlock(&dev->struct_mutex); |
713028b3 | 457 | cleanup_irq: |
52d7eced | 458 | drm_irq_uninstall(dev); |
9797fbfb CW |
459 | cleanup_gem_stolen: |
460 | i915_gem_cleanup_stolen(dev); | |
5a79395b CW |
461 | cleanup_vga_switcheroo: |
462 | vga_switcheroo_unregister_client(dev->pdev); | |
463 | cleanup_vga_client: | |
464 | vga_client_register(dev->pdev, NULL, NULL, NULL); | |
79e53945 JB |
465 | out: |
466 | return ret; | |
467 | } | |
468 | ||
243eaf38 | 469 | #if IS_ENABLED(CONFIG_FB) |
f96de58f | 470 | static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv) |
e188719a DV |
471 | { |
472 | struct apertures_struct *ap; | |
473 | struct pci_dev *pdev = dev_priv->dev->pdev; | |
474 | bool primary; | |
f96de58f | 475 | int ret; |
e188719a DV |
476 | |
477 | ap = alloc_apertures(1); | |
478 | if (!ap) | |
f96de58f | 479 | return -ENOMEM; |
e188719a | 480 | |
dabb7a91 | 481 | ap->ranges[0].base = dev_priv->gtt.mappable_base; |
f64e2922 | 482 | ap->ranges[0].size = dev_priv->gtt.mappable_end; |
93d18799 | 483 | |
e188719a DV |
484 | primary = |
485 | pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW; | |
486 | ||
f96de58f | 487 | ret = remove_conflicting_framebuffers(ap, "inteldrmfb", primary); |
e188719a DV |
488 | |
489 | kfree(ap); | |
f96de58f CW |
490 | |
491 | return ret; | |
e188719a | 492 | } |
4520f53a | 493 | #else |
f96de58f | 494 | static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv) |
4520f53a | 495 | { |
f96de58f | 496 | return 0; |
4520f53a DV |
497 | } |
498 | #endif | |
e188719a | 499 | |
a4de0526 DV |
500 | #if !defined(CONFIG_VGA_CONSOLE) |
501 | static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv) | |
502 | { | |
503 | return 0; | |
504 | } | |
505 | #elif !defined(CONFIG_DUMMY_CONSOLE) | |
506 | static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv) | |
507 | { | |
508 | return -ENODEV; | |
509 | } | |
510 | #else | |
511 | static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv) | |
512 | { | |
1bb9e632 | 513 | int ret = 0; |
a4de0526 DV |
514 | |
515 | DRM_INFO("Replacing VGA console driver\n"); | |
516 | ||
517 | console_lock(); | |
1bb9e632 DV |
518 | if (con_is_bound(&vga_con)) |
519 | ret = do_take_over_console(&dummy_con, 0, MAX_NR_CONSOLES - 1, 1); | |
a4de0526 DV |
520 | if (ret == 0) { |
521 | ret = do_unregister_con_driver(&vga_con); | |
522 | ||
523 | /* Ignore "already unregistered". */ | |
524 | if (ret == -ENODEV) | |
525 | ret = 0; | |
526 | } | |
527 | console_unlock(); | |
528 | ||
529 | return ret; | |
530 | } | |
531 | #endif | |
532 | ||
c96ea64e DV |
533 | static void i915_dump_device_info(struct drm_i915_private *dev_priv) |
534 | { | |
5c969aa7 | 535 | const struct intel_device_info *info = &dev_priv->info; |
c96ea64e | 536 | |
e2a5800a DL |
537 | #define PRINT_S(name) "%s" |
538 | #define SEP_EMPTY | |
79fc46df DL |
539 | #define PRINT_FLAG(name) info->name ? #name "," : "" |
540 | #define SEP_COMMA , | |
19c656a1 | 541 | DRM_DEBUG_DRIVER("i915 device info: gen=%i, pciid=0x%04x rev=0x%02x flags=" |
e2a5800a | 542 | DEV_INFO_FOR_EACH_FLAG(PRINT_S, SEP_EMPTY), |
c96ea64e DV |
543 | info->gen, |
544 | dev_priv->dev->pdev->device, | |
19c656a1 | 545 | dev_priv->dev->pdev->revision, |
79fc46df | 546 | DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_COMMA)); |
e2a5800a DL |
547 | #undef PRINT_S |
548 | #undef SEP_EMPTY | |
79fc46df DL |
549 | #undef PRINT_FLAG |
550 | #undef SEP_COMMA | |
c96ea64e DV |
551 | } |
552 | ||
22d3fd46 DL |
553 | /* |
554 | * Determine various intel_device_info fields at runtime. | |
555 | * | |
556 | * Use it when either: | |
557 | * - it's judged too laborious to fill n static structures with the limit | |
558 | * when a simple if statement does the job, | |
559 | * - run-time checks (eg read fuse/strap registers) are needed. | |
658ac4c6 DL |
560 | * |
561 | * This function needs to be called: | |
562 | * - after the MMIO has been setup as we are reading registers, | |
563 | * - after the PCH has been detected, | |
564 | * - before the first usage of the fields it can tweak. | |
22d3fd46 DL |
565 | */ |
566 | static void intel_device_info_runtime_init(struct drm_device *dev) | |
567 | { | |
658ac4c6 | 568 | struct drm_i915_private *dev_priv = dev->dev_private; |
22d3fd46 | 569 | struct intel_device_info *info; |
d615a166 | 570 | enum pipe pipe; |
22d3fd46 | 571 | |
658ac4c6 | 572 | info = (struct intel_device_info *)&dev_priv->info; |
22d3fd46 | 573 | |
1fc8ac3e | 574 | if (IS_VALLEYVIEW(dev) || INTEL_INFO(dev)->gen == 9) |
055e393f | 575 | for_each_pipe(dev_priv, pipe) |
d615a166 DL |
576 | info->num_sprites[pipe] = 2; |
577 | else | |
055e393f | 578 | for_each_pipe(dev_priv, pipe) |
d615a166 | 579 | info->num_sprites[pipe] = 1; |
658ac4c6 | 580 | |
a0bae57f DL |
581 | if (i915.disable_display) { |
582 | DRM_INFO("Display disabled (module parameter)\n"); | |
583 | info->num_pipes = 0; | |
584 | } else if (info->num_pipes > 0 && | |
585 | (INTEL_INFO(dev)->gen == 7 || INTEL_INFO(dev)->gen == 8) && | |
586 | !IS_VALLEYVIEW(dev)) { | |
658ac4c6 DL |
587 | u32 fuse_strap = I915_READ(FUSE_STRAP); |
588 | u32 sfuse_strap = I915_READ(SFUSE_STRAP); | |
589 | ||
590 | /* | |
591 | * SFUSE_STRAP is supposed to have a bit signalling the display | |
592 | * is fused off. Unfortunately it seems that, at least in | |
593 | * certain cases, fused off display means that PCH display | |
594 | * reads don't land anywhere. In that case, we read 0s. | |
595 | * | |
596 | * On CPT/PPT, we can detect this case as SFUSE_STRAP_FUSE_LOCK | |
597 | * should be set when taking over after the firmware. | |
598 | */ | |
599 | if (fuse_strap & ILK_INTERNAL_DISPLAY_DISABLE || | |
600 | sfuse_strap & SFUSE_STRAP_DISPLAY_DISABLED || | |
601 | (dev_priv->pch_type == PCH_CPT && | |
602 | !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) { | |
603 | DRM_INFO("Display fused off, disabling\n"); | |
604 | info->num_pipes = 0; | |
605 | } | |
606 | } | |
693d11c3 D |
607 | |
608 | if (IS_CHERRYVIEW(dev)) { | |
609 | u32 fuse, mask_eu; | |
610 | ||
611 | fuse = I915_READ(CHV_FUSE_GT); | |
612 | mask_eu = fuse & (CHV_FGT_EU_DIS_SS0_R0_MASK | | |
613 | CHV_FGT_EU_DIS_SS0_R1_MASK | | |
614 | CHV_FGT_EU_DIS_SS1_R0_MASK | | |
615 | CHV_FGT_EU_DIS_SS1_R1_MASK); | |
616 | info->eu_total = 16 - hweight32(mask_eu); | |
617 | } | |
22d3fd46 DL |
618 | } |
619 | ||
79e53945 JB |
620 | /** |
621 | * i915_driver_load - setup chip and create an initial config | |
622 | * @dev: DRM device | |
623 | * @flags: startup flags | |
624 | * | |
625 | * The driver load routine has to do several things: | |
626 | * - drive output discovery via intel_modeset_init() | |
627 | * - initialize the memory manager | |
628 | * - allocate initial config memory | |
629 | * - setup the DRM framebuffer with the allocated memory | |
630 | */ | |
84b1fd10 | 631 | int i915_driver_load(struct drm_device *dev, unsigned long flags) |
22eae947 | 632 | { |
ea059a1e | 633 | struct drm_i915_private *dev_priv; |
5c969aa7 | 634 | struct intel_device_info *info, *device_info; |
934d6086 | 635 | int ret = 0, mmio_bar, mmio_size; |
9021f284 | 636 | uint32_t aperture_size; |
fe669bf8 | 637 | |
26394d92 DV |
638 | info = (struct intel_device_info *) flags; |
639 | ||
640 | /* Refuse to load on gen6+ without kms enabled. */ | |
e147accb JN |
641 | if (info->gen >= 6 && !drm_core_check_feature(dev, DRIVER_MODESET)) { |
642 | DRM_INFO("Your hardware requires kernel modesetting (KMS)\n"); | |
643 | DRM_INFO("See CONFIG_DRM_I915_KMS, nomodeset, and i915.modeset parameters\n"); | |
26394d92 | 644 | return -ENODEV; |
e147accb | 645 | } |
26394d92 | 646 | |
24986ee0 DV |
647 | /* UMS needs agp support. */ |
648 | if (!drm_core_check_feature(dev, DRIVER_MODESET) && !dev->agp) | |
649 | return -EINVAL; | |
650 | ||
b14c5679 | 651 | dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL); |
ba8bbcf6 JB |
652 | if (dev_priv == NULL) |
653 | return -ENOMEM; | |
654 | ||
755f68f4 | 655 | dev->dev_private = dev_priv; |
673a394b | 656 | dev_priv->dev = dev; |
5c969aa7 | 657 | |
87f1f465 | 658 | /* Setup the write-once "constant" device info */ |
5c969aa7 | 659 | device_info = (struct intel_device_info *)&dev_priv->info; |
87f1f465 CW |
660 | memcpy(device_info, info, sizeof(dev_priv->info)); |
661 | device_info->device_id = dev->pdev->device; | |
ba8bbcf6 | 662 | |
7dcd2677 KK |
663 | spin_lock_init(&dev_priv->irq_lock); |
664 | spin_lock_init(&dev_priv->gpu_error.lock); | |
07f11d49 | 665 | mutex_init(&dev_priv->backlight_lock); |
907b28c5 | 666 | spin_lock_init(&dev_priv->uncore.lock); |
c20e8355 | 667 | spin_lock_init(&dev_priv->mm.object_stat_lock); |
84c33a64 | 668 | spin_lock_init(&dev_priv->mmio_flip_lock); |
7dcd2677 | 669 | mutex_init(&dev_priv->dpio_lock); |
7dcd2677 KK |
670 | mutex_init(&dev_priv->modeset_restore_lock); |
671 | ||
f742a552 | 672 | intel_pm_setup(dev); |
c67a470b | 673 | |
07144428 DL |
674 | intel_display_crc_init(dev); |
675 | ||
c96ea64e DV |
676 | i915_dump_device_info(dev_priv); |
677 | ||
ed1c9e2c PZ |
678 | /* Not all pre-production machines fall into this category, only the |
679 | * very first ones. Almost everything should work, except for maybe | |
680 | * suspend/resume. And we don't implement workarounds that affect only | |
681 | * pre-production machines. */ | |
682 | if (IS_HSW_EARLY_SDV(dev)) | |
683 | DRM_INFO("This is an early pre-production Haswell machine. " | |
684 | "It may not be fully functional.\n"); | |
685 | ||
ec2a4c3f DA |
686 | if (i915_get_bridge_dev(dev)) { |
687 | ret = -EIO; | |
688 | goto free_priv; | |
689 | } | |
690 | ||
1e1bd0fd BW |
691 | mmio_bar = IS_GEN2(dev) ? 1 : 0; |
692 | /* Before gen4, the registers and the GTT are behind different BARs. | |
693 | * However, from gen4 onwards, the registers and the GTT are shared | |
694 | * in the same BAR, so we want to restrict this ioremap from | |
695 | * clobbering the GTT which we want ioremap_wc instead. Fortunately, | |
696 | * the register BAR remains the same size for all the earlier | |
697 | * generations up to Ironlake. | |
698 | */ | |
699 | if (info->gen < 5) | |
700 | mmio_size = 512*1024; | |
701 | else | |
702 | mmio_size = 2*1024*1024; | |
703 | ||
704 | dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, mmio_size); | |
705 | if (!dev_priv->regs) { | |
706 | DRM_ERROR("failed to map registers\n"); | |
707 | ret = -EIO; | |
708 | goto put_bridge; | |
709 | } | |
710 | ||
c3d685a7 BW |
711 | /* This must be called before any calls to HAS_PCH_* */ |
712 | intel_detect_pch(dev); | |
713 | ||
714 | intel_uncore_init(dev); | |
715 | ||
e76e9aeb BW |
716 | ret = i915_gem_gtt_init(dev); |
717 | if (ret) | |
cbb47d17 | 718 | goto out_regs; |
e188719a | 719 | |
a4de0526 | 720 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
0485c9dc DV |
721 | /* WARNING: Apparently we must kick fbdev drivers before vgacon, |
722 | * otherwise the vga fbdev driver falls over. */ | |
723 | ret = i915_kick_out_firmware_fb(dev_priv); | |
a4de0526 | 724 | if (ret) { |
0485c9dc | 725 | DRM_ERROR("failed to remove conflicting framebuffer drivers\n"); |
a4de0526 DV |
726 | goto out_gtt; |
727 | } | |
728 | ||
0485c9dc | 729 | ret = i915_kick_out_vgacon(dev_priv); |
f96de58f | 730 | if (ret) { |
0485c9dc | 731 | DRM_ERROR("failed to remove conflicting VGA console\n"); |
f96de58f CW |
732 | goto out_gtt; |
733 | } | |
a4de0526 | 734 | } |
e188719a | 735 | |
466e69b8 DA |
736 | pci_set_master(dev->pdev); |
737 | ||
9f82d238 DV |
738 | /* overlay on gen2 is broken and can't address above 1G */ |
739 | if (IS_GEN2(dev)) | |
740 | dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30)); | |
741 | ||
6927faf3 JN |
742 | /* 965GM sometimes incorrectly writes to hardware status page (HWS) |
743 | * using 32bit addressing, overwriting memory if HWS is located | |
744 | * above 4GB. | |
745 | * | |
746 | * The documentation also mentions an issue with undefined | |
747 | * behaviour if any general state is accessed within a page above 4GB, | |
748 | * which also needs to be handled carefully. | |
749 | */ | |
750 | if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) | |
751 | dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(32)); | |
752 | ||
93d18799 | 753 | aperture_size = dev_priv->gtt.mappable_end; |
71e9339c | 754 | |
5d4545ae BW |
755 | dev_priv->gtt.mappable = |
756 | io_mapping_create_wc(dev_priv->gtt.mappable_base, | |
dd2757f8 | 757 | aperture_size); |
5d4545ae | 758 | if (dev_priv->gtt.mappable == NULL) { |
6644107d | 759 | ret = -EIO; |
cbb47d17 | 760 | goto out_gtt; |
6644107d VP |
761 | } |
762 | ||
911bdf0a BW |
763 | dev_priv->gtt.mtrr = arch_phys_wc_add(dev_priv->gtt.mappable_base, |
764 | aperture_size); | |
19966754 | 765 | |
e642abbf CW |
766 | /* The i915 workqueue is primarily used for batched retirement of |
767 | * requests (and thus managing bo) once the task has been completed | |
768 | * by the GPU. i915_gem_retire_requests() is called directly when we | |
769 | * need high-priority retirement, such as waiting for an explicit | |
770 | * bo. | |
771 | * | |
772 | * It is also used for periodic low-priority events, such as | |
df9c2042 | 773 | * idle-timers and recording error state. |
e642abbf CW |
774 | * |
775 | * All tasks on the workqueue are expected to acquire the dev mutex | |
776 | * so there is no point in running more than one instance of the | |
53621860 | 777 | * workqueue at any time. Use an ordered one. |
e642abbf | 778 | */ |
53621860 | 779 | dev_priv->wq = alloc_ordered_workqueue("i915", 0); |
9c9fe1f8 EA |
780 | if (dev_priv->wq == NULL) { |
781 | DRM_ERROR("Failed to create our workqueue.\n"); | |
782 | ret = -ENOMEM; | |
a7b85d2a | 783 | goto out_mtrrfree; |
9c9fe1f8 EA |
784 | } |
785 | ||
0e32b39c DA |
786 | dev_priv->dp_wq = alloc_ordered_workqueue("i915-dp", 0); |
787 | if (dev_priv->dp_wq == NULL) { | |
788 | DRM_ERROR("Failed to create our dp workqueue.\n"); | |
789 | ret = -ENOMEM; | |
790 | goto out_freewq; | |
791 | } | |
792 | ||
737b1506 CW |
793 | dev_priv->gpu_error.hangcheck_wq = |
794 | alloc_ordered_workqueue("i915-hangcheck", 0); | |
795 | if (dev_priv->gpu_error.hangcheck_wq == NULL) { | |
796 | DRM_ERROR("Failed to create our hangcheck workqueue.\n"); | |
797 | ret = -ENOMEM; | |
798 | goto out_freedpwq; | |
799 | } | |
800 | ||
b963291c | 801 | intel_irq_init(dev_priv); |
78511f2a | 802 | intel_uncore_sanitize(dev); |
9880b7a5 | 803 | |
c4804411 ZW |
804 | /* Try to make sure MCHBAR is enabled before poking at it */ |
805 | intel_setup_mchbar(dev); | |
f899fc64 | 806 | intel_setup_gmbus(dev); |
44834a67 | 807 | intel_opregion_setup(dev); |
c4804411 | 808 | |
6d139a87 BF |
809 | intel_setup_bios(dev); |
810 | ||
673a394b EA |
811 | i915_gem_load(dev); |
812 | ||
ed4cb414 EA |
813 | /* On the 945G/GM, the chipset reports the MSI capability on the |
814 | * integrated graphics even though the support isn't actually there | |
815 | * according to the published specs. It doesn't appear to function | |
816 | * correctly in testing on 945G. | |
817 | * This may be a side effect of MSI having been made available for PEG | |
818 | * and the registers being closely associated. | |
d1ed629f KP |
819 | * |
820 | * According to chipset errata, on the 965GM, MSI interrupts may | |
b60678a7 KP |
821 | * be lost or delayed, but we use them anyways to avoid |
822 | * stuck interrupts on some machines. | |
ed4cb414 | 823 | */ |
b60678a7 | 824 | if (!IS_I945G(dev) && !IS_I945GM(dev)) |
d3e74d02 | 825 | pci_enable_msi(dev->pdev); |
ed4cb414 | 826 | |
22d3fd46 | 827 | intel_device_info_runtime_init(dev); |
7f1f3851 | 828 | |
e3c74757 BW |
829 | if (INTEL_INFO(dev)->num_pipes) { |
830 | ret = drm_vblank_init(dev, INTEL_INFO(dev)->num_pipes); | |
831 | if (ret) | |
832 | goto out_gem_unload; | |
833 | } | |
52440211 | 834 | |
da7e29bd | 835 | intel_power_domains_init(dev_priv); |
a38911a3 | 836 | |
79e53945 | 837 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
53984635 | 838 | ret = i915_load_modeset_init(dev); |
79e53945 JB |
839 | if (ret < 0) { |
840 | DRM_ERROR("failed to init modeset\n"); | |
cbb47d17 | 841 | goto out_power_well; |
79e53945 JB |
842 | } |
843 | } | |
844 | ||
0136db58 BW |
845 | i915_setup_sysfs(dev); |
846 | ||
e3c74757 BW |
847 | if (INTEL_INFO(dev)->num_pipes) { |
848 | /* Must be done after probing outputs */ | |
849 | intel_opregion_init(dev); | |
8e5c2b77 | 850 | acpi_video_register(); |
e3c74757 | 851 | } |
74a365b3 | 852 | |
eb48eb00 DV |
853 | if (IS_GEN5(dev)) |
854 | intel_gpu_ips_init(dev_priv); | |
63ee41d7 | 855 | |
f458ebbc | 856 | intel_runtime_pm_enable(dev_priv); |
8a187455 | 857 | |
58fddc28 ID |
858 | i915_audio_component_init(dev_priv); |
859 | ||
79e53945 JB |
860 | return 0; |
861 | ||
cbb47d17 | 862 | out_power_well: |
f458ebbc | 863 | intel_power_domains_fini(dev_priv); |
cbb47d17 | 864 | drm_vblank_cleanup(dev); |
56e2ea34 | 865 | out_gem_unload: |
4bdc7293 ID |
866 | WARN_ON(unregister_oom_notifier(&dev_priv->mm.oom_notifier)); |
867 | unregister_shrinker(&dev_priv->mm.shrinker); | |
a7b85d2a | 868 | |
56e2ea34 CW |
869 | if (dev->pdev->msi_enabled) |
870 | pci_disable_msi(dev->pdev); | |
871 | ||
872 | intel_teardown_gmbus(dev); | |
873 | intel_teardown_mchbar(dev); | |
22accca0 | 874 | pm_qos_remove_request(&dev_priv->pm_qos); |
737b1506 CW |
875 | destroy_workqueue(dev_priv->gpu_error.hangcheck_wq); |
876 | out_freedpwq: | |
0e32b39c DA |
877 | destroy_workqueue(dev_priv->dp_wq); |
878 | out_freewq: | |
9c9fe1f8 | 879 | destroy_workqueue(dev_priv->wq); |
a7b85d2a | 880 | out_mtrrfree: |
911bdf0a | 881 | arch_phys_wc_del(dev_priv->gtt.mtrr); |
5d4545ae | 882 | io_mapping_free(dev_priv->gtt.mappable); |
cbb47d17 | 883 | out_gtt: |
90d0a0e8 | 884 | i915_global_gtt_cleanup(dev); |
cbb47d17 | 885 | out_regs: |
c3d685a7 | 886 | intel_uncore_fini(dev); |
6dda569f | 887 | pci_iounmap(dev->pdev, dev_priv->regs); |
ec2a4c3f DA |
888 | put_bridge: |
889 | pci_dev_put(dev_priv->bridge_dev); | |
79e53945 | 890 | free_priv: |
cbb47d17 CW |
891 | if (dev_priv->slab) |
892 | kmem_cache_destroy(dev_priv->slab); | |
9a298b2a | 893 | kfree(dev_priv); |
ba8bbcf6 JB |
894 | return ret; |
895 | } | |
896 | ||
897 | int i915_driver_unload(struct drm_device *dev) | |
898 | { | |
899 | struct drm_i915_private *dev_priv = dev->dev_private; | |
c911fc1c | 900 | int ret; |
ba8bbcf6 | 901 | |
58fddc28 ID |
902 | i915_audio_component_cleanup(dev_priv); |
903 | ||
ce58c32b CW |
904 | ret = i915_gem_suspend(dev); |
905 | if (ret) { | |
906 | DRM_ERROR("failed to idle hardware: %d\n", ret); | |
907 | return ret; | |
908 | } | |
909 | ||
41373cd5 | 910 | intel_power_domains_fini(dev_priv); |
8a187455 | 911 | |
eb48eb00 | 912 | intel_gpu_ips_teardown(); |
7648fa99 | 913 | |
0136db58 BW |
914 | i915_teardown_sysfs(dev); |
915 | ||
4bdc7293 ID |
916 | WARN_ON(unregister_oom_notifier(&dev_priv->mm.oom_notifier)); |
917 | unregister_shrinker(&dev_priv->mm.shrinker); | |
17250b71 | 918 | |
5d4545ae | 919 | io_mapping_free(dev_priv->gtt.mappable); |
911bdf0a | 920 | arch_phys_wc_del(dev_priv->gtt.mtrr); |
ab657db1 | 921 | |
44834a67 CW |
922 | acpi_video_unregister(); |
923 | ||
2ebfaf5f | 924 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
7b4f3990 | 925 | intel_fbdev_fini(dev); |
2ebfaf5f PZ |
926 | |
927 | drm_vblank_cleanup(dev); | |
928 | ||
929 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { | |
3d8620cc JB |
930 | intel_modeset_cleanup(dev); |
931 | ||
6363ee6f ZY |
932 | /* |
933 | * free the memory space allocated for the child device | |
934 | * config parsed from VBT | |
935 | */ | |
41aa3448 RV |
936 | if (dev_priv->vbt.child_dev && dev_priv->vbt.child_dev_num) { |
937 | kfree(dev_priv->vbt.child_dev); | |
938 | dev_priv->vbt.child_dev = NULL; | |
939 | dev_priv->vbt.child_dev_num = 0; | |
6363ee6f | 940 | } |
6c0d9350 | 941 | |
6a9ee8af | 942 | vga_switcheroo_unregister_client(dev->pdev); |
28d52043 | 943 | vga_client_register(dev->pdev, NULL, NULL, NULL); |
79e53945 JB |
944 | } |
945 | ||
a8b4899e | 946 | /* Free error state after interrupts are fully disabled. */ |
737b1506 | 947 | cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work); |
a8b4899e | 948 | i915_destroy_error_state(dev); |
bc0c7f14 | 949 | |
ed4cb414 EA |
950 | if (dev->pdev->msi_enabled) |
951 | pci_disable_msi(dev->pdev); | |
952 | ||
44834a67 | 953 | intel_opregion_fini(dev); |
8ee1c3db | 954 | |
79e53945 | 955 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
67e77c5a DV |
956 | /* Flush any outstanding unpin_work. */ |
957 | flush_workqueue(dev_priv->wq); | |
958 | ||
79e53945 JB |
959 | mutex_lock(&dev->struct_mutex); |
960 | i915_gem_cleanup_ringbuffer(dev); | |
78a42377 | 961 | i915_gem_batch_pool_fini(&dev_priv->mm.batch_pool); |
55a66628 | 962 | i915_gem_context_fini(dev); |
79e53945 | 963 | mutex_unlock(&dev->struct_mutex); |
9797fbfb | 964 | i915_gem_cleanup_stolen(dev); |
79e53945 JB |
965 | } |
966 | ||
f899fc64 | 967 | intel_teardown_gmbus(dev); |
c4804411 ZW |
968 | intel_teardown_mchbar(dev); |
969 | ||
0e32b39c | 970 | destroy_workqueue(dev_priv->dp_wq); |
bc0c7f14 | 971 | destroy_workqueue(dev_priv->wq); |
737b1506 | 972 | destroy_workqueue(dev_priv->gpu_error.hangcheck_wq); |
9ee32fea | 973 | pm_qos_remove_request(&dev_priv->pm_qos); |
bc0c7f14 | 974 | |
90d0a0e8 | 975 | i915_global_gtt_cleanup(dev); |
6640aab6 | 976 | |
aec347ab CW |
977 | intel_uncore_fini(dev); |
978 | if (dev_priv->regs != NULL) | |
979 | pci_iounmap(dev->pdev, dev_priv->regs); | |
980 | ||
42dcedd4 CW |
981 | if (dev_priv->slab) |
982 | kmem_cache_destroy(dev_priv->slab); | |
bc0c7f14 | 983 | |
ec2a4c3f | 984 | pci_dev_put(dev_priv->bridge_dev); |
2206e6a1 | 985 | kfree(dev_priv); |
ba8bbcf6 | 986 | |
22eae947 DA |
987 | return 0; |
988 | } | |
989 | ||
f787a5f5 | 990 | int i915_driver_open(struct drm_device *dev, struct drm_file *file) |
673a394b | 991 | { |
b29c19b6 | 992 | int ret; |
673a394b | 993 | |
b29c19b6 CW |
994 | ret = i915_gem_open(dev, file); |
995 | if (ret) | |
996 | return ret; | |
254f965c | 997 | |
673a394b EA |
998 | return 0; |
999 | } | |
1000 | ||
79e53945 JB |
1001 | /** |
1002 | * i915_driver_lastclose - clean up after all DRM clients have exited | |
1003 | * @dev: DRM device | |
1004 | * | |
1005 | * Take care of cleaning up after all DRM clients have exited. In the | |
1006 | * mode setting case, we want to restore the kernel's initial mode (just | |
1007 | * in case the last client left us in a bad state). | |
1008 | * | |
9021f284 | 1009 | * Additionally, in the non-mode setting case, we'll tear down the GTT |
79e53945 JB |
1010 | * and DMA structures, since the kernel won't be using them, and clea |
1011 | * up any GEM state. | |
1012 | */ | |
1a5036bf | 1013 | void i915_driver_lastclose(struct drm_device *dev) |
1da177e4 | 1014 | { |
377e91b2 DV |
1015 | intel_fbdev_restore_mode(dev); |
1016 | vga_switcheroo_process_delayed_switch(); | |
1da177e4 LT |
1017 | } |
1018 | ||
2885f6ac | 1019 | void i915_driver_preclose(struct drm_device *dev, struct drm_file *file) |
1da177e4 | 1020 | { |
0d1430a3 | 1021 | mutex_lock(&dev->struct_mutex); |
2885f6ac JH |
1022 | i915_gem_context_close(dev, file); |
1023 | i915_gem_release(dev, file); | |
0d1430a3 | 1024 | mutex_unlock(&dev->struct_mutex); |
e2fcdaa9 VS |
1025 | |
1026 | if (drm_core_check_feature(dev, DRIVER_MODESET)) | |
1027 | intel_modeset_preclose(dev, file); | |
1da177e4 LT |
1028 | } |
1029 | ||
f787a5f5 | 1030 | void i915_driver_postclose(struct drm_device *dev, struct drm_file *file) |
673a394b | 1031 | { |
f787a5f5 | 1032 | struct drm_i915_file_private *file_priv = file->driver_priv; |
673a394b | 1033 | |
a8ebba75 ZY |
1034 | if (file_priv && file_priv->bsd_ring) |
1035 | file_priv->bsd_ring = NULL; | |
f787a5f5 | 1036 | kfree(file_priv); |
673a394b EA |
1037 | } |
1038 | ||
4feb7659 DV |
1039 | static int |
1040 | i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data, | |
1041 | struct drm_file *file) | |
1042 | { | |
1043 | return -ENODEV; | |
1044 | } | |
1045 | ||
baa70943 | 1046 | const struct drm_ioctl_desc i915_ioctls[] = { |
77f31815 DV |
1047 | DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
1048 | DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH), | |
1049 | DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH), | |
1050 | DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH), | |
1051 | DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH), | |
1052 | DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH), | |
10ba5012 | 1053 | DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH|DRM_RENDER_ALLOW), |
1b2f1489 | 1054 | DRM_IOCTL_DEF_DRV(I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
b2c606fe DV |
1055 | DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH), |
1056 | DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH), | |
1057 | DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
77f31815 | 1058 | DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH), |
b2c606fe | 1059 | DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
d1c1edbc | 1060 | DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
77f31815 DV |
1061 | DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, drm_noop, DRM_AUTH), |
1062 | DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH), | |
1063 | DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
f548c0e9 | 1064 | DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED), |
1b2f1489 | 1065 | DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH|DRM_UNLOCKED), |
10ba5012 | 1066 | DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), |
4feb7659 DV |
1067 | DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED), |
1068 | DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED), | |
10ba5012 KH |
1069 | DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), |
1070 | DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
1071 | DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
1072 | DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
71b14ab6 DV |
1073 | DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED), |
1074 | DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED), | |
10ba5012 KH |
1075 | DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), |
1076 | DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
1077 | DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
1078 | DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
1079 | DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
1080 | DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
1081 | DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
1082 | DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
1083 | DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
1084 | DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
1b2f1489 | 1085 | DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED), |
10ba5012 | 1086 | DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), |
1b2f1489 DA |
1087 | DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED), |
1088 | DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED), | |
8ea30864 JB |
1089 | DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED), |
1090 | DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, intel_sprite_get_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED), | |
10ba5012 KH |
1091 | DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), |
1092 | DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
1093 | DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
1094 | DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
b6359918 | 1095 | DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_get_reset_stats_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), |
5cc9ed4b | 1096 | DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), |
c9dc0f35 CW |
1097 | DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), |
1098 | DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
c94f7029 DA |
1099 | }; |
1100 | ||
f95aeb17 | 1101 | int i915_max_ioctl = ARRAY_SIZE(i915_ioctls); |
cda17380 | 1102 | |
9021f284 DV |
1103 | /* |
1104 | * This is really ugly: Because old userspace abused the linux agp interface to | |
1105 | * manage the gtt, we need to claim that all intel devices are agp. For | |
1106 | * otherwise the drm core refuses to initialize the agp support code. | |
cda17380 | 1107 | */ |
1a5036bf | 1108 | int i915_driver_device_is_agp(struct drm_device *dev) |
cda17380 DA |
1109 | { |
1110 | return 1; | |
1111 | } |