Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* i915_dma.c -- DMA support for the I915 -*- linux-c -*- |
2 | */ | |
0d6aa60b | 3 | /* |
1da177e4 LT |
4 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
5 | * All Rights Reserved. | |
bc54fd1a DA |
6 | * |
7 | * Permission is hereby granted, free of charge, to any person obtaining a | |
8 | * copy of this software and associated documentation files (the | |
9 | * "Software"), to deal in the Software without restriction, including | |
10 | * without limitation the rights to use, copy, modify, merge, publish, | |
11 | * distribute, sub license, and/or sell copies of the Software, and to | |
12 | * permit persons to whom the Software is furnished to do so, subject to | |
13 | * the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice (including the | |
16 | * next paragraph) shall be included in all copies or substantial portions | |
17 | * of the Software. | |
18 | * | |
19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
20 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
21 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
22 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
23 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
24 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
25 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
26 | * | |
0d6aa60b | 27 | */ |
1da177e4 | 28 | |
a70491cc JP |
29 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
30 | ||
d1d70677 | 31 | #include <linux/async.h> |
760285e7 DH |
32 | #include <drm/drmP.h> |
33 | #include <drm/drm_crtc_helper.h> | |
34 | #include <drm/drm_fb_helper.h> | |
4f03b1fc | 35 | #include <drm/drm_legacy.h> |
79e53945 | 36 | #include "intel_drv.h" |
760285e7 | 37 | #include <drm/i915_drm.h> |
1da177e4 | 38 | #include "i915_drv.h" |
e21fd552 | 39 | #include "i915_vgpu.h" |
1c5d22f7 | 40 | #include "i915_trace.h" |
dcdb1674 | 41 | #include <linux/pci.h> |
a4de0526 DV |
42 | #include <linux/console.h> |
43 | #include <linux/vt.h> | |
28d52043 | 44 | #include <linux/vgaarb.h> |
c4804411 ZW |
45 | #include <linux/acpi.h> |
46 | #include <linux/pnp.h> | |
6a9ee8af | 47 | #include <linux/vga_switcheroo.h> |
5a0e3ad6 | 48 | #include <linux/slab.h> |
44834a67 | 49 | #include <acpi/video.h> |
8a187455 PZ |
50 | #include <linux/pm.h> |
51 | #include <linux/pm_runtime.h> | |
4bdc7293 | 52 | #include <linux/oom.h> |
1da177e4 | 53 | |
1da177e4 | 54 | |
c153f45f EA |
55 | static int i915_getparam(struct drm_device *dev, void *data, |
56 | struct drm_file *file_priv) | |
1da177e4 | 57 | { |
4c8a4be9 | 58 | struct drm_i915_private *dev_priv = dev->dev_private; |
c153f45f | 59 | drm_i915_getparam_t *param = data; |
1da177e4 LT |
60 | int value; |
61 | ||
c153f45f | 62 | switch (param->param) { |
1da177e4 | 63 | case I915_PARAM_IRQ_ACTIVE: |
1da177e4 | 64 | case I915_PARAM_ALLOW_BATCHBUFFER: |
0d6aa60b | 65 | case I915_PARAM_LAST_DISPATCH: |
ac883c84 | 66 | /* Reject all old ums/dri params. */ |
5c6c6003 | 67 | return -ENODEV; |
ed4c9c4a | 68 | case I915_PARAM_CHIPSET_ID: |
ffbab09b | 69 | value = dev->pdev->device; |
ed4c9c4a | 70 | break; |
27cd4461 NR |
71 | case I915_PARAM_REVISION: |
72 | value = dev->pdev->revision; | |
73 | break; | |
673a394b | 74 | case I915_PARAM_HAS_GEM: |
2e895b17 | 75 | value = 1; |
673a394b | 76 | break; |
0f973f27 | 77 | case I915_PARAM_NUM_FENCES_AVAIL: |
c668cde5 | 78 | value = dev_priv->num_fence_regs; |
0f973f27 | 79 | break; |
02e792fb DV |
80 | case I915_PARAM_HAS_OVERLAY: |
81 | value = dev_priv->overlay ? 1 : 0; | |
82 | break; | |
e9560f7c JB |
83 | case I915_PARAM_HAS_PAGEFLIPPING: |
84 | value = 1; | |
85 | break; | |
76446cac JB |
86 | case I915_PARAM_HAS_EXECBUF2: |
87 | /* depends on GEM */ | |
2e895b17 | 88 | value = 1; |
76446cac | 89 | break; |
e3a815fc | 90 | case I915_PARAM_HAS_BSD: |
edc912f5 | 91 | value = intel_ring_initialized(&dev_priv->ring[VCS]); |
e3a815fc | 92 | break; |
549f7365 | 93 | case I915_PARAM_HAS_BLT: |
edc912f5 | 94 | value = intel_ring_initialized(&dev_priv->ring[BCS]); |
549f7365 | 95 | break; |
a1f2cc73 XH |
96 | case I915_PARAM_HAS_VEBOX: |
97 | value = intel_ring_initialized(&dev_priv->ring[VECS]); | |
98 | break; | |
08e16dc8 ZG |
99 | case I915_PARAM_HAS_BSD2: |
100 | value = intel_ring_initialized(&dev_priv->ring[VCS2]); | |
101 | break; | |
a00b10c3 CW |
102 | case I915_PARAM_HAS_RELAXED_FENCING: |
103 | value = 1; | |
104 | break; | |
bbf0c6b3 DV |
105 | case I915_PARAM_HAS_COHERENT_RINGS: |
106 | value = 1; | |
107 | break; | |
72bfa19c CW |
108 | case I915_PARAM_HAS_EXEC_CONSTANTS: |
109 | value = INTEL_INFO(dev)->gen >= 4; | |
110 | break; | |
271d81b8 CW |
111 | case I915_PARAM_HAS_RELAXED_DELTA: |
112 | value = 1; | |
113 | break; | |
ae662d31 EA |
114 | case I915_PARAM_HAS_GEN7_SOL_RESET: |
115 | value = 1; | |
116 | break; | |
3d29b842 ED |
117 | case I915_PARAM_HAS_LLC: |
118 | value = HAS_LLC(dev); | |
119 | break; | |
651d794f CW |
120 | case I915_PARAM_HAS_WT: |
121 | value = HAS_WT(dev); | |
122 | break; | |
777ee96f | 123 | case I915_PARAM_HAS_ALIASING_PPGTT: |
896ab1a5 | 124 | value = USES_PPGTT(dev); |
777ee96f | 125 | break; |
172cf15d BW |
126 | case I915_PARAM_HAS_WAIT_TIMEOUT: |
127 | value = 1; | |
128 | break; | |
2fedbff9 CW |
129 | case I915_PARAM_HAS_SEMAPHORES: |
130 | value = i915_semaphore_is_enabled(dev); | |
131 | break; | |
ec6f1bb9 DA |
132 | case I915_PARAM_HAS_PRIME_VMAP_FLUSH: |
133 | value = 1; | |
134 | break; | |
d7d4eedd CW |
135 | case I915_PARAM_HAS_SECURE_BATCHES: |
136 | value = capable(CAP_SYS_ADMIN); | |
137 | break; | |
b45305fc DV |
138 | case I915_PARAM_HAS_PINNED_BATCHES: |
139 | value = 1; | |
140 | break; | |
ed5982e6 DV |
141 | case I915_PARAM_HAS_EXEC_NO_RELOC: |
142 | value = 1; | |
143 | break; | |
eef90ccb CW |
144 | case I915_PARAM_HAS_EXEC_HANDLE_LUT: |
145 | value = 1; | |
146 | break; | |
d728c8ef BV |
147 | case I915_PARAM_CMD_PARSER_VERSION: |
148 | value = i915_cmd_parser_get_version(); | |
149 | break; | |
6a2c4232 CW |
150 | case I915_PARAM_HAS_COHERENT_PHYS_GTT: |
151 | value = 1; | |
1816f923 AG |
152 | break; |
153 | case I915_PARAM_MMAP_VERSION: | |
154 | value = 1; | |
6a2c4232 | 155 | break; |
a1559ffe JM |
156 | case I915_PARAM_SUBSLICE_TOTAL: |
157 | value = INTEL_INFO(dev)->subslice_total; | |
158 | if (!value) | |
159 | return -ENODEV; | |
160 | break; | |
161 | case I915_PARAM_EU_TOTAL: | |
162 | value = INTEL_INFO(dev)->eu_total; | |
163 | if (!value) | |
164 | return -ENODEV; | |
165 | break; | |
49e4d842 CW |
166 | case I915_PARAM_HAS_GPU_RESET: |
167 | value = i915.enable_hangcheck && | |
49e4d842 CW |
168 | intel_has_gpu_reset(dev); |
169 | break; | |
a9ed33ca AJ |
170 | case I915_PARAM_HAS_RESOURCE_STREAMER: |
171 | value = HAS_RESOURCE_STREAMER(dev); | |
172 | break; | |
1da177e4 | 173 | default: |
e29c32da | 174 | DRM_DEBUG("Unknown parameter %d\n", param->param); |
20caafa6 | 175 | return -EINVAL; |
1da177e4 LT |
176 | } |
177 | ||
1d6ac185 DV |
178 | if (copy_to_user(param->value, &value, sizeof(int))) { |
179 | DRM_ERROR("copy_to_user failed\n"); | |
20caafa6 | 180 | return -EFAULT; |
1da177e4 LT |
181 | } |
182 | ||
183 | return 0; | |
184 | } | |
185 | ||
ec2a4c3f DA |
186 | static int i915_get_bridge_dev(struct drm_device *dev) |
187 | { | |
188 | struct drm_i915_private *dev_priv = dev->dev_private; | |
189 | ||
0206e353 | 190 | dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0)); |
ec2a4c3f DA |
191 | if (!dev_priv->bridge_dev) { |
192 | DRM_ERROR("bridge device not found\n"); | |
193 | return -1; | |
194 | } | |
195 | return 0; | |
196 | } | |
197 | ||
c4804411 ZW |
198 | #define MCHBAR_I915 0x44 |
199 | #define MCHBAR_I965 0x48 | |
200 | #define MCHBAR_SIZE (4*4096) | |
201 | ||
202 | #define DEVEN_REG 0x54 | |
203 | #define DEVEN_MCHBAR_EN (1 << 28) | |
204 | ||
205 | /* Allocate space for the MCH regs if needed, return nonzero on error */ | |
206 | static int | |
207 | intel_alloc_mchbar_resource(struct drm_device *dev) | |
208 | { | |
4c8a4be9 | 209 | struct drm_i915_private *dev_priv = dev->dev_private; |
a6c45cf0 | 210 | int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915; |
c4804411 ZW |
211 | u32 temp_lo, temp_hi = 0; |
212 | u64 mchbar_addr; | |
a25c25c2 | 213 | int ret; |
c4804411 | 214 | |
a6c45cf0 | 215 | if (INTEL_INFO(dev)->gen >= 4) |
c4804411 ZW |
216 | pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi); |
217 | pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo); | |
218 | mchbar_addr = ((u64)temp_hi << 32) | temp_lo; | |
219 | ||
220 | /* If ACPI doesn't have it, assume we need to allocate it ourselves */ | |
221 | #ifdef CONFIG_PNP | |
222 | if (mchbar_addr && | |
a25c25c2 CW |
223 | pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE)) |
224 | return 0; | |
c4804411 ZW |
225 | #endif |
226 | ||
227 | /* Get some space for it */ | |
a25c25c2 CW |
228 | dev_priv->mch_res.name = "i915 MCHBAR"; |
229 | dev_priv->mch_res.flags = IORESOURCE_MEM; | |
230 | ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus, | |
231 | &dev_priv->mch_res, | |
c4804411 ZW |
232 | MCHBAR_SIZE, MCHBAR_SIZE, |
233 | PCIBIOS_MIN_MEM, | |
a25c25c2 | 234 | 0, pcibios_align_resource, |
c4804411 ZW |
235 | dev_priv->bridge_dev); |
236 | if (ret) { | |
237 | DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret); | |
238 | dev_priv->mch_res.start = 0; | |
a25c25c2 | 239 | return ret; |
c4804411 ZW |
240 | } |
241 | ||
a6c45cf0 | 242 | if (INTEL_INFO(dev)->gen >= 4) |
c4804411 ZW |
243 | pci_write_config_dword(dev_priv->bridge_dev, reg + 4, |
244 | upper_32_bits(dev_priv->mch_res.start)); | |
245 | ||
246 | pci_write_config_dword(dev_priv->bridge_dev, reg, | |
247 | lower_32_bits(dev_priv->mch_res.start)); | |
a25c25c2 | 248 | return 0; |
c4804411 ZW |
249 | } |
250 | ||
251 | /* Setup MCHBAR if possible, return true if we should disable it again */ | |
252 | static void | |
253 | intel_setup_mchbar(struct drm_device *dev) | |
254 | { | |
4c8a4be9 | 255 | struct drm_i915_private *dev_priv = dev->dev_private; |
a6c45cf0 | 256 | int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915; |
c4804411 ZW |
257 | u32 temp; |
258 | bool enabled; | |
259 | ||
11ea8b7d JB |
260 | if (IS_VALLEYVIEW(dev)) |
261 | return; | |
262 | ||
c4804411 ZW |
263 | dev_priv->mchbar_need_disable = false; |
264 | ||
265 | if (IS_I915G(dev) || IS_I915GM(dev)) { | |
266 | pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp); | |
267 | enabled = !!(temp & DEVEN_MCHBAR_EN); | |
268 | } else { | |
269 | pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); | |
270 | enabled = temp & 1; | |
271 | } | |
272 | ||
273 | /* If it's already enabled, don't have to do anything */ | |
274 | if (enabled) | |
275 | return; | |
276 | ||
277 | if (intel_alloc_mchbar_resource(dev)) | |
278 | return; | |
279 | ||
280 | dev_priv->mchbar_need_disable = true; | |
281 | ||
282 | /* Space is allocated or reserved, so enable it. */ | |
283 | if (IS_I915G(dev) || IS_I915GM(dev)) { | |
284 | pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, | |
285 | temp | DEVEN_MCHBAR_EN); | |
286 | } else { | |
287 | pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); | |
288 | pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1); | |
289 | } | |
290 | } | |
291 | ||
292 | static void | |
293 | intel_teardown_mchbar(struct drm_device *dev) | |
294 | { | |
4c8a4be9 | 295 | struct drm_i915_private *dev_priv = dev->dev_private; |
a6c45cf0 | 296 | int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915; |
c4804411 ZW |
297 | u32 temp; |
298 | ||
299 | if (dev_priv->mchbar_need_disable) { | |
300 | if (IS_I915G(dev) || IS_I915GM(dev)) { | |
301 | pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp); | |
302 | temp &= ~DEVEN_MCHBAR_EN; | |
303 | pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp); | |
304 | } else { | |
305 | pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); | |
306 | temp &= ~1; | |
307 | pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp); | |
308 | } | |
309 | } | |
310 | ||
311 | if (dev_priv->mch_res.start) | |
312 | release_resource(&dev_priv->mch_res); | |
313 | } | |
314 | ||
28d52043 DA |
315 | /* true = enable decode, false = disable decoder */ |
316 | static unsigned int i915_vga_set_decode(void *cookie, bool state) | |
317 | { | |
318 | struct drm_device *dev = cookie; | |
319 | ||
320 | intel_modeset_vga_set_state(dev, state); | |
321 | if (state) | |
322 | return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | | |
323 | VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
324 | else | |
325 | return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
326 | } | |
327 | ||
6a9ee8af DA |
328 | static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state) |
329 | { | |
330 | struct drm_device *dev = pci_get_drvdata(pdev); | |
331 | pm_message_t pmm = { .event = PM_EVENT_SUSPEND }; | |
1a5036bf | 332 | |
6a9ee8af | 333 | if (state == VGA_SWITCHEROO_ON) { |
a70491cc | 334 | pr_info("switched on\n"); |
5bcf719b | 335 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; |
6a9ee8af DA |
336 | /* i915 resume handler doesn't set to D0 */ |
337 | pci_set_power_state(dev->pdev, PCI_D0); | |
1751fcf9 | 338 | i915_resume_switcheroo(dev); |
5bcf719b | 339 | dev->switch_power_state = DRM_SWITCH_POWER_ON; |
6a9ee8af | 340 | } else { |
a70491cc | 341 | pr_err("switched off\n"); |
5bcf719b | 342 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; |
1751fcf9 | 343 | i915_suspend_switcheroo(dev, pmm); |
5bcf719b | 344 | dev->switch_power_state = DRM_SWITCH_POWER_OFF; |
6a9ee8af DA |
345 | } |
346 | } | |
347 | ||
348 | static bool i915_switcheroo_can_switch(struct pci_dev *pdev) | |
349 | { | |
350 | struct drm_device *dev = pci_get_drvdata(pdev); | |
6a9ee8af | 351 | |
fc8fd40e DV |
352 | /* |
353 | * FIXME: open_count is protected by drm_global_mutex but that would lead to | |
354 | * locking inversion with the driver load path. And the access here is | |
355 | * completely racy anyway. So don't bother with locking for now. | |
356 | */ | |
357 | return dev->open_count == 0; | |
6a9ee8af DA |
358 | } |
359 | ||
26ec685f TI |
360 | static const struct vga_switcheroo_client_ops i915_switcheroo_ops = { |
361 | .set_gpu_state = i915_switcheroo_set_state, | |
362 | .reprobe = NULL, | |
363 | .can_switch = i915_switcheroo_can_switch, | |
364 | }; | |
365 | ||
2c7111db CW |
366 | static int i915_load_modeset_init(struct drm_device *dev) |
367 | { | |
368 | struct drm_i915_private *dev_priv = dev->dev_private; | |
369 | int ret; | |
79e53945 | 370 | |
6d139a87 | 371 | ret = intel_parse_bios(dev); |
79e53945 JB |
372 | if (ret) |
373 | DRM_INFO("failed to find VBIOS tables\n"); | |
374 | ||
934f992c CW |
375 | /* If we have > 1 VGA cards, then we need to arbitrate access |
376 | * to the common VGA resources. | |
377 | * | |
378 | * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA), | |
379 | * then we do not take part in VGA arbitration and the | |
380 | * vga_client_register() fails with -ENODEV. | |
381 | */ | |
ebff5fa9 DA |
382 | ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode); |
383 | if (ret && ret != -ENODEV) | |
384 | goto out; | |
28d52043 | 385 | |
723bfd70 JB |
386 | intel_register_dsm_handler(); |
387 | ||
0d69704a | 388 | ret = vga_switcheroo_register_client(dev->pdev, &i915_switcheroo_ops, false); |
6a9ee8af | 389 | if (ret) |
5a79395b | 390 | goto cleanup_vga_client; |
6a9ee8af | 391 | |
9797fbfb CW |
392 | /* Initialise stolen first so that we may reserve preallocated |
393 | * objects for the BIOS to KMS transition. | |
394 | */ | |
395 | ret = i915_gem_init_stolen(dev); | |
396 | if (ret) | |
397 | goto cleanup_vga_switcheroo; | |
398 | ||
e13192f6 ID |
399 | intel_power_domains_init_hw(dev_priv); |
400 | ||
2aeb7d3a | 401 | ret = intel_irq_install(dev_priv); |
52d7eced DV |
402 | if (ret) |
403 | goto cleanup_gem_stolen; | |
404 | ||
405 | /* Important: The output setup functions called by modeset_init need | |
406 | * working irqs for e.g. gmbus and dp aux transfers. */ | |
b01f2c3a JB |
407 | intel_modeset_init(dev); |
408 | ||
33a732f4 | 409 | intel_guc_ucode_init(dev); |
33a732f4 | 410 | |
1070a42b | 411 | ret = i915_gem_init(dev); |
79e53945 | 412 | if (ret) |
713028b3 | 413 | goto cleanup_irq; |
2c7111db | 414 | |
52d7eced | 415 | intel_modeset_gem_init(dev); |
2c7111db | 416 | |
79e53945 JB |
417 | /* Always safe in the mode setting case. */ |
418 | /* FIXME: do pre/post-mode set stuff in core KMS code */ | |
ba0bf120 | 419 | dev->vblank_disable_allowed = true; |
713028b3 | 420 | if (INTEL_INFO(dev)->num_pipes == 0) |
e3c74757 | 421 | return 0; |
79e53945 | 422 | |
5a79395b CW |
423 | ret = intel_fbdev_init(dev); |
424 | if (ret) | |
52d7eced DV |
425 | goto cleanup_gem; |
426 | ||
20afbda2 | 427 | /* Only enable hotplug handling once the fbdev is fully set up. */ |
b963291c | 428 | intel_hpd_init(dev_priv); |
20afbda2 DV |
429 | |
430 | /* | |
431 | * Some ports require correctly set-up hpd registers for detection to | |
432 | * work properly (leading to ghost connected connector status), e.g. VGA | |
433 | * on gm45. Hence we can only set up the initial fbdev config after hpd | |
434 | * irqs are fully enabled. Now we should scan for the initial config | |
435 | * only once hotplug handling is enabled, but due to screwed-up locking | |
436 | * around kms/fbdev init we can't protect the fdbev initial config | |
437 | * scanning against hotplug events. Hence do this first and ignore the | |
438 | * tiny window where we will loose hotplug notifactions. | |
439 | */ | |
d1d70677 | 440 | async_schedule(intel_fbdev_initial_config, dev_priv); |
20afbda2 | 441 | |
eb1f8e4f | 442 | drm_kms_helper_poll_init(dev); |
87acb0a5 | 443 | |
79e53945 JB |
444 | return 0; |
445 | ||
2c7111db CW |
446 | cleanup_gem: |
447 | mutex_lock(&dev->struct_mutex); | |
448 | i915_gem_cleanup_ringbuffer(dev); | |
55d23285 | 449 | i915_gem_context_fini(dev); |
2c7111db | 450 | mutex_unlock(&dev->struct_mutex); |
713028b3 | 451 | cleanup_irq: |
33a732f4 | 452 | intel_guc_ucode_fini(dev); |
52d7eced | 453 | drm_irq_uninstall(dev); |
9797fbfb CW |
454 | cleanup_gem_stolen: |
455 | i915_gem_cleanup_stolen(dev); | |
5a79395b CW |
456 | cleanup_vga_switcheroo: |
457 | vga_switcheroo_unregister_client(dev->pdev); | |
458 | cleanup_vga_client: | |
459 | vga_client_register(dev->pdev, NULL, NULL, NULL); | |
79e53945 JB |
460 | out: |
461 | return ret; | |
462 | } | |
463 | ||
243eaf38 | 464 | #if IS_ENABLED(CONFIG_FB) |
f96de58f | 465 | static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv) |
e188719a DV |
466 | { |
467 | struct apertures_struct *ap; | |
468 | struct pci_dev *pdev = dev_priv->dev->pdev; | |
469 | bool primary; | |
f96de58f | 470 | int ret; |
e188719a DV |
471 | |
472 | ap = alloc_apertures(1); | |
473 | if (!ap) | |
f96de58f | 474 | return -ENOMEM; |
e188719a | 475 | |
dabb7a91 | 476 | ap->ranges[0].base = dev_priv->gtt.mappable_base; |
f64e2922 | 477 | ap->ranges[0].size = dev_priv->gtt.mappable_end; |
93d18799 | 478 | |
e188719a DV |
479 | primary = |
480 | pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW; | |
481 | ||
f96de58f | 482 | ret = remove_conflicting_framebuffers(ap, "inteldrmfb", primary); |
e188719a DV |
483 | |
484 | kfree(ap); | |
f96de58f CW |
485 | |
486 | return ret; | |
e188719a | 487 | } |
4520f53a | 488 | #else |
f96de58f | 489 | static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv) |
4520f53a | 490 | { |
f96de58f | 491 | return 0; |
4520f53a DV |
492 | } |
493 | #endif | |
e188719a | 494 | |
a4de0526 DV |
495 | #if !defined(CONFIG_VGA_CONSOLE) |
496 | static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv) | |
497 | { | |
498 | return 0; | |
499 | } | |
500 | #elif !defined(CONFIG_DUMMY_CONSOLE) | |
501 | static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv) | |
502 | { | |
503 | return -ENODEV; | |
504 | } | |
505 | #else | |
506 | static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv) | |
507 | { | |
1bb9e632 | 508 | int ret = 0; |
a4de0526 DV |
509 | |
510 | DRM_INFO("Replacing VGA console driver\n"); | |
511 | ||
512 | console_lock(); | |
1bb9e632 DV |
513 | if (con_is_bound(&vga_con)) |
514 | ret = do_take_over_console(&dummy_con, 0, MAX_NR_CONSOLES - 1, 1); | |
a4de0526 DV |
515 | if (ret == 0) { |
516 | ret = do_unregister_con_driver(&vga_con); | |
517 | ||
518 | /* Ignore "already unregistered". */ | |
519 | if (ret == -ENODEV) | |
520 | ret = 0; | |
521 | } | |
522 | console_unlock(); | |
523 | ||
524 | return ret; | |
525 | } | |
526 | #endif | |
527 | ||
c96ea64e DV |
528 | static void i915_dump_device_info(struct drm_i915_private *dev_priv) |
529 | { | |
5c969aa7 | 530 | const struct intel_device_info *info = &dev_priv->info; |
c96ea64e | 531 | |
e2a5800a DL |
532 | #define PRINT_S(name) "%s" |
533 | #define SEP_EMPTY | |
79fc46df DL |
534 | #define PRINT_FLAG(name) info->name ? #name "," : "" |
535 | #define SEP_COMMA , | |
19c656a1 | 536 | DRM_DEBUG_DRIVER("i915 device info: gen=%i, pciid=0x%04x rev=0x%02x flags=" |
e2a5800a | 537 | DEV_INFO_FOR_EACH_FLAG(PRINT_S, SEP_EMPTY), |
c96ea64e DV |
538 | info->gen, |
539 | dev_priv->dev->pdev->device, | |
19c656a1 | 540 | dev_priv->dev->pdev->revision, |
79fc46df | 541 | DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_COMMA)); |
e2a5800a DL |
542 | #undef PRINT_S |
543 | #undef SEP_EMPTY | |
79fc46df DL |
544 | #undef PRINT_FLAG |
545 | #undef SEP_COMMA | |
c96ea64e DV |
546 | } |
547 | ||
9705ad8a JM |
548 | static void cherryview_sseu_info_init(struct drm_device *dev) |
549 | { | |
550 | struct drm_i915_private *dev_priv = dev->dev_private; | |
551 | struct intel_device_info *info; | |
552 | u32 fuse, eu_dis; | |
553 | ||
554 | info = (struct intel_device_info *)&dev_priv->info; | |
555 | fuse = I915_READ(CHV_FUSE_GT); | |
556 | ||
557 | info->slice_total = 1; | |
558 | ||
559 | if (!(fuse & CHV_FGT_DISABLE_SS0)) { | |
560 | info->subslice_per_slice++; | |
561 | eu_dis = fuse & (CHV_FGT_EU_DIS_SS0_R0_MASK | | |
562 | CHV_FGT_EU_DIS_SS0_R1_MASK); | |
563 | info->eu_total += 8 - hweight32(eu_dis); | |
564 | } | |
565 | ||
566 | if (!(fuse & CHV_FGT_DISABLE_SS1)) { | |
567 | info->subslice_per_slice++; | |
568 | eu_dis = fuse & (CHV_FGT_EU_DIS_SS1_R0_MASK | | |
569 | CHV_FGT_EU_DIS_SS1_R1_MASK); | |
570 | info->eu_total += 8 - hweight32(eu_dis); | |
571 | } | |
572 | ||
573 | info->subslice_total = info->subslice_per_slice; | |
574 | /* | |
575 | * CHV expected to always have a uniform distribution of EU | |
576 | * across subslices. | |
577 | */ | |
578 | info->eu_per_subslice = info->subslice_total ? | |
579 | info->eu_total / info->subslice_total : | |
580 | 0; | |
581 | /* | |
582 | * CHV supports subslice power gating on devices with more than | |
583 | * one subslice, and supports EU power gating on devices with | |
584 | * more than one EU pair per subslice. | |
585 | */ | |
586 | info->has_slice_pg = 0; | |
587 | info->has_subslice_pg = (info->subslice_total > 1); | |
588 | info->has_eu_pg = (info->eu_per_subslice > 2); | |
589 | } | |
590 | ||
591 | static void gen9_sseu_info_init(struct drm_device *dev) | |
592 | { | |
593 | struct drm_i915_private *dev_priv = dev->dev_private; | |
594 | struct intel_device_info *info; | |
dead16e2 | 595 | int s_max = 3, ss_max = 4, eu_max = 8; |
9705ad8a | 596 | int s, ss; |
dead16e2 JM |
597 | u32 fuse2, s_enable, ss_disable, eu_disable; |
598 | u8 eu_mask = 0xff; | |
599 | ||
9705ad8a JM |
600 | info = (struct intel_device_info *)&dev_priv->info; |
601 | fuse2 = I915_READ(GEN8_FUSE2); | |
602 | s_enable = (fuse2 & GEN8_F2_S_ENA_MASK) >> | |
603 | GEN8_F2_S_ENA_SHIFT; | |
604 | ss_disable = (fuse2 & GEN9_F2_SS_DIS_MASK) >> | |
605 | GEN9_F2_SS_DIS_SHIFT; | |
606 | ||
9705ad8a JM |
607 | info->slice_total = hweight32(s_enable); |
608 | /* | |
609 | * The subslice disable field is global, i.e. it applies | |
610 | * to each of the enabled slices. | |
611 | */ | |
612 | info->subslice_per_slice = ss_max - hweight32(ss_disable); | |
613 | info->subslice_total = info->slice_total * | |
614 | info->subslice_per_slice; | |
615 | ||
616 | /* | |
617 | * Iterate through enabled slices and subslices to | |
618 | * count the total enabled EU. | |
619 | */ | |
620 | for (s = 0; s < s_max; s++) { | |
621 | if (!(s_enable & (0x1 << s))) | |
622 | /* skip disabled slice */ | |
623 | continue; | |
624 | ||
dead16e2 | 625 | eu_disable = I915_READ(GEN9_EU_DISABLE(s)); |
9705ad8a | 626 | for (ss = 0; ss < ss_max; ss++) { |
dead16e2 | 627 | int eu_per_ss; |
9705ad8a JM |
628 | |
629 | if (ss_disable & (0x1 << ss)) | |
630 | /* skip disabled subslice */ | |
631 | continue; | |
632 | ||
dead16e2 JM |
633 | eu_per_ss = eu_max - hweight8((eu_disable >> (ss*8)) & |
634 | eu_mask); | |
9705ad8a JM |
635 | |
636 | /* | |
637 | * Record which subslice(s) has(have) 7 EUs. we | |
638 | * can tune the hash used to spread work among | |
639 | * subslices if they are unbalanced. | |
640 | */ | |
dead16e2 | 641 | if (eu_per_ss == 7) |
9705ad8a JM |
642 | info->subslice_7eu[s] |= 1 << ss; |
643 | ||
dead16e2 | 644 | info->eu_total += eu_per_ss; |
9705ad8a JM |
645 | } |
646 | } | |
647 | ||
648 | /* | |
649 | * SKL is expected to always have a uniform distribution | |
650 | * of EU across subslices with the exception that any one | |
651 | * EU in any one subslice may be fused off for die | |
dead16e2 JM |
652 | * recovery. BXT is expected to be perfectly uniform in EU |
653 | * distribution. | |
9705ad8a JM |
654 | */ |
655 | info->eu_per_subslice = info->subslice_total ? | |
656 | DIV_ROUND_UP(info->eu_total, | |
657 | info->subslice_total) : 0; | |
658 | /* | |
659 | * SKL supports slice power gating on devices with more than | |
660 | * one slice, and supports EU power gating on devices with | |
dead16e2 JM |
661 | * more than one EU pair per subslice. BXT supports subslice |
662 | * power gating on devices with more than one subslice, and | |
663 | * supports EU power gating on devices with more than one EU | |
664 | * pair per subslice. | |
9705ad8a | 665 | */ |
dead16e2 JM |
666 | info->has_slice_pg = (IS_SKYLAKE(dev) && (info->slice_total > 1)); |
667 | info->has_subslice_pg = (IS_BROXTON(dev) && (info->subslice_total > 1)); | |
668 | info->has_eu_pg = (info->eu_per_subslice > 2); | |
9705ad8a JM |
669 | } |
670 | ||
91bedd34 ŁD |
671 | static void broadwell_sseu_info_init(struct drm_device *dev) |
672 | { | |
673 | struct drm_i915_private *dev_priv = dev->dev_private; | |
674 | struct intel_device_info *info; | |
675 | const int s_max = 3, ss_max = 3, eu_max = 8; | |
676 | int s, ss; | |
677 | u32 fuse2, eu_disable[s_max], s_enable, ss_disable; | |
678 | ||
679 | fuse2 = I915_READ(GEN8_FUSE2); | |
680 | s_enable = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT; | |
681 | ss_disable = (fuse2 & GEN8_F2_SS_DIS_MASK) >> GEN8_F2_SS_DIS_SHIFT; | |
682 | ||
683 | eu_disable[0] = I915_READ(GEN8_EU_DISABLE0) & GEN8_EU_DIS0_S0_MASK; | |
684 | eu_disable[1] = (I915_READ(GEN8_EU_DISABLE0) >> GEN8_EU_DIS0_S1_SHIFT) | | |
685 | ((I915_READ(GEN8_EU_DISABLE1) & GEN8_EU_DIS1_S1_MASK) << | |
686 | (32 - GEN8_EU_DIS0_S1_SHIFT)); | |
687 | eu_disable[2] = (I915_READ(GEN8_EU_DISABLE1) >> GEN8_EU_DIS1_S2_SHIFT) | | |
688 | ((I915_READ(GEN8_EU_DISABLE2) & GEN8_EU_DIS2_S2_MASK) << | |
689 | (32 - GEN8_EU_DIS1_S2_SHIFT)); | |
690 | ||
691 | ||
692 | info = (struct intel_device_info *)&dev_priv->info; | |
693 | info->slice_total = hweight32(s_enable); | |
694 | ||
695 | /* | |
696 | * The subslice disable field is global, i.e. it applies | |
697 | * to each of the enabled slices. | |
698 | */ | |
699 | info->subslice_per_slice = ss_max - hweight32(ss_disable); | |
700 | info->subslice_total = info->slice_total * info->subslice_per_slice; | |
701 | ||
702 | /* | |
703 | * Iterate through enabled slices and subslices to | |
704 | * count the total enabled EU. | |
705 | */ | |
706 | for (s = 0; s < s_max; s++) { | |
707 | if (!(s_enable & (0x1 << s))) | |
708 | /* skip disabled slice */ | |
709 | continue; | |
710 | ||
711 | for (ss = 0; ss < ss_max; ss++) { | |
712 | u32 n_disabled; | |
713 | ||
714 | if (ss_disable & (0x1 << ss)) | |
715 | /* skip disabled subslice */ | |
716 | continue; | |
717 | ||
718 | n_disabled = hweight8(eu_disable[s] >> (ss * eu_max)); | |
719 | ||
720 | /* | |
721 | * Record which subslices have 7 EUs. | |
722 | */ | |
723 | if (eu_max - n_disabled == 7) | |
724 | info->subslice_7eu[s] |= 1 << ss; | |
725 | ||
726 | info->eu_total += eu_max - n_disabled; | |
727 | } | |
728 | } | |
729 | ||
730 | /* | |
731 | * BDW is expected to always have a uniform distribution of EU across | |
732 | * subslices with the exception that any one EU in any one subslice may | |
733 | * be fused off for die recovery. | |
734 | */ | |
735 | info->eu_per_subslice = info->subslice_total ? | |
736 | DIV_ROUND_UP(info->eu_total, info->subslice_total) : 0; | |
737 | ||
738 | /* | |
739 | * BDW supports slice power gating on devices with more than | |
740 | * one slice. | |
741 | */ | |
742 | info->has_slice_pg = (info->slice_total > 1); | |
743 | info->has_subslice_pg = 0; | |
744 | info->has_eu_pg = 0; | |
745 | } | |
746 | ||
22d3fd46 DL |
747 | /* |
748 | * Determine various intel_device_info fields at runtime. | |
749 | * | |
750 | * Use it when either: | |
751 | * - it's judged too laborious to fill n static structures with the limit | |
752 | * when a simple if statement does the job, | |
753 | * - run-time checks (eg read fuse/strap registers) are needed. | |
658ac4c6 DL |
754 | * |
755 | * This function needs to be called: | |
756 | * - after the MMIO has been setup as we are reading registers, | |
757 | * - after the PCH has been detected, | |
758 | * - before the first usage of the fields it can tweak. | |
22d3fd46 DL |
759 | */ |
760 | static void intel_device_info_runtime_init(struct drm_device *dev) | |
761 | { | |
658ac4c6 | 762 | struct drm_i915_private *dev_priv = dev->dev_private; |
22d3fd46 | 763 | struct intel_device_info *info; |
d615a166 | 764 | enum pipe pipe; |
22d3fd46 | 765 | |
658ac4c6 | 766 | info = (struct intel_device_info *)&dev_priv->info; |
22d3fd46 | 767 | |
edd43ed8 DL |
768 | /* |
769 | * Skylake and Broxton currently don't expose the topmost plane as its | |
770 | * use is exclusive with the legacy cursor and we only want to expose | |
771 | * one of those, not both. Until we can safely expose the topmost plane | |
772 | * as a DRM_PLANE_TYPE_CURSOR with all the features exposed/supported, | |
773 | * we don't expose the topmost plane at all to prevent ABI breakage | |
774 | * down the line. | |
775 | */ | |
8fb9397d | 776 | if (IS_BROXTON(dev)) { |
edd43ed8 DL |
777 | info->num_sprites[PIPE_A] = 2; |
778 | info->num_sprites[PIPE_B] = 2; | |
779 | info->num_sprites[PIPE_C] = 1; | |
780 | } else if (IS_VALLEYVIEW(dev)) | |
055e393f | 781 | for_each_pipe(dev_priv, pipe) |
d615a166 DL |
782 | info->num_sprites[pipe] = 2; |
783 | else | |
055e393f | 784 | for_each_pipe(dev_priv, pipe) |
d615a166 | 785 | info->num_sprites[pipe] = 1; |
658ac4c6 | 786 | |
a0bae57f DL |
787 | if (i915.disable_display) { |
788 | DRM_INFO("Display disabled (module parameter)\n"); | |
789 | info->num_pipes = 0; | |
790 | } else if (info->num_pipes > 0 && | |
791 | (INTEL_INFO(dev)->gen == 7 || INTEL_INFO(dev)->gen == 8) && | |
792 | !IS_VALLEYVIEW(dev)) { | |
658ac4c6 DL |
793 | u32 fuse_strap = I915_READ(FUSE_STRAP); |
794 | u32 sfuse_strap = I915_READ(SFUSE_STRAP); | |
795 | ||
796 | /* | |
797 | * SFUSE_STRAP is supposed to have a bit signalling the display | |
798 | * is fused off. Unfortunately it seems that, at least in | |
799 | * certain cases, fused off display means that PCH display | |
800 | * reads don't land anywhere. In that case, we read 0s. | |
801 | * | |
802 | * On CPT/PPT, we can detect this case as SFUSE_STRAP_FUSE_LOCK | |
803 | * should be set when taking over after the firmware. | |
804 | */ | |
805 | if (fuse_strap & ILK_INTERNAL_DISPLAY_DISABLE || | |
806 | sfuse_strap & SFUSE_STRAP_DISPLAY_DISABLED || | |
807 | (dev_priv->pch_type == PCH_CPT && | |
808 | !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) { | |
809 | DRM_INFO("Display fused off, disabling\n"); | |
810 | info->num_pipes = 0; | |
811 | } | |
812 | } | |
693d11c3 | 813 | |
3873218f | 814 | /* Initialize slice/subslice/EU info */ |
9705ad8a JM |
815 | if (IS_CHERRYVIEW(dev)) |
816 | cherryview_sseu_info_init(dev); | |
91bedd34 ŁD |
817 | else if (IS_BROADWELL(dev)) |
818 | broadwell_sseu_info_init(dev); | |
dead16e2 | 819 | else if (INTEL_INFO(dev)->gen >= 9) |
9705ad8a | 820 | gen9_sseu_info_init(dev); |
3873218f | 821 | |
3873218f JM |
822 | DRM_DEBUG_DRIVER("slice total: %u\n", info->slice_total); |
823 | DRM_DEBUG_DRIVER("subslice total: %u\n", info->subslice_total); | |
824 | DRM_DEBUG_DRIVER("subslice per slice: %u\n", info->subslice_per_slice); | |
825 | DRM_DEBUG_DRIVER("EU total: %u\n", info->eu_total); | |
826 | DRM_DEBUG_DRIVER("EU per subslice: %u\n", info->eu_per_subslice); | |
827 | DRM_DEBUG_DRIVER("has slice power gating: %s\n", | |
828 | info->has_slice_pg ? "y" : "n"); | |
829 | DRM_DEBUG_DRIVER("has subslice power gating: %s\n", | |
830 | info->has_subslice_pg ? "y" : "n"); | |
831 | DRM_DEBUG_DRIVER("has EU power gating: %s\n", | |
832 | info->has_eu_pg ? "y" : "n"); | |
22d3fd46 DL |
833 | } |
834 | ||
e27f299e VS |
835 | static void intel_init_dpio(struct drm_i915_private *dev_priv) |
836 | { | |
837 | if (!IS_VALLEYVIEW(dev_priv)) | |
838 | return; | |
839 | ||
840 | /* | |
841 | * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C), | |
842 | * CHV x1 PHY (DP/HDMI D) | |
843 | * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C) | |
844 | */ | |
845 | if (IS_CHERRYVIEW(dev_priv)) { | |
846 | DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2; | |
847 | DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO; | |
848 | } else { | |
849 | DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO; | |
850 | } | |
851 | } | |
852 | ||
79e53945 JB |
853 | /** |
854 | * i915_driver_load - setup chip and create an initial config | |
855 | * @dev: DRM device | |
856 | * @flags: startup flags | |
857 | * | |
858 | * The driver load routine has to do several things: | |
859 | * - drive output discovery via intel_modeset_init() | |
860 | * - initialize the memory manager | |
861 | * - allocate initial config memory | |
862 | * - setup the DRM framebuffer with the allocated memory | |
863 | */ | |
84b1fd10 | 864 | int i915_driver_load(struct drm_device *dev, unsigned long flags) |
22eae947 | 865 | { |
ea059a1e | 866 | struct drm_i915_private *dev_priv; |
5c969aa7 | 867 | struct intel_device_info *info, *device_info; |
934d6086 | 868 | int ret = 0, mmio_bar, mmio_size; |
9021f284 | 869 | uint32_t aperture_size; |
fe669bf8 | 870 | |
26394d92 DV |
871 | info = (struct intel_device_info *) flags; |
872 | ||
b14c5679 | 873 | dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL); |
ba8bbcf6 JB |
874 | if (dev_priv == NULL) |
875 | return -ENOMEM; | |
876 | ||
755f68f4 | 877 | dev->dev_private = dev_priv; |
673a394b | 878 | dev_priv->dev = dev; |
5c969aa7 | 879 | |
87f1f465 | 880 | /* Setup the write-once "constant" device info */ |
5c969aa7 | 881 | device_info = (struct intel_device_info *)&dev_priv->info; |
87f1f465 CW |
882 | memcpy(device_info, info, sizeof(dev_priv->info)); |
883 | device_info->device_id = dev->pdev->device; | |
ba8bbcf6 | 884 | |
7dcd2677 KK |
885 | spin_lock_init(&dev_priv->irq_lock); |
886 | spin_lock_init(&dev_priv->gpu_error.lock); | |
07f11d49 | 887 | mutex_init(&dev_priv->backlight_lock); |
907b28c5 | 888 | spin_lock_init(&dev_priv->uncore.lock); |
c20e8355 | 889 | spin_lock_init(&dev_priv->mm.object_stat_lock); |
84c33a64 | 890 | spin_lock_init(&dev_priv->mmio_flip_lock); |
a580516d | 891 | mutex_init(&dev_priv->sb_lock); |
7dcd2677 | 892 | mutex_init(&dev_priv->modeset_restore_lock); |
eb805623 | 893 | mutex_init(&dev_priv->csr_lock); |
4a21ef7d | 894 | mutex_init(&dev_priv->av_mutex); |
7dcd2677 | 895 | |
f742a552 | 896 | intel_pm_setup(dev); |
c67a470b | 897 | |
07144428 DL |
898 | intel_display_crc_init(dev); |
899 | ||
c96ea64e DV |
900 | i915_dump_device_info(dev_priv); |
901 | ||
ed1c9e2c PZ |
902 | /* Not all pre-production machines fall into this category, only the |
903 | * very first ones. Almost everything should work, except for maybe | |
904 | * suspend/resume. And we don't implement workarounds that affect only | |
905 | * pre-production machines. */ | |
906 | if (IS_HSW_EARLY_SDV(dev)) | |
907 | DRM_INFO("This is an early pre-production Haswell machine. " | |
908 | "It may not be fully functional.\n"); | |
909 | ||
ec2a4c3f DA |
910 | if (i915_get_bridge_dev(dev)) { |
911 | ret = -EIO; | |
912 | goto free_priv; | |
913 | } | |
914 | ||
1e1bd0fd BW |
915 | mmio_bar = IS_GEN2(dev) ? 1 : 0; |
916 | /* Before gen4, the registers and the GTT are behind different BARs. | |
917 | * However, from gen4 onwards, the registers and the GTT are shared | |
918 | * in the same BAR, so we want to restrict this ioremap from | |
919 | * clobbering the GTT which we want ioremap_wc instead. Fortunately, | |
920 | * the register BAR remains the same size for all the earlier | |
921 | * generations up to Ironlake. | |
922 | */ | |
923 | if (info->gen < 5) | |
924 | mmio_size = 512*1024; | |
925 | else | |
926 | mmio_size = 2*1024*1024; | |
927 | ||
928 | dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, mmio_size); | |
929 | if (!dev_priv->regs) { | |
930 | DRM_ERROR("failed to map registers\n"); | |
931 | ret = -EIO; | |
932 | goto put_bridge; | |
933 | } | |
934 | ||
c3d685a7 BW |
935 | /* This must be called before any calls to HAS_PCH_* */ |
936 | intel_detect_pch(dev); | |
937 | ||
938 | intel_uncore_init(dev); | |
939 | ||
eb805623 DV |
940 | /* Load CSR Firmware for SKL */ |
941 | intel_csr_ucode_init(dev); | |
942 | ||
e76e9aeb BW |
943 | ret = i915_gem_gtt_init(dev); |
944 | if (ret) | |
eb805623 | 945 | goto out_freecsr; |
e188719a | 946 | |
17fa6463 DV |
947 | /* WARNING: Apparently we must kick fbdev drivers before vgacon, |
948 | * otherwise the vga fbdev driver falls over. */ | |
949 | ret = i915_kick_out_firmware_fb(dev_priv); | |
950 | if (ret) { | |
951 | DRM_ERROR("failed to remove conflicting framebuffer drivers\n"); | |
952 | goto out_gtt; | |
953 | } | |
a4de0526 | 954 | |
17fa6463 DV |
955 | ret = i915_kick_out_vgacon(dev_priv); |
956 | if (ret) { | |
957 | DRM_ERROR("failed to remove conflicting VGA console\n"); | |
958 | goto out_gtt; | |
a4de0526 | 959 | } |
e188719a | 960 | |
466e69b8 DA |
961 | pci_set_master(dev->pdev); |
962 | ||
9f82d238 DV |
963 | /* overlay on gen2 is broken and can't address above 1G */ |
964 | if (IS_GEN2(dev)) | |
965 | dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30)); | |
966 | ||
6927faf3 JN |
967 | /* 965GM sometimes incorrectly writes to hardware status page (HWS) |
968 | * using 32bit addressing, overwriting memory if HWS is located | |
969 | * above 4GB. | |
970 | * | |
971 | * The documentation also mentions an issue with undefined | |
972 | * behaviour if any general state is accessed within a page above 4GB, | |
973 | * which also needs to be handled carefully. | |
974 | */ | |
975 | if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) | |
976 | dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(32)); | |
977 | ||
93d18799 | 978 | aperture_size = dev_priv->gtt.mappable_end; |
71e9339c | 979 | |
5d4545ae BW |
980 | dev_priv->gtt.mappable = |
981 | io_mapping_create_wc(dev_priv->gtt.mappable_base, | |
dd2757f8 | 982 | aperture_size); |
5d4545ae | 983 | if (dev_priv->gtt.mappable == NULL) { |
6644107d | 984 | ret = -EIO; |
cbb47d17 | 985 | goto out_gtt; |
6644107d VP |
986 | } |
987 | ||
911bdf0a BW |
988 | dev_priv->gtt.mtrr = arch_phys_wc_add(dev_priv->gtt.mappable_base, |
989 | aperture_size); | |
19966754 | 990 | |
e642abbf CW |
991 | /* The i915 workqueue is primarily used for batched retirement of |
992 | * requests (and thus managing bo) once the task has been completed | |
993 | * by the GPU. i915_gem_retire_requests() is called directly when we | |
994 | * need high-priority retirement, such as waiting for an explicit | |
995 | * bo. | |
996 | * | |
997 | * It is also used for periodic low-priority events, such as | |
df9c2042 | 998 | * idle-timers and recording error state. |
e642abbf CW |
999 | * |
1000 | * All tasks on the workqueue are expected to acquire the dev mutex | |
1001 | * so there is no point in running more than one instance of the | |
53621860 | 1002 | * workqueue at any time. Use an ordered one. |
e642abbf | 1003 | */ |
53621860 | 1004 | dev_priv->wq = alloc_ordered_workqueue("i915", 0); |
9c9fe1f8 EA |
1005 | if (dev_priv->wq == NULL) { |
1006 | DRM_ERROR("Failed to create our workqueue.\n"); | |
1007 | ret = -ENOMEM; | |
a7b85d2a | 1008 | goto out_mtrrfree; |
9c9fe1f8 EA |
1009 | } |
1010 | ||
5fcece80 JN |
1011 | dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0); |
1012 | if (dev_priv->hotplug.dp_wq == NULL) { | |
0e32b39c DA |
1013 | DRM_ERROR("Failed to create our dp workqueue.\n"); |
1014 | ret = -ENOMEM; | |
1015 | goto out_freewq; | |
1016 | } | |
1017 | ||
737b1506 CW |
1018 | dev_priv->gpu_error.hangcheck_wq = |
1019 | alloc_ordered_workqueue("i915-hangcheck", 0); | |
1020 | if (dev_priv->gpu_error.hangcheck_wq == NULL) { | |
1021 | DRM_ERROR("Failed to create our hangcheck workqueue.\n"); | |
1022 | ret = -ENOMEM; | |
1023 | goto out_freedpwq; | |
1024 | } | |
1025 | ||
b963291c | 1026 | intel_irq_init(dev_priv); |
78511f2a | 1027 | intel_uncore_sanitize(dev); |
9880b7a5 | 1028 | |
c4804411 ZW |
1029 | /* Try to make sure MCHBAR is enabled before poking at it */ |
1030 | intel_setup_mchbar(dev); | |
f899fc64 | 1031 | intel_setup_gmbus(dev); |
44834a67 | 1032 | intel_opregion_setup(dev); |
c4804411 | 1033 | |
673a394b EA |
1034 | i915_gem_load(dev); |
1035 | ||
ed4cb414 EA |
1036 | /* On the 945G/GM, the chipset reports the MSI capability on the |
1037 | * integrated graphics even though the support isn't actually there | |
1038 | * according to the published specs. It doesn't appear to function | |
1039 | * correctly in testing on 945G. | |
1040 | * This may be a side effect of MSI having been made available for PEG | |
1041 | * and the registers being closely associated. | |
d1ed629f KP |
1042 | * |
1043 | * According to chipset errata, on the 965GM, MSI interrupts may | |
b60678a7 KP |
1044 | * be lost or delayed, but we use them anyways to avoid |
1045 | * stuck interrupts on some machines. | |
ed4cb414 | 1046 | */ |
b60678a7 | 1047 | if (!IS_I945G(dev) && !IS_I945GM(dev)) |
d3e74d02 | 1048 | pci_enable_msi(dev->pdev); |
ed4cb414 | 1049 | |
22d3fd46 | 1050 | intel_device_info_runtime_init(dev); |
7f1f3851 | 1051 | |
e27f299e VS |
1052 | intel_init_dpio(dev_priv); |
1053 | ||
e3c74757 BW |
1054 | if (INTEL_INFO(dev)->num_pipes) { |
1055 | ret = drm_vblank_init(dev, INTEL_INFO(dev)->num_pipes); | |
1056 | if (ret) | |
1057 | goto out_gem_unload; | |
1058 | } | |
52440211 | 1059 | |
da7e29bd | 1060 | intel_power_domains_init(dev_priv); |
a38911a3 | 1061 | |
17fa6463 DV |
1062 | ret = i915_load_modeset_init(dev); |
1063 | if (ret < 0) { | |
1064 | DRM_ERROR("failed to init modeset\n"); | |
1065 | goto out_power_well; | |
79e53945 JB |
1066 | } |
1067 | ||
e21fd552 YZ |
1068 | /* |
1069 | * Notify a valid surface after modesetting, | |
1070 | * when running inside a VM. | |
1071 | */ | |
1072 | if (intel_vgpu_active(dev)) | |
1073 | I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY); | |
1074 | ||
0136db58 BW |
1075 | i915_setup_sysfs(dev); |
1076 | ||
e3c74757 BW |
1077 | if (INTEL_INFO(dev)->num_pipes) { |
1078 | /* Must be done after probing outputs */ | |
1079 | intel_opregion_init(dev); | |
8e5c2b77 | 1080 | acpi_video_register(); |
e3c74757 | 1081 | } |
74a365b3 | 1082 | |
eb48eb00 DV |
1083 | if (IS_GEN5(dev)) |
1084 | intel_gpu_ips_init(dev_priv); | |
63ee41d7 | 1085 | |
f458ebbc | 1086 | intel_runtime_pm_enable(dev_priv); |
8a187455 | 1087 | |
58fddc28 ID |
1088 | i915_audio_component_init(dev_priv); |
1089 | ||
79e53945 JB |
1090 | return 0; |
1091 | ||
cbb47d17 | 1092 | out_power_well: |
f458ebbc | 1093 | intel_power_domains_fini(dev_priv); |
cbb47d17 | 1094 | drm_vblank_cleanup(dev); |
56e2ea34 | 1095 | out_gem_unload: |
4bdc7293 ID |
1096 | WARN_ON(unregister_oom_notifier(&dev_priv->mm.oom_notifier)); |
1097 | unregister_shrinker(&dev_priv->mm.shrinker); | |
a7b85d2a | 1098 | |
56e2ea34 CW |
1099 | if (dev->pdev->msi_enabled) |
1100 | pci_disable_msi(dev->pdev); | |
1101 | ||
1102 | intel_teardown_gmbus(dev); | |
1103 | intel_teardown_mchbar(dev); | |
22accca0 | 1104 | pm_qos_remove_request(&dev_priv->pm_qos); |
737b1506 CW |
1105 | destroy_workqueue(dev_priv->gpu_error.hangcheck_wq); |
1106 | out_freedpwq: | |
5fcece80 | 1107 | destroy_workqueue(dev_priv->hotplug.dp_wq); |
0e32b39c | 1108 | out_freewq: |
9c9fe1f8 | 1109 | destroy_workqueue(dev_priv->wq); |
a7b85d2a | 1110 | out_mtrrfree: |
911bdf0a | 1111 | arch_phys_wc_del(dev_priv->gtt.mtrr); |
5d4545ae | 1112 | io_mapping_free(dev_priv->gtt.mappable); |
cbb47d17 | 1113 | out_gtt: |
90d0a0e8 | 1114 | i915_global_gtt_cleanup(dev); |
eb805623 DV |
1115 | out_freecsr: |
1116 | intel_csr_ucode_fini(dev); | |
c3d685a7 | 1117 | intel_uncore_fini(dev); |
6dda569f | 1118 | pci_iounmap(dev->pdev, dev_priv->regs); |
ec2a4c3f DA |
1119 | put_bridge: |
1120 | pci_dev_put(dev_priv->bridge_dev); | |
79e53945 | 1121 | free_priv: |
76b1cf21 JL |
1122 | kmem_cache_destroy(dev_priv->requests); |
1123 | kmem_cache_destroy(dev_priv->vmas); | |
1124 | kmem_cache_destroy(dev_priv->objects); | |
9a298b2a | 1125 | kfree(dev_priv); |
ba8bbcf6 JB |
1126 | return ret; |
1127 | } | |
1128 | ||
1129 | int i915_driver_unload(struct drm_device *dev) | |
1130 | { | |
1131 | struct drm_i915_private *dev_priv = dev->dev_private; | |
c911fc1c | 1132 | int ret; |
ba8bbcf6 | 1133 | |
58fddc28 ID |
1134 | i915_audio_component_cleanup(dev_priv); |
1135 | ||
ce58c32b CW |
1136 | ret = i915_gem_suspend(dev); |
1137 | if (ret) { | |
1138 | DRM_ERROR("failed to idle hardware: %d\n", ret); | |
1139 | return ret; | |
1140 | } | |
1141 | ||
41373cd5 | 1142 | intel_power_domains_fini(dev_priv); |
8a187455 | 1143 | |
eb48eb00 | 1144 | intel_gpu_ips_teardown(); |
7648fa99 | 1145 | |
0136db58 BW |
1146 | i915_teardown_sysfs(dev); |
1147 | ||
4bdc7293 ID |
1148 | WARN_ON(unregister_oom_notifier(&dev_priv->mm.oom_notifier)); |
1149 | unregister_shrinker(&dev_priv->mm.shrinker); | |
17250b71 | 1150 | |
5d4545ae | 1151 | io_mapping_free(dev_priv->gtt.mappable); |
911bdf0a | 1152 | arch_phys_wc_del(dev_priv->gtt.mtrr); |
ab657db1 | 1153 | |
44834a67 CW |
1154 | acpi_video_unregister(); |
1155 | ||
17fa6463 | 1156 | intel_fbdev_fini(dev); |
2ebfaf5f PZ |
1157 | |
1158 | drm_vblank_cleanup(dev); | |
1159 | ||
17fa6463 | 1160 | intel_modeset_cleanup(dev); |
6c0d9350 | 1161 | |
17fa6463 DV |
1162 | /* |
1163 | * free the memory space allocated for the child device | |
1164 | * config parsed from VBT | |
1165 | */ | |
1166 | if (dev_priv->vbt.child_dev && dev_priv->vbt.child_dev_num) { | |
1167 | kfree(dev_priv->vbt.child_dev); | |
1168 | dev_priv->vbt.child_dev = NULL; | |
1169 | dev_priv->vbt.child_dev_num = 0; | |
79e53945 | 1170 | } |
9aa61142 MR |
1171 | kfree(dev_priv->vbt.sdvo_lvds_vbt_mode); |
1172 | dev_priv->vbt.sdvo_lvds_vbt_mode = NULL; | |
1173 | kfree(dev_priv->vbt.lfp_lvds_vbt_mode); | |
1174 | dev_priv->vbt.lfp_lvds_vbt_mode = NULL; | |
79e53945 | 1175 | |
17fa6463 DV |
1176 | vga_switcheroo_unregister_client(dev->pdev); |
1177 | vga_client_register(dev->pdev, NULL, NULL, NULL); | |
1178 | ||
a8b4899e | 1179 | /* Free error state after interrupts are fully disabled. */ |
737b1506 | 1180 | cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work); |
a8b4899e | 1181 | i915_destroy_error_state(dev); |
bc0c7f14 | 1182 | |
ed4cb414 EA |
1183 | if (dev->pdev->msi_enabled) |
1184 | pci_disable_msi(dev->pdev); | |
1185 | ||
44834a67 | 1186 | intel_opregion_fini(dev); |
8ee1c3db | 1187 | |
17fa6463 DV |
1188 | /* Flush any outstanding unpin_work. */ |
1189 | flush_workqueue(dev_priv->wq); | |
67e77c5a | 1190 | |
33a732f4 | 1191 | intel_guc_ucode_fini(dev); |
bf248ca1 | 1192 | mutex_lock(&dev->struct_mutex); |
17fa6463 | 1193 | i915_gem_cleanup_ringbuffer(dev); |
17fa6463 DV |
1194 | i915_gem_context_fini(dev); |
1195 | mutex_unlock(&dev->struct_mutex); | |
7733b49b | 1196 | intel_fbc_cleanup_cfb(dev_priv); |
17fa6463 | 1197 | i915_gem_cleanup_stolen(dev); |
79e53945 | 1198 | |
eb805623 DV |
1199 | intel_csr_ucode_fini(dev); |
1200 | ||
f899fc64 | 1201 | intel_teardown_gmbus(dev); |
c4804411 ZW |
1202 | intel_teardown_mchbar(dev); |
1203 | ||
5fcece80 | 1204 | destroy_workqueue(dev_priv->hotplug.dp_wq); |
bc0c7f14 | 1205 | destroy_workqueue(dev_priv->wq); |
737b1506 | 1206 | destroy_workqueue(dev_priv->gpu_error.hangcheck_wq); |
9ee32fea | 1207 | pm_qos_remove_request(&dev_priv->pm_qos); |
bc0c7f14 | 1208 | |
90d0a0e8 | 1209 | i915_global_gtt_cleanup(dev); |
6640aab6 | 1210 | |
aec347ab CW |
1211 | intel_uncore_fini(dev); |
1212 | if (dev_priv->regs != NULL) | |
1213 | pci_iounmap(dev->pdev, dev_priv->regs); | |
1214 | ||
76b1cf21 JL |
1215 | kmem_cache_destroy(dev_priv->requests); |
1216 | kmem_cache_destroy(dev_priv->vmas); | |
1217 | kmem_cache_destroy(dev_priv->objects); | |
ec2a4c3f | 1218 | pci_dev_put(dev_priv->bridge_dev); |
2206e6a1 | 1219 | kfree(dev_priv); |
ba8bbcf6 | 1220 | |
22eae947 DA |
1221 | return 0; |
1222 | } | |
1223 | ||
f787a5f5 | 1224 | int i915_driver_open(struct drm_device *dev, struct drm_file *file) |
673a394b | 1225 | { |
b29c19b6 | 1226 | int ret; |
673a394b | 1227 | |
b29c19b6 CW |
1228 | ret = i915_gem_open(dev, file); |
1229 | if (ret) | |
1230 | return ret; | |
254f965c | 1231 | |
673a394b EA |
1232 | return 0; |
1233 | } | |
1234 | ||
79e53945 JB |
1235 | /** |
1236 | * i915_driver_lastclose - clean up after all DRM clients have exited | |
1237 | * @dev: DRM device | |
1238 | * | |
1239 | * Take care of cleaning up after all DRM clients have exited. In the | |
1240 | * mode setting case, we want to restore the kernel's initial mode (just | |
1241 | * in case the last client left us in a bad state). | |
1242 | * | |
9021f284 | 1243 | * Additionally, in the non-mode setting case, we'll tear down the GTT |
79e53945 JB |
1244 | * and DMA structures, since the kernel won't be using them, and clea |
1245 | * up any GEM state. | |
1246 | */ | |
1a5036bf | 1247 | void i915_driver_lastclose(struct drm_device *dev) |
1da177e4 | 1248 | { |
377e91b2 DV |
1249 | intel_fbdev_restore_mode(dev); |
1250 | vga_switcheroo_process_delayed_switch(); | |
1da177e4 LT |
1251 | } |
1252 | ||
2885f6ac | 1253 | void i915_driver_preclose(struct drm_device *dev, struct drm_file *file) |
1da177e4 | 1254 | { |
0d1430a3 | 1255 | mutex_lock(&dev->struct_mutex); |
2885f6ac JH |
1256 | i915_gem_context_close(dev, file); |
1257 | i915_gem_release(dev, file); | |
0d1430a3 | 1258 | mutex_unlock(&dev->struct_mutex); |
e2fcdaa9 | 1259 | |
17fa6463 | 1260 | intel_modeset_preclose(dev, file); |
1da177e4 LT |
1261 | } |
1262 | ||
f787a5f5 | 1263 | void i915_driver_postclose(struct drm_device *dev, struct drm_file *file) |
673a394b | 1264 | { |
f787a5f5 | 1265 | struct drm_i915_file_private *file_priv = file->driver_priv; |
673a394b | 1266 | |
a8ebba75 ZY |
1267 | if (file_priv && file_priv->bsd_ring) |
1268 | file_priv->bsd_ring = NULL; | |
f787a5f5 | 1269 | kfree(file_priv); |
673a394b EA |
1270 | } |
1271 | ||
4feb7659 DV |
1272 | static int |
1273 | i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data, | |
1274 | struct drm_file *file) | |
1275 | { | |
1276 | return -ENODEV; | |
1277 | } | |
1278 | ||
baa70943 | 1279 | const struct drm_ioctl_desc i915_ioctls[] = { |
77f31815 DV |
1280 | DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
1281 | DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH), | |
1282 | DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH), | |
1283 | DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH), | |
1284 | DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH), | |
1285 | DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH), | |
10ba5012 | 1286 | DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH|DRM_RENDER_ALLOW), |
c668cde5 | 1287 | DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
b2c606fe DV |
1288 | DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH), |
1289 | DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH), | |
1290 | DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
77f31815 | 1291 | DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH), |
b2c606fe | 1292 | DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
d1c1edbc | 1293 | DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
77f31815 DV |
1294 | DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, drm_noop, DRM_AUTH), |
1295 | DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH), | |
1296 | DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
f8c47144 DV |
1297 | DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
1298 | DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH), | |
1299 | DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_RENDER_ALLOW), | |
1300 | DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY), | |
1301 | DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY), | |
1302 | DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), | |
1303 | DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW), | |
1304 | DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW), | |
1305 | DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), | |
1306 | DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
1307 | DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
1308 | DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW), | |
1309 | DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW), | |
1310 | DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW), | |
1311 | DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW), | |
1312 | DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_RENDER_ALLOW), | |
1313 | DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW), | |
1314 | DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW), | |
1315 | DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_RENDER_ALLOW), | |
1316 | DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_RENDER_ALLOW), | |
1317 | DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW), | |
1318 | DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, 0), | |
1319 | DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW), | |
1320 | DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW), | |
1321 | DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW), | |
1322 | DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW), | |
1323 | DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER|DRM_CONTROL_ALLOW), | |
1324 | DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), | |
1325 | DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW), | |
1326 | DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW), | |
1327 | DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW), | |
1328 | DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_get_reset_stats_ioctl, DRM_RENDER_ALLOW), | |
1329 | DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW), | |
1330 | DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW), | |
1331 | DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW), | |
c94f7029 DA |
1332 | }; |
1333 | ||
f95aeb17 | 1334 | int i915_max_ioctl = ARRAY_SIZE(i915_ioctls); |