Commit | Line | Data |
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1da177e4 LT |
1 | /* i915_dma.c -- DMA support for the I915 -*- linux-c -*- |
2 | */ | |
0d6aa60b | 3 | /* |
1da177e4 LT |
4 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
5 | * All Rights Reserved. | |
bc54fd1a DA |
6 | * |
7 | * Permission is hereby granted, free of charge, to any person obtaining a | |
8 | * copy of this software and associated documentation files (the | |
9 | * "Software"), to deal in the Software without restriction, including | |
10 | * without limitation the rights to use, copy, modify, merge, publish, | |
11 | * distribute, sub license, and/or sell copies of the Software, and to | |
12 | * permit persons to whom the Software is furnished to do so, subject to | |
13 | * the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice (including the | |
16 | * next paragraph) shall be included in all copies or substantial portions | |
17 | * of the Software. | |
18 | * | |
19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
20 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
21 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
22 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
23 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
24 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
25 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
26 | * | |
0d6aa60b | 27 | */ |
1da177e4 | 28 | |
a70491cc JP |
29 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
30 | ||
760285e7 DH |
31 | #include <drm/drmP.h> |
32 | #include <drm/drm_crtc_helper.h> | |
33 | #include <drm/drm_fb_helper.h> | |
79e53945 | 34 | #include "intel_drv.h" |
760285e7 | 35 | #include <drm/i915_drm.h> |
1da177e4 | 36 | #include "i915_drv.h" |
1c5d22f7 | 37 | #include "i915_trace.h" |
dcdb1674 | 38 | #include <linux/pci.h> |
28d52043 | 39 | #include <linux/vgaarb.h> |
c4804411 ZW |
40 | #include <linux/acpi.h> |
41 | #include <linux/pnp.h> | |
6a9ee8af | 42 | #include <linux/vga_switcheroo.h> |
5a0e3ad6 | 43 | #include <linux/slab.h> |
44834a67 | 44 | #include <acpi/video.h> |
8a187455 PZ |
45 | #include <linux/pm.h> |
46 | #include <linux/pm_runtime.h> | |
1da177e4 | 47 | |
09422b2e DV |
48 | #define LP_RING(d) (&((struct drm_i915_private *)(d))->ring[RCS]) |
49 | ||
50 | #define BEGIN_LP_RING(n) \ | |
51 | intel_ring_begin(LP_RING(dev_priv), (n)) | |
52 | ||
53 | #define OUT_RING(x) \ | |
54 | intel_ring_emit(LP_RING(dev_priv), x) | |
55 | ||
56 | #define ADVANCE_LP_RING() \ | |
09246732 | 57 | __intel_ring_advance(LP_RING(dev_priv)) |
09422b2e DV |
58 | |
59 | /** | |
60 | * Lock test for when it's just for synchronization of ring access. | |
61 | * | |
62 | * In that case, we don't need to do it when GEM is initialized as nobody else | |
63 | * has access to the ring. | |
64 | */ | |
65 | #define RING_LOCK_TEST_WITH_RETURN(dev, file) do { \ | |
66 | if (LP_RING(dev->dev_private)->obj == NULL) \ | |
67 | LOCK_TEST_WITH_RETURN(dev, file); \ | |
68 | } while (0) | |
69 | ||
316d3884 DV |
70 | static inline u32 |
71 | intel_read_legacy_status_page(struct drm_i915_private *dev_priv, int reg) | |
72 | { | |
73 | if (I915_NEED_GFX_HWS(dev_priv->dev)) | |
74 | return ioread32(dev_priv->dri1.gfx_hws_cpu_addr + reg); | |
75 | else | |
76 | return intel_read_status_page(LP_RING(dev_priv), reg); | |
77 | } | |
78 | ||
79 | #define READ_HWSP(dev_priv, reg) intel_read_legacy_status_page(dev_priv, reg) | |
09422b2e DV |
80 | #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX) |
81 | #define I915_BREADCRUMB_INDEX 0x21 | |
82 | ||
d05c617e DV |
83 | void i915_update_dri1_breadcrumb(struct drm_device *dev) |
84 | { | |
4c8a4be9 | 85 | struct drm_i915_private *dev_priv = dev->dev_private; |
d05c617e DV |
86 | struct drm_i915_master_private *master_priv; |
87 | ||
6c719fac DV |
88 | /* |
89 | * The dri breadcrumb update races against the drm master disappearing. | |
90 | * Instead of trying to fix this (this is by far not the only ums issue) | |
91 | * just don't do the update in kms mode. | |
92 | */ | |
93 | if (drm_core_check_feature(dev, DRIVER_MODESET)) | |
94 | return; | |
95 | ||
d05c617e DV |
96 | if (dev->primary->master) { |
97 | master_priv = dev->primary->master->driver_priv; | |
98 | if (master_priv->sarea_priv) | |
99 | master_priv->sarea_priv->last_dispatch = | |
100 | READ_BREADCRUMB(dev_priv); | |
101 | } | |
102 | } | |
103 | ||
4cbf74cc CW |
104 | static void i915_write_hws_pga(struct drm_device *dev) |
105 | { | |
4c8a4be9 | 106 | struct drm_i915_private *dev_priv = dev->dev_private; |
4cbf74cc CW |
107 | u32 addr; |
108 | ||
109 | addr = dev_priv->status_page_dmah->busaddr; | |
110 | if (INTEL_INFO(dev)->gen >= 4) | |
111 | addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0; | |
112 | I915_WRITE(HWS_PGA, addr); | |
113 | } | |
114 | ||
398c9cb2 KP |
115 | /** |
116 | * Frees the hardware status page, whether it's a physical address or a virtual | |
117 | * address set up by the X Server. | |
118 | */ | |
3043c60c | 119 | static void i915_free_hws(struct drm_device *dev) |
398c9cb2 | 120 | { |
4c8a4be9 | 121 | struct drm_i915_private *dev_priv = dev->dev_private; |
1ec14ad3 CW |
122 | struct intel_ring_buffer *ring = LP_RING(dev_priv); |
123 | ||
398c9cb2 KP |
124 | if (dev_priv->status_page_dmah) { |
125 | drm_pci_free(dev, dev_priv->status_page_dmah); | |
126 | dev_priv->status_page_dmah = NULL; | |
127 | } | |
128 | ||
1ec14ad3 CW |
129 | if (ring->status_page.gfx_addr) { |
130 | ring->status_page.gfx_addr = 0; | |
316d3884 | 131 | iounmap(dev_priv->dri1.gfx_hws_cpu_addr); |
398c9cb2 KP |
132 | } |
133 | ||
134 | /* Need to rewrite hardware status page */ | |
135 | I915_WRITE(HWS_PGA, 0x1ffff000); | |
136 | } | |
137 | ||
84b1fd10 | 138 | void i915_kernel_lost_context(struct drm_device * dev) |
1da177e4 | 139 | { |
4c8a4be9 | 140 | struct drm_i915_private *dev_priv = dev->dev_private; |
7c1c2871 | 141 | struct drm_i915_master_private *master_priv; |
1ec14ad3 | 142 | struct intel_ring_buffer *ring = LP_RING(dev_priv); |
1da177e4 | 143 | |
79e53945 JB |
144 | /* |
145 | * We should never lose context on the ring with modesetting | |
146 | * as we don't expose it to userspace | |
147 | */ | |
148 | if (drm_core_check_feature(dev, DRIVER_MODESET)) | |
149 | return; | |
150 | ||
8168bd48 CW |
151 | ring->head = I915_READ_HEAD(ring) & HEAD_ADDR; |
152 | ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR; | |
633cf8f5 | 153 | ring->space = ring->head - (ring->tail + I915_RING_FREE_SPACE); |
1da177e4 | 154 | if (ring->space < 0) |
8187a2b7 | 155 | ring->space += ring->size; |
1da177e4 | 156 | |
7c1c2871 DA |
157 | if (!dev->primary->master) |
158 | return; | |
159 | ||
160 | master_priv = dev->primary->master->driver_priv; | |
161 | if (ring->head == ring->tail && master_priv->sarea_priv) | |
162 | master_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY; | |
1da177e4 LT |
163 | } |
164 | ||
84b1fd10 | 165 | static int i915_dma_cleanup(struct drm_device * dev) |
1da177e4 | 166 | { |
4c8a4be9 | 167 | struct drm_i915_private *dev_priv = dev->dev_private; |
1ec14ad3 CW |
168 | int i; |
169 | ||
1da177e4 LT |
170 | /* Make sure interrupts are disabled here because the uninstall ioctl |
171 | * may not have been called from userspace and after dev_private | |
172 | * is freed, it's too late. | |
173 | */ | |
ed4cb414 | 174 | if (dev->irq_enabled) |
b5e89ed5 | 175 | drm_irq_uninstall(dev); |
1da177e4 | 176 | |
ee0c6bfb | 177 | mutex_lock(&dev->struct_mutex); |
1ec14ad3 CW |
178 | for (i = 0; i < I915_NUM_RINGS; i++) |
179 | intel_cleanup_ring_buffer(&dev_priv->ring[i]); | |
ee0c6bfb | 180 | mutex_unlock(&dev->struct_mutex); |
dc7a9319 | 181 | |
398c9cb2 KP |
182 | /* Clear the HWS virtual address at teardown */ |
183 | if (I915_NEED_GFX_HWS(dev)) | |
184 | i915_free_hws(dev); | |
1da177e4 LT |
185 | |
186 | return 0; | |
187 | } | |
188 | ||
ba8bbcf6 | 189 | static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init) |
1da177e4 | 190 | { |
4c8a4be9 | 191 | struct drm_i915_private *dev_priv = dev->dev_private; |
7c1c2871 | 192 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
e8616b6c | 193 | int ret; |
1da177e4 | 194 | |
3a03ac1a DA |
195 | master_priv->sarea = drm_getsarea(dev); |
196 | if (master_priv->sarea) { | |
197 | master_priv->sarea_priv = (drm_i915_sarea_t *) | |
198 | ((u8 *)master_priv->sarea->handle + init->sarea_priv_offset); | |
199 | } else { | |
8a4c47f3 | 200 | DRM_DEBUG_DRIVER("sarea not found assuming DRI2 userspace\n"); |
3a03ac1a DA |
201 | } |
202 | ||
673a394b | 203 | if (init->ring_size != 0) { |
e8616b6c | 204 | if (LP_RING(dev_priv)->obj != NULL) { |
673a394b EA |
205 | i915_dma_cleanup(dev); |
206 | DRM_ERROR("Client tried to initialize ringbuffer in " | |
207 | "GEM mode\n"); | |
208 | return -EINVAL; | |
209 | } | |
1da177e4 | 210 | |
e8616b6c CW |
211 | ret = intel_render_ring_init_dri(dev, |
212 | init->ring_start, | |
213 | init->ring_size); | |
214 | if (ret) { | |
673a394b | 215 | i915_dma_cleanup(dev); |
e8616b6c | 216 | return ret; |
673a394b | 217 | } |
1da177e4 LT |
218 | } |
219 | ||
5d985ac8 DV |
220 | dev_priv->dri1.cpp = init->cpp; |
221 | dev_priv->dri1.back_offset = init->back_offset; | |
222 | dev_priv->dri1.front_offset = init->front_offset; | |
223 | dev_priv->dri1.current_page = 0; | |
7c1c2871 DA |
224 | if (master_priv->sarea_priv) |
225 | master_priv->sarea_priv->pf_current_page = 0; | |
1da177e4 | 226 | |
1da177e4 LT |
227 | /* Allow hardware batchbuffers unless told otherwise. |
228 | */ | |
8781342d | 229 | dev_priv->dri1.allow_batchbuffer = 1; |
1da177e4 | 230 | |
1da177e4 LT |
231 | return 0; |
232 | } | |
233 | ||
84b1fd10 | 234 | static int i915_dma_resume(struct drm_device * dev) |
1da177e4 | 235 | { |
4c8a4be9 | 236 | struct drm_i915_private *dev_priv = dev->dev_private; |
1ec14ad3 | 237 | struct intel_ring_buffer *ring = LP_RING(dev_priv); |
1da177e4 | 238 | |
8a4c47f3 | 239 | DRM_DEBUG_DRIVER("%s\n", __func__); |
1da177e4 | 240 | |
4225d0f2 | 241 | if (ring->virtual_start == NULL) { |
1da177e4 LT |
242 | DRM_ERROR("can not ioremap virtual address for" |
243 | " ring buffer\n"); | |
20caafa6 | 244 | return -ENOMEM; |
1da177e4 LT |
245 | } |
246 | ||
247 | /* Program Hardware Status Page */ | |
8187a2b7 | 248 | if (!ring->status_page.page_addr) { |
1da177e4 | 249 | DRM_ERROR("Can not find hardware status page\n"); |
20caafa6 | 250 | return -EINVAL; |
1da177e4 | 251 | } |
8a4c47f3 | 252 | DRM_DEBUG_DRIVER("hw status page @ %p\n", |
8187a2b7 ZN |
253 | ring->status_page.page_addr); |
254 | if (ring->status_page.gfx_addr != 0) | |
78501eac | 255 | intel_ring_setup_status_page(ring); |
dc7a9319 | 256 | else |
4cbf74cc | 257 | i915_write_hws_pga(dev); |
8187a2b7 | 258 | |
8a4c47f3 | 259 | DRM_DEBUG_DRIVER("Enabled hardware status page\n"); |
1da177e4 LT |
260 | |
261 | return 0; | |
262 | } | |
263 | ||
c153f45f EA |
264 | static int i915_dma_init(struct drm_device *dev, void *data, |
265 | struct drm_file *file_priv) | |
1da177e4 | 266 | { |
c153f45f | 267 | drm_i915_init_t *init = data; |
1da177e4 LT |
268 | int retcode = 0; |
269 | ||
cd9d4e9f DV |
270 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
271 | return -ENODEV; | |
272 | ||
c153f45f | 273 | switch (init->func) { |
1da177e4 | 274 | case I915_INIT_DMA: |
ba8bbcf6 | 275 | retcode = i915_initialize(dev, init); |
1da177e4 LT |
276 | break; |
277 | case I915_CLEANUP_DMA: | |
278 | retcode = i915_dma_cleanup(dev); | |
279 | break; | |
280 | case I915_RESUME_DMA: | |
0d6aa60b | 281 | retcode = i915_dma_resume(dev); |
1da177e4 LT |
282 | break; |
283 | default: | |
20caafa6 | 284 | retcode = -EINVAL; |
1da177e4 LT |
285 | break; |
286 | } | |
287 | ||
288 | return retcode; | |
289 | } | |
290 | ||
291 | /* Implement basically the same security restrictions as hardware does | |
292 | * for MI_BATCH_NON_SECURE. These can be made stricter at any time. | |
293 | * | |
294 | * Most of the calculations below involve calculating the size of a | |
295 | * particular instruction. It's important to get the size right as | |
296 | * that tells us where the next instruction to check is. Any illegal | |
297 | * instruction detected will be given a size of zero, which is a | |
298 | * signal to abort the rest of the buffer. | |
299 | */ | |
e1f99ce6 | 300 | static int validate_cmd(int cmd) |
1da177e4 LT |
301 | { |
302 | switch (((cmd >> 29) & 0x7)) { | |
303 | case 0x0: | |
304 | switch ((cmd >> 23) & 0x3f) { | |
305 | case 0x0: | |
306 | return 1; /* MI_NOOP */ | |
307 | case 0x4: | |
308 | return 1; /* MI_FLUSH */ | |
309 | default: | |
310 | return 0; /* disallow everything else */ | |
311 | } | |
312 | break; | |
313 | case 0x1: | |
314 | return 0; /* reserved */ | |
315 | case 0x2: | |
316 | return (cmd & 0xff) + 2; /* 2d commands */ | |
317 | case 0x3: | |
318 | if (((cmd >> 24) & 0x1f) <= 0x18) | |
319 | return 1; | |
320 | ||
321 | switch ((cmd >> 24) & 0x1f) { | |
322 | case 0x1c: | |
323 | return 1; | |
324 | case 0x1d: | |
b5e89ed5 | 325 | switch ((cmd >> 16) & 0xff) { |
1da177e4 LT |
326 | case 0x3: |
327 | return (cmd & 0x1f) + 2; | |
328 | case 0x4: | |
329 | return (cmd & 0xf) + 2; | |
330 | default: | |
331 | return (cmd & 0xffff) + 2; | |
332 | } | |
333 | case 0x1e: | |
334 | if (cmd & (1 << 23)) | |
335 | return (cmd & 0xffff) + 1; | |
336 | else | |
337 | return 1; | |
338 | case 0x1f: | |
339 | if ((cmd & (1 << 23)) == 0) /* inline vertices */ | |
340 | return (cmd & 0x1ffff) + 2; | |
341 | else if (cmd & (1 << 17)) /* indirect random */ | |
342 | if ((cmd & 0xffff) == 0) | |
343 | return 0; /* unknown length, too hard */ | |
344 | else | |
345 | return (((cmd & 0xffff) + 1) / 2) + 1; | |
346 | else | |
347 | return 2; /* indirect sequential */ | |
348 | default: | |
349 | return 0; | |
350 | } | |
351 | default: | |
352 | return 0; | |
353 | } | |
354 | ||
355 | return 0; | |
356 | } | |
357 | ||
201361a5 | 358 | static int i915_emit_cmds(struct drm_device * dev, int *buffer, int dwords) |
1da177e4 | 359 | { |
4c8a4be9 | 360 | struct drm_i915_private *dev_priv = dev->dev_private; |
e1f99ce6 | 361 | int i, ret; |
1da177e4 | 362 | |
1ec14ad3 | 363 | if ((dwords+1) * sizeof(int) >= LP_RING(dev_priv)->size - 8) |
20caafa6 | 364 | return -EINVAL; |
de227f5f | 365 | |
1da177e4 | 366 | for (i = 0; i < dwords;) { |
e1f99ce6 CW |
367 | int sz = validate_cmd(buffer[i]); |
368 | if (sz == 0 || i + sz > dwords) | |
20caafa6 | 369 | return -EINVAL; |
e1f99ce6 | 370 | i += sz; |
1da177e4 LT |
371 | } |
372 | ||
e1f99ce6 CW |
373 | ret = BEGIN_LP_RING((dwords+1)&~1); |
374 | if (ret) | |
375 | return ret; | |
376 | ||
377 | for (i = 0; i < dwords; i++) | |
378 | OUT_RING(buffer[i]); | |
de227f5f DA |
379 | if (dwords & 1) |
380 | OUT_RING(0); | |
381 | ||
382 | ADVANCE_LP_RING(); | |
383 | ||
1da177e4 LT |
384 | return 0; |
385 | } | |
386 | ||
673a394b EA |
387 | int |
388 | i915_emit_box(struct drm_device *dev, | |
c4e7a414 CW |
389 | struct drm_clip_rect *box, |
390 | int DR1, int DR4) | |
1da177e4 | 391 | { |
e1f99ce6 | 392 | struct drm_i915_private *dev_priv = dev->dev_private; |
e1f99ce6 | 393 | int ret; |
1da177e4 | 394 | |
c4e7a414 CW |
395 | if (box->y2 <= box->y1 || box->x2 <= box->x1 || |
396 | box->y2 <= 0 || box->x2 <= 0) { | |
1da177e4 | 397 | DRM_ERROR("Bad box %d,%d..%d,%d\n", |
c4e7a414 | 398 | box->x1, box->y1, box->x2, box->y2); |
20caafa6 | 399 | return -EINVAL; |
1da177e4 LT |
400 | } |
401 | ||
a6c45cf0 | 402 | if (INTEL_INFO(dev)->gen >= 4) { |
e1f99ce6 CW |
403 | ret = BEGIN_LP_RING(4); |
404 | if (ret) | |
405 | return ret; | |
406 | ||
c29b669c | 407 | OUT_RING(GFX_OP_DRAWRECT_INFO_I965); |
c4e7a414 CW |
408 | OUT_RING((box->x1 & 0xffff) | (box->y1 << 16)); |
409 | OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16)); | |
c29b669c | 410 | OUT_RING(DR4); |
c29b669c | 411 | } else { |
e1f99ce6 CW |
412 | ret = BEGIN_LP_RING(6); |
413 | if (ret) | |
414 | return ret; | |
415 | ||
c29b669c AH |
416 | OUT_RING(GFX_OP_DRAWRECT_INFO); |
417 | OUT_RING(DR1); | |
c4e7a414 CW |
418 | OUT_RING((box->x1 & 0xffff) | (box->y1 << 16)); |
419 | OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16)); | |
c29b669c AH |
420 | OUT_RING(DR4); |
421 | OUT_RING(0); | |
c29b669c | 422 | } |
e1f99ce6 | 423 | ADVANCE_LP_RING(); |
1da177e4 LT |
424 | |
425 | return 0; | |
426 | } | |
427 | ||
c29b669c AH |
428 | /* XXX: Emitting the counter should really be moved to part of the IRQ |
429 | * emit. For now, do it in both places: | |
430 | */ | |
431 | ||
84b1fd10 | 432 | static void i915_emit_breadcrumb(struct drm_device *dev) |
de227f5f | 433 | { |
4c8a4be9 | 434 | struct drm_i915_private *dev_priv = dev->dev_private; |
7c1c2871 | 435 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
de227f5f | 436 | |
231f42a4 DV |
437 | dev_priv->dri1.counter++; |
438 | if (dev_priv->dri1.counter > 0x7FFFFFFFUL) | |
439 | dev_priv->dri1.counter = 0; | |
7c1c2871 | 440 | if (master_priv->sarea_priv) |
231f42a4 | 441 | master_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter; |
de227f5f | 442 | |
e1f99ce6 CW |
443 | if (BEGIN_LP_RING(4) == 0) { |
444 | OUT_RING(MI_STORE_DWORD_INDEX); | |
445 | OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
231f42a4 | 446 | OUT_RING(dev_priv->dri1.counter); |
e1f99ce6 CW |
447 | OUT_RING(0); |
448 | ADVANCE_LP_RING(); | |
449 | } | |
de227f5f DA |
450 | } |
451 | ||
84b1fd10 | 452 | static int i915_dispatch_cmdbuffer(struct drm_device * dev, |
201361a5 EA |
453 | drm_i915_cmdbuffer_t *cmd, |
454 | struct drm_clip_rect *cliprects, | |
455 | void *cmdbuf) | |
1da177e4 LT |
456 | { |
457 | int nbox = cmd->num_cliprects; | |
458 | int i = 0, count, ret; | |
459 | ||
460 | if (cmd->sz & 0x3) { | |
461 | DRM_ERROR("alignment"); | |
20caafa6 | 462 | return -EINVAL; |
1da177e4 LT |
463 | } |
464 | ||
465 | i915_kernel_lost_context(dev); | |
466 | ||
467 | count = nbox ? nbox : 1; | |
468 | ||
469 | for (i = 0; i < count; i++) { | |
470 | if (i < nbox) { | |
c4e7a414 | 471 | ret = i915_emit_box(dev, &cliprects[i], |
1da177e4 LT |
472 | cmd->DR1, cmd->DR4); |
473 | if (ret) | |
474 | return ret; | |
475 | } | |
476 | ||
201361a5 | 477 | ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4); |
1da177e4 LT |
478 | if (ret) |
479 | return ret; | |
480 | } | |
481 | ||
de227f5f | 482 | i915_emit_breadcrumb(dev); |
1da177e4 LT |
483 | return 0; |
484 | } | |
485 | ||
84b1fd10 | 486 | static int i915_dispatch_batchbuffer(struct drm_device * dev, |
201361a5 EA |
487 | drm_i915_batchbuffer_t * batch, |
488 | struct drm_clip_rect *cliprects) | |
1da177e4 | 489 | { |
e1f99ce6 | 490 | struct drm_i915_private *dev_priv = dev->dev_private; |
1da177e4 | 491 | int nbox = batch->num_cliprects; |
e1f99ce6 | 492 | int i, count, ret; |
1da177e4 LT |
493 | |
494 | if ((batch->start | batch->used) & 0x7) { | |
495 | DRM_ERROR("alignment"); | |
20caafa6 | 496 | return -EINVAL; |
1da177e4 LT |
497 | } |
498 | ||
499 | i915_kernel_lost_context(dev); | |
500 | ||
501 | count = nbox ? nbox : 1; | |
1da177e4 LT |
502 | for (i = 0; i < count; i++) { |
503 | if (i < nbox) { | |
c4e7a414 | 504 | ret = i915_emit_box(dev, &cliprects[i], |
e1f99ce6 | 505 | batch->DR1, batch->DR4); |
1da177e4 LT |
506 | if (ret) |
507 | return ret; | |
508 | } | |
509 | ||
0790d5e1 | 510 | if (!IS_I830(dev) && !IS_845G(dev)) { |
e1f99ce6 CW |
511 | ret = BEGIN_LP_RING(2); |
512 | if (ret) | |
513 | return ret; | |
514 | ||
a6c45cf0 | 515 | if (INTEL_INFO(dev)->gen >= 4) { |
21f16289 DA |
516 | OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965); |
517 | OUT_RING(batch->start); | |
518 | } else { | |
519 | OUT_RING(MI_BATCH_BUFFER_START | (2 << 6)); | |
520 | OUT_RING(batch->start | MI_BATCH_NON_SECURE); | |
521 | } | |
1da177e4 | 522 | } else { |
e1f99ce6 CW |
523 | ret = BEGIN_LP_RING(4); |
524 | if (ret) | |
525 | return ret; | |
526 | ||
1da177e4 LT |
527 | OUT_RING(MI_BATCH_BUFFER); |
528 | OUT_RING(batch->start | MI_BATCH_NON_SECURE); | |
529 | OUT_RING(batch->start + batch->used - 4); | |
530 | OUT_RING(0); | |
1da177e4 | 531 | } |
e1f99ce6 | 532 | ADVANCE_LP_RING(); |
1da177e4 LT |
533 | } |
534 | ||
1cafd347 | 535 | |
f00a3ddf | 536 | if (IS_G4X(dev) || IS_GEN5(dev)) { |
e1f99ce6 CW |
537 | if (BEGIN_LP_RING(2) == 0) { |
538 | OUT_RING(MI_FLUSH | MI_NO_WRITE_FLUSH | MI_INVALIDATE_ISP); | |
539 | OUT_RING(MI_NOOP); | |
540 | ADVANCE_LP_RING(); | |
541 | } | |
1cafd347 | 542 | } |
1da177e4 | 543 | |
e1f99ce6 | 544 | i915_emit_breadcrumb(dev); |
1da177e4 LT |
545 | return 0; |
546 | } | |
547 | ||
af6061af | 548 | static int i915_dispatch_flip(struct drm_device * dev) |
1da177e4 | 549 | { |
4c8a4be9 | 550 | struct drm_i915_private *dev_priv = dev->dev_private; |
7c1c2871 DA |
551 | struct drm_i915_master_private *master_priv = |
552 | dev->primary->master->driver_priv; | |
e1f99ce6 | 553 | int ret; |
1da177e4 | 554 | |
7c1c2871 | 555 | if (!master_priv->sarea_priv) |
c99b058f KH |
556 | return -EINVAL; |
557 | ||
8a4c47f3 | 558 | DRM_DEBUG_DRIVER("%s: page=%d pfCurrentPage=%d\n", |
be25ed9c | 559 | __func__, |
5d985ac8 | 560 | dev_priv->dri1.current_page, |
be25ed9c | 561 | master_priv->sarea_priv->pf_current_page); |
1da177e4 | 562 | |
af6061af DA |
563 | i915_kernel_lost_context(dev); |
564 | ||
e1f99ce6 CW |
565 | ret = BEGIN_LP_RING(10); |
566 | if (ret) | |
567 | return ret; | |
568 | ||
585fb111 | 569 | OUT_RING(MI_FLUSH | MI_READ_FLUSH); |
af6061af | 570 | OUT_RING(0); |
1da177e4 | 571 | |
af6061af DA |
572 | OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP); |
573 | OUT_RING(0); | |
5d985ac8 DV |
574 | if (dev_priv->dri1.current_page == 0) { |
575 | OUT_RING(dev_priv->dri1.back_offset); | |
576 | dev_priv->dri1.current_page = 1; | |
1da177e4 | 577 | } else { |
5d985ac8 DV |
578 | OUT_RING(dev_priv->dri1.front_offset); |
579 | dev_priv->dri1.current_page = 0; | |
1da177e4 | 580 | } |
af6061af | 581 | OUT_RING(0); |
1da177e4 | 582 | |
af6061af DA |
583 | OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP); |
584 | OUT_RING(0); | |
e1f99ce6 | 585 | |
af6061af | 586 | ADVANCE_LP_RING(); |
1da177e4 | 587 | |
231f42a4 | 588 | master_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter++; |
1da177e4 | 589 | |
e1f99ce6 CW |
590 | if (BEGIN_LP_RING(4) == 0) { |
591 | OUT_RING(MI_STORE_DWORD_INDEX); | |
592 | OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
231f42a4 | 593 | OUT_RING(dev_priv->dri1.counter); |
e1f99ce6 CW |
594 | OUT_RING(0); |
595 | ADVANCE_LP_RING(); | |
596 | } | |
1da177e4 | 597 | |
5d985ac8 | 598 | master_priv->sarea_priv->pf_current_page = dev_priv->dri1.current_page; |
af6061af | 599 | return 0; |
1da177e4 LT |
600 | } |
601 | ||
1ec14ad3 | 602 | static int i915_quiescent(struct drm_device *dev) |
1da177e4 | 603 | { |
1da177e4 | 604 | i915_kernel_lost_context(dev); |
3e960501 | 605 | return intel_ring_idle(LP_RING(dev->dev_private)); |
1da177e4 LT |
606 | } |
607 | ||
c153f45f EA |
608 | static int i915_flush_ioctl(struct drm_device *dev, void *data, |
609 | struct drm_file *file_priv) | |
1da177e4 | 610 | { |
546b0974 EA |
611 | int ret; |
612 | ||
cd9d4e9f DV |
613 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
614 | return -ENODEV; | |
615 | ||
546b0974 | 616 | RING_LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 | 617 | |
546b0974 EA |
618 | mutex_lock(&dev->struct_mutex); |
619 | ret = i915_quiescent(dev); | |
620 | mutex_unlock(&dev->struct_mutex); | |
621 | ||
622 | return ret; | |
1da177e4 LT |
623 | } |
624 | ||
c153f45f EA |
625 | static int i915_batchbuffer(struct drm_device *dev, void *data, |
626 | struct drm_file *file_priv) | |
1da177e4 | 627 | { |
4c8a4be9 | 628 | struct drm_i915_private *dev_priv = dev->dev_private; |
4d10cc0f DV |
629 | struct drm_i915_master_private *master_priv; |
630 | drm_i915_sarea_t *sarea_priv; | |
c153f45f | 631 | drm_i915_batchbuffer_t *batch = data; |
1da177e4 | 632 | int ret; |
201361a5 | 633 | struct drm_clip_rect *cliprects = NULL; |
1da177e4 | 634 | |
cd9d4e9f DV |
635 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
636 | return -ENODEV; | |
637 | ||
4d10cc0f DV |
638 | master_priv = dev->primary->master->driver_priv; |
639 | sarea_priv = (drm_i915_sarea_t *) master_priv->sarea_priv; | |
640 | ||
8781342d | 641 | if (!dev_priv->dri1.allow_batchbuffer) { |
1da177e4 | 642 | DRM_ERROR("Batchbuffer ioctl disabled\n"); |
20caafa6 | 643 | return -EINVAL; |
1da177e4 LT |
644 | } |
645 | ||
8a4c47f3 | 646 | DRM_DEBUG_DRIVER("i915 batchbuffer, start %x used %d cliprects %d\n", |
be25ed9c | 647 | batch->start, batch->used, batch->num_cliprects); |
1da177e4 | 648 | |
546b0974 | 649 | RING_LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 | 650 | |
201361a5 EA |
651 | if (batch->num_cliprects < 0) |
652 | return -EINVAL; | |
653 | ||
654 | if (batch->num_cliprects) { | |
9a298b2a | 655 | cliprects = kcalloc(batch->num_cliprects, |
b14c5679 | 656 | sizeof(*cliprects), |
9a298b2a | 657 | GFP_KERNEL); |
201361a5 EA |
658 | if (cliprects == NULL) |
659 | return -ENOMEM; | |
660 | ||
661 | ret = copy_from_user(cliprects, batch->cliprects, | |
662 | batch->num_cliprects * | |
663 | sizeof(struct drm_clip_rect)); | |
9927a403 DC |
664 | if (ret != 0) { |
665 | ret = -EFAULT; | |
201361a5 | 666 | goto fail_free; |
9927a403 | 667 | } |
201361a5 | 668 | } |
1da177e4 | 669 | |
546b0974 | 670 | mutex_lock(&dev->struct_mutex); |
201361a5 | 671 | ret = i915_dispatch_batchbuffer(dev, batch, cliprects); |
546b0974 | 672 | mutex_unlock(&dev->struct_mutex); |
1da177e4 | 673 | |
c99b058f | 674 | if (sarea_priv) |
0baf823a | 675 | sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv); |
201361a5 EA |
676 | |
677 | fail_free: | |
9a298b2a | 678 | kfree(cliprects); |
201361a5 | 679 | |
1da177e4 LT |
680 | return ret; |
681 | } | |
682 | ||
c153f45f EA |
683 | static int i915_cmdbuffer(struct drm_device *dev, void *data, |
684 | struct drm_file *file_priv) | |
1da177e4 | 685 | { |
4c8a4be9 | 686 | struct drm_i915_private *dev_priv = dev->dev_private; |
4d10cc0f DV |
687 | struct drm_i915_master_private *master_priv; |
688 | drm_i915_sarea_t *sarea_priv; | |
c153f45f | 689 | drm_i915_cmdbuffer_t *cmdbuf = data; |
201361a5 EA |
690 | struct drm_clip_rect *cliprects = NULL; |
691 | void *batch_data; | |
1da177e4 LT |
692 | int ret; |
693 | ||
8a4c47f3 | 694 | DRM_DEBUG_DRIVER("i915 cmdbuffer, buf %p sz %d cliprects %d\n", |
be25ed9c | 695 | cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects); |
1da177e4 | 696 | |
cd9d4e9f DV |
697 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
698 | return -ENODEV; | |
699 | ||
4d10cc0f DV |
700 | master_priv = dev->primary->master->driver_priv; |
701 | sarea_priv = (drm_i915_sarea_t *) master_priv->sarea_priv; | |
702 | ||
546b0974 | 703 | RING_LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 | 704 | |
201361a5 EA |
705 | if (cmdbuf->num_cliprects < 0) |
706 | return -EINVAL; | |
707 | ||
9a298b2a | 708 | batch_data = kmalloc(cmdbuf->sz, GFP_KERNEL); |
201361a5 EA |
709 | if (batch_data == NULL) |
710 | return -ENOMEM; | |
711 | ||
712 | ret = copy_from_user(batch_data, cmdbuf->buf, cmdbuf->sz); | |
9927a403 DC |
713 | if (ret != 0) { |
714 | ret = -EFAULT; | |
201361a5 | 715 | goto fail_batch_free; |
9927a403 | 716 | } |
201361a5 EA |
717 | |
718 | if (cmdbuf->num_cliprects) { | |
9a298b2a | 719 | cliprects = kcalloc(cmdbuf->num_cliprects, |
b14c5679 | 720 | sizeof(*cliprects), GFP_KERNEL); |
a40e8d31 OA |
721 | if (cliprects == NULL) { |
722 | ret = -ENOMEM; | |
201361a5 | 723 | goto fail_batch_free; |
a40e8d31 | 724 | } |
201361a5 EA |
725 | |
726 | ret = copy_from_user(cliprects, cmdbuf->cliprects, | |
727 | cmdbuf->num_cliprects * | |
728 | sizeof(struct drm_clip_rect)); | |
9927a403 DC |
729 | if (ret != 0) { |
730 | ret = -EFAULT; | |
201361a5 | 731 | goto fail_clip_free; |
9927a403 | 732 | } |
1da177e4 LT |
733 | } |
734 | ||
546b0974 | 735 | mutex_lock(&dev->struct_mutex); |
201361a5 | 736 | ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data); |
546b0974 | 737 | mutex_unlock(&dev->struct_mutex); |
1da177e4 LT |
738 | if (ret) { |
739 | DRM_ERROR("i915_dispatch_cmdbuffer failed\n"); | |
355d7f37 | 740 | goto fail_clip_free; |
1da177e4 LT |
741 | } |
742 | ||
c99b058f | 743 | if (sarea_priv) |
0baf823a | 744 | sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv); |
201361a5 | 745 | |
201361a5 | 746 | fail_clip_free: |
9a298b2a | 747 | kfree(cliprects); |
355d7f37 | 748 | fail_batch_free: |
9a298b2a | 749 | kfree(batch_data); |
201361a5 EA |
750 | |
751 | return ret; | |
1da177e4 LT |
752 | } |
753 | ||
9488867a DV |
754 | static int i915_emit_irq(struct drm_device * dev) |
755 | { | |
4c8a4be9 | 756 | struct drm_i915_private *dev_priv = dev->dev_private; |
9488867a DV |
757 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
758 | ||
759 | i915_kernel_lost_context(dev); | |
760 | ||
761 | DRM_DEBUG_DRIVER("\n"); | |
762 | ||
231f42a4 DV |
763 | dev_priv->dri1.counter++; |
764 | if (dev_priv->dri1.counter > 0x7FFFFFFFUL) | |
765 | dev_priv->dri1.counter = 1; | |
9488867a | 766 | if (master_priv->sarea_priv) |
231f42a4 | 767 | master_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter; |
9488867a DV |
768 | |
769 | if (BEGIN_LP_RING(4) == 0) { | |
770 | OUT_RING(MI_STORE_DWORD_INDEX); | |
771 | OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
231f42a4 | 772 | OUT_RING(dev_priv->dri1.counter); |
9488867a DV |
773 | OUT_RING(MI_USER_INTERRUPT); |
774 | ADVANCE_LP_RING(); | |
775 | } | |
776 | ||
231f42a4 | 777 | return dev_priv->dri1.counter; |
9488867a DV |
778 | } |
779 | ||
780 | static int i915_wait_irq(struct drm_device * dev, int irq_nr) | |
781 | { | |
4c8a4be9 | 782 | struct drm_i915_private *dev_priv = dev->dev_private; |
9488867a DV |
783 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
784 | int ret = 0; | |
785 | struct intel_ring_buffer *ring = LP_RING(dev_priv); | |
786 | ||
787 | DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr, | |
788 | READ_BREADCRUMB(dev_priv)); | |
789 | ||
790 | if (READ_BREADCRUMB(dev_priv) >= irq_nr) { | |
791 | if (master_priv->sarea_priv) | |
792 | master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv); | |
793 | return 0; | |
794 | } | |
795 | ||
796 | if (master_priv->sarea_priv) | |
797 | master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT; | |
798 | ||
799 | if (ring->irq_get(ring)) { | |
bfd8303a | 800 | DRM_WAIT_ON(ret, ring->irq_queue, 3 * HZ, |
9488867a DV |
801 | READ_BREADCRUMB(dev_priv) >= irq_nr); |
802 | ring->irq_put(ring); | |
803 | } else if (wait_for(READ_BREADCRUMB(dev_priv) >= irq_nr, 3000)) | |
804 | ret = -EBUSY; | |
805 | ||
806 | if (ret == -EBUSY) { | |
807 | DRM_ERROR("EBUSY -- rec: %d emitted: %d\n", | |
231f42a4 | 808 | READ_BREADCRUMB(dev_priv), (int)dev_priv->dri1.counter); |
9488867a DV |
809 | } |
810 | ||
811 | return ret; | |
812 | } | |
813 | ||
814 | /* Needs the lock as it touches the ring. | |
815 | */ | |
816 | static int i915_irq_emit(struct drm_device *dev, void *data, | |
817 | struct drm_file *file_priv) | |
818 | { | |
4c8a4be9 | 819 | struct drm_i915_private *dev_priv = dev->dev_private; |
9488867a DV |
820 | drm_i915_irq_emit_t *emit = data; |
821 | int result; | |
822 | ||
823 | if (drm_core_check_feature(dev, DRIVER_MODESET)) | |
824 | return -ENODEV; | |
825 | ||
826 | if (!dev_priv || !LP_RING(dev_priv)->virtual_start) { | |
827 | DRM_ERROR("called with no initialization\n"); | |
828 | return -EINVAL; | |
829 | } | |
830 | ||
831 | RING_LOCK_TEST_WITH_RETURN(dev, file_priv); | |
832 | ||
833 | mutex_lock(&dev->struct_mutex); | |
834 | result = i915_emit_irq(dev); | |
835 | mutex_unlock(&dev->struct_mutex); | |
836 | ||
1d6ac185 | 837 | if (copy_to_user(emit->irq_seq, &result, sizeof(int))) { |
9488867a DV |
838 | DRM_ERROR("copy_to_user\n"); |
839 | return -EFAULT; | |
840 | } | |
841 | ||
842 | return 0; | |
843 | } | |
844 | ||
845 | /* Doesn't need the hardware lock. | |
846 | */ | |
847 | static int i915_irq_wait(struct drm_device *dev, void *data, | |
848 | struct drm_file *file_priv) | |
849 | { | |
4c8a4be9 | 850 | struct drm_i915_private *dev_priv = dev->dev_private; |
9488867a DV |
851 | drm_i915_irq_wait_t *irqwait = data; |
852 | ||
853 | if (drm_core_check_feature(dev, DRIVER_MODESET)) | |
854 | return -ENODEV; | |
855 | ||
856 | if (!dev_priv) { | |
857 | DRM_ERROR("called with no initialization\n"); | |
858 | return -EINVAL; | |
859 | } | |
860 | ||
861 | return i915_wait_irq(dev, irqwait->irq_seq); | |
862 | } | |
863 | ||
d1c1edbc DV |
864 | static int i915_vblank_pipe_get(struct drm_device *dev, void *data, |
865 | struct drm_file *file_priv) | |
866 | { | |
4c8a4be9 | 867 | struct drm_i915_private *dev_priv = dev->dev_private; |
d1c1edbc DV |
868 | drm_i915_vblank_pipe_t *pipe = data; |
869 | ||
870 | if (drm_core_check_feature(dev, DRIVER_MODESET)) | |
871 | return -ENODEV; | |
872 | ||
873 | if (!dev_priv) { | |
874 | DRM_ERROR("called with no initialization\n"); | |
875 | return -EINVAL; | |
876 | } | |
877 | ||
878 | pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B; | |
879 | ||
880 | return 0; | |
881 | } | |
882 | ||
883 | /** | |
884 | * Schedule buffer swap at given vertical blank. | |
885 | */ | |
886 | static int i915_vblank_swap(struct drm_device *dev, void *data, | |
887 | struct drm_file *file_priv) | |
888 | { | |
889 | /* The delayed swap mechanism was fundamentally racy, and has been | |
890 | * removed. The model was that the client requested a delayed flip/swap | |
891 | * from the kernel, then waited for vblank before continuing to perform | |
892 | * rendering. The problem was that the kernel might wake the client | |
893 | * up before it dispatched the vblank swap (since the lock has to be | |
894 | * held while touching the ringbuffer), in which case the client would | |
895 | * clear and start the next frame before the swap occurred, and | |
896 | * flicker would occur in addition to likely missing the vblank. | |
897 | * | |
898 | * In the absence of this ioctl, userland falls back to a correct path | |
899 | * of waiting for a vblank, then dispatching the swap on its own. | |
900 | * Context switching to userland and back is plenty fast enough for | |
901 | * meeting the requirements of vblank swapping. | |
902 | */ | |
903 | return -EINVAL; | |
904 | } | |
905 | ||
c153f45f EA |
906 | static int i915_flip_bufs(struct drm_device *dev, void *data, |
907 | struct drm_file *file_priv) | |
1da177e4 | 908 | { |
546b0974 EA |
909 | int ret; |
910 | ||
cd9d4e9f DV |
911 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
912 | return -ENODEV; | |
913 | ||
8a4c47f3 | 914 | DRM_DEBUG_DRIVER("%s\n", __func__); |
1da177e4 | 915 | |
546b0974 | 916 | RING_LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 | 917 | |
546b0974 EA |
918 | mutex_lock(&dev->struct_mutex); |
919 | ret = i915_dispatch_flip(dev); | |
920 | mutex_unlock(&dev->struct_mutex); | |
921 | ||
922 | return ret; | |
1da177e4 LT |
923 | } |
924 | ||
c153f45f EA |
925 | static int i915_getparam(struct drm_device *dev, void *data, |
926 | struct drm_file *file_priv) | |
1da177e4 | 927 | { |
4c8a4be9 | 928 | struct drm_i915_private *dev_priv = dev->dev_private; |
c153f45f | 929 | drm_i915_getparam_t *param = data; |
1da177e4 LT |
930 | int value; |
931 | ||
932 | if (!dev_priv) { | |
3e684eae | 933 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 934 | return -EINVAL; |
1da177e4 LT |
935 | } |
936 | ||
c153f45f | 937 | switch (param->param) { |
1da177e4 | 938 | case I915_PARAM_IRQ_ACTIVE: |
0a3e67a4 | 939 | value = dev->pdev->irq ? 1 : 0; |
1da177e4 LT |
940 | break; |
941 | case I915_PARAM_ALLOW_BATCHBUFFER: | |
8781342d | 942 | value = dev_priv->dri1.allow_batchbuffer ? 1 : 0; |
1da177e4 | 943 | break; |
0d6aa60b DA |
944 | case I915_PARAM_LAST_DISPATCH: |
945 | value = READ_BREADCRUMB(dev_priv); | |
946 | break; | |
ed4c9c4a | 947 | case I915_PARAM_CHIPSET_ID: |
ffbab09b | 948 | value = dev->pdev->device; |
ed4c9c4a | 949 | break; |
673a394b | 950 | case I915_PARAM_HAS_GEM: |
2e895b17 | 951 | value = 1; |
673a394b | 952 | break; |
0f973f27 JB |
953 | case I915_PARAM_NUM_FENCES_AVAIL: |
954 | value = dev_priv->num_fence_regs - dev_priv->fence_reg_start; | |
955 | break; | |
02e792fb DV |
956 | case I915_PARAM_HAS_OVERLAY: |
957 | value = dev_priv->overlay ? 1 : 0; | |
958 | break; | |
e9560f7c JB |
959 | case I915_PARAM_HAS_PAGEFLIPPING: |
960 | value = 1; | |
961 | break; | |
76446cac JB |
962 | case I915_PARAM_HAS_EXECBUF2: |
963 | /* depends on GEM */ | |
2e895b17 | 964 | value = 1; |
76446cac | 965 | break; |
e3a815fc | 966 | case I915_PARAM_HAS_BSD: |
edc912f5 | 967 | value = intel_ring_initialized(&dev_priv->ring[VCS]); |
e3a815fc | 968 | break; |
549f7365 | 969 | case I915_PARAM_HAS_BLT: |
edc912f5 | 970 | value = intel_ring_initialized(&dev_priv->ring[BCS]); |
549f7365 | 971 | break; |
a1f2cc73 XH |
972 | case I915_PARAM_HAS_VEBOX: |
973 | value = intel_ring_initialized(&dev_priv->ring[VECS]); | |
974 | break; | |
a00b10c3 CW |
975 | case I915_PARAM_HAS_RELAXED_FENCING: |
976 | value = 1; | |
977 | break; | |
bbf0c6b3 DV |
978 | case I915_PARAM_HAS_COHERENT_RINGS: |
979 | value = 1; | |
980 | break; | |
72bfa19c CW |
981 | case I915_PARAM_HAS_EXEC_CONSTANTS: |
982 | value = INTEL_INFO(dev)->gen >= 4; | |
983 | break; | |
271d81b8 CW |
984 | case I915_PARAM_HAS_RELAXED_DELTA: |
985 | value = 1; | |
986 | break; | |
ae662d31 EA |
987 | case I915_PARAM_HAS_GEN7_SOL_RESET: |
988 | value = 1; | |
989 | break; | |
3d29b842 ED |
990 | case I915_PARAM_HAS_LLC: |
991 | value = HAS_LLC(dev); | |
992 | break; | |
651d794f CW |
993 | case I915_PARAM_HAS_WT: |
994 | value = HAS_WT(dev); | |
995 | break; | |
777ee96f | 996 | case I915_PARAM_HAS_ALIASING_PPGTT: |
7d9c4779 | 997 | value = dev_priv->mm.aliasing_ppgtt || USES_FULL_PPGTT(dev); |
777ee96f | 998 | break; |
172cf15d BW |
999 | case I915_PARAM_HAS_WAIT_TIMEOUT: |
1000 | value = 1; | |
1001 | break; | |
2fedbff9 CW |
1002 | case I915_PARAM_HAS_SEMAPHORES: |
1003 | value = i915_semaphore_is_enabled(dev); | |
1004 | break; | |
ec6f1bb9 DA |
1005 | case I915_PARAM_HAS_PRIME_VMAP_FLUSH: |
1006 | value = 1; | |
1007 | break; | |
d7d4eedd CW |
1008 | case I915_PARAM_HAS_SECURE_BATCHES: |
1009 | value = capable(CAP_SYS_ADMIN); | |
1010 | break; | |
b45305fc DV |
1011 | case I915_PARAM_HAS_PINNED_BATCHES: |
1012 | value = 1; | |
1013 | break; | |
ed5982e6 DV |
1014 | case I915_PARAM_HAS_EXEC_NO_RELOC: |
1015 | value = 1; | |
1016 | break; | |
eef90ccb CW |
1017 | case I915_PARAM_HAS_EXEC_HANDLE_LUT: |
1018 | value = 1; | |
1019 | break; | |
1da177e4 | 1020 | default: |
e29c32da | 1021 | DRM_DEBUG("Unknown parameter %d\n", param->param); |
20caafa6 | 1022 | return -EINVAL; |
1da177e4 LT |
1023 | } |
1024 | ||
1d6ac185 DV |
1025 | if (copy_to_user(param->value, &value, sizeof(int))) { |
1026 | DRM_ERROR("copy_to_user failed\n"); | |
20caafa6 | 1027 | return -EFAULT; |
1da177e4 LT |
1028 | } |
1029 | ||
1030 | return 0; | |
1031 | } | |
1032 | ||
c153f45f EA |
1033 | static int i915_setparam(struct drm_device *dev, void *data, |
1034 | struct drm_file *file_priv) | |
1da177e4 | 1035 | { |
4c8a4be9 | 1036 | struct drm_i915_private *dev_priv = dev->dev_private; |
c153f45f | 1037 | drm_i915_setparam_t *param = data; |
1da177e4 LT |
1038 | |
1039 | if (!dev_priv) { | |
3e684eae | 1040 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 1041 | return -EINVAL; |
1da177e4 LT |
1042 | } |
1043 | ||
c153f45f | 1044 | switch (param->param) { |
1da177e4 | 1045 | case I915_SETPARAM_USE_MI_BATCHBUFFER_START: |
1da177e4 LT |
1046 | break; |
1047 | case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY: | |
1da177e4 LT |
1048 | break; |
1049 | case I915_SETPARAM_ALLOW_BATCHBUFFER: | |
8781342d | 1050 | dev_priv->dri1.allow_batchbuffer = param->value ? 1 : 0; |
1da177e4 | 1051 | break; |
0f973f27 JB |
1052 | case I915_SETPARAM_NUM_USED_FENCES: |
1053 | if (param->value > dev_priv->num_fence_regs || | |
1054 | param->value < 0) | |
1055 | return -EINVAL; | |
1056 | /* Userspace can use first N regs */ | |
1057 | dev_priv->fence_reg_start = param->value; | |
1058 | break; | |
1da177e4 | 1059 | default: |
8a4c47f3 | 1060 | DRM_DEBUG_DRIVER("unknown parameter %d\n", |
be25ed9c | 1061 | param->param); |
20caafa6 | 1062 | return -EINVAL; |
1da177e4 LT |
1063 | } |
1064 | ||
1065 | return 0; | |
1066 | } | |
1067 | ||
c153f45f EA |
1068 | static int i915_set_status_page(struct drm_device *dev, void *data, |
1069 | struct drm_file *file_priv) | |
dc7a9319 | 1070 | { |
4c8a4be9 | 1071 | struct drm_i915_private *dev_priv = dev->dev_private; |
c153f45f | 1072 | drm_i915_hws_addr_t *hws = data; |
4f1ba0f8 | 1073 | struct intel_ring_buffer *ring; |
b39d50e5 | 1074 | |
cd9d4e9f DV |
1075 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
1076 | return -ENODEV; | |
1077 | ||
b39d50e5 ZW |
1078 | if (!I915_NEED_GFX_HWS(dev)) |
1079 | return -EINVAL; | |
dc7a9319 WZ |
1080 | |
1081 | if (!dev_priv) { | |
3e684eae | 1082 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 1083 | return -EINVAL; |
dc7a9319 | 1084 | } |
dc7a9319 | 1085 | |
79e53945 JB |
1086 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
1087 | WARN(1, "tried to set status page when mode setting active\n"); | |
1088 | return 0; | |
1089 | } | |
1090 | ||
8a4c47f3 | 1091 | DRM_DEBUG_DRIVER("set status page addr 0x%08x\n", (u32)hws->addr); |
c153f45f | 1092 | |
4f1ba0f8 | 1093 | ring = LP_RING(dev_priv); |
8187a2b7 | 1094 | ring->status_page.gfx_addr = hws->addr & (0x1ffff<<12); |
dc7a9319 | 1095 | |
dd2757f8 | 1096 | dev_priv->dri1.gfx_hws_cpu_addr = |
5d4545ae | 1097 | ioremap_wc(dev_priv->gtt.mappable_base + hws->addr, 4096); |
316d3884 | 1098 | if (dev_priv->dri1.gfx_hws_cpu_addr == NULL) { |
dc7a9319 | 1099 | i915_dma_cleanup(dev); |
e20f9c64 | 1100 | ring->status_page.gfx_addr = 0; |
dc7a9319 WZ |
1101 | DRM_ERROR("can not ioremap virtual address for" |
1102 | " G33 hw status page\n"); | |
20caafa6 | 1103 | return -ENOMEM; |
dc7a9319 | 1104 | } |
316d3884 DV |
1105 | |
1106 | memset_io(dev_priv->dri1.gfx_hws_cpu_addr, 0, PAGE_SIZE); | |
8187a2b7 | 1107 | I915_WRITE(HWS_PGA, ring->status_page.gfx_addr); |
dc7a9319 | 1108 | |
8a4c47f3 | 1109 | DRM_DEBUG_DRIVER("load hws HWS_PGA with gfx mem 0x%x\n", |
e20f9c64 | 1110 | ring->status_page.gfx_addr); |
8a4c47f3 | 1111 | DRM_DEBUG_DRIVER("load hws at %p\n", |
e20f9c64 | 1112 | ring->status_page.page_addr); |
dc7a9319 WZ |
1113 | return 0; |
1114 | } | |
1115 | ||
ec2a4c3f DA |
1116 | static int i915_get_bridge_dev(struct drm_device *dev) |
1117 | { | |
1118 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1119 | ||
0206e353 | 1120 | dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0)); |
ec2a4c3f DA |
1121 | if (!dev_priv->bridge_dev) { |
1122 | DRM_ERROR("bridge device not found\n"); | |
1123 | return -1; | |
1124 | } | |
1125 | return 0; | |
1126 | } | |
1127 | ||
c4804411 ZW |
1128 | #define MCHBAR_I915 0x44 |
1129 | #define MCHBAR_I965 0x48 | |
1130 | #define MCHBAR_SIZE (4*4096) | |
1131 | ||
1132 | #define DEVEN_REG 0x54 | |
1133 | #define DEVEN_MCHBAR_EN (1 << 28) | |
1134 | ||
1135 | /* Allocate space for the MCH regs if needed, return nonzero on error */ | |
1136 | static int | |
1137 | intel_alloc_mchbar_resource(struct drm_device *dev) | |
1138 | { | |
4c8a4be9 | 1139 | struct drm_i915_private *dev_priv = dev->dev_private; |
a6c45cf0 | 1140 | int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915; |
c4804411 ZW |
1141 | u32 temp_lo, temp_hi = 0; |
1142 | u64 mchbar_addr; | |
a25c25c2 | 1143 | int ret; |
c4804411 | 1144 | |
a6c45cf0 | 1145 | if (INTEL_INFO(dev)->gen >= 4) |
c4804411 ZW |
1146 | pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi); |
1147 | pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo); | |
1148 | mchbar_addr = ((u64)temp_hi << 32) | temp_lo; | |
1149 | ||
1150 | /* If ACPI doesn't have it, assume we need to allocate it ourselves */ | |
1151 | #ifdef CONFIG_PNP | |
1152 | if (mchbar_addr && | |
a25c25c2 CW |
1153 | pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE)) |
1154 | return 0; | |
c4804411 ZW |
1155 | #endif |
1156 | ||
1157 | /* Get some space for it */ | |
a25c25c2 CW |
1158 | dev_priv->mch_res.name = "i915 MCHBAR"; |
1159 | dev_priv->mch_res.flags = IORESOURCE_MEM; | |
1160 | ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus, | |
1161 | &dev_priv->mch_res, | |
c4804411 ZW |
1162 | MCHBAR_SIZE, MCHBAR_SIZE, |
1163 | PCIBIOS_MIN_MEM, | |
a25c25c2 | 1164 | 0, pcibios_align_resource, |
c4804411 ZW |
1165 | dev_priv->bridge_dev); |
1166 | if (ret) { | |
1167 | DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret); | |
1168 | dev_priv->mch_res.start = 0; | |
a25c25c2 | 1169 | return ret; |
c4804411 ZW |
1170 | } |
1171 | ||
a6c45cf0 | 1172 | if (INTEL_INFO(dev)->gen >= 4) |
c4804411 ZW |
1173 | pci_write_config_dword(dev_priv->bridge_dev, reg + 4, |
1174 | upper_32_bits(dev_priv->mch_res.start)); | |
1175 | ||
1176 | pci_write_config_dword(dev_priv->bridge_dev, reg, | |
1177 | lower_32_bits(dev_priv->mch_res.start)); | |
a25c25c2 | 1178 | return 0; |
c4804411 ZW |
1179 | } |
1180 | ||
1181 | /* Setup MCHBAR if possible, return true if we should disable it again */ | |
1182 | static void | |
1183 | intel_setup_mchbar(struct drm_device *dev) | |
1184 | { | |
4c8a4be9 | 1185 | struct drm_i915_private *dev_priv = dev->dev_private; |
a6c45cf0 | 1186 | int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915; |
c4804411 ZW |
1187 | u32 temp; |
1188 | bool enabled; | |
1189 | ||
11ea8b7d JB |
1190 | if (IS_VALLEYVIEW(dev)) |
1191 | return; | |
1192 | ||
c4804411 ZW |
1193 | dev_priv->mchbar_need_disable = false; |
1194 | ||
1195 | if (IS_I915G(dev) || IS_I915GM(dev)) { | |
1196 | pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp); | |
1197 | enabled = !!(temp & DEVEN_MCHBAR_EN); | |
1198 | } else { | |
1199 | pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); | |
1200 | enabled = temp & 1; | |
1201 | } | |
1202 | ||
1203 | /* If it's already enabled, don't have to do anything */ | |
1204 | if (enabled) | |
1205 | return; | |
1206 | ||
1207 | if (intel_alloc_mchbar_resource(dev)) | |
1208 | return; | |
1209 | ||
1210 | dev_priv->mchbar_need_disable = true; | |
1211 | ||
1212 | /* Space is allocated or reserved, so enable it. */ | |
1213 | if (IS_I915G(dev) || IS_I915GM(dev)) { | |
1214 | pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, | |
1215 | temp | DEVEN_MCHBAR_EN); | |
1216 | } else { | |
1217 | pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); | |
1218 | pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1); | |
1219 | } | |
1220 | } | |
1221 | ||
1222 | static void | |
1223 | intel_teardown_mchbar(struct drm_device *dev) | |
1224 | { | |
4c8a4be9 | 1225 | struct drm_i915_private *dev_priv = dev->dev_private; |
a6c45cf0 | 1226 | int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915; |
c4804411 ZW |
1227 | u32 temp; |
1228 | ||
1229 | if (dev_priv->mchbar_need_disable) { | |
1230 | if (IS_I915G(dev) || IS_I915GM(dev)) { | |
1231 | pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp); | |
1232 | temp &= ~DEVEN_MCHBAR_EN; | |
1233 | pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp); | |
1234 | } else { | |
1235 | pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); | |
1236 | temp &= ~1; | |
1237 | pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp); | |
1238 | } | |
1239 | } | |
1240 | ||
1241 | if (dev_priv->mch_res.start) | |
1242 | release_resource(&dev_priv->mch_res); | |
1243 | } | |
1244 | ||
28d52043 DA |
1245 | /* true = enable decode, false = disable decoder */ |
1246 | static unsigned int i915_vga_set_decode(void *cookie, bool state) | |
1247 | { | |
1248 | struct drm_device *dev = cookie; | |
1249 | ||
1250 | intel_modeset_vga_set_state(dev, state); | |
1251 | if (state) | |
1252 | return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | | |
1253 | VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
1254 | else | |
1255 | return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
1256 | } | |
1257 | ||
6a9ee8af DA |
1258 | static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state) |
1259 | { | |
1260 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1261 | pm_message_t pmm = { .event = PM_EVENT_SUSPEND }; | |
1262 | if (state == VGA_SWITCHEROO_ON) { | |
a70491cc | 1263 | pr_info("switched on\n"); |
5bcf719b | 1264 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; |
6a9ee8af DA |
1265 | /* i915 resume handler doesn't set to D0 */ |
1266 | pci_set_power_state(dev->pdev, PCI_D0); | |
1267 | i915_resume(dev); | |
5bcf719b | 1268 | dev->switch_power_state = DRM_SWITCH_POWER_ON; |
6a9ee8af | 1269 | } else { |
a70491cc | 1270 | pr_err("switched off\n"); |
5bcf719b | 1271 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; |
6a9ee8af | 1272 | i915_suspend(dev, pmm); |
5bcf719b | 1273 | dev->switch_power_state = DRM_SWITCH_POWER_OFF; |
6a9ee8af DA |
1274 | } |
1275 | } | |
1276 | ||
1277 | static bool i915_switcheroo_can_switch(struct pci_dev *pdev) | |
1278 | { | |
1279 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1280 | bool can_switch; | |
1281 | ||
1282 | spin_lock(&dev->count_lock); | |
1283 | can_switch = (dev->open_count == 0); | |
1284 | spin_unlock(&dev->count_lock); | |
1285 | return can_switch; | |
1286 | } | |
1287 | ||
26ec685f TI |
1288 | static const struct vga_switcheroo_client_ops i915_switcheroo_ops = { |
1289 | .set_gpu_state = i915_switcheroo_set_state, | |
1290 | .reprobe = NULL, | |
1291 | .can_switch = i915_switcheroo_can_switch, | |
1292 | }; | |
1293 | ||
2c7111db CW |
1294 | static int i915_load_modeset_init(struct drm_device *dev) |
1295 | { | |
1296 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1297 | int ret; | |
79e53945 | 1298 | |
6d139a87 | 1299 | ret = intel_parse_bios(dev); |
79e53945 JB |
1300 | if (ret) |
1301 | DRM_INFO("failed to find VBIOS tables\n"); | |
1302 | ||
934f992c CW |
1303 | /* If we have > 1 VGA cards, then we need to arbitrate access |
1304 | * to the common VGA resources. | |
1305 | * | |
1306 | * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA), | |
1307 | * then we do not take part in VGA arbitration and the | |
1308 | * vga_client_register() fails with -ENODEV. | |
1309 | */ | |
ebff5fa9 DA |
1310 | ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode); |
1311 | if (ret && ret != -ENODEV) | |
1312 | goto out; | |
28d52043 | 1313 | |
723bfd70 JB |
1314 | intel_register_dsm_handler(); |
1315 | ||
0d69704a | 1316 | ret = vga_switcheroo_register_client(dev->pdev, &i915_switcheroo_ops, false); |
6a9ee8af | 1317 | if (ret) |
5a79395b | 1318 | goto cleanup_vga_client; |
6a9ee8af | 1319 | |
9797fbfb CW |
1320 | /* Initialise stolen first so that we may reserve preallocated |
1321 | * objects for the BIOS to KMS transition. | |
1322 | */ | |
1323 | ret = i915_gem_init_stolen(dev); | |
1324 | if (ret) | |
1325 | goto cleanup_vga_switcheroo; | |
1326 | ||
e13192f6 ID |
1327 | intel_power_domains_init_hw(dev_priv); |
1328 | ||
52d7eced DV |
1329 | ret = drm_irq_install(dev); |
1330 | if (ret) | |
1331 | goto cleanup_gem_stolen; | |
1332 | ||
1333 | /* Important: The output setup functions called by modeset_init need | |
1334 | * working irqs for e.g. gmbus and dp aux transfers. */ | |
b01f2c3a JB |
1335 | intel_modeset_init(dev); |
1336 | ||
1070a42b | 1337 | ret = i915_gem_init(dev); |
79e53945 | 1338 | if (ret) |
a1485320 | 1339 | goto cleanup_power; |
2c7111db | 1340 | |
073f34d9 JB |
1341 | INIT_WORK(&dev_priv->console_resume_work, intel_console_resume); |
1342 | ||
52d7eced | 1343 | intel_modeset_gem_init(dev); |
2c7111db | 1344 | |
79e53945 JB |
1345 | /* Always safe in the mode setting case. */ |
1346 | /* FIXME: do pre/post-mode set stuff in core KMS code */ | |
ba0bf120 | 1347 | dev->vblank_disable_allowed = true; |
ce352550 | 1348 | if (INTEL_INFO(dev)->num_pipes == 0) { |
da7e29bd | 1349 | intel_display_power_put(dev_priv, POWER_DOMAIN_VGA); |
e3c74757 | 1350 | return 0; |
ce352550 | 1351 | } |
79e53945 | 1352 | |
5a79395b CW |
1353 | ret = intel_fbdev_init(dev); |
1354 | if (ret) | |
52d7eced DV |
1355 | goto cleanup_gem; |
1356 | ||
20afbda2 DV |
1357 | /* Only enable hotplug handling once the fbdev is fully set up. */ |
1358 | intel_hpd_init(dev); | |
1359 | ||
1360 | /* | |
1361 | * Some ports require correctly set-up hpd registers for detection to | |
1362 | * work properly (leading to ghost connected connector status), e.g. VGA | |
1363 | * on gm45. Hence we can only set up the initial fbdev config after hpd | |
1364 | * irqs are fully enabled. Now we should scan for the initial config | |
1365 | * only once hotplug handling is enabled, but due to screwed-up locking | |
1366 | * around kms/fbdev init we can't protect the fdbev initial config | |
1367 | * scanning against hotplug events. Hence do this first and ignore the | |
1368 | * tiny window where we will loose hotplug notifactions. | |
1369 | */ | |
1370 | intel_fbdev_initial_config(dev); | |
1371 | ||
52d7eced DV |
1372 | /* Only enable hotplug handling once the fbdev is fully set up. */ |
1373 | dev_priv->enable_hotplug_processing = true; | |
5a79395b | 1374 | |
eb1f8e4f | 1375 | drm_kms_helper_poll_init(dev); |
87acb0a5 | 1376 | |
79e53945 JB |
1377 | return 0; |
1378 | ||
2c7111db CW |
1379 | cleanup_gem: |
1380 | mutex_lock(&dev->struct_mutex); | |
1381 | i915_gem_cleanup_ringbuffer(dev); | |
55d23285 | 1382 | i915_gem_context_fini(dev); |
2c7111db | 1383 | mutex_unlock(&dev->struct_mutex); |
bdf4fd7e | 1384 | WARN_ON(dev_priv->mm.aliasing_ppgtt); |
93bd8649 | 1385 | drm_mm_takedown(&dev_priv->gtt.base.mm); |
a1485320 | 1386 | cleanup_power: |
da7e29bd | 1387 | intel_display_power_put(dev_priv, POWER_DOMAIN_VGA); |
52d7eced | 1388 | drm_irq_uninstall(dev); |
9797fbfb CW |
1389 | cleanup_gem_stolen: |
1390 | i915_gem_cleanup_stolen(dev); | |
5a79395b CW |
1391 | cleanup_vga_switcheroo: |
1392 | vga_switcheroo_unregister_client(dev->pdev); | |
1393 | cleanup_vga_client: | |
1394 | vga_client_register(dev->pdev, NULL, NULL, NULL); | |
79e53945 JB |
1395 | out: |
1396 | return ret; | |
1397 | } | |
1398 | ||
7c1c2871 DA |
1399 | int i915_master_create(struct drm_device *dev, struct drm_master *master) |
1400 | { | |
1401 | struct drm_i915_master_private *master_priv; | |
1402 | ||
9a298b2a | 1403 | master_priv = kzalloc(sizeof(*master_priv), GFP_KERNEL); |
7c1c2871 DA |
1404 | if (!master_priv) |
1405 | return -ENOMEM; | |
1406 | ||
1407 | master->driver_priv = master_priv; | |
1408 | return 0; | |
1409 | } | |
1410 | ||
1411 | void i915_master_destroy(struct drm_device *dev, struct drm_master *master) | |
1412 | { | |
1413 | struct drm_i915_master_private *master_priv = master->driver_priv; | |
1414 | ||
1415 | if (!master_priv) | |
1416 | return; | |
1417 | ||
9a298b2a | 1418 | kfree(master_priv); |
7c1c2871 DA |
1419 | |
1420 | master->driver_priv = NULL; | |
1421 | } | |
1422 | ||
243eaf38 | 1423 | #if IS_ENABLED(CONFIG_FB) |
e188719a DV |
1424 | static void i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv) |
1425 | { | |
1426 | struct apertures_struct *ap; | |
1427 | struct pci_dev *pdev = dev_priv->dev->pdev; | |
1428 | bool primary; | |
1429 | ||
1430 | ap = alloc_apertures(1); | |
1431 | if (!ap) | |
1432 | return; | |
1433 | ||
dabb7a91 | 1434 | ap->ranges[0].base = dev_priv->gtt.mappable_base; |
f64e2922 | 1435 | ap->ranges[0].size = dev_priv->gtt.mappable_end; |
93d18799 | 1436 | |
e188719a DV |
1437 | primary = |
1438 | pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW; | |
1439 | ||
1440 | remove_conflicting_framebuffers(ap, "inteldrmfb", primary); | |
1441 | ||
1442 | kfree(ap); | |
1443 | } | |
4520f53a DV |
1444 | #else |
1445 | static void i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv) | |
1446 | { | |
1447 | } | |
1448 | #endif | |
e188719a | 1449 | |
c96ea64e DV |
1450 | static void i915_dump_device_info(struct drm_i915_private *dev_priv) |
1451 | { | |
5c969aa7 | 1452 | const struct intel_device_info *info = &dev_priv->info; |
c96ea64e | 1453 | |
e2a5800a DL |
1454 | #define PRINT_S(name) "%s" |
1455 | #define SEP_EMPTY | |
79fc46df DL |
1456 | #define PRINT_FLAG(name) info->name ? #name "," : "" |
1457 | #define SEP_COMMA , | |
c96ea64e | 1458 | DRM_DEBUG_DRIVER("i915 device info: gen=%i, pciid=0x%04x flags=" |
e2a5800a | 1459 | DEV_INFO_FOR_EACH_FLAG(PRINT_S, SEP_EMPTY), |
c96ea64e DV |
1460 | info->gen, |
1461 | dev_priv->dev->pdev->device, | |
79fc46df | 1462 | DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_COMMA)); |
e2a5800a DL |
1463 | #undef PRINT_S |
1464 | #undef SEP_EMPTY | |
79fc46df DL |
1465 | #undef PRINT_FLAG |
1466 | #undef SEP_COMMA | |
c96ea64e DV |
1467 | } |
1468 | ||
22d3fd46 DL |
1469 | /* |
1470 | * Determine various intel_device_info fields at runtime. | |
1471 | * | |
1472 | * Use it when either: | |
1473 | * - it's judged too laborious to fill n static structures with the limit | |
1474 | * when a simple if statement does the job, | |
1475 | * - run-time checks (eg read fuse/strap registers) are needed. | |
658ac4c6 DL |
1476 | * |
1477 | * This function needs to be called: | |
1478 | * - after the MMIO has been setup as we are reading registers, | |
1479 | * - after the PCH has been detected, | |
1480 | * - before the first usage of the fields it can tweak. | |
22d3fd46 DL |
1481 | */ |
1482 | static void intel_device_info_runtime_init(struct drm_device *dev) | |
1483 | { | |
658ac4c6 | 1484 | struct drm_i915_private *dev_priv = dev->dev_private; |
22d3fd46 | 1485 | struct intel_device_info *info; |
d615a166 | 1486 | enum pipe pipe; |
22d3fd46 | 1487 | |
658ac4c6 | 1488 | info = (struct intel_device_info *)&dev_priv->info; |
22d3fd46 | 1489 | |
22d3fd46 | 1490 | if (IS_VALLEYVIEW(dev)) |
d615a166 DL |
1491 | for_each_pipe(pipe) |
1492 | info->num_sprites[pipe] = 2; | |
1493 | else | |
1494 | for_each_pipe(pipe) | |
1495 | info->num_sprites[pipe] = 1; | |
658ac4c6 | 1496 | |
a0bae57f DL |
1497 | if (i915.disable_display) { |
1498 | DRM_INFO("Display disabled (module parameter)\n"); | |
1499 | info->num_pipes = 0; | |
1500 | } else if (info->num_pipes > 0 && | |
1501 | (INTEL_INFO(dev)->gen == 7 || INTEL_INFO(dev)->gen == 8) && | |
1502 | !IS_VALLEYVIEW(dev)) { | |
658ac4c6 DL |
1503 | u32 fuse_strap = I915_READ(FUSE_STRAP); |
1504 | u32 sfuse_strap = I915_READ(SFUSE_STRAP); | |
1505 | ||
1506 | /* | |
1507 | * SFUSE_STRAP is supposed to have a bit signalling the display | |
1508 | * is fused off. Unfortunately it seems that, at least in | |
1509 | * certain cases, fused off display means that PCH display | |
1510 | * reads don't land anywhere. In that case, we read 0s. | |
1511 | * | |
1512 | * On CPT/PPT, we can detect this case as SFUSE_STRAP_FUSE_LOCK | |
1513 | * should be set when taking over after the firmware. | |
1514 | */ | |
1515 | if (fuse_strap & ILK_INTERNAL_DISPLAY_DISABLE || | |
1516 | sfuse_strap & SFUSE_STRAP_DISPLAY_DISABLED || | |
1517 | (dev_priv->pch_type == PCH_CPT && | |
1518 | !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) { | |
1519 | DRM_INFO("Display fused off, disabling\n"); | |
1520 | info->num_pipes = 0; | |
1521 | } | |
1522 | } | |
22d3fd46 DL |
1523 | } |
1524 | ||
79e53945 JB |
1525 | /** |
1526 | * i915_driver_load - setup chip and create an initial config | |
1527 | * @dev: DRM device | |
1528 | * @flags: startup flags | |
1529 | * | |
1530 | * The driver load routine has to do several things: | |
1531 | * - drive output discovery via intel_modeset_init() | |
1532 | * - initialize the memory manager | |
1533 | * - allocate initial config memory | |
1534 | * - setup the DRM framebuffer with the allocated memory | |
1535 | */ | |
84b1fd10 | 1536 | int i915_driver_load(struct drm_device *dev, unsigned long flags) |
22eae947 | 1537 | { |
ea059a1e | 1538 | struct drm_i915_private *dev_priv; |
5c969aa7 | 1539 | struct intel_device_info *info, *device_info; |
934d6086 | 1540 | int ret = 0, mmio_bar, mmio_size; |
9021f284 | 1541 | uint32_t aperture_size; |
fe669bf8 | 1542 | |
26394d92 DV |
1543 | info = (struct intel_device_info *) flags; |
1544 | ||
1545 | /* Refuse to load on gen6+ without kms enabled. */ | |
e147accb JN |
1546 | if (info->gen >= 6 && !drm_core_check_feature(dev, DRIVER_MODESET)) { |
1547 | DRM_INFO("Your hardware requires kernel modesetting (KMS)\n"); | |
1548 | DRM_INFO("See CONFIG_DRM_I915_KMS, nomodeset, and i915.modeset parameters\n"); | |
26394d92 | 1549 | return -ENODEV; |
e147accb | 1550 | } |
26394d92 | 1551 | |
24986ee0 DV |
1552 | /* UMS needs agp support. */ |
1553 | if (!drm_core_check_feature(dev, DRIVER_MODESET) && !dev->agp) | |
1554 | return -EINVAL; | |
1555 | ||
b14c5679 | 1556 | dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL); |
ba8bbcf6 JB |
1557 | if (dev_priv == NULL) |
1558 | return -ENOMEM; | |
1559 | ||
ba8bbcf6 | 1560 | dev->dev_private = (void *)dev_priv; |
673a394b | 1561 | dev_priv->dev = dev; |
5c969aa7 DL |
1562 | |
1563 | /* copy initial configuration to dev_priv->info */ | |
1564 | device_info = (struct intel_device_info *)&dev_priv->info; | |
1565 | *device_info = *info; | |
ba8bbcf6 | 1566 | |
7dcd2677 KK |
1567 | spin_lock_init(&dev_priv->irq_lock); |
1568 | spin_lock_init(&dev_priv->gpu_error.lock); | |
58c68779 | 1569 | spin_lock_init(&dev_priv->backlight_lock); |
907b28c5 | 1570 | spin_lock_init(&dev_priv->uncore.lock); |
c20e8355 | 1571 | spin_lock_init(&dev_priv->mm.object_stat_lock); |
7dcd2677 | 1572 | mutex_init(&dev_priv->dpio_lock); |
7dcd2677 KK |
1573 | mutex_init(&dev_priv->modeset_restore_lock); |
1574 | ||
f742a552 | 1575 | intel_pm_setup(dev); |
c67a470b | 1576 | |
07144428 DL |
1577 | intel_display_crc_init(dev); |
1578 | ||
c96ea64e DV |
1579 | i915_dump_device_info(dev_priv); |
1580 | ||
ed1c9e2c PZ |
1581 | /* Not all pre-production machines fall into this category, only the |
1582 | * very first ones. Almost everything should work, except for maybe | |
1583 | * suspend/resume. And we don't implement workarounds that affect only | |
1584 | * pre-production machines. */ | |
1585 | if (IS_HSW_EARLY_SDV(dev)) | |
1586 | DRM_INFO("This is an early pre-production Haswell machine. " | |
1587 | "It may not be fully functional.\n"); | |
1588 | ||
ec2a4c3f DA |
1589 | if (i915_get_bridge_dev(dev)) { |
1590 | ret = -EIO; | |
1591 | goto free_priv; | |
1592 | } | |
1593 | ||
1e1bd0fd BW |
1594 | mmio_bar = IS_GEN2(dev) ? 1 : 0; |
1595 | /* Before gen4, the registers and the GTT are behind different BARs. | |
1596 | * However, from gen4 onwards, the registers and the GTT are shared | |
1597 | * in the same BAR, so we want to restrict this ioremap from | |
1598 | * clobbering the GTT which we want ioremap_wc instead. Fortunately, | |
1599 | * the register BAR remains the same size for all the earlier | |
1600 | * generations up to Ironlake. | |
1601 | */ | |
1602 | if (info->gen < 5) | |
1603 | mmio_size = 512*1024; | |
1604 | else | |
1605 | mmio_size = 2*1024*1024; | |
1606 | ||
1607 | dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, mmio_size); | |
1608 | if (!dev_priv->regs) { | |
1609 | DRM_ERROR("failed to map registers\n"); | |
1610 | ret = -EIO; | |
1611 | goto put_bridge; | |
1612 | } | |
1613 | ||
c3d685a7 BW |
1614 | /* This must be called before any calls to HAS_PCH_* */ |
1615 | intel_detect_pch(dev); | |
1616 | ||
1617 | intel_uncore_init(dev); | |
1618 | ||
e76e9aeb BW |
1619 | ret = i915_gem_gtt_init(dev); |
1620 | if (ret) | |
cbb47d17 | 1621 | goto out_regs; |
e188719a | 1622 | |
1623392a CW |
1623 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
1624 | i915_kick_out_firmware_fb(dev_priv); | |
e188719a | 1625 | |
466e69b8 DA |
1626 | pci_set_master(dev->pdev); |
1627 | ||
9f82d238 DV |
1628 | /* overlay on gen2 is broken and can't address above 1G */ |
1629 | if (IS_GEN2(dev)) | |
1630 | dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30)); | |
1631 | ||
6927faf3 JN |
1632 | /* 965GM sometimes incorrectly writes to hardware status page (HWS) |
1633 | * using 32bit addressing, overwriting memory if HWS is located | |
1634 | * above 4GB. | |
1635 | * | |
1636 | * The documentation also mentions an issue with undefined | |
1637 | * behaviour if any general state is accessed within a page above 4GB, | |
1638 | * which also needs to be handled carefully. | |
1639 | */ | |
1640 | if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) | |
1641 | dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(32)); | |
1642 | ||
93d18799 | 1643 | aperture_size = dev_priv->gtt.mappable_end; |
71e9339c | 1644 | |
5d4545ae BW |
1645 | dev_priv->gtt.mappable = |
1646 | io_mapping_create_wc(dev_priv->gtt.mappable_base, | |
dd2757f8 | 1647 | aperture_size); |
5d4545ae | 1648 | if (dev_priv->gtt.mappable == NULL) { |
6644107d | 1649 | ret = -EIO; |
cbb47d17 | 1650 | goto out_gtt; |
6644107d VP |
1651 | } |
1652 | ||
911bdf0a BW |
1653 | dev_priv->gtt.mtrr = arch_phys_wc_add(dev_priv->gtt.mappable_base, |
1654 | aperture_size); | |
19966754 | 1655 | |
e642abbf CW |
1656 | /* The i915 workqueue is primarily used for batched retirement of |
1657 | * requests (and thus managing bo) once the task has been completed | |
1658 | * by the GPU. i915_gem_retire_requests() is called directly when we | |
1659 | * need high-priority retirement, such as waiting for an explicit | |
1660 | * bo. | |
1661 | * | |
1662 | * It is also used for periodic low-priority events, such as | |
df9c2042 | 1663 | * idle-timers and recording error state. |
e642abbf CW |
1664 | * |
1665 | * All tasks on the workqueue are expected to acquire the dev mutex | |
1666 | * so there is no point in running more than one instance of the | |
53621860 | 1667 | * workqueue at any time. Use an ordered one. |
e642abbf | 1668 | */ |
53621860 | 1669 | dev_priv->wq = alloc_ordered_workqueue("i915", 0); |
9c9fe1f8 EA |
1670 | if (dev_priv->wq == NULL) { |
1671 | DRM_ERROR("Failed to create our workqueue.\n"); | |
1672 | ret = -ENOMEM; | |
a7b85d2a | 1673 | goto out_mtrrfree; |
9c9fe1f8 EA |
1674 | } |
1675 | ||
f71d4af4 | 1676 | intel_irq_init(dev); |
78511f2a | 1677 | intel_uncore_sanitize(dev); |
9880b7a5 | 1678 | |
c4804411 ZW |
1679 | /* Try to make sure MCHBAR is enabled before poking at it */ |
1680 | intel_setup_mchbar(dev); | |
f899fc64 | 1681 | intel_setup_gmbus(dev); |
44834a67 | 1682 | intel_opregion_setup(dev); |
c4804411 | 1683 | |
6d139a87 BF |
1684 | intel_setup_bios(dev); |
1685 | ||
673a394b EA |
1686 | i915_gem_load(dev); |
1687 | ||
ed4cb414 EA |
1688 | /* On the 945G/GM, the chipset reports the MSI capability on the |
1689 | * integrated graphics even though the support isn't actually there | |
1690 | * according to the published specs. It doesn't appear to function | |
1691 | * correctly in testing on 945G. | |
1692 | * This may be a side effect of MSI having been made available for PEG | |
1693 | * and the registers being closely associated. | |
d1ed629f KP |
1694 | * |
1695 | * According to chipset errata, on the 965GM, MSI interrupts may | |
b60678a7 KP |
1696 | * be lost or delayed, but we use them anyways to avoid |
1697 | * stuck interrupts on some machines. | |
ed4cb414 | 1698 | */ |
b60678a7 | 1699 | if (!IS_I945G(dev) && !IS_I945GM(dev)) |
d3e74d02 | 1700 | pci_enable_msi(dev->pdev); |
ed4cb414 | 1701 | |
22d3fd46 | 1702 | intel_device_info_runtime_init(dev); |
7f1f3851 | 1703 | |
e3c74757 BW |
1704 | if (INTEL_INFO(dev)->num_pipes) { |
1705 | ret = drm_vblank_init(dev, INTEL_INFO(dev)->num_pipes); | |
1706 | if (ret) | |
1707 | goto out_gem_unload; | |
1708 | } | |
52440211 | 1709 | |
da7e29bd | 1710 | intel_power_domains_init(dev_priv); |
a38911a3 | 1711 | |
79e53945 | 1712 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
53984635 | 1713 | ret = i915_load_modeset_init(dev); |
79e53945 JB |
1714 | if (ret < 0) { |
1715 | DRM_ERROR("failed to init modeset\n"); | |
cbb47d17 | 1716 | goto out_power_well; |
79e53945 | 1717 | } |
db1b76ca DV |
1718 | } else { |
1719 | /* Start out suspended in ums mode. */ | |
1720 | dev_priv->ums.mm_suspended = 1; | |
79e53945 JB |
1721 | } |
1722 | ||
0136db58 BW |
1723 | i915_setup_sysfs(dev); |
1724 | ||
e3c74757 BW |
1725 | if (INTEL_INFO(dev)->num_pipes) { |
1726 | /* Must be done after probing outputs */ | |
1727 | intel_opregion_init(dev); | |
8e5c2b77 | 1728 | acpi_video_register(); |
e3c74757 | 1729 | } |
74a365b3 | 1730 | |
eb48eb00 DV |
1731 | if (IS_GEN5(dev)) |
1732 | intel_gpu_ips_init(dev_priv); | |
63ee41d7 | 1733 | |
8a187455 PZ |
1734 | intel_init_runtime_pm(dev_priv); |
1735 | ||
79e53945 JB |
1736 | return 0; |
1737 | ||
cbb47d17 | 1738 | out_power_well: |
da7e29bd | 1739 | intel_power_domains_remove(dev_priv); |
cbb47d17 | 1740 | drm_vblank_cleanup(dev); |
56e2ea34 | 1741 | out_gem_unload: |
7dc19d5a | 1742 | if (dev_priv->mm.inactive_shrinker.scan_objects) |
a7b85d2a KP |
1743 | unregister_shrinker(&dev_priv->mm.inactive_shrinker); |
1744 | ||
56e2ea34 CW |
1745 | if (dev->pdev->msi_enabled) |
1746 | pci_disable_msi(dev->pdev); | |
1747 | ||
1748 | intel_teardown_gmbus(dev); | |
1749 | intel_teardown_mchbar(dev); | |
22accca0 | 1750 | pm_qos_remove_request(&dev_priv->pm_qos); |
9c9fe1f8 | 1751 | destroy_workqueue(dev_priv->wq); |
a7b85d2a | 1752 | out_mtrrfree: |
911bdf0a | 1753 | arch_phys_wc_del(dev_priv->gtt.mtrr); |
5d4545ae | 1754 | io_mapping_free(dev_priv->gtt.mappable); |
cbb47d17 CW |
1755 | out_gtt: |
1756 | list_del(&dev_priv->gtt.base.global_link); | |
1757 | drm_mm_takedown(&dev_priv->gtt.base.mm); | |
853ba5d2 | 1758 | dev_priv->gtt.base.cleanup(&dev_priv->gtt.base); |
cbb47d17 | 1759 | out_regs: |
c3d685a7 | 1760 | intel_uncore_fini(dev); |
6dda569f | 1761 | pci_iounmap(dev->pdev, dev_priv->regs); |
ec2a4c3f DA |
1762 | put_bridge: |
1763 | pci_dev_put(dev_priv->bridge_dev); | |
79e53945 | 1764 | free_priv: |
cbb47d17 CW |
1765 | if (dev_priv->slab) |
1766 | kmem_cache_destroy(dev_priv->slab); | |
9a298b2a | 1767 | kfree(dev_priv); |
ba8bbcf6 JB |
1768 | return ret; |
1769 | } | |
1770 | ||
1771 | int i915_driver_unload(struct drm_device *dev) | |
1772 | { | |
1773 | struct drm_i915_private *dev_priv = dev->dev_private; | |
c911fc1c | 1774 | int ret; |
ba8bbcf6 | 1775 | |
ce58c32b CW |
1776 | ret = i915_gem_suspend(dev); |
1777 | if (ret) { | |
1778 | DRM_ERROR("failed to idle hardware: %d\n", ret); | |
1779 | return ret; | |
1780 | } | |
1781 | ||
8a187455 PZ |
1782 | intel_fini_runtime_pm(dev_priv); |
1783 | ||
eb48eb00 | 1784 | intel_gpu_ips_teardown(); |
7648fa99 | 1785 | |
1c2256df ID |
1786 | /* The i915.ko module is still not prepared to be loaded when |
1787 | * the power well is not enabled, so just enable it in case | |
1788 | * we're going to unload/reload. */ | |
da7e29bd ID |
1789 | intel_display_set_init_power(dev_priv, true); |
1790 | intel_power_domains_remove(dev_priv); | |
a38911a3 | 1791 | |
0136db58 BW |
1792 | i915_teardown_sysfs(dev); |
1793 | ||
7dc19d5a | 1794 | if (dev_priv->mm.inactive_shrinker.scan_objects) |
17250b71 CW |
1795 | unregister_shrinker(&dev_priv->mm.inactive_shrinker); |
1796 | ||
5d4545ae | 1797 | io_mapping_free(dev_priv->gtt.mappable); |
911bdf0a | 1798 | arch_phys_wc_del(dev_priv->gtt.mtrr); |
ab657db1 | 1799 | |
44834a67 CW |
1800 | acpi_video_unregister(); |
1801 | ||
79e53945 | 1802 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
7b4f3990 | 1803 | intel_fbdev_fini(dev); |
3d8620cc | 1804 | intel_modeset_cleanup(dev); |
073f34d9 | 1805 | cancel_work_sync(&dev_priv->console_resume_work); |
3d8620cc | 1806 | |
6363ee6f ZY |
1807 | /* |
1808 | * free the memory space allocated for the child device | |
1809 | * config parsed from VBT | |
1810 | */ | |
41aa3448 RV |
1811 | if (dev_priv->vbt.child_dev && dev_priv->vbt.child_dev_num) { |
1812 | kfree(dev_priv->vbt.child_dev); | |
1813 | dev_priv->vbt.child_dev = NULL; | |
1814 | dev_priv->vbt.child_dev_num = 0; | |
6363ee6f | 1815 | } |
6c0d9350 | 1816 | |
6a9ee8af | 1817 | vga_switcheroo_unregister_client(dev->pdev); |
28d52043 | 1818 | vga_client_register(dev->pdev, NULL, NULL, NULL); |
79e53945 JB |
1819 | } |
1820 | ||
a8b4899e | 1821 | /* Free error state after interrupts are fully disabled. */ |
99584db3 DV |
1822 | del_timer_sync(&dev_priv->gpu_error.hangcheck_timer); |
1823 | cancel_work_sync(&dev_priv->gpu_error.work); | |
a8b4899e | 1824 | i915_destroy_error_state(dev); |
bc0c7f14 | 1825 | |
ed4cb414 EA |
1826 | if (dev->pdev->msi_enabled) |
1827 | pci_disable_msi(dev->pdev); | |
1828 | ||
44834a67 | 1829 | intel_opregion_fini(dev); |
8ee1c3db | 1830 | |
79e53945 | 1831 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
67e77c5a DV |
1832 | /* Flush any outstanding unpin_work. */ |
1833 | flush_workqueue(dev_priv->wq); | |
1834 | ||
79e53945 JB |
1835 | mutex_lock(&dev->struct_mutex); |
1836 | i915_gem_cleanup_ringbuffer(dev); | |
55a66628 | 1837 | i915_gem_context_fini(dev); |
bdf4fd7e | 1838 | WARN_ON(dev_priv->mm.aliasing_ppgtt); |
79e53945 | 1839 | mutex_unlock(&dev->struct_mutex); |
9797fbfb | 1840 | i915_gem_cleanup_stolen(dev); |
c2873e96 KP |
1841 | |
1842 | if (!I915_NEED_GFX_HWS(dev)) | |
1843 | i915_free_hws(dev); | |
79e53945 JB |
1844 | } |
1845 | ||
a7bbbd63 BW |
1846 | list_del(&dev_priv->gtt.base.global_link); |
1847 | WARN_ON(!list_empty(&dev_priv->vm_list)); | |
701394cc | 1848 | |
cbb47d17 CW |
1849 | drm_vblank_cleanup(dev); |
1850 | ||
f899fc64 | 1851 | intel_teardown_gmbus(dev); |
c4804411 ZW |
1852 | intel_teardown_mchbar(dev); |
1853 | ||
bc0c7f14 | 1854 | destroy_workqueue(dev_priv->wq); |
9ee32fea | 1855 | pm_qos_remove_request(&dev_priv->pm_qos); |
bc0c7f14 | 1856 | |
853ba5d2 | 1857 | dev_priv->gtt.base.cleanup(&dev_priv->gtt.base); |
6640aab6 | 1858 | |
aec347ab CW |
1859 | intel_uncore_fini(dev); |
1860 | if (dev_priv->regs != NULL) | |
1861 | pci_iounmap(dev->pdev, dev_priv->regs); | |
1862 | ||
42dcedd4 CW |
1863 | if (dev_priv->slab) |
1864 | kmem_cache_destroy(dev_priv->slab); | |
bc0c7f14 | 1865 | |
ec2a4c3f | 1866 | pci_dev_put(dev_priv->bridge_dev); |
9a298b2a | 1867 | kfree(dev->dev_private); |
ba8bbcf6 | 1868 | |
22eae947 DA |
1869 | return 0; |
1870 | } | |
1871 | ||
f787a5f5 | 1872 | int i915_driver_open(struct drm_device *dev, struct drm_file *file) |
673a394b | 1873 | { |
b29c19b6 | 1874 | int ret; |
673a394b | 1875 | |
b29c19b6 CW |
1876 | ret = i915_gem_open(dev, file); |
1877 | if (ret) | |
1878 | return ret; | |
254f965c | 1879 | |
673a394b EA |
1880 | return 0; |
1881 | } | |
1882 | ||
79e53945 JB |
1883 | /** |
1884 | * i915_driver_lastclose - clean up after all DRM clients have exited | |
1885 | * @dev: DRM device | |
1886 | * | |
1887 | * Take care of cleaning up after all DRM clients have exited. In the | |
1888 | * mode setting case, we want to restore the kernel's initial mode (just | |
1889 | * in case the last client left us in a bad state). | |
1890 | * | |
9021f284 | 1891 | * Additionally, in the non-mode setting case, we'll tear down the GTT |
79e53945 JB |
1892 | * and DMA structures, since the kernel won't be using them, and clea |
1893 | * up any GEM state. | |
1894 | */ | |
84b1fd10 | 1895 | void i915_driver_lastclose(struct drm_device * dev) |
1da177e4 | 1896 | { |
4c8a4be9 | 1897 | struct drm_i915_private *dev_priv = dev->dev_private; |
ba8bbcf6 | 1898 | |
e8aeaee7 DV |
1899 | /* On gen6+ we refuse to init without kms enabled, but then the drm core |
1900 | * goes right around and calls lastclose. Check for this and don't clean | |
1901 | * up anything. */ | |
1902 | if (!dev_priv) | |
1903 | return; | |
1904 | ||
1905 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { | |
0632fef6 | 1906 | intel_fbdev_restore_mode(dev); |
6a9ee8af | 1907 | vga_switcheroo_process_delayed_switch(); |
144a75fa | 1908 | return; |
79e53945 | 1909 | } |
144a75fa | 1910 | |
673a394b EA |
1911 | i915_gem_lastclose(dev); |
1912 | ||
b5e89ed5 | 1913 | i915_dma_cleanup(dev); |
1da177e4 LT |
1914 | } |
1915 | ||
6c340eac | 1916 | void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv) |
1da177e4 | 1917 | { |
0d1430a3 | 1918 | mutex_lock(&dev->struct_mutex); |
254f965c | 1919 | i915_gem_context_close(dev, file_priv); |
b962442e | 1920 | i915_gem_release(dev, file_priv); |
0d1430a3 | 1921 | mutex_unlock(&dev->struct_mutex); |
1da177e4 LT |
1922 | } |
1923 | ||
f787a5f5 | 1924 | void i915_driver_postclose(struct drm_device *dev, struct drm_file *file) |
673a394b | 1925 | { |
f787a5f5 | 1926 | struct drm_i915_file_private *file_priv = file->driver_priv; |
673a394b | 1927 | |
f787a5f5 | 1928 | kfree(file_priv); |
673a394b EA |
1929 | } |
1930 | ||
baa70943 | 1931 | const struct drm_ioctl_desc i915_ioctls[] = { |
1b2f1489 DA |
1932 | DRM_IOCTL_DEF_DRV(I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
1933 | DRM_IOCTL_DEF_DRV(I915_FLUSH, i915_flush_ioctl, DRM_AUTH), | |
1934 | DRM_IOCTL_DEF_DRV(I915_FLIP, i915_flip_bufs, DRM_AUTH), | |
1935 | DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH), | |
1936 | DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH), | |
1937 | DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH), | |
10ba5012 | 1938 | DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH|DRM_RENDER_ALLOW), |
1b2f1489 | 1939 | DRM_IOCTL_DEF_DRV(I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
b2c606fe DV |
1940 | DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH), |
1941 | DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH), | |
1942 | DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
1b2f1489 | 1943 | DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH), |
b2c606fe | 1944 | DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
d1c1edbc | 1945 | DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
1b2f1489 DA |
1946 | DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, i915_vblank_pipe_get, DRM_AUTH), |
1947 | DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH), | |
1948 | DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
1949 | DRM_IOCTL_DEF_DRV(I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED), | |
1950 | DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH|DRM_UNLOCKED), | |
10ba5012 | 1951 | DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), |
1b2f1489 DA |
1952 | DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED), |
1953 | DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED), | |
10ba5012 KH |
1954 | DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), |
1955 | DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
1956 | DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
1957 | DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
1b2f1489 DA |
1958 | DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED), |
1959 | DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED), | |
10ba5012 KH |
1960 | DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), |
1961 | DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
1962 | DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
1963 | DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
1964 | DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
1965 | DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
1966 | DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
1967 | DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
1968 | DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
1969 | DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
1b2f1489 | 1970 | DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED), |
10ba5012 | 1971 | DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), |
1b2f1489 DA |
1972 | DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED), |
1973 | DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED), | |
8ea30864 JB |
1974 | DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED), |
1975 | DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, intel_sprite_get_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED), | |
10ba5012 KH |
1976 | DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), |
1977 | DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
1978 | DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
1979 | DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
b6359918 | 1980 | DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_get_reset_stats_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), |
c94f7029 DA |
1981 | }; |
1982 | ||
1983 | int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls); | |
cda17380 | 1984 | |
9021f284 DV |
1985 | /* |
1986 | * This is really ugly: Because old userspace abused the linux agp interface to | |
1987 | * manage the gtt, we need to claim that all intel devices are agp. For | |
1988 | * otherwise the drm core refuses to initialize the agp support code. | |
cda17380 | 1989 | */ |
84b1fd10 | 1990 | int i915_driver_device_is_agp(struct drm_device * dev) |
cda17380 DA |
1991 | { |
1992 | return 1; | |
1993 | } |