Commit | Line | Data |
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1da177e4 LT |
1 | /* i915_dma.c -- DMA support for the I915 -*- linux-c -*- |
2 | */ | |
0d6aa60b | 3 | /* |
1da177e4 LT |
4 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
5 | * All Rights Reserved. | |
bc54fd1a DA |
6 | * |
7 | * Permission is hereby granted, free of charge, to any person obtaining a | |
8 | * copy of this software and associated documentation files (the | |
9 | * "Software"), to deal in the Software without restriction, including | |
10 | * without limitation the rights to use, copy, modify, merge, publish, | |
11 | * distribute, sub license, and/or sell copies of the Software, and to | |
12 | * permit persons to whom the Software is furnished to do so, subject to | |
13 | * the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice (including the | |
16 | * next paragraph) shall be included in all copies or substantial portions | |
17 | * of the Software. | |
18 | * | |
19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
20 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
21 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
22 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
23 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
24 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
25 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
26 | * | |
0d6aa60b | 27 | */ |
1da177e4 LT |
28 | |
29 | #include "drmP.h" | |
30 | #include "drm.h" | |
79e53945 | 31 | #include "drm_crtc_helper.h" |
785b93ef | 32 | #include "drm_fb_helper.h" |
79e53945 | 33 | #include "intel_drv.h" |
1da177e4 LT |
34 | #include "i915_drm.h" |
35 | #include "i915_drv.h" | |
1c5d22f7 | 36 | #include "i915_trace.h" |
dcdb1674 | 37 | #include <linux/pci.h> |
28d52043 | 38 | #include <linux/vgaarb.h> |
c4804411 ZW |
39 | #include <linux/acpi.h> |
40 | #include <linux/pnp.h> | |
6a9ee8af | 41 | #include <linux/vga_switcheroo.h> |
5a0e3ad6 | 42 | #include <linux/slab.h> |
44834a67 | 43 | #include <acpi/video.h> |
1da177e4 | 44 | |
398c9cb2 KP |
45 | /** |
46 | * Sets up the hardware status page for devices that need a physical address | |
47 | * in the register. | |
48 | */ | |
3043c60c | 49 | static int i915_init_phys_hws(struct drm_device *dev) |
398c9cb2 KP |
50 | { |
51 | drm_i915_private_t *dev_priv = dev->dev_private; | |
52 | /* Program Hardware Status Page */ | |
53 | dev_priv->status_page_dmah = | |
e6be8d9d | 54 | drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE); |
398c9cb2 KP |
55 | |
56 | if (!dev_priv->status_page_dmah) { | |
57 | DRM_ERROR("Can not allocate hardware status page\n"); | |
58 | return -ENOMEM; | |
59 | } | |
8187a2b7 ZN |
60 | dev_priv->render_ring.status_page.page_addr |
61 | = dev_priv->status_page_dmah->vaddr; | |
398c9cb2 KP |
62 | dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr; |
63 | ||
8187a2b7 | 64 | memset(dev_priv->render_ring.status_page.page_addr, 0, PAGE_SIZE); |
398c9cb2 | 65 | |
a6c45cf0 | 66 | if (INTEL_INFO(dev)->gen >= 4) |
9b974cc1 ZW |
67 | dev_priv->dma_status_page |= (dev_priv->dma_status_page >> 28) & |
68 | 0xf0; | |
69 | ||
398c9cb2 | 70 | I915_WRITE(HWS_PGA, dev_priv->dma_status_page); |
8a4c47f3 | 71 | DRM_DEBUG_DRIVER("Enabled hardware status page\n"); |
398c9cb2 KP |
72 | return 0; |
73 | } | |
74 | ||
75 | /** | |
76 | * Frees the hardware status page, whether it's a physical address or a virtual | |
77 | * address set up by the X Server. | |
78 | */ | |
3043c60c | 79 | static void i915_free_hws(struct drm_device *dev) |
398c9cb2 KP |
80 | { |
81 | drm_i915_private_t *dev_priv = dev->dev_private; | |
82 | if (dev_priv->status_page_dmah) { | |
83 | drm_pci_free(dev, dev_priv->status_page_dmah); | |
84 | dev_priv->status_page_dmah = NULL; | |
85 | } | |
86 | ||
852835f3 ZN |
87 | if (dev_priv->render_ring.status_page.gfx_addr) { |
88 | dev_priv->render_ring.status_page.gfx_addr = 0; | |
398c9cb2 KP |
89 | drm_core_ioremapfree(&dev_priv->hws_map, dev); |
90 | } | |
91 | ||
92 | /* Need to rewrite hardware status page */ | |
93 | I915_WRITE(HWS_PGA, 0x1ffff000); | |
94 | } | |
95 | ||
84b1fd10 | 96 | void i915_kernel_lost_context(struct drm_device * dev) |
1da177e4 LT |
97 | { |
98 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7c1c2871 | 99 | struct drm_i915_master_private *master_priv; |
8187a2b7 | 100 | struct intel_ring_buffer *ring = &dev_priv->render_ring; |
1da177e4 | 101 | |
79e53945 JB |
102 | /* |
103 | * We should never lose context on the ring with modesetting | |
104 | * as we don't expose it to userspace | |
105 | */ | |
106 | if (drm_core_check_feature(dev, DRIVER_MODESET)) | |
107 | return; | |
108 | ||
585fb111 JB |
109 | ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR; |
110 | ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR; | |
1da177e4 LT |
111 | ring->space = ring->head - (ring->tail + 8); |
112 | if (ring->space < 0) | |
8187a2b7 | 113 | ring->space += ring->size; |
1da177e4 | 114 | |
7c1c2871 DA |
115 | if (!dev->primary->master) |
116 | return; | |
117 | ||
118 | master_priv = dev->primary->master->driver_priv; | |
119 | if (ring->head == ring->tail && master_priv->sarea_priv) | |
120 | master_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY; | |
1da177e4 LT |
121 | } |
122 | ||
84b1fd10 | 123 | static int i915_dma_cleanup(struct drm_device * dev) |
1da177e4 | 124 | { |
ba8bbcf6 | 125 | drm_i915_private_t *dev_priv = dev->dev_private; |
1da177e4 LT |
126 | /* Make sure interrupts are disabled here because the uninstall ioctl |
127 | * may not have been called from userspace and after dev_private | |
128 | * is freed, it's too late. | |
129 | */ | |
ed4cb414 | 130 | if (dev->irq_enabled) |
b5e89ed5 | 131 | drm_irq_uninstall(dev); |
1da177e4 | 132 | |
ee0c6bfb | 133 | mutex_lock(&dev->struct_mutex); |
8187a2b7 | 134 | intel_cleanup_ring_buffer(dev, &dev_priv->render_ring); |
d1b851fc ZN |
135 | if (HAS_BSD(dev)) |
136 | intel_cleanup_ring_buffer(dev, &dev_priv->bsd_ring); | |
ee0c6bfb | 137 | mutex_unlock(&dev->struct_mutex); |
dc7a9319 | 138 | |
398c9cb2 KP |
139 | /* Clear the HWS virtual address at teardown */ |
140 | if (I915_NEED_GFX_HWS(dev)) | |
141 | i915_free_hws(dev); | |
1da177e4 LT |
142 | |
143 | return 0; | |
144 | } | |
145 | ||
ba8bbcf6 | 146 | static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init) |
1da177e4 | 147 | { |
ba8bbcf6 | 148 | drm_i915_private_t *dev_priv = dev->dev_private; |
7c1c2871 | 149 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
1da177e4 | 150 | |
3a03ac1a DA |
151 | master_priv->sarea = drm_getsarea(dev); |
152 | if (master_priv->sarea) { | |
153 | master_priv->sarea_priv = (drm_i915_sarea_t *) | |
154 | ((u8 *)master_priv->sarea->handle + init->sarea_priv_offset); | |
155 | } else { | |
8a4c47f3 | 156 | DRM_DEBUG_DRIVER("sarea not found assuming DRI2 userspace\n"); |
3a03ac1a DA |
157 | } |
158 | ||
673a394b | 159 | if (init->ring_size != 0) { |
8187a2b7 | 160 | if (dev_priv->render_ring.gem_object != NULL) { |
673a394b EA |
161 | i915_dma_cleanup(dev); |
162 | DRM_ERROR("Client tried to initialize ringbuffer in " | |
163 | "GEM mode\n"); | |
164 | return -EINVAL; | |
165 | } | |
1da177e4 | 166 | |
8187a2b7 | 167 | dev_priv->render_ring.size = init->ring_size; |
1da177e4 | 168 | |
d3301d86 EA |
169 | dev_priv->render_ring.map.offset = init->ring_start; |
170 | dev_priv->render_ring.map.size = init->ring_size; | |
171 | dev_priv->render_ring.map.type = 0; | |
172 | dev_priv->render_ring.map.flags = 0; | |
173 | dev_priv->render_ring.map.mtrr = 0; | |
1da177e4 | 174 | |
d3301d86 | 175 | drm_core_ioremap_wc(&dev_priv->render_ring.map, dev); |
673a394b | 176 | |
d3301d86 | 177 | if (dev_priv->render_ring.map.handle == NULL) { |
673a394b EA |
178 | i915_dma_cleanup(dev); |
179 | DRM_ERROR("can not ioremap virtual address for" | |
180 | " ring buffer\n"); | |
181 | return -ENOMEM; | |
182 | } | |
1da177e4 LT |
183 | } |
184 | ||
d3301d86 | 185 | dev_priv->render_ring.virtual_start = dev_priv->render_ring.map.handle; |
1da177e4 | 186 | |
a6b54f3f | 187 | dev_priv->cpp = init->cpp; |
1da177e4 LT |
188 | dev_priv->back_offset = init->back_offset; |
189 | dev_priv->front_offset = init->front_offset; | |
190 | dev_priv->current_page = 0; | |
7c1c2871 DA |
191 | if (master_priv->sarea_priv) |
192 | master_priv->sarea_priv->pf_current_page = 0; | |
1da177e4 | 193 | |
1da177e4 LT |
194 | /* Allow hardware batchbuffers unless told otherwise. |
195 | */ | |
196 | dev_priv->allow_batchbuffer = 1; | |
197 | ||
1da177e4 LT |
198 | return 0; |
199 | } | |
200 | ||
84b1fd10 | 201 | static int i915_dma_resume(struct drm_device * dev) |
1da177e4 LT |
202 | { |
203 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
204 | ||
8187a2b7 | 205 | struct intel_ring_buffer *ring; |
8a4c47f3 | 206 | DRM_DEBUG_DRIVER("%s\n", __func__); |
1da177e4 | 207 | |
8187a2b7 ZN |
208 | ring = &dev_priv->render_ring; |
209 | ||
210 | if (ring->map.handle == NULL) { | |
1da177e4 LT |
211 | DRM_ERROR("can not ioremap virtual address for" |
212 | " ring buffer\n"); | |
20caafa6 | 213 | return -ENOMEM; |
1da177e4 LT |
214 | } |
215 | ||
216 | /* Program Hardware Status Page */ | |
8187a2b7 | 217 | if (!ring->status_page.page_addr) { |
1da177e4 | 218 | DRM_ERROR("Can not find hardware status page\n"); |
20caafa6 | 219 | return -EINVAL; |
1da177e4 | 220 | } |
8a4c47f3 | 221 | DRM_DEBUG_DRIVER("hw status page @ %p\n", |
8187a2b7 ZN |
222 | ring->status_page.page_addr); |
223 | if (ring->status_page.gfx_addr != 0) | |
224 | ring->setup_status_page(dev, ring); | |
dc7a9319 | 225 | else |
585fb111 | 226 | I915_WRITE(HWS_PGA, dev_priv->dma_status_page); |
8187a2b7 | 227 | |
8a4c47f3 | 228 | DRM_DEBUG_DRIVER("Enabled hardware status page\n"); |
1da177e4 LT |
229 | |
230 | return 0; | |
231 | } | |
232 | ||
c153f45f EA |
233 | static int i915_dma_init(struct drm_device *dev, void *data, |
234 | struct drm_file *file_priv) | |
1da177e4 | 235 | { |
c153f45f | 236 | drm_i915_init_t *init = data; |
1da177e4 LT |
237 | int retcode = 0; |
238 | ||
c153f45f | 239 | switch (init->func) { |
1da177e4 | 240 | case I915_INIT_DMA: |
ba8bbcf6 | 241 | retcode = i915_initialize(dev, init); |
1da177e4 LT |
242 | break; |
243 | case I915_CLEANUP_DMA: | |
244 | retcode = i915_dma_cleanup(dev); | |
245 | break; | |
246 | case I915_RESUME_DMA: | |
0d6aa60b | 247 | retcode = i915_dma_resume(dev); |
1da177e4 LT |
248 | break; |
249 | default: | |
20caafa6 | 250 | retcode = -EINVAL; |
1da177e4 LT |
251 | break; |
252 | } | |
253 | ||
254 | return retcode; | |
255 | } | |
256 | ||
257 | /* Implement basically the same security restrictions as hardware does | |
258 | * for MI_BATCH_NON_SECURE. These can be made stricter at any time. | |
259 | * | |
260 | * Most of the calculations below involve calculating the size of a | |
261 | * particular instruction. It's important to get the size right as | |
262 | * that tells us where the next instruction to check is. Any illegal | |
263 | * instruction detected will be given a size of zero, which is a | |
264 | * signal to abort the rest of the buffer. | |
265 | */ | |
266 | static int do_validate_cmd(int cmd) | |
267 | { | |
268 | switch (((cmd >> 29) & 0x7)) { | |
269 | case 0x0: | |
270 | switch ((cmd >> 23) & 0x3f) { | |
271 | case 0x0: | |
272 | return 1; /* MI_NOOP */ | |
273 | case 0x4: | |
274 | return 1; /* MI_FLUSH */ | |
275 | default: | |
276 | return 0; /* disallow everything else */ | |
277 | } | |
278 | break; | |
279 | case 0x1: | |
280 | return 0; /* reserved */ | |
281 | case 0x2: | |
282 | return (cmd & 0xff) + 2; /* 2d commands */ | |
283 | case 0x3: | |
284 | if (((cmd >> 24) & 0x1f) <= 0x18) | |
285 | return 1; | |
286 | ||
287 | switch ((cmd >> 24) & 0x1f) { | |
288 | case 0x1c: | |
289 | return 1; | |
290 | case 0x1d: | |
b5e89ed5 | 291 | switch ((cmd >> 16) & 0xff) { |
1da177e4 LT |
292 | case 0x3: |
293 | return (cmd & 0x1f) + 2; | |
294 | case 0x4: | |
295 | return (cmd & 0xf) + 2; | |
296 | default: | |
297 | return (cmd & 0xffff) + 2; | |
298 | } | |
299 | case 0x1e: | |
300 | if (cmd & (1 << 23)) | |
301 | return (cmd & 0xffff) + 1; | |
302 | else | |
303 | return 1; | |
304 | case 0x1f: | |
305 | if ((cmd & (1 << 23)) == 0) /* inline vertices */ | |
306 | return (cmd & 0x1ffff) + 2; | |
307 | else if (cmd & (1 << 17)) /* indirect random */ | |
308 | if ((cmd & 0xffff) == 0) | |
309 | return 0; /* unknown length, too hard */ | |
310 | else | |
311 | return (((cmd & 0xffff) + 1) / 2) + 1; | |
312 | else | |
313 | return 2; /* indirect sequential */ | |
314 | default: | |
315 | return 0; | |
316 | } | |
317 | default: | |
318 | return 0; | |
319 | } | |
320 | ||
321 | return 0; | |
322 | } | |
323 | ||
324 | static int validate_cmd(int cmd) | |
325 | { | |
326 | int ret = do_validate_cmd(cmd); | |
327 | ||
bc5f4523 | 328 | /* printk("validate_cmd( %x ): %d\n", cmd, ret); */ |
1da177e4 LT |
329 | |
330 | return ret; | |
331 | } | |
332 | ||
201361a5 | 333 | static int i915_emit_cmds(struct drm_device * dev, int *buffer, int dwords) |
1da177e4 LT |
334 | { |
335 | drm_i915_private_t *dev_priv = dev->dev_private; | |
336 | int i; | |
1da177e4 | 337 | |
8187a2b7 | 338 | if ((dwords+1) * sizeof(int) >= dev_priv->render_ring.size - 8) |
20caafa6 | 339 | return -EINVAL; |
de227f5f | 340 | |
c29b669c | 341 | BEGIN_LP_RING((dwords+1)&~1); |
de227f5f | 342 | |
1da177e4 LT |
343 | for (i = 0; i < dwords;) { |
344 | int cmd, sz; | |
345 | ||
201361a5 | 346 | cmd = buffer[i]; |
1da177e4 | 347 | |
1da177e4 | 348 | if ((sz = validate_cmd(cmd)) == 0 || i + sz > dwords) |
20caafa6 | 349 | return -EINVAL; |
1da177e4 | 350 | |
1da177e4 LT |
351 | OUT_RING(cmd); |
352 | ||
353 | while (++i, --sz) { | |
201361a5 | 354 | OUT_RING(buffer[i]); |
1da177e4 | 355 | } |
1da177e4 LT |
356 | } |
357 | ||
de227f5f DA |
358 | if (dwords & 1) |
359 | OUT_RING(0); | |
360 | ||
361 | ADVANCE_LP_RING(); | |
362 | ||
1da177e4 LT |
363 | return 0; |
364 | } | |
365 | ||
673a394b EA |
366 | int |
367 | i915_emit_box(struct drm_device *dev, | |
201361a5 | 368 | struct drm_clip_rect *boxes, |
673a394b | 369 | int i, int DR1, int DR4) |
1da177e4 | 370 | { |
201361a5 | 371 | struct drm_clip_rect box = boxes[i]; |
1da177e4 | 372 | |
1da177e4 LT |
373 | if (box.y2 <= box.y1 || box.x2 <= box.x1 || box.y2 <= 0 || box.x2 <= 0) { |
374 | DRM_ERROR("Bad box %d,%d..%d,%d\n", | |
375 | box.x1, box.y1, box.x2, box.y2); | |
20caafa6 | 376 | return -EINVAL; |
1da177e4 LT |
377 | } |
378 | ||
a6c45cf0 | 379 | if (INTEL_INFO(dev)->gen >= 4) { |
c29b669c AH |
380 | BEGIN_LP_RING(4); |
381 | OUT_RING(GFX_OP_DRAWRECT_INFO_I965); | |
382 | OUT_RING((box.x1 & 0xffff) | (box.y1 << 16)); | |
78eca43d | 383 | OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16)); |
c29b669c AH |
384 | OUT_RING(DR4); |
385 | ADVANCE_LP_RING(); | |
386 | } else { | |
387 | BEGIN_LP_RING(6); | |
388 | OUT_RING(GFX_OP_DRAWRECT_INFO); | |
389 | OUT_RING(DR1); | |
390 | OUT_RING((box.x1 & 0xffff) | (box.y1 << 16)); | |
391 | OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16)); | |
392 | OUT_RING(DR4); | |
393 | OUT_RING(0); | |
394 | ADVANCE_LP_RING(); | |
395 | } | |
1da177e4 LT |
396 | |
397 | return 0; | |
398 | } | |
399 | ||
c29b669c AH |
400 | /* XXX: Emitting the counter should really be moved to part of the IRQ |
401 | * emit. For now, do it in both places: | |
402 | */ | |
403 | ||
84b1fd10 | 404 | static void i915_emit_breadcrumb(struct drm_device *dev) |
de227f5f DA |
405 | { |
406 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7c1c2871 | 407 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
de227f5f | 408 | |
c99b058f | 409 | dev_priv->counter++; |
af6061af | 410 | if (dev_priv->counter > 0x7FFFFFFFUL) |
c99b058f | 411 | dev_priv->counter = 0; |
7c1c2871 DA |
412 | if (master_priv->sarea_priv) |
413 | master_priv->sarea_priv->last_enqueue = dev_priv->counter; | |
de227f5f DA |
414 | |
415 | BEGIN_LP_RING(4); | |
585fb111 | 416 | OUT_RING(MI_STORE_DWORD_INDEX); |
0baf823a | 417 | OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT); |
de227f5f DA |
418 | OUT_RING(dev_priv->counter); |
419 | OUT_RING(0); | |
420 | ADVANCE_LP_RING(); | |
421 | } | |
422 | ||
84b1fd10 | 423 | static int i915_dispatch_cmdbuffer(struct drm_device * dev, |
201361a5 EA |
424 | drm_i915_cmdbuffer_t *cmd, |
425 | struct drm_clip_rect *cliprects, | |
426 | void *cmdbuf) | |
1da177e4 LT |
427 | { |
428 | int nbox = cmd->num_cliprects; | |
429 | int i = 0, count, ret; | |
430 | ||
431 | if (cmd->sz & 0x3) { | |
432 | DRM_ERROR("alignment"); | |
20caafa6 | 433 | return -EINVAL; |
1da177e4 LT |
434 | } |
435 | ||
436 | i915_kernel_lost_context(dev); | |
437 | ||
438 | count = nbox ? nbox : 1; | |
439 | ||
440 | for (i = 0; i < count; i++) { | |
441 | if (i < nbox) { | |
201361a5 | 442 | ret = i915_emit_box(dev, cliprects, i, |
1da177e4 LT |
443 | cmd->DR1, cmd->DR4); |
444 | if (ret) | |
445 | return ret; | |
446 | } | |
447 | ||
201361a5 | 448 | ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4); |
1da177e4 LT |
449 | if (ret) |
450 | return ret; | |
451 | } | |
452 | ||
de227f5f | 453 | i915_emit_breadcrumb(dev); |
1da177e4 LT |
454 | return 0; |
455 | } | |
456 | ||
84b1fd10 | 457 | static int i915_dispatch_batchbuffer(struct drm_device * dev, |
201361a5 EA |
458 | drm_i915_batchbuffer_t * batch, |
459 | struct drm_clip_rect *cliprects) | |
1da177e4 | 460 | { |
1da177e4 LT |
461 | int nbox = batch->num_cliprects; |
462 | int i = 0, count; | |
1da177e4 LT |
463 | |
464 | if ((batch->start | batch->used) & 0x7) { | |
465 | DRM_ERROR("alignment"); | |
20caafa6 | 466 | return -EINVAL; |
1da177e4 LT |
467 | } |
468 | ||
469 | i915_kernel_lost_context(dev); | |
470 | ||
471 | count = nbox ? nbox : 1; | |
472 | ||
473 | for (i = 0; i < count; i++) { | |
474 | if (i < nbox) { | |
201361a5 | 475 | int ret = i915_emit_box(dev, cliprects, i, |
1da177e4 LT |
476 | batch->DR1, batch->DR4); |
477 | if (ret) | |
478 | return ret; | |
479 | } | |
480 | ||
0790d5e1 | 481 | if (!IS_I830(dev) && !IS_845G(dev)) { |
1da177e4 | 482 | BEGIN_LP_RING(2); |
a6c45cf0 | 483 | if (INTEL_INFO(dev)->gen >= 4) { |
21f16289 DA |
484 | OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965); |
485 | OUT_RING(batch->start); | |
486 | } else { | |
487 | OUT_RING(MI_BATCH_BUFFER_START | (2 << 6)); | |
488 | OUT_RING(batch->start | MI_BATCH_NON_SECURE); | |
489 | } | |
1da177e4 LT |
490 | ADVANCE_LP_RING(); |
491 | } else { | |
492 | BEGIN_LP_RING(4); | |
493 | OUT_RING(MI_BATCH_BUFFER); | |
494 | OUT_RING(batch->start | MI_BATCH_NON_SECURE); | |
495 | OUT_RING(batch->start + batch->used - 4); | |
496 | OUT_RING(0); | |
497 | ADVANCE_LP_RING(); | |
498 | } | |
499 | } | |
500 | ||
1cafd347 ZN |
501 | |
502 | if (IS_G4X(dev) || IS_IRONLAKE(dev)) { | |
503 | BEGIN_LP_RING(2); | |
504 | OUT_RING(MI_FLUSH | MI_NO_WRITE_FLUSH | MI_INVALIDATE_ISP); | |
505 | OUT_RING(MI_NOOP); | |
506 | ADVANCE_LP_RING(); | |
507 | } | |
de227f5f | 508 | i915_emit_breadcrumb(dev); |
1da177e4 LT |
509 | |
510 | return 0; | |
511 | } | |
512 | ||
af6061af | 513 | static int i915_dispatch_flip(struct drm_device * dev) |
1da177e4 LT |
514 | { |
515 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7c1c2871 DA |
516 | struct drm_i915_master_private *master_priv = |
517 | dev->primary->master->driver_priv; | |
1da177e4 | 518 | |
7c1c2871 | 519 | if (!master_priv->sarea_priv) |
c99b058f KH |
520 | return -EINVAL; |
521 | ||
8a4c47f3 | 522 | DRM_DEBUG_DRIVER("%s: page=%d pfCurrentPage=%d\n", |
be25ed9c | 523 | __func__, |
524 | dev_priv->current_page, | |
525 | master_priv->sarea_priv->pf_current_page); | |
1da177e4 | 526 | |
af6061af DA |
527 | i915_kernel_lost_context(dev); |
528 | ||
529 | BEGIN_LP_RING(2); | |
585fb111 | 530 | OUT_RING(MI_FLUSH | MI_READ_FLUSH); |
af6061af DA |
531 | OUT_RING(0); |
532 | ADVANCE_LP_RING(); | |
1da177e4 | 533 | |
af6061af DA |
534 | BEGIN_LP_RING(6); |
535 | OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP); | |
536 | OUT_RING(0); | |
537 | if (dev_priv->current_page == 0) { | |
538 | OUT_RING(dev_priv->back_offset); | |
539 | dev_priv->current_page = 1; | |
1da177e4 | 540 | } else { |
af6061af DA |
541 | OUT_RING(dev_priv->front_offset); |
542 | dev_priv->current_page = 0; | |
1da177e4 | 543 | } |
af6061af DA |
544 | OUT_RING(0); |
545 | ADVANCE_LP_RING(); | |
1da177e4 | 546 | |
af6061af DA |
547 | BEGIN_LP_RING(2); |
548 | OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP); | |
549 | OUT_RING(0); | |
550 | ADVANCE_LP_RING(); | |
1da177e4 | 551 | |
7c1c2871 | 552 | master_priv->sarea_priv->last_enqueue = dev_priv->counter++; |
1da177e4 LT |
553 | |
554 | BEGIN_LP_RING(4); | |
585fb111 | 555 | OUT_RING(MI_STORE_DWORD_INDEX); |
0baf823a | 556 | OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT); |
af6061af DA |
557 | OUT_RING(dev_priv->counter); |
558 | OUT_RING(0); | |
1da177e4 LT |
559 | ADVANCE_LP_RING(); |
560 | ||
7c1c2871 | 561 | master_priv->sarea_priv->pf_current_page = dev_priv->current_page; |
af6061af | 562 | return 0; |
1da177e4 LT |
563 | } |
564 | ||
84b1fd10 | 565 | static int i915_quiescent(struct drm_device * dev) |
1da177e4 LT |
566 | { |
567 | drm_i915_private_t *dev_priv = dev->dev_private; | |
568 | ||
569 | i915_kernel_lost_context(dev); | |
8187a2b7 ZN |
570 | return intel_wait_ring_buffer(dev, &dev_priv->render_ring, |
571 | dev_priv->render_ring.size - 8); | |
1da177e4 LT |
572 | } |
573 | ||
c153f45f EA |
574 | static int i915_flush_ioctl(struct drm_device *dev, void *data, |
575 | struct drm_file *file_priv) | |
1da177e4 | 576 | { |
546b0974 EA |
577 | int ret; |
578 | ||
579 | RING_LOCK_TEST_WITH_RETURN(dev, file_priv); | |
1da177e4 | 580 | |
546b0974 EA |
581 | mutex_lock(&dev->struct_mutex); |
582 | ret = i915_quiescent(dev); | |
583 | mutex_unlock(&dev->struct_mutex); | |
584 | ||
585 | return ret; | |
1da177e4 LT |
586 | } |
587 | ||
c153f45f EA |
588 | static int i915_batchbuffer(struct drm_device *dev, void *data, |
589 | struct drm_file *file_priv) | |
1da177e4 | 590 | { |
1da177e4 | 591 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
7c1c2871 | 592 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
1da177e4 | 593 | drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *) |
7c1c2871 | 594 | master_priv->sarea_priv; |
c153f45f | 595 | drm_i915_batchbuffer_t *batch = data; |
1da177e4 | 596 | int ret; |
201361a5 | 597 | struct drm_clip_rect *cliprects = NULL; |
1da177e4 LT |
598 | |
599 | if (!dev_priv->allow_batchbuffer) { | |
600 | DRM_ERROR("Batchbuffer ioctl disabled\n"); | |
20caafa6 | 601 | return -EINVAL; |
1da177e4 LT |
602 | } |
603 | ||
8a4c47f3 | 604 | DRM_DEBUG_DRIVER("i915 batchbuffer, start %x used %d cliprects %d\n", |
be25ed9c | 605 | batch->start, batch->used, batch->num_cliprects); |
1da177e4 | 606 | |
546b0974 | 607 | RING_LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 | 608 | |
201361a5 EA |
609 | if (batch->num_cliprects < 0) |
610 | return -EINVAL; | |
611 | ||
612 | if (batch->num_cliprects) { | |
9a298b2a EA |
613 | cliprects = kcalloc(batch->num_cliprects, |
614 | sizeof(struct drm_clip_rect), | |
615 | GFP_KERNEL); | |
201361a5 EA |
616 | if (cliprects == NULL) |
617 | return -ENOMEM; | |
618 | ||
619 | ret = copy_from_user(cliprects, batch->cliprects, | |
620 | batch->num_cliprects * | |
621 | sizeof(struct drm_clip_rect)); | |
9927a403 DC |
622 | if (ret != 0) { |
623 | ret = -EFAULT; | |
201361a5 | 624 | goto fail_free; |
9927a403 | 625 | } |
201361a5 | 626 | } |
1da177e4 | 627 | |
546b0974 | 628 | mutex_lock(&dev->struct_mutex); |
201361a5 | 629 | ret = i915_dispatch_batchbuffer(dev, batch, cliprects); |
546b0974 | 630 | mutex_unlock(&dev->struct_mutex); |
1da177e4 | 631 | |
c99b058f | 632 | if (sarea_priv) |
0baf823a | 633 | sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv); |
201361a5 EA |
634 | |
635 | fail_free: | |
9a298b2a | 636 | kfree(cliprects); |
201361a5 | 637 | |
1da177e4 LT |
638 | return ret; |
639 | } | |
640 | ||
c153f45f EA |
641 | static int i915_cmdbuffer(struct drm_device *dev, void *data, |
642 | struct drm_file *file_priv) | |
1da177e4 | 643 | { |
1da177e4 | 644 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
7c1c2871 | 645 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
1da177e4 | 646 | drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *) |
7c1c2871 | 647 | master_priv->sarea_priv; |
c153f45f | 648 | drm_i915_cmdbuffer_t *cmdbuf = data; |
201361a5 EA |
649 | struct drm_clip_rect *cliprects = NULL; |
650 | void *batch_data; | |
1da177e4 LT |
651 | int ret; |
652 | ||
8a4c47f3 | 653 | DRM_DEBUG_DRIVER("i915 cmdbuffer, buf %p sz %d cliprects %d\n", |
be25ed9c | 654 | cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects); |
1da177e4 | 655 | |
546b0974 | 656 | RING_LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 | 657 | |
201361a5 EA |
658 | if (cmdbuf->num_cliprects < 0) |
659 | return -EINVAL; | |
660 | ||
9a298b2a | 661 | batch_data = kmalloc(cmdbuf->sz, GFP_KERNEL); |
201361a5 EA |
662 | if (batch_data == NULL) |
663 | return -ENOMEM; | |
664 | ||
665 | ret = copy_from_user(batch_data, cmdbuf->buf, cmdbuf->sz); | |
9927a403 DC |
666 | if (ret != 0) { |
667 | ret = -EFAULT; | |
201361a5 | 668 | goto fail_batch_free; |
9927a403 | 669 | } |
201361a5 EA |
670 | |
671 | if (cmdbuf->num_cliprects) { | |
9a298b2a EA |
672 | cliprects = kcalloc(cmdbuf->num_cliprects, |
673 | sizeof(struct drm_clip_rect), GFP_KERNEL); | |
a40e8d31 OA |
674 | if (cliprects == NULL) { |
675 | ret = -ENOMEM; | |
201361a5 | 676 | goto fail_batch_free; |
a40e8d31 | 677 | } |
201361a5 EA |
678 | |
679 | ret = copy_from_user(cliprects, cmdbuf->cliprects, | |
680 | cmdbuf->num_cliprects * | |
681 | sizeof(struct drm_clip_rect)); | |
9927a403 DC |
682 | if (ret != 0) { |
683 | ret = -EFAULT; | |
201361a5 | 684 | goto fail_clip_free; |
9927a403 | 685 | } |
1da177e4 LT |
686 | } |
687 | ||
546b0974 | 688 | mutex_lock(&dev->struct_mutex); |
201361a5 | 689 | ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data); |
546b0974 | 690 | mutex_unlock(&dev->struct_mutex); |
1da177e4 LT |
691 | if (ret) { |
692 | DRM_ERROR("i915_dispatch_cmdbuffer failed\n"); | |
355d7f37 | 693 | goto fail_clip_free; |
1da177e4 LT |
694 | } |
695 | ||
c99b058f | 696 | if (sarea_priv) |
0baf823a | 697 | sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv); |
201361a5 | 698 | |
201361a5 | 699 | fail_clip_free: |
9a298b2a | 700 | kfree(cliprects); |
355d7f37 | 701 | fail_batch_free: |
9a298b2a | 702 | kfree(batch_data); |
201361a5 EA |
703 | |
704 | return ret; | |
1da177e4 LT |
705 | } |
706 | ||
c153f45f EA |
707 | static int i915_flip_bufs(struct drm_device *dev, void *data, |
708 | struct drm_file *file_priv) | |
1da177e4 | 709 | { |
546b0974 EA |
710 | int ret; |
711 | ||
8a4c47f3 | 712 | DRM_DEBUG_DRIVER("%s\n", __func__); |
1da177e4 | 713 | |
546b0974 | 714 | RING_LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 | 715 | |
546b0974 EA |
716 | mutex_lock(&dev->struct_mutex); |
717 | ret = i915_dispatch_flip(dev); | |
718 | mutex_unlock(&dev->struct_mutex); | |
719 | ||
720 | return ret; | |
1da177e4 LT |
721 | } |
722 | ||
c153f45f EA |
723 | static int i915_getparam(struct drm_device *dev, void *data, |
724 | struct drm_file *file_priv) | |
1da177e4 | 725 | { |
1da177e4 | 726 | drm_i915_private_t *dev_priv = dev->dev_private; |
c153f45f | 727 | drm_i915_getparam_t *param = data; |
1da177e4 LT |
728 | int value; |
729 | ||
730 | if (!dev_priv) { | |
3e684eae | 731 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 732 | return -EINVAL; |
1da177e4 LT |
733 | } |
734 | ||
c153f45f | 735 | switch (param->param) { |
1da177e4 | 736 | case I915_PARAM_IRQ_ACTIVE: |
0a3e67a4 | 737 | value = dev->pdev->irq ? 1 : 0; |
1da177e4 LT |
738 | break; |
739 | case I915_PARAM_ALLOW_BATCHBUFFER: | |
740 | value = dev_priv->allow_batchbuffer ? 1 : 0; | |
741 | break; | |
0d6aa60b DA |
742 | case I915_PARAM_LAST_DISPATCH: |
743 | value = READ_BREADCRUMB(dev_priv); | |
744 | break; | |
ed4c9c4a KH |
745 | case I915_PARAM_CHIPSET_ID: |
746 | value = dev->pci_device; | |
747 | break; | |
673a394b | 748 | case I915_PARAM_HAS_GEM: |
ac5c4e76 | 749 | value = dev_priv->has_gem; |
673a394b | 750 | break; |
0f973f27 JB |
751 | case I915_PARAM_NUM_FENCES_AVAIL: |
752 | value = dev_priv->num_fence_regs - dev_priv->fence_reg_start; | |
753 | break; | |
02e792fb DV |
754 | case I915_PARAM_HAS_OVERLAY: |
755 | value = dev_priv->overlay ? 1 : 0; | |
756 | break; | |
e9560f7c JB |
757 | case I915_PARAM_HAS_PAGEFLIPPING: |
758 | value = 1; | |
759 | break; | |
76446cac JB |
760 | case I915_PARAM_HAS_EXECBUF2: |
761 | /* depends on GEM */ | |
762 | value = dev_priv->has_gem; | |
763 | break; | |
e3a815fc ZN |
764 | case I915_PARAM_HAS_BSD: |
765 | value = HAS_BSD(dev); | |
766 | break; | |
1da177e4 | 767 | default: |
8a4c47f3 | 768 | DRM_DEBUG_DRIVER("Unknown parameter %d\n", |
76446cac | 769 | param->param); |
20caafa6 | 770 | return -EINVAL; |
1da177e4 LT |
771 | } |
772 | ||
c153f45f | 773 | if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) { |
1da177e4 | 774 | DRM_ERROR("DRM_COPY_TO_USER failed\n"); |
20caafa6 | 775 | return -EFAULT; |
1da177e4 LT |
776 | } |
777 | ||
778 | return 0; | |
779 | } | |
780 | ||
c153f45f EA |
781 | static int i915_setparam(struct drm_device *dev, void *data, |
782 | struct drm_file *file_priv) | |
1da177e4 | 783 | { |
1da177e4 | 784 | drm_i915_private_t *dev_priv = dev->dev_private; |
c153f45f | 785 | drm_i915_setparam_t *param = data; |
1da177e4 LT |
786 | |
787 | if (!dev_priv) { | |
3e684eae | 788 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 789 | return -EINVAL; |
1da177e4 LT |
790 | } |
791 | ||
c153f45f | 792 | switch (param->param) { |
1da177e4 | 793 | case I915_SETPARAM_USE_MI_BATCHBUFFER_START: |
1da177e4 LT |
794 | break; |
795 | case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY: | |
c153f45f | 796 | dev_priv->tex_lru_log_granularity = param->value; |
1da177e4 LT |
797 | break; |
798 | case I915_SETPARAM_ALLOW_BATCHBUFFER: | |
c153f45f | 799 | dev_priv->allow_batchbuffer = param->value; |
1da177e4 | 800 | break; |
0f973f27 JB |
801 | case I915_SETPARAM_NUM_USED_FENCES: |
802 | if (param->value > dev_priv->num_fence_regs || | |
803 | param->value < 0) | |
804 | return -EINVAL; | |
805 | /* Userspace can use first N regs */ | |
806 | dev_priv->fence_reg_start = param->value; | |
807 | break; | |
1da177e4 | 808 | default: |
8a4c47f3 | 809 | DRM_DEBUG_DRIVER("unknown parameter %d\n", |
be25ed9c | 810 | param->param); |
20caafa6 | 811 | return -EINVAL; |
1da177e4 LT |
812 | } |
813 | ||
814 | return 0; | |
815 | } | |
816 | ||
c153f45f EA |
817 | static int i915_set_status_page(struct drm_device *dev, void *data, |
818 | struct drm_file *file_priv) | |
dc7a9319 | 819 | { |
dc7a9319 | 820 | drm_i915_private_t *dev_priv = dev->dev_private; |
c153f45f | 821 | drm_i915_hws_addr_t *hws = data; |
8187a2b7 | 822 | struct intel_ring_buffer *ring = &dev_priv->render_ring; |
b39d50e5 ZW |
823 | |
824 | if (!I915_NEED_GFX_HWS(dev)) | |
825 | return -EINVAL; | |
dc7a9319 WZ |
826 | |
827 | if (!dev_priv) { | |
3e684eae | 828 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 829 | return -EINVAL; |
dc7a9319 | 830 | } |
dc7a9319 | 831 | |
79e53945 JB |
832 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
833 | WARN(1, "tried to set status page when mode setting active\n"); | |
834 | return 0; | |
835 | } | |
836 | ||
8a4c47f3 | 837 | DRM_DEBUG_DRIVER("set status page addr 0x%08x\n", (u32)hws->addr); |
c153f45f | 838 | |
8187a2b7 | 839 | ring->status_page.gfx_addr = hws->addr & (0x1ffff<<12); |
dc7a9319 | 840 | |
8b409580 | 841 | dev_priv->hws_map.offset = dev->agp->base + hws->addr; |
dc7a9319 WZ |
842 | dev_priv->hws_map.size = 4*1024; |
843 | dev_priv->hws_map.type = 0; | |
844 | dev_priv->hws_map.flags = 0; | |
845 | dev_priv->hws_map.mtrr = 0; | |
846 | ||
dd0910b3 | 847 | drm_core_ioremap_wc(&dev_priv->hws_map, dev); |
dc7a9319 | 848 | if (dev_priv->hws_map.handle == NULL) { |
dc7a9319 | 849 | i915_dma_cleanup(dev); |
e20f9c64 | 850 | ring->status_page.gfx_addr = 0; |
dc7a9319 WZ |
851 | DRM_ERROR("can not ioremap virtual address for" |
852 | " G33 hw status page\n"); | |
20caafa6 | 853 | return -ENOMEM; |
dc7a9319 | 854 | } |
8187a2b7 ZN |
855 | ring->status_page.page_addr = dev_priv->hws_map.handle; |
856 | memset(ring->status_page.page_addr, 0, PAGE_SIZE); | |
857 | I915_WRITE(HWS_PGA, ring->status_page.gfx_addr); | |
dc7a9319 | 858 | |
8a4c47f3 | 859 | DRM_DEBUG_DRIVER("load hws HWS_PGA with gfx mem 0x%x\n", |
e20f9c64 | 860 | ring->status_page.gfx_addr); |
8a4c47f3 | 861 | DRM_DEBUG_DRIVER("load hws at %p\n", |
e20f9c64 | 862 | ring->status_page.page_addr); |
dc7a9319 WZ |
863 | return 0; |
864 | } | |
865 | ||
ec2a4c3f DA |
866 | static int i915_get_bridge_dev(struct drm_device *dev) |
867 | { | |
868 | struct drm_i915_private *dev_priv = dev->dev_private; | |
869 | ||
870 | dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0,0)); | |
871 | if (!dev_priv->bridge_dev) { | |
872 | DRM_ERROR("bridge device not found\n"); | |
873 | return -1; | |
874 | } | |
875 | return 0; | |
876 | } | |
877 | ||
c4804411 ZW |
878 | #define MCHBAR_I915 0x44 |
879 | #define MCHBAR_I965 0x48 | |
880 | #define MCHBAR_SIZE (4*4096) | |
881 | ||
882 | #define DEVEN_REG 0x54 | |
883 | #define DEVEN_MCHBAR_EN (1 << 28) | |
884 | ||
885 | /* Allocate space for the MCH regs if needed, return nonzero on error */ | |
886 | static int | |
887 | intel_alloc_mchbar_resource(struct drm_device *dev) | |
888 | { | |
889 | drm_i915_private_t *dev_priv = dev->dev_private; | |
a6c45cf0 | 890 | int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915; |
c4804411 ZW |
891 | u32 temp_lo, temp_hi = 0; |
892 | u64 mchbar_addr; | |
a25c25c2 | 893 | int ret; |
c4804411 | 894 | |
a6c45cf0 | 895 | if (INTEL_INFO(dev)->gen >= 4) |
c4804411 ZW |
896 | pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi); |
897 | pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo); | |
898 | mchbar_addr = ((u64)temp_hi << 32) | temp_lo; | |
899 | ||
900 | /* If ACPI doesn't have it, assume we need to allocate it ourselves */ | |
901 | #ifdef CONFIG_PNP | |
902 | if (mchbar_addr && | |
a25c25c2 CW |
903 | pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE)) |
904 | return 0; | |
c4804411 ZW |
905 | #endif |
906 | ||
907 | /* Get some space for it */ | |
a25c25c2 CW |
908 | dev_priv->mch_res.name = "i915 MCHBAR"; |
909 | dev_priv->mch_res.flags = IORESOURCE_MEM; | |
910 | ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus, | |
911 | &dev_priv->mch_res, | |
c4804411 ZW |
912 | MCHBAR_SIZE, MCHBAR_SIZE, |
913 | PCIBIOS_MIN_MEM, | |
a25c25c2 | 914 | 0, pcibios_align_resource, |
c4804411 ZW |
915 | dev_priv->bridge_dev); |
916 | if (ret) { | |
917 | DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret); | |
918 | dev_priv->mch_res.start = 0; | |
a25c25c2 | 919 | return ret; |
c4804411 ZW |
920 | } |
921 | ||
a6c45cf0 | 922 | if (INTEL_INFO(dev)->gen >= 4) |
c4804411 ZW |
923 | pci_write_config_dword(dev_priv->bridge_dev, reg + 4, |
924 | upper_32_bits(dev_priv->mch_res.start)); | |
925 | ||
926 | pci_write_config_dword(dev_priv->bridge_dev, reg, | |
927 | lower_32_bits(dev_priv->mch_res.start)); | |
a25c25c2 | 928 | return 0; |
c4804411 ZW |
929 | } |
930 | ||
931 | /* Setup MCHBAR if possible, return true if we should disable it again */ | |
932 | static void | |
933 | intel_setup_mchbar(struct drm_device *dev) | |
934 | { | |
935 | drm_i915_private_t *dev_priv = dev->dev_private; | |
a6c45cf0 | 936 | int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915; |
c4804411 ZW |
937 | u32 temp; |
938 | bool enabled; | |
939 | ||
940 | dev_priv->mchbar_need_disable = false; | |
941 | ||
942 | if (IS_I915G(dev) || IS_I915GM(dev)) { | |
943 | pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp); | |
944 | enabled = !!(temp & DEVEN_MCHBAR_EN); | |
945 | } else { | |
946 | pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); | |
947 | enabled = temp & 1; | |
948 | } | |
949 | ||
950 | /* If it's already enabled, don't have to do anything */ | |
951 | if (enabled) | |
952 | return; | |
953 | ||
954 | if (intel_alloc_mchbar_resource(dev)) | |
955 | return; | |
956 | ||
957 | dev_priv->mchbar_need_disable = true; | |
958 | ||
959 | /* Space is allocated or reserved, so enable it. */ | |
960 | if (IS_I915G(dev) || IS_I915GM(dev)) { | |
961 | pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, | |
962 | temp | DEVEN_MCHBAR_EN); | |
963 | } else { | |
964 | pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); | |
965 | pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1); | |
966 | } | |
967 | } | |
968 | ||
969 | static void | |
970 | intel_teardown_mchbar(struct drm_device *dev) | |
971 | { | |
972 | drm_i915_private_t *dev_priv = dev->dev_private; | |
a6c45cf0 | 973 | int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915; |
c4804411 ZW |
974 | u32 temp; |
975 | ||
976 | if (dev_priv->mchbar_need_disable) { | |
977 | if (IS_I915G(dev) || IS_I915GM(dev)) { | |
978 | pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp); | |
979 | temp &= ~DEVEN_MCHBAR_EN; | |
980 | pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp); | |
981 | } else { | |
982 | pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); | |
983 | temp &= ~1; | |
984 | pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp); | |
985 | } | |
986 | } | |
987 | ||
988 | if (dev_priv->mch_res.start) | |
989 | release_resource(&dev_priv->mch_res); | |
990 | } | |
991 | ||
80824003 JB |
992 | #define PTE_ADDRESS_MASK 0xfffff000 |
993 | #define PTE_ADDRESS_MASK_HIGH 0x000000f0 /* i915+ */ | |
994 | #define PTE_MAPPING_TYPE_UNCACHED (0 << 1) | |
995 | #define PTE_MAPPING_TYPE_DCACHE (1 << 1) /* i830 only */ | |
996 | #define PTE_MAPPING_TYPE_CACHED (3 << 1) | |
997 | #define PTE_MAPPING_TYPE_MASK (3 << 1) | |
998 | #define PTE_VALID (1 << 0) | |
999 | ||
1000 | /** | |
1001 | * i915_gtt_to_phys - take a GTT address and turn it into a physical one | |
1002 | * @dev: drm device | |
1003 | * @gtt_addr: address to translate | |
1004 | * | |
1005 | * Some chip functions require allocations from stolen space but need the | |
1006 | * physical address of the memory in question. We use this routine | |
1007 | * to get a physical address suitable for register programming from a given | |
1008 | * GTT address. | |
1009 | */ | |
1010 | static unsigned long i915_gtt_to_phys(struct drm_device *dev, | |
1011 | unsigned long gtt_addr) | |
1012 | { | |
1013 | unsigned long *gtt; | |
1014 | unsigned long entry, phys; | |
a6c45cf0 | 1015 | int gtt_bar = IS_GEN2(dev) ? 1 : 0; |
80824003 JB |
1016 | int gtt_offset, gtt_size; |
1017 | ||
a6c45cf0 CW |
1018 | if (INTEL_INFO(dev)->gen >= 4) { |
1019 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen > 4) { | |
80824003 JB |
1020 | gtt_offset = 2*1024*1024; |
1021 | gtt_size = 2*1024*1024; | |
1022 | } else { | |
1023 | gtt_offset = 512*1024; | |
1024 | gtt_size = 512*1024; | |
1025 | } | |
1026 | } else { | |
1027 | gtt_bar = 3; | |
1028 | gtt_offset = 0; | |
1029 | gtt_size = pci_resource_len(dev->pdev, gtt_bar); | |
1030 | } | |
1031 | ||
1032 | gtt = ioremap_wc(pci_resource_start(dev->pdev, gtt_bar) + gtt_offset, | |
1033 | gtt_size); | |
1034 | if (!gtt) { | |
1035 | DRM_ERROR("ioremap of GTT failed\n"); | |
1036 | return 0; | |
1037 | } | |
1038 | ||
1039 | entry = *(volatile u32 *)(gtt + (gtt_addr / 1024)); | |
1040 | ||
44d98a61 | 1041 | DRM_DEBUG_DRIVER("GTT addr: 0x%08lx, PTE: 0x%08lx\n", gtt_addr, entry); |
80824003 JB |
1042 | |
1043 | /* Mask out these reserved bits on this hardware. */ | |
a6c45cf0 | 1044 | if (INTEL_INFO(dev)->gen < 4 && !IS_G33(dev)) |
80824003 | 1045 | entry &= ~PTE_ADDRESS_MASK_HIGH; |
80824003 JB |
1046 | |
1047 | /* If it's not a mapping type we know, then bail. */ | |
1048 | if ((entry & PTE_MAPPING_TYPE_MASK) != PTE_MAPPING_TYPE_UNCACHED && | |
1049 | (entry & PTE_MAPPING_TYPE_MASK) != PTE_MAPPING_TYPE_CACHED) { | |
1050 | iounmap(gtt); | |
1051 | return 0; | |
1052 | } | |
1053 | ||
1054 | if (!(entry & PTE_VALID)) { | |
1055 | DRM_ERROR("bad GTT entry in stolen space\n"); | |
1056 | iounmap(gtt); | |
1057 | return 0; | |
1058 | } | |
1059 | ||
1060 | iounmap(gtt); | |
1061 | ||
1062 | phys =(entry & PTE_ADDRESS_MASK) | | |
1063 | ((uint64_t)(entry & PTE_ADDRESS_MASK_HIGH) << (32 - 4)); | |
1064 | ||
44d98a61 | 1065 | DRM_DEBUG_DRIVER("GTT addr: 0x%08lx, phys addr: 0x%08lx\n", gtt_addr, phys); |
80824003 JB |
1066 | |
1067 | return phys; | |
1068 | } | |
1069 | ||
1070 | static void i915_warn_stolen(struct drm_device *dev) | |
1071 | { | |
1072 | DRM_ERROR("not enough stolen space for compressed buffer, disabling\n"); | |
1073 | DRM_ERROR("hint: you may be able to increase stolen memory size in the BIOS to avoid this\n"); | |
1074 | } | |
1075 | ||
1076 | static void i915_setup_compression(struct drm_device *dev, int size) | |
1077 | { | |
1078 | struct drm_i915_private *dev_priv = dev->dev_private; | |
132b6aab | 1079 | struct drm_mm_node *compressed_fb, *uninitialized_var(compressed_llb); |
29bd0ae2 AM |
1080 | unsigned long cfb_base; |
1081 | unsigned long ll_base = 0; | |
80824003 JB |
1082 | |
1083 | /* Leave 1M for line length buffer & misc. */ | |
19966754 | 1084 | compressed_fb = drm_mm_search_free(&dev_priv->mm.vram, size, 4096, 0); |
80824003 | 1085 | if (!compressed_fb) { |
b5e50c3f | 1086 | dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL; |
80824003 JB |
1087 | i915_warn_stolen(dev); |
1088 | return; | |
1089 | } | |
1090 | ||
1091 | compressed_fb = drm_mm_get_block(compressed_fb, size, 4096); | |
1092 | if (!compressed_fb) { | |
1093 | i915_warn_stolen(dev); | |
b5e50c3f | 1094 | dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL; |
80824003 JB |
1095 | return; |
1096 | } | |
1097 | ||
74dff282 JB |
1098 | cfb_base = i915_gtt_to_phys(dev, compressed_fb->start); |
1099 | if (!cfb_base) { | |
1100 | DRM_ERROR("failed to get stolen phys addr, disabling FBC\n"); | |
1101 | drm_mm_put_block(compressed_fb); | |
80824003 JB |
1102 | } |
1103 | ||
b52eb4dc | 1104 | if (!(IS_GM45(dev) || IS_IRONLAKE_M(dev))) { |
19966754 | 1105 | compressed_llb = drm_mm_search_free(&dev_priv->mm.vram, 4096, |
74dff282 JB |
1106 | 4096, 0); |
1107 | if (!compressed_llb) { | |
1108 | i915_warn_stolen(dev); | |
1109 | return; | |
1110 | } | |
1111 | ||
1112 | compressed_llb = drm_mm_get_block(compressed_llb, 4096, 4096); | |
1113 | if (!compressed_llb) { | |
1114 | i915_warn_stolen(dev); | |
1115 | return; | |
1116 | } | |
1117 | ||
1118 | ll_base = i915_gtt_to_phys(dev, compressed_llb->start); | |
1119 | if (!ll_base) { | |
1120 | DRM_ERROR("failed to get stolen phys addr, disabling FBC\n"); | |
1121 | drm_mm_put_block(compressed_fb); | |
1122 | drm_mm_put_block(compressed_llb); | |
1123 | } | |
80824003 JB |
1124 | } |
1125 | ||
1126 | dev_priv->cfb_size = size; | |
1127 | ||
ee5382ae | 1128 | intel_disable_fbc(dev); |
20bf377e | 1129 | dev_priv->compressed_fb = compressed_fb; |
b52eb4dc ZY |
1130 | if (IS_IRONLAKE_M(dev)) |
1131 | I915_WRITE(ILK_DPFC_CB_BASE, compressed_fb->start); | |
1132 | else if (IS_GM45(dev)) { | |
74dff282 JB |
1133 | I915_WRITE(DPFC_CB_BASE, compressed_fb->start); |
1134 | } else { | |
74dff282 JB |
1135 | I915_WRITE(FBC_CFB_BASE, cfb_base); |
1136 | I915_WRITE(FBC_LL_BASE, ll_base); | |
20bf377e | 1137 | dev_priv->compressed_llb = compressed_llb; |
80824003 JB |
1138 | } |
1139 | ||
b52eb4dc | 1140 | DRM_DEBUG_KMS("FBC base 0x%08lx, ll base 0x%08lx, size %dM\n", cfb_base, |
80824003 | 1141 | ll_base, size >> 20); |
80824003 JB |
1142 | } |
1143 | ||
20bf377e JB |
1144 | static void i915_cleanup_compression(struct drm_device *dev) |
1145 | { | |
1146 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1147 | ||
1148 | drm_mm_put_block(dev_priv->compressed_fb); | |
aebf0daf | 1149 | if (dev_priv->compressed_llb) |
20bf377e JB |
1150 | drm_mm_put_block(dev_priv->compressed_llb); |
1151 | } | |
1152 | ||
28d52043 DA |
1153 | /* true = enable decode, false = disable decoder */ |
1154 | static unsigned int i915_vga_set_decode(void *cookie, bool state) | |
1155 | { | |
1156 | struct drm_device *dev = cookie; | |
1157 | ||
1158 | intel_modeset_vga_set_state(dev, state); | |
1159 | if (state) | |
1160 | return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | | |
1161 | VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
1162 | else | |
1163 | return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
1164 | } | |
1165 | ||
6a9ee8af DA |
1166 | static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state) |
1167 | { | |
1168 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1169 | pm_message_t pmm = { .event = PM_EVENT_SUSPEND }; | |
1170 | if (state == VGA_SWITCHEROO_ON) { | |
fbf81762 | 1171 | printk(KERN_INFO "i915: switched on\n"); |
6a9ee8af DA |
1172 | /* i915 resume handler doesn't set to D0 */ |
1173 | pci_set_power_state(dev->pdev, PCI_D0); | |
1174 | i915_resume(dev); | |
1175 | } else { | |
1176 | printk(KERN_ERR "i915: switched off\n"); | |
1177 | i915_suspend(dev, pmm); | |
1178 | } | |
1179 | } | |
1180 | ||
1181 | static bool i915_switcheroo_can_switch(struct pci_dev *pdev) | |
1182 | { | |
1183 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1184 | bool can_switch; | |
1185 | ||
1186 | spin_lock(&dev->count_lock); | |
1187 | can_switch = (dev->open_count == 0); | |
1188 | spin_unlock(&dev->count_lock); | |
1189 | return can_switch; | |
1190 | } | |
1191 | ||
2a34f5e6 EA |
1192 | static int i915_load_modeset_init(struct drm_device *dev, |
1193 | unsigned long prealloc_size, | |
1194 | unsigned long agp_size) | |
79e53945 JB |
1195 | { |
1196 | struct drm_i915_private *dev_priv = dev->dev_private; | |
79e53945 JB |
1197 | int ret = 0; |
1198 | ||
19966754 DV |
1199 | /* Basic memrange allocator for stolen space (aka mm.vram) */ |
1200 | drm_mm_init(&dev_priv->mm.vram, 0, prealloc_size); | |
79e53945 | 1201 | |
11ed50ec BG |
1202 | /* We're off and running w/KMS */ |
1203 | dev_priv->mm.suspended = 0; | |
79e53945 | 1204 | |
13f4c435 EA |
1205 | /* Let GEM Manage from end of prealloc space to end of aperture. |
1206 | * | |
1207 | * However, leave one page at the end still bound to the scratch page. | |
1208 | * There are a number of places where the hardware apparently | |
1209 | * prefetches past the end of the object, and we've seen multiple | |
1210 | * hangs with the GPU head pointer stuck in a batchbuffer bound | |
1211 | * at the last page of the aperture. One page should be enough to | |
1212 | * keep any prefetching inside of the aperture. | |
1213 | */ | |
1214 | i915_gem_do_init(dev, prealloc_size, agp_size - 4096); | |
79e53945 | 1215 | |
11ed50ec | 1216 | mutex_lock(&dev->struct_mutex); |
79e53945 | 1217 | ret = i915_gem_init_ringbuffer(dev); |
11ed50ec | 1218 | mutex_unlock(&dev->struct_mutex); |
79e53945 | 1219 | if (ret) |
b8da7de5 | 1220 | goto out; |
79e53945 | 1221 | |
80824003 | 1222 | /* Try to set up FBC with a reasonable compressed buffer size */ |
9216d44d | 1223 | if (I915_HAS_FBC(dev) && i915_powersave) { |
80824003 JB |
1224 | int cfb_size; |
1225 | ||
1226 | /* Try to get an 8M buffer... */ | |
1227 | if (prealloc_size > (9*1024*1024)) | |
1228 | cfb_size = 8*1024*1024; | |
1229 | else /* fall back to 7/8 of the stolen space */ | |
1230 | cfb_size = prealloc_size * 7 / 8; | |
1231 | i915_setup_compression(dev, cfb_size); | |
1232 | } | |
1233 | ||
79e53945 JB |
1234 | /* Allow hardware batchbuffers unless told otherwise. |
1235 | */ | |
1236 | dev_priv->allow_batchbuffer = 1; | |
1237 | ||
1238 | ret = intel_init_bios(dev); | |
1239 | if (ret) | |
1240 | DRM_INFO("failed to find VBIOS tables\n"); | |
1241 | ||
28d52043 DA |
1242 | /* if we have > 1 VGA cards, then disable the radeon VGA resources */ |
1243 | ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode); | |
1244 | if (ret) | |
5a79395b | 1245 | goto cleanup_ringbuffer; |
28d52043 | 1246 | |
6a9ee8af DA |
1247 | ret = vga_switcheroo_register_client(dev->pdev, |
1248 | i915_switcheroo_set_state, | |
1249 | i915_switcheroo_can_switch); | |
1250 | if (ret) | |
5a79395b | 1251 | goto cleanup_vga_client; |
6a9ee8af | 1252 | |
1afe3e9d JB |
1253 | /* IIR "flip pending" bit means done if this bit is set */ |
1254 | if (IS_GEN3(dev) && (I915_READ(ECOSKPD) & ECO_FLIP_DONE)) | |
1255 | dev_priv->flip_pending_is_done = true; | |
1256 | ||
b01f2c3a JB |
1257 | intel_modeset_init(dev); |
1258 | ||
79e53945 JB |
1259 | ret = drm_irq_install(dev); |
1260 | if (ret) | |
5a79395b | 1261 | goto cleanup_vga_switcheroo; |
79e53945 | 1262 | |
79e53945 JB |
1263 | /* Always safe in the mode setting case. */ |
1264 | /* FIXME: do pre/post-mode set stuff in core KMS code */ | |
1265 | dev->vblank_disable_allowed = 1; | |
1266 | ||
5a79395b CW |
1267 | ret = intel_fbdev_init(dev); |
1268 | if (ret) | |
1269 | goto cleanup_irq; | |
1270 | ||
eb1f8e4f | 1271 | drm_kms_helper_poll_init(dev); |
79e53945 JB |
1272 | return 0; |
1273 | ||
5a79395b CW |
1274 | cleanup_irq: |
1275 | drm_irq_uninstall(dev); | |
1276 | cleanup_vga_switcheroo: | |
1277 | vga_switcheroo_unregister_client(dev->pdev); | |
1278 | cleanup_vga_client: | |
1279 | vga_client_register(dev->pdev, NULL, NULL, NULL); | |
1280 | cleanup_ringbuffer: | |
21099537 | 1281 | mutex_lock(&dev->struct_mutex); |
79e53945 | 1282 | i915_gem_cleanup_ringbuffer(dev); |
21099537 | 1283 | mutex_unlock(&dev->struct_mutex); |
79e53945 JB |
1284 | out: |
1285 | return ret; | |
1286 | } | |
1287 | ||
7c1c2871 DA |
1288 | int i915_master_create(struct drm_device *dev, struct drm_master *master) |
1289 | { | |
1290 | struct drm_i915_master_private *master_priv; | |
1291 | ||
9a298b2a | 1292 | master_priv = kzalloc(sizeof(*master_priv), GFP_KERNEL); |
7c1c2871 DA |
1293 | if (!master_priv) |
1294 | return -ENOMEM; | |
1295 | ||
1296 | master->driver_priv = master_priv; | |
1297 | return 0; | |
1298 | } | |
1299 | ||
1300 | void i915_master_destroy(struct drm_device *dev, struct drm_master *master) | |
1301 | { | |
1302 | struct drm_i915_master_private *master_priv = master->driver_priv; | |
1303 | ||
1304 | if (!master_priv) | |
1305 | return; | |
1306 | ||
9a298b2a | 1307 | kfree(master_priv); |
7c1c2871 DA |
1308 | |
1309 | master->driver_priv = NULL; | |
1310 | } | |
1311 | ||
7648fa99 | 1312 | static void i915_pineview_get_mem_freq(struct drm_device *dev) |
7662c8bd SL |
1313 | { |
1314 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1315 | u32 tmp; | |
1316 | ||
7662c8bd SL |
1317 | tmp = I915_READ(CLKCFG); |
1318 | ||
1319 | switch (tmp & CLKCFG_FSB_MASK) { | |
1320 | case CLKCFG_FSB_533: | |
1321 | dev_priv->fsb_freq = 533; /* 133*4 */ | |
1322 | break; | |
1323 | case CLKCFG_FSB_800: | |
1324 | dev_priv->fsb_freq = 800; /* 200*4 */ | |
1325 | break; | |
1326 | case CLKCFG_FSB_667: | |
1327 | dev_priv->fsb_freq = 667; /* 167*4 */ | |
1328 | break; | |
1329 | case CLKCFG_FSB_400: | |
1330 | dev_priv->fsb_freq = 400; /* 100*4 */ | |
1331 | break; | |
1332 | } | |
1333 | ||
1334 | switch (tmp & CLKCFG_MEM_MASK) { | |
1335 | case CLKCFG_MEM_533: | |
1336 | dev_priv->mem_freq = 533; | |
1337 | break; | |
1338 | case CLKCFG_MEM_667: | |
1339 | dev_priv->mem_freq = 667; | |
1340 | break; | |
1341 | case CLKCFG_MEM_800: | |
1342 | dev_priv->mem_freq = 800; | |
1343 | break; | |
1344 | } | |
95534263 LP |
1345 | |
1346 | /* detect pineview DDR3 setting */ | |
1347 | tmp = I915_READ(CSHRDDR3CTL); | |
1348 | dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0; | |
7662c8bd SL |
1349 | } |
1350 | ||
7648fa99 JB |
1351 | static void i915_ironlake_get_mem_freq(struct drm_device *dev) |
1352 | { | |
1353 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1354 | u16 ddrpll, csipll; | |
1355 | ||
1356 | ddrpll = I915_READ16(DDRMPLL1); | |
1357 | csipll = I915_READ16(CSIPLL0); | |
1358 | ||
1359 | switch (ddrpll & 0xff) { | |
1360 | case 0xc: | |
1361 | dev_priv->mem_freq = 800; | |
1362 | break; | |
1363 | case 0x10: | |
1364 | dev_priv->mem_freq = 1066; | |
1365 | break; | |
1366 | case 0x14: | |
1367 | dev_priv->mem_freq = 1333; | |
1368 | break; | |
1369 | case 0x18: | |
1370 | dev_priv->mem_freq = 1600; | |
1371 | break; | |
1372 | default: | |
1373 | DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n", | |
1374 | ddrpll & 0xff); | |
1375 | dev_priv->mem_freq = 0; | |
1376 | break; | |
1377 | } | |
1378 | ||
1379 | dev_priv->r_t = dev_priv->mem_freq; | |
1380 | ||
1381 | switch (csipll & 0x3ff) { | |
1382 | case 0x00c: | |
1383 | dev_priv->fsb_freq = 3200; | |
1384 | break; | |
1385 | case 0x00e: | |
1386 | dev_priv->fsb_freq = 3733; | |
1387 | break; | |
1388 | case 0x010: | |
1389 | dev_priv->fsb_freq = 4266; | |
1390 | break; | |
1391 | case 0x012: | |
1392 | dev_priv->fsb_freq = 4800; | |
1393 | break; | |
1394 | case 0x014: | |
1395 | dev_priv->fsb_freq = 5333; | |
1396 | break; | |
1397 | case 0x016: | |
1398 | dev_priv->fsb_freq = 5866; | |
1399 | break; | |
1400 | case 0x018: | |
1401 | dev_priv->fsb_freq = 6400; | |
1402 | break; | |
1403 | default: | |
1404 | DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n", | |
1405 | csipll & 0x3ff); | |
1406 | dev_priv->fsb_freq = 0; | |
1407 | break; | |
1408 | } | |
1409 | ||
1410 | if (dev_priv->fsb_freq == 3200) { | |
1411 | dev_priv->c_m = 0; | |
1412 | } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) { | |
1413 | dev_priv->c_m = 1; | |
1414 | } else { | |
1415 | dev_priv->c_m = 2; | |
1416 | } | |
1417 | } | |
1418 | ||
1419 | struct v_table { | |
1420 | u8 vid; | |
1421 | unsigned long vd; /* in .1 mil */ | |
1422 | unsigned long vm; /* in .1 mil */ | |
1423 | u8 pvid; | |
1424 | }; | |
1425 | ||
1426 | static struct v_table v_table[] = { | |
1427 | { 0, 16125, 15000, 0x7f, }, | |
1428 | { 1, 16000, 14875, 0x7e, }, | |
1429 | { 2, 15875, 14750, 0x7d, }, | |
1430 | { 3, 15750, 14625, 0x7c, }, | |
1431 | { 4, 15625, 14500, 0x7b, }, | |
1432 | { 5, 15500, 14375, 0x7a, }, | |
1433 | { 6, 15375, 14250, 0x79, }, | |
1434 | { 7, 15250, 14125, 0x78, }, | |
1435 | { 8, 15125, 14000, 0x77, }, | |
1436 | { 9, 15000, 13875, 0x76, }, | |
1437 | { 10, 14875, 13750, 0x75, }, | |
1438 | { 11, 14750, 13625, 0x74, }, | |
1439 | { 12, 14625, 13500, 0x73, }, | |
1440 | { 13, 14500, 13375, 0x72, }, | |
1441 | { 14, 14375, 13250, 0x71, }, | |
1442 | { 15, 14250, 13125, 0x70, }, | |
1443 | { 16, 14125, 13000, 0x6f, }, | |
1444 | { 17, 14000, 12875, 0x6e, }, | |
1445 | { 18, 13875, 12750, 0x6d, }, | |
1446 | { 19, 13750, 12625, 0x6c, }, | |
1447 | { 20, 13625, 12500, 0x6b, }, | |
1448 | { 21, 13500, 12375, 0x6a, }, | |
1449 | { 22, 13375, 12250, 0x69, }, | |
1450 | { 23, 13250, 12125, 0x68, }, | |
1451 | { 24, 13125, 12000, 0x67, }, | |
1452 | { 25, 13000, 11875, 0x66, }, | |
1453 | { 26, 12875, 11750, 0x65, }, | |
1454 | { 27, 12750, 11625, 0x64, }, | |
1455 | { 28, 12625, 11500, 0x63, }, | |
1456 | { 29, 12500, 11375, 0x62, }, | |
1457 | { 30, 12375, 11250, 0x61, }, | |
1458 | { 31, 12250, 11125, 0x60, }, | |
1459 | { 32, 12125, 11000, 0x5f, }, | |
1460 | { 33, 12000, 10875, 0x5e, }, | |
1461 | { 34, 11875, 10750, 0x5d, }, | |
1462 | { 35, 11750, 10625, 0x5c, }, | |
1463 | { 36, 11625, 10500, 0x5b, }, | |
1464 | { 37, 11500, 10375, 0x5a, }, | |
1465 | { 38, 11375, 10250, 0x59, }, | |
1466 | { 39, 11250, 10125, 0x58, }, | |
1467 | { 40, 11125, 10000, 0x57, }, | |
1468 | { 41, 11000, 9875, 0x56, }, | |
1469 | { 42, 10875, 9750, 0x55, }, | |
1470 | { 43, 10750, 9625, 0x54, }, | |
1471 | { 44, 10625, 9500, 0x53, }, | |
1472 | { 45, 10500, 9375, 0x52, }, | |
1473 | { 46, 10375, 9250, 0x51, }, | |
1474 | { 47, 10250, 9125, 0x50, }, | |
1475 | { 48, 10125, 9000, 0x4f, }, | |
1476 | { 49, 10000, 8875, 0x4e, }, | |
1477 | { 50, 9875, 8750, 0x4d, }, | |
1478 | { 51, 9750, 8625, 0x4c, }, | |
1479 | { 52, 9625, 8500, 0x4b, }, | |
1480 | { 53, 9500, 8375, 0x4a, }, | |
1481 | { 54, 9375, 8250, 0x49, }, | |
1482 | { 55, 9250, 8125, 0x48, }, | |
1483 | { 56, 9125, 8000, 0x47, }, | |
1484 | { 57, 9000, 7875, 0x46, }, | |
1485 | { 58, 8875, 7750, 0x45, }, | |
1486 | { 59, 8750, 7625, 0x44, }, | |
1487 | { 60, 8625, 7500, 0x43, }, | |
1488 | { 61, 8500, 7375, 0x42, }, | |
1489 | { 62, 8375, 7250, 0x41, }, | |
1490 | { 63, 8250, 7125, 0x40, }, | |
1491 | { 64, 8125, 7000, 0x3f, }, | |
1492 | { 65, 8000, 6875, 0x3e, }, | |
1493 | { 66, 7875, 6750, 0x3d, }, | |
1494 | { 67, 7750, 6625, 0x3c, }, | |
1495 | { 68, 7625, 6500, 0x3b, }, | |
1496 | { 69, 7500, 6375, 0x3a, }, | |
1497 | { 70, 7375, 6250, 0x39, }, | |
1498 | { 71, 7250, 6125, 0x38, }, | |
1499 | { 72, 7125, 6000, 0x37, }, | |
1500 | { 73, 7000, 5875, 0x36, }, | |
1501 | { 74, 6875, 5750, 0x35, }, | |
1502 | { 75, 6750, 5625, 0x34, }, | |
1503 | { 76, 6625, 5500, 0x33, }, | |
1504 | { 77, 6500, 5375, 0x32, }, | |
1505 | { 78, 6375, 5250, 0x31, }, | |
1506 | { 79, 6250, 5125, 0x30, }, | |
1507 | { 80, 6125, 5000, 0x2f, }, | |
1508 | { 81, 6000, 4875, 0x2e, }, | |
1509 | { 82, 5875, 4750, 0x2d, }, | |
1510 | { 83, 5750, 4625, 0x2c, }, | |
1511 | { 84, 5625, 4500, 0x2b, }, | |
1512 | { 85, 5500, 4375, 0x2a, }, | |
1513 | { 86, 5375, 4250, 0x29, }, | |
1514 | { 87, 5250, 4125, 0x28, }, | |
1515 | { 88, 5125, 4000, 0x27, }, | |
1516 | { 89, 5000, 3875, 0x26, }, | |
1517 | { 90, 4875, 3750, 0x25, }, | |
1518 | { 91, 4750, 3625, 0x24, }, | |
1519 | { 92, 4625, 3500, 0x23, }, | |
1520 | { 93, 4500, 3375, 0x22, }, | |
1521 | { 94, 4375, 3250, 0x21, }, | |
1522 | { 95, 4250, 3125, 0x20, }, | |
1523 | { 96, 4125, 3000, 0x1f, }, | |
1524 | { 97, 4125, 3000, 0x1e, }, | |
1525 | { 98, 4125, 3000, 0x1d, }, | |
1526 | { 99, 4125, 3000, 0x1c, }, | |
1527 | { 100, 4125, 3000, 0x1b, }, | |
1528 | { 101, 4125, 3000, 0x1a, }, | |
1529 | { 102, 4125, 3000, 0x19, }, | |
1530 | { 103, 4125, 3000, 0x18, }, | |
1531 | { 104, 4125, 3000, 0x17, }, | |
1532 | { 105, 4125, 3000, 0x16, }, | |
1533 | { 106, 4125, 3000, 0x15, }, | |
1534 | { 107, 4125, 3000, 0x14, }, | |
1535 | { 108, 4125, 3000, 0x13, }, | |
1536 | { 109, 4125, 3000, 0x12, }, | |
1537 | { 110, 4125, 3000, 0x11, }, | |
1538 | { 111, 4125, 3000, 0x10, }, | |
1539 | { 112, 4125, 3000, 0x0f, }, | |
1540 | { 113, 4125, 3000, 0x0e, }, | |
1541 | { 114, 4125, 3000, 0x0d, }, | |
1542 | { 115, 4125, 3000, 0x0c, }, | |
1543 | { 116, 4125, 3000, 0x0b, }, | |
1544 | { 117, 4125, 3000, 0x0a, }, | |
1545 | { 118, 4125, 3000, 0x09, }, | |
1546 | { 119, 4125, 3000, 0x08, }, | |
1547 | { 120, 1125, 0, 0x07, }, | |
1548 | { 121, 1000, 0, 0x06, }, | |
1549 | { 122, 875, 0, 0x05, }, | |
1550 | { 123, 750, 0, 0x04, }, | |
1551 | { 124, 625, 0, 0x03, }, | |
1552 | { 125, 500, 0, 0x02, }, | |
1553 | { 126, 375, 0, 0x01, }, | |
1554 | { 127, 0, 0, 0x00, }, | |
1555 | }; | |
1556 | ||
1557 | struct cparams { | |
1558 | int i; | |
1559 | int t; | |
1560 | int m; | |
1561 | int c; | |
1562 | }; | |
1563 | ||
1564 | static struct cparams cparams[] = { | |
1565 | { 1, 1333, 301, 28664 }, | |
1566 | { 1, 1066, 294, 24460 }, | |
1567 | { 1, 800, 294, 25192 }, | |
1568 | { 0, 1333, 276, 27605 }, | |
1569 | { 0, 1066, 276, 27605 }, | |
1570 | { 0, 800, 231, 23784 }, | |
1571 | }; | |
1572 | ||
1573 | unsigned long i915_chipset_val(struct drm_i915_private *dev_priv) | |
1574 | { | |
1575 | u64 total_count, diff, ret; | |
1576 | u32 count1, count2, count3, m = 0, c = 0; | |
1577 | unsigned long now = jiffies_to_msecs(jiffies), diff1; | |
1578 | int i; | |
1579 | ||
1580 | diff1 = now - dev_priv->last_time1; | |
1581 | ||
1582 | count1 = I915_READ(DMIEC); | |
1583 | count2 = I915_READ(DDREC); | |
1584 | count3 = I915_READ(CSIEC); | |
1585 | ||
1586 | total_count = count1 + count2 + count3; | |
1587 | ||
1588 | /* FIXME: handle per-counter overflow */ | |
1589 | if (total_count < dev_priv->last_count1) { | |
1590 | diff = ~0UL - dev_priv->last_count1; | |
1591 | diff += total_count; | |
1592 | } else { | |
1593 | diff = total_count - dev_priv->last_count1; | |
1594 | } | |
1595 | ||
1596 | for (i = 0; i < ARRAY_SIZE(cparams); i++) { | |
1597 | if (cparams[i].i == dev_priv->c_m && | |
1598 | cparams[i].t == dev_priv->r_t) { | |
1599 | m = cparams[i].m; | |
1600 | c = cparams[i].c; | |
1601 | break; | |
1602 | } | |
1603 | } | |
1604 | ||
1605 | div_u64(diff, diff1); | |
1606 | ret = ((m * diff) + c); | |
1607 | div_u64(ret, 10); | |
1608 | ||
1609 | dev_priv->last_count1 = total_count; | |
1610 | dev_priv->last_time1 = now; | |
1611 | ||
1612 | return ret; | |
1613 | } | |
1614 | ||
1615 | unsigned long i915_mch_val(struct drm_i915_private *dev_priv) | |
1616 | { | |
1617 | unsigned long m, x, b; | |
1618 | u32 tsfs; | |
1619 | ||
1620 | tsfs = I915_READ(TSFS); | |
1621 | ||
1622 | m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT); | |
1623 | x = I915_READ8(TR1); | |
1624 | ||
1625 | b = tsfs & TSFS_INTR_MASK; | |
1626 | ||
1627 | return ((m * x) / 127) - b; | |
1628 | } | |
1629 | ||
1630 | static unsigned long pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid) | |
1631 | { | |
1632 | unsigned long val = 0; | |
1633 | int i; | |
1634 | ||
1635 | for (i = 0; i < ARRAY_SIZE(v_table); i++) { | |
1636 | if (v_table[i].pvid == pxvid) { | |
1637 | if (IS_MOBILE(dev_priv->dev)) | |
1638 | val = v_table[i].vm; | |
1639 | else | |
1640 | val = v_table[i].vd; | |
1641 | } | |
1642 | } | |
1643 | ||
1644 | return val; | |
1645 | } | |
1646 | ||
1647 | void i915_update_gfx_val(struct drm_i915_private *dev_priv) | |
1648 | { | |
1649 | struct timespec now, diff1; | |
1650 | u64 diff; | |
1651 | unsigned long diffms; | |
1652 | u32 count; | |
1653 | ||
1654 | getrawmonotonic(&now); | |
1655 | diff1 = timespec_sub(now, dev_priv->last_time2); | |
1656 | ||
1657 | /* Don't divide by 0 */ | |
1658 | diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000; | |
1659 | if (!diffms) | |
1660 | return; | |
1661 | ||
1662 | count = I915_READ(GFXEC); | |
1663 | ||
1664 | if (count < dev_priv->last_count2) { | |
1665 | diff = ~0UL - dev_priv->last_count2; | |
1666 | diff += count; | |
1667 | } else { | |
1668 | diff = count - dev_priv->last_count2; | |
1669 | } | |
1670 | ||
1671 | dev_priv->last_count2 = count; | |
1672 | dev_priv->last_time2 = now; | |
1673 | ||
1674 | /* More magic constants... */ | |
1675 | diff = diff * 1181; | |
1676 | div_u64(diff, diffms * 10); | |
1677 | dev_priv->gfx_power = diff; | |
1678 | } | |
1679 | ||
1680 | unsigned long i915_gfx_val(struct drm_i915_private *dev_priv) | |
1681 | { | |
1682 | unsigned long t, corr, state1, corr2, state2; | |
1683 | u32 pxvid, ext_v; | |
1684 | ||
1685 | pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->cur_delay * 4)); | |
1686 | pxvid = (pxvid >> 24) & 0x7f; | |
1687 | ext_v = pvid_to_extvid(dev_priv, pxvid); | |
1688 | ||
1689 | state1 = ext_v; | |
1690 | ||
1691 | t = i915_mch_val(dev_priv); | |
1692 | ||
1693 | /* Revel in the empirically derived constants */ | |
1694 | ||
1695 | /* Correction factor in 1/100000 units */ | |
1696 | if (t > 80) | |
1697 | corr = ((t * 2349) + 135940); | |
1698 | else if (t >= 50) | |
1699 | corr = ((t * 964) + 29317); | |
1700 | else /* < 50 */ | |
1701 | corr = ((t * 301) + 1004); | |
1702 | ||
1703 | corr = corr * ((150142 * state1) / 10000 - 78642); | |
1704 | corr /= 100000; | |
1705 | corr2 = (corr * dev_priv->corr); | |
1706 | ||
1707 | state2 = (corr2 * state1) / 10000; | |
1708 | state2 /= 100; /* convert to mW */ | |
1709 | ||
1710 | i915_update_gfx_val(dev_priv); | |
1711 | ||
1712 | return dev_priv->gfx_power + state2; | |
1713 | } | |
1714 | ||
1715 | /* Global for IPS driver to get at the current i915 device */ | |
1716 | static struct drm_i915_private *i915_mch_dev; | |
1717 | /* | |
1718 | * Lock protecting IPS related data structures | |
1719 | * - i915_mch_dev | |
1720 | * - dev_priv->max_delay | |
1721 | * - dev_priv->min_delay | |
1722 | * - dev_priv->fmax | |
1723 | * - dev_priv->gpu_busy | |
1724 | */ | |
995b6762 | 1725 | static DEFINE_SPINLOCK(mchdev_lock); |
7648fa99 JB |
1726 | |
1727 | /** | |
1728 | * i915_read_mch_val - return value for IPS use | |
1729 | * | |
1730 | * Calculate and return a value for the IPS driver to use when deciding whether | |
1731 | * we have thermal and power headroom to increase CPU or GPU power budget. | |
1732 | */ | |
1733 | unsigned long i915_read_mch_val(void) | |
1734 | { | |
1735 | struct drm_i915_private *dev_priv; | |
1736 | unsigned long chipset_val, graphics_val, ret = 0; | |
1737 | ||
1738 | spin_lock(&mchdev_lock); | |
1739 | if (!i915_mch_dev) | |
1740 | goto out_unlock; | |
1741 | dev_priv = i915_mch_dev; | |
1742 | ||
1743 | chipset_val = i915_chipset_val(dev_priv); | |
1744 | graphics_val = i915_gfx_val(dev_priv); | |
1745 | ||
1746 | ret = chipset_val + graphics_val; | |
1747 | ||
1748 | out_unlock: | |
1749 | spin_unlock(&mchdev_lock); | |
1750 | ||
1751 | return ret; | |
1752 | } | |
1753 | EXPORT_SYMBOL_GPL(i915_read_mch_val); | |
1754 | ||
1755 | /** | |
1756 | * i915_gpu_raise - raise GPU frequency limit | |
1757 | * | |
1758 | * Raise the limit; IPS indicates we have thermal headroom. | |
1759 | */ | |
1760 | bool i915_gpu_raise(void) | |
1761 | { | |
1762 | struct drm_i915_private *dev_priv; | |
1763 | bool ret = true; | |
1764 | ||
1765 | spin_lock(&mchdev_lock); | |
1766 | if (!i915_mch_dev) { | |
1767 | ret = false; | |
1768 | goto out_unlock; | |
1769 | } | |
1770 | dev_priv = i915_mch_dev; | |
1771 | ||
1772 | if (dev_priv->max_delay > dev_priv->fmax) | |
1773 | dev_priv->max_delay--; | |
1774 | ||
1775 | out_unlock: | |
1776 | spin_unlock(&mchdev_lock); | |
1777 | ||
1778 | return ret; | |
1779 | } | |
1780 | EXPORT_SYMBOL_GPL(i915_gpu_raise); | |
1781 | ||
1782 | /** | |
1783 | * i915_gpu_lower - lower GPU frequency limit | |
1784 | * | |
1785 | * IPS indicates we're close to a thermal limit, so throttle back the GPU | |
1786 | * frequency maximum. | |
1787 | */ | |
1788 | bool i915_gpu_lower(void) | |
1789 | { | |
1790 | struct drm_i915_private *dev_priv; | |
1791 | bool ret = true; | |
1792 | ||
1793 | spin_lock(&mchdev_lock); | |
1794 | if (!i915_mch_dev) { | |
1795 | ret = false; | |
1796 | goto out_unlock; | |
1797 | } | |
1798 | dev_priv = i915_mch_dev; | |
1799 | ||
1800 | if (dev_priv->max_delay < dev_priv->min_delay) | |
1801 | dev_priv->max_delay++; | |
1802 | ||
1803 | out_unlock: | |
1804 | spin_unlock(&mchdev_lock); | |
1805 | ||
1806 | return ret; | |
1807 | } | |
1808 | EXPORT_SYMBOL_GPL(i915_gpu_lower); | |
1809 | ||
1810 | /** | |
1811 | * i915_gpu_busy - indicate GPU business to IPS | |
1812 | * | |
1813 | * Tell the IPS driver whether or not the GPU is busy. | |
1814 | */ | |
1815 | bool i915_gpu_busy(void) | |
1816 | { | |
1817 | struct drm_i915_private *dev_priv; | |
1818 | bool ret = false; | |
1819 | ||
1820 | spin_lock(&mchdev_lock); | |
1821 | if (!i915_mch_dev) | |
1822 | goto out_unlock; | |
1823 | dev_priv = i915_mch_dev; | |
1824 | ||
1825 | ret = dev_priv->busy; | |
1826 | ||
1827 | out_unlock: | |
1828 | spin_unlock(&mchdev_lock); | |
1829 | ||
1830 | return ret; | |
1831 | } | |
1832 | EXPORT_SYMBOL_GPL(i915_gpu_busy); | |
1833 | ||
1834 | /** | |
1835 | * i915_gpu_turbo_disable - disable graphics turbo | |
1836 | * | |
1837 | * Disable graphics turbo by resetting the max frequency and setting the | |
1838 | * current frequency to the default. | |
1839 | */ | |
1840 | bool i915_gpu_turbo_disable(void) | |
1841 | { | |
1842 | struct drm_i915_private *dev_priv; | |
1843 | bool ret = true; | |
1844 | ||
1845 | spin_lock(&mchdev_lock); | |
1846 | if (!i915_mch_dev) { | |
1847 | ret = false; | |
1848 | goto out_unlock; | |
1849 | } | |
1850 | dev_priv = i915_mch_dev; | |
1851 | ||
1852 | dev_priv->max_delay = dev_priv->fstart; | |
1853 | ||
1854 | if (!ironlake_set_drps(dev_priv->dev, dev_priv->fstart)) | |
1855 | ret = false; | |
1856 | ||
1857 | out_unlock: | |
1858 | spin_unlock(&mchdev_lock); | |
1859 | ||
1860 | return ret; | |
1861 | } | |
1862 | EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable); | |
1863 | ||
79e53945 JB |
1864 | /** |
1865 | * i915_driver_load - setup chip and create an initial config | |
1866 | * @dev: DRM device | |
1867 | * @flags: startup flags | |
1868 | * | |
1869 | * The driver load routine has to do several things: | |
1870 | * - drive output discovery via intel_modeset_init() | |
1871 | * - initialize the memory manager | |
1872 | * - allocate initial config memory | |
1873 | * - setup the DRM framebuffer with the allocated memory | |
1874 | */ | |
84b1fd10 | 1875 | int i915_driver_load(struct drm_device *dev, unsigned long flags) |
22eae947 | 1876 | { |
ea059a1e | 1877 | struct drm_i915_private *dev_priv; |
d883f7f1 | 1878 | resource_size_t base, size; |
cfdf1fa2 | 1879 | int ret = 0, mmio_bar; |
ac622a9c | 1880 | uint32_t agp_size, prealloc_size; |
22eae947 DA |
1881 | /* i915 has 4 more counters */ |
1882 | dev->counters += 4; | |
1883 | dev->types[6] = _DRM_STAT_IRQ; | |
1884 | dev->types[7] = _DRM_STAT_PRIMARY; | |
1885 | dev->types[8] = _DRM_STAT_SECONDARY; | |
1886 | dev->types[9] = _DRM_STAT_DMA; | |
1887 | ||
9a298b2a | 1888 | dev_priv = kzalloc(sizeof(drm_i915_private_t), GFP_KERNEL); |
ba8bbcf6 JB |
1889 | if (dev_priv == NULL) |
1890 | return -ENOMEM; | |
1891 | ||
ba8bbcf6 | 1892 | dev->dev_private = (void *)dev_priv; |
673a394b | 1893 | dev_priv->dev = dev; |
cfdf1fa2 | 1894 | dev_priv->info = (struct intel_device_info *) flags; |
ba8bbcf6 JB |
1895 | |
1896 | /* Add register map (needed for suspend/resume) */ | |
a6c45cf0 | 1897 | mmio_bar = IS_GEN2(dev) ? 1 : 0; |
01d73a69 JC |
1898 | base = pci_resource_start(dev->pdev, mmio_bar); |
1899 | size = pci_resource_len(dev->pdev, mmio_bar); | |
ba8bbcf6 | 1900 | |
ec2a4c3f DA |
1901 | if (i915_get_bridge_dev(dev)) { |
1902 | ret = -EIO; | |
1903 | goto free_priv; | |
1904 | } | |
1905 | ||
9f82d238 DV |
1906 | /* overlay on gen2 is broken and can't address above 1G */ |
1907 | if (IS_GEN2(dev)) | |
1908 | dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30)); | |
1909 | ||
3043c60c | 1910 | dev_priv->regs = ioremap(base, size); |
79e53945 JB |
1911 | if (!dev_priv->regs) { |
1912 | DRM_ERROR("failed to map registers\n"); | |
1913 | ret = -EIO; | |
ec2a4c3f | 1914 | goto put_bridge; |
79e53945 | 1915 | } |
ed4cb414 | 1916 | |
ab657db1 EA |
1917 | dev_priv->mm.gtt_mapping = |
1918 | io_mapping_create_wc(dev->agp->base, | |
1919 | dev->agp->agp_info.aper_size * 1024*1024); | |
6644107d VP |
1920 | if (dev_priv->mm.gtt_mapping == NULL) { |
1921 | ret = -EIO; | |
1922 | goto out_rmmap; | |
1923 | } | |
1924 | ||
ab657db1 EA |
1925 | /* Set up a WC MTRR for non-PAT systems. This is more common than |
1926 | * one would think, because the kernel disables PAT on first | |
1927 | * generation Core chips because WC PAT gets overridden by a UC | |
1928 | * MTRR if present. Even if a UC MTRR isn't present. | |
1929 | */ | |
1930 | dev_priv->mm.gtt_mtrr = mtrr_add(dev->agp->base, | |
1931 | dev->agp->agp_info.aper_size * | |
1932 | 1024 * 1024, | |
1933 | MTRR_TYPE_WRCOMB, 1); | |
1934 | if (dev_priv->mm.gtt_mtrr < 0) { | |
040aefa2 | 1935 | DRM_INFO("MTRR allocation failed. Graphics " |
ab657db1 EA |
1936 | "performance may suffer.\n"); |
1937 | } | |
1938 | ||
19966754 DV |
1939 | dev_priv->mm.gtt = intel_gtt_get(); |
1940 | if (!dev_priv->mm.gtt) { | |
1941 | DRM_ERROR("Failed to initialize GTT\n"); | |
1942 | ret = -ENODEV; | |
2a34f5e6 | 1943 | goto out_iomapfree; |
d1d6ca73 JB |
1944 | } |
1945 | ||
19966754 DV |
1946 | prealloc_size = dev_priv->mm.gtt->gtt_stolen_entries << PAGE_SHIFT; |
1947 | agp_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT; | |
1948 | ||
e642abbf CW |
1949 | /* The i915 workqueue is primarily used for batched retirement of |
1950 | * requests (and thus managing bo) once the task has been completed | |
1951 | * by the GPU. i915_gem_retire_requests() is called directly when we | |
1952 | * need high-priority retirement, such as waiting for an explicit | |
1953 | * bo. | |
1954 | * | |
1955 | * It is also used for periodic low-priority events, such as | |
1956 | * idle-timers and hangcheck. | |
1957 | * | |
1958 | * All tasks on the workqueue are expected to acquire the dev mutex | |
1959 | * so there is no point in running more than one instance of the | |
1960 | * workqueue at any time: max_active = 1 and NON_REENTRANT. | |
1961 | */ | |
1962 | dev_priv->wq = alloc_workqueue("i915", | |
1963 | WQ_UNBOUND | WQ_NON_REENTRANT, | |
1964 | 1); | |
9c9fe1f8 EA |
1965 | if (dev_priv->wq == NULL) { |
1966 | DRM_ERROR("Failed to create our workqueue.\n"); | |
1967 | ret = -ENOMEM; | |
1968 | goto out_iomapfree; | |
1969 | } | |
1970 | ||
ac5c4e76 DA |
1971 | /* enable GEM by default */ |
1972 | dev_priv->has_gem = 1; | |
ac5c4e76 | 1973 | |
2a34f5e6 EA |
1974 | if (prealloc_size > agp_size * 3 / 4) { |
1975 | DRM_ERROR("Detected broken video BIOS with %d/%dkB of video " | |
1976 | "memory stolen.\n", | |
1977 | prealloc_size / 1024, agp_size / 1024); | |
1978 | DRM_ERROR("Disabling GEM. (try reducing stolen memory or " | |
1979 | "updating the BIOS to fix).\n"); | |
1980 | dev_priv->has_gem = 0; | |
1981 | } | |
1982 | ||
79a78dd6 CW |
1983 | if (dev_priv->has_gem == 0 && |
1984 | drm_core_check_feature(dev, DRIVER_MODESET)) { | |
1985 | DRM_ERROR("kernel modesetting requires GEM, disabling driver.\n"); | |
1986 | ret = -ENODEV; | |
1987 | goto out_iomapfree; | |
1988 | } | |
1989 | ||
9880b7a5 | 1990 | dev->driver->get_vblank_counter = i915_get_vblank_counter; |
42c2798b | 1991 | dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */ |
bad720ff | 1992 | if (IS_G4X(dev) || IS_IRONLAKE(dev) || IS_GEN6(dev)) { |
42c2798b | 1993 | dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */ |
9880b7a5 | 1994 | dev->driver->get_vblank_counter = gm45_get_vblank_counter; |
42c2798b | 1995 | } |
9880b7a5 | 1996 | |
c4804411 ZW |
1997 | /* Try to make sure MCHBAR is enabled before poking at it */ |
1998 | intel_setup_mchbar(dev); | |
f899fc64 | 1999 | intel_setup_gmbus(dev); |
44834a67 | 2000 | intel_opregion_setup(dev); |
c4804411 | 2001 | |
673a394b EA |
2002 | i915_gem_load(dev); |
2003 | ||
398c9cb2 KP |
2004 | /* Init HWS */ |
2005 | if (!I915_NEED_GFX_HWS(dev)) { | |
2006 | ret = i915_init_phys_hws(dev); | |
2007 | if (ret != 0) | |
9c9fe1f8 | 2008 | goto out_workqueue_free; |
398c9cb2 | 2009 | } |
ed4cb414 | 2010 | |
7648fa99 JB |
2011 | if (IS_PINEVIEW(dev)) |
2012 | i915_pineview_get_mem_freq(dev); | |
2013 | else if (IS_IRONLAKE(dev)) | |
2014 | i915_ironlake_get_mem_freq(dev); | |
7662c8bd | 2015 | |
ed4cb414 EA |
2016 | /* On the 945G/GM, the chipset reports the MSI capability on the |
2017 | * integrated graphics even though the support isn't actually there | |
2018 | * according to the published specs. It doesn't appear to function | |
2019 | * correctly in testing on 945G. | |
2020 | * This may be a side effect of MSI having been made available for PEG | |
2021 | * and the registers being closely associated. | |
d1ed629f KP |
2022 | * |
2023 | * According to chipset errata, on the 965GM, MSI interrupts may | |
b60678a7 KP |
2024 | * be lost or delayed, but we use them anyways to avoid |
2025 | * stuck interrupts on some machines. | |
ed4cb414 | 2026 | */ |
b60678a7 | 2027 | if (!IS_I945G(dev) && !IS_I945GM(dev)) |
d3e74d02 | 2028 | pci_enable_msi(dev->pdev); |
ed4cb414 EA |
2029 | |
2030 | spin_lock_init(&dev_priv->user_irq_lock); | |
63eeaf38 | 2031 | spin_lock_init(&dev_priv->error_lock); |
9d34e5db | 2032 | dev_priv->trace_irq_seqno = 0; |
ed4cb414 | 2033 | |
52440211 KP |
2034 | ret = drm_vblank_init(dev, I915_NUM_PIPE); |
2035 | ||
2036 | if (ret) { | |
2037 | (void) i915_driver_unload(dev); | |
2038 | return ret; | |
2039 | } | |
2040 | ||
11ed50ec BG |
2041 | /* Start out suspended */ |
2042 | dev_priv->mm.suspended = 1; | |
2043 | ||
3bad0781 ZW |
2044 | intel_detect_pch(dev); |
2045 | ||
79e53945 | 2046 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
ac622a9c | 2047 | ret = i915_load_modeset_init(dev, prealloc_size, agp_size); |
79e53945 JB |
2048 | if (ret < 0) { |
2049 | DRM_ERROR("failed to init modeset\n"); | |
9c9fe1f8 | 2050 | goto out_workqueue_free; |
79e53945 JB |
2051 | } |
2052 | } | |
2053 | ||
74a365b3 | 2054 | /* Must be done after probing outputs */ |
44834a67 CW |
2055 | intel_opregion_init(dev); |
2056 | acpi_video_register(); | |
74a365b3 | 2057 | |
f65d9421 BG |
2058 | setup_timer(&dev_priv->hangcheck_timer, i915_hangcheck_elapsed, |
2059 | (unsigned long) dev); | |
7648fa99 JB |
2060 | |
2061 | spin_lock(&mchdev_lock); | |
2062 | i915_mch_dev = dev_priv; | |
2063 | dev_priv->mchdev_lock = &mchdev_lock; | |
2064 | spin_unlock(&mchdev_lock); | |
2065 | ||
79e53945 JB |
2066 | return 0; |
2067 | ||
9c9fe1f8 EA |
2068 | out_workqueue_free: |
2069 | destroy_workqueue(dev_priv->wq); | |
6644107d VP |
2070 | out_iomapfree: |
2071 | io_mapping_free(dev_priv->mm.gtt_mapping); | |
79e53945 JB |
2072 | out_rmmap: |
2073 | iounmap(dev_priv->regs); | |
ec2a4c3f DA |
2074 | put_bridge: |
2075 | pci_dev_put(dev_priv->bridge_dev); | |
79e53945 | 2076 | free_priv: |
9a298b2a | 2077 | kfree(dev_priv); |
ba8bbcf6 JB |
2078 | return ret; |
2079 | } | |
2080 | ||
2081 | int i915_driver_unload(struct drm_device *dev) | |
2082 | { | |
2083 | struct drm_i915_private *dev_priv = dev->dev_private; | |
c911fc1c | 2084 | int ret; |
ba8bbcf6 | 2085 | |
7648fa99 JB |
2086 | spin_lock(&mchdev_lock); |
2087 | i915_mch_dev = NULL; | |
2088 | spin_unlock(&mchdev_lock); | |
2089 | ||
c911fc1c DV |
2090 | mutex_lock(&dev->struct_mutex); |
2091 | ret = i915_gpu_idle(dev); | |
2092 | if (ret) | |
2093 | DRM_ERROR("failed to idle hardware: %d\n", ret); | |
2094 | mutex_unlock(&dev->struct_mutex); | |
2095 | ||
75ef9da2 DV |
2096 | /* Cancel the retire work handler, which should be idle now. */ |
2097 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); | |
2098 | ||
ab657db1 EA |
2099 | io_mapping_free(dev_priv->mm.gtt_mapping); |
2100 | if (dev_priv->mm.gtt_mtrr >= 0) { | |
2101 | mtrr_del(dev_priv->mm.gtt_mtrr, dev->agp->base, | |
2102 | dev->agp->agp_info.aper_size * 1024 * 1024); | |
2103 | dev_priv->mm.gtt_mtrr = -1; | |
2104 | } | |
2105 | ||
44834a67 CW |
2106 | acpi_video_unregister(); |
2107 | ||
79e53945 | 2108 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
3d8620cc JB |
2109 | intel_modeset_cleanup(dev); |
2110 | ||
6363ee6f ZY |
2111 | /* |
2112 | * free the memory space allocated for the child device | |
2113 | * config parsed from VBT | |
2114 | */ | |
2115 | if (dev_priv->child_dev && dev_priv->child_dev_num) { | |
2116 | kfree(dev_priv->child_dev); | |
2117 | dev_priv->child_dev = NULL; | |
2118 | dev_priv->child_dev_num = 0; | |
2119 | } | |
6c0d9350 | 2120 | |
6a9ee8af | 2121 | vga_switcheroo_unregister_client(dev->pdev); |
28d52043 | 2122 | vga_client_register(dev->pdev, NULL, NULL, NULL); |
79e53945 JB |
2123 | } |
2124 | ||
a8b4899e | 2125 | /* Free error state after interrupts are fully disabled. */ |
bc0c7f14 DV |
2126 | del_timer_sync(&dev_priv->hangcheck_timer); |
2127 | cancel_work_sync(&dev_priv->error_work); | |
a8b4899e | 2128 | i915_destroy_error_state(dev); |
bc0c7f14 | 2129 | |
ed4cb414 EA |
2130 | if (dev->pdev->msi_enabled) |
2131 | pci_disable_msi(dev->pdev); | |
2132 | ||
3043c60c EA |
2133 | if (dev_priv->regs != NULL) |
2134 | iounmap(dev_priv->regs); | |
ba8bbcf6 | 2135 | |
44834a67 | 2136 | intel_opregion_fini(dev); |
8ee1c3db | 2137 | |
79e53945 | 2138 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
67e77c5a DV |
2139 | /* Flush any outstanding unpin_work. */ |
2140 | flush_workqueue(dev_priv->wq); | |
2141 | ||
71acb5eb DA |
2142 | i915_gem_free_all_phys_object(dev); |
2143 | ||
79e53945 JB |
2144 | mutex_lock(&dev->struct_mutex); |
2145 | i915_gem_cleanup_ringbuffer(dev); | |
2146 | mutex_unlock(&dev->struct_mutex); | |
20bf377e JB |
2147 | if (I915_HAS_FBC(dev) && i915_powersave) |
2148 | i915_cleanup_compression(dev); | |
19966754 | 2149 | drm_mm_takedown(&dev_priv->mm.vram); |
02e792fb DV |
2150 | |
2151 | intel_cleanup_overlay(dev); | |
79e53945 JB |
2152 | } |
2153 | ||
f899fc64 | 2154 | intel_teardown_gmbus(dev); |
c4804411 ZW |
2155 | intel_teardown_mchbar(dev); |
2156 | ||
bc0c7f14 DV |
2157 | destroy_workqueue(dev_priv->wq); |
2158 | ||
ec2a4c3f | 2159 | pci_dev_put(dev_priv->bridge_dev); |
9a298b2a | 2160 | kfree(dev->dev_private); |
ba8bbcf6 | 2161 | |
22eae947 DA |
2162 | return 0; |
2163 | } | |
2164 | ||
673a394b EA |
2165 | int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv) |
2166 | { | |
2167 | struct drm_i915_file_private *i915_file_priv; | |
2168 | ||
8a4c47f3 | 2169 | DRM_DEBUG_DRIVER("\n"); |
673a394b | 2170 | i915_file_priv = (struct drm_i915_file_private *) |
9a298b2a | 2171 | kmalloc(sizeof(*i915_file_priv), GFP_KERNEL); |
673a394b EA |
2172 | |
2173 | if (!i915_file_priv) | |
2174 | return -ENOMEM; | |
2175 | ||
2176 | file_priv->driver_priv = i915_file_priv; | |
2177 | ||
b962442e | 2178 | INIT_LIST_HEAD(&i915_file_priv->mm.request_list); |
673a394b EA |
2179 | |
2180 | return 0; | |
2181 | } | |
2182 | ||
79e53945 JB |
2183 | /** |
2184 | * i915_driver_lastclose - clean up after all DRM clients have exited | |
2185 | * @dev: DRM device | |
2186 | * | |
2187 | * Take care of cleaning up after all DRM clients have exited. In the | |
2188 | * mode setting case, we want to restore the kernel's initial mode (just | |
2189 | * in case the last client left us in a bad state). | |
2190 | * | |
2191 | * Additionally, in the non-mode setting case, we'll tear down the AGP | |
2192 | * and DMA structures, since the kernel won't be using them, and clea | |
2193 | * up any GEM state. | |
2194 | */ | |
84b1fd10 | 2195 | void i915_driver_lastclose(struct drm_device * dev) |
1da177e4 | 2196 | { |
ba8bbcf6 JB |
2197 | drm_i915_private_t *dev_priv = dev->dev_private; |
2198 | ||
79e53945 | 2199 | if (!dev_priv || drm_core_check_feature(dev, DRIVER_MODESET)) { |
785b93ef | 2200 | drm_fb_helper_restore(); |
6a9ee8af | 2201 | vga_switcheroo_process_delayed_switch(); |
144a75fa | 2202 | return; |
79e53945 | 2203 | } |
144a75fa | 2204 | |
673a394b EA |
2205 | i915_gem_lastclose(dev); |
2206 | ||
ba8bbcf6 | 2207 | if (dev_priv->agp_heap) |
b5e89ed5 | 2208 | i915_mem_takedown(&(dev_priv->agp_heap)); |
ba8bbcf6 | 2209 | |
b5e89ed5 | 2210 | i915_dma_cleanup(dev); |
1da177e4 LT |
2211 | } |
2212 | ||
6c340eac | 2213 | void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv) |
1da177e4 | 2214 | { |
ba8bbcf6 | 2215 | drm_i915_private_t *dev_priv = dev->dev_private; |
b962442e | 2216 | i915_gem_release(dev, file_priv); |
79e53945 JB |
2217 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
2218 | i915_mem_release(dev, file_priv, dev_priv->agp_heap); | |
1da177e4 LT |
2219 | } |
2220 | ||
673a394b EA |
2221 | void i915_driver_postclose(struct drm_device *dev, struct drm_file *file_priv) |
2222 | { | |
2223 | struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv; | |
2224 | ||
9a298b2a | 2225 | kfree(i915_file_priv); |
673a394b EA |
2226 | } |
2227 | ||
c153f45f | 2228 | struct drm_ioctl_desc i915_ioctls[] = { |
1b2f1489 DA |
2229 | DRM_IOCTL_DEF_DRV(I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
2230 | DRM_IOCTL_DEF_DRV(I915_FLUSH, i915_flush_ioctl, DRM_AUTH), | |
2231 | DRM_IOCTL_DEF_DRV(I915_FLIP, i915_flip_bufs, DRM_AUTH), | |
2232 | DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH), | |
2233 | DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH), | |
2234 | DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH), | |
2235 | DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH), | |
2236 | DRM_IOCTL_DEF_DRV(I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
2237 | DRM_IOCTL_DEF_DRV(I915_ALLOC, i915_mem_alloc, DRM_AUTH), | |
2238 | DRM_IOCTL_DEF_DRV(I915_FREE, i915_mem_free, DRM_AUTH), | |
2239 | DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, i915_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
2240 | DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH), | |
2241 | DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, i915_mem_destroy_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
2242 | DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
2243 | DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, i915_vblank_pipe_get, DRM_AUTH), | |
2244 | DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH), | |
2245 | DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
2246 | DRM_IOCTL_DEF_DRV(I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED), | |
2247 | DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH|DRM_UNLOCKED), | |
2248 | DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_UNLOCKED), | |
2249 | DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED), | |
2250 | DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED), | |
2251 | DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED), | |
2252 | DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_UNLOCKED), | |
2253 | DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED), | |
2254 | DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED), | |
2255 | DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_UNLOCKED), | |
2256 | DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED), | |
2257 | DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED), | |
2258 | DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_UNLOCKED), | |
2259 | DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED), | |
2260 | DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED), | |
2261 | DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED), | |
2262 | DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_UNLOCKED), | |
2263 | DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_UNLOCKED), | |
2264 | DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED), | |
2265 | DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED), | |
2266 | DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED), | |
2267 | DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED), | |
2268 | DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED), | |
c94f7029 DA |
2269 | }; |
2270 | ||
2271 | int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls); | |
cda17380 DA |
2272 | |
2273 | /** | |
2274 | * Determine if the device really is AGP or not. | |
2275 | * | |
2276 | * All Intel graphics chipsets are treated as AGP, even if they are really | |
2277 | * PCI-e. | |
2278 | * | |
2279 | * \param dev The device to be tested. | |
2280 | * | |
2281 | * \returns | |
2282 | * A value of 1 is always retured to indictate every i9x5 is AGP. | |
2283 | */ | |
84b1fd10 | 2284 | int i915_driver_device_is_agp(struct drm_device * dev) |
cda17380 DA |
2285 | { |
2286 | return 1; | |
2287 | } |