Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* i915_dma.c -- DMA support for the I915 -*- linux-c -*- |
2 | */ | |
0d6aa60b | 3 | /* |
1da177e4 LT |
4 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
5 | * All Rights Reserved. | |
bc54fd1a DA |
6 | * |
7 | * Permission is hereby granted, free of charge, to any person obtaining a | |
8 | * copy of this software and associated documentation files (the | |
9 | * "Software"), to deal in the Software without restriction, including | |
10 | * without limitation the rights to use, copy, modify, merge, publish, | |
11 | * distribute, sub license, and/or sell copies of the Software, and to | |
12 | * permit persons to whom the Software is furnished to do so, subject to | |
13 | * the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice (including the | |
16 | * next paragraph) shall be included in all copies or substantial portions | |
17 | * of the Software. | |
18 | * | |
19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
20 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
21 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
22 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
23 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
24 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
25 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
26 | * | |
0d6aa60b | 27 | */ |
1da177e4 | 28 | |
a70491cc JP |
29 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
30 | ||
760285e7 DH |
31 | #include <drm/drmP.h> |
32 | #include <drm/drm_crtc_helper.h> | |
33 | #include <drm/drm_fb_helper.h> | |
4f03b1fc | 34 | #include <drm/drm_legacy.h> |
79e53945 | 35 | #include "intel_drv.h" |
760285e7 | 36 | #include <drm/i915_drm.h> |
1da177e4 | 37 | #include "i915_drv.h" |
e21fd552 | 38 | #include "i915_vgpu.h" |
1c5d22f7 | 39 | #include "i915_trace.h" |
dcdb1674 | 40 | #include <linux/pci.h> |
a4de0526 DV |
41 | #include <linux/console.h> |
42 | #include <linux/vt.h> | |
28d52043 | 43 | #include <linux/vgaarb.h> |
c4804411 ZW |
44 | #include <linux/acpi.h> |
45 | #include <linux/pnp.h> | |
6a9ee8af | 46 | #include <linux/vga_switcheroo.h> |
5a0e3ad6 | 47 | #include <linux/slab.h> |
44834a67 | 48 | #include <acpi/video.h> |
8a187455 PZ |
49 | #include <linux/pm.h> |
50 | #include <linux/pm_runtime.h> | |
4bdc7293 | 51 | #include <linux/oom.h> |
1da177e4 | 52 | |
4fec15d1 ID |
53 | static unsigned int i915_load_fail_count; |
54 | ||
55 | bool __i915_inject_load_failure(const char *func, int line) | |
56 | { | |
57 | if (i915_load_fail_count >= i915.inject_load_failure) | |
58 | return false; | |
59 | ||
60 | if (++i915_load_fail_count == i915.inject_load_failure) { | |
61 | DRM_INFO("Injecting failure at checkpoint %u [%s:%d]\n", | |
62 | i915.inject_load_failure, func, line); | |
63 | return true; | |
64 | } | |
65 | ||
66 | return false; | |
67 | } | |
1da177e4 | 68 | |
c153f45f EA |
69 | static int i915_getparam(struct drm_device *dev, void *data, |
70 | struct drm_file *file_priv) | |
1da177e4 | 71 | { |
4c8a4be9 | 72 | struct drm_i915_private *dev_priv = dev->dev_private; |
c153f45f | 73 | drm_i915_getparam_t *param = data; |
1da177e4 LT |
74 | int value; |
75 | ||
c153f45f | 76 | switch (param->param) { |
1da177e4 | 77 | case I915_PARAM_IRQ_ACTIVE: |
1da177e4 | 78 | case I915_PARAM_ALLOW_BATCHBUFFER: |
0d6aa60b | 79 | case I915_PARAM_LAST_DISPATCH: |
ac883c84 | 80 | /* Reject all old ums/dri params. */ |
5c6c6003 | 81 | return -ENODEV; |
ed4c9c4a | 82 | case I915_PARAM_CHIPSET_ID: |
ffbab09b | 83 | value = dev->pdev->device; |
ed4c9c4a | 84 | break; |
27cd4461 NR |
85 | case I915_PARAM_REVISION: |
86 | value = dev->pdev->revision; | |
87 | break; | |
673a394b | 88 | case I915_PARAM_HAS_GEM: |
2e895b17 | 89 | value = 1; |
673a394b | 90 | break; |
0f973f27 | 91 | case I915_PARAM_NUM_FENCES_AVAIL: |
c668cde5 | 92 | value = dev_priv->num_fence_regs; |
0f973f27 | 93 | break; |
02e792fb DV |
94 | case I915_PARAM_HAS_OVERLAY: |
95 | value = dev_priv->overlay ? 1 : 0; | |
96 | break; | |
e9560f7c JB |
97 | case I915_PARAM_HAS_PAGEFLIPPING: |
98 | value = 1; | |
99 | break; | |
76446cac JB |
100 | case I915_PARAM_HAS_EXECBUF2: |
101 | /* depends on GEM */ | |
2e895b17 | 102 | value = 1; |
76446cac | 103 | break; |
e3a815fc | 104 | case I915_PARAM_HAS_BSD: |
117897f4 | 105 | value = intel_engine_initialized(&dev_priv->engine[VCS]); |
e3a815fc | 106 | break; |
549f7365 | 107 | case I915_PARAM_HAS_BLT: |
117897f4 | 108 | value = intel_engine_initialized(&dev_priv->engine[BCS]); |
549f7365 | 109 | break; |
a1f2cc73 | 110 | case I915_PARAM_HAS_VEBOX: |
117897f4 | 111 | value = intel_engine_initialized(&dev_priv->engine[VECS]); |
a1f2cc73 | 112 | break; |
08e16dc8 | 113 | case I915_PARAM_HAS_BSD2: |
117897f4 | 114 | value = intel_engine_initialized(&dev_priv->engine[VCS2]); |
08e16dc8 | 115 | break; |
a00b10c3 CW |
116 | case I915_PARAM_HAS_RELAXED_FENCING: |
117 | value = 1; | |
118 | break; | |
bbf0c6b3 DV |
119 | case I915_PARAM_HAS_COHERENT_RINGS: |
120 | value = 1; | |
121 | break; | |
72bfa19c CW |
122 | case I915_PARAM_HAS_EXEC_CONSTANTS: |
123 | value = INTEL_INFO(dev)->gen >= 4; | |
124 | break; | |
271d81b8 CW |
125 | case I915_PARAM_HAS_RELAXED_DELTA: |
126 | value = 1; | |
127 | break; | |
ae662d31 EA |
128 | case I915_PARAM_HAS_GEN7_SOL_RESET: |
129 | value = 1; | |
130 | break; | |
3d29b842 ED |
131 | case I915_PARAM_HAS_LLC: |
132 | value = HAS_LLC(dev); | |
133 | break; | |
651d794f CW |
134 | case I915_PARAM_HAS_WT: |
135 | value = HAS_WT(dev); | |
136 | break; | |
777ee96f | 137 | case I915_PARAM_HAS_ALIASING_PPGTT: |
896ab1a5 | 138 | value = USES_PPGTT(dev); |
777ee96f | 139 | break; |
172cf15d BW |
140 | case I915_PARAM_HAS_WAIT_TIMEOUT: |
141 | value = 1; | |
142 | break; | |
2fedbff9 CW |
143 | case I915_PARAM_HAS_SEMAPHORES: |
144 | value = i915_semaphore_is_enabled(dev); | |
145 | break; | |
ec6f1bb9 DA |
146 | case I915_PARAM_HAS_PRIME_VMAP_FLUSH: |
147 | value = 1; | |
148 | break; | |
d7d4eedd CW |
149 | case I915_PARAM_HAS_SECURE_BATCHES: |
150 | value = capable(CAP_SYS_ADMIN); | |
151 | break; | |
b45305fc DV |
152 | case I915_PARAM_HAS_PINNED_BATCHES: |
153 | value = 1; | |
154 | break; | |
ed5982e6 DV |
155 | case I915_PARAM_HAS_EXEC_NO_RELOC: |
156 | value = 1; | |
157 | break; | |
eef90ccb CW |
158 | case I915_PARAM_HAS_EXEC_HANDLE_LUT: |
159 | value = 1; | |
160 | break; | |
d728c8ef BV |
161 | case I915_PARAM_CMD_PARSER_VERSION: |
162 | value = i915_cmd_parser_get_version(); | |
163 | break; | |
6a2c4232 CW |
164 | case I915_PARAM_HAS_COHERENT_PHYS_GTT: |
165 | value = 1; | |
1816f923 AG |
166 | break; |
167 | case I915_PARAM_MMAP_VERSION: | |
168 | value = 1; | |
6a2c4232 | 169 | break; |
a1559ffe JM |
170 | case I915_PARAM_SUBSLICE_TOTAL: |
171 | value = INTEL_INFO(dev)->subslice_total; | |
172 | if (!value) | |
173 | return -ENODEV; | |
174 | break; | |
175 | case I915_PARAM_EU_TOTAL: | |
176 | value = INTEL_INFO(dev)->eu_total; | |
177 | if (!value) | |
178 | return -ENODEV; | |
179 | break; | |
49e4d842 CW |
180 | case I915_PARAM_HAS_GPU_RESET: |
181 | value = i915.enable_hangcheck && | |
49e4d842 CW |
182 | intel_has_gpu_reset(dev); |
183 | break; | |
a9ed33ca AJ |
184 | case I915_PARAM_HAS_RESOURCE_STREAMER: |
185 | value = HAS_RESOURCE_STREAMER(dev); | |
186 | break; | |
506a8e87 CW |
187 | case I915_PARAM_HAS_EXEC_SOFTPIN: |
188 | value = 1; | |
189 | break; | |
1da177e4 | 190 | default: |
e29c32da | 191 | DRM_DEBUG("Unknown parameter %d\n", param->param); |
20caafa6 | 192 | return -EINVAL; |
1da177e4 LT |
193 | } |
194 | ||
1d6ac185 DV |
195 | if (copy_to_user(param->value, &value, sizeof(int))) { |
196 | DRM_ERROR("copy_to_user failed\n"); | |
20caafa6 | 197 | return -EFAULT; |
1da177e4 LT |
198 | } |
199 | ||
200 | return 0; | |
201 | } | |
202 | ||
ec2a4c3f DA |
203 | static int i915_get_bridge_dev(struct drm_device *dev) |
204 | { | |
205 | struct drm_i915_private *dev_priv = dev->dev_private; | |
206 | ||
0206e353 | 207 | dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0)); |
ec2a4c3f DA |
208 | if (!dev_priv->bridge_dev) { |
209 | DRM_ERROR("bridge device not found\n"); | |
210 | return -1; | |
211 | } | |
212 | return 0; | |
213 | } | |
214 | ||
c4804411 ZW |
215 | #define MCHBAR_I915 0x44 |
216 | #define MCHBAR_I965 0x48 | |
217 | #define MCHBAR_SIZE (4*4096) | |
218 | ||
219 | #define DEVEN_REG 0x54 | |
220 | #define DEVEN_MCHBAR_EN (1 << 28) | |
221 | ||
222 | /* Allocate space for the MCH regs if needed, return nonzero on error */ | |
223 | static int | |
224 | intel_alloc_mchbar_resource(struct drm_device *dev) | |
225 | { | |
4c8a4be9 | 226 | struct drm_i915_private *dev_priv = dev->dev_private; |
a6c45cf0 | 227 | int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915; |
c4804411 ZW |
228 | u32 temp_lo, temp_hi = 0; |
229 | u64 mchbar_addr; | |
a25c25c2 | 230 | int ret; |
c4804411 | 231 | |
a6c45cf0 | 232 | if (INTEL_INFO(dev)->gen >= 4) |
c4804411 ZW |
233 | pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi); |
234 | pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo); | |
235 | mchbar_addr = ((u64)temp_hi << 32) | temp_lo; | |
236 | ||
237 | /* If ACPI doesn't have it, assume we need to allocate it ourselves */ | |
238 | #ifdef CONFIG_PNP | |
239 | if (mchbar_addr && | |
a25c25c2 CW |
240 | pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE)) |
241 | return 0; | |
c4804411 ZW |
242 | #endif |
243 | ||
244 | /* Get some space for it */ | |
a25c25c2 CW |
245 | dev_priv->mch_res.name = "i915 MCHBAR"; |
246 | dev_priv->mch_res.flags = IORESOURCE_MEM; | |
247 | ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus, | |
248 | &dev_priv->mch_res, | |
c4804411 ZW |
249 | MCHBAR_SIZE, MCHBAR_SIZE, |
250 | PCIBIOS_MIN_MEM, | |
a25c25c2 | 251 | 0, pcibios_align_resource, |
c4804411 ZW |
252 | dev_priv->bridge_dev); |
253 | if (ret) { | |
254 | DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret); | |
255 | dev_priv->mch_res.start = 0; | |
a25c25c2 | 256 | return ret; |
c4804411 ZW |
257 | } |
258 | ||
a6c45cf0 | 259 | if (INTEL_INFO(dev)->gen >= 4) |
c4804411 ZW |
260 | pci_write_config_dword(dev_priv->bridge_dev, reg + 4, |
261 | upper_32_bits(dev_priv->mch_res.start)); | |
262 | ||
263 | pci_write_config_dword(dev_priv->bridge_dev, reg, | |
264 | lower_32_bits(dev_priv->mch_res.start)); | |
a25c25c2 | 265 | return 0; |
c4804411 ZW |
266 | } |
267 | ||
268 | /* Setup MCHBAR if possible, return true if we should disable it again */ | |
269 | static void | |
270 | intel_setup_mchbar(struct drm_device *dev) | |
271 | { | |
4c8a4be9 | 272 | struct drm_i915_private *dev_priv = dev->dev_private; |
a6c45cf0 | 273 | int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915; |
c4804411 ZW |
274 | u32 temp; |
275 | bool enabled; | |
276 | ||
666a4537 | 277 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
11ea8b7d JB |
278 | return; |
279 | ||
c4804411 ZW |
280 | dev_priv->mchbar_need_disable = false; |
281 | ||
282 | if (IS_I915G(dev) || IS_I915GM(dev)) { | |
283 | pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp); | |
284 | enabled = !!(temp & DEVEN_MCHBAR_EN); | |
285 | } else { | |
286 | pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); | |
287 | enabled = temp & 1; | |
288 | } | |
289 | ||
290 | /* If it's already enabled, don't have to do anything */ | |
291 | if (enabled) | |
292 | return; | |
293 | ||
294 | if (intel_alloc_mchbar_resource(dev)) | |
295 | return; | |
296 | ||
297 | dev_priv->mchbar_need_disable = true; | |
298 | ||
299 | /* Space is allocated or reserved, so enable it. */ | |
300 | if (IS_I915G(dev) || IS_I915GM(dev)) { | |
301 | pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, | |
302 | temp | DEVEN_MCHBAR_EN); | |
303 | } else { | |
304 | pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); | |
305 | pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1); | |
306 | } | |
307 | } | |
308 | ||
309 | static void | |
310 | intel_teardown_mchbar(struct drm_device *dev) | |
311 | { | |
4c8a4be9 | 312 | struct drm_i915_private *dev_priv = dev->dev_private; |
a6c45cf0 | 313 | int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915; |
c4804411 ZW |
314 | u32 temp; |
315 | ||
316 | if (dev_priv->mchbar_need_disable) { | |
317 | if (IS_I915G(dev) || IS_I915GM(dev)) { | |
318 | pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp); | |
319 | temp &= ~DEVEN_MCHBAR_EN; | |
320 | pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp); | |
321 | } else { | |
322 | pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); | |
323 | temp &= ~1; | |
324 | pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp); | |
325 | } | |
326 | } | |
327 | ||
328 | if (dev_priv->mch_res.start) | |
329 | release_resource(&dev_priv->mch_res); | |
330 | } | |
331 | ||
28d52043 DA |
332 | /* true = enable decode, false = disable decoder */ |
333 | static unsigned int i915_vga_set_decode(void *cookie, bool state) | |
334 | { | |
335 | struct drm_device *dev = cookie; | |
336 | ||
337 | intel_modeset_vga_set_state(dev, state); | |
338 | if (state) | |
339 | return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | | |
340 | VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
341 | else | |
342 | return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
343 | } | |
344 | ||
6a9ee8af DA |
345 | static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state) |
346 | { | |
347 | struct drm_device *dev = pci_get_drvdata(pdev); | |
348 | pm_message_t pmm = { .event = PM_EVENT_SUSPEND }; | |
1a5036bf | 349 | |
6a9ee8af | 350 | if (state == VGA_SWITCHEROO_ON) { |
a70491cc | 351 | pr_info("switched on\n"); |
5bcf719b | 352 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; |
6a9ee8af DA |
353 | /* i915 resume handler doesn't set to D0 */ |
354 | pci_set_power_state(dev->pdev, PCI_D0); | |
1751fcf9 | 355 | i915_resume_switcheroo(dev); |
5bcf719b | 356 | dev->switch_power_state = DRM_SWITCH_POWER_ON; |
6a9ee8af | 357 | } else { |
fa9d6078 | 358 | pr_info("switched off\n"); |
5bcf719b | 359 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; |
1751fcf9 | 360 | i915_suspend_switcheroo(dev, pmm); |
5bcf719b | 361 | dev->switch_power_state = DRM_SWITCH_POWER_OFF; |
6a9ee8af DA |
362 | } |
363 | } | |
364 | ||
365 | static bool i915_switcheroo_can_switch(struct pci_dev *pdev) | |
366 | { | |
367 | struct drm_device *dev = pci_get_drvdata(pdev); | |
6a9ee8af | 368 | |
fc8fd40e DV |
369 | /* |
370 | * FIXME: open_count is protected by drm_global_mutex but that would lead to | |
371 | * locking inversion with the driver load path. And the access here is | |
372 | * completely racy anyway. So don't bother with locking for now. | |
373 | */ | |
374 | return dev->open_count == 0; | |
6a9ee8af DA |
375 | } |
376 | ||
26ec685f TI |
377 | static const struct vga_switcheroo_client_ops i915_switcheroo_ops = { |
378 | .set_gpu_state = i915_switcheroo_set_state, | |
379 | .reprobe = NULL, | |
380 | .can_switch = i915_switcheroo_can_switch, | |
381 | }; | |
382 | ||
2c7111db CW |
383 | static int i915_load_modeset_init(struct drm_device *dev) |
384 | { | |
385 | struct drm_i915_private *dev_priv = dev->dev_private; | |
386 | int ret; | |
79e53945 | 387 | |
4fec15d1 ID |
388 | if (i915_inject_load_failure()) |
389 | return -ENODEV; | |
390 | ||
98f3a1dc | 391 | ret = intel_bios_init(dev_priv); |
79e53945 JB |
392 | if (ret) |
393 | DRM_INFO("failed to find VBIOS tables\n"); | |
394 | ||
934f992c CW |
395 | /* If we have > 1 VGA cards, then we need to arbitrate access |
396 | * to the common VGA resources. | |
397 | * | |
398 | * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA), | |
399 | * then we do not take part in VGA arbitration and the | |
400 | * vga_client_register() fails with -ENODEV. | |
401 | */ | |
ebff5fa9 DA |
402 | ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode); |
403 | if (ret && ret != -ENODEV) | |
404 | goto out; | |
28d52043 | 405 | |
723bfd70 JB |
406 | intel_register_dsm_handler(); |
407 | ||
0d69704a | 408 | ret = vga_switcheroo_register_client(dev->pdev, &i915_switcheroo_ops, false); |
6a9ee8af | 409 | if (ret) |
5a79395b | 410 | goto cleanup_vga_client; |
6a9ee8af | 411 | |
73dfc227 | 412 | intel_power_domains_init_hw(dev_priv, false); |
e13192f6 | 413 | |
f4448375 | 414 | intel_csr_ucode_init(dev_priv); |
ebae38d0 | 415 | |
2aeb7d3a | 416 | ret = intel_irq_install(dev_priv); |
52d7eced | 417 | if (ret) |
89250fec | 418 | goto cleanup_csr; |
52d7eced | 419 | |
f5949141 DV |
420 | intel_setup_gmbus(dev); |
421 | ||
52d7eced DV |
422 | /* Important: The output setup functions called by modeset_init need |
423 | * working irqs for e.g. gmbus and dp aux transfers. */ | |
b01f2c3a JB |
424 | intel_modeset_init(dev); |
425 | ||
33a732f4 | 426 | intel_guc_ucode_init(dev); |
33a732f4 | 427 | |
1070a42b | 428 | ret = i915_gem_init(dev); |
79e53945 | 429 | if (ret) |
713028b3 | 430 | goto cleanup_irq; |
2c7111db | 431 | |
52d7eced | 432 | intel_modeset_gem_init(dev); |
2c7111db | 433 | |
79e53945 JB |
434 | /* Always safe in the mode setting case. */ |
435 | /* FIXME: do pre/post-mode set stuff in core KMS code */ | |
ba0bf120 | 436 | dev->vblank_disable_allowed = true; |
713028b3 | 437 | if (INTEL_INFO(dev)->num_pipes == 0) |
e3c74757 | 438 | return 0; |
79e53945 | 439 | |
5a79395b CW |
440 | ret = intel_fbdev_init(dev); |
441 | if (ret) | |
52d7eced DV |
442 | goto cleanup_gem; |
443 | ||
20afbda2 | 444 | /* Only enable hotplug handling once the fbdev is fully set up. */ |
b963291c | 445 | intel_hpd_init(dev_priv); |
20afbda2 DV |
446 | |
447 | /* | |
448 | * Some ports require correctly set-up hpd registers for detection to | |
449 | * work properly (leading to ghost connected connector status), e.g. VGA | |
450 | * on gm45. Hence we can only set up the initial fbdev config after hpd | |
451 | * irqs are fully enabled. Now we should scan for the initial config | |
452 | * only once hotplug handling is enabled, but due to screwed-up locking | |
453 | * around kms/fbdev init we can't protect the fdbev initial config | |
454 | * scanning against hotplug events. Hence do this first and ignore the | |
455 | * tiny window where we will loose hotplug notifactions. | |
456 | */ | |
e00bf696 | 457 | intel_fbdev_initial_config_async(dev); |
20afbda2 | 458 | |
eb1f8e4f | 459 | drm_kms_helper_poll_init(dev); |
87acb0a5 | 460 | |
79e53945 JB |
461 | return 0; |
462 | ||
2c7111db CW |
463 | cleanup_gem: |
464 | mutex_lock(&dev->struct_mutex); | |
117897f4 | 465 | i915_gem_cleanup_engines(dev); |
55d23285 | 466 | i915_gem_context_fini(dev); |
2c7111db | 467 | mutex_unlock(&dev->struct_mutex); |
713028b3 | 468 | cleanup_irq: |
33a732f4 | 469 | intel_guc_ucode_fini(dev); |
52d7eced | 470 | drm_irq_uninstall(dev); |
f5949141 | 471 | intel_teardown_gmbus(dev); |
89250fec ID |
472 | cleanup_csr: |
473 | intel_csr_ucode_fini(dev_priv); | |
65ff442f | 474 | intel_power_domains_fini(dev_priv); |
5a79395b CW |
475 | vga_switcheroo_unregister_client(dev->pdev); |
476 | cleanup_vga_client: | |
477 | vga_client_register(dev->pdev, NULL, NULL, NULL); | |
79e53945 JB |
478 | out: |
479 | return ret; | |
480 | } | |
481 | ||
243eaf38 | 482 | #if IS_ENABLED(CONFIG_FB) |
f96de58f | 483 | static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv) |
e188719a DV |
484 | { |
485 | struct apertures_struct *ap; | |
486 | struct pci_dev *pdev = dev_priv->dev->pdev; | |
487 | bool primary; | |
f96de58f | 488 | int ret; |
e188719a DV |
489 | |
490 | ap = alloc_apertures(1); | |
491 | if (!ap) | |
f96de58f | 492 | return -ENOMEM; |
e188719a | 493 | |
62106b4f JL |
494 | ap->ranges[0].base = dev_priv->ggtt.mappable_base; |
495 | ap->ranges[0].size = dev_priv->ggtt.mappable_end; | |
93d18799 | 496 | |
e188719a DV |
497 | primary = |
498 | pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW; | |
499 | ||
f96de58f | 500 | ret = remove_conflicting_framebuffers(ap, "inteldrmfb", primary); |
e188719a DV |
501 | |
502 | kfree(ap); | |
f96de58f CW |
503 | |
504 | return ret; | |
e188719a | 505 | } |
4520f53a | 506 | #else |
f96de58f | 507 | static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv) |
4520f53a | 508 | { |
f96de58f | 509 | return 0; |
4520f53a DV |
510 | } |
511 | #endif | |
e188719a | 512 | |
a4de0526 DV |
513 | #if !defined(CONFIG_VGA_CONSOLE) |
514 | static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv) | |
515 | { | |
516 | return 0; | |
517 | } | |
518 | #elif !defined(CONFIG_DUMMY_CONSOLE) | |
519 | static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv) | |
520 | { | |
521 | return -ENODEV; | |
522 | } | |
523 | #else | |
524 | static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv) | |
525 | { | |
1bb9e632 | 526 | int ret = 0; |
a4de0526 DV |
527 | |
528 | DRM_INFO("Replacing VGA console driver\n"); | |
529 | ||
530 | console_lock(); | |
1bb9e632 DV |
531 | if (con_is_bound(&vga_con)) |
532 | ret = do_take_over_console(&dummy_con, 0, MAX_NR_CONSOLES - 1, 1); | |
a4de0526 DV |
533 | if (ret == 0) { |
534 | ret = do_unregister_con_driver(&vga_con); | |
535 | ||
536 | /* Ignore "already unregistered". */ | |
537 | if (ret == -ENODEV) | |
538 | ret = 0; | |
539 | } | |
540 | console_unlock(); | |
541 | ||
542 | return ret; | |
543 | } | |
544 | #endif | |
545 | ||
c96ea64e DV |
546 | static void i915_dump_device_info(struct drm_i915_private *dev_priv) |
547 | { | |
5c969aa7 | 548 | const struct intel_device_info *info = &dev_priv->info; |
c96ea64e | 549 | |
e2a5800a DL |
550 | #define PRINT_S(name) "%s" |
551 | #define SEP_EMPTY | |
79fc46df DL |
552 | #define PRINT_FLAG(name) info->name ? #name "," : "" |
553 | #define SEP_COMMA , | |
19c656a1 | 554 | DRM_DEBUG_DRIVER("i915 device info: gen=%i, pciid=0x%04x rev=0x%02x flags=" |
e2a5800a | 555 | DEV_INFO_FOR_EACH_FLAG(PRINT_S, SEP_EMPTY), |
c96ea64e DV |
556 | info->gen, |
557 | dev_priv->dev->pdev->device, | |
19c656a1 | 558 | dev_priv->dev->pdev->revision, |
79fc46df | 559 | DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_COMMA)); |
e2a5800a DL |
560 | #undef PRINT_S |
561 | #undef SEP_EMPTY | |
79fc46df DL |
562 | #undef PRINT_FLAG |
563 | #undef SEP_COMMA | |
c96ea64e DV |
564 | } |
565 | ||
9705ad8a JM |
566 | static void cherryview_sseu_info_init(struct drm_device *dev) |
567 | { | |
568 | struct drm_i915_private *dev_priv = dev->dev_private; | |
569 | struct intel_device_info *info; | |
570 | u32 fuse, eu_dis; | |
571 | ||
572 | info = (struct intel_device_info *)&dev_priv->info; | |
573 | fuse = I915_READ(CHV_FUSE_GT); | |
574 | ||
575 | info->slice_total = 1; | |
576 | ||
577 | if (!(fuse & CHV_FGT_DISABLE_SS0)) { | |
578 | info->subslice_per_slice++; | |
579 | eu_dis = fuse & (CHV_FGT_EU_DIS_SS0_R0_MASK | | |
580 | CHV_FGT_EU_DIS_SS0_R1_MASK); | |
581 | info->eu_total += 8 - hweight32(eu_dis); | |
582 | } | |
583 | ||
584 | if (!(fuse & CHV_FGT_DISABLE_SS1)) { | |
585 | info->subslice_per_slice++; | |
586 | eu_dis = fuse & (CHV_FGT_EU_DIS_SS1_R0_MASK | | |
587 | CHV_FGT_EU_DIS_SS1_R1_MASK); | |
588 | info->eu_total += 8 - hweight32(eu_dis); | |
589 | } | |
590 | ||
591 | info->subslice_total = info->subslice_per_slice; | |
592 | /* | |
593 | * CHV expected to always have a uniform distribution of EU | |
594 | * across subslices. | |
595 | */ | |
596 | info->eu_per_subslice = info->subslice_total ? | |
597 | info->eu_total / info->subslice_total : | |
598 | 0; | |
599 | /* | |
600 | * CHV supports subslice power gating on devices with more than | |
601 | * one subslice, and supports EU power gating on devices with | |
602 | * more than one EU pair per subslice. | |
603 | */ | |
604 | info->has_slice_pg = 0; | |
605 | info->has_subslice_pg = (info->subslice_total > 1); | |
606 | info->has_eu_pg = (info->eu_per_subslice > 2); | |
607 | } | |
608 | ||
609 | static void gen9_sseu_info_init(struct drm_device *dev) | |
610 | { | |
611 | struct drm_i915_private *dev_priv = dev->dev_private; | |
612 | struct intel_device_info *info; | |
dead16e2 | 613 | int s_max = 3, ss_max = 4, eu_max = 8; |
9705ad8a | 614 | int s, ss; |
dead16e2 JM |
615 | u32 fuse2, s_enable, ss_disable, eu_disable; |
616 | u8 eu_mask = 0xff; | |
617 | ||
9705ad8a JM |
618 | info = (struct intel_device_info *)&dev_priv->info; |
619 | fuse2 = I915_READ(GEN8_FUSE2); | |
620 | s_enable = (fuse2 & GEN8_F2_S_ENA_MASK) >> | |
621 | GEN8_F2_S_ENA_SHIFT; | |
622 | ss_disable = (fuse2 & GEN9_F2_SS_DIS_MASK) >> | |
623 | GEN9_F2_SS_DIS_SHIFT; | |
624 | ||
9705ad8a JM |
625 | info->slice_total = hweight32(s_enable); |
626 | /* | |
627 | * The subslice disable field is global, i.e. it applies | |
628 | * to each of the enabled slices. | |
629 | */ | |
630 | info->subslice_per_slice = ss_max - hweight32(ss_disable); | |
631 | info->subslice_total = info->slice_total * | |
632 | info->subslice_per_slice; | |
633 | ||
634 | /* | |
635 | * Iterate through enabled slices and subslices to | |
636 | * count the total enabled EU. | |
637 | */ | |
638 | for (s = 0; s < s_max; s++) { | |
639 | if (!(s_enable & (0x1 << s))) | |
640 | /* skip disabled slice */ | |
641 | continue; | |
642 | ||
dead16e2 | 643 | eu_disable = I915_READ(GEN9_EU_DISABLE(s)); |
9705ad8a | 644 | for (ss = 0; ss < ss_max; ss++) { |
dead16e2 | 645 | int eu_per_ss; |
9705ad8a JM |
646 | |
647 | if (ss_disable & (0x1 << ss)) | |
648 | /* skip disabled subslice */ | |
649 | continue; | |
650 | ||
dead16e2 JM |
651 | eu_per_ss = eu_max - hweight8((eu_disable >> (ss*8)) & |
652 | eu_mask); | |
9705ad8a JM |
653 | |
654 | /* | |
655 | * Record which subslice(s) has(have) 7 EUs. we | |
656 | * can tune the hash used to spread work among | |
657 | * subslices if they are unbalanced. | |
658 | */ | |
dead16e2 | 659 | if (eu_per_ss == 7) |
9705ad8a JM |
660 | info->subslice_7eu[s] |= 1 << ss; |
661 | ||
dead16e2 | 662 | info->eu_total += eu_per_ss; |
9705ad8a JM |
663 | } |
664 | } | |
665 | ||
666 | /* | |
667 | * SKL is expected to always have a uniform distribution | |
668 | * of EU across subslices with the exception that any one | |
669 | * EU in any one subslice may be fused off for die | |
dead16e2 JM |
670 | * recovery. BXT is expected to be perfectly uniform in EU |
671 | * distribution. | |
9705ad8a JM |
672 | */ |
673 | info->eu_per_subslice = info->subslice_total ? | |
674 | DIV_ROUND_UP(info->eu_total, | |
675 | info->subslice_total) : 0; | |
676 | /* | |
677 | * SKL supports slice power gating on devices with more than | |
678 | * one slice, and supports EU power gating on devices with | |
dead16e2 JM |
679 | * more than one EU pair per subslice. BXT supports subslice |
680 | * power gating on devices with more than one subslice, and | |
681 | * supports EU power gating on devices with more than one EU | |
682 | * pair per subslice. | |
9705ad8a | 683 | */ |
ef11bdb3 RV |
684 | info->has_slice_pg = ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) && |
685 | (info->slice_total > 1)); | |
dead16e2 JM |
686 | info->has_subslice_pg = (IS_BROXTON(dev) && (info->subslice_total > 1)); |
687 | info->has_eu_pg = (info->eu_per_subslice > 2); | |
9705ad8a JM |
688 | } |
689 | ||
91bedd34 ŁD |
690 | static void broadwell_sseu_info_init(struct drm_device *dev) |
691 | { | |
692 | struct drm_i915_private *dev_priv = dev->dev_private; | |
693 | struct intel_device_info *info; | |
694 | const int s_max = 3, ss_max = 3, eu_max = 8; | |
695 | int s, ss; | |
696 | u32 fuse2, eu_disable[s_max], s_enable, ss_disable; | |
697 | ||
698 | fuse2 = I915_READ(GEN8_FUSE2); | |
699 | s_enable = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT; | |
700 | ss_disable = (fuse2 & GEN8_F2_SS_DIS_MASK) >> GEN8_F2_SS_DIS_SHIFT; | |
701 | ||
702 | eu_disable[0] = I915_READ(GEN8_EU_DISABLE0) & GEN8_EU_DIS0_S0_MASK; | |
703 | eu_disable[1] = (I915_READ(GEN8_EU_DISABLE0) >> GEN8_EU_DIS0_S1_SHIFT) | | |
704 | ((I915_READ(GEN8_EU_DISABLE1) & GEN8_EU_DIS1_S1_MASK) << | |
705 | (32 - GEN8_EU_DIS0_S1_SHIFT)); | |
706 | eu_disable[2] = (I915_READ(GEN8_EU_DISABLE1) >> GEN8_EU_DIS1_S2_SHIFT) | | |
707 | ((I915_READ(GEN8_EU_DISABLE2) & GEN8_EU_DIS2_S2_MASK) << | |
708 | (32 - GEN8_EU_DIS1_S2_SHIFT)); | |
709 | ||
710 | ||
711 | info = (struct intel_device_info *)&dev_priv->info; | |
712 | info->slice_total = hweight32(s_enable); | |
713 | ||
714 | /* | |
715 | * The subslice disable field is global, i.e. it applies | |
716 | * to each of the enabled slices. | |
717 | */ | |
718 | info->subslice_per_slice = ss_max - hweight32(ss_disable); | |
719 | info->subslice_total = info->slice_total * info->subslice_per_slice; | |
720 | ||
721 | /* | |
722 | * Iterate through enabled slices and subslices to | |
723 | * count the total enabled EU. | |
724 | */ | |
725 | for (s = 0; s < s_max; s++) { | |
726 | if (!(s_enable & (0x1 << s))) | |
727 | /* skip disabled slice */ | |
728 | continue; | |
729 | ||
730 | for (ss = 0; ss < ss_max; ss++) { | |
731 | u32 n_disabled; | |
732 | ||
733 | if (ss_disable & (0x1 << ss)) | |
734 | /* skip disabled subslice */ | |
735 | continue; | |
736 | ||
737 | n_disabled = hweight8(eu_disable[s] >> (ss * eu_max)); | |
738 | ||
739 | /* | |
740 | * Record which subslices have 7 EUs. | |
741 | */ | |
742 | if (eu_max - n_disabled == 7) | |
743 | info->subslice_7eu[s] |= 1 << ss; | |
744 | ||
745 | info->eu_total += eu_max - n_disabled; | |
746 | } | |
747 | } | |
748 | ||
749 | /* | |
750 | * BDW is expected to always have a uniform distribution of EU across | |
751 | * subslices with the exception that any one EU in any one subslice may | |
752 | * be fused off for die recovery. | |
753 | */ | |
754 | info->eu_per_subslice = info->subslice_total ? | |
755 | DIV_ROUND_UP(info->eu_total, info->subslice_total) : 0; | |
756 | ||
757 | /* | |
758 | * BDW supports slice power gating on devices with more than | |
759 | * one slice. | |
760 | */ | |
761 | info->has_slice_pg = (info->slice_total > 1); | |
762 | info->has_subslice_pg = 0; | |
763 | info->has_eu_pg = 0; | |
764 | } | |
765 | ||
22d3fd46 DL |
766 | /* |
767 | * Determine various intel_device_info fields at runtime. | |
768 | * | |
769 | * Use it when either: | |
770 | * - it's judged too laborious to fill n static structures with the limit | |
771 | * when a simple if statement does the job, | |
772 | * - run-time checks (eg read fuse/strap registers) are needed. | |
658ac4c6 DL |
773 | * |
774 | * This function needs to be called: | |
775 | * - after the MMIO has been setup as we are reading registers, | |
776 | * - after the PCH has been detected, | |
777 | * - before the first usage of the fields it can tweak. | |
22d3fd46 DL |
778 | */ |
779 | static void intel_device_info_runtime_init(struct drm_device *dev) | |
780 | { | |
658ac4c6 | 781 | struct drm_i915_private *dev_priv = dev->dev_private; |
22d3fd46 | 782 | struct intel_device_info *info; |
d615a166 | 783 | enum pipe pipe; |
22d3fd46 | 784 | |
658ac4c6 | 785 | info = (struct intel_device_info *)&dev_priv->info; |
22d3fd46 | 786 | |
edd43ed8 DL |
787 | /* |
788 | * Skylake and Broxton currently don't expose the topmost plane as its | |
789 | * use is exclusive with the legacy cursor and we only want to expose | |
790 | * one of those, not both. Until we can safely expose the topmost plane | |
791 | * as a DRM_PLANE_TYPE_CURSOR with all the features exposed/supported, | |
792 | * we don't expose the topmost plane at all to prevent ABI breakage | |
793 | * down the line. | |
794 | */ | |
8fb9397d | 795 | if (IS_BROXTON(dev)) { |
edd43ed8 DL |
796 | info->num_sprites[PIPE_A] = 2; |
797 | info->num_sprites[PIPE_B] = 2; | |
798 | info->num_sprites[PIPE_C] = 1; | |
666a4537 | 799 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
055e393f | 800 | for_each_pipe(dev_priv, pipe) |
d615a166 DL |
801 | info->num_sprites[pipe] = 2; |
802 | else | |
055e393f | 803 | for_each_pipe(dev_priv, pipe) |
d615a166 | 804 | info->num_sprites[pipe] = 1; |
658ac4c6 | 805 | |
a0bae57f DL |
806 | if (i915.disable_display) { |
807 | DRM_INFO("Display disabled (module parameter)\n"); | |
808 | info->num_pipes = 0; | |
809 | } else if (info->num_pipes > 0 && | |
810 | (INTEL_INFO(dev)->gen == 7 || INTEL_INFO(dev)->gen == 8) && | |
a7e478c7 | 811 | HAS_PCH_SPLIT(dev)) { |
658ac4c6 DL |
812 | u32 fuse_strap = I915_READ(FUSE_STRAP); |
813 | u32 sfuse_strap = I915_READ(SFUSE_STRAP); | |
814 | ||
815 | /* | |
816 | * SFUSE_STRAP is supposed to have a bit signalling the display | |
817 | * is fused off. Unfortunately it seems that, at least in | |
818 | * certain cases, fused off display means that PCH display | |
819 | * reads don't land anywhere. In that case, we read 0s. | |
820 | * | |
821 | * On CPT/PPT, we can detect this case as SFUSE_STRAP_FUSE_LOCK | |
822 | * should be set when taking over after the firmware. | |
823 | */ | |
824 | if (fuse_strap & ILK_INTERNAL_DISPLAY_DISABLE || | |
825 | sfuse_strap & SFUSE_STRAP_DISPLAY_DISABLED || | |
826 | (dev_priv->pch_type == PCH_CPT && | |
827 | !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) { | |
828 | DRM_INFO("Display fused off, disabling\n"); | |
829 | info->num_pipes = 0; | |
8c448cad GF |
830 | } else if (fuse_strap & IVB_PIPE_C_DISABLE) { |
831 | DRM_INFO("PipeC fused off\n"); | |
832 | info->num_pipes -= 1; | |
658ac4c6 | 833 | } |
bf4f2fb0 PJ |
834 | } else if (info->num_pipes > 0 && INTEL_INFO(dev)->gen == 9) { |
835 | u32 dfsm = I915_READ(SKL_DFSM); | |
836 | u8 disabled_mask = 0; | |
837 | bool invalid; | |
838 | int num_bits; | |
839 | ||
840 | if (dfsm & SKL_DFSM_PIPE_A_DISABLE) | |
841 | disabled_mask |= BIT(PIPE_A); | |
842 | if (dfsm & SKL_DFSM_PIPE_B_DISABLE) | |
843 | disabled_mask |= BIT(PIPE_B); | |
844 | if (dfsm & SKL_DFSM_PIPE_C_DISABLE) | |
845 | disabled_mask |= BIT(PIPE_C); | |
846 | ||
847 | num_bits = hweight8(disabled_mask); | |
848 | ||
849 | switch (disabled_mask) { | |
850 | case BIT(PIPE_A): | |
851 | case BIT(PIPE_B): | |
852 | case BIT(PIPE_A) | BIT(PIPE_B): | |
853 | case BIT(PIPE_A) | BIT(PIPE_C): | |
854 | invalid = true; | |
855 | break; | |
856 | default: | |
857 | invalid = false; | |
858 | } | |
859 | ||
860 | if (num_bits > info->num_pipes || invalid) | |
861 | DRM_ERROR("invalid pipe fuse configuration: 0x%x\n", | |
862 | disabled_mask); | |
863 | else | |
864 | info->num_pipes -= num_bits; | |
658ac4c6 | 865 | } |
693d11c3 | 866 | |
3873218f | 867 | /* Initialize slice/subslice/EU info */ |
9705ad8a JM |
868 | if (IS_CHERRYVIEW(dev)) |
869 | cherryview_sseu_info_init(dev); | |
91bedd34 ŁD |
870 | else if (IS_BROADWELL(dev)) |
871 | broadwell_sseu_info_init(dev); | |
dead16e2 | 872 | else if (INTEL_INFO(dev)->gen >= 9) |
9705ad8a | 873 | gen9_sseu_info_init(dev); |
3873218f | 874 | |
ca377809 TU |
875 | /* Snooping is broken on BXT A stepping. */ |
876 | info->has_snoop = !info->has_llc; | |
877 | info->has_snoop &= !IS_BXT_REVID(dev, 0, BXT_REVID_A1); | |
878 | ||
3873218f JM |
879 | DRM_DEBUG_DRIVER("slice total: %u\n", info->slice_total); |
880 | DRM_DEBUG_DRIVER("subslice total: %u\n", info->subslice_total); | |
881 | DRM_DEBUG_DRIVER("subslice per slice: %u\n", info->subslice_per_slice); | |
882 | DRM_DEBUG_DRIVER("EU total: %u\n", info->eu_total); | |
883 | DRM_DEBUG_DRIVER("EU per subslice: %u\n", info->eu_per_subslice); | |
884 | DRM_DEBUG_DRIVER("has slice power gating: %s\n", | |
885 | info->has_slice_pg ? "y" : "n"); | |
886 | DRM_DEBUG_DRIVER("has subslice power gating: %s\n", | |
887 | info->has_subslice_pg ? "y" : "n"); | |
888 | DRM_DEBUG_DRIVER("has EU power gating: %s\n", | |
889 | info->has_eu_pg ? "y" : "n"); | |
22d3fd46 DL |
890 | } |
891 | ||
e27f299e VS |
892 | static void intel_init_dpio(struct drm_i915_private *dev_priv) |
893 | { | |
e27f299e VS |
894 | /* |
895 | * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C), | |
896 | * CHV x1 PHY (DP/HDMI D) | |
897 | * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C) | |
898 | */ | |
899 | if (IS_CHERRYVIEW(dev_priv)) { | |
900 | DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2; | |
901 | DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO; | |
666a4537 | 902 | } else if (IS_VALLEYVIEW(dev_priv)) { |
e27f299e VS |
903 | DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO; |
904 | } | |
905 | } | |
906 | ||
399bb5b6 ID |
907 | static int i915_workqueues_init(struct drm_i915_private *dev_priv) |
908 | { | |
909 | /* | |
910 | * The i915 workqueue is primarily used for batched retirement of | |
911 | * requests (and thus managing bo) once the task has been completed | |
912 | * by the GPU. i915_gem_retire_requests() is called directly when we | |
913 | * need high-priority retirement, such as waiting for an explicit | |
914 | * bo. | |
915 | * | |
916 | * It is also used for periodic low-priority events, such as | |
917 | * idle-timers and recording error state. | |
918 | * | |
919 | * All tasks on the workqueue are expected to acquire the dev mutex | |
920 | * so there is no point in running more than one instance of the | |
921 | * workqueue at any time. Use an ordered one. | |
922 | */ | |
923 | dev_priv->wq = alloc_ordered_workqueue("i915", 0); | |
924 | if (dev_priv->wq == NULL) | |
925 | goto out_err; | |
926 | ||
927 | dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0); | |
928 | if (dev_priv->hotplug.dp_wq == NULL) | |
929 | goto out_free_wq; | |
930 | ||
931 | dev_priv->gpu_error.hangcheck_wq = | |
932 | alloc_ordered_workqueue("i915-hangcheck", 0); | |
933 | if (dev_priv->gpu_error.hangcheck_wq == NULL) | |
934 | goto out_free_dp_wq; | |
935 | ||
936 | return 0; | |
937 | ||
938 | out_free_dp_wq: | |
939 | destroy_workqueue(dev_priv->hotplug.dp_wq); | |
940 | out_free_wq: | |
941 | destroy_workqueue(dev_priv->wq); | |
942 | out_err: | |
943 | DRM_ERROR("Failed to allocate workqueues.\n"); | |
944 | ||
945 | return -ENOMEM; | |
946 | } | |
947 | ||
948 | static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv) | |
949 | { | |
950 | destroy_workqueue(dev_priv->gpu_error.hangcheck_wq); | |
951 | destroy_workqueue(dev_priv->hotplug.dp_wq); | |
952 | destroy_workqueue(dev_priv->wq); | |
953 | } | |
954 | ||
5d7a6eef ID |
955 | /** |
956 | * i915_driver_init_early - setup state not requiring device access | |
957 | * @dev_priv: device private | |
958 | * | |
959 | * Initialize everything that is a "SW-only" state, that is state not | |
960 | * requiring accessing the device or exposing the driver via kernel internal | |
961 | * or userspace interfaces. Example steps belonging here: lock initialization, | |
962 | * system memory allocation, setting up device specific attributes and | |
963 | * function hooks not requiring accessing the device. | |
964 | */ | |
965 | static int i915_driver_init_early(struct drm_i915_private *dev_priv, | |
966 | struct drm_device *dev, | |
967 | struct intel_device_info *info) | |
968 | { | |
969 | struct intel_device_info *device_info; | |
970 | int ret = 0; | |
971 | ||
4fec15d1 ID |
972 | if (i915_inject_load_failure()) |
973 | return -ENODEV; | |
974 | ||
5d7a6eef ID |
975 | dev_priv->dev = dev; |
976 | ||
977 | /* Setup the write-once "constant" device info */ | |
978 | device_info = (struct intel_device_info *)&dev_priv->info; | |
979 | memcpy(device_info, info, sizeof(dev_priv->info)); | |
980 | device_info->device_id = dev->pdev->device; | |
981 | ||
982 | spin_lock_init(&dev_priv->irq_lock); | |
983 | spin_lock_init(&dev_priv->gpu_error.lock); | |
984 | mutex_init(&dev_priv->backlight_lock); | |
985 | spin_lock_init(&dev_priv->uncore.lock); | |
986 | spin_lock_init(&dev_priv->mm.object_stat_lock); | |
987 | spin_lock_init(&dev_priv->mmio_flip_lock); | |
988 | mutex_init(&dev_priv->sb_lock); | |
989 | mutex_init(&dev_priv->modeset_restore_lock); | |
990 | mutex_init(&dev_priv->av_mutex); | |
991 | mutex_init(&dev_priv->wm.wm_mutex); | |
992 | mutex_init(&dev_priv->pps_mutex); | |
993 | ||
994 | ret = i915_workqueues_init(dev_priv); | |
995 | if (ret < 0) | |
996 | return ret; | |
997 | ||
998 | /* This must be called before any calls to HAS_PCH_* */ | |
999 | intel_detect_pch(dev); | |
1000 | ||
1001 | intel_pm_setup(dev); | |
1002 | intel_init_dpio(dev_priv); | |
1003 | intel_power_domains_init(dev_priv); | |
1004 | intel_irq_init(dev_priv); | |
1005 | intel_init_display_hooks(dev_priv); | |
1006 | intel_init_clock_gating_hooks(dev_priv); | |
1007 | intel_init_audio_hooks(dev_priv); | |
1008 | i915_gem_load_init(dev); | |
1009 | ||
1010 | intel_display_crc_init(dev); | |
1011 | ||
1012 | i915_dump_device_info(dev_priv); | |
1013 | ||
1014 | /* Not all pre-production machines fall into this category, only the | |
1015 | * very first ones. Almost everything should work, except for maybe | |
1016 | * suspend/resume. And we don't implement workarounds that affect only | |
1017 | * pre-production machines. */ | |
1018 | if (IS_HSW_EARLY_SDV(dev)) | |
1019 | DRM_INFO("This is an early pre-production Haswell machine. " | |
1020 | "It may not be fully functional.\n"); | |
1021 | ||
1022 | return 0; | |
1023 | } | |
1024 | ||
1025 | /** | |
1026 | * i915_driver_cleanup_early - cleanup the setup done in i915_driver_init_early() | |
1027 | * @dev_priv: device private | |
1028 | */ | |
1029 | static void i915_driver_cleanup_early(struct drm_i915_private *dev_priv) | |
1030 | { | |
1031 | i915_gem_load_cleanup(dev_priv->dev); | |
1032 | i915_workqueues_cleanup(dev_priv); | |
1033 | } | |
1034 | ||
ad5c3d3f ID |
1035 | static int i915_mmio_setup(struct drm_device *dev) |
1036 | { | |
1037 | struct drm_i915_private *dev_priv = to_i915(dev); | |
1038 | int mmio_bar; | |
1039 | int mmio_size; | |
1040 | ||
1041 | mmio_bar = IS_GEN2(dev) ? 1 : 0; | |
1042 | /* | |
1043 | * Before gen4, the registers and the GTT are behind different BARs. | |
1044 | * However, from gen4 onwards, the registers and the GTT are shared | |
1045 | * in the same BAR, so we want to restrict this ioremap from | |
1046 | * clobbering the GTT which we want ioremap_wc instead. Fortunately, | |
1047 | * the register BAR remains the same size for all the earlier | |
1048 | * generations up to Ironlake. | |
1049 | */ | |
1050 | if (INTEL_INFO(dev)->gen < 5) | |
1051 | mmio_size = 512 * 1024; | |
1052 | else | |
1053 | mmio_size = 2 * 1024 * 1024; | |
1054 | dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, mmio_size); | |
1055 | if (dev_priv->regs == NULL) { | |
1056 | DRM_ERROR("failed to map registers\n"); | |
1057 | ||
1058 | return -EIO; | |
1059 | } | |
1060 | ||
1061 | /* Try to make sure MCHBAR is enabled before poking at it */ | |
1062 | intel_setup_mchbar(dev); | |
1063 | ||
1064 | return 0; | |
1065 | } | |
1066 | ||
1067 | static void i915_mmio_cleanup(struct drm_device *dev) | |
1068 | { | |
1069 | struct drm_i915_private *dev_priv = to_i915(dev); | |
1070 | ||
1071 | intel_teardown_mchbar(dev); | |
1072 | pci_iounmap(dev->pdev, dev_priv->regs); | |
1073 | } | |
1074 | ||
f28cea45 ID |
1075 | /** |
1076 | * i915_driver_init_mmio - setup device MMIO | |
1077 | * @dev_priv: device private | |
1078 | * | |
1079 | * Setup minimal device state necessary for MMIO accesses later in the | |
1080 | * initialization sequence. The setup here should avoid any other device-wide | |
1081 | * side effects or exposing the driver via kernel internal or user space | |
1082 | * interfaces. | |
1083 | */ | |
1084 | static int i915_driver_init_mmio(struct drm_i915_private *dev_priv) | |
1085 | { | |
1086 | struct drm_device *dev = dev_priv->dev; | |
1087 | int ret; | |
1088 | ||
4fec15d1 ID |
1089 | if (i915_inject_load_failure()) |
1090 | return -ENODEV; | |
1091 | ||
f28cea45 ID |
1092 | if (i915_get_bridge_dev(dev)) |
1093 | return -EIO; | |
1094 | ||
1095 | ret = i915_mmio_setup(dev); | |
1096 | if (ret < 0) | |
1097 | goto put_bridge; | |
1098 | ||
1099 | intel_uncore_init(dev); | |
1100 | ||
1101 | return 0; | |
1102 | ||
1103 | put_bridge: | |
1104 | pci_dev_put(dev_priv->bridge_dev); | |
1105 | ||
1106 | return ret; | |
1107 | } | |
1108 | ||
1109 | /** | |
1110 | * i915_driver_cleanup_mmio - cleanup the setup done in i915_driver_init_mmio() | |
1111 | * @dev_priv: device private | |
1112 | */ | |
1113 | static void i915_driver_cleanup_mmio(struct drm_i915_private *dev_priv) | |
1114 | { | |
1115 | struct drm_device *dev = dev_priv->dev; | |
1116 | ||
1117 | intel_uncore_fini(dev); | |
1118 | i915_mmio_cleanup(dev); | |
1119 | pci_dev_put(dev_priv->bridge_dev); | |
1120 | } | |
1121 | ||
79e53945 | 1122 | /** |
09cfcb45 ID |
1123 | * i915_driver_init_hw - setup state requiring device access |
1124 | * @dev_priv: device private | |
79e53945 | 1125 | * |
09cfcb45 ID |
1126 | * Setup state that requires accessing the device, but doesn't require |
1127 | * exposing the driver via kernel internal or userspace interfaces. | |
79e53945 | 1128 | */ |
09cfcb45 | 1129 | static int i915_driver_init_hw(struct drm_i915_private *dev_priv) |
22eae947 | 1130 | { |
09cfcb45 | 1131 | struct drm_device *dev = dev_priv->dev; |
9021f284 | 1132 | uint32_t aperture_size; |
09cfcb45 | 1133 | int ret; |
c3d685a7 | 1134 | |
4fec15d1 ID |
1135 | if (i915_inject_load_failure()) |
1136 | return -ENODEV; | |
1137 | ||
13c8f4c8 ID |
1138 | intel_device_info_runtime_init(dev); |
1139 | ||
e76e9aeb BW |
1140 | ret = i915_gem_gtt_init(dev); |
1141 | if (ret) | |
09cfcb45 | 1142 | return ret; |
e188719a | 1143 | |
17fa6463 DV |
1144 | /* WARNING: Apparently we must kick fbdev drivers before vgacon, |
1145 | * otherwise the vga fbdev driver falls over. */ | |
1146 | ret = i915_kick_out_firmware_fb(dev_priv); | |
1147 | if (ret) { | |
1148 | DRM_ERROR("failed to remove conflicting framebuffer drivers\n"); | |
1149 | goto out_gtt; | |
1150 | } | |
a4de0526 | 1151 | |
17fa6463 DV |
1152 | ret = i915_kick_out_vgacon(dev_priv); |
1153 | if (ret) { | |
1154 | DRM_ERROR("failed to remove conflicting VGA console\n"); | |
1155 | goto out_gtt; | |
a4de0526 | 1156 | } |
e188719a | 1157 | |
466e69b8 DA |
1158 | pci_set_master(dev->pdev); |
1159 | ||
9f82d238 DV |
1160 | /* overlay on gen2 is broken and can't address above 1G */ |
1161 | if (IS_GEN2(dev)) | |
1162 | dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30)); | |
1163 | ||
6927faf3 JN |
1164 | /* 965GM sometimes incorrectly writes to hardware status page (HWS) |
1165 | * using 32bit addressing, overwriting memory if HWS is located | |
1166 | * above 4GB. | |
1167 | * | |
1168 | * The documentation also mentions an issue with undefined | |
1169 | * behaviour if any general state is accessed within a page above 4GB, | |
1170 | * which also needs to be handled carefully. | |
1171 | */ | |
1172 | if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) | |
1173 | dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(32)); | |
1174 | ||
62106b4f | 1175 | aperture_size = dev_priv->ggtt.mappable_end; |
71e9339c | 1176 | |
62106b4f JL |
1177 | dev_priv->ggtt.mappable = |
1178 | io_mapping_create_wc(dev_priv->ggtt.mappable_base, | |
dd2757f8 | 1179 | aperture_size); |
62106b4f | 1180 | if (dev_priv->ggtt.mappable == NULL) { |
6644107d | 1181 | ret = -EIO; |
cbb47d17 | 1182 | goto out_gtt; |
6644107d VP |
1183 | } |
1184 | ||
62106b4f | 1185 | dev_priv->ggtt.mtrr = arch_phys_wc_add(dev_priv->ggtt.mappable_base, |
911bdf0a | 1186 | aperture_size); |
19966754 | 1187 | |
bd39ec5d ID |
1188 | pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, |
1189 | PM_QOS_DEFAULT_VALUE); | |
1190 | ||
78511f2a | 1191 | intel_uncore_sanitize(dev); |
9880b7a5 | 1192 | |
44834a67 | 1193 | intel_opregion_setup(dev); |
c4804411 | 1194 | |
40ae4e16 ID |
1195 | i915_gem_load_init_fences(dev_priv); |
1196 | ||
ed4cb414 EA |
1197 | /* On the 945G/GM, the chipset reports the MSI capability on the |
1198 | * integrated graphics even though the support isn't actually there | |
1199 | * according to the published specs. It doesn't appear to function | |
1200 | * correctly in testing on 945G. | |
1201 | * This may be a side effect of MSI having been made available for PEG | |
1202 | * and the registers being closely associated. | |
d1ed629f KP |
1203 | * |
1204 | * According to chipset errata, on the 965GM, MSI interrupts may | |
b60678a7 KP |
1205 | * be lost or delayed, but we use them anyways to avoid |
1206 | * stuck interrupts on some machines. | |
ed4cb414 | 1207 | */ |
b074eae1 ID |
1208 | if (!IS_I945G(dev) && !IS_I945GM(dev)) { |
1209 | if (pci_enable_msi(dev->pdev) < 0) | |
1210 | DRM_DEBUG_DRIVER("can't enable MSI"); | |
1211 | } | |
ed4cb414 | 1212 | |
09cfcb45 ID |
1213 | return 0; |
1214 | ||
1215 | out_gtt: | |
1216 | i915_global_gtt_cleanup(dev); | |
1217 | ||
1218 | return ret; | |
1219 | } | |
1220 | ||
1221 | /** | |
1222 | * i915_driver_cleanup_hw - cleanup the setup done in i915_driver_init_hw() | |
1223 | * @dev_priv: device private | |
1224 | */ | |
1225 | static void i915_driver_cleanup_hw(struct drm_i915_private *dev_priv) | |
1226 | { | |
1227 | struct drm_device *dev = dev_priv->dev; | |
1228 | ||
1229 | if (dev->pdev->msi_enabled) | |
1230 | pci_disable_msi(dev->pdev); | |
1231 | ||
1232 | pm_qos_remove_request(&dev_priv->pm_qos); | |
62106b4f JL |
1233 | arch_phys_wc_del(dev_priv->ggtt.mtrr); |
1234 | io_mapping_free(dev_priv->ggtt.mappable); | |
09cfcb45 ID |
1235 | i915_global_gtt_cleanup(dev); |
1236 | } | |
1237 | ||
432f856d ID |
1238 | /** |
1239 | * i915_driver_register - register the driver with the rest of the system | |
1240 | * @dev_priv: device private | |
1241 | * | |
1242 | * Perform any steps necessary to make the driver available via kernel | |
1243 | * internal or userspace interfaces. | |
1244 | */ | |
1245 | static void i915_driver_register(struct drm_i915_private *dev_priv) | |
1246 | { | |
1247 | struct drm_device *dev = dev_priv->dev; | |
1248 | ||
1249 | i915_gem_shrinker_init(dev_priv); | |
1250 | /* | |
1251 | * Notify a valid surface after modesetting, | |
1252 | * when running inside a VM. | |
1253 | */ | |
1254 | if (intel_vgpu_active(dev)) | |
1255 | I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY); | |
1256 | ||
1257 | i915_setup_sysfs(dev); | |
1258 | ||
1259 | if (INTEL_INFO(dev_priv)->num_pipes) { | |
1260 | /* Must be done after probing outputs */ | |
1261 | intel_opregion_init(dev); | |
1262 | acpi_video_register(); | |
1263 | } | |
1264 | ||
1265 | if (IS_GEN5(dev_priv)) | |
1266 | intel_gpu_ips_init(dev_priv); | |
1267 | ||
1268 | i915_audio_component_init(dev_priv); | |
1269 | } | |
1270 | ||
1271 | /** | |
1272 | * i915_driver_unregister - cleanup the registration done in i915_driver_regiser() | |
1273 | * @dev_priv: device private | |
1274 | */ | |
1275 | static void i915_driver_unregister(struct drm_i915_private *dev_priv) | |
1276 | { | |
1277 | i915_audio_component_cleanup(dev_priv); | |
1278 | intel_gpu_ips_teardown(); | |
1279 | acpi_video_unregister(); | |
1280 | intel_opregion_fini(dev_priv->dev); | |
1281 | i915_teardown_sysfs(dev_priv->dev); | |
1282 | i915_gem_shrinker_cleanup(dev_priv); | |
1283 | } | |
1284 | ||
09cfcb45 ID |
1285 | /** |
1286 | * i915_driver_load - setup chip and create an initial config | |
1287 | * @dev: DRM device | |
1288 | * @flags: startup flags | |
1289 | * | |
1290 | * The driver load routine has to do several things: | |
1291 | * - drive output discovery via intel_modeset_init() | |
1292 | * - initialize the memory manager | |
1293 | * - allocate initial config memory | |
1294 | * - setup the DRM framebuffer with the allocated memory | |
1295 | */ | |
1296 | int i915_driver_load(struct drm_device *dev, unsigned long flags) | |
1297 | { | |
1298 | struct drm_i915_private *dev_priv; | |
1299 | int ret = 0; | |
1300 | ||
1301 | dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL); | |
1302 | if (dev_priv == NULL) | |
1303 | return -ENOMEM; | |
1304 | ||
1305 | dev->dev_private = dev_priv; | |
1306 | ||
1307 | ret = i915_driver_init_early(dev_priv, dev, | |
1308 | (struct intel_device_info *)flags); | |
1309 | ||
1310 | if (ret < 0) | |
1311 | goto out_free_priv; | |
1312 | ||
1313 | intel_runtime_pm_get(dev_priv); | |
1314 | ||
1315 | ret = i915_driver_init_mmio(dev_priv); | |
1316 | if (ret < 0) | |
1317 | goto out_runtime_pm_put; | |
1318 | ||
1319 | ret = i915_driver_init_hw(dev_priv); | |
1320 | if (ret < 0) | |
1321 | goto out_cleanup_mmio; | |
1322 | ||
432f856d ID |
1323 | /* |
1324 | * TODO: move the vblank init and parts of modeset init steps into one | |
1325 | * of the i915_driver_init_/i915_driver_register functions according | |
1326 | * to the role/effect of the given init step. | |
1327 | */ | |
e3c74757 BW |
1328 | if (INTEL_INFO(dev)->num_pipes) { |
1329 | ret = drm_vblank_init(dev, INTEL_INFO(dev)->num_pipes); | |
1330 | if (ret) | |
09cfcb45 | 1331 | goto out_cleanup_hw; |
e3c74757 | 1332 | } |
52440211 | 1333 | |
17fa6463 DV |
1334 | ret = i915_load_modeset_init(dev); |
1335 | if (ret < 0) { | |
1336 | DRM_ERROR("failed to init modeset\n"); | |
65ff442f | 1337 | goto out_cleanup_vblank; |
79e53945 JB |
1338 | } |
1339 | ||
432f856d | 1340 | i915_driver_register(dev_priv); |
58fddc28 | 1341 | |
3487b66b ID |
1342 | intel_runtime_pm_enable(dev_priv); |
1343 | ||
1f814dac ID |
1344 | intel_runtime_pm_put(dev_priv); |
1345 | ||
79e53945 JB |
1346 | return 0; |
1347 | ||
65ff442f | 1348 | out_cleanup_vblank: |
cbb47d17 | 1349 | drm_vblank_cleanup(dev); |
09cfcb45 ID |
1350 | out_cleanup_hw: |
1351 | i915_driver_cleanup_hw(dev_priv); | |
f28cea45 ID |
1352 | out_cleanup_mmio: |
1353 | i915_driver_cleanup_mmio(dev_priv); | |
02036cee | 1354 | out_runtime_pm_put: |
1f814dac | 1355 | intel_runtime_pm_put(dev_priv); |
5d7a6eef | 1356 | i915_driver_cleanup_early(dev_priv); |
399bb5b6 | 1357 | out_free_priv: |
9a298b2a | 1358 | kfree(dev_priv); |
399bb5b6 | 1359 | |
ba8bbcf6 JB |
1360 | return ret; |
1361 | } | |
1362 | ||
1363 | int i915_driver_unload(struct drm_device *dev) | |
1364 | { | |
1365 | struct drm_i915_private *dev_priv = dev->dev_private; | |
c911fc1c | 1366 | int ret; |
ba8bbcf6 | 1367 | |
2013bfc0 VS |
1368 | intel_fbdev_fini(dev); |
1369 | ||
ce58c32b CW |
1370 | ret = i915_gem_suspend(dev); |
1371 | if (ret) { | |
1372 | DRM_ERROR("failed to idle hardware: %d\n", ret); | |
1373 | return ret; | |
1374 | } | |
1375 | ||
250ad48e | 1376 | intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); |
8a187455 | 1377 | |
432f856d | 1378 | i915_driver_unregister(dev_priv); |
44834a67 | 1379 | |
2ebfaf5f PZ |
1380 | drm_vblank_cleanup(dev); |
1381 | ||
17fa6463 | 1382 | intel_modeset_cleanup(dev); |
6c0d9350 | 1383 | |
17fa6463 DV |
1384 | /* |
1385 | * free the memory space allocated for the child device | |
1386 | * config parsed from VBT | |
1387 | */ | |
1388 | if (dev_priv->vbt.child_dev && dev_priv->vbt.child_dev_num) { | |
1389 | kfree(dev_priv->vbt.child_dev); | |
1390 | dev_priv->vbt.child_dev = NULL; | |
1391 | dev_priv->vbt.child_dev_num = 0; | |
79e53945 | 1392 | } |
9aa61142 MR |
1393 | kfree(dev_priv->vbt.sdvo_lvds_vbt_mode); |
1394 | dev_priv->vbt.sdvo_lvds_vbt_mode = NULL; | |
1395 | kfree(dev_priv->vbt.lfp_lvds_vbt_mode); | |
1396 | dev_priv->vbt.lfp_lvds_vbt_mode = NULL; | |
79e53945 | 1397 | |
17fa6463 DV |
1398 | vga_switcheroo_unregister_client(dev->pdev); |
1399 | vga_client_register(dev->pdev, NULL, NULL, NULL); | |
1400 | ||
89250fec ID |
1401 | intel_csr_ucode_fini(dev_priv); |
1402 | ||
a8b4899e | 1403 | /* Free error state after interrupts are fully disabled. */ |
737b1506 | 1404 | cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work); |
a8b4899e | 1405 | i915_destroy_error_state(dev); |
bc0c7f14 | 1406 | |
17fa6463 DV |
1407 | /* Flush any outstanding unpin_work. */ |
1408 | flush_workqueue(dev_priv->wq); | |
67e77c5a | 1409 | |
33a732f4 | 1410 | intel_guc_ucode_fini(dev); |
bf248ca1 | 1411 | mutex_lock(&dev->struct_mutex); |
117897f4 | 1412 | i915_gem_cleanup_engines(dev); |
17fa6463 DV |
1413 | i915_gem_context_fini(dev); |
1414 | mutex_unlock(&dev->struct_mutex); | |
7733b49b | 1415 | intel_fbc_cleanup_cfb(dev_priv); |
79e53945 | 1416 | |
250ad48e ID |
1417 | intel_power_domains_fini(dev_priv); |
1418 | ||
09cfcb45 | 1419 | i915_driver_cleanup_hw(dev_priv); |
f28cea45 | 1420 | i915_driver_cleanup_mmio(dev_priv); |
250ad48e ID |
1421 | |
1422 | intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); | |
1423 | ||
5d7a6eef | 1424 | i915_driver_cleanup_early(dev_priv); |
2206e6a1 | 1425 | kfree(dev_priv); |
ba8bbcf6 | 1426 | |
22eae947 DA |
1427 | return 0; |
1428 | } | |
1429 | ||
f787a5f5 | 1430 | int i915_driver_open(struct drm_device *dev, struct drm_file *file) |
673a394b | 1431 | { |
b29c19b6 | 1432 | int ret; |
673a394b | 1433 | |
b29c19b6 CW |
1434 | ret = i915_gem_open(dev, file); |
1435 | if (ret) | |
1436 | return ret; | |
254f965c | 1437 | |
673a394b EA |
1438 | return 0; |
1439 | } | |
1440 | ||
79e53945 JB |
1441 | /** |
1442 | * i915_driver_lastclose - clean up after all DRM clients have exited | |
1443 | * @dev: DRM device | |
1444 | * | |
1445 | * Take care of cleaning up after all DRM clients have exited. In the | |
1446 | * mode setting case, we want to restore the kernel's initial mode (just | |
1447 | * in case the last client left us in a bad state). | |
1448 | * | |
9021f284 | 1449 | * Additionally, in the non-mode setting case, we'll tear down the GTT |
79e53945 JB |
1450 | * and DMA structures, since the kernel won't be using them, and clea |
1451 | * up any GEM state. | |
1452 | */ | |
1a5036bf | 1453 | void i915_driver_lastclose(struct drm_device *dev) |
1da177e4 | 1454 | { |
377e91b2 DV |
1455 | intel_fbdev_restore_mode(dev); |
1456 | vga_switcheroo_process_delayed_switch(); | |
1da177e4 LT |
1457 | } |
1458 | ||
2885f6ac | 1459 | void i915_driver_preclose(struct drm_device *dev, struct drm_file *file) |
1da177e4 | 1460 | { |
0d1430a3 | 1461 | mutex_lock(&dev->struct_mutex); |
2885f6ac JH |
1462 | i915_gem_context_close(dev, file); |
1463 | i915_gem_release(dev, file); | |
0d1430a3 | 1464 | mutex_unlock(&dev->struct_mutex); |
1da177e4 LT |
1465 | } |
1466 | ||
f787a5f5 | 1467 | void i915_driver_postclose(struct drm_device *dev, struct drm_file *file) |
673a394b | 1468 | { |
f787a5f5 | 1469 | struct drm_i915_file_private *file_priv = file->driver_priv; |
673a394b | 1470 | |
f787a5f5 | 1471 | kfree(file_priv); |
673a394b EA |
1472 | } |
1473 | ||
4feb7659 DV |
1474 | static int |
1475 | i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data, | |
1476 | struct drm_file *file) | |
1477 | { | |
1478 | return -ENODEV; | |
1479 | } | |
1480 | ||
baa70943 | 1481 | const struct drm_ioctl_desc i915_ioctls[] = { |
77f31815 DV |
1482 | DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
1483 | DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH), | |
1484 | DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH), | |
1485 | DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH), | |
1486 | DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH), | |
1487 | DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH), | |
10ba5012 | 1488 | DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH|DRM_RENDER_ALLOW), |
c668cde5 | 1489 | DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
b2c606fe DV |
1490 | DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH), |
1491 | DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH), | |
1492 | DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
77f31815 | 1493 | DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH), |
b2c606fe | 1494 | DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
d1c1edbc | 1495 | DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
77f31815 DV |
1496 | DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, drm_noop, DRM_AUTH), |
1497 | DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH), | |
1498 | DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
f8c47144 DV |
1499 | DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
1500 | DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH), | |
1501 | DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_RENDER_ALLOW), | |
1502 | DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY), | |
1503 | DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY), | |
1504 | DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), | |
1505 | DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW), | |
1506 | DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW), | |
1507 | DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), | |
1508 | DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
1509 | DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
1510 | DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW), | |
1511 | DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW), | |
1512 | DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW), | |
1513 | DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW), | |
1514 | DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_RENDER_ALLOW), | |
1515 | DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW), | |
1516 | DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW), | |
1517 | DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_RENDER_ALLOW), | |
1518 | DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_RENDER_ALLOW), | |
1519 | DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW), | |
1520 | DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, 0), | |
1521 | DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW), | |
1522 | DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW), | |
1523 | DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW), | |
1524 | DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW), | |
1525 | DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER|DRM_CONTROL_ALLOW), | |
1526 | DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), | |
1527 | DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW), | |
1528 | DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW), | |
1529 | DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW), | |
1530 | DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_get_reset_stats_ioctl, DRM_RENDER_ALLOW), | |
1531 | DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW), | |
1532 | DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW), | |
1533 | DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW), | |
c94f7029 DA |
1534 | }; |
1535 | ||
f95aeb17 | 1536 | int i915_max_ioctl = ARRAY_SIZE(i915_ioctls); |