Commit | Line | Data |
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1da177e4 LT |
1 | /* i915_dma.c -- DMA support for the I915 -*- linux-c -*- |
2 | */ | |
0d6aa60b | 3 | /* |
1da177e4 LT |
4 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
5 | * All Rights Reserved. | |
bc54fd1a DA |
6 | * |
7 | * Permission is hereby granted, free of charge, to any person obtaining a | |
8 | * copy of this software and associated documentation files (the | |
9 | * "Software"), to deal in the Software without restriction, including | |
10 | * without limitation the rights to use, copy, modify, merge, publish, | |
11 | * distribute, sub license, and/or sell copies of the Software, and to | |
12 | * permit persons to whom the Software is furnished to do so, subject to | |
13 | * the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice (including the | |
16 | * next paragraph) shall be included in all copies or substantial portions | |
17 | * of the Software. | |
18 | * | |
19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
20 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
21 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
22 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
23 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
24 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
25 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
26 | * | |
0d6aa60b | 27 | */ |
1da177e4 | 28 | |
a70491cc JP |
29 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
30 | ||
1da177e4 LT |
31 | #include "drmP.h" |
32 | #include "drm.h" | |
79e53945 | 33 | #include "drm_crtc_helper.h" |
785b93ef | 34 | #include "drm_fb_helper.h" |
79e53945 | 35 | #include "intel_drv.h" |
1da177e4 LT |
36 | #include "i915_drm.h" |
37 | #include "i915_drv.h" | |
1c5d22f7 | 38 | #include "i915_trace.h" |
dcdb1674 | 39 | #include <linux/pci.h> |
28d52043 | 40 | #include <linux/vgaarb.h> |
c4804411 ZW |
41 | #include <linux/acpi.h> |
42 | #include <linux/pnp.h> | |
6a9ee8af | 43 | #include <linux/vga_switcheroo.h> |
5a0e3ad6 | 44 | #include <linux/slab.h> |
44834a67 | 45 | #include <acpi/video.h> |
9e984bc1 | 46 | #include <asm/pat.h> |
1da177e4 | 47 | |
09422b2e DV |
48 | #define LP_RING(d) (&((struct drm_i915_private *)(d))->ring[RCS]) |
49 | ||
50 | #define BEGIN_LP_RING(n) \ | |
51 | intel_ring_begin(LP_RING(dev_priv), (n)) | |
52 | ||
53 | #define OUT_RING(x) \ | |
54 | intel_ring_emit(LP_RING(dev_priv), x) | |
55 | ||
56 | #define ADVANCE_LP_RING() \ | |
57 | intel_ring_advance(LP_RING(dev_priv)) | |
58 | ||
59 | /** | |
60 | * Lock test for when it's just for synchronization of ring access. | |
61 | * | |
62 | * In that case, we don't need to do it when GEM is initialized as nobody else | |
63 | * has access to the ring. | |
64 | */ | |
65 | #define RING_LOCK_TEST_WITH_RETURN(dev, file) do { \ | |
66 | if (LP_RING(dev->dev_private)->obj == NULL) \ | |
67 | LOCK_TEST_WITH_RETURN(dev, file); \ | |
68 | } while (0) | |
69 | ||
316d3884 DV |
70 | static inline u32 |
71 | intel_read_legacy_status_page(struct drm_i915_private *dev_priv, int reg) | |
72 | { | |
73 | if (I915_NEED_GFX_HWS(dev_priv->dev)) | |
74 | return ioread32(dev_priv->dri1.gfx_hws_cpu_addr + reg); | |
75 | else | |
76 | return intel_read_status_page(LP_RING(dev_priv), reg); | |
77 | } | |
78 | ||
79 | #define READ_HWSP(dev_priv, reg) intel_read_legacy_status_page(dev_priv, reg) | |
09422b2e DV |
80 | #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX) |
81 | #define I915_BREADCRUMB_INDEX 0x21 | |
82 | ||
d05c617e DV |
83 | void i915_update_dri1_breadcrumb(struct drm_device *dev) |
84 | { | |
85 | drm_i915_private_t *dev_priv = dev->dev_private; | |
86 | struct drm_i915_master_private *master_priv; | |
87 | ||
88 | if (dev->primary->master) { | |
89 | master_priv = dev->primary->master->driver_priv; | |
90 | if (master_priv->sarea_priv) | |
91 | master_priv->sarea_priv->last_dispatch = | |
92 | READ_BREADCRUMB(dev_priv); | |
93 | } | |
94 | } | |
95 | ||
4cbf74cc CW |
96 | static void i915_write_hws_pga(struct drm_device *dev) |
97 | { | |
98 | drm_i915_private_t *dev_priv = dev->dev_private; | |
99 | u32 addr; | |
100 | ||
101 | addr = dev_priv->status_page_dmah->busaddr; | |
102 | if (INTEL_INFO(dev)->gen >= 4) | |
103 | addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0; | |
104 | I915_WRITE(HWS_PGA, addr); | |
105 | } | |
106 | ||
398c9cb2 KP |
107 | /** |
108 | * Sets up the hardware status page for devices that need a physical address | |
109 | * in the register. | |
110 | */ | |
3043c60c | 111 | static int i915_init_phys_hws(struct drm_device *dev) |
398c9cb2 KP |
112 | { |
113 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1ec14ad3 | 114 | |
398c9cb2 KP |
115 | /* Program Hardware Status Page */ |
116 | dev_priv->status_page_dmah = | |
e6be8d9d | 117 | drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE); |
398c9cb2 KP |
118 | |
119 | if (!dev_priv->status_page_dmah) { | |
120 | DRM_ERROR("Can not allocate hardware status page\n"); | |
121 | return -ENOMEM; | |
122 | } | |
398c9cb2 | 123 | |
f3234706 KP |
124 | memset_io((void __force __iomem *)dev_priv->status_page_dmah->vaddr, |
125 | 0, PAGE_SIZE); | |
398c9cb2 | 126 | |
4cbf74cc | 127 | i915_write_hws_pga(dev); |
9b974cc1 | 128 | |
8a4c47f3 | 129 | DRM_DEBUG_DRIVER("Enabled hardware status page\n"); |
398c9cb2 KP |
130 | return 0; |
131 | } | |
132 | ||
133 | /** | |
134 | * Frees the hardware status page, whether it's a physical address or a virtual | |
135 | * address set up by the X Server. | |
136 | */ | |
3043c60c | 137 | static void i915_free_hws(struct drm_device *dev) |
398c9cb2 KP |
138 | { |
139 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1ec14ad3 CW |
140 | struct intel_ring_buffer *ring = LP_RING(dev_priv); |
141 | ||
398c9cb2 KP |
142 | if (dev_priv->status_page_dmah) { |
143 | drm_pci_free(dev, dev_priv->status_page_dmah); | |
144 | dev_priv->status_page_dmah = NULL; | |
145 | } | |
146 | ||
1ec14ad3 CW |
147 | if (ring->status_page.gfx_addr) { |
148 | ring->status_page.gfx_addr = 0; | |
316d3884 | 149 | iounmap(dev_priv->dri1.gfx_hws_cpu_addr); |
398c9cb2 KP |
150 | } |
151 | ||
152 | /* Need to rewrite hardware status page */ | |
153 | I915_WRITE(HWS_PGA, 0x1ffff000); | |
154 | } | |
155 | ||
84b1fd10 | 156 | void i915_kernel_lost_context(struct drm_device * dev) |
1da177e4 LT |
157 | { |
158 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7c1c2871 | 159 | struct drm_i915_master_private *master_priv; |
1ec14ad3 | 160 | struct intel_ring_buffer *ring = LP_RING(dev_priv); |
1da177e4 | 161 | |
79e53945 JB |
162 | /* |
163 | * We should never lose context on the ring with modesetting | |
164 | * as we don't expose it to userspace | |
165 | */ | |
166 | if (drm_core_check_feature(dev, DRIVER_MODESET)) | |
167 | return; | |
168 | ||
8168bd48 CW |
169 | ring->head = I915_READ_HEAD(ring) & HEAD_ADDR; |
170 | ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR; | |
1da177e4 LT |
171 | ring->space = ring->head - (ring->tail + 8); |
172 | if (ring->space < 0) | |
8187a2b7 | 173 | ring->space += ring->size; |
1da177e4 | 174 | |
7c1c2871 DA |
175 | if (!dev->primary->master) |
176 | return; | |
177 | ||
178 | master_priv = dev->primary->master->driver_priv; | |
179 | if (ring->head == ring->tail && master_priv->sarea_priv) | |
180 | master_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY; | |
1da177e4 LT |
181 | } |
182 | ||
84b1fd10 | 183 | static int i915_dma_cleanup(struct drm_device * dev) |
1da177e4 | 184 | { |
ba8bbcf6 | 185 | drm_i915_private_t *dev_priv = dev->dev_private; |
1ec14ad3 CW |
186 | int i; |
187 | ||
1da177e4 LT |
188 | /* Make sure interrupts are disabled here because the uninstall ioctl |
189 | * may not have been called from userspace and after dev_private | |
190 | * is freed, it's too late. | |
191 | */ | |
ed4cb414 | 192 | if (dev->irq_enabled) |
b5e89ed5 | 193 | drm_irq_uninstall(dev); |
1da177e4 | 194 | |
ee0c6bfb | 195 | mutex_lock(&dev->struct_mutex); |
1ec14ad3 CW |
196 | for (i = 0; i < I915_NUM_RINGS; i++) |
197 | intel_cleanup_ring_buffer(&dev_priv->ring[i]); | |
ee0c6bfb | 198 | mutex_unlock(&dev->struct_mutex); |
dc7a9319 | 199 | |
398c9cb2 KP |
200 | /* Clear the HWS virtual address at teardown */ |
201 | if (I915_NEED_GFX_HWS(dev)) | |
202 | i915_free_hws(dev); | |
1da177e4 LT |
203 | |
204 | return 0; | |
205 | } | |
206 | ||
ba8bbcf6 | 207 | static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init) |
1da177e4 | 208 | { |
ba8bbcf6 | 209 | drm_i915_private_t *dev_priv = dev->dev_private; |
7c1c2871 | 210 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
e8616b6c | 211 | int ret; |
1da177e4 | 212 | |
3a03ac1a DA |
213 | master_priv->sarea = drm_getsarea(dev); |
214 | if (master_priv->sarea) { | |
215 | master_priv->sarea_priv = (drm_i915_sarea_t *) | |
216 | ((u8 *)master_priv->sarea->handle + init->sarea_priv_offset); | |
217 | } else { | |
8a4c47f3 | 218 | DRM_DEBUG_DRIVER("sarea not found assuming DRI2 userspace\n"); |
3a03ac1a DA |
219 | } |
220 | ||
673a394b | 221 | if (init->ring_size != 0) { |
e8616b6c | 222 | if (LP_RING(dev_priv)->obj != NULL) { |
673a394b EA |
223 | i915_dma_cleanup(dev); |
224 | DRM_ERROR("Client tried to initialize ringbuffer in " | |
225 | "GEM mode\n"); | |
226 | return -EINVAL; | |
227 | } | |
1da177e4 | 228 | |
e8616b6c CW |
229 | ret = intel_render_ring_init_dri(dev, |
230 | init->ring_start, | |
231 | init->ring_size); | |
232 | if (ret) { | |
673a394b | 233 | i915_dma_cleanup(dev); |
e8616b6c | 234 | return ret; |
673a394b | 235 | } |
1da177e4 LT |
236 | } |
237 | ||
a6b54f3f | 238 | dev_priv->cpp = init->cpp; |
1da177e4 LT |
239 | dev_priv->back_offset = init->back_offset; |
240 | dev_priv->front_offset = init->front_offset; | |
241 | dev_priv->current_page = 0; | |
7c1c2871 DA |
242 | if (master_priv->sarea_priv) |
243 | master_priv->sarea_priv->pf_current_page = 0; | |
1da177e4 | 244 | |
1da177e4 LT |
245 | /* Allow hardware batchbuffers unless told otherwise. |
246 | */ | |
8781342d | 247 | dev_priv->dri1.allow_batchbuffer = 1; |
1da177e4 | 248 | |
1da177e4 LT |
249 | return 0; |
250 | } | |
251 | ||
84b1fd10 | 252 | static int i915_dma_resume(struct drm_device * dev) |
1da177e4 LT |
253 | { |
254 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
1ec14ad3 | 255 | struct intel_ring_buffer *ring = LP_RING(dev_priv); |
1da177e4 | 256 | |
8a4c47f3 | 257 | DRM_DEBUG_DRIVER("%s\n", __func__); |
1da177e4 | 258 | |
4225d0f2 | 259 | if (ring->virtual_start == NULL) { |
1da177e4 LT |
260 | DRM_ERROR("can not ioremap virtual address for" |
261 | " ring buffer\n"); | |
20caafa6 | 262 | return -ENOMEM; |
1da177e4 LT |
263 | } |
264 | ||
265 | /* Program Hardware Status Page */ | |
8187a2b7 | 266 | if (!ring->status_page.page_addr) { |
1da177e4 | 267 | DRM_ERROR("Can not find hardware status page\n"); |
20caafa6 | 268 | return -EINVAL; |
1da177e4 | 269 | } |
8a4c47f3 | 270 | DRM_DEBUG_DRIVER("hw status page @ %p\n", |
8187a2b7 ZN |
271 | ring->status_page.page_addr); |
272 | if (ring->status_page.gfx_addr != 0) | |
78501eac | 273 | intel_ring_setup_status_page(ring); |
dc7a9319 | 274 | else |
4cbf74cc | 275 | i915_write_hws_pga(dev); |
8187a2b7 | 276 | |
8a4c47f3 | 277 | DRM_DEBUG_DRIVER("Enabled hardware status page\n"); |
1da177e4 LT |
278 | |
279 | return 0; | |
280 | } | |
281 | ||
c153f45f EA |
282 | static int i915_dma_init(struct drm_device *dev, void *data, |
283 | struct drm_file *file_priv) | |
1da177e4 | 284 | { |
c153f45f | 285 | drm_i915_init_t *init = data; |
1da177e4 LT |
286 | int retcode = 0; |
287 | ||
cd9d4e9f DV |
288 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
289 | return -ENODEV; | |
290 | ||
c153f45f | 291 | switch (init->func) { |
1da177e4 | 292 | case I915_INIT_DMA: |
ba8bbcf6 | 293 | retcode = i915_initialize(dev, init); |
1da177e4 LT |
294 | break; |
295 | case I915_CLEANUP_DMA: | |
296 | retcode = i915_dma_cleanup(dev); | |
297 | break; | |
298 | case I915_RESUME_DMA: | |
0d6aa60b | 299 | retcode = i915_dma_resume(dev); |
1da177e4 LT |
300 | break; |
301 | default: | |
20caafa6 | 302 | retcode = -EINVAL; |
1da177e4 LT |
303 | break; |
304 | } | |
305 | ||
306 | return retcode; | |
307 | } | |
308 | ||
309 | /* Implement basically the same security restrictions as hardware does | |
310 | * for MI_BATCH_NON_SECURE. These can be made stricter at any time. | |
311 | * | |
312 | * Most of the calculations below involve calculating the size of a | |
313 | * particular instruction. It's important to get the size right as | |
314 | * that tells us where the next instruction to check is. Any illegal | |
315 | * instruction detected will be given a size of zero, which is a | |
316 | * signal to abort the rest of the buffer. | |
317 | */ | |
e1f99ce6 | 318 | static int validate_cmd(int cmd) |
1da177e4 LT |
319 | { |
320 | switch (((cmd >> 29) & 0x7)) { | |
321 | case 0x0: | |
322 | switch ((cmd >> 23) & 0x3f) { | |
323 | case 0x0: | |
324 | return 1; /* MI_NOOP */ | |
325 | case 0x4: | |
326 | return 1; /* MI_FLUSH */ | |
327 | default: | |
328 | return 0; /* disallow everything else */ | |
329 | } | |
330 | break; | |
331 | case 0x1: | |
332 | return 0; /* reserved */ | |
333 | case 0x2: | |
334 | return (cmd & 0xff) + 2; /* 2d commands */ | |
335 | case 0x3: | |
336 | if (((cmd >> 24) & 0x1f) <= 0x18) | |
337 | return 1; | |
338 | ||
339 | switch ((cmd >> 24) & 0x1f) { | |
340 | case 0x1c: | |
341 | return 1; | |
342 | case 0x1d: | |
b5e89ed5 | 343 | switch ((cmd >> 16) & 0xff) { |
1da177e4 LT |
344 | case 0x3: |
345 | return (cmd & 0x1f) + 2; | |
346 | case 0x4: | |
347 | return (cmd & 0xf) + 2; | |
348 | default: | |
349 | return (cmd & 0xffff) + 2; | |
350 | } | |
351 | case 0x1e: | |
352 | if (cmd & (1 << 23)) | |
353 | return (cmd & 0xffff) + 1; | |
354 | else | |
355 | return 1; | |
356 | case 0x1f: | |
357 | if ((cmd & (1 << 23)) == 0) /* inline vertices */ | |
358 | return (cmd & 0x1ffff) + 2; | |
359 | else if (cmd & (1 << 17)) /* indirect random */ | |
360 | if ((cmd & 0xffff) == 0) | |
361 | return 0; /* unknown length, too hard */ | |
362 | else | |
363 | return (((cmd & 0xffff) + 1) / 2) + 1; | |
364 | else | |
365 | return 2; /* indirect sequential */ | |
366 | default: | |
367 | return 0; | |
368 | } | |
369 | default: | |
370 | return 0; | |
371 | } | |
372 | ||
373 | return 0; | |
374 | } | |
375 | ||
201361a5 | 376 | static int i915_emit_cmds(struct drm_device * dev, int *buffer, int dwords) |
1da177e4 LT |
377 | { |
378 | drm_i915_private_t *dev_priv = dev->dev_private; | |
e1f99ce6 | 379 | int i, ret; |
1da177e4 | 380 | |
1ec14ad3 | 381 | if ((dwords+1) * sizeof(int) >= LP_RING(dev_priv)->size - 8) |
20caafa6 | 382 | return -EINVAL; |
de227f5f | 383 | |
1da177e4 | 384 | for (i = 0; i < dwords;) { |
e1f99ce6 CW |
385 | int sz = validate_cmd(buffer[i]); |
386 | if (sz == 0 || i + sz > dwords) | |
20caafa6 | 387 | return -EINVAL; |
e1f99ce6 | 388 | i += sz; |
1da177e4 LT |
389 | } |
390 | ||
e1f99ce6 CW |
391 | ret = BEGIN_LP_RING((dwords+1)&~1); |
392 | if (ret) | |
393 | return ret; | |
394 | ||
395 | for (i = 0; i < dwords; i++) | |
396 | OUT_RING(buffer[i]); | |
de227f5f DA |
397 | if (dwords & 1) |
398 | OUT_RING(0); | |
399 | ||
400 | ADVANCE_LP_RING(); | |
401 | ||
1da177e4 LT |
402 | return 0; |
403 | } | |
404 | ||
673a394b EA |
405 | int |
406 | i915_emit_box(struct drm_device *dev, | |
c4e7a414 CW |
407 | struct drm_clip_rect *box, |
408 | int DR1, int DR4) | |
1da177e4 | 409 | { |
e1f99ce6 | 410 | struct drm_i915_private *dev_priv = dev->dev_private; |
e1f99ce6 | 411 | int ret; |
1da177e4 | 412 | |
c4e7a414 CW |
413 | if (box->y2 <= box->y1 || box->x2 <= box->x1 || |
414 | box->y2 <= 0 || box->x2 <= 0) { | |
1da177e4 | 415 | DRM_ERROR("Bad box %d,%d..%d,%d\n", |
c4e7a414 | 416 | box->x1, box->y1, box->x2, box->y2); |
20caafa6 | 417 | return -EINVAL; |
1da177e4 LT |
418 | } |
419 | ||
a6c45cf0 | 420 | if (INTEL_INFO(dev)->gen >= 4) { |
e1f99ce6 CW |
421 | ret = BEGIN_LP_RING(4); |
422 | if (ret) | |
423 | return ret; | |
424 | ||
c29b669c | 425 | OUT_RING(GFX_OP_DRAWRECT_INFO_I965); |
c4e7a414 CW |
426 | OUT_RING((box->x1 & 0xffff) | (box->y1 << 16)); |
427 | OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16)); | |
c29b669c | 428 | OUT_RING(DR4); |
c29b669c | 429 | } else { |
e1f99ce6 CW |
430 | ret = BEGIN_LP_RING(6); |
431 | if (ret) | |
432 | return ret; | |
433 | ||
c29b669c AH |
434 | OUT_RING(GFX_OP_DRAWRECT_INFO); |
435 | OUT_RING(DR1); | |
c4e7a414 CW |
436 | OUT_RING((box->x1 & 0xffff) | (box->y1 << 16)); |
437 | OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16)); | |
c29b669c AH |
438 | OUT_RING(DR4); |
439 | OUT_RING(0); | |
c29b669c | 440 | } |
e1f99ce6 | 441 | ADVANCE_LP_RING(); |
1da177e4 LT |
442 | |
443 | return 0; | |
444 | } | |
445 | ||
c29b669c AH |
446 | /* XXX: Emitting the counter should really be moved to part of the IRQ |
447 | * emit. For now, do it in both places: | |
448 | */ | |
449 | ||
84b1fd10 | 450 | static void i915_emit_breadcrumb(struct drm_device *dev) |
de227f5f DA |
451 | { |
452 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7c1c2871 | 453 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
de227f5f | 454 | |
c99b058f | 455 | dev_priv->counter++; |
af6061af | 456 | if (dev_priv->counter > 0x7FFFFFFFUL) |
c99b058f | 457 | dev_priv->counter = 0; |
7c1c2871 DA |
458 | if (master_priv->sarea_priv) |
459 | master_priv->sarea_priv->last_enqueue = dev_priv->counter; | |
de227f5f | 460 | |
e1f99ce6 CW |
461 | if (BEGIN_LP_RING(4) == 0) { |
462 | OUT_RING(MI_STORE_DWORD_INDEX); | |
463 | OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
464 | OUT_RING(dev_priv->counter); | |
465 | OUT_RING(0); | |
466 | ADVANCE_LP_RING(); | |
467 | } | |
de227f5f DA |
468 | } |
469 | ||
84b1fd10 | 470 | static int i915_dispatch_cmdbuffer(struct drm_device * dev, |
201361a5 EA |
471 | drm_i915_cmdbuffer_t *cmd, |
472 | struct drm_clip_rect *cliprects, | |
473 | void *cmdbuf) | |
1da177e4 LT |
474 | { |
475 | int nbox = cmd->num_cliprects; | |
476 | int i = 0, count, ret; | |
477 | ||
478 | if (cmd->sz & 0x3) { | |
479 | DRM_ERROR("alignment"); | |
20caafa6 | 480 | return -EINVAL; |
1da177e4 LT |
481 | } |
482 | ||
483 | i915_kernel_lost_context(dev); | |
484 | ||
485 | count = nbox ? nbox : 1; | |
486 | ||
487 | for (i = 0; i < count; i++) { | |
488 | if (i < nbox) { | |
c4e7a414 | 489 | ret = i915_emit_box(dev, &cliprects[i], |
1da177e4 LT |
490 | cmd->DR1, cmd->DR4); |
491 | if (ret) | |
492 | return ret; | |
493 | } | |
494 | ||
201361a5 | 495 | ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4); |
1da177e4 LT |
496 | if (ret) |
497 | return ret; | |
498 | } | |
499 | ||
de227f5f | 500 | i915_emit_breadcrumb(dev); |
1da177e4 LT |
501 | return 0; |
502 | } | |
503 | ||
84b1fd10 | 504 | static int i915_dispatch_batchbuffer(struct drm_device * dev, |
201361a5 EA |
505 | drm_i915_batchbuffer_t * batch, |
506 | struct drm_clip_rect *cliprects) | |
1da177e4 | 507 | { |
e1f99ce6 | 508 | struct drm_i915_private *dev_priv = dev->dev_private; |
1da177e4 | 509 | int nbox = batch->num_cliprects; |
e1f99ce6 | 510 | int i, count, ret; |
1da177e4 LT |
511 | |
512 | if ((batch->start | batch->used) & 0x7) { | |
513 | DRM_ERROR("alignment"); | |
20caafa6 | 514 | return -EINVAL; |
1da177e4 LT |
515 | } |
516 | ||
517 | i915_kernel_lost_context(dev); | |
518 | ||
519 | count = nbox ? nbox : 1; | |
1da177e4 LT |
520 | for (i = 0; i < count; i++) { |
521 | if (i < nbox) { | |
c4e7a414 | 522 | ret = i915_emit_box(dev, &cliprects[i], |
e1f99ce6 | 523 | batch->DR1, batch->DR4); |
1da177e4 LT |
524 | if (ret) |
525 | return ret; | |
526 | } | |
527 | ||
0790d5e1 | 528 | if (!IS_I830(dev) && !IS_845G(dev)) { |
e1f99ce6 CW |
529 | ret = BEGIN_LP_RING(2); |
530 | if (ret) | |
531 | return ret; | |
532 | ||
a6c45cf0 | 533 | if (INTEL_INFO(dev)->gen >= 4) { |
21f16289 DA |
534 | OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965); |
535 | OUT_RING(batch->start); | |
536 | } else { | |
537 | OUT_RING(MI_BATCH_BUFFER_START | (2 << 6)); | |
538 | OUT_RING(batch->start | MI_BATCH_NON_SECURE); | |
539 | } | |
1da177e4 | 540 | } else { |
e1f99ce6 CW |
541 | ret = BEGIN_LP_RING(4); |
542 | if (ret) | |
543 | return ret; | |
544 | ||
1da177e4 LT |
545 | OUT_RING(MI_BATCH_BUFFER); |
546 | OUT_RING(batch->start | MI_BATCH_NON_SECURE); | |
547 | OUT_RING(batch->start + batch->used - 4); | |
548 | OUT_RING(0); | |
1da177e4 | 549 | } |
e1f99ce6 | 550 | ADVANCE_LP_RING(); |
1da177e4 LT |
551 | } |
552 | ||
1cafd347 | 553 | |
f00a3ddf | 554 | if (IS_G4X(dev) || IS_GEN5(dev)) { |
e1f99ce6 CW |
555 | if (BEGIN_LP_RING(2) == 0) { |
556 | OUT_RING(MI_FLUSH | MI_NO_WRITE_FLUSH | MI_INVALIDATE_ISP); | |
557 | OUT_RING(MI_NOOP); | |
558 | ADVANCE_LP_RING(); | |
559 | } | |
1cafd347 | 560 | } |
1da177e4 | 561 | |
e1f99ce6 | 562 | i915_emit_breadcrumb(dev); |
1da177e4 LT |
563 | return 0; |
564 | } | |
565 | ||
af6061af | 566 | static int i915_dispatch_flip(struct drm_device * dev) |
1da177e4 LT |
567 | { |
568 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7c1c2871 DA |
569 | struct drm_i915_master_private *master_priv = |
570 | dev->primary->master->driver_priv; | |
e1f99ce6 | 571 | int ret; |
1da177e4 | 572 | |
7c1c2871 | 573 | if (!master_priv->sarea_priv) |
c99b058f KH |
574 | return -EINVAL; |
575 | ||
8a4c47f3 | 576 | DRM_DEBUG_DRIVER("%s: page=%d pfCurrentPage=%d\n", |
be25ed9c | 577 | __func__, |
578 | dev_priv->current_page, | |
579 | master_priv->sarea_priv->pf_current_page); | |
1da177e4 | 580 | |
af6061af DA |
581 | i915_kernel_lost_context(dev); |
582 | ||
e1f99ce6 CW |
583 | ret = BEGIN_LP_RING(10); |
584 | if (ret) | |
585 | return ret; | |
586 | ||
585fb111 | 587 | OUT_RING(MI_FLUSH | MI_READ_FLUSH); |
af6061af | 588 | OUT_RING(0); |
1da177e4 | 589 | |
af6061af DA |
590 | OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP); |
591 | OUT_RING(0); | |
592 | if (dev_priv->current_page == 0) { | |
593 | OUT_RING(dev_priv->back_offset); | |
594 | dev_priv->current_page = 1; | |
1da177e4 | 595 | } else { |
af6061af DA |
596 | OUT_RING(dev_priv->front_offset); |
597 | dev_priv->current_page = 0; | |
1da177e4 | 598 | } |
af6061af | 599 | OUT_RING(0); |
1da177e4 | 600 | |
af6061af DA |
601 | OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP); |
602 | OUT_RING(0); | |
e1f99ce6 | 603 | |
af6061af | 604 | ADVANCE_LP_RING(); |
1da177e4 | 605 | |
7c1c2871 | 606 | master_priv->sarea_priv->last_enqueue = dev_priv->counter++; |
1da177e4 | 607 | |
e1f99ce6 CW |
608 | if (BEGIN_LP_RING(4) == 0) { |
609 | OUT_RING(MI_STORE_DWORD_INDEX); | |
610 | OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
611 | OUT_RING(dev_priv->counter); | |
612 | OUT_RING(0); | |
613 | ADVANCE_LP_RING(); | |
614 | } | |
1da177e4 | 615 | |
7c1c2871 | 616 | master_priv->sarea_priv->pf_current_page = dev_priv->current_page; |
af6061af | 617 | return 0; |
1da177e4 LT |
618 | } |
619 | ||
1ec14ad3 | 620 | static int i915_quiescent(struct drm_device *dev) |
1da177e4 | 621 | { |
1ec14ad3 | 622 | struct intel_ring_buffer *ring = LP_RING(dev->dev_private); |
1da177e4 LT |
623 | |
624 | i915_kernel_lost_context(dev); | |
96f298aa | 625 | return intel_wait_ring_idle(ring); |
1da177e4 LT |
626 | } |
627 | ||
c153f45f EA |
628 | static int i915_flush_ioctl(struct drm_device *dev, void *data, |
629 | struct drm_file *file_priv) | |
1da177e4 | 630 | { |
546b0974 EA |
631 | int ret; |
632 | ||
cd9d4e9f DV |
633 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
634 | return -ENODEV; | |
635 | ||
546b0974 | 636 | RING_LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 | 637 | |
546b0974 EA |
638 | mutex_lock(&dev->struct_mutex); |
639 | ret = i915_quiescent(dev); | |
640 | mutex_unlock(&dev->struct_mutex); | |
641 | ||
642 | return ret; | |
1da177e4 LT |
643 | } |
644 | ||
c153f45f EA |
645 | static int i915_batchbuffer(struct drm_device *dev, void *data, |
646 | struct drm_file *file_priv) | |
1da177e4 | 647 | { |
1da177e4 | 648 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
7c1c2871 | 649 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
1da177e4 | 650 | drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *) |
7c1c2871 | 651 | master_priv->sarea_priv; |
c153f45f | 652 | drm_i915_batchbuffer_t *batch = data; |
1da177e4 | 653 | int ret; |
201361a5 | 654 | struct drm_clip_rect *cliprects = NULL; |
1da177e4 | 655 | |
cd9d4e9f DV |
656 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
657 | return -ENODEV; | |
658 | ||
8781342d | 659 | if (!dev_priv->dri1.allow_batchbuffer) { |
1da177e4 | 660 | DRM_ERROR("Batchbuffer ioctl disabled\n"); |
20caafa6 | 661 | return -EINVAL; |
1da177e4 LT |
662 | } |
663 | ||
8a4c47f3 | 664 | DRM_DEBUG_DRIVER("i915 batchbuffer, start %x used %d cliprects %d\n", |
be25ed9c | 665 | batch->start, batch->used, batch->num_cliprects); |
1da177e4 | 666 | |
546b0974 | 667 | RING_LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 | 668 | |
201361a5 EA |
669 | if (batch->num_cliprects < 0) |
670 | return -EINVAL; | |
671 | ||
672 | if (batch->num_cliprects) { | |
9a298b2a EA |
673 | cliprects = kcalloc(batch->num_cliprects, |
674 | sizeof(struct drm_clip_rect), | |
675 | GFP_KERNEL); | |
201361a5 EA |
676 | if (cliprects == NULL) |
677 | return -ENOMEM; | |
678 | ||
679 | ret = copy_from_user(cliprects, batch->cliprects, | |
680 | batch->num_cliprects * | |
681 | sizeof(struct drm_clip_rect)); | |
9927a403 DC |
682 | if (ret != 0) { |
683 | ret = -EFAULT; | |
201361a5 | 684 | goto fail_free; |
9927a403 | 685 | } |
201361a5 | 686 | } |
1da177e4 | 687 | |
546b0974 | 688 | mutex_lock(&dev->struct_mutex); |
201361a5 | 689 | ret = i915_dispatch_batchbuffer(dev, batch, cliprects); |
546b0974 | 690 | mutex_unlock(&dev->struct_mutex); |
1da177e4 | 691 | |
c99b058f | 692 | if (sarea_priv) |
0baf823a | 693 | sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv); |
201361a5 EA |
694 | |
695 | fail_free: | |
9a298b2a | 696 | kfree(cliprects); |
201361a5 | 697 | |
1da177e4 LT |
698 | return ret; |
699 | } | |
700 | ||
c153f45f EA |
701 | static int i915_cmdbuffer(struct drm_device *dev, void *data, |
702 | struct drm_file *file_priv) | |
1da177e4 | 703 | { |
1da177e4 | 704 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
7c1c2871 | 705 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
1da177e4 | 706 | drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *) |
7c1c2871 | 707 | master_priv->sarea_priv; |
c153f45f | 708 | drm_i915_cmdbuffer_t *cmdbuf = data; |
201361a5 EA |
709 | struct drm_clip_rect *cliprects = NULL; |
710 | void *batch_data; | |
1da177e4 LT |
711 | int ret; |
712 | ||
8a4c47f3 | 713 | DRM_DEBUG_DRIVER("i915 cmdbuffer, buf %p sz %d cliprects %d\n", |
be25ed9c | 714 | cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects); |
1da177e4 | 715 | |
cd9d4e9f DV |
716 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
717 | return -ENODEV; | |
718 | ||
546b0974 | 719 | RING_LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 | 720 | |
201361a5 EA |
721 | if (cmdbuf->num_cliprects < 0) |
722 | return -EINVAL; | |
723 | ||
9a298b2a | 724 | batch_data = kmalloc(cmdbuf->sz, GFP_KERNEL); |
201361a5 EA |
725 | if (batch_data == NULL) |
726 | return -ENOMEM; | |
727 | ||
728 | ret = copy_from_user(batch_data, cmdbuf->buf, cmdbuf->sz); | |
9927a403 DC |
729 | if (ret != 0) { |
730 | ret = -EFAULT; | |
201361a5 | 731 | goto fail_batch_free; |
9927a403 | 732 | } |
201361a5 EA |
733 | |
734 | if (cmdbuf->num_cliprects) { | |
9a298b2a EA |
735 | cliprects = kcalloc(cmdbuf->num_cliprects, |
736 | sizeof(struct drm_clip_rect), GFP_KERNEL); | |
a40e8d31 OA |
737 | if (cliprects == NULL) { |
738 | ret = -ENOMEM; | |
201361a5 | 739 | goto fail_batch_free; |
a40e8d31 | 740 | } |
201361a5 EA |
741 | |
742 | ret = copy_from_user(cliprects, cmdbuf->cliprects, | |
743 | cmdbuf->num_cliprects * | |
744 | sizeof(struct drm_clip_rect)); | |
9927a403 DC |
745 | if (ret != 0) { |
746 | ret = -EFAULT; | |
201361a5 | 747 | goto fail_clip_free; |
9927a403 | 748 | } |
1da177e4 LT |
749 | } |
750 | ||
546b0974 | 751 | mutex_lock(&dev->struct_mutex); |
201361a5 | 752 | ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data); |
546b0974 | 753 | mutex_unlock(&dev->struct_mutex); |
1da177e4 LT |
754 | if (ret) { |
755 | DRM_ERROR("i915_dispatch_cmdbuffer failed\n"); | |
355d7f37 | 756 | goto fail_clip_free; |
1da177e4 LT |
757 | } |
758 | ||
c99b058f | 759 | if (sarea_priv) |
0baf823a | 760 | sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv); |
201361a5 | 761 | |
201361a5 | 762 | fail_clip_free: |
9a298b2a | 763 | kfree(cliprects); |
355d7f37 | 764 | fail_batch_free: |
9a298b2a | 765 | kfree(batch_data); |
201361a5 EA |
766 | |
767 | return ret; | |
1da177e4 LT |
768 | } |
769 | ||
9488867a DV |
770 | static int i915_emit_irq(struct drm_device * dev) |
771 | { | |
772 | drm_i915_private_t *dev_priv = dev->dev_private; | |
773 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; | |
774 | ||
775 | i915_kernel_lost_context(dev); | |
776 | ||
777 | DRM_DEBUG_DRIVER("\n"); | |
778 | ||
779 | dev_priv->counter++; | |
780 | if (dev_priv->counter > 0x7FFFFFFFUL) | |
781 | dev_priv->counter = 1; | |
782 | if (master_priv->sarea_priv) | |
783 | master_priv->sarea_priv->last_enqueue = dev_priv->counter; | |
784 | ||
785 | if (BEGIN_LP_RING(4) == 0) { | |
786 | OUT_RING(MI_STORE_DWORD_INDEX); | |
787 | OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
788 | OUT_RING(dev_priv->counter); | |
789 | OUT_RING(MI_USER_INTERRUPT); | |
790 | ADVANCE_LP_RING(); | |
791 | } | |
792 | ||
793 | return dev_priv->counter; | |
794 | } | |
795 | ||
796 | static int i915_wait_irq(struct drm_device * dev, int irq_nr) | |
797 | { | |
798 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
799 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; | |
800 | int ret = 0; | |
801 | struct intel_ring_buffer *ring = LP_RING(dev_priv); | |
802 | ||
803 | DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr, | |
804 | READ_BREADCRUMB(dev_priv)); | |
805 | ||
806 | if (READ_BREADCRUMB(dev_priv) >= irq_nr) { | |
807 | if (master_priv->sarea_priv) | |
808 | master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv); | |
809 | return 0; | |
810 | } | |
811 | ||
812 | if (master_priv->sarea_priv) | |
813 | master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT; | |
814 | ||
815 | if (ring->irq_get(ring)) { | |
816 | DRM_WAIT_ON(ret, ring->irq_queue, 3 * DRM_HZ, | |
817 | READ_BREADCRUMB(dev_priv) >= irq_nr); | |
818 | ring->irq_put(ring); | |
819 | } else if (wait_for(READ_BREADCRUMB(dev_priv) >= irq_nr, 3000)) | |
820 | ret = -EBUSY; | |
821 | ||
822 | if (ret == -EBUSY) { | |
823 | DRM_ERROR("EBUSY -- rec: %d emitted: %d\n", | |
824 | READ_BREADCRUMB(dev_priv), (int)dev_priv->counter); | |
825 | } | |
826 | ||
827 | return ret; | |
828 | } | |
829 | ||
830 | /* Needs the lock as it touches the ring. | |
831 | */ | |
832 | static int i915_irq_emit(struct drm_device *dev, void *data, | |
833 | struct drm_file *file_priv) | |
834 | { | |
835 | drm_i915_private_t *dev_priv = dev->dev_private; | |
836 | drm_i915_irq_emit_t *emit = data; | |
837 | int result; | |
838 | ||
839 | if (drm_core_check_feature(dev, DRIVER_MODESET)) | |
840 | return -ENODEV; | |
841 | ||
842 | if (!dev_priv || !LP_RING(dev_priv)->virtual_start) { | |
843 | DRM_ERROR("called with no initialization\n"); | |
844 | return -EINVAL; | |
845 | } | |
846 | ||
847 | RING_LOCK_TEST_WITH_RETURN(dev, file_priv); | |
848 | ||
849 | mutex_lock(&dev->struct_mutex); | |
850 | result = i915_emit_irq(dev); | |
851 | mutex_unlock(&dev->struct_mutex); | |
852 | ||
853 | if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) { | |
854 | DRM_ERROR("copy_to_user\n"); | |
855 | return -EFAULT; | |
856 | } | |
857 | ||
858 | return 0; | |
859 | } | |
860 | ||
861 | /* Doesn't need the hardware lock. | |
862 | */ | |
863 | static int i915_irq_wait(struct drm_device *dev, void *data, | |
864 | struct drm_file *file_priv) | |
865 | { | |
866 | drm_i915_private_t *dev_priv = dev->dev_private; | |
867 | drm_i915_irq_wait_t *irqwait = data; | |
868 | ||
869 | if (drm_core_check_feature(dev, DRIVER_MODESET)) | |
870 | return -ENODEV; | |
871 | ||
872 | if (!dev_priv) { | |
873 | DRM_ERROR("called with no initialization\n"); | |
874 | return -EINVAL; | |
875 | } | |
876 | ||
877 | return i915_wait_irq(dev, irqwait->irq_seq); | |
878 | } | |
879 | ||
d1c1edbc DV |
880 | static int i915_vblank_pipe_get(struct drm_device *dev, void *data, |
881 | struct drm_file *file_priv) | |
882 | { | |
883 | drm_i915_private_t *dev_priv = dev->dev_private; | |
884 | drm_i915_vblank_pipe_t *pipe = data; | |
885 | ||
886 | if (drm_core_check_feature(dev, DRIVER_MODESET)) | |
887 | return -ENODEV; | |
888 | ||
889 | if (!dev_priv) { | |
890 | DRM_ERROR("called with no initialization\n"); | |
891 | return -EINVAL; | |
892 | } | |
893 | ||
894 | pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B; | |
895 | ||
896 | return 0; | |
897 | } | |
898 | ||
899 | /** | |
900 | * Schedule buffer swap at given vertical blank. | |
901 | */ | |
902 | static int i915_vblank_swap(struct drm_device *dev, void *data, | |
903 | struct drm_file *file_priv) | |
904 | { | |
905 | /* The delayed swap mechanism was fundamentally racy, and has been | |
906 | * removed. The model was that the client requested a delayed flip/swap | |
907 | * from the kernel, then waited for vblank before continuing to perform | |
908 | * rendering. The problem was that the kernel might wake the client | |
909 | * up before it dispatched the vblank swap (since the lock has to be | |
910 | * held while touching the ringbuffer), in which case the client would | |
911 | * clear and start the next frame before the swap occurred, and | |
912 | * flicker would occur in addition to likely missing the vblank. | |
913 | * | |
914 | * In the absence of this ioctl, userland falls back to a correct path | |
915 | * of waiting for a vblank, then dispatching the swap on its own. | |
916 | * Context switching to userland and back is plenty fast enough for | |
917 | * meeting the requirements of vblank swapping. | |
918 | */ | |
919 | return -EINVAL; | |
920 | } | |
921 | ||
c153f45f EA |
922 | static int i915_flip_bufs(struct drm_device *dev, void *data, |
923 | struct drm_file *file_priv) | |
1da177e4 | 924 | { |
546b0974 EA |
925 | int ret; |
926 | ||
cd9d4e9f DV |
927 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
928 | return -ENODEV; | |
929 | ||
8a4c47f3 | 930 | DRM_DEBUG_DRIVER("%s\n", __func__); |
1da177e4 | 931 | |
546b0974 | 932 | RING_LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 | 933 | |
546b0974 EA |
934 | mutex_lock(&dev->struct_mutex); |
935 | ret = i915_dispatch_flip(dev); | |
936 | mutex_unlock(&dev->struct_mutex); | |
937 | ||
938 | return ret; | |
1da177e4 LT |
939 | } |
940 | ||
c153f45f EA |
941 | static int i915_getparam(struct drm_device *dev, void *data, |
942 | struct drm_file *file_priv) | |
1da177e4 | 943 | { |
1da177e4 | 944 | drm_i915_private_t *dev_priv = dev->dev_private; |
c153f45f | 945 | drm_i915_getparam_t *param = data; |
1da177e4 LT |
946 | int value; |
947 | ||
948 | if (!dev_priv) { | |
3e684eae | 949 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 950 | return -EINVAL; |
1da177e4 LT |
951 | } |
952 | ||
c153f45f | 953 | switch (param->param) { |
1da177e4 | 954 | case I915_PARAM_IRQ_ACTIVE: |
0a3e67a4 | 955 | value = dev->pdev->irq ? 1 : 0; |
1da177e4 LT |
956 | break; |
957 | case I915_PARAM_ALLOW_BATCHBUFFER: | |
8781342d | 958 | value = dev_priv->dri1.allow_batchbuffer ? 1 : 0; |
1da177e4 | 959 | break; |
0d6aa60b DA |
960 | case I915_PARAM_LAST_DISPATCH: |
961 | value = READ_BREADCRUMB(dev_priv); | |
962 | break; | |
ed4c9c4a KH |
963 | case I915_PARAM_CHIPSET_ID: |
964 | value = dev->pci_device; | |
965 | break; | |
673a394b | 966 | case I915_PARAM_HAS_GEM: |
2e895b17 | 967 | value = 1; |
673a394b | 968 | break; |
0f973f27 JB |
969 | case I915_PARAM_NUM_FENCES_AVAIL: |
970 | value = dev_priv->num_fence_regs - dev_priv->fence_reg_start; | |
971 | break; | |
02e792fb DV |
972 | case I915_PARAM_HAS_OVERLAY: |
973 | value = dev_priv->overlay ? 1 : 0; | |
974 | break; | |
e9560f7c JB |
975 | case I915_PARAM_HAS_PAGEFLIPPING: |
976 | value = 1; | |
977 | break; | |
76446cac JB |
978 | case I915_PARAM_HAS_EXECBUF2: |
979 | /* depends on GEM */ | |
2e895b17 | 980 | value = 1; |
76446cac | 981 | break; |
e3a815fc | 982 | case I915_PARAM_HAS_BSD: |
edc912f5 | 983 | value = intel_ring_initialized(&dev_priv->ring[VCS]); |
e3a815fc | 984 | break; |
549f7365 | 985 | case I915_PARAM_HAS_BLT: |
edc912f5 | 986 | value = intel_ring_initialized(&dev_priv->ring[BCS]); |
549f7365 | 987 | break; |
a00b10c3 CW |
988 | case I915_PARAM_HAS_RELAXED_FENCING: |
989 | value = 1; | |
990 | break; | |
bbf0c6b3 DV |
991 | case I915_PARAM_HAS_COHERENT_RINGS: |
992 | value = 1; | |
993 | break; | |
72bfa19c CW |
994 | case I915_PARAM_HAS_EXEC_CONSTANTS: |
995 | value = INTEL_INFO(dev)->gen >= 4; | |
996 | break; | |
271d81b8 CW |
997 | case I915_PARAM_HAS_RELAXED_DELTA: |
998 | value = 1; | |
999 | break; | |
ae662d31 EA |
1000 | case I915_PARAM_HAS_GEN7_SOL_RESET: |
1001 | value = 1; | |
1002 | break; | |
3d29b842 ED |
1003 | case I915_PARAM_HAS_LLC: |
1004 | value = HAS_LLC(dev); | |
1005 | break; | |
777ee96f DV |
1006 | case I915_PARAM_HAS_ALIASING_PPGTT: |
1007 | value = dev_priv->mm.aliasing_ppgtt ? 1 : 0; | |
1008 | break; | |
1da177e4 | 1009 | default: |
8a4c47f3 | 1010 | DRM_DEBUG_DRIVER("Unknown parameter %d\n", |
76446cac | 1011 | param->param); |
20caafa6 | 1012 | return -EINVAL; |
1da177e4 LT |
1013 | } |
1014 | ||
c153f45f | 1015 | if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) { |
1da177e4 | 1016 | DRM_ERROR("DRM_COPY_TO_USER failed\n"); |
20caafa6 | 1017 | return -EFAULT; |
1da177e4 LT |
1018 | } |
1019 | ||
1020 | return 0; | |
1021 | } | |
1022 | ||
c153f45f EA |
1023 | static int i915_setparam(struct drm_device *dev, void *data, |
1024 | struct drm_file *file_priv) | |
1da177e4 | 1025 | { |
1da177e4 | 1026 | drm_i915_private_t *dev_priv = dev->dev_private; |
c153f45f | 1027 | drm_i915_setparam_t *param = data; |
1da177e4 LT |
1028 | |
1029 | if (!dev_priv) { | |
3e684eae | 1030 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 1031 | return -EINVAL; |
1da177e4 LT |
1032 | } |
1033 | ||
c153f45f | 1034 | switch (param->param) { |
1da177e4 | 1035 | case I915_SETPARAM_USE_MI_BATCHBUFFER_START: |
1da177e4 LT |
1036 | break; |
1037 | case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY: | |
1da177e4 LT |
1038 | break; |
1039 | case I915_SETPARAM_ALLOW_BATCHBUFFER: | |
8781342d | 1040 | dev_priv->dri1.allow_batchbuffer = param->value ? 1 : 0; |
1da177e4 | 1041 | break; |
0f973f27 JB |
1042 | case I915_SETPARAM_NUM_USED_FENCES: |
1043 | if (param->value > dev_priv->num_fence_regs || | |
1044 | param->value < 0) | |
1045 | return -EINVAL; | |
1046 | /* Userspace can use first N regs */ | |
1047 | dev_priv->fence_reg_start = param->value; | |
1048 | break; | |
1da177e4 | 1049 | default: |
8a4c47f3 | 1050 | DRM_DEBUG_DRIVER("unknown parameter %d\n", |
be25ed9c | 1051 | param->param); |
20caafa6 | 1052 | return -EINVAL; |
1da177e4 LT |
1053 | } |
1054 | ||
1055 | return 0; | |
1056 | } | |
1057 | ||
c153f45f EA |
1058 | static int i915_set_status_page(struct drm_device *dev, void *data, |
1059 | struct drm_file *file_priv) | |
dc7a9319 | 1060 | { |
dc7a9319 | 1061 | drm_i915_private_t *dev_priv = dev->dev_private; |
c153f45f | 1062 | drm_i915_hws_addr_t *hws = data; |
1ec14ad3 | 1063 | struct intel_ring_buffer *ring = LP_RING(dev_priv); |
b39d50e5 | 1064 | |
cd9d4e9f DV |
1065 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
1066 | return -ENODEV; | |
1067 | ||
b39d50e5 ZW |
1068 | if (!I915_NEED_GFX_HWS(dev)) |
1069 | return -EINVAL; | |
dc7a9319 WZ |
1070 | |
1071 | if (!dev_priv) { | |
3e684eae | 1072 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 1073 | return -EINVAL; |
dc7a9319 | 1074 | } |
dc7a9319 | 1075 | |
79e53945 JB |
1076 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
1077 | WARN(1, "tried to set status page when mode setting active\n"); | |
1078 | return 0; | |
1079 | } | |
1080 | ||
8a4c47f3 | 1081 | DRM_DEBUG_DRIVER("set status page addr 0x%08x\n", (u32)hws->addr); |
c153f45f | 1082 | |
8187a2b7 | 1083 | ring->status_page.gfx_addr = hws->addr & (0x1ffff<<12); |
dc7a9319 | 1084 | |
316d3884 DV |
1085 | dev_priv->dri1.gfx_hws_cpu_addr = ioremap_wc(dev->agp->base + hws->addr, |
1086 | 4096); | |
1087 | if (dev_priv->dri1.gfx_hws_cpu_addr == NULL) { | |
dc7a9319 | 1088 | i915_dma_cleanup(dev); |
e20f9c64 | 1089 | ring->status_page.gfx_addr = 0; |
dc7a9319 WZ |
1090 | DRM_ERROR("can not ioremap virtual address for" |
1091 | " G33 hw status page\n"); | |
20caafa6 | 1092 | return -ENOMEM; |
dc7a9319 | 1093 | } |
316d3884 DV |
1094 | |
1095 | memset_io(dev_priv->dri1.gfx_hws_cpu_addr, 0, PAGE_SIZE); | |
8187a2b7 | 1096 | I915_WRITE(HWS_PGA, ring->status_page.gfx_addr); |
dc7a9319 | 1097 | |
8a4c47f3 | 1098 | DRM_DEBUG_DRIVER("load hws HWS_PGA with gfx mem 0x%x\n", |
e20f9c64 | 1099 | ring->status_page.gfx_addr); |
8a4c47f3 | 1100 | DRM_DEBUG_DRIVER("load hws at %p\n", |
e20f9c64 | 1101 | ring->status_page.page_addr); |
dc7a9319 WZ |
1102 | return 0; |
1103 | } | |
1104 | ||
ec2a4c3f DA |
1105 | static int i915_get_bridge_dev(struct drm_device *dev) |
1106 | { | |
1107 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1108 | ||
0206e353 | 1109 | dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0)); |
ec2a4c3f DA |
1110 | if (!dev_priv->bridge_dev) { |
1111 | DRM_ERROR("bridge device not found\n"); | |
1112 | return -1; | |
1113 | } | |
1114 | return 0; | |
1115 | } | |
1116 | ||
c4804411 ZW |
1117 | #define MCHBAR_I915 0x44 |
1118 | #define MCHBAR_I965 0x48 | |
1119 | #define MCHBAR_SIZE (4*4096) | |
1120 | ||
1121 | #define DEVEN_REG 0x54 | |
1122 | #define DEVEN_MCHBAR_EN (1 << 28) | |
1123 | ||
1124 | /* Allocate space for the MCH regs if needed, return nonzero on error */ | |
1125 | static int | |
1126 | intel_alloc_mchbar_resource(struct drm_device *dev) | |
1127 | { | |
1128 | drm_i915_private_t *dev_priv = dev->dev_private; | |
a6c45cf0 | 1129 | int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915; |
c4804411 ZW |
1130 | u32 temp_lo, temp_hi = 0; |
1131 | u64 mchbar_addr; | |
a25c25c2 | 1132 | int ret; |
c4804411 | 1133 | |
a6c45cf0 | 1134 | if (INTEL_INFO(dev)->gen >= 4) |
c4804411 ZW |
1135 | pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi); |
1136 | pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo); | |
1137 | mchbar_addr = ((u64)temp_hi << 32) | temp_lo; | |
1138 | ||
1139 | /* If ACPI doesn't have it, assume we need to allocate it ourselves */ | |
1140 | #ifdef CONFIG_PNP | |
1141 | if (mchbar_addr && | |
a25c25c2 CW |
1142 | pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE)) |
1143 | return 0; | |
c4804411 ZW |
1144 | #endif |
1145 | ||
1146 | /* Get some space for it */ | |
a25c25c2 CW |
1147 | dev_priv->mch_res.name = "i915 MCHBAR"; |
1148 | dev_priv->mch_res.flags = IORESOURCE_MEM; | |
1149 | ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus, | |
1150 | &dev_priv->mch_res, | |
c4804411 ZW |
1151 | MCHBAR_SIZE, MCHBAR_SIZE, |
1152 | PCIBIOS_MIN_MEM, | |
a25c25c2 | 1153 | 0, pcibios_align_resource, |
c4804411 ZW |
1154 | dev_priv->bridge_dev); |
1155 | if (ret) { | |
1156 | DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret); | |
1157 | dev_priv->mch_res.start = 0; | |
a25c25c2 | 1158 | return ret; |
c4804411 ZW |
1159 | } |
1160 | ||
a6c45cf0 | 1161 | if (INTEL_INFO(dev)->gen >= 4) |
c4804411 ZW |
1162 | pci_write_config_dword(dev_priv->bridge_dev, reg + 4, |
1163 | upper_32_bits(dev_priv->mch_res.start)); | |
1164 | ||
1165 | pci_write_config_dword(dev_priv->bridge_dev, reg, | |
1166 | lower_32_bits(dev_priv->mch_res.start)); | |
a25c25c2 | 1167 | return 0; |
c4804411 ZW |
1168 | } |
1169 | ||
1170 | /* Setup MCHBAR if possible, return true if we should disable it again */ | |
1171 | static void | |
1172 | intel_setup_mchbar(struct drm_device *dev) | |
1173 | { | |
1174 | drm_i915_private_t *dev_priv = dev->dev_private; | |
a6c45cf0 | 1175 | int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915; |
c4804411 ZW |
1176 | u32 temp; |
1177 | bool enabled; | |
1178 | ||
1179 | dev_priv->mchbar_need_disable = false; | |
1180 | ||
1181 | if (IS_I915G(dev) || IS_I915GM(dev)) { | |
1182 | pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp); | |
1183 | enabled = !!(temp & DEVEN_MCHBAR_EN); | |
1184 | } else { | |
1185 | pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); | |
1186 | enabled = temp & 1; | |
1187 | } | |
1188 | ||
1189 | /* If it's already enabled, don't have to do anything */ | |
1190 | if (enabled) | |
1191 | return; | |
1192 | ||
1193 | if (intel_alloc_mchbar_resource(dev)) | |
1194 | return; | |
1195 | ||
1196 | dev_priv->mchbar_need_disable = true; | |
1197 | ||
1198 | /* Space is allocated or reserved, so enable it. */ | |
1199 | if (IS_I915G(dev) || IS_I915GM(dev)) { | |
1200 | pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, | |
1201 | temp | DEVEN_MCHBAR_EN); | |
1202 | } else { | |
1203 | pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); | |
1204 | pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1); | |
1205 | } | |
1206 | } | |
1207 | ||
1208 | static void | |
1209 | intel_teardown_mchbar(struct drm_device *dev) | |
1210 | { | |
1211 | drm_i915_private_t *dev_priv = dev->dev_private; | |
a6c45cf0 | 1212 | int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915; |
c4804411 ZW |
1213 | u32 temp; |
1214 | ||
1215 | if (dev_priv->mchbar_need_disable) { | |
1216 | if (IS_I915G(dev) || IS_I915GM(dev)) { | |
1217 | pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp); | |
1218 | temp &= ~DEVEN_MCHBAR_EN; | |
1219 | pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp); | |
1220 | } else { | |
1221 | pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); | |
1222 | temp &= ~1; | |
1223 | pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp); | |
1224 | } | |
1225 | } | |
1226 | ||
1227 | if (dev_priv->mch_res.start) | |
1228 | release_resource(&dev_priv->mch_res); | |
1229 | } | |
1230 | ||
28d52043 DA |
1231 | /* true = enable decode, false = disable decoder */ |
1232 | static unsigned int i915_vga_set_decode(void *cookie, bool state) | |
1233 | { | |
1234 | struct drm_device *dev = cookie; | |
1235 | ||
1236 | intel_modeset_vga_set_state(dev, state); | |
1237 | if (state) | |
1238 | return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | | |
1239 | VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
1240 | else | |
1241 | return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
1242 | } | |
1243 | ||
6a9ee8af DA |
1244 | static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state) |
1245 | { | |
1246 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1247 | pm_message_t pmm = { .event = PM_EVENT_SUSPEND }; | |
1248 | if (state == VGA_SWITCHEROO_ON) { | |
a70491cc | 1249 | pr_info("switched on\n"); |
5bcf719b | 1250 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; |
6a9ee8af DA |
1251 | /* i915 resume handler doesn't set to D0 */ |
1252 | pci_set_power_state(dev->pdev, PCI_D0); | |
1253 | i915_resume(dev); | |
5bcf719b | 1254 | dev->switch_power_state = DRM_SWITCH_POWER_ON; |
6a9ee8af | 1255 | } else { |
a70491cc | 1256 | pr_err("switched off\n"); |
5bcf719b | 1257 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; |
6a9ee8af | 1258 | i915_suspend(dev, pmm); |
5bcf719b | 1259 | dev->switch_power_state = DRM_SWITCH_POWER_OFF; |
6a9ee8af DA |
1260 | } |
1261 | } | |
1262 | ||
1263 | static bool i915_switcheroo_can_switch(struct pci_dev *pdev) | |
1264 | { | |
1265 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1266 | bool can_switch; | |
1267 | ||
1268 | spin_lock(&dev->count_lock); | |
1269 | can_switch = (dev->open_count == 0); | |
1270 | spin_unlock(&dev->count_lock); | |
1271 | return can_switch; | |
1272 | } | |
1273 | ||
26ec685f TI |
1274 | static const struct vga_switcheroo_client_ops i915_switcheroo_ops = { |
1275 | .set_gpu_state = i915_switcheroo_set_state, | |
1276 | .reprobe = NULL, | |
1277 | .can_switch = i915_switcheroo_can_switch, | |
1278 | }; | |
1279 | ||
2c7111db CW |
1280 | static int i915_load_modeset_init(struct drm_device *dev) |
1281 | { | |
1282 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1283 | int ret; | |
79e53945 | 1284 | |
6d139a87 | 1285 | ret = intel_parse_bios(dev); |
79e53945 JB |
1286 | if (ret) |
1287 | DRM_INFO("failed to find VBIOS tables\n"); | |
1288 | ||
934f992c CW |
1289 | /* If we have > 1 VGA cards, then we need to arbitrate access |
1290 | * to the common VGA resources. | |
1291 | * | |
1292 | * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA), | |
1293 | * then we do not take part in VGA arbitration and the | |
1294 | * vga_client_register() fails with -ENODEV. | |
1295 | */ | |
28d52043 | 1296 | ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode); |
934f992c | 1297 | if (ret && ret != -ENODEV) |
2c7111db | 1298 | goto out; |
28d52043 | 1299 | |
723bfd70 JB |
1300 | intel_register_dsm_handler(); |
1301 | ||
26ec685f | 1302 | ret = vga_switcheroo_register_client(dev->pdev, &i915_switcheroo_ops); |
6a9ee8af | 1303 | if (ret) |
5a79395b | 1304 | goto cleanup_vga_client; |
6a9ee8af | 1305 | |
9797fbfb CW |
1306 | /* Initialise stolen first so that we may reserve preallocated |
1307 | * objects for the BIOS to KMS transition. | |
1308 | */ | |
1309 | ret = i915_gem_init_stolen(dev); | |
1310 | if (ret) | |
1311 | goto cleanup_vga_switcheroo; | |
1312 | ||
b01f2c3a JB |
1313 | intel_modeset_init(dev); |
1314 | ||
1070a42b | 1315 | ret = i915_gem_init(dev); |
79e53945 | 1316 | if (ret) |
9797fbfb | 1317 | goto cleanup_gem_stolen; |
79e53945 | 1318 | |
2c7111db CW |
1319 | intel_modeset_gem_init(dev); |
1320 | ||
1321 | ret = drm_irq_install(dev); | |
1322 | if (ret) | |
1323 | goto cleanup_gem; | |
1324 | ||
79e53945 JB |
1325 | /* Always safe in the mode setting case. */ |
1326 | /* FIXME: do pre/post-mode set stuff in core KMS code */ | |
1327 | dev->vblank_disable_allowed = 1; | |
1328 | ||
5a79395b CW |
1329 | ret = intel_fbdev_init(dev); |
1330 | if (ret) | |
1331 | goto cleanup_irq; | |
1332 | ||
eb1f8e4f | 1333 | drm_kms_helper_poll_init(dev); |
87acb0a5 CW |
1334 | |
1335 | /* We're off and running w/KMS */ | |
1336 | dev_priv->mm.suspended = 0; | |
1337 | ||
79e53945 JB |
1338 | return 0; |
1339 | ||
5a79395b CW |
1340 | cleanup_irq: |
1341 | drm_irq_uninstall(dev); | |
2c7111db CW |
1342 | cleanup_gem: |
1343 | mutex_lock(&dev->struct_mutex); | |
1344 | i915_gem_cleanup_ringbuffer(dev); | |
1345 | mutex_unlock(&dev->struct_mutex); | |
1d2a314c | 1346 | i915_gem_cleanup_aliasing_ppgtt(dev); |
9797fbfb CW |
1347 | cleanup_gem_stolen: |
1348 | i915_gem_cleanup_stolen(dev); | |
5a79395b CW |
1349 | cleanup_vga_switcheroo: |
1350 | vga_switcheroo_unregister_client(dev->pdev); | |
1351 | cleanup_vga_client: | |
1352 | vga_client_register(dev->pdev, NULL, NULL, NULL); | |
79e53945 JB |
1353 | out: |
1354 | return ret; | |
1355 | } | |
1356 | ||
7c1c2871 DA |
1357 | int i915_master_create(struct drm_device *dev, struct drm_master *master) |
1358 | { | |
1359 | struct drm_i915_master_private *master_priv; | |
1360 | ||
9a298b2a | 1361 | master_priv = kzalloc(sizeof(*master_priv), GFP_KERNEL); |
7c1c2871 DA |
1362 | if (!master_priv) |
1363 | return -ENOMEM; | |
1364 | ||
1365 | master->driver_priv = master_priv; | |
1366 | return 0; | |
1367 | } | |
1368 | ||
1369 | void i915_master_destroy(struct drm_device *dev, struct drm_master *master) | |
1370 | { | |
1371 | struct drm_i915_master_private *master_priv = master->driver_priv; | |
1372 | ||
1373 | if (!master_priv) | |
1374 | return; | |
1375 | ||
9a298b2a | 1376 | kfree(master_priv); |
7c1c2871 DA |
1377 | |
1378 | master->driver_priv = NULL; | |
1379 | } | |
1380 | ||
e2b665c4 AJ |
1381 | static void |
1382 | i915_mtrr_setup(struct drm_i915_private *dev_priv, unsigned long base, | |
1383 | unsigned long size) | |
1384 | { | |
23f54bea CW |
1385 | dev_priv->mm.gtt_mtrr = -1; |
1386 | ||
9e984bc1 AJ |
1387 | #if defined(CONFIG_X86_PAT) |
1388 | if (cpu_has_pat) | |
1389 | return; | |
1390 | #endif | |
1391 | ||
e2b665c4 AJ |
1392 | /* Set up a WC MTRR for non-PAT systems. This is more common than |
1393 | * one would think, because the kernel disables PAT on first | |
1394 | * generation Core chips because WC PAT gets overridden by a UC | |
1395 | * MTRR if present. Even if a UC MTRR isn't present. | |
1396 | */ | |
1397 | dev_priv->mm.gtt_mtrr = mtrr_add(base, size, MTRR_TYPE_WRCOMB, 1); | |
1398 | if (dev_priv->mm.gtt_mtrr < 0) { | |
1399 | DRM_INFO("MTRR allocation failed. Graphics " | |
1400 | "performance may suffer.\n"); | |
1401 | } | |
1402 | } | |
1403 | ||
9f846a16 DV |
1404 | static void i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv) |
1405 | { | |
1406 | struct apertures_struct *ap; | |
1407 | struct pci_dev *pdev = dev_priv->dev->pdev; | |
1408 | bool primary; | |
1409 | ||
1410 | ap = alloc_apertures(1); | |
1411 | if (!ap) | |
1412 | return; | |
1413 | ||
1414 | ap->ranges[0].base = dev_priv->dev->agp->base; | |
1415 | ap->ranges[0].size = | |
1416 | dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT; | |
1417 | primary = | |
1418 | pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW; | |
1419 | ||
1420 | remove_conflicting_framebuffers(ap, "inteldrmfb", primary); | |
1421 | ||
1422 | kfree(ap); | |
1423 | } | |
1424 | ||
79e53945 JB |
1425 | /** |
1426 | * i915_driver_load - setup chip and create an initial config | |
1427 | * @dev: DRM device | |
1428 | * @flags: startup flags | |
1429 | * | |
1430 | * The driver load routine has to do several things: | |
1431 | * - drive output discovery via intel_modeset_init() | |
1432 | * - initialize the memory manager | |
1433 | * - allocate initial config memory | |
1434 | * - setup the DRM framebuffer with the allocated memory | |
1435 | */ | |
84b1fd10 | 1436 | int i915_driver_load(struct drm_device *dev, unsigned long flags) |
22eae947 | 1437 | { |
ea059a1e | 1438 | struct drm_i915_private *dev_priv; |
26394d92 | 1439 | struct intel_device_info *info; |
cfdf1fa2 | 1440 | int ret = 0, mmio_bar; |
9021f284 | 1441 | uint32_t aperture_size; |
fe669bf8 | 1442 | |
26394d92 DV |
1443 | info = (struct intel_device_info *) flags; |
1444 | ||
1445 | /* Refuse to load on gen6+ without kms enabled. */ | |
1446 | if (info->gen >= 6 && !drm_core_check_feature(dev, DRIVER_MODESET)) | |
1447 | return -ENODEV; | |
1448 | ||
fe669bf8 | 1449 | |
22eae947 DA |
1450 | /* i915 has 4 more counters */ |
1451 | dev->counters += 4; | |
1452 | dev->types[6] = _DRM_STAT_IRQ; | |
1453 | dev->types[7] = _DRM_STAT_PRIMARY; | |
1454 | dev->types[8] = _DRM_STAT_SECONDARY; | |
1455 | dev->types[9] = _DRM_STAT_DMA; | |
1456 | ||
9a298b2a | 1457 | dev_priv = kzalloc(sizeof(drm_i915_private_t), GFP_KERNEL); |
ba8bbcf6 JB |
1458 | if (dev_priv == NULL) |
1459 | return -ENOMEM; | |
1460 | ||
ba8bbcf6 | 1461 | dev->dev_private = (void *)dev_priv; |
673a394b | 1462 | dev_priv->dev = dev; |
26394d92 | 1463 | dev_priv->info = info; |
ba8bbcf6 | 1464 | |
ec2a4c3f DA |
1465 | if (i915_get_bridge_dev(dev)) { |
1466 | ret = -EIO; | |
1467 | goto free_priv; | |
1468 | } | |
1469 | ||
9f846a16 DV |
1470 | dev_priv->mm.gtt = intel_gtt_get(); |
1471 | if (!dev_priv->mm.gtt) { | |
1472 | DRM_ERROR("Failed to initialize GTT\n"); | |
1473 | ret = -ENODEV; | |
1474 | goto put_bridge; | |
1475 | } | |
1476 | ||
1477 | i915_kick_out_firmware_fb(dev_priv); | |
1478 | ||
466e69b8 DA |
1479 | pci_set_master(dev->pdev); |
1480 | ||
9f82d238 DV |
1481 | /* overlay on gen2 is broken and can't address above 1G */ |
1482 | if (IS_GEN2(dev)) | |
1483 | dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30)); | |
1484 | ||
6927faf3 JN |
1485 | /* 965GM sometimes incorrectly writes to hardware status page (HWS) |
1486 | * using 32bit addressing, overwriting memory if HWS is located | |
1487 | * above 4GB. | |
1488 | * | |
1489 | * The documentation also mentions an issue with undefined | |
1490 | * behaviour if any general state is accessed within a page above 4GB, | |
1491 | * which also needs to be handled carefully. | |
1492 | */ | |
1493 | if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) | |
1494 | dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(32)); | |
1495 | ||
b4ce0f85 CW |
1496 | mmio_bar = IS_GEN2(dev) ? 1 : 0; |
1497 | dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, 0); | |
1498 | if (!dev_priv->regs) { | |
1499 | DRM_ERROR("failed to map registers\n"); | |
1500 | ret = -EIO; | |
1501 | goto put_bridge; | |
1502 | } | |
1503 | ||
9021f284 | 1504 | aperture_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT; |
71e9339c | 1505 | |
0206e353 | 1506 | dev_priv->mm.gtt_mapping = |
9021f284 | 1507 | io_mapping_create_wc(dev->agp->base, aperture_size); |
6644107d VP |
1508 | if (dev_priv->mm.gtt_mapping == NULL) { |
1509 | ret = -EIO; | |
1510 | goto out_rmmap; | |
1511 | } | |
1512 | ||
9021f284 | 1513 | i915_mtrr_setup(dev_priv, dev->agp->base, aperture_size); |
19966754 | 1514 | |
e642abbf CW |
1515 | /* The i915 workqueue is primarily used for batched retirement of |
1516 | * requests (and thus managing bo) once the task has been completed | |
1517 | * by the GPU. i915_gem_retire_requests() is called directly when we | |
1518 | * need high-priority retirement, such as waiting for an explicit | |
1519 | * bo. | |
1520 | * | |
1521 | * It is also used for periodic low-priority events, such as | |
df9c2042 | 1522 | * idle-timers and recording error state. |
e642abbf CW |
1523 | * |
1524 | * All tasks on the workqueue are expected to acquire the dev mutex | |
1525 | * so there is no point in running more than one instance of the | |
1526 | * workqueue at any time: max_active = 1 and NON_REENTRANT. | |
1527 | */ | |
1528 | dev_priv->wq = alloc_workqueue("i915", | |
1529 | WQ_UNBOUND | WQ_NON_REENTRANT, | |
1530 | 1); | |
9c9fe1f8 EA |
1531 | if (dev_priv->wq == NULL) { |
1532 | DRM_ERROR("Failed to create our workqueue.\n"); | |
1533 | ret = -ENOMEM; | |
a7b85d2a | 1534 | goto out_mtrrfree; |
9c9fe1f8 EA |
1535 | } |
1536 | ||
f71d4af4 | 1537 | intel_irq_init(dev); |
9880b7a5 | 1538 | |
c4804411 ZW |
1539 | /* Try to make sure MCHBAR is enabled before poking at it */ |
1540 | intel_setup_mchbar(dev); | |
f899fc64 | 1541 | intel_setup_gmbus(dev); |
44834a67 | 1542 | intel_opregion_setup(dev); |
c4804411 | 1543 | |
6d139a87 BF |
1544 | /* Make sure the bios did its job and set up vital registers */ |
1545 | intel_setup_bios(dev); | |
1546 | ||
673a394b EA |
1547 | i915_gem_load(dev); |
1548 | ||
398c9cb2 KP |
1549 | /* Init HWS */ |
1550 | if (!I915_NEED_GFX_HWS(dev)) { | |
1551 | ret = i915_init_phys_hws(dev); | |
56e2ea34 CW |
1552 | if (ret) |
1553 | goto out_gem_unload; | |
398c9cb2 | 1554 | } |
ed4cb414 EA |
1555 | |
1556 | /* On the 945G/GM, the chipset reports the MSI capability on the | |
1557 | * integrated graphics even though the support isn't actually there | |
1558 | * according to the published specs. It doesn't appear to function | |
1559 | * correctly in testing on 945G. | |
1560 | * This may be a side effect of MSI having been made available for PEG | |
1561 | * and the registers being closely associated. | |
d1ed629f KP |
1562 | * |
1563 | * According to chipset errata, on the 965GM, MSI interrupts may | |
b60678a7 KP |
1564 | * be lost or delayed, but we use them anyways to avoid |
1565 | * stuck interrupts on some machines. | |
ed4cb414 | 1566 | */ |
b60678a7 | 1567 | if (!IS_I945G(dev) && !IS_I945GM(dev)) |
d3e74d02 | 1568 | pci_enable_msi(dev->pdev); |
ed4cb414 | 1569 | |
9f1f46a4 | 1570 | spin_lock_init(&dev_priv->gt_lock); |
1ec14ad3 | 1571 | spin_lock_init(&dev_priv->irq_lock); |
63eeaf38 | 1572 | spin_lock_init(&dev_priv->error_lock); |
4912d041 | 1573 | spin_lock_init(&dev_priv->rps_lock); |
ed4cb414 | 1574 | |
c51ed787 | 1575 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) |
27f8227b JB |
1576 | dev_priv->num_pipe = 3; |
1577 | else if (IS_MOBILE(dev) || !IS_GEN2(dev)) | |
9db4a9c7 JB |
1578 | dev_priv->num_pipe = 2; |
1579 | else | |
1580 | dev_priv->num_pipe = 1; | |
1581 | ||
1582 | ret = drm_vblank_init(dev, dev_priv->num_pipe); | |
56e2ea34 CW |
1583 | if (ret) |
1584 | goto out_gem_unload; | |
52440211 | 1585 | |
11ed50ec BG |
1586 | /* Start out suspended */ |
1587 | dev_priv->mm.suspended = 1; | |
1588 | ||
3bad0781 ZW |
1589 | intel_detect_pch(dev); |
1590 | ||
79e53945 | 1591 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
53984635 | 1592 | ret = i915_load_modeset_init(dev); |
79e53945 JB |
1593 | if (ret < 0) { |
1594 | DRM_ERROR("failed to init modeset\n"); | |
56e2ea34 | 1595 | goto out_gem_unload; |
79e53945 JB |
1596 | } |
1597 | } | |
1598 | ||
0136db58 BW |
1599 | i915_setup_sysfs(dev); |
1600 | ||
74a365b3 | 1601 | /* Must be done after probing outputs */ |
44834a67 CW |
1602 | intel_opregion_init(dev); |
1603 | acpi_video_register(); | |
74a365b3 | 1604 | |
f65d9421 BG |
1605 | setup_timer(&dev_priv->hangcheck_timer, i915_hangcheck_elapsed, |
1606 | (unsigned long) dev); | |
7648fa99 | 1607 | |
eb48eb00 DV |
1608 | if (IS_GEN5(dev)) |
1609 | intel_gpu_ips_init(dev_priv); | |
63ee41d7 | 1610 | |
79e53945 JB |
1611 | return 0; |
1612 | ||
56e2ea34 | 1613 | out_gem_unload: |
a7b85d2a KP |
1614 | if (dev_priv->mm.inactive_shrinker.shrink) |
1615 | unregister_shrinker(&dev_priv->mm.inactive_shrinker); | |
1616 | ||
56e2ea34 CW |
1617 | if (dev->pdev->msi_enabled) |
1618 | pci_disable_msi(dev->pdev); | |
1619 | ||
1620 | intel_teardown_gmbus(dev); | |
1621 | intel_teardown_mchbar(dev); | |
9c9fe1f8 | 1622 | destroy_workqueue(dev_priv->wq); |
a7b85d2a KP |
1623 | out_mtrrfree: |
1624 | if (dev_priv->mm.gtt_mtrr >= 0) { | |
1625 | mtrr_del(dev_priv->mm.gtt_mtrr, dev->agp->base, | |
1626 | dev->agp->agp_info.aper_size * 1024 * 1024); | |
1627 | dev_priv->mm.gtt_mtrr = -1; | |
1628 | } | |
6644107d | 1629 | io_mapping_free(dev_priv->mm.gtt_mapping); |
79e53945 | 1630 | out_rmmap: |
6dda569f | 1631 | pci_iounmap(dev->pdev, dev_priv->regs); |
ec2a4c3f DA |
1632 | put_bridge: |
1633 | pci_dev_put(dev_priv->bridge_dev); | |
79e53945 | 1634 | free_priv: |
9a298b2a | 1635 | kfree(dev_priv); |
ba8bbcf6 JB |
1636 | return ret; |
1637 | } | |
1638 | ||
1639 | int i915_driver_unload(struct drm_device *dev) | |
1640 | { | |
1641 | struct drm_i915_private *dev_priv = dev->dev_private; | |
c911fc1c | 1642 | int ret; |
ba8bbcf6 | 1643 | |
eb48eb00 | 1644 | intel_gpu_ips_teardown(); |
7648fa99 | 1645 | |
0136db58 BW |
1646 | i915_teardown_sysfs(dev); |
1647 | ||
17250b71 CW |
1648 | if (dev_priv->mm.inactive_shrinker.shrink) |
1649 | unregister_shrinker(&dev_priv->mm.inactive_shrinker); | |
1650 | ||
c911fc1c | 1651 | mutex_lock(&dev->struct_mutex); |
b2da9fe5 | 1652 | ret = i915_gpu_idle(dev); |
c911fc1c DV |
1653 | if (ret) |
1654 | DRM_ERROR("failed to idle hardware: %d\n", ret); | |
b2da9fe5 | 1655 | i915_gem_retire_requests(dev); |
c911fc1c DV |
1656 | mutex_unlock(&dev->struct_mutex); |
1657 | ||
75ef9da2 DV |
1658 | /* Cancel the retire work handler, which should be idle now. */ |
1659 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); | |
1660 | ||
ab657db1 EA |
1661 | io_mapping_free(dev_priv->mm.gtt_mapping); |
1662 | if (dev_priv->mm.gtt_mtrr >= 0) { | |
1663 | mtrr_del(dev_priv->mm.gtt_mtrr, dev->agp->base, | |
1664 | dev->agp->agp_info.aper_size * 1024 * 1024); | |
1665 | dev_priv->mm.gtt_mtrr = -1; | |
1666 | } | |
1667 | ||
44834a67 CW |
1668 | acpi_video_unregister(); |
1669 | ||
79e53945 | 1670 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
7b4f3990 | 1671 | intel_fbdev_fini(dev); |
3d8620cc JB |
1672 | intel_modeset_cleanup(dev); |
1673 | ||
6363ee6f ZY |
1674 | /* |
1675 | * free the memory space allocated for the child device | |
1676 | * config parsed from VBT | |
1677 | */ | |
1678 | if (dev_priv->child_dev && dev_priv->child_dev_num) { | |
1679 | kfree(dev_priv->child_dev); | |
1680 | dev_priv->child_dev = NULL; | |
1681 | dev_priv->child_dev_num = 0; | |
1682 | } | |
6c0d9350 | 1683 | |
6a9ee8af | 1684 | vga_switcheroo_unregister_client(dev->pdev); |
28d52043 | 1685 | vga_client_register(dev->pdev, NULL, NULL, NULL); |
79e53945 JB |
1686 | } |
1687 | ||
a8b4899e | 1688 | /* Free error state after interrupts are fully disabled. */ |
bc0c7f14 DV |
1689 | del_timer_sync(&dev_priv->hangcheck_timer); |
1690 | cancel_work_sync(&dev_priv->error_work); | |
a8b4899e | 1691 | i915_destroy_error_state(dev); |
bc0c7f14 | 1692 | |
ed4cb414 EA |
1693 | if (dev->pdev->msi_enabled) |
1694 | pci_disable_msi(dev->pdev); | |
1695 | ||
44834a67 | 1696 | intel_opregion_fini(dev); |
8ee1c3db | 1697 | |
79e53945 | 1698 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
67e77c5a DV |
1699 | /* Flush any outstanding unpin_work. */ |
1700 | flush_workqueue(dev_priv->wq); | |
1701 | ||
79e53945 | 1702 | mutex_lock(&dev->struct_mutex); |
ecbec53b | 1703 | i915_gem_free_all_phys_object(dev); |
79e53945 JB |
1704 | i915_gem_cleanup_ringbuffer(dev); |
1705 | mutex_unlock(&dev->struct_mutex); | |
1d2a314c | 1706 | i915_gem_cleanup_aliasing_ppgtt(dev); |
9797fbfb | 1707 | i915_gem_cleanup_stolen(dev); |
fe669bf8 | 1708 | drm_mm_takedown(&dev_priv->mm.stolen); |
02e792fb DV |
1709 | |
1710 | intel_cleanup_overlay(dev); | |
c2873e96 KP |
1711 | |
1712 | if (!I915_NEED_GFX_HWS(dev)) | |
1713 | i915_free_hws(dev); | |
79e53945 JB |
1714 | } |
1715 | ||
701394cc | 1716 | if (dev_priv->regs != NULL) |
6dda569f | 1717 | pci_iounmap(dev->pdev, dev_priv->regs); |
701394cc | 1718 | |
f899fc64 | 1719 | intel_teardown_gmbus(dev); |
c4804411 ZW |
1720 | intel_teardown_mchbar(dev); |
1721 | ||
bc0c7f14 DV |
1722 | destroy_workqueue(dev_priv->wq); |
1723 | ||
ec2a4c3f | 1724 | pci_dev_put(dev_priv->bridge_dev); |
9a298b2a | 1725 | kfree(dev->dev_private); |
ba8bbcf6 | 1726 | |
22eae947 DA |
1727 | return 0; |
1728 | } | |
1729 | ||
f787a5f5 | 1730 | int i915_driver_open(struct drm_device *dev, struct drm_file *file) |
673a394b | 1731 | { |
f787a5f5 | 1732 | struct drm_i915_file_private *file_priv; |
673a394b | 1733 | |
8a4c47f3 | 1734 | DRM_DEBUG_DRIVER("\n"); |
f787a5f5 CW |
1735 | file_priv = kmalloc(sizeof(*file_priv), GFP_KERNEL); |
1736 | if (!file_priv) | |
673a394b EA |
1737 | return -ENOMEM; |
1738 | ||
f787a5f5 | 1739 | file->driver_priv = file_priv; |
673a394b | 1740 | |
1c25595f | 1741 | spin_lock_init(&file_priv->mm.lock); |
f787a5f5 | 1742 | INIT_LIST_HEAD(&file_priv->mm.request_list); |
673a394b EA |
1743 | |
1744 | return 0; | |
1745 | } | |
1746 | ||
79e53945 JB |
1747 | /** |
1748 | * i915_driver_lastclose - clean up after all DRM clients have exited | |
1749 | * @dev: DRM device | |
1750 | * | |
1751 | * Take care of cleaning up after all DRM clients have exited. In the | |
1752 | * mode setting case, we want to restore the kernel's initial mode (just | |
1753 | * in case the last client left us in a bad state). | |
1754 | * | |
9021f284 | 1755 | * Additionally, in the non-mode setting case, we'll tear down the GTT |
79e53945 JB |
1756 | * and DMA structures, since the kernel won't be using them, and clea |
1757 | * up any GEM state. | |
1758 | */ | |
84b1fd10 | 1759 | void i915_driver_lastclose(struct drm_device * dev) |
1da177e4 | 1760 | { |
ba8bbcf6 JB |
1761 | drm_i915_private_t *dev_priv = dev->dev_private; |
1762 | ||
79e53945 | 1763 | if (!dev_priv || drm_core_check_feature(dev, DRIVER_MODESET)) { |
e8e7a2b8 | 1764 | intel_fb_restore_mode(dev); |
6a9ee8af | 1765 | vga_switcheroo_process_delayed_switch(); |
144a75fa | 1766 | return; |
79e53945 | 1767 | } |
144a75fa | 1768 | |
673a394b EA |
1769 | i915_gem_lastclose(dev); |
1770 | ||
b5e89ed5 | 1771 | i915_dma_cleanup(dev); |
1da177e4 LT |
1772 | } |
1773 | ||
6c340eac | 1774 | void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv) |
1da177e4 | 1775 | { |
b962442e | 1776 | i915_gem_release(dev, file_priv); |
1da177e4 LT |
1777 | } |
1778 | ||
f787a5f5 | 1779 | void i915_driver_postclose(struct drm_device *dev, struct drm_file *file) |
673a394b | 1780 | { |
f787a5f5 | 1781 | struct drm_i915_file_private *file_priv = file->driver_priv; |
673a394b | 1782 | |
f787a5f5 | 1783 | kfree(file_priv); |
673a394b EA |
1784 | } |
1785 | ||
c153f45f | 1786 | struct drm_ioctl_desc i915_ioctls[] = { |
1b2f1489 DA |
1787 | DRM_IOCTL_DEF_DRV(I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
1788 | DRM_IOCTL_DEF_DRV(I915_FLUSH, i915_flush_ioctl, DRM_AUTH), | |
1789 | DRM_IOCTL_DEF_DRV(I915_FLIP, i915_flip_bufs, DRM_AUTH), | |
1790 | DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH), | |
1791 | DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH), | |
1792 | DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH), | |
1793 | DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH), | |
1794 | DRM_IOCTL_DEF_DRV(I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
b2c606fe DV |
1795 | DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH), |
1796 | DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH), | |
1797 | DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
1b2f1489 | 1798 | DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH), |
b2c606fe | 1799 | DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
d1c1edbc | 1800 | DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
1b2f1489 DA |
1801 | DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, i915_vblank_pipe_get, DRM_AUTH), |
1802 | DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH), | |
1803 | DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
1804 | DRM_IOCTL_DEF_DRV(I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED), | |
1805 | DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH|DRM_UNLOCKED), | |
1806 | DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_UNLOCKED), | |
1807 | DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED), | |
1808 | DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED), | |
1809 | DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED), | |
1810 | DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_UNLOCKED), | |
1811 | DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED), | |
1812 | DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED), | |
1813 | DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_UNLOCKED), | |
1814 | DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED), | |
1815 | DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED), | |
1816 | DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_UNLOCKED), | |
1817 | DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED), | |
1818 | DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED), | |
1819 | DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED), | |
1820 | DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_UNLOCKED), | |
1821 | DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_UNLOCKED), | |
1822 | DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED), | |
1823 | DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED), | |
1824 | DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED), | |
1825 | DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED), | |
1826 | DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED), | |
8ea30864 JB |
1827 | DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED), |
1828 | DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, intel_sprite_get_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED), | |
c94f7029 DA |
1829 | }; |
1830 | ||
1831 | int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls); | |
cda17380 | 1832 | |
9021f284 DV |
1833 | /* |
1834 | * This is really ugly: Because old userspace abused the linux agp interface to | |
1835 | * manage the gtt, we need to claim that all intel devices are agp. For | |
1836 | * otherwise the drm core refuses to initialize the agp support code. | |
cda17380 | 1837 | */ |
84b1fd10 | 1838 | int i915_driver_device_is_agp(struct drm_device * dev) |
cda17380 DA |
1839 | { |
1840 | return 1; | |
1841 | } |