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drm/i915: extract dri1 breadcrumb update from irq handler
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_dma.c
CommitLineData
1da177e4
LT		 1/* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
2 */
0d6aa60b 3/*
1da177e4
LT		 4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
bc54fd1a
DA		 6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
0d6aa60b 27 */
1da177e4 28
a70491cc
JP		 29#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
1da177e4
LT		 31#include "drmP.h"
32#include "drm.h"
79e53945 33#include "drm_crtc_helper.h"
785b93ef 34#include "drm_fb_helper.h"
79e53945 35#include "intel_drv.h"
1da177e4
LT		 36#include "i915_drm.h"
37#include "i915_drv.h"
1c5d22f7 38#include "i915_trace.h"
63ee41d7 39#include "../../../platform/x86/intel_ips.h"
dcdb1674 40#include <linux/pci.h>
28d52043 41#include <linux/vgaarb.h>
c4804411
ZW		 42#include <linux/acpi.h>
43#include <linux/pnp.h>
6a9ee8af 44#include <linux/vga_switcheroo.h>
5a0e3ad6 45#include <linux/slab.h>
e0cd3608 46#include <linux/module.h>
44834a67 47#include <acpi/video.h>
9e984bc1 48#include <asm/pat.h>
1da177e4 49
d05c617e
DV		 50void i915_update_dri1_breadcrumb(struct drm_device *dev)
51{
52 drm_i915_private_t *dev_priv = dev->dev_private;
53 struct drm_i915_master_private *master_priv;
54
55 if (dev->primary->master) {
56 master_priv = dev->primary->master->driver_priv;
57 if (master_priv->sarea_priv)
58 master_priv->sarea_priv->last_dispatch =
59 READ_BREADCRUMB(dev_priv);
60 }
61}
62
4cbf74cc
CW		 63static void i915_write_hws_pga(struct drm_device *dev)
64{
65 drm_i915_private_t *dev_priv = dev->dev_private;
66 u32 addr;
67
68 addr = dev_priv->status_page_dmah->busaddr;
69 if (INTEL_INFO(dev)->gen >= 4)
70 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
71 I915_WRITE(HWS_PGA, addr);
72}
73
398c9cb2
KP		 74/**
75 * Sets up the hardware status page for devices that need a physical address
76 * in the register.
77 */
3043c60c 78static int i915_init_phys_hws(struct drm_device *dev)
398c9cb2
KP		 79{
80 drm_i915_private_t *dev_priv = dev->dev_private;
1ec14ad3 81
398c9cb2
KP		 82 /* Program Hardware Status Page */
83 dev_priv->status_page_dmah =
e6be8d9d 84 drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE);
398c9cb2
KP		 85
86 if (!dev_priv->status_page_dmah) {
87 DRM_ERROR("Can not allocate hardware status page\n");
88 return -ENOMEM;
89 }
398c9cb2 90
f3234706
KP		 91 memset_io((void __force __iomem *)dev_priv->status_page_dmah->vaddr,
92 0, PAGE_SIZE);
398c9cb2 93
4cbf74cc 94 i915_write_hws_pga(dev);
9b974cc1 95
8a4c47f3 96 DRM_DEBUG_DRIVER("Enabled hardware status page\n");
398c9cb2
KP		 97 return 0;
98}
99
100/**
101 * Frees the hardware status page, whether it's a physical address or a virtual
102 * address set up by the X Server.
103 */
3043c60c 104static void i915_free_hws(struct drm_device *dev)
398c9cb2
KP		 105{
106 drm_i915_private_t *dev_priv = dev->dev_private;
1ec14ad3
CW		 107 struct intel_ring_buffer *ring = LP_RING(dev_priv);
108
398c9cb2
KP		 109 if (dev_priv->status_page_dmah) {
110 drm_pci_free(dev, dev_priv->status_page_dmah);
111 dev_priv->status_page_dmah = NULL;
112 }
113
1ec14ad3
CW		 114 if (ring->status_page.gfx_addr) {
115 ring->status_page.gfx_addr = 0;
398c9cb2
KP		 116 drm_core_ioremapfree(&dev_priv->hws_map, dev);
117 }
118
119 /* Need to rewrite hardware status page */
120 I915_WRITE(HWS_PGA, 0x1ffff000);
121}
122
84b1fd10 123void i915_kernel_lost_context(struct drm_device * dev)
1da177e4
LT		 124{
125 drm_i915_private_t *dev_priv = dev->dev_private;
7c1c2871 126 struct drm_i915_master_private *master_priv;
1ec14ad3 127 struct intel_ring_buffer *ring = LP_RING(dev_priv);
1da177e4 128
79e53945
JB		 129 /*
130 * We should never lose context on the ring with modesetting
131 * as we don't expose it to userspace
132 */
133 if (drm_core_check_feature(dev, DRIVER_MODESET))
134 return;
135
8168bd48
CW		 136 ring->head = I915_READ_HEAD(ring) & HEAD_ADDR;
137 ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
1da177e4
LT		 138 ring->space = ring->head - (ring->tail + 8);
139 if (ring->space < 0)
8187a2b7 140 ring->space += ring->size;
1da177e4 141
7c1c2871
DA		 142 if (!dev->primary->master)
143 return;
144
145 master_priv = dev->primary->master->driver_priv;
146 if (ring->head == ring->tail && master_priv->sarea_priv)
147 master_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
1da177e4
LT		 148}
149
84b1fd10 150static int i915_dma_cleanup(struct drm_device * dev)
1da177e4 151{
ba8bbcf6 152 drm_i915_private_t *dev_priv = dev->dev_private;
1ec14ad3
CW		 153 int i;
154
1da177e4
LT		 155 /* Make sure interrupts are disabled here because the uninstall ioctl
156 * may not have been called from userspace and after dev_private
157 * is freed, it's too late.
158 */
ed4cb414 159 if (dev->irq_enabled)
b5e89ed5 160 drm_irq_uninstall(dev);
1da177e4 161
ee0c6bfb 162 mutex_lock(&dev->struct_mutex);
1ec14ad3
CW		 163 for (i = 0; i < I915_NUM_RINGS; i++)
164 intel_cleanup_ring_buffer(&dev_priv->ring[i]);
ee0c6bfb 165 mutex_unlock(&dev->struct_mutex);
dc7a9319 166
398c9cb2
KP		 167 /* Clear the HWS virtual address at teardown */
168 if (I915_NEED_GFX_HWS(dev))
169 i915_free_hws(dev);
1da177e4
LT		 170
171 return 0;
172}
173
ba8bbcf6 174static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
1da177e4 175{
ba8bbcf6 176 drm_i915_private_t *dev_priv = dev->dev_private;
7c1c2871 177 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
e8616b6c 178 int ret;
1da177e4 179
3a03ac1a
DA		 180 master_priv->sarea = drm_getsarea(dev);
181 if (master_priv->sarea) {
182 master_priv->sarea_priv = (drm_i915_sarea_t *)
183 ((u8 *)master_priv->sarea->handle + init->sarea_priv_offset);
184 } else {
8a4c47f3 185 DRM_DEBUG_DRIVER("sarea not found assuming DRI2 userspace\n");
3a03ac1a
DA		 186 }
187
673a394b 188 if (init->ring_size != 0) {
e8616b6c 189 if (LP_RING(dev_priv)->obj != NULL) {
673a394b
EA		 190 i915_dma_cleanup(dev);
191 DRM_ERROR("Client tried to initialize ringbuffer in "
192 "GEM mode\n");
193 return -EINVAL;
194 }
1da177e4 195
e8616b6c
CW		 196 ret = intel_render_ring_init_dri(dev,
197 init->ring_start,
198 init->ring_size);
199 if (ret) {
673a394b 200 i915_dma_cleanup(dev);
e8616b6c 201 return ret;
673a394b 202 }
1da177e4
LT		 203 }
204
a6b54f3f 205 dev_priv->cpp = init->cpp;
1da177e4
LT		 206 dev_priv->back_offset = init->back_offset;
207 dev_priv->front_offset = init->front_offset;
208 dev_priv->current_page = 0;
7c1c2871
DA		 209 if (master_priv->sarea_priv)
210 master_priv->sarea_priv->pf_current_page = 0;
1da177e4 211
1da177e4
LT		 212 /* Allow hardware batchbuffers unless told otherwise.
213 */
8781342d 214 dev_priv->dri1.allow_batchbuffer = 1;
1da177e4 215
1da177e4
LT		 216 return 0;
217}
218
84b1fd10 219static int i915_dma_resume(struct drm_device * dev)
1da177e4
LT		 220{
221 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1ec14ad3 222 struct intel_ring_buffer *ring = LP_RING(dev_priv);
1da177e4 223
8a4c47f3 224 DRM_DEBUG_DRIVER("%s\n", __func__);
1da177e4 225
8187a2b7 226 if (ring->map.handle == NULL) {
1da177e4
LT		 227 DRM_ERROR("can not ioremap virtual address for"
228 " ring buffer\n");
20caafa6 229 return -ENOMEM;
1da177e4
LT		 230 }
231
232 /* Program Hardware Status Page */
8187a2b7 233 if (!ring->status_page.page_addr) {
1da177e4 234 DRM_ERROR("Can not find hardware status page\n");
20caafa6 235 return -EINVAL;
1da177e4 236 }
8a4c47f3 237 DRM_DEBUG_DRIVER("hw status page @ %p\n",
8187a2b7
ZN		 238 ring->status_page.page_addr);
239 if (ring->status_page.gfx_addr != 0)
78501eac 240 intel_ring_setup_status_page(ring);
dc7a9319 241 else
4cbf74cc 242 i915_write_hws_pga(dev);
8187a2b7 243
8a4c47f3 244 DRM_DEBUG_DRIVER("Enabled hardware status page\n");
1da177e4
LT		 245
246 return 0;
247}
248
c153f45f
EA		 249static int i915_dma_init(struct drm_device *dev, void *data,
250 struct drm_file *file_priv)
1da177e4 251{
c153f45f 252 drm_i915_init_t *init = data;
1da177e4
LT		 253 int retcode = 0;
254
cd9d4e9f
DV		 255 if (drm_core_check_feature(dev, DRIVER_MODESET))
256 return -ENODEV;
257
c153f45f 258 switch (init->func) {
1da177e4 259 case I915_INIT_DMA:
ba8bbcf6 260 retcode = i915_initialize(dev, init);
1da177e4
LT		 261 break;
262 case I915_CLEANUP_DMA:
263 retcode = i915_dma_cleanup(dev);
264 break;
265 case I915_RESUME_DMA:
0d6aa60b 266 retcode = i915_dma_resume(dev);
1da177e4
LT		 267 break;
268 default:
20caafa6 269 retcode = -EINVAL;
1da177e4
LT		 270 break;
271 }
272
273 return retcode;
274}
275
276/* Implement basically the same security restrictions as hardware does
277 * for MI_BATCH_NON_SECURE. These can be made stricter at any time.
278 *
279 * Most of the calculations below involve calculating the size of a
280 * particular instruction. It's important to get the size right as
281 * that tells us where the next instruction to check is. Any illegal
282 * instruction detected will be given a size of zero, which is a
283 * signal to abort the rest of the buffer.
284 */
e1f99ce6 285static int validate_cmd(int cmd)
1da177e4
LT		 286{
287 switch (((cmd >> 29) & 0x7)) {
288 case 0x0:
289 switch ((cmd >> 23) & 0x3f) {
290 case 0x0:
291 return 1; /* MI_NOOP */
292 case 0x4:
293 return 1; /* MI_FLUSH */
294 default:
295 return 0; /* disallow everything else */
296 }
297 break;
298 case 0x1:
299 return 0; /* reserved */
300 case 0x2:
301 return (cmd & 0xff) + 2; /* 2d commands */
302 case 0x3:
303 if (((cmd >> 24) & 0x1f) <= 0x18)
304 return 1;
305
306 switch ((cmd >> 24) & 0x1f) {
307 case 0x1c:
308 return 1;
309 case 0x1d:
b5e89ed5 310 switch ((cmd >> 16) & 0xff) {
1da177e4
LT		 311 case 0x3:
312 return (cmd & 0x1f) + 2;
313 case 0x4:
314 return (cmd & 0xf) + 2;
315 default:
316 return (cmd & 0xffff) + 2;
317 }
318 case 0x1e:
319 if (cmd & (1 << 23))
320 return (cmd & 0xffff) + 1;
321 else
322 return 1;
323 case 0x1f:
324 if ((cmd & (1 << 23)) == 0) /* inline vertices */
325 return (cmd & 0x1ffff) + 2;
326 else if (cmd & (1 << 17)) /* indirect random */
327 if ((cmd & 0xffff) == 0)
328 return 0; /* unknown length, too hard */
329 else
330 return (((cmd & 0xffff) + 1) / 2) + 1;
331 else
332 return 2; /* indirect sequential */
333 default:
334 return 0;
335 }
336 default:
337 return 0;
338 }
339
340 return 0;
341}
342
201361a5 343static int i915_emit_cmds(struct drm_device * dev, int *buffer, int dwords)
1da177e4
LT		 344{
345 drm_i915_private_t *dev_priv = dev->dev_private;
e1f99ce6 346 int i, ret;
1da177e4 347
1ec14ad3 348 if ((dwords+1) * sizeof(int) >= LP_RING(dev_priv)->size - 8)
20caafa6 349 return -EINVAL;
de227f5f 350
1da177e4 351 for (i = 0; i < dwords;) {
e1f99ce6
CW		 352 int sz = validate_cmd(buffer[i]);
353 if (sz == 0 || i + sz > dwords)
20caafa6 354 return -EINVAL;
e1f99ce6 355 i += sz;
1da177e4
LT		 356 }
357
e1f99ce6
CW		 358 ret = BEGIN_LP_RING((dwords+1)&~1);
359 if (ret)
360 return ret;
361
362 for (i = 0; i < dwords; i++)
363 OUT_RING(buffer[i]);
de227f5f
DA		 364 if (dwords & 1)
365 OUT_RING(0);
366
367 ADVANCE_LP_RING();
368
1da177e4
LT		 369 return 0;
370}
371
673a394b
EA		 372int
373i915_emit_box(struct drm_device *dev,
c4e7a414
CW		 374 struct drm_clip_rect *box,
375 int DR1, int DR4)
1da177e4 376{
e1f99ce6 377 struct drm_i915_private *dev_priv = dev->dev_private;
e1f99ce6 378 int ret;
1da177e4 379
c4e7a414
CW		 380 if (box->y2 <= box->y1 || box->x2 <= box->x1 ||
381 box->y2 <= 0 || box->x2 <= 0) {
1da177e4 382 DRM_ERROR("Bad box %d,%d..%d,%d\n",
c4e7a414 383 box->x1, box->y1, box->x2, box->y2);
20caafa6 384 return -EINVAL;
1da177e4
LT		 385 }
386
a6c45cf0 387 if (INTEL_INFO(dev)->gen >= 4) {
e1f99ce6
CW		 388 ret = BEGIN_LP_RING(4);
389 if (ret)
390 return ret;
391
c29b669c 392 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
c4e7a414
CW		 393 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
394 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
c29b669c 395 OUT_RING(DR4);
c29b669c 396 } else {
e1f99ce6
CW		 397 ret = BEGIN_LP_RING(6);
398 if (ret)
399 return ret;
400
c29b669c
AH		 401 OUT_RING(GFX_OP_DRAWRECT_INFO);
402 OUT_RING(DR1);
c4e7a414
CW		 403 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
404 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
c29b669c
AH		 405 OUT_RING(DR4);
406 OUT_RING(0);
c29b669c 407 }
e1f99ce6 408 ADVANCE_LP_RING();
1da177e4
LT		 409
410 return 0;
411}
412
c29b669c
AH		 413/* XXX: Emitting the counter should really be moved to part of the IRQ
414 * emit. For now, do it in both places:
415 */
416
84b1fd10 417static void i915_emit_breadcrumb(struct drm_device *dev)
de227f5f
DA		 418{
419 drm_i915_private_t *dev_priv = dev->dev_private;
7c1c2871 420 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
de227f5f 421
c99b058f 422 dev_priv->counter++;
af6061af 423 if (dev_priv->counter > 0x7FFFFFFFUL)
c99b058f 424 dev_priv->counter = 0;
7c1c2871
DA		 425 if (master_priv->sarea_priv)
426 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
de227f5f 427
e1f99ce6
CW		 428 if (BEGIN_LP_RING(4) == 0) {
429 OUT_RING(MI_STORE_DWORD_INDEX);
430 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
431 OUT_RING(dev_priv->counter);
432 OUT_RING(0);
433 ADVANCE_LP_RING();
434 }
de227f5f
DA		 435}
436
84b1fd10 437static int i915_dispatch_cmdbuffer(struct drm_device * dev,
201361a5
EA		 438 drm_i915_cmdbuffer_t *cmd,
439 struct drm_clip_rect *cliprects,
440 void *cmdbuf)
1da177e4
LT		 441{
442 int nbox = cmd->num_cliprects;
443 int i = 0, count, ret;
444
445 if (cmd->sz & 0x3) {
446 DRM_ERROR("alignment");
20caafa6 447 return -EINVAL;
1da177e4
LT		 448 }
449
450 i915_kernel_lost_context(dev);
451
452 count = nbox ? nbox : 1;
453
454 for (i = 0; i < count; i++) {
455 if (i < nbox) {
c4e7a414 456 ret = i915_emit_box(dev, &cliprects[i],
1da177e4
LT		 457 cmd->DR1, cmd->DR4);
458 if (ret)
459 return ret;
460 }
461
201361a5 462 ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4);
1da177e4
LT		 463 if (ret)
464 return ret;
465 }
466
de227f5f 467 i915_emit_breadcrumb(dev);
1da177e4
LT		 468 return 0;
469}
470
84b1fd10 471static int i915_dispatch_batchbuffer(struct drm_device * dev,
201361a5
EA		 472 drm_i915_batchbuffer_t * batch,
473 struct drm_clip_rect *cliprects)
1da177e4 474{
e1f99ce6 475 struct drm_i915_private *dev_priv = dev->dev_private;
1da177e4 476 int nbox = batch->num_cliprects;
e1f99ce6 477 int i, count, ret;
1da177e4
LT		 478
479 if ((batch->start | batch->used) & 0x7) {
480 DRM_ERROR("alignment");
20caafa6 481 return -EINVAL;
1da177e4
LT		 482 }
483
484 i915_kernel_lost_context(dev);
485
486 count = nbox ? nbox : 1;
1da177e4
LT		 487 for (i = 0; i < count; i++) {
488 if (i < nbox) {
c4e7a414 489 ret = i915_emit_box(dev, &cliprects[i],
e1f99ce6 490 batch->DR1, batch->DR4);
1da177e4
LT		 491 if (ret)
492 return ret;
493 }
494
0790d5e1 495 if (!IS_I830(dev) && !IS_845G(dev)) {
e1f99ce6
CW		 496 ret = BEGIN_LP_RING(2);
497 if (ret)
498 return ret;
499
a6c45cf0 500 if (INTEL_INFO(dev)->gen >= 4) {
21f16289
DA		 501 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
502 OUT_RING(batch->start);
503 } else {
504 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
505 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
506 }
1da177e4 507 } else {
e1f99ce6
CW		 508 ret = BEGIN_LP_RING(4);
509 if (ret)
510 return ret;
511
1da177e4
LT		 512 OUT_RING(MI_BATCH_BUFFER);
513 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
514 OUT_RING(batch->start + batch->used - 4);
515 OUT_RING(0);
1da177e4 516 }
e1f99ce6 517 ADVANCE_LP_RING();
1da177e4
LT		 518 }
519
1cafd347 520
f00a3ddf 521 if (IS_G4X(dev) || IS_GEN5(dev)) {
e1f99ce6
CW		 522 if (BEGIN_LP_RING(2) == 0) {
523 OUT_RING(MI_FLUSH | MI_NO_WRITE_FLUSH | MI_INVALIDATE_ISP);
524 OUT_RING(MI_NOOP);
525 ADVANCE_LP_RING();
526 }
1cafd347 527 }
1da177e4 528
e1f99ce6 529 i915_emit_breadcrumb(dev);
1da177e4
LT		 530 return 0;
531}
532
af6061af 533static int i915_dispatch_flip(struct drm_device * dev)
1da177e4
LT		 534{
535 drm_i915_private_t *dev_priv = dev->dev_private;
7c1c2871
DA		 536 struct drm_i915_master_private *master_priv =
537 dev->primary->master->driver_priv;
e1f99ce6 538 int ret;
1da177e4 539
7c1c2871 540 if (!master_priv->sarea_priv)
c99b058f
KH		 541 return -EINVAL;
542
8a4c47f3 543 DRM_DEBUG_DRIVER("%s: page=%d pfCurrentPage=%d\n",
be25ed9c 544 __func__,
545 dev_priv->current_page,
546 master_priv->sarea_priv->pf_current_page);
1da177e4 547
af6061af
DA		 548 i915_kernel_lost_context(dev);
549
e1f99ce6
CW		 550 ret = BEGIN_LP_RING(10);
551 if (ret)
552 return ret;
553
585fb111 554 OUT_RING(MI_FLUSH | MI_READ_FLUSH);
af6061af 555 OUT_RING(0);
1da177e4 556
af6061af
DA		 557 OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
558 OUT_RING(0);
559 if (dev_priv->current_page == 0) {
560 OUT_RING(dev_priv->back_offset);
561 dev_priv->current_page = 1;
1da177e4 562 } else {
af6061af
DA		 563 OUT_RING(dev_priv->front_offset);
564 dev_priv->current_page = 0;
1da177e4 565 }
af6061af 566 OUT_RING(0);
1da177e4 567
af6061af
DA		 568 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
569 OUT_RING(0);
e1f99ce6 570
af6061af 571 ADVANCE_LP_RING();
1da177e4 572
7c1c2871 573 master_priv->sarea_priv->last_enqueue = dev_priv->counter++;
1da177e4 574
e1f99ce6
CW		 575 if (BEGIN_LP_RING(4) == 0) {
576 OUT_RING(MI_STORE_DWORD_INDEX);
577 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
578 OUT_RING(dev_priv->counter);
579 OUT_RING(0);
580 ADVANCE_LP_RING();
581 }
1da177e4 582
7c1c2871 583 master_priv->sarea_priv->pf_current_page = dev_priv->current_page;
af6061af 584 return 0;
1da177e4
LT		 585}
586
1ec14ad3 587static int i915_quiescent(struct drm_device *dev)
1da177e4 588{
1ec14ad3 589 struct intel_ring_buffer *ring = LP_RING(dev->dev_private);
1da177e4
LT		 590
591 i915_kernel_lost_context(dev);
96f298aa 592 return intel_wait_ring_idle(ring);
1da177e4
LT		 593}
594
c153f45f
EA		 595static int i915_flush_ioctl(struct drm_device *dev, void *data,
596 struct drm_file *file_priv)
1da177e4 597{
546b0974
EA		 598 int ret;
599
cd9d4e9f
DV		 600 if (drm_core_check_feature(dev, DRIVER_MODESET))
601 return -ENODEV;
602
546b0974 603 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
1da177e4 604
546b0974
EA		 605 mutex_lock(&dev->struct_mutex);
606 ret = i915_quiescent(dev);
607 mutex_unlock(&dev->struct_mutex);
608
609 return ret;
1da177e4
LT		 610}
611
c153f45f
EA		 612static int i915_batchbuffer(struct drm_device *dev, void *data,
613 struct drm_file *file_priv)
1da177e4 614{
1da177e4 615 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
7c1c2871 616 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1da177e4 617 drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
7c1c2871 618 master_priv->sarea_priv;
c153f45f 619 drm_i915_batchbuffer_t *batch = data;
1da177e4 620 int ret;
201361a5 621 struct drm_clip_rect *cliprects = NULL;
1da177e4 622
cd9d4e9f
DV		 623 if (drm_core_check_feature(dev, DRIVER_MODESET))
624 return -ENODEV;
625
8781342d 626 if (!dev_priv->dri1.allow_batchbuffer) {
1da177e4 627 DRM_ERROR("Batchbuffer ioctl disabled\n");
20caafa6 628 return -EINVAL;
1da177e4
LT		 629 }
630
8a4c47f3 631 DRM_DEBUG_DRIVER("i915 batchbuffer, start %x used %d cliprects %d\n",
be25ed9c 632 batch->start, batch->used, batch->num_cliprects);
1da177e4 633
546b0974 634 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
1da177e4 635
201361a5
EA		 636 if (batch->num_cliprects < 0)
637 return -EINVAL;
638
639 if (batch->num_cliprects) {
9a298b2a
EA		 640 cliprects = kcalloc(batch->num_cliprects,
641 sizeof(struct drm_clip_rect),
642 GFP_KERNEL);
201361a5
EA		 643 if (cliprects == NULL)
644 return -ENOMEM;
645
646 ret = copy_from_user(cliprects, batch->cliprects,
647 batch->num_cliprects *
648 sizeof(struct drm_clip_rect));
9927a403
DC		 649 if (ret != 0) {
650 ret = -EFAULT;
201361a5 651 goto fail_free;
9927a403 652 }
201361a5 653 }
1da177e4 654
546b0974 655 mutex_lock(&dev->struct_mutex);
201361a5 656 ret = i915_dispatch_batchbuffer(dev, batch, cliprects);
546b0974 657 mutex_unlock(&dev->struct_mutex);
1da177e4 658
c99b058f 659 if (sarea_priv)
0baf823a 660 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
201361a5
EA		 661
662fail_free:
9a298b2a 663 kfree(cliprects);
201361a5 664
1da177e4
LT		 665 return ret;
666}
667
c153f45f
EA		 668static int i915_cmdbuffer(struct drm_device *dev, void *data,
669 struct drm_file *file_priv)
1da177e4 670{
1da177e4 671 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
7c1c2871 672 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1da177e4 673 drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
7c1c2871 674 master_priv->sarea_priv;
c153f45f 675 drm_i915_cmdbuffer_t *cmdbuf = data;
201361a5
EA		 676 struct drm_clip_rect *cliprects = NULL;
677 void *batch_data;
1da177e4
LT		 678 int ret;
679
8a4c47f3 680 DRM_DEBUG_DRIVER("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
be25ed9c 681 cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
1da177e4 682
cd9d4e9f
DV		 683 if (drm_core_check_feature(dev, DRIVER_MODESET))
684 return -ENODEV;
685
546b0974 686 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
1da177e4 687
201361a5
EA		 688 if (cmdbuf->num_cliprects < 0)
689 return -EINVAL;
690
9a298b2a 691 batch_data = kmalloc(cmdbuf->sz, GFP_KERNEL);
201361a5
EA		 692 if (batch_data == NULL)
693 return -ENOMEM;
694
695 ret = copy_from_user(batch_data, cmdbuf->buf, cmdbuf->sz);
9927a403
DC		 696 if (ret != 0) {
697 ret = -EFAULT;
201361a5 698 goto fail_batch_free;
9927a403 699 }
201361a5
EA		 700
701 if (cmdbuf->num_cliprects) {
9a298b2a
EA		 702 cliprects = kcalloc(cmdbuf->num_cliprects,
703 sizeof(struct drm_clip_rect), GFP_KERNEL);
a40e8d31
OA		 704 if (cliprects == NULL) {
705 ret = -ENOMEM;
201361a5 706 goto fail_batch_free;
a40e8d31 707 }
201361a5
EA		 708
709 ret = copy_from_user(cliprects, cmdbuf->cliprects,
710 cmdbuf->num_cliprects *
711 sizeof(struct drm_clip_rect));
9927a403
DC		 712 if (ret != 0) {
713 ret = -EFAULT;
201361a5 714 goto fail_clip_free;
9927a403 715 }
1da177e4
LT		 716 }
717
546b0974 718 mutex_lock(&dev->struct_mutex);
201361a5 719 ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data);
546b0974 720 mutex_unlock(&dev->struct_mutex);
1da177e4
LT		 721 if (ret) {
722 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
355d7f37 723 goto fail_clip_free;
1da177e4
LT		 724 }
725
c99b058f 726 if (sarea_priv)
0baf823a 727 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
201361a5 728
201361a5 729fail_clip_free:
9a298b2a 730 kfree(cliprects);
355d7f37 731fail_batch_free:
9a298b2a 732 kfree(batch_data);
201361a5
EA		 733
734 return ret;
1da177e4
LT		 735}
736
9488867a
DV		 737static int i915_emit_irq(struct drm_device * dev)
738{
739 drm_i915_private_t *dev_priv = dev->dev_private;
740 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
741
742 i915_kernel_lost_context(dev);
743
744 DRM_DEBUG_DRIVER("\n");
745
746 dev_priv->counter++;
747 if (dev_priv->counter > 0x7FFFFFFFUL)
748 dev_priv->counter = 1;
749 if (master_priv->sarea_priv)
750 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
751
752 if (BEGIN_LP_RING(4) == 0) {
753 OUT_RING(MI_STORE_DWORD_INDEX);
754 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
755 OUT_RING(dev_priv->counter);
756 OUT_RING(MI_USER_INTERRUPT);
757 ADVANCE_LP_RING();
758 }
759
760 return dev_priv->counter;
761}
762
763static int i915_wait_irq(struct drm_device * dev, int irq_nr)
764{
765 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
766 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
767 int ret = 0;
768 struct intel_ring_buffer *ring = LP_RING(dev_priv);
769
770 DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr,
771 READ_BREADCRUMB(dev_priv));
772
773 if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
774 if (master_priv->sarea_priv)
775 master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
776 return 0;
777 }
778
779 if (master_priv->sarea_priv)
780 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
781
782 if (ring->irq_get(ring)) {
783 DRM_WAIT_ON(ret, ring->irq_queue, 3 * DRM_HZ,
784 READ_BREADCRUMB(dev_priv) >= irq_nr);
785 ring->irq_put(ring);
786 } else if (wait_for(READ_BREADCRUMB(dev_priv) >= irq_nr, 3000))
787 ret = -EBUSY;
788
789 if (ret == -EBUSY) {
790 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
791 READ_BREADCRUMB(dev_priv), (int)dev_priv->counter);
792 }
793
794 return ret;
795}
796
797/* Needs the lock as it touches the ring.
798 */
799static int i915_irq_emit(struct drm_device *dev, void *data,
800 struct drm_file *file_priv)
801{
802 drm_i915_private_t *dev_priv = dev->dev_private;
803 drm_i915_irq_emit_t *emit = data;
804 int result;
805
806 if (drm_core_check_feature(dev, DRIVER_MODESET))
807 return -ENODEV;
808
809 if (!dev_priv || !LP_RING(dev_priv)->virtual_start) {
810 DRM_ERROR("called with no initialization\n");
811 return -EINVAL;
812 }
813
814 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
815
816 mutex_lock(&dev->struct_mutex);
817 result = i915_emit_irq(dev);
818 mutex_unlock(&dev->struct_mutex);
819
820 if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
821 DRM_ERROR("copy_to_user\n");
822 return -EFAULT;
823 }
824
825 return 0;
826}
827
828/* Doesn't need the hardware lock.
829 */
830static int i915_irq_wait(struct drm_device *dev, void *data,
831 struct drm_file *file_priv)
832{
833 drm_i915_private_t *dev_priv = dev->dev_private;
834 drm_i915_irq_wait_t *irqwait = data;
835
836 if (drm_core_check_feature(dev, DRIVER_MODESET))
837 return -ENODEV;
838
839 if (!dev_priv) {
840 DRM_ERROR("called with no initialization\n");
841 return -EINVAL;
842 }
843
844 return i915_wait_irq(dev, irqwait->irq_seq);
845}
846
d1c1edbc
DV		 847static int i915_vblank_pipe_get(struct drm_device *dev, void *data,
848 struct drm_file *file_priv)
849{
850 drm_i915_private_t *dev_priv = dev->dev_private;
851 drm_i915_vblank_pipe_t *pipe = data;
852
853 if (drm_core_check_feature(dev, DRIVER_MODESET))
854 return -ENODEV;
855
856 if (!dev_priv) {
857 DRM_ERROR("called with no initialization\n");
858 return -EINVAL;
859 }
860
861 pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
862
863 return 0;
864}
865
866/**
867 * Schedule buffer swap at given vertical blank.
868 */
869static int i915_vblank_swap(struct drm_device *dev, void *data,
870 struct drm_file *file_priv)
871{
872 /* The delayed swap mechanism was fundamentally racy, and has been
873 * removed. The model was that the client requested a delayed flip/swap
874 * from the kernel, then waited for vblank before continuing to perform
875 * rendering. The problem was that the kernel might wake the client
876 * up before it dispatched the vblank swap (since the lock has to be
877 * held while touching the ringbuffer), in which case the client would
878 * clear and start the next frame before the swap occurred, and
879 * flicker would occur in addition to likely missing the vblank.
880 *
881 * In the absence of this ioctl, userland falls back to a correct path
882 * of waiting for a vblank, then dispatching the swap on its own.
883 * Context switching to userland and back is plenty fast enough for
884 * meeting the requirements of vblank swapping.
885 */
886 return -EINVAL;
887}
888
c153f45f
EA		 889static int i915_flip_bufs(struct drm_device *dev, void *data,
890 struct drm_file *file_priv)
1da177e4 891{
546b0974
EA		 892 int ret;
893
cd9d4e9f
DV		 894 if (drm_core_check_feature(dev, DRIVER_MODESET))
895 return -ENODEV;
896
8a4c47f3 897 DRM_DEBUG_DRIVER("%s\n", __func__);
1da177e4 898
546b0974 899 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
1da177e4 900
546b0974
EA		 901 mutex_lock(&dev->struct_mutex);
902 ret = i915_dispatch_flip(dev);
903 mutex_unlock(&dev->struct_mutex);
904
905 return ret;
1da177e4
LT		 906}
907
c153f45f
EA		 908static int i915_getparam(struct drm_device *dev, void *data,
909 struct drm_file *file_priv)
1da177e4 910{
1da177e4 911 drm_i915_private_t *dev_priv = dev->dev_private;
c153f45f 912 drm_i915_getparam_t *param = data;
1da177e4
LT		 913 int value;
914
915 if (!dev_priv) {
3e684eae 916 DRM_ERROR("called with no initialization\n");
20caafa6 917 return -EINVAL;
1da177e4
LT		 918 }
919
c153f45f 920 switch (param->param) {
1da177e4 921 case I915_PARAM_IRQ_ACTIVE:
0a3e67a4 922 value = dev->pdev->irq ? 1 : 0;
1da177e4
LT		 923 break;
924 case I915_PARAM_ALLOW_BATCHBUFFER:
8781342d 925 value = dev_priv->dri1.allow_batchbuffer ? 1 : 0;
1da177e4 926 break;
0d6aa60b
DA		 927 case I915_PARAM_LAST_DISPATCH:
928 value = READ_BREADCRUMB(dev_priv);
929 break;
ed4c9c4a
KH		 930 case I915_PARAM_CHIPSET_ID:
931 value = dev->pci_device;
932 break;
673a394b 933 case I915_PARAM_HAS_GEM:
2e895b17 934 value = 1;
673a394b 935 break;
0f973f27
JB		 936 case I915_PARAM_NUM_FENCES_AVAIL:
937 value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
938 break;
02e792fb
DV		 939 case I915_PARAM_HAS_OVERLAY:
940 value = dev_priv->overlay ? 1 : 0;
941 break;
e9560f7c
JB		 942 case I915_PARAM_HAS_PAGEFLIPPING:
943 value = 1;
944 break;
76446cac
JB		 945 case I915_PARAM_HAS_EXECBUF2:
946 /* depends on GEM */
2e895b17 947 value = 1;
76446cac 948 break;
e3a815fc
ZN		 949 case I915_PARAM_HAS_BSD:
950 value = HAS_BSD(dev);
951 break;
549f7365
CW		 952 case I915_PARAM_HAS_BLT:
953 value = HAS_BLT(dev);
954 break;
a00b10c3
CW		 955 case I915_PARAM_HAS_RELAXED_FENCING:
956 value = 1;
957 break;
bbf0c6b3
DV		 958 case I915_PARAM_HAS_COHERENT_RINGS:
959 value = 1;
960 break;
72bfa19c
CW		 961 case I915_PARAM_HAS_EXEC_CONSTANTS:
962 value = INTEL_INFO(dev)->gen >= 4;
963 break;
271d81b8
CW		 964 case I915_PARAM_HAS_RELAXED_DELTA:
965 value = 1;
966 break;
ae662d31
EA		 967 case I915_PARAM_HAS_GEN7_SOL_RESET:
968 value = 1;
969 break;
3d29b842
ED		 970 case I915_PARAM_HAS_LLC:
971 value = HAS_LLC(dev);
972 break;
777ee96f
DV		 973 case I915_PARAM_HAS_ALIASING_PPGTT:
974 value = dev_priv->mm.aliasing_ppgtt ? 1 : 0;
975 break;
1da177e4 976 default:
8a4c47f3 977 DRM_DEBUG_DRIVER("Unknown parameter %d\n",
76446cac 978 param->param);
20caafa6 979 return -EINVAL;
1da177e4
LT		 980 }
981
c153f45f 982 if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
1da177e4 983 DRM_ERROR("DRM_COPY_TO_USER failed\n");
20caafa6 984 return -EFAULT;
1da177e4
LT		 985 }
986
987 return 0;
988}
989
c153f45f
EA		 990static int i915_setparam(struct drm_device *dev, void *data,
991 struct drm_file *file_priv)
1da177e4 992{
1da177e4 993 drm_i915_private_t *dev_priv = dev->dev_private;
c153f45f 994 drm_i915_setparam_t *param = data;
1da177e4
LT		 995
996 if (!dev_priv) {
3e684eae 997 DRM_ERROR("called with no initialization\n");
20caafa6 998 return -EINVAL;
1da177e4
LT		 999 }
1000
c153f45f 1001 switch (param->param) {
1da177e4 1002 case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
1da177e4
LT		 1003 break;
1004 case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
1da177e4
LT		 1005 break;
1006 case I915_SETPARAM_ALLOW_BATCHBUFFER:
8781342d 1007 dev_priv->dri1.allow_batchbuffer = param->value ? 1 : 0;
1da177e4 1008 break;
0f973f27
JB		 1009 case I915_SETPARAM_NUM_USED_FENCES:
1010 if (param->value > dev_priv->num_fence_regs ||
1011 param->value < 0)
1012 return -EINVAL;
1013 /* Userspace can use first N regs */
1014 dev_priv->fence_reg_start = param->value;
1015 break;
1da177e4 1016 default:
8a4c47f3 1017 DRM_DEBUG_DRIVER("unknown parameter %d\n",
be25ed9c 1018 param->param);
20caafa6 1019 return -EINVAL;
1da177e4
LT		 1020 }
1021
1022 return 0;
1023}
1024
c153f45f
EA		 1025static int i915_set_status_page(struct drm_device *dev, void *data,
1026 struct drm_file *file_priv)
dc7a9319 1027{
dc7a9319 1028 drm_i915_private_t *dev_priv = dev->dev_private;
c153f45f 1029 drm_i915_hws_addr_t *hws = data;
1ec14ad3 1030 struct intel_ring_buffer *ring = LP_RING(dev_priv);
b39d50e5 1031
cd9d4e9f
DV		 1032 if (drm_core_check_feature(dev, DRIVER_MODESET))
1033 return -ENODEV;
1034
b39d50e5
ZW		 1035 if (!I915_NEED_GFX_HWS(dev))
1036 return -EINVAL;
dc7a9319
WZ		 1037
1038 if (!dev_priv) {
3e684eae 1039 DRM_ERROR("called with no initialization\n");
20caafa6 1040 return -EINVAL;
dc7a9319 1041 }
dc7a9319 1042
79e53945
JB		 1043 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1044 WARN(1, "tried to set status page when mode setting active\n");
1045 return 0;
1046 }
1047
8a4c47f3 1048 DRM_DEBUG_DRIVER("set status page addr 0x%08x\n", (u32)hws->addr);
c153f45f 1049
8187a2b7 1050 ring->status_page.gfx_addr = hws->addr & (0x1ffff<<12);
dc7a9319 1051
8b409580 1052 dev_priv->hws_map.offset = dev->agp->base + hws->addr;
dc7a9319
WZ		 1053 dev_priv->hws_map.size = 4*1024;
1054 dev_priv->hws_map.type = 0;
1055 dev_priv->hws_map.flags = 0;
1056 dev_priv->hws_map.mtrr = 0;
1057
dd0910b3 1058 drm_core_ioremap_wc(&dev_priv->hws_map, dev);
dc7a9319 1059 if (dev_priv->hws_map.handle == NULL) {
dc7a9319 1060 i915_dma_cleanup(dev);
e20f9c64 1061 ring->status_page.gfx_addr = 0;
dc7a9319
WZ		 1062 DRM_ERROR("can not ioremap virtual address for"
1063 " G33 hw status page\n");
20caafa6 1064 return -ENOMEM;
dc7a9319 1065 }
311bd68e
CW		 1066 ring->status_page.page_addr =
1067 (void __force __iomem *)dev_priv->hws_map.handle;
1068 memset_io(ring->status_page.page_addr, 0, PAGE_SIZE);
8187a2b7 1069 I915_WRITE(HWS_PGA, ring->status_page.gfx_addr);
dc7a9319 1070
8a4c47f3 1071 DRM_DEBUG_DRIVER("load hws HWS_PGA with gfx mem 0x%x\n",
e20f9c64 1072 ring->status_page.gfx_addr);
8a4c47f3 1073 DRM_DEBUG_DRIVER("load hws at %p\n",
e20f9c64 1074 ring->status_page.page_addr);
dc7a9319
WZ		 1075 return 0;
1076}
1077
ec2a4c3f
DA		 1078static int i915_get_bridge_dev(struct drm_device *dev)
1079{
1080 struct drm_i915_private *dev_priv = dev->dev_private;
1081
0206e353 1082 dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
ec2a4c3f
DA		 1083 if (!dev_priv->bridge_dev) {
1084 DRM_ERROR("bridge device not found\n");
1085 return -1;
1086 }
1087 return 0;
1088}
1089
c4804411
ZW		 1090#define MCHBAR_I915 0x44
1091#define MCHBAR_I965 0x48
1092#define MCHBAR_SIZE (4*4096)
1093
1094#define DEVEN_REG 0x54
1095#define DEVEN_MCHBAR_EN (1 << 28)
1096
1097/* Allocate space for the MCH regs if needed, return nonzero on error */
1098static int
1099intel_alloc_mchbar_resource(struct drm_device *dev)
1100{
1101 drm_i915_private_t *dev_priv = dev->dev_private;
a6c45cf0 1102 int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
c4804411
ZW		 1103 u32 temp_lo, temp_hi = 0;
1104 u64 mchbar_addr;
a25c25c2 1105 int ret;
c4804411 1106
a6c45cf0 1107 if (INTEL_INFO(dev)->gen >= 4)
c4804411
ZW		 1108 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
1109 pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
1110 mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
1111
1112 /* If ACPI doesn't have it, assume we need to allocate it ourselves */
1113#ifdef CONFIG_PNP
1114 if (mchbar_addr &&
a25c25c2
CW		 1115 pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
1116 return 0;
c4804411
ZW		 1117#endif
1118
1119 /* Get some space for it */
a25c25c2
CW		 1120 dev_priv->mch_res.name = "i915 MCHBAR";
1121 dev_priv->mch_res.flags = IORESOURCE_MEM;
1122 ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
1123 &dev_priv->mch_res,
c4804411
ZW		 1124 MCHBAR_SIZE, MCHBAR_SIZE,
1125 PCIBIOS_MIN_MEM,
a25c25c2 1126 0, pcibios_align_resource,
c4804411
ZW		 1127 dev_priv->bridge_dev);
1128 if (ret) {
1129 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
1130 dev_priv->mch_res.start = 0;
a25c25c2 1131 return ret;
c4804411
ZW		 1132 }
1133
a6c45cf0 1134 if (INTEL_INFO(dev)->gen >= 4)
c4804411
ZW		 1135 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
1136 upper_32_bits(dev_priv->mch_res.start));
1137
1138 pci_write_config_dword(dev_priv->bridge_dev, reg,
1139 lower_32_bits(dev_priv->mch_res.start));
a25c25c2 1140 return 0;
c4804411
ZW		 1141}
1142
1143/* Setup MCHBAR if possible, return true if we should disable it again */
1144static void
1145intel_setup_mchbar(struct drm_device *dev)
1146{
1147 drm_i915_private_t *dev_priv = dev->dev_private;
a6c45cf0 1148 int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
c4804411
ZW		 1149 u32 temp;
1150 bool enabled;
1151
1152 dev_priv->mchbar_need_disable = false;
1153
1154 if (IS_I915G(dev) || IS_I915GM(dev)) {
1155 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
1156 enabled = !!(temp & DEVEN_MCHBAR_EN);
1157 } else {
1158 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1159 enabled = temp & 1;
1160 }
1161
1162 /* If it's already enabled, don't have to do anything */
1163 if (enabled)
1164 return;
1165
1166 if (intel_alloc_mchbar_resource(dev))
1167 return;
1168
1169 dev_priv->mchbar_need_disable = true;
1170
1171 /* Space is allocated or reserved, so enable it. */
1172 if (IS_I915G(dev) || IS_I915GM(dev)) {
1173 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG,
1174 temp | DEVEN_MCHBAR_EN);
1175 } else {
1176 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1177 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
1178 }
1179}
1180
1181static void
1182intel_teardown_mchbar(struct drm_device *dev)
1183{
1184 drm_i915_private_t *dev_priv = dev->dev_private;
a6c45cf0 1185 int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
c4804411
ZW		 1186 u32 temp;
1187
1188 if (dev_priv->mchbar_need_disable) {
1189 if (IS_I915G(dev) || IS_I915GM(dev)) {
1190 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
1191 temp &= ~DEVEN_MCHBAR_EN;
1192 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp);
1193 } else {
1194 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1195 temp &= ~1;
1196 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp);
1197 }
1198 }
1199
1200 if (dev_priv->mch_res.start)
1201 release_resource(&dev_priv->mch_res);
1202}
1203
28d52043
DA		 1204/* true = enable decode, false = disable decoder */
1205static unsigned int i915_vga_set_decode(void *cookie, bool state)
1206{
1207 struct drm_device *dev = cookie;
1208
1209 intel_modeset_vga_set_state(dev, state);
1210 if (state)
1211 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
1212 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1213 else
1214 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1215}
1216
6a9ee8af
DA		 1217static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1218{
1219 struct drm_device *dev = pci_get_drvdata(pdev);
1220 pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
1221 if (state == VGA_SWITCHEROO_ON) {
a70491cc 1222 pr_info("switched on\n");
5bcf719b 1223 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
6a9ee8af
DA		 1224 /* i915 resume handler doesn't set to D0 */
1225 pci_set_power_state(dev->pdev, PCI_D0);
1226 i915_resume(dev);
5bcf719b 1227 dev->switch_power_state = DRM_SWITCH_POWER_ON;
6a9ee8af 1228 } else {
a70491cc 1229 pr_err("switched off\n");
5bcf719b 1230 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
6a9ee8af 1231 i915_suspend(dev, pmm);
5bcf719b 1232 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
6a9ee8af
DA		 1233 }
1234}
1235
1236static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
1237{
1238 struct drm_device *dev = pci_get_drvdata(pdev);
1239 bool can_switch;
1240
1241 spin_lock(&dev->count_lock);
1242 can_switch = (dev->open_count == 0);
1243 spin_unlock(&dev->count_lock);
1244 return can_switch;
1245}
1246
2c7111db
CW		 1247static int i915_load_modeset_init(struct drm_device *dev)
1248{
1249 struct drm_i915_private *dev_priv = dev->dev_private;
1250 int ret;
79e53945 1251
6d139a87 1252 ret = intel_parse_bios(dev);
79e53945
JB		 1253 if (ret)
1254 DRM_INFO("failed to find VBIOS tables\n");
1255
934f992c
CW		 1256 /* If we have > 1 VGA cards, then we need to arbitrate access
1257 * to the common VGA resources.
1258 *
1259 * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
1260 * then we do not take part in VGA arbitration and the
1261 * vga_client_register() fails with -ENODEV.
1262 */
28d52043 1263 ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
934f992c 1264 if (ret && ret != -ENODEV)
2c7111db 1265 goto out;
28d52043 1266
723bfd70
JB		 1267 intel_register_dsm_handler();
1268
6a9ee8af
DA		 1269 ret = vga_switcheroo_register_client(dev->pdev,
1270 i915_switcheroo_set_state,
8d608aa6 1271 NULL,
6a9ee8af
DA		 1272 i915_switcheroo_can_switch);
1273 if (ret)
5a79395b 1274 goto cleanup_vga_client;
6a9ee8af 1275
9797fbfb
CW		 1276 /* Initialise stolen first so that we may reserve preallocated
1277 * objects for the BIOS to KMS transition.
1278 */
1279 ret = i915_gem_init_stolen(dev);
1280 if (ret)
1281 goto cleanup_vga_switcheroo;
1282
b01f2c3a
JB		 1283 intel_modeset_init(dev);
1284
1070a42b 1285 ret = i915_gem_init(dev);
79e53945 1286 if (ret)
9797fbfb 1287 goto cleanup_gem_stolen;
79e53945 1288
2c7111db
CW		 1289 intel_modeset_gem_init(dev);
1290
1291 ret = drm_irq_install(dev);
1292 if (ret)
1293 goto cleanup_gem;
1294
79e53945
JB		 1295 /* Always safe in the mode setting case. */
1296 /* FIXME: do pre/post-mode set stuff in core KMS code */
1297 dev->vblank_disable_allowed = 1;
1298
5a79395b
CW		 1299 ret = intel_fbdev_init(dev);
1300 if (ret)
1301 goto cleanup_irq;
1302
eb1f8e4f 1303 drm_kms_helper_poll_init(dev);
87acb0a5
CW		 1304
1305 /* We're off and running w/KMS */
1306 dev_priv->mm.suspended = 0;
1307
79e53945
JB		 1308 return 0;
1309
5a79395b
CW		 1310cleanup_irq:
1311 drm_irq_uninstall(dev);
2c7111db
CW		 1312cleanup_gem:
1313 mutex_lock(&dev->struct_mutex);
1314 i915_gem_cleanup_ringbuffer(dev);
1315 mutex_unlock(&dev->struct_mutex);
1d2a314c 1316 i915_gem_cleanup_aliasing_ppgtt(dev);
9797fbfb
CW		 1317cleanup_gem_stolen:
1318 i915_gem_cleanup_stolen(dev);
5a79395b
CW		 1319cleanup_vga_switcheroo:
1320 vga_switcheroo_unregister_client(dev->pdev);
1321cleanup_vga_client:
1322 vga_client_register(dev->pdev, NULL, NULL, NULL);
79e53945
JB		 1323out:
1324 return ret;
1325}
1326
7c1c2871
DA		 1327int i915_master_create(struct drm_device *dev, struct drm_master *master)
1328{
1329 struct drm_i915_master_private *master_priv;
1330
9a298b2a 1331 master_priv = kzalloc(sizeof(*master_priv), GFP_KERNEL);
7c1c2871
DA		 1332 if (!master_priv)
1333 return -ENOMEM;
1334
1335 master->driver_priv = master_priv;
1336 return 0;
1337}
1338
1339void i915_master_destroy(struct drm_device *dev, struct drm_master *master)
1340{
1341 struct drm_i915_master_private *master_priv = master->driver_priv;
1342
1343 if (!master_priv)
1344 return;
1345
9a298b2a 1346 kfree(master_priv);
7c1c2871
DA		 1347
1348 master->driver_priv = NULL;
1349}
1350
7648fa99 1351static void i915_pineview_get_mem_freq(struct drm_device *dev)
7662c8bd
SL		 1352{
1353 drm_i915_private_t *dev_priv = dev->dev_private;
1354 u32 tmp;
1355
7662c8bd
SL		 1356 tmp = I915_READ(CLKCFG);
1357
1358 switch (tmp & CLKCFG_FSB_MASK) {
1359 case CLKCFG_FSB_533:
1360 dev_priv->fsb_freq = 533; /* 133*4 */
1361 break;
1362 case CLKCFG_FSB_800:
1363 dev_priv->fsb_freq = 800; /* 200*4 */
1364 break;
1365 case CLKCFG_FSB_667:
1366 dev_priv->fsb_freq = 667; /* 167*4 */
1367 break;
1368 case CLKCFG_FSB_400:
1369 dev_priv->fsb_freq = 400; /* 100*4 */
1370 break;
1371 }
1372
1373 switch (tmp & CLKCFG_MEM_MASK) {
1374 case CLKCFG_MEM_533:
1375 dev_priv->mem_freq = 533;
1376 break;
1377 case CLKCFG_MEM_667:
1378 dev_priv->mem_freq = 667;
1379 break;
1380 case CLKCFG_MEM_800:
1381 dev_priv->mem_freq = 800;
1382 break;
1383 }
95534263
LP		 1384
1385 /* detect pineview DDR3 setting */
1386 tmp = I915_READ(CSHRDDR3CTL);
1387 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
7662c8bd
SL		 1388}
1389
7648fa99
JB		 1390static void i915_ironlake_get_mem_freq(struct drm_device *dev)
1391{
1392 drm_i915_private_t *dev_priv = dev->dev_private;
1393 u16 ddrpll, csipll;
1394
1395 ddrpll = I915_READ16(DDRMPLL1);
1396 csipll = I915_READ16(CSIPLL0);
1397
1398 switch (ddrpll & 0xff) {
1399 case 0xc:
1400 dev_priv->mem_freq = 800;
1401 break;
1402 case 0x10:
1403 dev_priv->mem_freq = 1066;
1404 break;
1405 case 0x14:
1406 dev_priv->mem_freq = 1333;
1407 break;
1408 case 0x18:
1409 dev_priv->mem_freq = 1600;
1410 break;
1411 default:
1412 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
1413 ddrpll & 0xff);
1414 dev_priv->mem_freq = 0;
1415 break;
1416 }
1417
1418 dev_priv->r_t = dev_priv->mem_freq;
1419
1420 switch (csipll & 0x3ff) {
1421 case 0x00c:
1422 dev_priv->fsb_freq = 3200;
1423 break;
1424 case 0x00e:
1425 dev_priv->fsb_freq = 3733;
1426 break;
1427 case 0x010:
1428 dev_priv->fsb_freq = 4266;
1429 break;
1430 case 0x012:
1431 dev_priv->fsb_freq = 4800;
1432 break;
1433 case 0x014:
1434 dev_priv->fsb_freq = 5333;
1435 break;
1436 case 0x016:
1437 dev_priv->fsb_freq = 5866;
1438 break;
1439 case 0x018:
1440 dev_priv->fsb_freq = 6400;
1441 break;
1442 default:
1443 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
1444 csipll & 0x3ff);
1445 dev_priv->fsb_freq = 0;
1446 break;
1447 }
1448
1449 if (dev_priv->fsb_freq == 3200) {
1450 dev_priv->c_m = 0;
1451 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
1452 dev_priv->c_m = 1;
1453 } else {
1454 dev_priv->c_m = 2;
1455 }
1456}
1457
faa60c41
CW		 1458static const struct cparams {
1459 u16 i;
1460 u16 t;
1461 u16 m;
1462 u16 c;
1463} cparams[] = {
7648fa99
JB		 1464 { 1, 1333, 301, 28664 },
1465 { 1, 1066, 294, 24460 },
1466 { 1, 800, 294, 25192 },
1467 { 0, 1333, 276, 27605 },
1468 { 0, 1066, 276, 27605 },
1469 { 0, 800, 231, 23784 },
1470};
1471
1472unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
1473{
1474 u64 total_count, diff, ret;
1475 u32 count1, count2, count3, m = 0, c = 0;
1476 unsigned long now = jiffies_to_msecs(jiffies), diff1;
1477 int i;
1478
1479 diff1 = now - dev_priv->last_time1;
1480
4ed0b577
ED		 1481 /* Prevent division-by-zero if we are asking too fast.
1482 * Also, we don't get interesting results if we are polling
1483 * faster than once in 10ms, so just return the saved value
1484 * in such cases.
1485 */
1486 if (diff1 <= 10)
1487 return dev_priv->chipset_power;
1488
7648fa99
JB		 1489 count1 = I915_READ(DMIEC);
1490 count2 = I915_READ(DDREC);
1491 count3 = I915_READ(CSIEC);
1492
1493 total_count = count1 + count2 + count3;
1494
1495 /* FIXME: handle per-counter overflow */
1496 if (total_count < dev_priv->last_count1) {
1497 diff = ~0UL - dev_priv->last_count1;
1498 diff += total_count;
1499 } else {
1500 diff = total_count - dev_priv->last_count1;
1501 }
1502
1503 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
1504 if (cparams[i].i == dev_priv->c_m &&
1505 cparams[i].t == dev_priv->r_t) {
1506 m = cparams[i].m;
1507 c = cparams[i].c;
1508 break;
1509 }
1510 }
1511
d270ae34 1512 diff = div_u64(diff, diff1);
7648fa99 1513 ret = ((m * diff) + c);
d270ae34 1514 ret = div_u64(ret, 10);
7648fa99
JB		 1515
1516 dev_priv->last_count1 = total_count;
1517 dev_priv->last_time1 = now;
1518
4ed0b577
ED		 1519 dev_priv->chipset_power = ret;
1520
7648fa99
JB		 1521 return ret;
1522}
1523
1524unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
1525{
1526 unsigned long m, x, b;
1527 u32 tsfs;
1528
1529 tsfs = I915_READ(TSFS);
1530
1531 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
1532 x = I915_READ8(TR1);
1533
1534 b = tsfs & TSFS_INTR_MASK;
1535
1536 return ((m * x) / 127) - b;
1537}
1538
faa60c41 1539static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
7648fa99 1540{
faa60c41
CW		 1541 static const struct v_table {
1542 u16 vd; /* in .1 mil */
1543 u16 vm; /* in .1 mil */
1544 } v_table[] = {
1545 { 0, 0, },
1546 { 375, 0, },
1547 { 500, 0, },
1548 { 625, 0, },
1549 { 750, 0, },
1550 { 875, 0, },
1551 { 1000, 0, },
1552 { 1125, 0, },
1553 { 4125, 3000, },
1554 { 4125, 3000, },
1555 { 4125, 3000, },
1556 { 4125, 3000, },
1557 { 4125, 3000, },
1558 { 4125, 3000, },
1559 { 4125, 3000, },
1560 { 4125, 3000, },
1561 { 4125, 3000, },
1562 { 4125, 3000, },
1563 { 4125, 3000, },
1564 { 4125, 3000, },
1565 { 4125, 3000, },
1566 { 4125, 3000, },
1567 { 4125, 3000, },
1568 { 4125, 3000, },
1569 { 4125, 3000, },
1570 { 4125, 3000, },
1571 { 4125, 3000, },
1572 { 4125, 3000, },
1573 { 4125, 3000, },
1574 { 4125, 3000, },
1575 { 4125, 3000, },
1576 { 4125, 3000, },
1577 { 4250, 3125, },
1578 { 4375, 3250, },
1579 { 4500, 3375, },
1580 { 4625, 3500, },
1581 { 4750, 3625, },
1582 { 4875, 3750, },
1583 { 5000, 3875, },
1584 { 5125, 4000, },
1585 { 5250, 4125, },
1586 { 5375, 4250, },
1587 { 5500, 4375, },
1588 { 5625, 4500, },
1589 { 5750, 4625, },
1590 { 5875, 4750, },
1591 { 6000, 4875, },
1592 { 6125, 5000, },
1593 { 6250, 5125, },
1594 { 6375, 5250, },
1595 { 6500, 5375, },
1596 { 6625, 5500, },
1597 { 6750, 5625, },
1598 { 6875, 5750, },
1599 { 7000, 5875, },
1600 { 7125, 6000, },
1601 { 7250, 6125, },
1602 { 7375, 6250, },
1603 { 7500, 6375, },
1604 { 7625, 6500, },
1605 { 7750, 6625, },
1606 { 7875, 6750, },
1607 { 8000, 6875, },
1608 { 8125, 7000, },
1609 { 8250, 7125, },
1610 { 8375, 7250, },
1611 { 8500, 7375, },
1612 { 8625, 7500, },
1613 { 8750, 7625, },
1614 { 8875, 7750, },
1615 { 9000, 7875, },
1616 { 9125, 8000, },
1617 { 9250, 8125, },
1618 { 9375, 8250, },
1619 { 9500, 8375, },
1620 { 9625, 8500, },
1621 { 9750, 8625, },
1622 { 9875, 8750, },
1623 { 10000, 8875, },
1624 { 10125, 9000, },
1625 { 10250, 9125, },
1626 { 10375, 9250, },
1627 { 10500, 9375, },
1628 { 10625, 9500, },
1629 { 10750, 9625, },
1630 { 10875, 9750, },
1631 { 11000, 9875, },
1632 { 11125, 10000, },
1633 { 11250, 10125, },
1634 { 11375, 10250, },
1635 { 11500, 10375, },
1636 { 11625, 10500, },
1637 { 11750, 10625, },
1638 { 11875, 10750, },
1639 { 12000, 10875, },
1640 { 12125, 11000, },
1641 { 12250, 11125, },
1642 { 12375, 11250, },
1643 { 12500, 11375, },
1644 { 12625, 11500, },
1645 { 12750, 11625, },
1646 { 12875, 11750, },
1647 { 13000, 11875, },
1648 { 13125, 12000, },
1649 { 13250, 12125, },
1650 { 13375, 12250, },
1651 { 13500, 12375, },
1652 { 13625, 12500, },
1653 { 13750, 12625, },
1654 { 13875, 12750, },
1655 { 14000, 12875, },
1656 { 14125, 13000, },
1657 { 14250, 13125, },
1658 { 14375, 13250, },
1659 { 14500, 13375, },
1660 { 14625, 13500, },
1661 { 14750, 13625, },
1662 { 14875, 13750, },
1663 { 15000, 13875, },
1664 { 15125, 14000, },
1665 { 15250, 14125, },
1666 { 15375, 14250, },
1667 { 15500, 14375, },
1668 { 15625, 14500, },
1669 { 15750, 14625, },
1670 { 15875, 14750, },
1671 { 16000, 14875, },
1672 { 16125, 15000, },
1673 };
1674 if (dev_priv->info->is_mobile)
1675 return v_table[pxvid].vm;
1676 else
1677 return v_table[pxvid].vd;
7648fa99
JB		 1678}
1679
1680void i915_update_gfx_val(struct drm_i915_private *dev_priv)
1681{
1682 struct timespec now, diff1;
1683 u64 diff;
1684 unsigned long diffms;
1685 u32 count;
1686
582be6b4
CW		 1687 if (dev_priv->info->gen != 5)
1688 return;
1689
7648fa99
JB		 1690 getrawmonotonic(&now);
1691 diff1 = timespec_sub(now, dev_priv->last_time2);
1692
1693 /* Don't divide by 0 */
1694 diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
1695 if (!diffms)
1696 return;
1697
1698 count = I915_READ(GFXEC);
1699
1700 if (count < dev_priv->last_count2) {
1701 diff = ~0UL - dev_priv->last_count2;
1702 diff += count;
1703 } else {
1704 diff = count - dev_priv->last_count2;
1705 }
1706
1707 dev_priv->last_count2 = count;
1708 dev_priv->last_time2 = now;
1709
1710 /* More magic constants... */
1711 diff = diff * 1181;
d270ae34 1712 diff = div_u64(diff, diffms * 10);
7648fa99
JB		 1713 dev_priv->gfx_power = diff;
1714}
1715
1716unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
1717{
1718 unsigned long t, corr, state1, corr2, state2;
1719 u32 pxvid, ext_v;
1720
1721 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->cur_delay * 4));
1722 pxvid = (pxvid >> 24) & 0x7f;
1723 ext_v = pvid_to_extvid(dev_priv, pxvid);
1724
1725 state1 = ext_v;
1726
1727 t = i915_mch_val(dev_priv);
1728
1729 /* Revel in the empirically derived constants */
1730
1731 /* Correction factor in 1/100000 units */
1732 if (t > 80)
1733 corr = ((t * 2349) + 135940);
1734 else if (t >= 50)
1735 corr = ((t * 964) + 29317);
1736 else /* < 50 */
1737 corr = ((t * 301) + 1004);
1738
1739 corr = corr * ((150142 * state1) / 10000 - 78642);
1740 corr /= 100000;
1741 corr2 = (corr * dev_priv->corr);
1742
1743 state2 = (corr2 * state1) / 10000;
1744 state2 /= 100; /* convert to mW */
1745
1746 i915_update_gfx_val(dev_priv);
1747
1748 return dev_priv->gfx_power + state2;
1749}
1750
1751/* Global for IPS driver to get at the current i915 device */
1752static struct drm_i915_private *i915_mch_dev;
1753/*
1754 * Lock protecting IPS related data structures
1755 * - i915_mch_dev
1756 * - dev_priv->max_delay
1757 * - dev_priv->min_delay
1758 * - dev_priv->fmax
1759 * - dev_priv->gpu_busy
1760 */
995b6762 1761static DEFINE_SPINLOCK(mchdev_lock);
7648fa99
JB		 1762
1763/**
1764 * i915_read_mch_val - return value for IPS use
1765 *
1766 * Calculate and return a value for the IPS driver to use when deciding whether
1767 * we have thermal and power headroom to increase CPU or GPU power budget.
1768 */
1769unsigned long i915_read_mch_val(void)
1770{
0206e353 1771 struct drm_i915_private *dev_priv;
7648fa99
JB		 1772 unsigned long chipset_val, graphics_val, ret = 0;
1773
0206e353 1774 spin_lock(&mchdev_lock);
7648fa99
JB		 1775 if (!i915_mch_dev)
1776 goto out_unlock;
1777 dev_priv = i915_mch_dev;
1778
1779 chipset_val = i915_chipset_val(dev_priv);
1780 graphics_val = i915_gfx_val(dev_priv);
1781
1782 ret = chipset_val + graphics_val;
1783
1784out_unlock:
0206e353 1785 spin_unlock(&mchdev_lock);
7648fa99 1786
0206e353 1787 return ret;
7648fa99
JB		 1788}
1789EXPORT_SYMBOL_GPL(i915_read_mch_val);
1790
1791/**
1792 * i915_gpu_raise - raise GPU frequency limit
1793 *
1794 * Raise the limit; IPS indicates we have thermal headroom.
1795 */
1796bool i915_gpu_raise(void)
1797{
0206e353 1798 struct drm_i915_private *dev_priv;
7648fa99
JB		 1799 bool ret = true;
1800
0206e353 1801 spin_lock(&mchdev_lock);
7648fa99
JB		 1802 if (!i915_mch_dev) {
1803 ret = false;
1804 goto out_unlock;
1805 }
1806 dev_priv = i915_mch_dev;
1807
1808 if (dev_priv->max_delay > dev_priv->fmax)
1809 dev_priv->max_delay--;
1810
1811out_unlock:
0206e353 1812 spin_unlock(&mchdev_lock);
7648fa99 1813
0206e353 1814 return ret;
7648fa99
JB		 1815}
1816EXPORT_SYMBOL_GPL(i915_gpu_raise);
1817
1818/**
1819 * i915_gpu_lower - lower GPU frequency limit
1820 *
1821 * IPS indicates we're close to a thermal limit, so throttle back the GPU
1822 * frequency maximum.
1823 */
1824bool i915_gpu_lower(void)
1825{
0206e353 1826 struct drm_i915_private *dev_priv;
7648fa99
JB		 1827 bool ret = true;
1828
0206e353 1829 spin_lock(&mchdev_lock);
7648fa99
JB		 1830 if (!i915_mch_dev) {
1831 ret = false;
1832 goto out_unlock;
1833 }
1834 dev_priv = i915_mch_dev;
1835
1836 if (dev_priv->max_delay < dev_priv->min_delay)
1837 dev_priv->max_delay++;
1838
1839out_unlock:
0206e353 1840 spin_unlock(&mchdev_lock);
7648fa99 1841
0206e353 1842 return ret;
7648fa99
JB		 1843}
1844EXPORT_SYMBOL_GPL(i915_gpu_lower);
1845
1846/**
1847 * i915_gpu_busy - indicate GPU business to IPS
1848 *
1849 * Tell the IPS driver whether or not the GPU is busy.
1850 */
1851bool i915_gpu_busy(void)
1852{
0206e353 1853 struct drm_i915_private *dev_priv;
7648fa99
JB		 1854 bool ret = false;
1855
0206e353 1856 spin_lock(&mchdev_lock);
7648fa99
JB		 1857 if (!i915_mch_dev)
1858 goto out_unlock;
1859 dev_priv = i915_mch_dev;
1860
1861 ret = dev_priv->busy;
1862
1863out_unlock:
0206e353 1864 spin_unlock(&mchdev_lock);
7648fa99 1865
0206e353 1866 return ret;
7648fa99
JB		 1867}
1868EXPORT_SYMBOL_GPL(i915_gpu_busy);
1869
1870/**
1871 * i915_gpu_turbo_disable - disable graphics turbo
1872 *
1873 * Disable graphics turbo by resetting the max frequency and setting the
1874 * current frequency to the default.
1875 */
1876bool i915_gpu_turbo_disable(void)
1877{
0206e353 1878 struct drm_i915_private *dev_priv;
7648fa99
JB		 1879 bool ret = true;
1880
0206e353 1881 spin_lock(&mchdev_lock);
7648fa99
JB		 1882 if (!i915_mch_dev) {
1883 ret = false;
1884 goto out_unlock;
1885 }
1886 dev_priv = i915_mch_dev;
1887
1888 dev_priv->max_delay = dev_priv->fstart;
1889
1890 if (!ironlake_set_drps(dev_priv->dev, dev_priv->fstart))
1891 ret = false;
1892
1893out_unlock:
0206e353 1894 spin_unlock(&mchdev_lock);
7648fa99 1895
0206e353 1896 return ret;
7648fa99
JB		 1897}
1898EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
1899
63ee41d7
EA		 1900/**
1901 * Tells the intel_ips driver that the i915 driver is now loaded, if
1902 * IPS got loaded first.
1903 *
1904 * This awkward dance is so that neither module has to depend on the
1905 * other in order for IPS to do the appropriate communication of
1906 * GPU turbo limits to i915.
1907 */
1908static void
1909ips_ping_for_i915_load(void)
1910{
1911 void (*link)(void);
1912
1913 link = symbol_get(ips_link_to_i915_driver);
1914 if (link) {
1915 link();
1916 symbol_put(ips_link_to_i915_driver);
1917 }
1918}
1919
e2b665c4
AJ		 1920static void
1921i915_mtrr_setup(struct drm_i915_private *dev_priv, unsigned long base,
1922 unsigned long size)
1923{
23f54bea
CW		 1924 dev_priv->mm.gtt_mtrr = -1;
1925
9e984bc1
AJ		 1926#if defined(CONFIG_X86_PAT)
1927 if (cpu_has_pat)
1928 return;
1929#endif
1930
e2b665c4
AJ		 1931 /* Set up a WC MTRR for non-PAT systems. This is more common than
1932 * one would think, because the kernel disables PAT on first
1933 * generation Core chips because WC PAT gets overridden by a UC
1934 * MTRR if present. Even if a UC MTRR isn't present.
1935 */
1936 dev_priv->mm.gtt_mtrr = mtrr_add(base, size, MTRR_TYPE_WRCOMB, 1);
1937 if (dev_priv->mm.gtt_mtrr < 0) {
1938 DRM_INFO("MTRR allocation failed. Graphics "
1939 "performance may suffer.\n");
1940 }
1941}
1942
79e53945
JB		 1943/**
1944 * i915_driver_load - setup chip and create an initial config
1945 * @dev: DRM device
1946 * @flags: startup flags
1947 *
1948 * The driver load routine has to do several things:
1949 * - drive output discovery via intel_modeset_init()
1950 * - initialize the memory manager
1951 * - allocate initial config memory
1952 * - setup the DRM framebuffer with the allocated memory
1953 */
84b1fd10 1954int i915_driver_load(struct drm_device *dev, unsigned long flags)
22eae947 1955{
ea059a1e 1956 struct drm_i915_private *dev_priv;
26394d92 1957 struct intel_device_info *info;
cfdf1fa2 1958 int ret = 0, mmio_bar;
9021f284 1959 uint32_t aperture_size;
fe669bf8 1960
26394d92
DV		 1961 info = (struct intel_device_info *) flags;
1962
1963 /* Refuse to load on gen6+ without kms enabled. */
1964 if (info->gen >= 6 && !drm_core_check_feature(dev, DRIVER_MODESET))
1965 return -ENODEV;
1966
fe669bf8 1967
22eae947
DA		 1968 /* i915 has 4 more counters */
1969 dev->counters += 4;
1970 dev->types[6] = _DRM_STAT_IRQ;
1971 dev->types[7] = _DRM_STAT_PRIMARY;
1972 dev->types[8] = _DRM_STAT_SECONDARY;
1973 dev->types[9] = _DRM_STAT_DMA;
1974
9a298b2a 1975 dev_priv = kzalloc(sizeof(drm_i915_private_t), GFP_KERNEL);
ba8bbcf6
JB		 1976 if (dev_priv == NULL)
1977 return -ENOMEM;
1978
ba8bbcf6 1979 dev->dev_private = (void *)dev_priv;
673a394b 1980 dev_priv->dev = dev;
26394d92 1981 dev_priv->info = info;
ba8bbcf6 1982
ec2a4c3f
DA		 1983 if (i915_get_bridge_dev(dev)) {
1984 ret = -EIO;
1985 goto free_priv;
1986 }
1987
466e69b8
DA		 1988 pci_set_master(dev->pdev);
1989
9f82d238
DV		 1990 /* overlay on gen2 is broken and can't address above 1G */
1991 if (IS_GEN2(dev))
1992 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30));
1993
6927faf3
JN		 1994 /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1995 * using 32bit addressing, overwriting memory if HWS is located
1996 * above 4GB.
1997 *
1998 * The documentation also mentions an issue with undefined
1999 * behaviour if any general state is accessed within a page above 4GB,
2000 * which also needs to be handled carefully.
2001 */
2002 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2003 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(32));
2004
b4ce0f85
CW		 2005 mmio_bar = IS_GEN2(dev) ? 1 : 0;
2006 dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, 0);
2007 if (!dev_priv->regs) {
2008 DRM_ERROR("failed to map registers\n");
2009 ret = -EIO;
2010 goto put_bridge;
2011 }
2012
71e9339c
CW		 2013 dev_priv->mm.gtt = intel_gtt_get();
2014 if (!dev_priv->mm.gtt) {
2015 DRM_ERROR("Failed to initialize GTT\n");
2016 ret = -ENODEV;
a7b85d2a 2017 goto out_rmmap;
71e9339c
CW		 2018 }
2019
9021f284 2020 aperture_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
71e9339c 2021
0206e353 2022 dev_priv->mm.gtt_mapping =
9021f284 2023 io_mapping_create_wc(dev->agp->base, aperture_size);
6644107d
VP		 2024 if (dev_priv->mm.gtt_mapping == NULL) {
2025 ret = -EIO;
2026 goto out_rmmap;
2027 }
2028
9021f284 2029 i915_mtrr_setup(dev_priv, dev->agp->base, aperture_size);
19966754 2030
e642abbf
CW		 2031 /* The i915 workqueue is primarily used for batched retirement of
2032 * requests (and thus managing bo) once the task has been completed
2033 * by the GPU. i915_gem_retire_requests() is called directly when we
2034 * need high-priority retirement, such as waiting for an explicit
2035 * bo.
2036 *
2037 * It is also used for periodic low-priority events, such as
df9c2042 2038 * idle-timers and recording error state.
e642abbf
CW		 2039 *
2040 * All tasks on the workqueue are expected to acquire the dev mutex
2041 * so there is no point in running more than one instance of the
2042 * workqueue at any time: max_active = 1 and NON_REENTRANT.
2043 */
2044 dev_priv->wq = alloc_workqueue("i915",
2045 WQ_UNBOUND | WQ_NON_REENTRANT,
2046 1);
9c9fe1f8
EA		 2047 if (dev_priv->wq == NULL) {
2048 DRM_ERROR("Failed to create our workqueue.\n");
2049 ret = -ENOMEM;
a7b85d2a 2050 goto out_mtrrfree;
9c9fe1f8
EA		 2051 }
2052
f71d4af4 2053 intel_irq_init(dev);
9880b7a5 2054
c4804411
ZW		 2055 /* Try to make sure MCHBAR is enabled before poking at it */
2056 intel_setup_mchbar(dev);
f899fc64 2057 intel_setup_gmbus(dev);
44834a67 2058 intel_opregion_setup(dev);
c4804411 2059
6d139a87
BF		 2060 /* Make sure the bios did its job and set up vital registers */
2061 intel_setup_bios(dev);
2062
673a394b
EA		 2063 i915_gem_load(dev);
2064
398c9cb2
KP		 2065 /* Init HWS */
2066 if (!I915_NEED_GFX_HWS(dev)) {
2067 ret = i915_init_phys_hws(dev);
56e2ea34
CW		 2068 if (ret)
2069 goto out_gem_unload;
398c9cb2 2070 }
ed4cb414 2071
7648fa99
JB		 2072 if (IS_PINEVIEW(dev))
2073 i915_pineview_get_mem_freq(dev);
f00a3ddf 2074 else if (IS_GEN5(dev))
7648fa99 2075 i915_ironlake_get_mem_freq(dev);
7662c8bd 2076
ed4cb414
EA		 2077 /* On the 945G/GM, the chipset reports the MSI capability on the
2078 * integrated graphics even though the support isn't actually there
2079 * according to the published specs. It doesn't appear to function
2080 * correctly in testing on 945G.
2081 * This may be a side effect of MSI having been made available for PEG
2082 * and the registers being closely associated.
d1ed629f
KP		 2083 *
2084 * According to chipset errata, on the 965GM, MSI interrupts may
b60678a7
KP		 2085 * be lost or delayed, but we use them anyways to avoid
2086 * stuck interrupts on some machines.
ed4cb414 2087 */
b60678a7 2088 if (!IS_I945G(dev) && !IS_I945GM(dev))
d3e74d02 2089 pci_enable_msi(dev->pdev);
ed4cb414 2090
9f1f46a4 2091 spin_lock_init(&dev_priv->gt_lock);
1ec14ad3 2092 spin_lock_init(&dev_priv->irq_lock);
63eeaf38 2093 spin_lock_init(&dev_priv->error_lock);
4912d041 2094 spin_lock_init(&dev_priv->rps_lock);
ed4cb414 2095
c51ed787 2096 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
27f8227b
JB		 2097 dev_priv->num_pipe = 3;
2098 else if (IS_MOBILE(dev) || !IS_GEN2(dev))
9db4a9c7
JB		 2099 dev_priv->num_pipe = 2;
2100 else
2101 dev_priv->num_pipe = 1;
2102
2103 ret = drm_vblank_init(dev, dev_priv->num_pipe);
56e2ea34
CW		 2104 if (ret)
2105 goto out_gem_unload;
52440211 2106
11ed50ec
BG		 2107 /* Start out suspended */
2108 dev_priv->mm.suspended = 1;
2109
3bad0781
ZW		 2110 intel_detect_pch(dev);
2111
79e53945 2112 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
53984635 2113 ret = i915_load_modeset_init(dev);
79e53945
JB		 2114 if (ret < 0) {
2115 DRM_ERROR("failed to init modeset\n");
56e2ea34 2116 goto out_gem_unload;
79e53945
JB		 2117 }
2118 }
2119
0136db58
BW		 2120 i915_setup_sysfs(dev);
2121
74a365b3 2122 /* Must be done after probing outputs */
44834a67
CW		 2123 intel_opregion_init(dev);
2124 acpi_video_register();
74a365b3 2125
f65d9421
BG		 2126 setup_timer(&dev_priv->hangcheck_timer, i915_hangcheck_elapsed,
2127 (unsigned long) dev);
7648fa99 2128
582be6b4
CW		 2129 if (IS_GEN5(dev)) {
2130 spin_lock(&mchdev_lock);
2131 i915_mch_dev = dev_priv;
2132 dev_priv->mchdev_lock = &mchdev_lock;
2133 spin_unlock(&mchdev_lock);
7648fa99 2134
582be6b4
CW		 2135 ips_ping_for_i915_load();
2136 }
63ee41d7 2137
79e53945
JB		 2138 return 0;
2139
56e2ea34 2140out_gem_unload:
a7b85d2a
KP		 2141 if (dev_priv->mm.inactive_shrinker.shrink)
2142 unregister_shrinker(&dev_priv->mm.inactive_shrinker);
2143
56e2ea34
CW		 2144 if (dev->pdev->msi_enabled)
2145 pci_disable_msi(dev->pdev);
2146
2147 intel_teardown_gmbus(dev);
2148 intel_teardown_mchbar(dev);
9c9fe1f8 2149 destroy_workqueue(dev_priv->wq);
a7b85d2a
KP		 2150out_mtrrfree:
2151 if (dev_priv->mm.gtt_mtrr >= 0) {
2152 mtrr_del(dev_priv->mm.gtt_mtrr, dev->agp->base,
2153 dev->agp->agp_info.aper_size * 1024 * 1024);
2154 dev_priv->mm.gtt_mtrr = -1;
2155 }
6644107d 2156 io_mapping_free(dev_priv->mm.gtt_mapping);
79e53945 2157out_rmmap:
6dda569f 2158 pci_iounmap(dev->pdev, dev_priv->regs);
ec2a4c3f
DA		 2159put_bridge:
2160 pci_dev_put(dev_priv->bridge_dev);
79e53945 2161free_priv:
9a298b2a 2162 kfree(dev_priv);
ba8bbcf6
JB		 2163 return ret;
2164}
2165
2166int i915_driver_unload(struct drm_device *dev)
2167{
2168 struct drm_i915_private *dev_priv = dev->dev_private;
c911fc1c 2169 int ret;
ba8bbcf6 2170
7648fa99
JB		 2171 spin_lock(&mchdev_lock);
2172 i915_mch_dev = NULL;
2173 spin_unlock(&mchdev_lock);
2174
0136db58
BW		 2175 i915_teardown_sysfs(dev);
2176
17250b71
CW		 2177 if (dev_priv->mm.inactive_shrinker.shrink)
2178 unregister_shrinker(&dev_priv->mm.inactive_shrinker);
2179
c911fc1c 2180 mutex_lock(&dev->struct_mutex);
b2da9fe5 2181 ret = i915_gpu_idle(dev);
c911fc1c
DV		 2182 if (ret)
2183 DRM_ERROR("failed to idle hardware: %d\n", ret);
b2da9fe5 2184 i915_gem_retire_requests(dev);
c911fc1c
DV		 2185 mutex_unlock(&dev->struct_mutex);
2186
75ef9da2
DV		 2187 /* Cancel the retire work handler, which should be idle now. */
2188 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
2189
ab657db1
EA		 2190 io_mapping_free(dev_priv->mm.gtt_mapping);
2191 if (dev_priv->mm.gtt_mtrr >= 0) {
2192 mtrr_del(dev_priv->mm.gtt_mtrr, dev->agp->base,
2193 dev->agp->agp_info.aper_size * 1024 * 1024);
2194 dev_priv->mm.gtt_mtrr = -1;
2195 }
2196
44834a67
CW		 2197 acpi_video_unregister();
2198
79e53945 2199 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
7b4f3990 2200 intel_fbdev_fini(dev);
3d8620cc
JB		 2201 intel_modeset_cleanup(dev);
2202
6363ee6f
ZY		 2203 /*
2204 * free the memory space allocated for the child device
2205 * config parsed from VBT
2206 */
2207 if (dev_priv->child_dev && dev_priv->child_dev_num) {
2208 kfree(dev_priv->child_dev);
2209 dev_priv->child_dev = NULL;
2210 dev_priv->child_dev_num = 0;
2211 }
6c0d9350 2212
6a9ee8af 2213 vga_switcheroo_unregister_client(dev->pdev);
28d52043 2214 vga_client_register(dev->pdev, NULL, NULL, NULL);
79e53945
JB		 2215 }
2216
a8b4899e 2217 /* Free error state after interrupts are fully disabled. */
bc0c7f14
DV		 2218 del_timer_sync(&dev_priv->hangcheck_timer);
2219 cancel_work_sync(&dev_priv->error_work);
a8b4899e 2220 i915_destroy_error_state(dev);
bc0c7f14 2221
ed4cb414
EA		 2222 if (dev->pdev->msi_enabled)
2223 pci_disable_msi(dev->pdev);
2224
44834a67 2225 intel_opregion_fini(dev);
8ee1c3db 2226
79e53945 2227 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
67e77c5a
DV		 2228 /* Flush any outstanding unpin_work. */
2229 flush_workqueue(dev_priv->wq);
2230
79e53945 2231 mutex_lock(&dev->struct_mutex);
ecbec53b 2232 i915_gem_free_all_phys_object(dev);
79e53945
JB		 2233 i915_gem_cleanup_ringbuffer(dev);
2234 mutex_unlock(&dev->struct_mutex);
1d2a314c 2235 i915_gem_cleanup_aliasing_ppgtt(dev);
9797fbfb 2236 i915_gem_cleanup_stolen(dev);
fe669bf8 2237 drm_mm_takedown(&dev_priv->mm.stolen);
02e792fb
DV		 2238
2239 intel_cleanup_overlay(dev);
c2873e96
KP		 2240
2241 if (!I915_NEED_GFX_HWS(dev))
2242 i915_free_hws(dev);
79e53945
JB		 2243 }
2244
701394cc 2245 if (dev_priv->regs != NULL)
6dda569f 2246 pci_iounmap(dev->pdev, dev_priv->regs);
701394cc 2247
f899fc64 2248 intel_teardown_gmbus(dev);
c4804411
ZW		 2249 intel_teardown_mchbar(dev);
2250
bc0c7f14
DV		 2251 destroy_workqueue(dev_priv->wq);
2252
ec2a4c3f 2253 pci_dev_put(dev_priv->bridge_dev);
9a298b2a 2254 kfree(dev->dev_private);
ba8bbcf6 2255
22eae947
DA		 2256 return 0;
2257}
2258
f787a5f5 2259int i915_driver_open(struct drm_device *dev, struct drm_file *file)
673a394b 2260{
f787a5f5 2261 struct drm_i915_file_private *file_priv;
673a394b 2262
8a4c47f3 2263 DRM_DEBUG_DRIVER("\n");
f787a5f5
CW		 2264 file_priv = kmalloc(sizeof(*file_priv), GFP_KERNEL);
2265 if (!file_priv)
673a394b
EA		 2266 return -ENOMEM;
2267
f787a5f5 2268 file->driver_priv = file_priv;
673a394b 2269
1c25595f 2270 spin_lock_init(&file_priv->mm.lock);
f787a5f5 2271 INIT_LIST_HEAD(&file_priv->mm.request_list);
673a394b
EA		 2272
2273 return 0;
2274}
2275
79e53945
JB		 2276/**
2277 * i915_driver_lastclose - clean up after all DRM clients have exited
2278 * @dev: DRM device
2279 *
2280 * Take care of cleaning up after all DRM clients have exited. In the
2281 * mode setting case, we want to restore the kernel's initial mode (just
2282 * in case the last client left us in a bad state).
2283 *
9021f284 2284 * Additionally, in the non-mode setting case, we'll tear down the GTT
79e53945
JB		 2285 * and DMA structures, since the kernel won't be using them, and clea
2286 * up any GEM state.
2287 */
84b1fd10 2288void i915_driver_lastclose(struct drm_device * dev)
1da177e4 2289{
ba8bbcf6
JB		 2290 drm_i915_private_t *dev_priv = dev->dev_private;
2291
79e53945 2292 if (!dev_priv || drm_core_check_feature(dev, DRIVER_MODESET)) {
e8e7a2b8 2293 intel_fb_restore_mode(dev);
6a9ee8af 2294 vga_switcheroo_process_delayed_switch();
144a75fa 2295 return;
79e53945 2296 }
144a75fa 2297
673a394b
EA		 2298 i915_gem_lastclose(dev);
2299
b5e89ed5 2300 i915_dma_cleanup(dev);
1da177e4
LT		 2301}
2302
6c340eac 2303void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
1da177e4 2304{
b962442e 2305 i915_gem_release(dev, file_priv);
1da177e4
LT		 2306}
2307
f787a5f5 2308void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
673a394b 2309{
f787a5f5 2310 struct drm_i915_file_private *file_priv = file->driver_priv;
673a394b 2311
f787a5f5 2312 kfree(file_priv);
673a394b
EA		 2313}
2314
c153f45f 2315struct drm_ioctl_desc i915_ioctls[] = {
1b2f1489
DA		 2316 DRM_IOCTL_DEF_DRV(I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2317 DRM_IOCTL_DEF_DRV(I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
2318 DRM_IOCTL_DEF_DRV(I915_FLIP, i915_flip_bufs, DRM_AUTH),
2319 DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
2320 DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
2321 DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
2322 DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH),
2323 DRM_IOCTL_DEF_DRV(I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
b2c606fe
DV		 2324 DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
2325 DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
2326 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1b2f1489 2327 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
b2c606fe 2328 DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
d1c1edbc 2329 DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1b2f1489
DA		 2330 DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, i915_vblank_pipe_get, DRM_AUTH),
2331 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
2332 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2333 DRM_IOCTL_DEF_DRV(I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2334 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH|DRM_UNLOCKED),
2335 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_UNLOCKED),
2336 DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
2337 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
2338 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED),
2339 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_UNLOCKED),
2340 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2341 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2342 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_UNLOCKED),
2343 DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED),
2344 DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED),
2345 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_UNLOCKED),
2346 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED),
2347 DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED),
2348 DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED),
2349 DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_UNLOCKED),
2350 DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_UNLOCKED),
2351 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED),
2352 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED),
2353 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED),
2354 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
2355 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
8ea30864
JB		 2356 DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
2357 DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, intel_sprite_get_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
c94f7029
DA		 2358};
2359
2360int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
cda17380 2361
9021f284
DV		 2362/*
2363 * This is really ugly: Because old userspace abused the linux agp interface to
2364 * manage the gtt, we need to claim that all intel devices are agp. For
2365 * otherwise the drm core refuses to initialize the agp support code.
cda17380 2366 */
84b1fd10 2367int i915_driver_device_is_agp(struct drm_device * dev)
cda17380
DA		 2368{
2369 return 1;
2370}
Linux kernel - Deliverables
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