Commit | Line | Data |
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1da177e4 LT |
1 | /* i915_dma.c -- DMA support for the I915 -*- linux-c -*- |
2 | */ | |
0d6aa60b | 3 | /* |
1da177e4 LT |
4 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
5 | * All Rights Reserved. | |
bc54fd1a DA |
6 | * |
7 | * Permission is hereby granted, free of charge, to any person obtaining a | |
8 | * copy of this software and associated documentation files (the | |
9 | * "Software"), to deal in the Software without restriction, including | |
10 | * without limitation the rights to use, copy, modify, merge, publish, | |
11 | * distribute, sub license, and/or sell copies of the Software, and to | |
12 | * permit persons to whom the Software is furnished to do so, subject to | |
13 | * the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice (including the | |
16 | * next paragraph) shall be included in all copies or substantial portions | |
17 | * of the Software. | |
18 | * | |
19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
20 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
21 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
22 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
23 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
24 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
25 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
26 | * | |
0d6aa60b | 27 | */ |
1da177e4 | 28 | |
a70491cc JP |
29 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
30 | ||
d1d70677 | 31 | #include <linux/async.h> |
760285e7 DH |
32 | #include <drm/drmP.h> |
33 | #include <drm/drm_crtc_helper.h> | |
34 | #include <drm/drm_fb_helper.h> | |
4f03b1fc | 35 | #include <drm/drm_legacy.h> |
79e53945 | 36 | #include "intel_drv.h" |
760285e7 | 37 | #include <drm/i915_drm.h> |
1da177e4 | 38 | #include "i915_drv.h" |
e21fd552 | 39 | #include "i915_vgpu.h" |
1c5d22f7 | 40 | #include "i915_trace.h" |
dcdb1674 | 41 | #include <linux/pci.h> |
a4de0526 DV |
42 | #include <linux/console.h> |
43 | #include <linux/vt.h> | |
28d52043 | 44 | #include <linux/vgaarb.h> |
c4804411 ZW |
45 | #include <linux/acpi.h> |
46 | #include <linux/pnp.h> | |
6a9ee8af | 47 | #include <linux/vga_switcheroo.h> |
5a0e3ad6 | 48 | #include <linux/slab.h> |
44834a67 | 49 | #include <acpi/video.h> |
8a187455 PZ |
50 | #include <linux/pm.h> |
51 | #include <linux/pm_runtime.h> | |
4bdc7293 | 52 | #include <linux/oom.h> |
1da177e4 | 53 | |
1da177e4 | 54 | |
c153f45f EA |
55 | static int i915_getparam(struct drm_device *dev, void *data, |
56 | struct drm_file *file_priv) | |
1da177e4 | 57 | { |
4c8a4be9 | 58 | struct drm_i915_private *dev_priv = dev->dev_private; |
c153f45f | 59 | drm_i915_getparam_t *param = data; |
1da177e4 LT |
60 | int value; |
61 | ||
c153f45f | 62 | switch (param->param) { |
1da177e4 | 63 | case I915_PARAM_IRQ_ACTIVE: |
1da177e4 | 64 | case I915_PARAM_ALLOW_BATCHBUFFER: |
0d6aa60b | 65 | case I915_PARAM_LAST_DISPATCH: |
ac883c84 | 66 | /* Reject all old ums/dri params. */ |
5c6c6003 | 67 | return -ENODEV; |
ed4c9c4a | 68 | case I915_PARAM_CHIPSET_ID: |
ffbab09b | 69 | value = dev->pdev->device; |
ed4c9c4a | 70 | break; |
27cd4461 NR |
71 | case I915_PARAM_REVISION: |
72 | value = dev->pdev->revision; | |
73 | break; | |
673a394b | 74 | case I915_PARAM_HAS_GEM: |
2e895b17 | 75 | value = 1; |
673a394b | 76 | break; |
0f973f27 JB |
77 | case I915_PARAM_NUM_FENCES_AVAIL: |
78 | value = dev_priv->num_fence_regs - dev_priv->fence_reg_start; | |
79 | break; | |
02e792fb DV |
80 | case I915_PARAM_HAS_OVERLAY: |
81 | value = dev_priv->overlay ? 1 : 0; | |
82 | break; | |
e9560f7c JB |
83 | case I915_PARAM_HAS_PAGEFLIPPING: |
84 | value = 1; | |
85 | break; | |
76446cac JB |
86 | case I915_PARAM_HAS_EXECBUF2: |
87 | /* depends on GEM */ | |
2e895b17 | 88 | value = 1; |
76446cac | 89 | break; |
e3a815fc | 90 | case I915_PARAM_HAS_BSD: |
edc912f5 | 91 | value = intel_ring_initialized(&dev_priv->ring[VCS]); |
e3a815fc | 92 | break; |
549f7365 | 93 | case I915_PARAM_HAS_BLT: |
edc912f5 | 94 | value = intel_ring_initialized(&dev_priv->ring[BCS]); |
549f7365 | 95 | break; |
a1f2cc73 XH |
96 | case I915_PARAM_HAS_VEBOX: |
97 | value = intel_ring_initialized(&dev_priv->ring[VECS]); | |
98 | break; | |
08e16dc8 ZG |
99 | case I915_PARAM_HAS_BSD2: |
100 | value = intel_ring_initialized(&dev_priv->ring[VCS2]); | |
101 | break; | |
a00b10c3 CW |
102 | case I915_PARAM_HAS_RELAXED_FENCING: |
103 | value = 1; | |
104 | break; | |
bbf0c6b3 DV |
105 | case I915_PARAM_HAS_COHERENT_RINGS: |
106 | value = 1; | |
107 | break; | |
72bfa19c CW |
108 | case I915_PARAM_HAS_EXEC_CONSTANTS: |
109 | value = INTEL_INFO(dev)->gen >= 4; | |
110 | break; | |
271d81b8 CW |
111 | case I915_PARAM_HAS_RELAXED_DELTA: |
112 | value = 1; | |
113 | break; | |
ae662d31 EA |
114 | case I915_PARAM_HAS_GEN7_SOL_RESET: |
115 | value = 1; | |
116 | break; | |
3d29b842 ED |
117 | case I915_PARAM_HAS_LLC: |
118 | value = HAS_LLC(dev); | |
119 | break; | |
651d794f CW |
120 | case I915_PARAM_HAS_WT: |
121 | value = HAS_WT(dev); | |
122 | break; | |
777ee96f | 123 | case I915_PARAM_HAS_ALIASING_PPGTT: |
896ab1a5 | 124 | value = USES_PPGTT(dev); |
777ee96f | 125 | break; |
172cf15d BW |
126 | case I915_PARAM_HAS_WAIT_TIMEOUT: |
127 | value = 1; | |
128 | break; | |
2fedbff9 CW |
129 | case I915_PARAM_HAS_SEMAPHORES: |
130 | value = i915_semaphore_is_enabled(dev); | |
131 | break; | |
ec6f1bb9 DA |
132 | case I915_PARAM_HAS_PRIME_VMAP_FLUSH: |
133 | value = 1; | |
134 | break; | |
d7d4eedd CW |
135 | case I915_PARAM_HAS_SECURE_BATCHES: |
136 | value = capable(CAP_SYS_ADMIN); | |
137 | break; | |
b45305fc DV |
138 | case I915_PARAM_HAS_PINNED_BATCHES: |
139 | value = 1; | |
140 | break; | |
ed5982e6 DV |
141 | case I915_PARAM_HAS_EXEC_NO_RELOC: |
142 | value = 1; | |
143 | break; | |
eef90ccb CW |
144 | case I915_PARAM_HAS_EXEC_HANDLE_LUT: |
145 | value = 1; | |
146 | break; | |
d728c8ef BV |
147 | case I915_PARAM_CMD_PARSER_VERSION: |
148 | value = i915_cmd_parser_get_version(); | |
149 | break; | |
6a2c4232 CW |
150 | case I915_PARAM_HAS_COHERENT_PHYS_GTT: |
151 | value = 1; | |
1816f923 AG |
152 | break; |
153 | case I915_PARAM_MMAP_VERSION: | |
154 | value = 1; | |
6a2c4232 | 155 | break; |
a1559ffe JM |
156 | case I915_PARAM_SUBSLICE_TOTAL: |
157 | value = INTEL_INFO(dev)->subslice_total; | |
158 | if (!value) | |
159 | return -ENODEV; | |
160 | break; | |
161 | case I915_PARAM_EU_TOTAL: | |
162 | value = INTEL_INFO(dev)->eu_total; | |
163 | if (!value) | |
164 | return -ENODEV; | |
165 | break; | |
1da177e4 | 166 | default: |
e29c32da | 167 | DRM_DEBUG("Unknown parameter %d\n", param->param); |
20caafa6 | 168 | return -EINVAL; |
1da177e4 LT |
169 | } |
170 | ||
1d6ac185 DV |
171 | if (copy_to_user(param->value, &value, sizeof(int))) { |
172 | DRM_ERROR("copy_to_user failed\n"); | |
20caafa6 | 173 | return -EFAULT; |
1da177e4 LT |
174 | } |
175 | ||
176 | return 0; | |
177 | } | |
178 | ||
c153f45f EA |
179 | static int i915_setparam(struct drm_device *dev, void *data, |
180 | struct drm_file *file_priv) | |
1da177e4 | 181 | { |
4c8a4be9 | 182 | struct drm_i915_private *dev_priv = dev->dev_private; |
c153f45f | 183 | drm_i915_setparam_t *param = data; |
1da177e4 | 184 | |
c153f45f | 185 | switch (param->param) { |
1da177e4 | 186 | case I915_SETPARAM_USE_MI_BATCHBUFFER_START: |
1da177e4 | 187 | case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY: |
1da177e4 | 188 | case I915_SETPARAM_ALLOW_BATCHBUFFER: |
ac883c84 | 189 | /* Reject all old ums/dri params. */ |
5c6c6003 CW |
190 | return -ENODEV; |
191 | ||
0f973f27 JB |
192 | case I915_SETPARAM_NUM_USED_FENCES: |
193 | if (param->value > dev_priv->num_fence_regs || | |
194 | param->value < 0) | |
195 | return -EINVAL; | |
196 | /* Userspace can use first N regs */ | |
197 | dev_priv->fence_reg_start = param->value; | |
198 | break; | |
1da177e4 | 199 | default: |
8a4c47f3 | 200 | DRM_DEBUG_DRIVER("unknown parameter %d\n", |
be25ed9c | 201 | param->param); |
20caafa6 | 202 | return -EINVAL; |
1da177e4 LT |
203 | } |
204 | ||
205 | return 0; | |
206 | } | |
207 | ||
ec2a4c3f DA |
208 | static int i915_get_bridge_dev(struct drm_device *dev) |
209 | { | |
210 | struct drm_i915_private *dev_priv = dev->dev_private; | |
211 | ||
0206e353 | 212 | dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0)); |
ec2a4c3f DA |
213 | if (!dev_priv->bridge_dev) { |
214 | DRM_ERROR("bridge device not found\n"); | |
215 | return -1; | |
216 | } | |
217 | return 0; | |
218 | } | |
219 | ||
c4804411 ZW |
220 | #define MCHBAR_I915 0x44 |
221 | #define MCHBAR_I965 0x48 | |
222 | #define MCHBAR_SIZE (4*4096) | |
223 | ||
224 | #define DEVEN_REG 0x54 | |
225 | #define DEVEN_MCHBAR_EN (1 << 28) | |
226 | ||
227 | /* Allocate space for the MCH regs if needed, return nonzero on error */ | |
228 | static int | |
229 | intel_alloc_mchbar_resource(struct drm_device *dev) | |
230 | { | |
4c8a4be9 | 231 | struct drm_i915_private *dev_priv = dev->dev_private; |
a6c45cf0 | 232 | int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915; |
c4804411 ZW |
233 | u32 temp_lo, temp_hi = 0; |
234 | u64 mchbar_addr; | |
a25c25c2 | 235 | int ret; |
c4804411 | 236 | |
a6c45cf0 | 237 | if (INTEL_INFO(dev)->gen >= 4) |
c4804411 ZW |
238 | pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi); |
239 | pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo); | |
240 | mchbar_addr = ((u64)temp_hi << 32) | temp_lo; | |
241 | ||
242 | /* If ACPI doesn't have it, assume we need to allocate it ourselves */ | |
243 | #ifdef CONFIG_PNP | |
244 | if (mchbar_addr && | |
a25c25c2 CW |
245 | pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE)) |
246 | return 0; | |
c4804411 ZW |
247 | #endif |
248 | ||
249 | /* Get some space for it */ | |
a25c25c2 CW |
250 | dev_priv->mch_res.name = "i915 MCHBAR"; |
251 | dev_priv->mch_res.flags = IORESOURCE_MEM; | |
252 | ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus, | |
253 | &dev_priv->mch_res, | |
c4804411 ZW |
254 | MCHBAR_SIZE, MCHBAR_SIZE, |
255 | PCIBIOS_MIN_MEM, | |
a25c25c2 | 256 | 0, pcibios_align_resource, |
c4804411 ZW |
257 | dev_priv->bridge_dev); |
258 | if (ret) { | |
259 | DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret); | |
260 | dev_priv->mch_res.start = 0; | |
a25c25c2 | 261 | return ret; |
c4804411 ZW |
262 | } |
263 | ||
a6c45cf0 | 264 | if (INTEL_INFO(dev)->gen >= 4) |
c4804411 ZW |
265 | pci_write_config_dword(dev_priv->bridge_dev, reg + 4, |
266 | upper_32_bits(dev_priv->mch_res.start)); | |
267 | ||
268 | pci_write_config_dword(dev_priv->bridge_dev, reg, | |
269 | lower_32_bits(dev_priv->mch_res.start)); | |
a25c25c2 | 270 | return 0; |
c4804411 ZW |
271 | } |
272 | ||
273 | /* Setup MCHBAR if possible, return true if we should disable it again */ | |
274 | static void | |
275 | intel_setup_mchbar(struct drm_device *dev) | |
276 | { | |
4c8a4be9 | 277 | struct drm_i915_private *dev_priv = dev->dev_private; |
a6c45cf0 | 278 | int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915; |
c4804411 ZW |
279 | u32 temp; |
280 | bool enabled; | |
281 | ||
11ea8b7d JB |
282 | if (IS_VALLEYVIEW(dev)) |
283 | return; | |
284 | ||
c4804411 ZW |
285 | dev_priv->mchbar_need_disable = false; |
286 | ||
287 | if (IS_I915G(dev) || IS_I915GM(dev)) { | |
288 | pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp); | |
289 | enabled = !!(temp & DEVEN_MCHBAR_EN); | |
290 | } else { | |
291 | pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); | |
292 | enabled = temp & 1; | |
293 | } | |
294 | ||
295 | /* If it's already enabled, don't have to do anything */ | |
296 | if (enabled) | |
297 | return; | |
298 | ||
299 | if (intel_alloc_mchbar_resource(dev)) | |
300 | return; | |
301 | ||
302 | dev_priv->mchbar_need_disable = true; | |
303 | ||
304 | /* Space is allocated or reserved, so enable it. */ | |
305 | if (IS_I915G(dev) || IS_I915GM(dev)) { | |
306 | pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, | |
307 | temp | DEVEN_MCHBAR_EN); | |
308 | } else { | |
309 | pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); | |
310 | pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1); | |
311 | } | |
312 | } | |
313 | ||
314 | static void | |
315 | intel_teardown_mchbar(struct drm_device *dev) | |
316 | { | |
4c8a4be9 | 317 | struct drm_i915_private *dev_priv = dev->dev_private; |
a6c45cf0 | 318 | int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915; |
c4804411 ZW |
319 | u32 temp; |
320 | ||
321 | if (dev_priv->mchbar_need_disable) { | |
322 | if (IS_I915G(dev) || IS_I915GM(dev)) { | |
323 | pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp); | |
324 | temp &= ~DEVEN_MCHBAR_EN; | |
325 | pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp); | |
326 | } else { | |
327 | pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); | |
328 | temp &= ~1; | |
329 | pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp); | |
330 | } | |
331 | } | |
332 | ||
333 | if (dev_priv->mch_res.start) | |
334 | release_resource(&dev_priv->mch_res); | |
335 | } | |
336 | ||
28d52043 DA |
337 | /* true = enable decode, false = disable decoder */ |
338 | static unsigned int i915_vga_set_decode(void *cookie, bool state) | |
339 | { | |
340 | struct drm_device *dev = cookie; | |
341 | ||
342 | intel_modeset_vga_set_state(dev, state); | |
343 | if (state) | |
344 | return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | | |
345 | VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
346 | else | |
347 | return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
348 | } | |
349 | ||
6a9ee8af DA |
350 | static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state) |
351 | { | |
352 | struct drm_device *dev = pci_get_drvdata(pdev); | |
353 | pm_message_t pmm = { .event = PM_EVENT_SUSPEND }; | |
1a5036bf | 354 | |
6a9ee8af | 355 | if (state == VGA_SWITCHEROO_ON) { |
a70491cc | 356 | pr_info("switched on\n"); |
5bcf719b | 357 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; |
6a9ee8af DA |
358 | /* i915 resume handler doesn't set to D0 */ |
359 | pci_set_power_state(dev->pdev, PCI_D0); | |
fc49b3da | 360 | i915_resume_legacy(dev); |
5bcf719b | 361 | dev->switch_power_state = DRM_SWITCH_POWER_ON; |
6a9ee8af | 362 | } else { |
a70491cc | 363 | pr_err("switched off\n"); |
5bcf719b | 364 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; |
fc49b3da | 365 | i915_suspend_legacy(dev, pmm); |
5bcf719b | 366 | dev->switch_power_state = DRM_SWITCH_POWER_OFF; |
6a9ee8af DA |
367 | } |
368 | } | |
369 | ||
370 | static bool i915_switcheroo_can_switch(struct pci_dev *pdev) | |
371 | { | |
372 | struct drm_device *dev = pci_get_drvdata(pdev); | |
6a9ee8af | 373 | |
fc8fd40e DV |
374 | /* |
375 | * FIXME: open_count is protected by drm_global_mutex but that would lead to | |
376 | * locking inversion with the driver load path. And the access here is | |
377 | * completely racy anyway. So don't bother with locking for now. | |
378 | */ | |
379 | return dev->open_count == 0; | |
6a9ee8af DA |
380 | } |
381 | ||
26ec685f TI |
382 | static const struct vga_switcheroo_client_ops i915_switcheroo_ops = { |
383 | .set_gpu_state = i915_switcheroo_set_state, | |
384 | .reprobe = NULL, | |
385 | .can_switch = i915_switcheroo_can_switch, | |
386 | }; | |
387 | ||
2c7111db CW |
388 | static int i915_load_modeset_init(struct drm_device *dev) |
389 | { | |
390 | struct drm_i915_private *dev_priv = dev->dev_private; | |
391 | int ret; | |
79e53945 | 392 | |
6d139a87 | 393 | ret = intel_parse_bios(dev); |
79e53945 JB |
394 | if (ret) |
395 | DRM_INFO("failed to find VBIOS tables\n"); | |
396 | ||
934f992c CW |
397 | /* If we have > 1 VGA cards, then we need to arbitrate access |
398 | * to the common VGA resources. | |
399 | * | |
400 | * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA), | |
401 | * then we do not take part in VGA arbitration and the | |
402 | * vga_client_register() fails with -ENODEV. | |
403 | */ | |
ebff5fa9 DA |
404 | ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode); |
405 | if (ret && ret != -ENODEV) | |
406 | goto out; | |
28d52043 | 407 | |
723bfd70 JB |
408 | intel_register_dsm_handler(); |
409 | ||
0d69704a | 410 | ret = vga_switcheroo_register_client(dev->pdev, &i915_switcheroo_ops, false); |
6a9ee8af | 411 | if (ret) |
5a79395b | 412 | goto cleanup_vga_client; |
6a9ee8af | 413 | |
9797fbfb CW |
414 | /* Initialise stolen first so that we may reserve preallocated |
415 | * objects for the BIOS to KMS transition. | |
416 | */ | |
417 | ret = i915_gem_init_stolen(dev); | |
418 | if (ret) | |
419 | goto cleanup_vga_switcheroo; | |
420 | ||
e13192f6 ID |
421 | intel_power_domains_init_hw(dev_priv); |
422 | ||
2aeb7d3a | 423 | ret = intel_irq_install(dev_priv); |
52d7eced DV |
424 | if (ret) |
425 | goto cleanup_gem_stolen; | |
426 | ||
427 | /* Important: The output setup functions called by modeset_init need | |
428 | * working irqs for e.g. gmbus and dp aux transfers. */ | |
b01f2c3a JB |
429 | intel_modeset_init(dev); |
430 | ||
1070a42b | 431 | ret = i915_gem_init(dev); |
79e53945 | 432 | if (ret) |
713028b3 | 433 | goto cleanup_irq; |
2c7111db | 434 | |
52d7eced | 435 | intel_modeset_gem_init(dev); |
2c7111db | 436 | |
79e53945 JB |
437 | /* Always safe in the mode setting case. */ |
438 | /* FIXME: do pre/post-mode set stuff in core KMS code */ | |
ba0bf120 | 439 | dev->vblank_disable_allowed = true; |
713028b3 | 440 | if (INTEL_INFO(dev)->num_pipes == 0) |
e3c74757 | 441 | return 0; |
79e53945 | 442 | |
5a79395b CW |
443 | ret = intel_fbdev_init(dev); |
444 | if (ret) | |
52d7eced DV |
445 | goto cleanup_gem; |
446 | ||
20afbda2 | 447 | /* Only enable hotplug handling once the fbdev is fully set up. */ |
b963291c | 448 | intel_hpd_init(dev_priv); |
20afbda2 DV |
449 | |
450 | /* | |
451 | * Some ports require correctly set-up hpd registers for detection to | |
452 | * work properly (leading to ghost connected connector status), e.g. VGA | |
453 | * on gm45. Hence we can only set up the initial fbdev config after hpd | |
454 | * irqs are fully enabled. Now we should scan for the initial config | |
455 | * only once hotplug handling is enabled, but due to screwed-up locking | |
456 | * around kms/fbdev init we can't protect the fdbev initial config | |
457 | * scanning against hotplug events. Hence do this first and ignore the | |
458 | * tiny window where we will loose hotplug notifactions. | |
459 | */ | |
d1d70677 | 460 | async_schedule(intel_fbdev_initial_config, dev_priv); |
20afbda2 | 461 | |
eb1f8e4f | 462 | drm_kms_helper_poll_init(dev); |
87acb0a5 | 463 | |
79e53945 JB |
464 | return 0; |
465 | ||
2c7111db CW |
466 | cleanup_gem: |
467 | mutex_lock(&dev->struct_mutex); | |
468 | i915_gem_cleanup_ringbuffer(dev); | |
55d23285 | 469 | i915_gem_context_fini(dev); |
2c7111db | 470 | mutex_unlock(&dev->struct_mutex); |
713028b3 | 471 | cleanup_irq: |
52d7eced | 472 | drm_irq_uninstall(dev); |
9797fbfb CW |
473 | cleanup_gem_stolen: |
474 | i915_gem_cleanup_stolen(dev); | |
5a79395b CW |
475 | cleanup_vga_switcheroo: |
476 | vga_switcheroo_unregister_client(dev->pdev); | |
477 | cleanup_vga_client: | |
478 | vga_client_register(dev->pdev, NULL, NULL, NULL); | |
79e53945 JB |
479 | out: |
480 | return ret; | |
481 | } | |
482 | ||
243eaf38 | 483 | #if IS_ENABLED(CONFIG_FB) |
f96de58f | 484 | static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv) |
e188719a DV |
485 | { |
486 | struct apertures_struct *ap; | |
487 | struct pci_dev *pdev = dev_priv->dev->pdev; | |
488 | bool primary; | |
f96de58f | 489 | int ret; |
e188719a DV |
490 | |
491 | ap = alloc_apertures(1); | |
492 | if (!ap) | |
f96de58f | 493 | return -ENOMEM; |
e188719a | 494 | |
dabb7a91 | 495 | ap->ranges[0].base = dev_priv->gtt.mappable_base; |
f64e2922 | 496 | ap->ranges[0].size = dev_priv->gtt.mappable_end; |
93d18799 | 497 | |
e188719a DV |
498 | primary = |
499 | pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW; | |
500 | ||
f96de58f | 501 | ret = remove_conflicting_framebuffers(ap, "inteldrmfb", primary); |
e188719a DV |
502 | |
503 | kfree(ap); | |
f96de58f CW |
504 | |
505 | return ret; | |
e188719a | 506 | } |
4520f53a | 507 | #else |
f96de58f | 508 | static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv) |
4520f53a | 509 | { |
f96de58f | 510 | return 0; |
4520f53a DV |
511 | } |
512 | #endif | |
e188719a | 513 | |
a4de0526 DV |
514 | #if !defined(CONFIG_VGA_CONSOLE) |
515 | static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv) | |
516 | { | |
517 | return 0; | |
518 | } | |
519 | #elif !defined(CONFIG_DUMMY_CONSOLE) | |
520 | static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv) | |
521 | { | |
522 | return -ENODEV; | |
523 | } | |
524 | #else | |
525 | static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv) | |
526 | { | |
1bb9e632 | 527 | int ret = 0; |
a4de0526 DV |
528 | |
529 | DRM_INFO("Replacing VGA console driver\n"); | |
530 | ||
531 | console_lock(); | |
1bb9e632 DV |
532 | if (con_is_bound(&vga_con)) |
533 | ret = do_take_over_console(&dummy_con, 0, MAX_NR_CONSOLES - 1, 1); | |
a4de0526 DV |
534 | if (ret == 0) { |
535 | ret = do_unregister_con_driver(&vga_con); | |
536 | ||
537 | /* Ignore "already unregistered". */ | |
538 | if (ret == -ENODEV) | |
539 | ret = 0; | |
540 | } | |
541 | console_unlock(); | |
542 | ||
543 | return ret; | |
544 | } | |
545 | #endif | |
546 | ||
c96ea64e DV |
547 | static void i915_dump_device_info(struct drm_i915_private *dev_priv) |
548 | { | |
5c969aa7 | 549 | const struct intel_device_info *info = &dev_priv->info; |
c96ea64e | 550 | |
e2a5800a DL |
551 | #define PRINT_S(name) "%s" |
552 | #define SEP_EMPTY | |
79fc46df DL |
553 | #define PRINT_FLAG(name) info->name ? #name "," : "" |
554 | #define SEP_COMMA , | |
19c656a1 | 555 | DRM_DEBUG_DRIVER("i915 device info: gen=%i, pciid=0x%04x rev=0x%02x flags=" |
e2a5800a | 556 | DEV_INFO_FOR_EACH_FLAG(PRINT_S, SEP_EMPTY), |
c96ea64e DV |
557 | info->gen, |
558 | dev_priv->dev->pdev->device, | |
19c656a1 | 559 | dev_priv->dev->pdev->revision, |
79fc46df | 560 | DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_COMMA)); |
e2a5800a DL |
561 | #undef PRINT_S |
562 | #undef SEP_EMPTY | |
79fc46df DL |
563 | #undef PRINT_FLAG |
564 | #undef SEP_COMMA | |
c96ea64e DV |
565 | } |
566 | ||
22d3fd46 DL |
567 | /* |
568 | * Determine various intel_device_info fields at runtime. | |
569 | * | |
570 | * Use it when either: | |
571 | * - it's judged too laborious to fill n static structures with the limit | |
572 | * when a simple if statement does the job, | |
573 | * - run-time checks (eg read fuse/strap registers) are needed. | |
658ac4c6 DL |
574 | * |
575 | * This function needs to be called: | |
576 | * - after the MMIO has been setup as we are reading registers, | |
577 | * - after the PCH has been detected, | |
578 | * - before the first usage of the fields it can tweak. | |
22d3fd46 DL |
579 | */ |
580 | static void intel_device_info_runtime_init(struct drm_device *dev) | |
581 | { | |
658ac4c6 | 582 | struct drm_i915_private *dev_priv = dev->dev_private; |
22d3fd46 | 583 | struct intel_device_info *info; |
d615a166 | 584 | enum pipe pipe; |
22d3fd46 | 585 | |
658ac4c6 | 586 | info = (struct intel_device_info *)&dev_priv->info; |
22d3fd46 | 587 | |
1fc8ac3e | 588 | if (IS_VALLEYVIEW(dev) || INTEL_INFO(dev)->gen == 9) |
055e393f | 589 | for_each_pipe(dev_priv, pipe) |
d615a166 DL |
590 | info->num_sprites[pipe] = 2; |
591 | else | |
055e393f | 592 | for_each_pipe(dev_priv, pipe) |
d615a166 | 593 | info->num_sprites[pipe] = 1; |
658ac4c6 | 594 | |
a0bae57f DL |
595 | if (i915.disable_display) { |
596 | DRM_INFO("Display disabled (module parameter)\n"); | |
597 | info->num_pipes = 0; | |
598 | } else if (info->num_pipes > 0 && | |
599 | (INTEL_INFO(dev)->gen == 7 || INTEL_INFO(dev)->gen == 8) && | |
600 | !IS_VALLEYVIEW(dev)) { | |
658ac4c6 DL |
601 | u32 fuse_strap = I915_READ(FUSE_STRAP); |
602 | u32 sfuse_strap = I915_READ(SFUSE_STRAP); | |
603 | ||
604 | /* | |
605 | * SFUSE_STRAP is supposed to have a bit signalling the display | |
606 | * is fused off. Unfortunately it seems that, at least in | |
607 | * certain cases, fused off display means that PCH display | |
608 | * reads don't land anywhere. In that case, we read 0s. | |
609 | * | |
610 | * On CPT/PPT, we can detect this case as SFUSE_STRAP_FUSE_LOCK | |
611 | * should be set when taking over after the firmware. | |
612 | */ | |
613 | if (fuse_strap & ILK_INTERNAL_DISPLAY_DISABLE || | |
614 | sfuse_strap & SFUSE_STRAP_DISPLAY_DISABLED || | |
615 | (dev_priv->pch_type == PCH_CPT && | |
616 | !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) { | |
617 | DRM_INFO("Display fused off, disabling\n"); | |
618 | info->num_pipes = 0; | |
619 | } | |
620 | } | |
693d11c3 | 621 | |
3873218f | 622 | /* Initialize slice/subslice/EU info */ |
693d11c3 | 623 | if (IS_CHERRYVIEW(dev)) { |
c93043ae | 624 | u32 fuse, eu_dis; |
693d11c3 D |
625 | |
626 | fuse = I915_READ(CHV_FUSE_GT); | |
c93043ae JM |
627 | |
628 | info->slice_total = 1; | |
629 | ||
630 | if (!(fuse & CHV_FGT_DISABLE_SS0)) { | |
631 | info->subslice_per_slice++; | |
632 | eu_dis = fuse & (CHV_FGT_EU_DIS_SS0_R0_MASK | | |
633 | CHV_FGT_EU_DIS_SS0_R1_MASK); | |
634 | info->eu_total += 8 - hweight32(eu_dis); | |
635 | } | |
636 | ||
637 | if (!(fuse & CHV_FGT_DISABLE_SS1)) { | |
638 | info->subslice_per_slice++; | |
639 | eu_dis = fuse & (CHV_FGT_EU_DIS_SS1_R0_MASK | | |
640 | CHV_FGT_EU_DIS_SS1_R1_MASK); | |
641 | info->eu_total += 8 - hweight32(eu_dis); | |
642 | } | |
643 | ||
644 | info->subslice_total = info->subslice_per_slice; | |
645 | /* | |
646 | * CHV expected to always have a uniform distribution of EU | |
647 | * across subslices. | |
648 | */ | |
649 | info->eu_per_subslice = info->subslice_total ? | |
650 | info->eu_total / info->subslice_total : | |
651 | 0; | |
652 | /* | |
653 | * CHV supports subslice power gating on devices with more than | |
654 | * one subslice, and supports EU power gating on devices with | |
655 | * more than one EU pair per subslice. | |
656 | */ | |
657 | info->has_slice_pg = 0; | |
658 | info->has_subslice_pg = (info->subslice_total > 1); | |
659 | info->has_eu_pg = (info->eu_per_subslice > 2); | |
3873218f JM |
660 | } else if (IS_SKYLAKE(dev)) { |
661 | const int s_max = 3, ss_max = 4, eu_max = 8; | |
662 | int s, ss; | |
663 | u32 fuse2, eu_disable[s_max], s_enable, ss_disable; | |
664 | ||
665 | fuse2 = I915_READ(GEN8_FUSE2); | |
666 | s_enable = (fuse2 & GEN8_F2_S_ENA_MASK) >> | |
667 | GEN8_F2_S_ENA_SHIFT; | |
668 | ss_disable = (fuse2 & GEN9_F2_SS_DIS_MASK) >> | |
669 | GEN9_F2_SS_DIS_SHIFT; | |
670 | ||
671 | eu_disable[0] = I915_READ(GEN8_EU_DISABLE0); | |
672 | eu_disable[1] = I915_READ(GEN8_EU_DISABLE1); | |
673 | eu_disable[2] = I915_READ(GEN8_EU_DISABLE2); | |
674 | ||
675 | info->slice_total = hweight32(s_enable); | |
676 | /* | |
677 | * The subslice disable field is global, i.e. it applies | |
678 | * to each of the enabled slices. | |
679 | */ | |
680 | info->subslice_per_slice = ss_max - hweight32(ss_disable); | |
681 | info->subslice_total = info->slice_total * | |
682 | info->subslice_per_slice; | |
683 | ||
684 | /* | |
685 | * Iterate through enabled slices and subslices to | |
686 | * count the total enabled EU. | |
687 | */ | |
688 | for (s = 0; s < s_max; s++) { | |
689 | if (!(s_enable & (0x1 << s))) | |
690 | /* skip disabled slice */ | |
691 | continue; | |
692 | ||
693 | for (ss = 0; ss < ss_max; ss++) { | |
b7668791 DL |
694 | u32 n_disabled; |
695 | ||
3873218f JM |
696 | if (ss_disable & (0x1 << ss)) |
697 | /* skip disabled subslice */ | |
698 | continue; | |
699 | ||
b7668791 DL |
700 | n_disabled = hweight8(eu_disable[s] >> |
701 | (ss * eu_max)); | |
702 | ||
703 | /* | |
704 | * Record which subslice(s) has(have) 7 EUs. we | |
705 | * can tune the hash used to spread work among | |
706 | * subslices if they are unbalanced. | |
707 | */ | |
708 | if (eu_max - n_disabled == 7) | |
709 | info->subslice_7eu[s] |= 1 << ss; | |
710 | ||
711 | info->eu_total += eu_max - n_disabled; | |
3873218f JM |
712 | } |
713 | } | |
714 | ||
715 | /* | |
716 | * SKL is expected to always have a uniform distribution | |
717 | * of EU across subslices with the exception that any one | |
718 | * EU in any one subslice may be fused off for die | |
719 | * recovery. | |
720 | */ | |
721 | info->eu_per_subslice = info->subslice_total ? | |
722 | DIV_ROUND_UP(info->eu_total, | |
723 | info->subslice_total) : 0; | |
724 | /* | |
725 | * SKL supports slice power gating on devices with more than | |
726 | * one slice, and supports EU power gating on devices with | |
727 | * more than one EU pair per subslice. | |
728 | */ | |
729 | info->has_slice_pg = (info->slice_total > 1) ? 1 : 0; | |
730 | info->has_subslice_pg = 0; | |
731 | info->has_eu_pg = (info->eu_per_subslice > 2) ? 1 : 0; | |
693d11c3 | 732 | } |
3873218f JM |
733 | DRM_DEBUG_DRIVER("slice total: %u\n", info->slice_total); |
734 | DRM_DEBUG_DRIVER("subslice total: %u\n", info->subslice_total); | |
735 | DRM_DEBUG_DRIVER("subslice per slice: %u\n", info->subslice_per_slice); | |
736 | DRM_DEBUG_DRIVER("EU total: %u\n", info->eu_total); | |
737 | DRM_DEBUG_DRIVER("EU per subslice: %u\n", info->eu_per_subslice); | |
738 | DRM_DEBUG_DRIVER("has slice power gating: %s\n", | |
739 | info->has_slice_pg ? "y" : "n"); | |
740 | DRM_DEBUG_DRIVER("has subslice power gating: %s\n", | |
741 | info->has_subslice_pg ? "y" : "n"); | |
742 | DRM_DEBUG_DRIVER("has EU power gating: %s\n", | |
743 | info->has_eu_pg ? "y" : "n"); | |
22d3fd46 DL |
744 | } |
745 | ||
79e53945 JB |
746 | /** |
747 | * i915_driver_load - setup chip and create an initial config | |
748 | * @dev: DRM device | |
749 | * @flags: startup flags | |
750 | * | |
751 | * The driver load routine has to do several things: | |
752 | * - drive output discovery via intel_modeset_init() | |
753 | * - initialize the memory manager | |
754 | * - allocate initial config memory | |
755 | * - setup the DRM framebuffer with the allocated memory | |
756 | */ | |
84b1fd10 | 757 | int i915_driver_load(struct drm_device *dev, unsigned long flags) |
22eae947 | 758 | { |
ea059a1e | 759 | struct drm_i915_private *dev_priv; |
5c969aa7 | 760 | struct intel_device_info *info, *device_info; |
934d6086 | 761 | int ret = 0, mmio_bar, mmio_size; |
9021f284 | 762 | uint32_t aperture_size; |
fe669bf8 | 763 | |
26394d92 DV |
764 | info = (struct intel_device_info *) flags; |
765 | ||
b14c5679 | 766 | dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL); |
ba8bbcf6 JB |
767 | if (dev_priv == NULL) |
768 | return -ENOMEM; | |
769 | ||
755f68f4 | 770 | dev->dev_private = dev_priv; |
673a394b | 771 | dev_priv->dev = dev; |
5c969aa7 | 772 | |
87f1f465 | 773 | /* Setup the write-once "constant" device info */ |
5c969aa7 | 774 | device_info = (struct intel_device_info *)&dev_priv->info; |
87f1f465 CW |
775 | memcpy(device_info, info, sizeof(dev_priv->info)); |
776 | device_info->device_id = dev->pdev->device; | |
ba8bbcf6 | 777 | |
7dcd2677 KK |
778 | spin_lock_init(&dev_priv->irq_lock); |
779 | spin_lock_init(&dev_priv->gpu_error.lock); | |
07f11d49 | 780 | mutex_init(&dev_priv->backlight_lock); |
907b28c5 | 781 | spin_lock_init(&dev_priv->uncore.lock); |
c20e8355 | 782 | spin_lock_init(&dev_priv->mm.object_stat_lock); |
84c33a64 | 783 | spin_lock_init(&dev_priv->mmio_flip_lock); |
7dcd2677 | 784 | mutex_init(&dev_priv->dpio_lock); |
7dcd2677 KK |
785 | mutex_init(&dev_priv->modeset_restore_lock); |
786 | ||
f742a552 | 787 | intel_pm_setup(dev); |
c67a470b | 788 | |
07144428 DL |
789 | intel_display_crc_init(dev); |
790 | ||
c96ea64e DV |
791 | i915_dump_device_info(dev_priv); |
792 | ||
ed1c9e2c PZ |
793 | /* Not all pre-production machines fall into this category, only the |
794 | * very first ones. Almost everything should work, except for maybe | |
795 | * suspend/resume. And we don't implement workarounds that affect only | |
796 | * pre-production machines. */ | |
797 | if (IS_HSW_EARLY_SDV(dev)) | |
798 | DRM_INFO("This is an early pre-production Haswell machine. " | |
799 | "It may not be fully functional.\n"); | |
800 | ||
ec2a4c3f DA |
801 | if (i915_get_bridge_dev(dev)) { |
802 | ret = -EIO; | |
803 | goto free_priv; | |
804 | } | |
805 | ||
1e1bd0fd BW |
806 | mmio_bar = IS_GEN2(dev) ? 1 : 0; |
807 | /* Before gen4, the registers and the GTT are behind different BARs. | |
808 | * However, from gen4 onwards, the registers and the GTT are shared | |
809 | * in the same BAR, so we want to restrict this ioremap from | |
810 | * clobbering the GTT which we want ioremap_wc instead. Fortunately, | |
811 | * the register BAR remains the same size for all the earlier | |
812 | * generations up to Ironlake. | |
813 | */ | |
814 | if (info->gen < 5) | |
815 | mmio_size = 512*1024; | |
816 | else | |
817 | mmio_size = 2*1024*1024; | |
818 | ||
819 | dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, mmio_size); | |
820 | if (!dev_priv->regs) { | |
821 | DRM_ERROR("failed to map registers\n"); | |
822 | ret = -EIO; | |
823 | goto put_bridge; | |
824 | } | |
825 | ||
c3d685a7 BW |
826 | /* This must be called before any calls to HAS_PCH_* */ |
827 | intel_detect_pch(dev); | |
828 | ||
829 | intel_uncore_init(dev); | |
830 | ||
e76e9aeb BW |
831 | ret = i915_gem_gtt_init(dev); |
832 | if (ret) | |
cbb47d17 | 833 | goto out_regs; |
e188719a | 834 | |
17fa6463 DV |
835 | /* WARNING: Apparently we must kick fbdev drivers before vgacon, |
836 | * otherwise the vga fbdev driver falls over. */ | |
837 | ret = i915_kick_out_firmware_fb(dev_priv); | |
838 | if (ret) { | |
839 | DRM_ERROR("failed to remove conflicting framebuffer drivers\n"); | |
840 | goto out_gtt; | |
841 | } | |
a4de0526 | 842 | |
17fa6463 DV |
843 | ret = i915_kick_out_vgacon(dev_priv); |
844 | if (ret) { | |
845 | DRM_ERROR("failed to remove conflicting VGA console\n"); | |
846 | goto out_gtt; | |
a4de0526 | 847 | } |
e188719a | 848 | |
466e69b8 DA |
849 | pci_set_master(dev->pdev); |
850 | ||
9f82d238 DV |
851 | /* overlay on gen2 is broken and can't address above 1G */ |
852 | if (IS_GEN2(dev)) | |
853 | dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30)); | |
854 | ||
6927faf3 JN |
855 | /* 965GM sometimes incorrectly writes to hardware status page (HWS) |
856 | * using 32bit addressing, overwriting memory if HWS is located | |
857 | * above 4GB. | |
858 | * | |
859 | * The documentation also mentions an issue with undefined | |
860 | * behaviour if any general state is accessed within a page above 4GB, | |
861 | * which also needs to be handled carefully. | |
862 | */ | |
863 | if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) | |
864 | dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(32)); | |
865 | ||
93d18799 | 866 | aperture_size = dev_priv->gtt.mappable_end; |
71e9339c | 867 | |
5d4545ae BW |
868 | dev_priv->gtt.mappable = |
869 | io_mapping_create_wc(dev_priv->gtt.mappable_base, | |
dd2757f8 | 870 | aperture_size); |
5d4545ae | 871 | if (dev_priv->gtt.mappable == NULL) { |
6644107d | 872 | ret = -EIO; |
cbb47d17 | 873 | goto out_gtt; |
6644107d VP |
874 | } |
875 | ||
911bdf0a BW |
876 | dev_priv->gtt.mtrr = arch_phys_wc_add(dev_priv->gtt.mappable_base, |
877 | aperture_size); | |
19966754 | 878 | |
e642abbf CW |
879 | /* The i915 workqueue is primarily used for batched retirement of |
880 | * requests (and thus managing bo) once the task has been completed | |
881 | * by the GPU. i915_gem_retire_requests() is called directly when we | |
882 | * need high-priority retirement, such as waiting for an explicit | |
883 | * bo. | |
884 | * | |
885 | * It is also used for periodic low-priority events, such as | |
df9c2042 | 886 | * idle-timers and recording error state. |
e642abbf CW |
887 | * |
888 | * All tasks on the workqueue are expected to acquire the dev mutex | |
889 | * so there is no point in running more than one instance of the | |
53621860 | 890 | * workqueue at any time. Use an ordered one. |
e642abbf | 891 | */ |
53621860 | 892 | dev_priv->wq = alloc_ordered_workqueue("i915", 0); |
9c9fe1f8 EA |
893 | if (dev_priv->wq == NULL) { |
894 | DRM_ERROR("Failed to create our workqueue.\n"); | |
895 | ret = -ENOMEM; | |
a7b85d2a | 896 | goto out_mtrrfree; |
9c9fe1f8 EA |
897 | } |
898 | ||
0e32b39c DA |
899 | dev_priv->dp_wq = alloc_ordered_workqueue("i915-dp", 0); |
900 | if (dev_priv->dp_wq == NULL) { | |
901 | DRM_ERROR("Failed to create our dp workqueue.\n"); | |
902 | ret = -ENOMEM; | |
903 | goto out_freewq; | |
904 | } | |
905 | ||
737b1506 CW |
906 | dev_priv->gpu_error.hangcheck_wq = |
907 | alloc_ordered_workqueue("i915-hangcheck", 0); | |
908 | if (dev_priv->gpu_error.hangcheck_wq == NULL) { | |
909 | DRM_ERROR("Failed to create our hangcheck workqueue.\n"); | |
910 | ret = -ENOMEM; | |
911 | goto out_freedpwq; | |
912 | } | |
913 | ||
b963291c | 914 | intel_irq_init(dev_priv); |
78511f2a | 915 | intel_uncore_sanitize(dev); |
9880b7a5 | 916 | |
c4804411 ZW |
917 | /* Try to make sure MCHBAR is enabled before poking at it */ |
918 | intel_setup_mchbar(dev); | |
f899fc64 | 919 | intel_setup_gmbus(dev); |
44834a67 | 920 | intel_opregion_setup(dev); |
c4804411 | 921 | |
6d139a87 BF |
922 | intel_setup_bios(dev); |
923 | ||
673a394b EA |
924 | i915_gem_load(dev); |
925 | ||
ed4cb414 EA |
926 | /* On the 945G/GM, the chipset reports the MSI capability on the |
927 | * integrated graphics even though the support isn't actually there | |
928 | * according to the published specs. It doesn't appear to function | |
929 | * correctly in testing on 945G. | |
930 | * This may be a side effect of MSI having been made available for PEG | |
931 | * and the registers being closely associated. | |
d1ed629f KP |
932 | * |
933 | * According to chipset errata, on the 965GM, MSI interrupts may | |
b60678a7 KP |
934 | * be lost or delayed, but we use them anyways to avoid |
935 | * stuck interrupts on some machines. | |
ed4cb414 | 936 | */ |
b60678a7 | 937 | if (!IS_I945G(dev) && !IS_I945GM(dev)) |
d3e74d02 | 938 | pci_enable_msi(dev->pdev); |
ed4cb414 | 939 | |
22d3fd46 | 940 | intel_device_info_runtime_init(dev); |
7f1f3851 | 941 | |
e3c74757 BW |
942 | if (INTEL_INFO(dev)->num_pipes) { |
943 | ret = drm_vblank_init(dev, INTEL_INFO(dev)->num_pipes); | |
944 | if (ret) | |
945 | goto out_gem_unload; | |
946 | } | |
52440211 | 947 | |
da7e29bd | 948 | intel_power_domains_init(dev_priv); |
a38911a3 | 949 | |
17fa6463 DV |
950 | ret = i915_load_modeset_init(dev); |
951 | if (ret < 0) { | |
952 | DRM_ERROR("failed to init modeset\n"); | |
953 | goto out_power_well; | |
79e53945 JB |
954 | } |
955 | ||
e21fd552 YZ |
956 | /* |
957 | * Notify a valid surface after modesetting, | |
958 | * when running inside a VM. | |
959 | */ | |
960 | if (intel_vgpu_active(dev)) | |
961 | I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY); | |
962 | ||
0136db58 BW |
963 | i915_setup_sysfs(dev); |
964 | ||
e3c74757 BW |
965 | if (INTEL_INFO(dev)->num_pipes) { |
966 | /* Must be done after probing outputs */ | |
967 | intel_opregion_init(dev); | |
8e5c2b77 | 968 | acpi_video_register(); |
e3c74757 | 969 | } |
74a365b3 | 970 | |
eb48eb00 DV |
971 | if (IS_GEN5(dev)) |
972 | intel_gpu_ips_init(dev_priv); | |
63ee41d7 | 973 | |
f458ebbc | 974 | intel_runtime_pm_enable(dev_priv); |
8a187455 | 975 | |
58fddc28 ID |
976 | i915_audio_component_init(dev_priv); |
977 | ||
79e53945 JB |
978 | return 0; |
979 | ||
cbb47d17 | 980 | out_power_well: |
f458ebbc | 981 | intel_power_domains_fini(dev_priv); |
cbb47d17 | 982 | drm_vblank_cleanup(dev); |
56e2ea34 | 983 | out_gem_unload: |
4bdc7293 ID |
984 | WARN_ON(unregister_oom_notifier(&dev_priv->mm.oom_notifier)); |
985 | unregister_shrinker(&dev_priv->mm.shrinker); | |
a7b85d2a | 986 | |
56e2ea34 CW |
987 | if (dev->pdev->msi_enabled) |
988 | pci_disable_msi(dev->pdev); | |
989 | ||
990 | intel_teardown_gmbus(dev); | |
991 | intel_teardown_mchbar(dev); | |
22accca0 | 992 | pm_qos_remove_request(&dev_priv->pm_qos); |
737b1506 CW |
993 | destroy_workqueue(dev_priv->gpu_error.hangcheck_wq); |
994 | out_freedpwq: | |
0e32b39c DA |
995 | destroy_workqueue(dev_priv->dp_wq); |
996 | out_freewq: | |
9c9fe1f8 | 997 | destroy_workqueue(dev_priv->wq); |
a7b85d2a | 998 | out_mtrrfree: |
911bdf0a | 999 | arch_phys_wc_del(dev_priv->gtt.mtrr); |
5d4545ae | 1000 | io_mapping_free(dev_priv->gtt.mappable); |
cbb47d17 | 1001 | out_gtt: |
90d0a0e8 | 1002 | i915_global_gtt_cleanup(dev); |
cbb47d17 | 1003 | out_regs: |
c3d685a7 | 1004 | intel_uncore_fini(dev); |
6dda569f | 1005 | pci_iounmap(dev->pdev, dev_priv->regs); |
ec2a4c3f DA |
1006 | put_bridge: |
1007 | pci_dev_put(dev_priv->bridge_dev); | |
79e53945 | 1008 | free_priv: |
cbb47d17 CW |
1009 | if (dev_priv->slab) |
1010 | kmem_cache_destroy(dev_priv->slab); | |
9a298b2a | 1011 | kfree(dev_priv); |
ba8bbcf6 JB |
1012 | return ret; |
1013 | } | |
1014 | ||
1015 | int i915_driver_unload(struct drm_device *dev) | |
1016 | { | |
1017 | struct drm_i915_private *dev_priv = dev->dev_private; | |
c911fc1c | 1018 | int ret; |
ba8bbcf6 | 1019 | |
58fddc28 ID |
1020 | i915_audio_component_cleanup(dev_priv); |
1021 | ||
ce58c32b CW |
1022 | ret = i915_gem_suspend(dev); |
1023 | if (ret) { | |
1024 | DRM_ERROR("failed to idle hardware: %d\n", ret); | |
1025 | return ret; | |
1026 | } | |
1027 | ||
41373cd5 | 1028 | intel_power_domains_fini(dev_priv); |
8a187455 | 1029 | |
eb48eb00 | 1030 | intel_gpu_ips_teardown(); |
7648fa99 | 1031 | |
0136db58 BW |
1032 | i915_teardown_sysfs(dev); |
1033 | ||
4bdc7293 ID |
1034 | WARN_ON(unregister_oom_notifier(&dev_priv->mm.oom_notifier)); |
1035 | unregister_shrinker(&dev_priv->mm.shrinker); | |
17250b71 | 1036 | |
5d4545ae | 1037 | io_mapping_free(dev_priv->gtt.mappable); |
911bdf0a | 1038 | arch_phys_wc_del(dev_priv->gtt.mtrr); |
ab657db1 | 1039 | |
44834a67 CW |
1040 | acpi_video_unregister(); |
1041 | ||
17fa6463 | 1042 | intel_fbdev_fini(dev); |
2ebfaf5f PZ |
1043 | |
1044 | drm_vblank_cleanup(dev); | |
1045 | ||
17fa6463 | 1046 | intel_modeset_cleanup(dev); |
6c0d9350 | 1047 | |
17fa6463 DV |
1048 | /* |
1049 | * free the memory space allocated for the child device | |
1050 | * config parsed from VBT | |
1051 | */ | |
1052 | if (dev_priv->vbt.child_dev && dev_priv->vbt.child_dev_num) { | |
1053 | kfree(dev_priv->vbt.child_dev); | |
1054 | dev_priv->vbt.child_dev = NULL; | |
1055 | dev_priv->vbt.child_dev_num = 0; | |
79e53945 JB |
1056 | } |
1057 | ||
17fa6463 DV |
1058 | vga_switcheroo_unregister_client(dev->pdev); |
1059 | vga_client_register(dev->pdev, NULL, NULL, NULL); | |
1060 | ||
a8b4899e | 1061 | /* Free error state after interrupts are fully disabled. */ |
737b1506 | 1062 | cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work); |
a8b4899e | 1063 | i915_destroy_error_state(dev); |
bc0c7f14 | 1064 | |
ed4cb414 EA |
1065 | if (dev->pdev->msi_enabled) |
1066 | pci_disable_msi(dev->pdev); | |
1067 | ||
44834a67 | 1068 | intel_opregion_fini(dev); |
8ee1c3db | 1069 | |
17fa6463 DV |
1070 | /* Flush any outstanding unpin_work. */ |
1071 | flush_workqueue(dev_priv->wq); | |
67e77c5a | 1072 | |
17fa6463 DV |
1073 | mutex_lock(&dev->struct_mutex); |
1074 | i915_gem_cleanup_ringbuffer(dev); | |
1075 | i915_gem_batch_pool_fini(&dev_priv->mm.batch_pool); | |
1076 | i915_gem_context_fini(dev); | |
1077 | mutex_unlock(&dev->struct_mutex); | |
1078 | i915_gem_cleanup_stolen(dev); | |
79e53945 | 1079 | |
f899fc64 | 1080 | intel_teardown_gmbus(dev); |
c4804411 ZW |
1081 | intel_teardown_mchbar(dev); |
1082 | ||
0e32b39c | 1083 | destroy_workqueue(dev_priv->dp_wq); |
bc0c7f14 | 1084 | destroy_workqueue(dev_priv->wq); |
737b1506 | 1085 | destroy_workqueue(dev_priv->gpu_error.hangcheck_wq); |
9ee32fea | 1086 | pm_qos_remove_request(&dev_priv->pm_qos); |
bc0c7f14 | 1087 | |
90d0a0e8 | 1088 | i915_global_gtt_cleanup(dev); |
6640aab6 | 1089 | |
aec347ab CW |
1090 | intel_uncore_fini(dev); |
1091 | if (dev_priv->regs != NULL) | |
1092 | pci_iounmap(dev->pdev, dev_priv->regs); | |
1093 | ||
42dcedd4 CW |
1094 | if (dev_priv->slab) |
1095 | kmem_cache_destroy(dev_priv->slab); | |
bc0c7f14 | 1096 | |
ec2a4c3f | 1097 | pci_dev_put(dev_priv->bridge_dev); |
2206e6a1 | 1098 | kfree(dev_priv); |
ba8bbcf6 | 1099 | |
22eae947 DA |
1100 | return 0; |
1101 | } | |
1102 | ||
f787a5f5 | 1103 | int i915_driver_open(struct drm_device *dev, struct drm_file *file) |
673a394b | 1104 | { |
b29c19b6 | 1105 | int ret; |
673a394b | 1106 | |
b29c19b6 CW |
1107 | ret = i915_gem_open(dev, file); |
1108 | if (ret) | |
1109 | return ret; | |
254f965c | 1110 | |
673a394b EA |
1111 | return 0; |
1112 | } | |
1113 | ||
79e53945 JB |
1114 | /** |
1115 | * i915_driver_lastclose - clean up after all DRM clients have exited | |
1116 | * @dev: DRM device | |
1117 | * | |
1118 | * Take care of cleaning up after all DRM clients have exited. In the | |
1119 | * mode setting case, we want to restore the kernel's initial mode (just | |
1120 | * in case the last client left us in a bad state). | |
1121 | * | |
9021f284 | 1122 | * Additionally, in the non-mode setting case, we'll tear down the GTT |
79e53945 JB |
1123 | * and DMA structures, since the kernel won't be using them, and clea |
1124 | * up any GEM state. | |
1125 | */ | |
1a5036bf | 1126 | void i915_driver_lastclose(struct drm_device *dev) |
1da177e4 | 1127 | { |
377e91b2 DV |
1128 | intel_fbdev_restore_mode(dev); |
1129 | vga_switcheroo_process_delayed_switch(); | |
1da177e4 LT |
1130 | } |
1131 | ||
2885f6ac | 1132 | void i915_driver_preclose(struct drm_device *dev, struct drm_file *file) |
1da177e4 | 1133 | { |
0d1430a3 | 1134 | mutex_lock(&dev->struct_mutex); |
2885f6ac JH |
1135 | i915_gem_context_close(dev, file); |
1136 | i915_gem_release(dev, file); | |
0d1430a3 | 1137 | mutex_unlock(&dev->struct_mutex); |
e2fcdaa9 | 1138 | |
17fa6463 | 1139 | intel_modeset_preclose(dev, file); |
1da177e4 LT |
1140 | } |
1141 | ||
f787a5f5 | 1142 | void i915_driver_postclose(struct drm_device *dev, struct drm_file *file) |
673a394b | 1143 | { |
f787a5f5 | 1144 | struct drm_i915_file_private *file_priv = file->driver_priv; |
673a394b | 1145 | |
a8ebba75 ZY |
1146 | if (file_priv && file_priv->bsd_ring) |
1147 | file_priv->bsd_ring = NULL; | |
f787a5f5 | 1148 | kfree(file_priv); |
673a394b EA |
1149 | } |
1150 | ||
4feb7659 DV |
1151 | static int |
1152 | i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data, | |
1153 | struct drm_file *file) | |
1154 | { | |
1155 | return -ENODEV; | |
1156 | } | |
1157 | ||
baa70943 | 1158 | const struct drm_ioctl_desc i915_ioctls[] = { |
77f31815 DV |
1159 | DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
1160 | DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH), | |
1161 | DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH), | |
1162 | DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH), | |
1163 | DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH), | |
1164 | DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH), | |
10ba5012 | 1165 | DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH|DRM_RENDER_ALLOW), |
1b2f1489 | 1166 | DRM_IOCTL_DEF_DRV(I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
b2c606fe DV |
1167 | DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH), |
1168 | DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH), | |
1169 | DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
77f31815 | 1170 | DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH), |
b2c606fe | 1171 | DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
d1c1edbc | 1172 | DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
77f31815 DV |
1173 | DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, drm_noop, DRM_AUTH), |
1174 | DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH), | |
1175 | DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
f548c0e9 | 1176 | DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED), |
1b2f1489 | 1177 | DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH|DRM_UNLOCKED), |
10ba5012 | 1178 | DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), |
4feb7659 DV |
1179 | DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED), |
1180 | DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED), | |
10ba5012 KH |
1181 | DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), |
1182 | DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
1183 | DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
1184 | DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
71b14ab6 DV |
1185 | DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED), |
1186 | DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED), | |
10ba5012 KH |
1187 | DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), |
1188 | DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
1189 | DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
1190 | DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
1191 | DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
1192 | DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
1193 | DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
1194 | DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
1195 | DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
1196 | DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
1b2f1489 | 1197 | DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED), |
10ba5012 | 1198 | DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), |
1b2f1489 DA |
1199 | DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED), |
1200 | DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED), | |
8ea30864 JB |
1201 | DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED), |
1202 | DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, intel_sprite_get_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED), | |
10ba5012 KH |
1203 | DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), |
1204 | DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
1205 | DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
1206 | DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
b6359918 | 1207 | DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_get_reset_stats_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), |
5cc9ed4b | 1208 | DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), |
c9dc0f35 CW |
1209 | DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), |
1210 | DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
c94f7029 DA |
1211 | }; |
1212 | ||
f95aeb17 | 1213 | int i915_max_ioctl = ARRAY_SIZE(i915_ioctls); |
cda17380 | 1214 | |
9021f284 DV |
1215 | /* |
1216 | * This is really ugly: Because old userspace abused the linux agp interface to | |
1217 | * manage the gtt, we need to claim that all intel devices are agp. For | |
1218 | * otherwise the drm core refuses to initialize the agp support code. | |
cda17380 | 1219 | */ |
1a5036bf | 1220 | int i915_driver_device_is_agp(struct drm_device *dev) |
cda17380 DA |
1221 | { |
1222 | return 1; | |
1223 | } |