Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* i915_dma.c -- DMA support for the I915 -*- linux-c -*- |
2 | */ | |
0d6aa60b | 3 | /* |
1da177e4 LT |
4 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
5 | * All Rights Reserved. | |
bc54fd1a DA |
6 | * |
7 | * Permission is hereby granted, free of charge, to any person obtaining a | |
8 | * copy of this software and associated documentation files (the | |
9 | * "Software"), to deal in the Software without restriction, including | |
10 | * without limitation the rights to use, copy, modify, merge, publish, | |
11 | * distribute, sub license, and/or sell copies of the Software, and to | |
12 | * permit persons to whom the Software is furnished to do so, subject to | |
13 | * the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice (including the | |
16 | * next paragraph) shall be included in all copies or substantial portions | |
17 | * of the Software. | |
18 | * | |
19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
20 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
21 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
22 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
23 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
24 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
25 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
26 | * | |
0d6aa60b | 27 | */ |
1da177e4 | 28 | |
a70491cc JP |
29 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
30 | ||
760285e7 DH |
31 | #include <drm/drmP.h> |
32 | #include <drm/drm_crtc_helper.h> | |
33 | #include <drm/drm_fb_helper.h> | |
4f03b1fc | 34 | #include <drm/drm_legacy.h> |
79e53945 | 35 | #include "intel_drv.h" |
760285e7 | 36 | #include <drm/i915_drm.h> |
1da177e4 | 37 | #include "i915_drv.h" |
e21fd552 | 38 | #include "i915_vgpu.h" |
1c5d22f7 | 39 | #include "i915_trace.h" |
dcdb1674 | 40 | #include <linux/pci.h> |
a4de0526 DV |
41 | #include <linux/console.h> |
42 | #include <linux/vt.h> | |
28d52043 | 43 | #include <linux/vgaarb.h> |
c4804411 ZW |
44 | #include <linux/acpi.h> |
45 | #include <linux/pnp.h> | |
6a9ee8af | 46 | #include <linux/vga_switcheroo.h> |
5a0e3ad6 | 47 | #include <linux/slab.h> |
44834a67 | 48 | #include <acpi/video.h> |
8a187455 PZ |
49 | #include <linux/pm.h> |
50 | #include <linux/pm_runtime.h> | |
4bdc7293 | 51 | #include <linux/oom.h> |
1da177e4 | 52 | |
4fec15d1 ID |
53 | static unsigned int i915_load_fail_count; |
54 | ||
55 | bool __i915_inject_load_failure(const char *func, int line) | |
56 | { | |
57 | if (i915_load_fail_count >= i915.inject_load_failure) | |
58 | return false; | |
59 | ||
60 | if (++i915_load_fail_count == i915.inject_load_failure) { | |
61 | DRM_INFO("Injecting failure at checkpoint %u [%s:%d]\n", | |
62 | i915.inject_load_failure, func, line); | |
63 | return true; | |
64 | } | |
65 | ||
66 | return false; | |
67 | } | |
1da177e4 | 68 | |
d15d7538 ID |
69 | #define FDO_BUG_URL "https://bugs.freedesktop.org/enter_bug.cgi?product=DRI" |
70 | #define FDO_BUG_MSG "Please file a bug at " FDO_BUG_URL " against DRM/Intel " \ | |
71 | "providing the dmesg log by booting with drm.debug=0xf" | |
72 | ||
73 | void | |
74 | __i915_printk(struct drm_i915_private *dev_priv, const char *level, | |
75 | const char *fmt, ...) | |
76 | { | |
77 | static bool shown_bug_once; | |
78 | struct device *dev = dev_priv->dev->dev; | |
79 | bool is_error = level[1] <= KERN_ERR[1]; | |
ad45d839 | 80 | bool is_debug = level[1] == KERN_DEBUG[1]; |
d15d7538 ID |
81 | struct va_format vaf; |
82 | va_list args; | |
83 | ||
ad45d839 ID |
84 | if (is_debug && !(drm_debug & DRM_UT_DRIVER)) |
85 | return; | |
86 | ||
d15d7538 ID |
87 | va_start(args, fmt); |
88 | ||
89 | vaf.fmt = fmt; | |
90 | vaf.va = &args; | |
91 | ||
92 | dev_printk(level, dev, "[" DRM_NAME ":%ps] %pV", | |
93 | __builtin_return_address(0), &vaf); | |
94 | ||
95 | if (is_error && !shown_bug_once) { | |
96 | dev_notice(dev, "%s", FDO_BUG_MSG); | |
97 | shown_bug_once = true; | |
98 | } | |
99 | ||
100 | va_end(args); | |
101 | } | |
102 | ||
103 | static bool i915_error_injected(struct drm_i915_private *dev_priv) | |
104 | { | |
105 | return i915.inject_load_failure && | |
106 | i915_load_fail_count == i915.inject_load_failure; | |
107 | } | |
108 | ||
109 | #define i915_load_error(dev_priv, fmt, ...) \ | |
110 | __i915_printk(dev_priv, \ | |
111 | i915_error_injected(dev_priv) ? KERN_DEBUG : KERN_ERR, \ | |
112 | fmt, ##__VA_ARGS__) | |
113 | ||
c153f45f EA |
114 | static int i915_getparam(struct drm_device *dev, void *data, |
115 | struct drm_file *file_priv) | |
1da177e4 | 116 | { |
4c8a4be9 | 117 | struct drm_i915_private *dev_priv = dev->dev_private; |
c153f45f | 118 | drm_i915_getparam_t *param = data; |
1da177e4 LT |
119 | int value; |
120 | ||
c153f45f | 121 | switch (param->param) { |
1da177e4 | 122 | case I915_PARAM_IRQ_ACTIVE: |
1da177e4 | 123 | case I915_PARAM_ALLOW_BATCHBUFFER: |
0d6aa60b | 124 | case I915_PARAM_LAST_DISPATCH: |
ac883c84 | 125 | /* Reject all old ums/dri params. */ |
5c6c6003 | 126 | return -ENODEV; |
ed4c9c4a | 127 | case I915_PARAM_CHIPSET_ID: |
ffbab09b | 128 | value = dev->pdev->device; |
ed4c9c4a | 129 | break; |
27cd4461 NR |
130 | case I915_PARAM_REVISION: |
131 | value = dev->pdev->revision; | |
132 | break; | |
673a394b | 133 | case I915_PARAM_HAS_GEM: |
2e895b17 | 134 | value = 1; |
673a394b | 135 | break; |
0f973f27 | 136 | case I915_PARAM_NUM_FENCES_AVAIL: |
c668cde5 | 137 | value = dev_priv->num_fence_regs; |
0f973f27 | 138 | break; |
02e792fb DV |
139 | case I915_PARAM_HAS_OVERLAY: |
140 | value = dev_priv->overlay ? 1 : 0; | |
141 | break; | |
e9560f7c JB |
142 | case I915_PARAM_HAS_PAGEFLIPPING: |
143 | value = 1; | |
144 | break; | |
76446cac JB |
145 | case I915_PARAM_HAS_EXECBUF2: |
146 | /* depends on GEM */ | |
2e895b17 | 147 | value = 1; |
76446cac | 148 | break; |
e3a815fc | 149 | case I915_PARAM_HAS_BSD: |
117897f4 | 150 | value = intel_engine_initialized(&dev_priv->engine[VCS]); |
e3a815fc | 151 | break; |
549f7365 | 152 | case I915_PARAM_HAS_BLT: |
117897f4 | 153 | value = intel_engine_initialized(&dev_priv->engine[BCS]); |
549f7365 | 154 | break; |
a1f2cc73 | 155 | case I915_PARAM_HAS_VEBOX: |
117897f4 | 156 | value = intel_engine_initialized(&dev_priv->engine[VECS]); |
a1f2cc73 | 157 | break; |
08e16dc8 | 158 | case I915_PARAM_HAS_BSD2: |
117897f4 | 159 | value = intel_engine_initialized(&dev_priv->engine[VCS2]); |
08e16dc8 | 160 | break; |
a00b10c3 CW |
161 | case I915_PARAM_HAS_RELAXED_FENCING: |
162 | value = 1; | |
163 | break; | |
bbf0c6b3 DV |
164 | case I915_PARAM_HAS_COHERENT_RINGS: |
165 | value = 1; | |
166 | break; | |
72bfa19c CW |
167 | case I915_PARAM_HAS_EXEC_CONSTANTS: |
168 | value = INTEL_INFO(dev)->gen >= 4; | |
169 | break; | |
271d81b8 CW |
170 | case I915_PARAM_HAS_RELAXED_DELTA: |
171 | value = 1; | |
172 | break; | |
ae662d31 EA |
173 | case I915_PARAM_HAS_GEN7_SOL_RESET: |
174 | value = 1; | |
175 | break; | |
3d29b842 ED |
176 | case I915_PARAM_HAS_LLC: |
177 | value = HAS_LLC(dev); | |
178 | break; | |
651d794f CW |
179 | case I915_PARAM_HAS_WT: |
180 | value = HAS_WT(dev); | |
181 | break; | |
777ee96f | 182 | case I915_PARAM_HAS_ALIASING_PPGTT: |
896ab1a5 | 183 | value = USES_PPGTT(dev); |
777ee96f | 184 | break; |
172cf15d BW |
185 | case I915_PARAM_HAS_WAIT_TIMEOUT: |
186 | value = 1; | |
187 | break; | |
2fedbff9 CW |
188 | case I915_PARAM_HAS_SEMAPHORES: |
189 | value = i915_semaphore_is_enabled(dev); | |
190 | break; | |
ec6f1bb9 DA |
191 | case I915_PARAM_HAS_PRIME_VMAP_FLUSH: |
192 | value = 1; | |
193 | break; | |
d7d4eedd CW |
194 | case I915_PARAM_HAS_SECURE_BATCHES: |
195 | value = capable(CAP_SYS_ADMIN); | |
196 | break; | |
b45305fc DV |
197 | case I915_PARAM_HAS_PINNED_BATCHES: |
198 | value = 1; | |
199 | break; | |
ed5982e6 DV |
200 | case I915_PARAM_HAS_EXEC_NO_RELOC: |
201 | value = 1; | |
202 | break; | |
eef90ccb CW |
203 | case I915_PARAM_HAS_EXEC_HANDLE_LUT: |
204 | value = 1; | |
205 | break; | |
d728c8ef BV |
206 | case I915_PARAM_CMD_PARSER_VERSION: |
207 | value = i915_cmd_parser_get_version(); | |
208 | break; | |
6a2c4232 CW |
209 | case I915_PARAM_HAS_COHERENT_PHYS_GTT: |
210 | value = 1; | |
1816f923 AG |
211 | break; |
212 | case I915_PARAM_MMAP_VERSION: | |
213 | value = 1; | |
6a2c4232 | 214 | break; |
a1559ffe JM |
215 | case I915_PARAM_SUBSLICE_TOTAL: |
216 | value = INTEL_INFO(dev)->subslice_total; | |
217 | if (!value) | |
218 | return -ENODEV; | |
219 | break; | |
220 | case I915_PARAM_EU_TOTAL: | |
221 | value = INTEL_INFO(dev)->eu_total; | |
222 | if (!value) | |
223 | return -ENODEV; | |
224 | break; | |
49e4d842 CW |
225 | case I915_PARAM_HAS_GPU_RESET: |
226 | value = i915.enable_hangcheck && | |
49e4d842 CW |
227 | intel_has_gpu_reset(dev); |
228 | break; | |
a9ed33ca AJ |
229 | case I915_PARAM_HAS_RESOURCE_STREAMER: |
230 | value = HAS_RESOURCE_STREAMER(dev); | |
231 | break; | |
506a8e87 CW |
232 | case I915_PARAM_HAS_EXEC_SOFTPIN: |
233 | value = 1; | |
234 | break; | |
1da177e4 | 235 | default: |
e29c32da | 236 | DRM_DEBUG("Unknown parameter %d\n", param->param); |
20caafa6 | 237 | return -EINVAL; |
1da177e4 LT |
238 | } |
239 | ||
1d6ac185 DV |
240 | if (copy_to_user(param->value, &value, sizeof(int))) { |
241 | DRM_ERROR("copy_to_user failed\n"); | |
20caafa6 | 242 | return -EFAULT; |
1da177e4 LT |
243 | } |
244 | ||
245 | return 0; | |
246 | } | |
247 | ||
ec2a4c3f DA |
248 | static int i915_get_bridge_dev(struct drm_device *dev) |
249 | { | |
250 | struct drm_i915_private *dev_priv = dev->dev_private; | |
251 | ||
0206e353 | 252 | dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0)); |
ec2a4c3f DA |
253 | if (!dev_priv->bridge_dev) { |
254 | DRM_ERROR("bridge device not found\n"); | |
255 | return -1; | |
256 | } | |
257 | return 0; | |
258 | } | |
259 | ||
c4804411 ZW |
260 | /* Allocate space for the MCH regs if needed, return nonzero on error */ |
261 | static int | |
262 | intel_alloc_mchbar_resource(struct drm_device *dev) | |
263 | { | |
4c8a4be9 | 264 | struct drm_i915_private *dev_priv = dev->dev_private; |
a6c45cf0 | 265 | int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915; |
c4804411 ZW |
266 | u32 temp_lo, temp_hi = 0; |
267 | u64 mchbar_addr; | |
a25c25c2 | 268 | int ret; |
c4804411 | 269 | |
a6c45cf0 | 270 | if (INTEL_INFO(dev)->gen >= 4) |
c4804411 ZW |
271 | pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi); |
272 | pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo); | |
273 | mchbar_addr = ((u64)temp_hi << 32) | temp_lo; | |
274 | ||
275 | /* If ACPI doesn't have it, assume we need to allocate it ourselves */ | |
276 | #ifdef CONFIG_PNP | |
277 | if (mchbar_addr && | |
a25c25c2 CW |
278 | pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE)) |
279 | return 0; | |
c4804411 ZW |
280 | #endif |
281 | ||
282 | /* Get some space for it */ | |
a25c25c2 CW |
283 | dev_priv->mch_res.name = "i915 MCHBAR"; |
284 | dev_priv->mch_res.flags = IORESOURCE_MEM; | |
285 | ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus, | |
286 | &dev_priv->mch_res, | |
c4804411 ZW |
287 | MCHBAR_SIZE, MCHBAR_SIZE, |
288 | PCIBIOS_MIN_MEM, | |
a25c25c2 | 289 | 0, pcibios_align_resource, |
c4804411 ZW |
290 | dev_priv->bridge_dev); |
291 | if (ret) { | |
292 | DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret); | |
293 | dev_priv->mch_res.start = 0; | |
a25c25c2 | 294 | return ret; |
c4804411 ZW |
295 | } |
296 | ||
a6c45cf0 | 297 | if (INTEL_INFO(dev)->gen >= 4) |
c4804411 ZW |
298 | pci_write_config_dword(dev_priv->bridge_dev, reg + 4, |
299 | upper_32_bits(dev_priv->mch_res.start)); | |
300 | ||
301 | pci_write_config_dword(dev_priv->bridge_dev, reg, | |
302 | lower_32_bits(dev_priv->mch_res.start)); | |
a25c25c2 | 303 | return 0; |
c4804411 ZW |
304 | } |
305 | ||
306 | /* Setup MCHBAR if possible, return true if we should disable it again */ | |
307 | static void | |
308 | intel_setup_mchbar(struct drm_device *dev) | |
309 | { | |
4c8a4be9 | 310 | struct drm_i915_private *dev_priv = dev->dev_private; |
a6c45cf0 | 311 | int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915; |
c4804411 ZW |
312 | u32 temp; |
313 | bool enabled; | |
314 | ||
666a4537 | 315 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
11ea8b7d JB |
316 | return; |
317 | ||
c4804411 ZW |
318 | dev_priv->mchbar_need_disable = false; |
319 | ||
320 | if (IS_I915G(dev) || IS_I915GM(dev)) { | |
e10fa551 | 321 | pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp); |
c4804411 ZW |
322 | enabled = !!(temp & DEVEN_MCHBAR_EN); |
323 | } else { | |
324 | pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); | |
325 | enabled = temp & 1; | |
326 | } | |
327 | ||
328 | /* If it's already enabled, don't have to do anything */ | |
329 | if (enabled) | |
330 | return; | |
331 | ||
332 | if (intel_alloc_mchbar_resource(dev)) | |
333 | return; | |
334 | ||
335 | dev_priv->mchbar_need_disable = true; | |
336 | ||
337 | /* Space is allocated or reserved, so enable it. */ | |
338 | if (IS_I915G(dev) || IS_I915GM(dev)) { | |
e10fa551 | 339 | pci_write_config_dword(dev_priv->bridge_dev, DEVEN, |
c4804411 ZW |
340 | temp | DEVEN_MCHBAR_EN); |
341 | } else { | |
342 | pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); | |
343 | pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1); | |
344 | } | |
345 | } | |
346 | ||
347 | static void | |
348 | intel_teardown_mchbar(struct drm_device *dev) | |
349 | { | |
4c8a4be9 | 350 | struct drm_i915_private *dev_priv = dev->dev_private; |
a6c45cf0 | 351 | int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915; |
c4804411 ZW |
352 | |
353 | if (dev_priv->mchbar_need_disable) { | |
354 | if (IS_I915G(dev) || IS_I915GM(dev)) { | |
e10fa551 JL |
355 | u32 deven_val; |
356 | ||
357 | pci_read_config_dword(dev_priv->bridge_dev, DEVEN, | |
358 | &deven_val); | |
359 | deven_val &= ~DEVEN_MCHBAR_EN; | |
360 | pci_write_config_dword(dev_priv->bridge_dev, DEVEN, | |
361 | deven_val); | |
c4804411 | 362 | } else { |
e10fa551 JL |
363 | u32 mchbar_val; |
364 | ||
365 | pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, | |
366 | &mchbar_val); | |
367 | mchbar_val &= ~1; | |
368 | pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, | |
369 | mchbar_val); | |
c4804411 ZW |
370 | } |
371 | } | |
372 | ||
373 | if (dev_priv->mch_res.start) | |
374 | release_resource(&dev_priv->mch_res); | |
375 | } | |
376 | ||
28d52043 DA |
377 | /* true = enable decode, false = disable decoder */ |
378 | static unsigned int i915_vga_set_decode(void *cookie, bool state) | |
379 | { | |
380 | struct drm_device *dev = cookie; | |
381 | ||
382 | intel_modeset_vga_set_state(dev, state); | |
383 | if (state) | |
384 | return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | | |
385 | VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
386 | else | |
387 | return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
388 | } | |
389 | ||
6a9ee8af DA |
390 | static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state) |
391 | { | |
392 | struct drm_device *dev = pci_get_drvdata(pdev); | |
393 | pm_message_t pmm = { .event = PM_EVENT_SUSPEND }; | |
1a5036bf | 394 | |
6a9ee8af | 395 | if (state == VGA_SWITCHEROO_ON) { |
a70491cc | 396 | pr_info("switched on\n"); |
5bcf719b | 397 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; |
6a9ee8af DA |
398 | /* i915 resume handler doesn't set to D0 */ |
399 | pci_set_power_state(dev->pdev, PCI_D0); | |
1751fcf9 | 400 | i915_resume_switcheroo(dev); |
5bcf719b | 401 | dev->switch_power_state = DRM_SWITCH_POWER_ON; |
6a9ee8af | 402 | } else { |
fa9d6078 | 403 | pr_info("switched off\n"); |
5bcf719b | 404 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; |
1751fcf9 | 405 | i915_suspend_switcheroo(dev, pmm); |
5bcf719b | 406 | dev->switch_power_state = DRM_SWITCH_POWER_OFF; |
6a9ee8af DA |
407 | } |
408 | } | |
409 | ||
410 | static bool i915_switcheroo_can_switch(struct pci_dev *pdev) | |
411 | { | |
412 | struct drm_device *dev = pci_get_drvdata(pdev); | |
6a9ee8af | 413 | |
fc8fd40e DV |
414 | /* |
415 | * FIXME: open_count is protected by drm_global_mutex but that would lead to | |
416 | * locking inversion with the driver load path. And the access here is | |
417 | * completely racy anyway. So don't bother with locking for now. | |
418 | */ | |
419 | return dev->open_count == 0; | |
6a9ee8af DA |
420 | } |
421 | ||
26ec685f TI |
422 | static const struct vga_switcheroo_client_ops i915_switcheroo_ops = { |
423 | .set_gpu_state = i915_switcheroo_set_state, | |
424 | .reprobe = NULL, | |
425 | .can_switch = i915_switcheroo_can_switch, | |
426 | }; | |
427 | ||
2c7111db CW |
428 | static int i915_load_modeset_init(struct drm_device *dev) |
429 | { | |
430 | struct drm_i915_private *dev_priv = dev->dev_private; | |
431 | int ret; | |
79e53945 | 432 | |
4fec15d1 ID |
433 | if (i915_inject_load_failure()) |
434 | return -ENODEV; | |
435 | ||
98f3a1dc | 436 | ret = intel_bios_init(dev_priv); |
79e53945 JB |
437 | if (ret) |
438 | DRM_INFO("failed to find VBIOS tables\n"); | |
439 | ||
934f992c CW |
440 | /* If we have > 1 VGA cards, then we need to arbitrate access |
441 | * to the common VGA resources. | |
442 | * | |
443 | * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA), | |
444 | * then we do not take part in VGA arbitration and the | |
445 | * vga_client_register() fails with -ENODEV. | |
446 | */ | |
ebff5fa9 DA |
447 | ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode); |
448 | if (ret && ret != -ENODEV) | |
449 | goto out; | |
28d52043 | 450 | |
723bfd70 JB |
451 | intel_register_dsm_handler(); |
452 | ||
0d69704a | 453 | ret = vga_switcheroo_register_client(dev->pdev, &i915_switcheroo_ops, false); |
6a9ee8af | 454 | if (ret) |
5a79395b | 455 | goto cleanup_vga_client; |
6a9ee8af | 456 | |
73dfc227 | 457 | intel_power_domains_init_hw(dev_priv, false); |
e13192f6 | 458 | |
f4448375 | 459 | intel_csr_ucode_init(dev_priv); |
ebae38d0 | 460 | |
2aeb7d3a | 461 | ret = intel_irq_install(dev_priv); |
52d7eced | 462 | if (ret) |
89250fec | 463 | goto cleanup_csr; |
52d7eced | 464 | |
f5949141 DV |
465 | intel_setup_gmbus(dev); |
466 | ||
52d7eced DV |
467 | /* Important: The output setup functions called by modeset_init need |
468 | * working irqs for e.g. gmbus and dp aux transfers. */ | |
b01f2c3a JB |
469 | intel_modeset_init(dev); |
470 | ||
33a732f4 | 471 | intel_guc_ucode_init(dev); |
33a732f4 | 472 | |
1070a42b | 473 | ret = i915_gem_init(dev); |
79e53945 | 474 | if (ret) |
713028b3 | 475 | goto cleanup_irq; |
2c7111db | 476 | |
52d7eced | 477 | intel_modeset_gem_init(dev); |
2c7111db | 478 | |
79e53945 JB |
479 | /* Always safe in the mode setting case. */ |
480 | /* FIXME: do pre/post-mode set stuff in core KMS code */ | |
ba0bf120 | 481 | dev->vblank_disable_allowed = true; |
713028b3 | 482 | if (INTEL_INFO(dev)->num_pipes == 0) |
e3c74757 | 483 | return 0; |
79e53945 | 484 | |
5a79395b CW |
485 | ret = intel_fbdev_init(dev); |
486 | if (ret) | |
52d7eced DV |
487 | goto cleanup_gem; |
488 | ||
20afbda2 | 489 | /* Only enable hotplug handling once the fbdev is fully set up. */ |
b963291c | 490 | intel_hpd_init(dev_priv); |
20afbda2 DV |
491 | |
492 | /* | |
493 | * Some ports require correctly set-up hpd registers for detection to | |
494 | * work properly (leading to ghost connected connector status), e.g. VGA | |
495 | * on gm45. Hence we can only set up the initial fbdev config after hpd | |
934458c2 JL |
496 | * irqs are fully enabled. Now we should scan for the initial config |
497 | * only once hotplug handling is enabled, but due to screwed-up locking | |
498 | * around kms/fbdev init we can't protect the fdbev initial config | |
499 | * scanning against hotplug events. Hence do this first and ignore the | |
500 | * tiny window where we will loose hotplug notifactions. | |
20afbda2 | 501 | */ |
e00bf696 | 502 | intel_fbdev_initial_config_async(dev); |
20afbda2 | 503 | |
eb1f8e4f | 504 | drm_kms_helper_poll_init(dev); |
87acb0a5 | 505 | |
79e53945 JB |
506 | return 0; |
507 | ||
2c7111db CW |
508 | cleanup_gem: |
509 | mutex_lock(&dev->struct_mutex); | |
117897f4 | 510 | i915_gem_cleanup_engines(dev); |
55d23285 | 511 | i915_gem_context_fini(dev); |
2c7111db | 512 | mutex_unlock(&dev->struct_mutex); |
713028b3 | 513 | cleanup_irq: |
33a732f4 | 514 | intel_guc_ucode_fini(dev); |
52d7eced | 515 | drm_irq_uninstall(dev); |
f5949141 | 516 | intel_teardown_gmbus(dev); |
89250fec ID |
517 | cleanup_csr: |
518 | intel_csr_ucode_fini(dev_priv); | |
65ff442f | 519 | intel_power_domains_fini(dev_priv); |
5a79395b CW |
520 | vga_switcheroo_unregister_client(dev->pdev); |
521 | cleanup_vga_client: | |
522 | vga_client_register(dev->pdev, NULL, NULL, NULL); | |
79e53945 JB |
523 | out: |
524 | return ret; | |
525 | } | |
526 | ||
243eaf38 | 527 | #if IS_ENABLED(CONFIG_FB) |
f96de58f | 528 | static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv) |
e188719a DV |
529 | { |
530 | struct apertures_struct *ap; | |
531 | struct pci_dev *pdev = dev_priv->dev->pdev; | |
72e96d64 | 532 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
e188719a | 533 | bool primary; |
f96de58f | 534 | int ret; |
e188719a DV |
535 | |
536 | ap = alloc_apertures(1); | |
537 | if (!ap) | |
f96de58f | 538 | return -ENOMEM; |
e188719a | 539 | |
72e96d64 JL |
540 | ap->ranges[0].base = ggtt->mappable_base; |
541 | ap->ranges[0].size = ggtt->mappable_end; | |
93d18799 | 542 | |
e188719a DV |
543 | primary = |
544 | pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW; | |
545 | ||
f96de58f | 546 | ret = remove_conflicting_framebuffers(ap, "inteldrmfb", primary); |
e188719a DV |
547 | |
548 | kfree(ap); | |
f96de58f CW |
549 | |
550 | return ret; | |
e188719a | 551 | } |
4520f53a | 552 | #else |
f96de58f | 553 | static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv) |
4520f53a | 554 | { |
f96de58f | 555 | return 0; |
4520f53a DV |
556 | } |
557 | #endif | |
e188719a | 558 | |
a4de0526 DV |
559 | #if !defined(CONFIG_VGA_CONSOLE) |
560 | static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv) | |
561 | { | |
562 | return 0; | |
563 | } | |
564 | #elif !defined(CONFIG_DUMMY_CONSOLE) | |
565 | static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv) | |
566 | { | |
567 | return -ENODEV; | |
568 | } | |
569 | #else | |
570 | static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv) | |
571 | { | |
1bb9e632 | 572 | int ret = 0; |
a4de0526 DV |
573 | |
574 | DRM_INFO("Replacing VGA console driver\n"); | |
575 | ||
576 | console_lock(); | |
1bb9e632 DV |
577 | if (con_is_bound(&vga_con)) |
578 | ret = do_take_over_console(&dummy_con, 0, MAX_NR_CONSOLES - 1, 1); | |
a4de0526 DV |
579 | if (ret == 0) { |
580 | ret = do_unregister_con_driver(&vga_con); | |
581 | ||
582 | /* Ignore "already unregistered". */ | |
583 | if (ret == -ENODEV) | |
584 | ret = 0; | |
585 | } | |
586 | console_unlock(); | |
587 | ||
588 | return ret; | |
589 | } | |
590 | #endif | |
591 | ||
c96ea64e DV |
592 | static void i915_dump_device_info(struct drm_i915_private *dev_priv) |
593 | { | |
5c969aa7 | 594 | const struct intel_device_info *info = &dev_priv->info; |
c96ea64e | 595 | |
e2a5800a DL |
596 | #define PRINT_S(name) "%s" |
597 | #define SEP_EMPTY | |
79fc46df DL |
598 | #define PRINT_FLAG(name) info->name ? #name "," : "" |
599 | #define SEP_COMMA , | |
19c656a1 | 600 | DRM_DEBUG_DRIVER("i915 device info: gen=%i, pciid=0x%04x rev=0x%02x flags=" |
e2a5800a | 601 | DEV_INFO_FOR_EACH_FLAG(PRINT_S, SEP_EMPTY), |
c96ea64e DV |
602 | info->gen, |
603 | dev_priv->dev->pdev->device, | |
19c656a1 | 604 | dev_priv->dev->pdev->revision, |
79fc46df | 605 | DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_COMMA)); |
e2a5800a DL |
606 | #undef PRINT_S |
607 | #undef SEP_EMPTY | |
79fc46df DL |
608 | #undef PRINT_FLAG |
609 | #undef SEP_COMMA | |
c96ea64e DV |
610 | } |
611 | ||
9705ad8a JM |
612 | static void cherryview_sseu_info_init(struct drm_device *dev) |
613 | { | |
614 | struct drm_i915_private *dev_priv = dev->dev_private; | |
615 | struct intel_device_info *info; | |
616 | u32 fuse, eu_dis; | |
617 | ||
618 | info = (struct intel_device_info *)&dev_priv->info; | |
619 | fuse = I915_READ(CHV_FUSE_GT); | |
620 | ||
621 | info->slice_total = 1; | |
622 | ||
623 | if (!(fuse & CHV_FGT_DISABLE_SS0)) { | |
624 | info->subslice_per_slice++; | |
625 | eu_dis = fuse & (CHV_FGT_EU_DIS_SS0_R0_MASK | | |
626 | CHV_FGT_EU_DIS_SS0_R1_MASK); | |
627 | info->eu_total += 8 - hweight32(eu_dis); | |
628 | } | |
629 | ||
630 | if (!(fuse & CHV_FGT_DISABLE_SS1)) { | |
631 | info->subslice_per_slice++; | |
632 | eu_dis = fuse & (CHV_FGT_EU_DIS_SS1_R0_MASK | | |
633 | CHV_FGT_EU_DIS_SS1_R1_MASK); | |
634 | info->eu_total += 8 - hweight32(eu_dis); | |
635 | } | |
636 | ||
637 | info->subslice_total = info->subslice_per_slice; | |
638 | /* | |
639 | * CHV expected to always have a uniform distribution of EU | |
640 | * across subslices. | |
641 | */ | |
642 | info->eu_per_subslice = info->subslice_total ? | |
643 | info->eu_total / info->subslice_total : | |
644 | 0; | |
645 | /* | |
646 | * CHV supports subslice power gating on devices with more than | |
647 | * one subslice, and supports EU power gating on devices with | |
648 | * more than one EU pair per subslice. | |
649 | */ | |
650 | info->has_slice_pg = 0; | |
651 | info->has_subslice_pg = (info->subslice_total > 1); | |
652 | info->has_eu_pg = (info->eu_per_subslice > 2); | |
653 | } | |
654 | ||
655 | static void gen9_sseu_info_init(struct drm_device *dev) | |
656 | { | |
657 | struct drm_i915_private *dev_priv = dev->dev_private; | |
658 | struct intel_device_info *info; | |
dead16e2 | 659 | int s_max = 3, ss_max = 4, eu_max = 8; |
9705ad8a | 660 | int s, ss; |
dead16e2 JM |
661 | u32 fuse2, s_enable, ss_disable, eu_disable; |
662 | u8 eu_mask = 0xff; | |
663 | ||
9705ad8a JM |
664 | info = (struct intel_device_info *)&dev_priv->info; |
665 | fuse2 = I915_READ(GEN8_FUSE2); | |
666 | s_enable = (fuse2 & GEN8_F2_S_ENA_MASK) >> | |
667 | GEN8_F2_S_ENA_SHIFT; | |
668 | ss_disable = (fuse2 & GEN9_F2_SS_DIS_MASK) >> | |
669 | GEN9_F2_SS_DIS_SHIFT; | |
670 | ||
9705ad8a JM |
671 | info->slice_total = hweight32(s_enable); |
672 | /* | |
673 | * The subslice disable field is global, i.e. it applies | |
674 | * to each of the enabled slices. | |
675 | */ | |
676 | info->subslice_per_slice = ss_max - hweight32(ss_disable); | |
677 | info->subslice_total = info->slice_total * | |
678 | info->subslice_per_slice; | |
679 | ||
680 | /* | |
681 | * Iterate through enabled slices and subslices to | |
682 | * count the total enabled EU. | |
683 | */ | |
684 | for (s = 0; s < s_max; s++) { | |
685 | if (!(s_enable & (0x1 << s))) | |
686 | /* skip disabled slice */ | |
687 | continue; | |
688 | ||
dead16e2 | 689 | eu_disable = I915_READ(GEN9_EU_DISABLE(s)); |
9705ad8a | 690 | for (ss = 0; ss < ss_max; ss++) { |
dead16e2 | 691 | int eu_per_ss; |
9705ad8a JM |
692 | |
693 | if (ss_disable & (0x1 << ss)) | |
694 | /* skip disabled subslice */ | |
695 | continue; | |
696 | ||
dead16e2 JM |
697 | eu_per_ss = eu_max - hweight8((eu_disable >> (ss*8)) & |
698 | eu_mask); | |
9705ad8a JM |
699 | |
700 | /* | |
701 | * Record which subslice(s) has(have) 7 EUs. we | |
702 | * can tune the hash used to spread work among | |
703 | * subslices if they are unbalanced. | |
704 | */ | |
dead16e2 | 705 | if (eu_per_ss == 7) |
9705ad8a JM |
706 | info->subslice_7eu[s] |= 1 << ss; |
707 | ||
dead16e2 | 708 | info->eu_total += eu_per_ss; |
9705ad8a JM |
709 | } |
710 | } | |
711 | ||
712 | /* | |
713 | * SKL is expected to always have a uniform distribution | |
714 | * of EU across subslices with the exception that any one | |
715 | * EU in any one subslice may be fused off for die | |
dead16e2 JM |
716 | * recovery. BXT is expected to be perfectly uniform in EU |
717 | * distribution. | |
9705ad8a JM |
718 | */ |
719 | info->eu_per_subslice = info->subslice_total ? | |
720 | DIV_ROUND_UP(info->eu_total, | |
721 | info->subslice_total) : 0; | |
722 | /* | |
723 | * SKL supports slice power gating on devices with more than | |
724 | * one slice, and supports EU power gating on devices with | |
dead16e2 JM |
725 | * more than one EU pair per subslice. BXT supports subslice |
726 | * power gating on devices with more than one subslice, and | |
727 | * supports EU power gating on devices with more than one EU | |
728 | * pair per subslice. | |
9705ad8a | 729 | */ |
ef11bdb3 RV |
730 | info->has_slice_pg = ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) && |
731 | (info->slice_total > 1)); | |
dead16e2 JM |
732 | info->has_subslice_pg = (IS_BROXTON(dev) && (info->subslice_total > 1)); |
733 | info->has_eu_pg = (info->eu_per_subslice > 2); | |
9705ad8a JM |
734 | } |
735 | ||
91bedd34 ŁD |
736 | static void broadwell_sseu_info_init(struct drm_device *dev) |
737 | { | |
738 | struct drm_i915_private *dev_priv = dev->dev_private; | |
739 | struct intel_device_info *info; | |
740 | const int s_max = 3, ss_max = 3, eu_max = 8; | |
741 | int s, ss; | |
742 | u32 fuse2, eu_disable[s_max], s_enable, ss_disable; | |
743 | ||
744 | fuse2 = I915_READ(GEN8_FUSE2); | |
745 | s_enable = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT; | |
746 | ss_disable = (fuse2 & GEN8_F2_SS_DIS_MASK) >> GEN8_F2_SS_DIS_SHIFT; | |
747 | ||
748 | eu_disable[0] = I915_READ(GEN8_EU_DISABLE0) & GEN8_EU_DIS0_S0_MASK; | |
749 | eu_disable[1] = (I915_READ(GEN8_EU_DISABLE0) >> GEN8_EU_DIS0_S1_SHIFT) | | |
750 | ((I915_READ(GEN8_EU_DISABLE1) & GEN8_EU_DIS1_S1_MASK) << | |
751 | (32 - GEN8_EU_DIS0_S1_SHIFT)); | |
752 | eu_disable[2] = (I915_READ(GEN8_EU_DISABLE1) >> GEN8_EU_DIS1_S2_SHIFT) | | |
753 | ((I915_READ(GEN8_EU_DISABLE2) & GEN8_EU_DIS2_S2_MASK) << | |
754 | (32 - GEN8_EU_DIS1_S2_SHIFT)); | |
755 | ||
756 | ||
757 | info = (struct intel_device_info *)&dev_priv->info; | |
758 | info->slice_total = hweight32(s_enable); | |
759 | ||
760 | /* | |
761 | * The subslice disable field is global, i.e. it applies | |
762 | * to each of the enabled slices. | |
763 | */ | |
764 | info->subslice_per_slice = ss_max - hweight32(ss_disable); | |
765 | info->subslice_total = info->slice_total * info->subslice_per_slice; | |
766 | ||
767 | /* | |
768 | * Iterate through enabled slices and subslices to | |
769 | * count the total enabled EU. | |
770 | */ | |
771 | for (s = 0; s < s_max; s++) { | |
772 | if (!(s_enable & (0x1 << s))) | |
773 | /* skip disabled slice */ | |
774 | continue; | |
775 | ||
776 | for (ss = 0; ss < ss_max; ss++) { | |
777 | u32 n_disabled; | |
778 | ||
779 | if (ss_disable & (0x1 << ss)) | |
780 | /* skip disabled subslice */ | |
781 | continue; | |
782 | ||
783 | n_disabled = hweight8(eu_disable[s] >> (ss * eu_max)); | |
784 | ||
785 | /* | |
786 | * Record which subslices have 7 EUs. | |
787 | */ | |
788 | if (eu_max - n_disabled == 7) | |
789 | info->subslice_7eu[s] |= 1 << ss; | |
790 | ||
791 | info->eu_total += eu_max - n_disabled; | |
792 | } | |
793 | } | |
794 | ||
795 | /* | |
796 | * BDW is expected to always have a uniform distribution of EU across | |
797 | * subslices with the exception that any one EU in any one subslice may | |
798 | * be fused off for die recovery. | |
799 | */ | |
800 | info->eu_per_subslice = info->subslice_total ? | |
801 | DIV_ROUND_UP(info->eu_total, info->subslice_total) : 0; | |
802 | ||
803 | /* | |
804 | * BDW supports slice power gating on devices with more than | |
805 | * one slice. | |
806 | */ | |
807 | info->has_slice_pg = (info->slice_total > 1); | |
808 | info->has_subslice_pg = 0; | |
809 | info->has_eu_pg = 0; | |
810 | } | |
811 | ||
22d3fd46 DL |
812 | /* |
813 | * Determine various intel_device_info fields at runtime. | |
814 | * | |
815 | * Use it when either: | |
816 | * - it's judged too laborious to fill n static structures with the limit | |
817 | * when a simple if statement does the job, | |
818 | * - run-time checks (eg read fuse/strap registers) are needed. | |
658ac4c6 DL |
819 | * |
820 | * This function needs to be called: | |
821 | * - after the MMIO has been setup as we are reading registers, | |
822 | * - after the PCH has been detected, | |
823 | * - before the first usage of the fields it can tweak. | |
22d3fd46 DL |
824 | */ |
825 | static void intel_device_info_runtime_init(struct drm_device *dev) | |
826 | { | |
658ac4c6 | 827 | struct drm_i915_private *dev_priv = dev->dev_private; |
22d3fd46 | 828 | struct intel_device_info *info; |
d615a166 | 829 | enum pipe pipe; |
22d3fd46 | 830 | |
658ac4c6 | 831 | info = (struct intel_device_info *)&dev_priv->info; |
22d3fd46 | 832 | |
edd43ed8 DL |
833 | /* |
834 | * Skylake and Broxton currently don't expose the topmost plane as its | |
835 | * use is exclusive with the legacy cursor and we only want to expose | |
836 | * one of those, not both. Until we can safely expose the topmost plane | |
837 | * as a DRM_PLANE_TYPE_CURSOR with all the features exposed/supported, | |
838 | * we don't expose the topmost plane at all to prevent ABI breakage | |
839 | * down the line. | |
840 | */ | |
8fb9397d | 841 | if (IS_BROXTON(dev)) { |
edd43ed8 DL |
842 | info->num_sprites[PIPE_A] = 2; |
843 | info->num_sprites[PIPE_B] = 2; | |
844 | info->num_sprites[PIPE_C] = 1; | |
666a4537 | 845 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
055e393f | 846 | for_each_pipe(dev_priv, pipe) |
d615a166 DL |
847 | info->num_sprites[pipe] = 2; |
848 | else | |
055e393f | 849 | for_each_pipe(dev_priv, pipe) |
d615a166 | 850 | info->num_sprites[pipe] = 1; |
658ac4c6 | 851 | |
a0bae57f DL |
852 | if (i915.disable_display) { |
853 | DRM_INFO("Display disabled (module parameter)\n"); | |
854 | info->num_pipes = 0; | |
855 | } else if (info->num_pipes > 0 && | |
856 | (INTEL_INFO(dev)->gen == 7 || INTEL_INFO(dev)->gen == 8) && | |
a7e478c7 | 857 | HAS_PCH_SPLIT(dev)) { |
658ac4c6 DL |
858 | u32 fuse_strap = I915_READ(FUSE_STRAP); |
859 | u32 sfuse_strap = I915_READ(SFUSE_STRAP); | |
860 | ||
861 | /* | |
862 | * SFUSE_STRAP is supposed to have a bit signalling the display | |
863 | * is fused off. Unfortunately it seems that, at least in | |
864 | * certain cases, fused off display means that PCH display | |
865 | * reads don't land anywhere. In that case, we read 0s. | |
866 | * | |
867 | * On CPT/PPT, we can detect this case as SFUSE_STRAP_FUSE_LOCK | |
868 | * should be set when taking over after the firmware. | |
869 | */ | |
870 | if (fuse_strap & ILK_INTERNAL_DISPLAY_DISABLE || | |
871 | sfuse_strap & SFUSE_STRAP_DISPLAY_DISABLED || | |
872 | (dev_priv->pch_type == PCH_CPT && | |
873 | !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) { | |
874 | DRM_INFO("Display fused off, disabling\n"); | |
875 | info->num_pipes = 0; | |
8c448cad GF |
876 | } else if (fuse_strap & IVB_PIPE_C_DISABLE) { |
877 | DRM_INFO("PipeC fused off\n"); | |
878 | info->num_pipes -= 1; | |
658ac4c6 | 879 | } |
bf4f2fb0 PJ |
880 | } else if (info->num_pipes > 0 && INTEL_INFO(dev)->gen == 9) { |
881 | u32 dfsm = I915_READ(SKL_DFSM); | |
882 | u8 disabled_mask = 0; | |
883 | bool invalid; | |
884 | int num_bits; | |
885 | ||
886 | if (dfsm & SKL_DFSM_PIPE_A_DISABLE) | |
887 | disabled_mask |= BIT(PIPE_A); | |
888 | if (dfsm & SKL_DFSM_PIPE_B_DISABLE) | |
889 | disabled_mask |= BIT(PIPE_B); | |
890 | if (dfsm & SKL_DFSM_PIPE_C_DISABLE) | |
891 | disabled_mask |= BIT(PIPE_C); | |
892 | ||
893 | num_bits = hweight8(disabled_mask); | |
894 | ||
895 | switch (disabled_mask) { | |
896 | case BIT(PIPE_A): | |
897 | case BIT(PIPE_B): | |
898 | case BIT(PIPE_A) | BIT(PIPE_B): | |
899 | case BIT(PIPE_A) | BIT(PIPE_C): | |
900 | invalid = true; | |
901 | break; | |
902 | default: | |
903 | invalid = false; | |
904 | } | |
905 | ||
906 | if (num_bits > info->num_pipes || invalid) | |
907 | DRM_ERROR("invalid pipe fuse configuration: 0x%x\n", | |
908 | disabled_mask); | |
909 | else | |
910 | info->num_pipes -= num_bits; | |
658ac4c6 | 911 | } |
693d11c3 | 912 | |
3873218f | 913 | /* Initialize slice/subslice/EU info */ |
9705ad8a JM |
914 | if (IS_CHERRYVIEW(dev)) |
915 | cherryview_sseu_info_init(dev); | |
91bedd34 ŁD |
916 | else if (IS_BROADWELL(dev)) |
917 | broadwell_sseu_info_init(dev); | |
dead16e2 | 918 | else if (INTEL_INFO(dev)->gen >= 9) |
9705ad8a | 919 | gen9_sseu_info_init(dev); |
3873218f | 920 | |
ca377809 TU |
921 | /* Snooping is broken on BXT A stepping. */ |
922 | info->has_snoop = !info->has_llc; | |
923 | info->has_snoop &= !IS_BXT_REVID(dev, 0, BXT_REVID_A1); | |
924 | ||
3873218f JM |
925 | DRM_DEBUG_DRIVER("slice total: %u\n", info->slice_total); |
926 | DRM_DEBUG_DRIVER("subslice total: %u\n", info->subslice_total); | |
927 | DRM_DEBUG_DRIVER("subslice per slice: %u\n", info->subslice_per_slice); | |
928 | DRM_DEBUG_DRIVER("EU total: %u\n", info->eu_total); | |
929 | DRM_DEBUG_DRIVER("EU per subslice: %u\n", info->eu_per_subslice); | |
930 | DRM_DEBUG_DRIVER("has slice power gating: %s\n", | |
931 | info->has_slice_pg ? "y" : "n"); | |
932 | DRM_DEBUG_DRIVER("has subslice power gating: %s\n", | |
933 | info->has_subslice_pg ? "y" : "n"); | |
934 | DRM_DEBUG_DRIVER("has EU power gating: %s\n", | |
935 | info->has_eu_pg ? "y" : "n"); | |
22d3fd46 DL |
936 | } |
937 | ||
e27f299e VS |
938 | static void intel_init_dpio(struct drm_i915_private *dev_priv) |
939 | { | |
e27f299e VS |
940 | /* |
941 | * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C), | |
942 | * CHV x1 PHY (DP/HDMI D) | |
943 | * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C) | |
944 | */ | |
945 | if (IS_CHERRYVIEW(dev_priv)) { | |
946 | DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2; | |
947 | DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO; | |
666a4537 | 948 | } else if (IS_VALLEYVIEW(dev_priv)) { |
e27f299e VS |
949 | DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO; |
950 | } | |
951 | } | |
952 | ||
399bb5b6 ID |
953 | static int i915_workqueues_init(struct drm_i915_private *dev_priv) |
954 | { | |
955 | /* | |
956 | * The i915 workqueue is primarily used for batched retirement of | |
957 | * requests (and thus managing bo) once the task has been completed | |
958 | * by the GPU. i915_gem_retire_requests() is called directly when we | |
959 | * need high-priority retirement, such as waiting for an explicit | |
960 | * bo. | |
961 | * | |
962 | * It is also used for periodic low-priority events, such as | |
963 | * idle-timers and recording error state. | |
964 | * | |
965 | * All tasks on the workqueue are expected to acquire the dev mutex | |
966 | * so there is no point in running more than one instance of the | |
967 | * workqueue at any time. Use an ordered one. | |
968 | */ | |
969 | dev_priv->wq = alloc_ordered_workqueue("i915", 0); | |
970 | if (dev_priv->wq == NULL) | |
971 | goto out_err; | |
972 | ||
973 | dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0); | |
974 | if (dev_priv->hotplug.dp_wq == NULL) | |
975 | goto out_free_wq; | |
976 | ||
977 | dev_priv->gpu_error.hangcheck_wq = | |
978 | alloc_ordered_workqueue("i915-hangcheck", 0); | |
979 | if (dev_priv->gpu_error.hangcheck_wq == NULL) | |
980 | goto out_free_dp_wq; | |
981 | ||
982 | return 0; | |
983 | ||
984 | out_free_dp_wq: | |
985 | destroy_workqueue(dev_priv->hotplug.dp_wq); | |
986 | out_free_wq: | |
987 | destroy_workqueue(dev_priv->wq); | |
988 | out_err: | |
989 | DRM_ERROR("Failed to allocate workqueues.\n"); | |
990 | ||
991 | return -ENOMEM; | |
992 | } | |
993 | ||
994 | static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv) | |
995 | { | |
996 | destroy_workqueue(dev_priv->gpu_error.hangcheck_wq); | |
997 | destroy_workqueue(dev_priv->hotplug.dp_wq); | |
998 | destroy_workqueue(dev_priv->wq); | |
999 | } | |
1000 | ||
5d7a6eef ID |
1001 | /** |
1002 | * i915_driver_init_early - setup state not requiring device access | |
1003 | * @dev_priv: device private | |
1004 | * | |
1005 | * Initialize everything that is a "SW-only" state, that is state not | |
1006 | * requiring accessing the device or exposing the driver via kernel internal | |
1007 | * or userspace interfaces. Example steps belonging here: lock initialization, | |
1008 | * system memory allocation, setting up device specific attributes and | |
1009 | * function hooks not requiring accessing the device. | |
1010 | */ | |
1011 | static int i915_driver_init_early(struct drm_i915_private *dev_priv, | |
1012 | struct drm_device *dev, | |
1013 | struct intel_device_info *info) | |
1014 | { | |
1015 | struct intel_device_info *device_info; | |
1016 | int ret = 0; | |
1017 | ||
4fec15d1 ID |
1018 | if (i915_inject_load_failure()) |
1019 | return -ENODEV; | |
1020 | ||
5d7a6eef ID |
1021 | /* Setup the write-once "constant" device info */ |
1022 | device_info = (struct intel_device_info *)&dev_priv->info; | |
1023 | memcpy(device_info, info, sizeof(dev_priv->info)); | |
1024 | device_info->device_id = dev->pdev->device; | |
1025 | ||
1026 | spin_lock_init(&dev_priv->irq_lock); | |
1027 | spin_lock_init(&dev_priv->gpu_error.lock); | |
1028 | mutex_init(&dev_priv->backlight_lock); | |
1029 | spin_lock_init(&dev_priv->uncore.lock); | |
1030 | spin_lock_init(&dev_priv->mm.object_stat_lock); | |
1031 | spin_lock_init(&dev_priv->mmio_flip_lock); | |
1032 | mutex_init(&dev_priv->sb_lock); | |
1033 | mutex_init(&dev_priv->modeset_restore_lock); | |
1034 | mutex_init(&dev_priv->av_mutex); | |
1035 | mutex_init(&dev_priv->wm.wm_mutex); | |
1036 | mutex_init(&dev_priv->pps_mutex); | |
1037 | ||
1038 | ret = i915_workqueues_init(dev_priv); | |
1039 | if (ret < 0) | |
1040 | return ret; | |
1041 | ||
1042 | /* This must be called before any calls to HAS_PCH_* */ | |
1043 | intel_detect_pch(dev); | |
1044 | ||
1045 | intel_pm_setup(dev); | |
1046 | intel_init_dpio(dev_priv); | |
1047 | intel_power_domains_init(dev_priv); | |
1048 | intel_irq_init(dev_priv); | |
1049 | intel_init_display_hooks(dev_priv); | |
1050 | intel_init_clock_gating_hooks(dev_priv); | |
1051 | intel_init_audio_hooks(dev_priv); | |
1052 | i915_gem_load_init(dev); | |
1053 | ||
1054 | intel_display_crc_init(dev); | |
1055 | ||
1056 | i915_dump_device_info(dev_priv); | |
1057 | ||
1058 | /* Not all pre-production machines fall into this category, only the | |
1059 | * very first ones. Almost everything should work, except for maybe | |
1060 | * suspend/resume. And we don't implement workarounds that affect only | |
1061 | * pre-production machines. */ | |
1062 | if (IS_HSW_EARLY_SDV(dev)) | |
1063 | DRM_INFO("This is an early pre-production Haswell machine. " | |
1064 | "It may not be fully functional.\n"); | |
1065 | ||
1066 | return 0; | |
1067 | } | |
1068 | ||
1069 | /** | |
1070 | * i915_driver_cleanup_early - cleanup the setup done in i915_driver_init_early() | |
1071 | * @dev_priv: device private | |
1072 | */ | |
1073 | static void i915_driver_cleanup_early(struct drm_i915_private *dev_priv) | |
1074 | { | |
1075 | i915_gem_load_cleanup(dev_priv->dev); | |
1076 | i915_workqueues_cleanup(dev_priv); | |
1077 | } | |
1078 | ||
ad5c3d3f ID |
1079 | static int i915_mmio_setup(struct drm_device *dev) |
1080 | { | |
1081 | struct drm_i915_private *dev_priv = to_i915(dev); | |
1082 | int mmio_bar; | |
1083 | int mmio_size; | |
1084 | ||
1085 | mmio_bar = IS_GEN2(dev) ? 1 : 0; | |
1086 | /* | |
1087 | * Before gen4, the registers and the GTT are behind different BARs. | |
1088 | * However, from gen4 onwards, the registers and the GTT are shared | |
1089 | * in the same BAR, so we want to restrict this ioremap from | |
1090 | * clobbering the GTT which we want ioremap_wc instead. Fortunately, | |
1091 | * the register BAR remains the same size for all the earlier | |
1092 | * generations up to Ironlake. | |
1093 | */ | |
1094 | if (INTEL_INFO(dev)->gen < 5) | |
1095 | mmio_size = 512 * 1024; | |
1096 | else | |
1097 | mmio_size = 2 * 1024 * 1024; | |
1098 | dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, mmio_size); | |
1099 | if (dev_priv->regs == NULL) { | |
1100 | DRM_ERROR("failed to map registers\n"); | |
1101 | ||
1102 | return -EIO; | |
1103 | } | |
1104 | ||
1105 | /* Try to make sure MCHBAR is enabled before poking at it */ | |
1106 | intel_setup_mchbar(dev); | |
1107 | ||
1108 | return 0; | |
1109 | } | |
1110 | ||
1111 | static void i915_mmio_cleanup(struct drm_device *dev) | |
1112 | { | |
1113 | struct drm_i915_private *dev_priv = to_i915(dev); | |
1114 | ||
1115 | intel_teardown_mchbar(dev); | |
1116 | pci_iounmap(dev->pdev, dev_priv->regs); | |
1117 | } | |
1118 | ||
f28cea45 ID |
1119 | /** |
1120 | * i915_driver_init_mmio - setup device MMIO | |
1121 | * @dev_priv: device private | |
1122 | * | |
1123 | * Setup minimal device state necessary for MMIO accesses later in the | |
1124 | * initialization sequence. The setup here should avoid any other device-wide | |
1125 | * side effects or exposing the driver via kernel internal or user space | |
1126 | * interfaces. | |
1127 | */ | |
1128 | static int i915_driver_init_mmio(struct drm_i915_private *dev_priv) | |
1129 | { | |
1130 | struct drm_device *dev = dev_priv->dev; | |
1131 | int ret; | |
1132 | ||
4fec15d1 ID |
1133 | if (i915_inject_load_failure()) |
1134 | return -ENODEV; | |
1135 | ||
f28cea45 ID |
1136 | if (i915_get_bridge_dev(dev)) |
1137 | return -EIO; | |
1138 | ||
1139 | ret = i915_mmio_setup(dev); | |
1140 | if (ret < 0) | |
1141 | goto put_bridge; | |
1142 | ||
1143 | intel_uncore_init(dev); | |
1144 | ||
1145 | return 0; | |
1146 | ||
1147 | put_bridge: | |
1148 | pci_dev_put(dev_priv->bridge_dev); | |
1149 | ||
1150 | return ret; | |
1151 | } | |
1152 | ||
1153 | /** | |
1154 | * i915_driver_cleanup_mmio - cleanup the setup done in i915_driver_init_mmio() | |
1155 | * @dev_priv: device private | |
1156 | */ | |
1157 | static void i915_driver_cleanup_mmio(struct drm_i915_private *dev_priv) | |
1158 | { | |
1159 | struct drm_device *dev = dev_priv->dev; | |
1160 | ||
1161 | intel_uncore_fini(dev); | |
1162 | i915_mmio_cleanup(dev); | |
1163 | pci_dev_put(dev_priv->bridge_dev); | |
1164 | } | |
1165 | ||
79e53945 | 1166 | /** |
09cfcb45 ID |
1167 | * i915_driver_init_hw - setup state requiring device access |
1168 | * @dev_priv: device private | |
79e53945 | 1169 | * |
09cfcb45 ID |
1170 | * Setup state that requires accessing the device, but doesn't require |
1171 | * exposing the driver via kernel internal or userspace interfaces. | |
79e53945 | 1172 | */ |
09cfcb45 | 1173 | static int i915_driver_init_hw(struct drm_i915_private *dev_priv) |
22eae947 | 1174 | { |
09cfcb45 | 1175 | struct drm_device *dev = dev_priv->dev; |
72e96d64 | 1176 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
9021f284 | 1177 | uint32_t aperture_size; |
09cfcb45 | 1178 | int ret; |
c3d685a7 | 1179 | |
4fec15d1 ID |
1180 | if (i915_inject_load_failure()) |
1181 | return -ENODEV; | |
1182 | ||
13c8f4c8 ID |
1183 | intel_device_info_runtime_init(dev); |
1184 | ||
d85489d3 | 1185 | ret = i915_ggtt_init_hw(dev); |
e76e9aeb | 1186 | if (ret) |
09cfcb45 | 1187 | return ret; |
e188719a | 1188 | |
17fa6463 DV |
1189 | /* WARNING: Apparently we must kick fbdev drivers before vgacon, |
1190 | * otherwise the vga fbdev driver falls over. */ | |
1191 | ret = i915_kick_out_firmware_fb(dev_priv); | |
1192 | if (ret) { | |
1193 | DRM_ERROR("failed to remove conflicting framebuffer drivers\n"); | |
d85489d3 | 1194 | goto out_ggtt; |
17fa6463 | 1195 | } |
a4de0526 | 1196 | |
17fa6463 DV |
1197 | ret = i915_kick_out_vgacon(dev_priv); |
1198 | if (ret) { | |
1199 | DRM_ERROR("failed to remove conflicting VGA console\n"); | |
d85489d3 | 1200 | goto out_ggtt; |
a4de0526 | 1201 | } |
e188719a | 1202 | |
466e69b8 DA |
1203 | pci_set_master(dev->pdev); |
1204 | ||
9f82d238 DV |
1205 | /* overlay on gen2 is broken and can't address above 1G */ |
1206 | if (IS_GEN2(dev)) | |
1207 | dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30)); | |
1208 | ||
6927faf3 JN |
1209 | /* 965GM sometimes incorrectly writes to hardware status page (HWS) |
1210 | * using 32bit addressing, overwriting memory if HWS is located | |
1211 | * above 4GB. | |
1212 | * | |
1213 | * The documentation also mentions an issue with undefined | |
1214 | * behaviour if any general state is accessed within a page above 4GB, | |
1215 | * which also needs to be handled carefully. | |
1216 | */ | |
1217 | if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) | |
1218 | dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(32)); | |
1219 | ||
72e96d64 | 1220 | aperture_size = ggtt->mappable_end; |
71e9339c | 1221 | |
72e96d64 JL |
1222 | ggtt->mappable = |
1223 | io_mapping_create_wc(ggtt->mappable_base, | |
dd2757f8 | 1224 | aperture_size); |
72e96d64 | 1225 | if (!ggtt->mappable) { |
6644107d | 1226 | ret = -EIO; |
d85489d3 | 1227 | goto out_ggtt; |
6644107d VP |
1228 | } |
1229 | ||
72e96d64 | 1230 | ggtt->mtrr = arch_phys_wc_add(ggtt->mappable_base, |
911bdf0a | 1231 | aperture_size); |
19966754 | 1232 | |
bd39ec5d ID |
1233 | pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, |
1234 | PM_QOS_DEFAULT_VALUE); | |
1235 | ||
78511f2a | 1236 | intel_uncore_sanitize(dev); |
9880b7a5 | 1237 | |
44834a67 | 1238 | intel_opregion_setup(dev); |
c4804411 | 1239 | |
40ae4e16 ID |
1240 | i915_gem_load_init_fences(dev_priv); |
1241 | ||
ed4cb414 EA |
1242 | /* On the 945G/GM, the chipset reports the MSI capability on the |
1243 | * integrated graphics even though the support isn't actually there | |
1244 | * according to the published specs. It doesn't appear to function | |
1245 | * correctly in testing on 945G. | |
1246 | * This may be a side effect of MSI having been made available for PEG | |
1247 | * and the registers being closely associated. | |
d1ed629f KP |
1248 | * |
1249 | * According to chipset errata, on the 965GM, MSI interrupts may | |
b60678a7 KP |
1250 | * be lost or delayed, but we use them anyways to avoid |
1251 | * stuck interrupts on some machines. | |
ed4cb414 | 1252 | */ |
b074eae1 ID |
1253 | if (!IS_I945G(dev) && !IS_I945GM(dev)) { |
1254 | if (pci_enable_msi(dev->pdev) < 0) | |
1255 | DRM_DEBUG_DRIVER("can't enable MSI"); | |
1256 | } | |
ed4cb414 | 1257 | |
09cfcb45 ID |
1258 | return 0; |
1259 | ||
d85489d3 JL |
1260 | out_ggtt: |
1261 | i915_ggtt_cleanup_hw(dev); | |
09cfcb45 ID |
1262 | |
1263 | return ret; | |
1264 | } | |
1265 | ||
1266 | /** | |
1267 | * i915_driver_cleanup_hw - cleanup the setup done in i915_driver_init_hw() | |
1268 | * @dev_priv: device private | |
1269 | */ | |
1270 | static void i915_driver_cleanup_hw(struct drm_i915_private *dev_priv) | |
1271 | { | |
1272 | struct drm_device *dev = dev_priv->dev; | |
72e96d64 | 1273 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
09cfcb45 ID |
1274 | |
1275 | if (dev->pdev->msi_enabled) | |
1276 | pci_disable_msi(dev->pdev); | |
1277 | ||
1278 | pm_qos_remove_request(&dev_priv->pm_qos); | |
72e96d64 JL |
1279 | arch_phys_wc_del(ggtt->mtrr); |
1280 | io_mapping_free(ggtt->mappable); | |
d85489d3 | 1281 | i915_ggtt_cleanup_hw(dev); |
09cfcb45 ID |
1282 | } |
1283 | ||
432f856d ID |
1284 | /** |
1285 | * i915_driver_register - register the driver with the rest of the system | |
1286 | * @dev_priv: device private | |
1287 | * | |
1288 | * Perform any steps necessary to make the driver available via kernel | |
1289 | * internal or userspace interfaces. | |
1290 | */ | |
1291 | static void i915_driver_register(struct drm_i915_private *dev_priv) | |
1292 | { | |
1293 | struct drm_device *dev = dev_priv->dev; | |
1294 | ||
1295 | i915_gem_shrinker_init(dev_priv); | |
1296 | /* | |
1297 | * Notify a valid surface after modesetting, | |
1298 | * when running inside a VM. | |
1299 | */ | |
1300 | if (intel_vgpu_active(dev)) | |
1301 | I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY); | |
1302 | ||
1303 | i915_setup_sysfs(dev); | |
1304 | ||
1305 | if (INTEL_INFO(dev_priv)->num_pipes) { | |
1306 | /* Must be done after probing outputs */ | |
1307 | intel_opregion_init(dev); | |
1308 | acpi_video_register(); | |
1309 | } | |
1310 | ||
1311 | if (IS_GEN5(dev_priv)) | |
1312 | intel_gpu_ips_init(dev_priv); | |
1313 | ||
1314 | i915_audio_component_init(dev_priv); | |
1315 | } | |
1316 | ||
1317 | /** | |
1318 | * i915_driver_unregister - cleanup the registration done in i915_driver_regiser() | |
1319 | * @dev_priv: device private | |
1320 | */ | |
1321 | static void i915_driver_unregister(struct drm_i915_private *dev_priv) | |
1322 | { | |
1323 | i915_audio_component_cleanup(dev_priv); | |
1324 | intel_gpu_ips_teardown(); | |
1325 | acpi_video_unregister(); | |
1326 | intel_opregion_fini(dev_priv->dev); | |
1327 | i915_teardown_sysfs(dev_priv->dev); | |
1328 | i915_gem_shrinker_cleanup(dev_priv); | |
1329 | } | |
1330 | ||
09cfcb45 ID |
1331 | /** |
1332 | * i915_driver_load - setup chip and create an initial config | |
1333 | * @dev: DRM device | |
1334 | * @flags: startup flags | |
1335 | * | |
1336 | * The driver load routine has to do several things: | |
1337 | * - drive output discovery via intel_modeset_init() | |
1338 | * - initialize the memory manager | |
1339 | * - allocate initial config memory | |
1340 | * - setup the DRM framebuffer with the allocated memory | |
1341 | */ | |
1342 | int i915_driver_load(struct drm_device *dev, unsigned long flags) | |
1343 | { | |
1344 | struct drm_i915_private *dev_priv; | |
1345 | int ret = 0; | |
1346 | ||
1347 | dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL); | |
1348 | if (dev_priv == NULL) | |
1349 | return -ENOMEM; | |
1350 | ||
1351 | dev->dev_private = dev_priv; | |
d15d7538 ID |
1352 | /* Must be set before calling __i915_printk */ |
1353 | dev_priv->dev = dev; | |
09cfcb45 ID |
1354 | |
1355 | ret = i915_driver_init_early(dev_priv, dev, | |
1356 | (struct intel_device_info *)flags); | |
1357 | ||
1358 | if (ret < 0) | |
1359 | goto out_free_priv; | |
1360 | ||
1361 | intel_runtime_pm_get(dev_priv); | |
1362 | ||
1363 | ret = i915_driver_init_mmio(dev_priv); | |
1364 | if (ret < 0) | |
1365 | goto out_runtime_pm_put; | |
1366 | ||
1367 | ret = i915_driver_init_hw(dev_priv); | |
1368 | if (ret < 0) | |
1369 | goto out_cleanup_mmio; | |
1370 | ||
432f856d ID |
1371 | /* |
1372 | * TODO: move the vblank init and parts of modeset init steps into one | |
1373 | * of the i915_driver_init_/i915_driver_register functions according | |
1374 | * to the role/effect of the given init step. | |
1375 | */ | |
e3c74757 BW |
1376 | if (INTEL_INFO(dev)->num_pipes) { |
1377 | ret = drm_vblank_init(dev, INTEL_INFO(dev)->num_pipes); | |
1378 | if (ret) | |
09cfcb45 | 1379 | goto out_cleanup_hw; |
e3c74757 | 1380 | } |
52440211 | 1381 | |
17fa6463 | 1382 | ret = i915_load_modeset_init(dev); |
d15d7538 | 1383 | if (ret < 0) |
65ff442f | 1384 | goto out_cleanup_vblank; |
79e53945 | 1385 | |
432f856d | 1386 | i915_driver_register(dev_priv); |
58fddc28 | 1387 | |
3487b66b ID |
1388 | intel_runtime_pm_enable(dev_priv); |
1389 | ||
1f814dac ID |
1390 | intel_runtime_pm_put(dev_priv); |
1391 | ||
79e53945 JB |
1392 | return 0; |
1393 | ||
65ff442f | 1394 | out_cleanup_vblank: |
cbb47d17 | 1395 | drm_vblank_cleanup(dev); |
09cfcb45 ID |
1396 | out_cleanup_hw: |
1397 | i915_driver_cleanup_hw(dev_priv); | |
f28cea45 ID |
1398 | out_cleanup_mmio: |
1399 | i915_driver_cleanup_mmio(dev_priv); | |
02036cee | 1400 | out_runtime_pm_put: |
1f814dac | 1401 | intel_runtime_pm_put(dev_priv); |
5d7a6eef | 1402 | i915_driver_cleanup_early(dev_priv); |
399bb5b6 | 1403 | out_free_priv: |
d15d7538 ID |
1404 | i915_load_error(dev_priv, "Device initialization failed (%d)\n", ret); |
1405 | ||
2dc10cd8 MK |
1406 | kfree(dev_priv); |
1407 | ||
ba8bbcf6 JB |
1408 | return ret; |
1409 | } | |
1410 | ||
1411 | int i915_driver_unload(struct drm_device *dev) | |
1412 | { | |
1413 | struct drm_i915_private *dev_priv = dev->dev_private; | |
c911fc1c | 1414 | int ret; |
ba8bbcf6 | 1415 | |
2013bfc0 VS |
1416 | intel_fbdev_fini(dev); |
1417 | ||
ce58c32b CW |
1418 | ret = i915_gem_suspend(dev); |
1419 | if (ret) { | |
1420 | DRM_ERROR("failed to idle hardware: %d\n", ret); | |
1421 | return ret; | |
1422 | } | |
1423 | ||
250ad48e | 1424 | intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); |
8a187455 | 1425 | |
432f856d | 1426 | i915_driver_unregister(dev_priv); |
44834a67 | 1427 | |
2ebfaf5f PZ |
1428 | drm_vblank_cleanup(dev); |
1429 | ||
17fa6463 | 1430 | intel_modeset_cleanup(dev); |
6c0d9350 | 1431 | |
17fa6463 DV |
1432 | /* |
1433 | * free the memory space allocated for the child device | |
1434 | * config parsed from VBT | |
1435 | */ | |
1436 | if (dev_priv->vbt.child_dev && dev_priv->vbt.child_dev_num) { | |
1437 | kfree(dev_priv->vbt.child_dev); | |
1438 | dev_priv->vbt.child_dev = NULL; | |
1439 | dev_priv->vbt.child_dev_num = 0; | |
79e53945 | 1440 | } |
9aa61142 MR |
1441 | kfree(dev_priv->vbt.sdvo_lvds_vbt_mode); |
1442 | dev_priv->vbt.sdvo_lvds_vbt_mode = NULL; | |
1443 | kfree(dev_priv->vbt.lfp_lvds_vbt_mode); | |
1444 | dev_priv->vbt.lfp_lvds_vbt_mode = NULL; | |
79e53945 | 1445 | |
17fa6463 DV |
1446 | vga_switcheroo_unregister_client(dev->pdev); |
1447 | vga_client_register(dev->pdev, NULL, NULL, NULL); | |
1448 | ||
89250fec ID |
1449 | intel_csr_ucode_fini(dev_priv); |
1450 | ||
a8b4899e | 1451 | /* Free error state after interrupts are fully disabled. */ |
737b1506 | 1452 | cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work); |
a8b4899e | 1453 | i915_destroy_error_state(dev); |
bc0c7f14 | 1454 | |
17fa6463 DV |
1455 | /* Flush any outstanding unpin_work. */ |
1456 | flush_workqueue(dev_priv->wq); | |
67e77c5a | 1457 | |
33a732f4 | 1458 | intel_guc_ucode_fini(dev); |
bf248ca1 | 1459 | mutex_lock(&dev->struct_mutex); |
117897f4 | 1460 | i915_gem_cleanup_engines(dev); |
17fa6463 DV |
1461 | i915_gem_context_fini(dev); |
1462 | mutex_unlock(&dev->struct_mutex); | |
7733b49b | 1463 | intel_fbc_cleanup_cfb(dev_priv); |
79e53945 | 1464 | |
250ad48e ID |
1465 | intel_power_domains_fini(dev_priv); |
1466 | ||
09cfcb45 | 1467 | i915_driver_cleanup_hw(dev_priv); |
f28cea45 | 1468 | i915_driver_cleanup_mmio(dev_priv); |
250ad48e ID |
1469 | |
1470 | intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); | |
1471 | ||
5d7a6eef | 1472 | i915_driver_cleanup_early(dev_priv); |
2206e6a1 | 1473 | kfree(dev_priv); |
ba8bbcf6 | 1474 | |
22eae947 DA |
1475 | return 0; |
1476 | } | |
1477 | ||
f787a5f5 | 1478 | int i915_driver_open(struct drm_device *dev, struct drm_file *file) |
673a394b | 1479 | { |
b29c19b6 | 1480 | int ret; |
673a394b | 1481 | |
b29c19b6 CW |
1482 | ret = i915_gem_open(dev, file); |
1483 | if (ret) | |
1484 | return ret; | |
254f965c | 1485 | |
673a394b EA |
1486 | return 0; |
1487 | } | |
1488 | ||
79e53945 JB |
1489 | /** |
1490 | * i915_driver_lastclose - clean up after all DRM clients have exited | |
1491 | * @dev: DRM device | |
1492 | * | |
1493 | * Take care of cleaning up after all DRM clients have exited. In the | |
1494 | * mode setting case, we want to restore the kernel's initial mode (just | |
1495 | * in case the last client left us in a bad state). | |
1496 | * | |
9021f284 | 1497 | * Additionally, in the non-mode setting case, we'll tear down the GTT |
79e53945 JB |
1498 | * and DMA structures, since the kernel won't be using them, and clea |
1499 | * up any GEM state. | |
1500 | */ | |
1a5036bf | 1501 | void i915_driver_lastclose(struct drm_device *dev) |
1da177e4 | 1502 | { |
377e91b2 DV |
1503 | intel_fbdev_restore_mode(dev); |
1504 | vga_switcheroo_process_delayed_switch(); | |
1da177e4 LT |
1505 | } |
1506 | ||
2885f6ac | 1507 | void i915_driver_preclose(struct drm_device *dev, struct drm_file *file) |
1da177e4 | 1508 | { |
0d1430a3 | 1509 | mutex_lock(&dev->struct_mutex); |
2885f6ac JH |
1510 | i915_gem_context_close(dev, file); |
1511 | i915_gem_release(dev, file); | |
0d1430a3 | 1512 | mutex_unlock(&dev->struct_mutex); |
1da177e4 LT |
1513 | } |
1514 | ||
f787a5f5 | 1515 | void i915_driver_postclose(struct drm_device *dev, struct drm_file *file) |
673a394b | 1516 | { |
f787a5f5 | 1517 | struct drm_i915_file_private *file_priv = file->driver_priv; |
673a394b | 1518 | |
f787a5f5 | 1519 | kfree(file_priv); |
673a394b EA |
1520 | } |
1521 | ||
4feb7659 DV |
1522 | static int |
1523 | i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data, | |
1524 | struct drm_file *file) | |
1525 | { | |
1526 | return -ENODEV; | |
1527 | } | |
1528 | ||
baa70943 | 1529 | const struct drm_ioctl_desc i915_ioctls[] = { |
77f31815 DV |
1530 | DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
1531 | DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH), | |
1532 | DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH), | |
1533 | DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH), | |
1534 | DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH), | |
1535 | DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH), | |
10ba5012 | 1536 | DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH|DRM_RENDER_ALLOW), |
c668cde5 | 1537 | DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
b2c606fe DV |
1538 | DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH), |
1539 | DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH), | |
1540 | DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
77f31815 | 1541 | DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH), |
b2c606fe | 1542 | DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
d1c1edbc | 1543 | DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
77f31815 DV |
1544 | DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, drm_noop, DRM_AUTH), |
1545 | DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH), | |
1546 | DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
f8c47144 DV |
1547 | DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
1548 | DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH), | |
1549 | DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_RENDER_ALLOW), | |
1550 | DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY), | |
1551 | DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY), | |
1552 | DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), | |
1553 | DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW), | |
1554 | DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW), | |
1555 | DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), | |
1556 | DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
1557 | DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
1558 | DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW), | |
1559 | DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW), | |
1560 | DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW), | |
1561 | DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW), | |
1562 | DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_RENDER_ALLOW), | |
1563 | DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW), | |
1564 | DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW), | |
1565 | DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_RENDER_ALLOW), | |
1566 | DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_RENDER_ALLOW), | |
1567 | DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW), | |
1568 | DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, 0), | |
1569 | DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW), | |
1570 | DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW), | |
1571 | DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW), | |
1572 | DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW), | |
1573 | DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER|DRM_CONTROL_ALLOW), | |
1574 | DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), | |
1575 | DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW), | |
1576 | DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW), | |
1577 | DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW), | |
1578 | DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_get_reset_stats_ioctl, DRM_RENDER_ALLOW), | |
1579 | DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW), | |
1580 | DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW), | |
1581 | DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW), | |
c94f7029 DA |
1582 | }; |
1583 | ||
f95aeb17 | 1584 | int i915_max_ioctl = ARRAY_SIZE(i915_ioctls); |