Commit | Line | Data |
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1da177e4 LT |
1 | /* i915_dma.c -- DMA support for the I915 -*- linux-c -*- |
2 | */ | |
0d6aa60b | 3 | /* |
1da177e4 LT |
4 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
5 | * All Rights Reserved. | |
bc54fd1a DA |
6 | * |
7 | * Permission is hereby granted, free of charge, to any person obtaining a | |
8 | * copy of this software and associated documentation files (the | |
9 | * "Software"), to deal in the Software without restriction, including | |
10 | * without limitation the rights to use, copy, modify, merge, publish, | |
11 | * distribute, sub license, and/or sell copies of the Software, and to | |
12 | * permit persons to whom the Software is furnished to do so, subject to | |
13 | * the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice (including the | |
16 | * next paragraph) shall be included in all copies or substantial portions | |
17 | * of the Software. | |
18 | * | |
19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
20 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
21 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
22 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
23 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
24 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
25 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
26 | * | |
0d6aa60b | 27 | */ |
1da177e4 | 28 | |
a70491cc JP |
29 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
30 | ||
760285e7 DH |
31 | #include <drm/drmP.h> |
32 | #include <drm/drm_crtc_helper.h> | |
33 | #include <drm/drm_fb_helper.h> | |
79e53945 | 34 | #include "intel_drv.h" |
760285e7 | 35 | #include <drm/i915_drm.h> |
1da177e4 | 36 | #include "i915_drv.h" |
1c5d22f7 | 37 | #include "i915_trace.h" |
dcdb1674 | 38 | #include <linux/pci.h> |
28d52043 | 39 | #include <linux/vgaarb.h> |
c4804411 ZW |
40 | #include <linux/acpi.h> |
41 | #include <linux/pnp.h> | |
6a9ee8af | 42 | #include <linux/vga_switcheroo.h> |
5a0e3ad6 | 43 | #include <linux/slab.h> |
44834a67 | 44 | #include <acpi/video.h> |
9e984bc1 | 45 | #include <asm/pat.h> |
1da177e4 | 46 | |
09422b2e DV |
47 | #define LP_RING(d) (&((struct drm_i915_private *)(d))->ring[RCS]) |
48 | ||
49 | #define BEGIN_LP_RING(n) \ | |
50 | intel_ring_begin(LP_RING(dev_priv), (n)) | |
51 | ||
52 | #define OUT_RING(x) \ | |
53 | intel_ring_emit(LP_RING(dev_priv), x) | |
54 | ||
55 | #define ADVANCE_LP_RING() \ | |
56 | intel_ring_advance(LP_RING(dev_priv)) | |
57 | ||
58 | /** | |
59 | * Lock test for when it's just for synchronization of ring access. | |
60 | * | |
61 | * In that case, we don't need to do it when GEM is initialized as nobody else | |
62 | * has access to the ring. | |
63 | */ | |
64 | #define RING_LOCK_TEST_WITH_RETURN(dev, file) do { \ | |
65 | if (LP_RING(dev->dev_private)->obj == NULL) \ | |
66 | LOCK_TEST_WITH_RETURN(dev, file); \ | |
67 | } while (0) | |
68 | ||
316d3884 DV |
69 | static inline u32 |
70 | intel_read_legacy_status_page(struct drm_i915_private *dev_priv, int reg) | |
71 | { | |
72 | if (I915_NEED_GFX_HWS(dev_priv->dev)) | |
73 | return ioread32(dev_priv->dri1.gfx_hws_cpu_addr + reg); | |
74 | else | |
75 | return intel_read_status_page(LP_RING(dev_priv), reg); | |
76 | } | |
77 | ||
78 | #define READ_HWSP(dev_priv, reg) intel_read_legacy_status_page(dev_priv, reg) | |
09422b2e DV |
79 | #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX) |
80 | #define I915_BREADCRUMB_INDEX 0x21 | |
81 | ||
d05c617e DV |
82 | void i915_update_dri1_breadcrumb(struct drm_device *dev) |
83 | { | |
84 | drm_i915_private_t *dev_priv = dev->dev_private; | |
85 | struct drm_i915_master_private *master_priv; | |
86 | ||
87 | if (dev->primary->master) { | |
88 | master_priv = dev->primary->master->driver_priv; | |
89 | if (master_priv->sarea_priv) | |
90 | master_priv->sarea_priv->last_dispatch = | |
91 | READ_BREADCRUMB(dev_priv); | |
92 | } | |
93 | } | |
94 | ||
4cbf74cc CW |
95 | static void i915_write_hws_pga(struct drm_device *dev) |
96 | { | |
97 | drm_i915_private_t *dev_priv = dev->dev_private; | |
98 | u32 addr; | |
99 | ||
100 | addr = dev_priv->status_page_dmah->busaddr; | |
101 | if (INTEL_INFO(dev)->gen >= 4) | |
102 | addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0; | |
103 | I915_WRITE(HWS_PGA, addr); | |
104 | } | |
105 | ||
398c9cb2 KP |
106 | /** |
107 | * Sets up the hardware status page for devices that need a physical address | |
108 | * in the register. | |
109 | */ | |
3043c60c | 110 | static int i915_init_phys_hws(struct drm_device *dev) |
398c9cb2 KP |
111 | { |
112 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1ec14ad3 | 113 | |
398c9cb2 KP |
114 | /* Program Hardware Status Page */ |
115 | dev_priv->status_page_dmah = | |
e6be8d9d | 116 | drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE); |
398c9cb2 KP |
117 | |
118 | if (!dev_priv->status_page_dmah) { | |
119 | DRM_ERROR("Can not allocate hardware status page\n"); | |
120 | return -ENOMEM; | |
121 | } | |
398c9cb2 | 122 | |
f3234706 KP |
123 | memset_io((void __force __iomem *)dev_priv->status_page_dmah->vaddr, |
124 | 0, PAGE_SIZE); | |
398c9cb2 | 125 | |
4cbf74cc | 126 | i915_write_hws_pga(dev); |
9b974cc1 | 127 | |
8a4c47f3 | 128 | DRM_DEBUG_DRIVER("Enabled hardware status page\n"); |
398c9cb2 KP |
129 | return 0; |
130 | } | |
131 | ||
132 | /** | |
133 | * Frees the hardware status page, whether it's a physical address or a virtual | |
134 | * address set up by the X Server. | |
135 | */ | |
3043c60c | 136 | static void i915_free_hws(struct drm_device *dev) |
398c9cb2 KP |
137 | { |
138 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1ec14ad3 CW |
139 | struct intel_ring_buffer *ring = LP_RING(dev_priv); |
140 | ||
398c9cb2 KP |
141 | if (dev_priv->status_page_dmah) { |
142 | drm_pci_free(dev, dev_priv->status_page_dmah); | |
143 | dev_priv->status_page_dmah = NULL; | |
144 | } | |
145 | ||
1ec14ad3 CW |
146 | if (ring->status_page.gfx_addr) { |
147 | ring->status_page.gfx_addr = 0; | |
316d3884 | 148 | iounmap(dev_priv->dri1.gfx_hws_cpu_addr); |
398c9cb2 KP |
149 | } |
150 | ||
151 | /* Need to rewrite hardware status page */ | |
152 | I915_WRITE(HWS_PGA, 0x1ffff000); | |
153 | } | |
154 | ||
84b1fd10 | 155 | void i915_kernel_lost_context(struct drm_device * dev) |
1da177e4 LT |
156 | { |
157 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7c1c2871 | 158 | struct drm_i915_master_private *master_priv; |
1ec14ad3 | 159 | struct intel_ring_buffer *ring = LP_RING(dev_priv); |
1da177e4 | 160 | |
79e53945 JB |
161 | /* |
162 | * We should never lose context on the ring with modesetting | |
163 | * as we don't expose it to userspace | |
164 | */ | |
165 | if (drm_core_check_feature(dev, DRIVER_MODESET)) | |
166 | return; | |
167 | ||
8168bd48 CW |
168 | ring->head = I915_READ_HEAD(ring) & HEAD_ADDR; |
169 | ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR; | |
1da177e4 LT |
170 | ring->space = ring->head - (ring->tail + 8); |
171 | if (ring->space < 0) | |
8187a2b7 | 172 | ring->space += ring->size; |
1da177e4 | 173 | |
7c1c2871 DA |
174 | if (!dev->primary->master) |
175 | return; | |
176 | ||
177 | master_priv = dev->primary->master->driver_priv; | |
178 | if (ring->head == ring->tail && master_priv->sarea_priv) | |
179 | master_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY; | |
1da177e4 LT |
180 | } |
181 | ||
84b1fd10 | 182 | static int i915_dma_cleanup(struct drm_device * dev) |
1da177e4 | 183 | { |
ba8bbcf6 | 184 | drm_i915_private_t *dev_priv = dev->dev_private; |
1ec14ad3 CW |
185 | int i; |
186 | ||
1da177e4 LT |
187 | /* Make sure interrupts are disabled here because the uninstall ioctl |
188 | * may not have been called from userspace and after dev_private | |
189 | * is freed, it's too late. | |
190 | */ | |
ed4cb414 | 191 | if (dev->irq_enabled) |
b5e89ed5 | 192 | drm_irq_uninstall(dev); |
1da177e4 | 193 | |
ee0c6bfb | 194 | mutex_lock(&dev->struct_mutex); |
1ec14ad3 CW |
195 | for (i = 0; i < I915_NUM_RINGS; i++) |
196 | intel_cleanup_ring_buffer(&dev_priv->ring[i]); | |
ee0c6bfb | 197 | mutex_unlock(&dev->struct_mutex); |
dc7a9319 | 198 | |
398c9cb2 KP |
199 | /* Clear the HWS virtual address at teardown */ |
200 | if (I915_NEED_GFX_HWS(dev)) | |
201 | i915_free_hws(dev); | |
1da177e4 LT |
202 | |
203 | return 0; | |
204 | } | |
205 | ||
ba8bbcf6 | 206 | static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init) |
1da177e4 | 207 | { |
ba8bbcf6 | 208 | drm_i915_private_t *dev_priv = dev->dev_private; |
7c1c2871 | 209 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
e8616b6c | 210 | int ret; |
1da177e4 | 211 | |
3a03ac1a DA |
212 | master_priv->sarea = drm_getsarea(dev); |
213 | if (master_priv->sarea) { | |
214 | master_priv->sarea_priv = (drm_i915_sarea_t *) | |
215 | ((u8 *)master_priv->sarea->handle + init->sarea_priv_offset); | |
216 | } else { | |
8a4c47f3 | 217 | DRM_DEBUG_DRIVER("sarea not found assuming DRI2 userspace\n"); |
3a03ac1a DA |
218 | } |
219 | ||
673a394b | 220 | if (init->ring_size != 0) { |
e8616b6c | 221 | if (LP_RING(dev_priv)->obj != NULL) { |
673a394b EA |
222 | i915_dma_cleanup(dev); |
223 | DRM_ERROR("Client tried to initialize ringbuffer in " | |
224 | "GEM mode\n"); | |
225 | return -EINVAL; | |
226 | } | |
1da177e4 | 227 | |
e8616b6c CW |
228 | ret = intel_render_ring_init_dri(dev, |
229 | init->ring_start, | |
230 | init->ring_size); | |
231 | if (ret) { | |
673a394b | 232 | i915_dma_cleanup(dev); |
e8616b6c | 233 | return ret; |
673a394b | 234 | } |
1da177e4 LT |
235 | } |
236 | ||
5d985ac8 DV |
237 | dev_priv->dri1.cpp = init->cpp; |
238 | dev_priv->dri1.back_offset = init->back_offset; | |
239 | dev_priv->dri1.front_offset = init->front_offset; | |
240 | dev_priv->dri1.current_page = 0; | |
7c1c2871 DA |
241 | if (master_priv->sarea_priv) |
242 | master_priv->sarea_priv->pf_current_page = 0; | |
1da177e4 | 243 | |
1da177e4 LT |
244 | /* Allow hardware batchbuffers unless told otherwise. |
245 | */ | |
8781342d | 246 | dev_priv->dri1.allow_batchbuffer = 1; |
1da177e4 | 247 | |
1da177e4 LT |
248 | return 0; |
249 | } | |
250 | ||
84b1fd10 | 251 | static int i915_dma_resume(struct drm_device * dev) |
1da177e4 LT |
252 | { |
253 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
1ec14ad3 | 254 | struct intel_ring_buffer *ring = LP_RING(dev_priv); |
1da177e4 | 255 | |
8a4c47f3 | 256 | DRM_DEBUG_DRIVER("%s\n", __func__); |
1da177e4 | 257 | |
4225d0f2 | 258 | if (ring->virtual_start == NULL) { |
1da177e4 LT |
259 | DRM_ERROR("can not ioremap virtual address for" |
260 | " ring buffer\n"); | |
20caafa6 | 261 | return -ENOMEM; |
1da177e4 LT |
262 | } |
263 | ||
264 | /* Program Hardware Status Page */ | |
8187a2b7 | 265 | if (!ring->status_page.page_addr) { |
1da177e4 | 266 | DRM_ERROR("Can not find hardware status page\n"); |
20caafa6 | 267 | return -EINVAL; |
1da177e4 | 268 | } |
8a4c47f3 | 269 | DRM_DEBUG_DRIVER("hw status page @ %p\n", |
8187a2b7 ZN |
270 | ring->status_page.page_addr); |
271 | if (ring->status_page.gfx_addr != 0) | |
78501eac | 272 | intel_ring_setup_status_page(ring); |
dc7a9319 | 273 | else |
4cbf74cc | 274 | i915_write_hws_pga(dev); |
8187a2b7 | 275 | |
8a4c47f3 | 276 | DRM_DEBUG_DRIVER("Enabled hardware status page\n"); |
1da177e4 LT |
277 | |
278 | return 0; | |
279 | } | |
280 | ||
c153f45f EA |
281 | static int i915_dma_init(struct drm_device *dev, void *data, |
282 | struct drm_file *file_priv) | |
1da177e4 | 283 | { |
c153f45f | 284 | drm_i915_init_t *init = data; |
1da177e4 LT |
285 | int retcode = 0; |
286 | ||
cd9d4e9f DV |
287 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
288 | return -ENODEV; | |
289 | ||
c153f45f | 290 | switch (init->func) { |
1da177e4 | 291 | case I915_INIT_DMA: |
ba8bbcf6 | 292 | retcode = i915_initialize(dev, init); |
1da177e4 LT |
293 | break; |
294 | case I915_CLEANUP_DMA: | |
295 | retcode = i915_dma_cleanup(dev); | |
296 | break; | |
297 | case I915_RESUME_DMA: | |
0d6aa60b | 298 | retcode = i915_dma_resume(dev); |
1da177e4 LT |
299 | break; |
300 | default: | |
20caafa6 | 301 | retcode = -EINVAL; |
1da177e4 LT |
302 | break; |
303 | } | |
304 | ||
305 | return retcode; | |
306 | } | |
307 | ||
308 | /* Implement basically the same security restrictions as hardware does | |
309 | * for MI_BATCH_NON_SECURE. These can be made stricter at any time. | |
310 | * | |
311 | * Most of the calculations below involve calculating the size of a | |
312 | * particular instruction. It's important to get the size right as | |
313 | * that tells us where the next instruction to check is. Any illegal | |
314 | * instruction detected will be given a size of zero, which is a | |
315 | * signal to abort the rest of the buffer. | |
316 | */ | |
e1f99ce6 | 317 | static int validate_cmd(int cmd) |
1da177e4 LT |
318 | { |
319 | switch (((cmd >> 29) & 0x7)) { | |
320 | case 0x0: | |
321 | switch ((cmd >> 23) & 0x3f) { | |
322 | case 0x0: | |
323 | return 1; /* MI_NOOP */ | |
324 | case 0x4: | |
325 | return 1; /* MI_FLUSH */ | |
326 | default: | |
327 | return 0; /* disallow everything else */ | |
328 | } | |
329 | break; | |
330 | case 0x1: | |
331 | return 0; /* reserved */ | |
332 | case 0x2: | |
333 | return (cmd & 0xff) + 2; /* 2d commands */ | |
334 | case 0x3: | |
335 | if (((cmd >> 24) & 0x1f) <= 0x18) | |
336 | return 1; | |
337 | ||
338 | switch ((cmd >> 24) & 0x1f) { | |
339 | case 0x1c: | |
340 | return 1; | |
341 | case 0x1d: | |
b5e89ed5 | 342 | switch ((cmd >> 16) & 0xff) { |
1da177e4 LT |
343 | case 0x3: |
344 | return (cmd & 0x1f) + 2; | |
345 | case 0x4: | |
346 | return (cmd & 0xf) + 2; | |
347 | default: | |
348 | return (cmd & 0xffff) + 2; | |
349 | } | |
350 | case 0x1e: | |
351 | if (cmd & (1 << 23)) | |
352 | return (cmd & 0xffff) + 1; | |
353 | else | |
354 | return 1; | |
355 | case 0x1f: | |
356 | if ((cmd & (1 << 23)) == 0) /* inline vertices */ | |
357 | return (cmd & 0x1ffff) + 2; | |
358 | else if (cmd & (1 << 17)) /* indirect random */ | |
359 | if ((cmd & 0xffff) == 0) | |
360 | return 0; /* unknown length, too hard */ | |
361 | else | |
362 | return (((cmd & 0xffff) + 1) / 2) + 1; | |
363 | else | |
364 | return 2; /* indirect sequential */ | |
365 | default: | |
366 | return 0; | |
367 | } | |
368 | default: | |
369 | return 0; | |
370 | } | |
371 | ||
372 | return 0; | |
373 | } | |
374 | ||
201361a5 | 375 | static int i915_emit_cmds(struct drm_device * dev, int *buffer, int dwords) |
1da177e4 LT |
376 | { |
377 | drm_i915_private_t *dev_priv = dev->dev_private; | |
e1f99ce6 | 378 | int i, ret; |
1da177e4 | 379 | |
1ec14ad3 | 380 | if ((dwords+1) * sizeof(int) >= LP_RING(dev_priv)->size - 8) |
20caafa6 | 381 | return -EINVAL; |
de227f5f | 382 | |
1da177e4 | 383 | for (i = 0; i < dwords;) { |
e1f99ce6 CW |
384 | int sz = validate_cmd(buffer[i]); |
385 | if (sz == 0 || i + sz > dwords) | |
20caafa6 | 386 | return -EINVAL; |
e1f99ce6 | 387 | i += sz; |
1da177e4 LT |
388 | } |
389 | ||
e1f99ce6 CW |
390 | ret = BEGIN_LP_RING((dwords+1)&~1); |
391 | if (ret) | |
392 | return ret; | |
393 | ||
394 | for (i = 0; i < dwords; i++) | |
395 | OUT_RING(buffer[i]); | |
de227f5f DA |
396 | if (dwords & 1) |
397 | OUT_RING(0); | |
398 | ||
399 | ADVANCE_LP_RING(); | |
400 | ||
1da177e4 LT |
401 | return 0; |
402 | } | |
403 | ||
673a394b EA |
404 | int |
405 | i915_emit_box(struct drm_device *dev, | |
c4e7a414 CW |
406 | struct drm_clip_rect *box, |
407 | int DR1, int DR4) | |
1da177e4 | 408 | { |
e1f99ce6 | 409 | struct drm_i915_private *dev_priv = dev->dev_private; |
e1f99ce6 | 410 | int ret; |
1da177e4 | 411 | |
c4e7a414 CW |
412 | if (box->y2 <= box->y1 || box->x2 <= box->x1 || |
413 | box->y2 <= 0 || box->x2 <= 0) { | |
1da177e4 | 414 | DRM_ERROR("Bad box %d,%d..%d,%d\n", |
c4e7a414 | 415 | box->x1, box->y1, box->x2, box->y2); |
20caafa6 | 416 | return -EINVAL; |
1da177e4 LT |
417 | } |
418 | ||
a6c45cf0 | 419 | if (INTEL_INFO(dev)->gen >= 4) { |
e1f99ce6 CW |
420 | ret = BEGIN_LP_RING(4); |
421 | if (ret) | |
422 | return ret; | |
423 | ||
c29b669c | 424 | OUT_RING(GFX_OP_DRAWRECT_INFO_I965); |
c4e7a414 CW |
425 | OUT_RING((box->x1 & 0xffff) | (box->y1 << 16)); |
426 | OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16)); | |
c29b669c | 427 | OUT_RING(DR4); |
c29b669c | 428 | } else { |
e1f99ce6 CW |
429 | ret = BEGIN_LP_RING(6); |
430 | if (ret) | |
431 | return ret; | |
432 | ||
c29b669c AH |
433 | OUT_RING(GFX_OP_DRAWRECT_INFO); |
434 | OUT_RING(DR1); | |
c4e7a414 CW |
435 | OUT_RING((box->x1 & 0xffff) | (box->y1 << 16)); |
436 | OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16)); | |
c29b669c AH |
437 | OUT_RING(DR4); |
438 | OUT_RING(0); | |
c29b669c | 439 | } |
e1f99ce6 | 440 | ADVANCE_LP_RING(); |
1da177e4 LT |
441 | |
442 | return 0; | |
443 | } | |
444 | ||
c29b669c AH |
445 | /* XXX: Emitting the counter should really be moved to part of the IRQ |
446 | * emit. For now, do it in both places: | |
447 | */ | |
448 | ||
84b1fd10 | 449 | static void i915_emit_breadcrumb(struct drm_device *dev) |
de227f5f DA |
450 | { |
451 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7c1c2871 | 452 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
de227f5f | 453 | |
c99b058f | 454 | dev_priv->counter++; |
af6061af | 455 | if (dev_priv->counter > 0x7FFFFFFFUL) |
c99b058f | 456 | dev_priv->counter = 0; |
7c1c2871 DA |
457 | if (master_priv->sarea_priv) |
458 | master_priv->sarea_priv->last_enqueue = dev_priv->counter; | |
de227f5f | 459 | |
e1f99ce6 CW |
460 | if (BEGIN_LP_RING(4) == 0) { |
461 | OUT_RING(MI_STORE_DWORD_INDEX); | |
462 | OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
463 | OUT_RING(dev_priv->counter); | |
464 | OUT_RING(0); | |
465 | ADVANCE_LP_RING(); | |
466 | } | |
de227f5f DA |
467 | } |
468 | ||
84b1fd10 | 469 | static int i915_dispatch_cmdbuffer(struct drm_device * dev, |
201361a5 EA |
470 | drm_i915_cmdbuffer_t *cmd, |
471 | struct drm_clip_rect *cliprects, | |
472 | void *cmdbuf) | |
1da177e4 LT |
473 | { |
474 | int nbox = cmd->num_cliprects; | |
475 | int i = 0, count, ret; | |
476 | ||
477 | if (cmd->sz & 0x3) { | |
478 | DRM_ERROR("alignment"); | |
20caafa6 | 479 | return -EINVAL; |
1da177e4 LT |
480 | } |
481 | ||
482 | i915_kernel_lost_context(dev); | |
483 | ||
484 | count = nbox ? nbox : 1; | |
485 | ||
486 | for (i = 0; i < count; i++) { | |
487 | if (i < nbox) { | |
c4e7a414 | 488 | ret = i915_emit_box(dev, &cliprects[i], |
1da177e4 LT |
489 | cmd->DR1, cmd->DR4); |
490 | if (ret) | |
491 | return ret; | |
492 | } | |
493 | ||
201361a5 | 494 | ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4); |
1da177e4 LT |
495 | if (ret) |
496 | return ret; | |
497 | } | |
498 | ||
de227f5f | 499 | i915_emit_breadcrumb(dev); |
1da177e4 LT |
500 | return 0; |
501 | } | |
502 | ||
84b1fd10 | 503 | static int i915_dispatch_batchbuffer(struct drm_device * dev, |
201361a5 EA |
504 | drm_i915_batchbuffer_t * batch, |
505 | struct drm_clip_rect *cliprects) | |
1da177e4 | 506 | { |
e1f99ce6 | 507 | struct drm_i915_private *dev_priv = dev->dev_private; |
1da177e4 | 508 | int nbox = batch->num_cliprects; |
e1f99ce6 | 509 | int i, count, ret; |
1da177e4 LT |
510 | |
511 | if ((batch->start | batch->used) & 0x7) { | |
512 | DRM_ERROR("alignment"); | |
20caafa6 | 513 | return -EINVAL; |
1da177e4 LT |
514 | } |
515 | ||
516 | i915_kernel_lost_context(dev); | |
517 | ||
518 | count = nbox ? nbox : 1; | |
1da177e4 LT |
519 | for (i = 0; i < count; i++) { |
520 | if (i < nbox) { | |
c4e7a414 | 521 | ret = i915_emit_box(dev, &cliprects[i], |
e1f99ce6 | 522 | batch->DR1, batch->DR4); |
1da177e4 LT |
523 | if (ret) |
524 | return ret; | |
525 | } | |
526 | ||
0790d5e1 | 527 | if (!IS_I830(dev) && !IS_845G(dev)) { |
e1f99ce6 CW |
528 | ret = BEGIN_LP_RING(2); |
529 | if (ret) | |
530 | return ret; | |
531 | ||
a6c45cf0 | 532 | if (INTEL_INFO(dev)->gen >= 4) { |
21f16289 DA |
533 | OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965); |
534 | OUT_RING(batch->start); | |
535 | } else { | |
536 | OUT_RING(MI_BATCH_BUFFER_START | (2 << 6)); | |
537 | OUT_RING(batch->start | MI_BATCH_NON_SECURE); | |
538 | } | |
1da177e4 | 539 | } else { |
e1f99ce6 CW |
540 | ret = BEGIN_LP_RING(4); |
541 | if (ret) | |
542 | return ret; | |
543 | ||
1da177e4 LT |
544 | OUT_RING(MI_BATCH_BUFFER); |
545 | OUT_RING(batch->start | MI_BATCH_NON_SECURE); | |
546 | OUT_RING(batch->start + batch->used - 4); | |
547 | OUT_RING(0); | |
1da177e4 | 548 | } |
e1f99ce6 | 549 | ADVANCE_LP_RING(); |
1da177e4 LT |
550 | } |
551 | ||
1cafd347 | 552 | |
f00a3ddf | 553 | if (IS_G4X(dev) || IS_GEN5(dev)) { |
e1f99ce6 CW |
554 | if (BEGIN_LP_RING(2) == 0) { |
555 | OUT_RING(MI_FLUSH | MI_NO_WRITE_FLUSH | MI_INVALIDATE_ISP); | |
556 | OUT_RING(MI_NOOP); | |
557 | ADVANCE_LP_RING(); | |
558 | } | |
1cafd347 | 559 | } |
1da177e4 | 560 | |
e1f99ce6 | 561 | i915_emit_breadcrumb(dev); |
1da177e4 LT |
562 | return 0; |
563 | } | |
564 | ||
af6061af | 565 | static int i915_dispatch_flip(struct drm_device * dev) |
1da177e4 LT |
566 | { |
567 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7c1c2871 DA |
568 | struct drm_i915_master_private *master_priv = |
569 | dev->primary->master->driver_priv; | |
e1f99ce6 | 570 | int ret; |
1da177e4 | 571 | |
7c1c2871 | 572 | if (!master_priv->sarea_priv) |
c99b058f KH |
573 | return -EINVAL; |
574 | ||
8a4c47f3 | 575 | DRM_DEBUG_DRIVER("%s: page=%d pfCurrentPage=%d\n", |
be25ed9c | 576 | __func__, |
5d985ac8 | 577 | dev_priv->dri1.current_page, |
be25ed9c | 578 | master_priv->sarea_priv->pf_current_page); |
1da177e4 | 579 | |
af6061af DA |
580 | i915_kernel_lost_context(dev); |
581 | ||
e1f99ce6 CW |
582 | ret = BEGIN_LP_RING(10); |
583 | if (ret) | |
584 | return ret; | |
585 | ||
585fb111 | 586 | OUT_RING(MI_FLUSH | MI_READ_FLUSH); |
af6061af | 587 | OUT_RING(0); |
1da177e4 | 588 | |
af6061af DA |
589 | OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP); |
590 | OUT_RING(0); | |
5d985ac8 DV |
591 | if (dev_priv->dri1.current_page == 0) { |
592 | OUT_RING(dev_priv->dri1.back_offset); | |
593 | dev_priv->dri1.current_page = 1; | |
1da177e4 | 594 | } else { |
5d985ac8 DV |
595 | OUT_RING(dev_priv->dri1.front_offset); |
596 | dev_priv->dri1.current_page = 0; | |
1da177e4 | 597 | } |
af6061af | 598 | OUT_RING(0); |
1da177e4 | 599 | |
af6061af DA |
600 | OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP); |
601 | OUT_RING(0); | |
e1f99ce6 | 602 | |
af6061af | 603 | ADVANCE_LP_RING(); |
1da177e4 | 604 | |
7c1c2871 | 605 | master_priv->sarea_priv->last_enqueue = dev_priv->counter++; |
1da177e4 | 606 | |
e1f99ce6 CW |
607 | if (BEGIN_LP_RING(4) == 0) { |
608 | OUT_RING(MI_STORE_DWORD_INDEX); | |
609 | OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
610 | OUT_RING(dev_priv->counter); | |
611 | OUT_RING(0); | |
612 | ADVANCE_LP_RING(); | |
613 | } | |
1da177e4 | 614 | |
5d985ac8 | 615 | master_priv->sarea_priv->pf_current_page = dev_priv->dri1.current_page; |
af6061af | 616 | return 0; |
1da177e4 LT |
617 | } |
618 | ||
1ec14ad3 | 619 | static int i915_quiescent(struct drm_device *dev) |
1da177e4 | 620 | { |
1ec14ad3 | 621 | struct intel_ring_buffer *ring = LP_RING(dev->dev_private); |
1da177e4 LT |
622 | |
623 | i915_kernel_lost_context(dev); | |
96f298aa | 624 | return intel_wait_ring_idle(ring); |
1da177e4 LT |
625 | } |
626 | ||
c153f45f EA |
627 | static int i915_flush_ioctl(struct drm_device *dev, void *data, |
628 | struct drm_file *file_priv) | |
1da177e4 | 629 | { |
546b0974 EA |
630 | int ret; |
631 | ||
cd9d4e9f DV |
632 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
633 | return -ENODEV; | |
634 | ||
546b0974 | 635 | RING_LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 | 636 | |
546b0974 EA |
637 | mutex_lock(&dev->struct_mutex); |
638 | ret = i915_quiescent(dev); | |
639 | mutex_unlock(&dev->struct_mutex); | |
640 | ||
641 | return ret; | |
1da177e4 LT |
642 | } |
643 | ||
c153f45f EA |
644 | static int i915_batchbuffer(struct drm_device *dev, void *data, |
645 | struct drm_file *file_priv) | |
1da177e4 | 646 | { |
1da177e4 | 647 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
7c1c2871 | 648 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
1da177e4 | 649 | drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *) |
7c1c2871 | 650 | master_priv->sarea_priv; |
c153f45f | 651 | drm_i915_batchbuffer_t *batch = data; |
1da177e4 | 652 | int ret; |
201361a5 | 653 | struct drm_clip_rect *cliprects = NULL; |
1da177e4 | 654 | |
cd9d4e9f DV |
655 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
656 | return -ENODEV; | |
657 | ||
8781342d | 658 | if (!dev_priv->dri1.allow_batchbuffer) { |
1da177e4 | 659 | DRM_ERROR("Batchbuffer ioctl disabled\n"); |
20caafa6 | 660 | return -EINVAL; |
1da177e4 LT |
661 | } |
662 | ||
8a4c47f3 | 663 | DRM_DEBUG_DRIVER("i915 batchbuffer, start %x used %d cliprects %d\n", |
be25ed9c | 664 | batch->start, batch->used, batch->num_cliprects); |
1da177e4 | 665 | |
546b0974 | 666 | RING_LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 | 667 | |
201361a5 EA |
668 | if (batch->num_cliprects < 0) |
669 | return -EINVAL; | |
670 | ||
671 | if (batch->num_cliprects) { | |
9a298b2a EA |
672 | cliprects = kcalloc(batch->num_cliprects, |
673 | sizeof(struct drm_clip_rect), | |
674 | GFP_KERNEL); | |
201361a5 EA |
675 | if (cliprects == NULL) |
676 | return -ENOMEM; | |
677 | ||
678 | ret = copy_from_user(cliprects, batch->cliprects, | |
679 | batch->num_cliprects * | |
680 | sizeof(struct drm_clip_rect)); | |
9927a403 DC |
681 | if (ret != 0) { |
682 | ret = -EFAULT; | |
201361a5 | 683 | goto fail_free; |
9927a403 | 684 | } |
201361a5 | 685 | } |
1da177e4 | 686 | |
546b0974 | 687 | mutex_lock(&dev->struct_mutex); |
201361a5 | 688 | ret = i915_dispatch_batchbuffer(dev, batch, cliprects); |
546b0974 | 689 | mutex_unlock(&dev->struct_mutex); |
1da177e4 | 690 | |
c99b058f | 691 | if (sarea_priv) |
0baf823a | 692 | sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv); |
201361a5 EA |
693 | |
694 | fail_free: | |
9a298b2a | 695 | kfree(cliprects); |
201361a5 | 696 | |
1da177e4 LT |
697 | return ret; |
698 | } | |
699 | ||
c153f45f EA |
700 | static int i915_cmdbuffer(struct drm_device *dev, void *data, |
701 | struct drm_file *file_priv) | |
1da177e4 | 702 | { |
1da177e4 | 703 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
7c1c2871 | 704 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
1da177e4 | 705 | drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *) |
7c1c2871 | 706 | master_priv->sarea_priv; |
c153f45f | 707 | drm_i915_cmdbuffer_t *cmdbuf = data; |
201361a5 EA |
708 | struct drm_clip_rect *cliprects = NULL; |
709 | void *batch_data; | |
1da177e4 LT |
710 | int ret; |
711 | ||
8a4c47f3 | 712 | DRM_DEBUG_DRIVER("i915 cmdbuffer, buf %p sz %d cliprects %d\n", |
be25ed9c | 713 | cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects); |
1da177e4 | 714 | |
cd9d4e9f DV |
715 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
716 | return -ENODEV; | |
717 | ||
546b0974 | 718 | RING_LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 | 719 | |
201361a5 EA |
720 | if (cmdbuf->num_cliprects < 0) |
721 | return -EINVAL; | |
722 | ||
9a298b2a | 723 | batch_data = kmalloc(cmdbuf->sz, GFP_KERNEL); |
201361a5 EA |
724 | if (batch_data == NULL) |
725 | return -ENOMEM; | |
726 | ||
727 | ret = copy_from_user(batch_data, cmdbuf->buf, cmdbuf->sz); | |
9927a403 DC |
728 | if (ret != 0) { |
729 | ret = -EFAULT; | |
201361a5 | 730 | goto fail_batch_free; |
9927a403 | 731 | } |
201361a5 EA |
732 | |
733 | if (cmdbuf->num_cliprects) { | |
9a298b2a EA |
734 | cliprects = kcalloc(cmdbuf->num_cliprects, |
735 | sizeof(struct drm_clip_rect), GFP_KERNEL); | |
a40e8d31 OA |
736 | if (cliprects == NULL) { |
737 | ret = -ENOMEM; | |
201361a5 | 738 | goto fail_batch_free; |
a40e8d31 | 739 | } |
201361a5 EA |
740 | |
741 | ret = copy_from_user(cliprects, cmdbuf->cliprects, | |
742 | cmdbuf->num_cliprects * | |
743 | sizeof(struct drm_clip_rect)); | |
9927a403 DC |
744 | if (ret != 0) { |
745 | ret = -EFAULT; | |
201361a5 | 746 | goto fail_clip_free; |
9927a403 | 747 | } |
1da177e4 LT |
748 | } |
749 | ||
546b0974 | 750 | mutex_lock(&dev->struct_mutex); |
201361a5 | 751 | ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data); |
546b0974 | 752 | mutex_unlock(&dev->struct_mutex); |
1da177e4 LT |
753 | if (ret) { |
754 | DRM_ERROR("i915_dispatch_cmdbuffer failed\n"); | |
355d7f37 | 755 | goto fail_clip_free; |
1da177e4 LT |
756 | } |
757 | ||
c99b058f | 758 | if (sarea_priv) |
0baf823a | 759 | sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv); |
201361a5 | 760 | |
201361a5 | 761 | fail_clip_free: |
9a298b2a | 762 | kfree(cliprects); |
355d7f37 | 763 | fail_batch_free: |
9a298b2a | 764 | kfree(batch_data); |
201361a5 EA |
765 | |
766 | return ret; | |
1da177e4 LT |
767 | } |
768 | ||
9488867a DV |
769 | static int i915_emit_irq(struct drm_device * dev) |
770 | { | |
771 | drm_i915_private_t *dev_priv = dev->dev_private; | |
772 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; | |
773 | ||
774 | i915_kernel_lost_context(dev); | |
775 | ||
776 | DRM_DEBUG_DRIVER("\n"); | |
777 | ||
778 | dev_priv->counter++; | |
779 | if (dev_priv->counter > 0x7FFFFFFFUL) | |
780 | dev_priv->counter = 1; | |
781 | if (master_priv->sarea_priv) | |
782 | master_priv->sarea_priv->last_enqueue = dev_priv->counter; | |
783 | ||
784 | if (BEGIN_LP_RING(4) == 0) { | |
785 | OUT_RING(MI_STORE_DWORD_INDEX); | |
786 | OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
787 | OUT_RING(dev_priv->counter); | |
788 | OUT_RING(MI_USER_INTERRUPT); | |
789 | ADVANCE_LP_RING(); | |
790 | } | |
791 | ||
792 | return dev_priv->counter; | |
793 | } | |
794 | ||
795 | static int i915_wait_irq(struct drm_device * dev, int irq_nr) | |
796 | { | |
797 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
798 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; | |
799 | int ret = 0; | |
800 | struct intel_ring_buffer *ring = LP_RING(dev_priv); | |
801 | ||
802 | DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr, | |
803 | READ_BREADCRUMB(dev_priv)); | |
804 | ||
805 | if (READ_BREADCRUMB(dev_priv) >= irq_nr) { | |
806 | if (master_priv->sarea_priv) | |
807 | master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv); | |
808 | return 0; | |
809 | } | |
810 | ||
811 | if (master_priv->sarea_priv) | |
812 | master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT; | |
813 | ||
814 | if (ring->irq_get(ring)) { | |
815 | DRM_WAIT_ON(ret, ring->irq_queue, 3 * DRM_HZ, | |
816 | READ_BREADCRUMB(dev_priv) >= irq_nr); | |
817 | ring->irq_put(ring); | |
818 | } else if (wait_for(READ_BREADCRUMB(dev_priv) >= irq_nr, 3000)) | |
819 | ret = -EBUSY; | |
820 | ||
821 | if (ret == -EBUSY) { | |
822 | DRM_ERROR("EBUSY -- rec: %d emitted: %d\n", | |
823 | READ_BREADCRUMB(dev_priv), (int)dev_priv->counter); | |
824 | } | |
825 | ||
826 | return ret; | |
827 | } | |
828 | ||
829 | /* Needs the lock as it touches the ring. | |
830 | */ | |
831 | static int i915_irq_emit(struct drm_device *dev, void *data, | |
832 | struct drm_file *file_priv) | |
833 | { | |
834 | drm_i915_private_t *dev_priv = dev->dev_private; | |
835 | drm_i915_irq_emit_t *emit = data; | |
836 | int result; | |
837 | ||
838 | if (drm_core_check_feature(dev, DRIVER_MODESET)) | |
839 | return -ENODEV; | |
840 | ||
841 | if (!dev_priv || !LP_RING(dev_priv)->virtual_start) { | |
842 | DRM_ERROR("called with no initialization\n"); | |
843 | return -EINVAL; | |
844 | } | |
845 | ||
846 | RING_LOCK_TEST_WITH_RETURN(dev, file_priv); | |
847 | ||
848 | mutex_lock(&dev->struct_mutex); | |
849 | result = i915_emit_irq(dev); | |
850 | mutex_unlock(&dev->struct_mutex); | |
851 | ||
852 | if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) { | |
853 | DRM_ERROR("copy_to_user\n"); | |
854 | return -EFAULT; | |
855 | } | |
856 | ||
857 | return 0; | |
858 | } | |
859 | ||
860 | /* Doesn't need the hardware lock. | |
861 | */ | |
862 | static int i915_irq_wait(struct drm_device *dev, void *data, | |
863 | struct drm_file *file_priv) | |
864 | { | |
865 | drm_i915_private_t *dev_priv = dev->dev_private; | |
866 | drm_i915_irq_wait_t *irqwait = data; | |
867 | ||
868 | if (drm_core_check_feature(dev, DRIVER_MODESET)) | |
869 | return -ENODEV; | |
870 | ||
871 | if (!dev_priv) { | |
872 | DRM_ERROR("called with no initialization\n"); | |
873 | return -EINVAL; | |
874 | } | |
875 | ||
876 | return i915_wait_irq(dev, irqwait->irq_seq); | |
877 | } | |
878 | ||
d1c1edbc DV |
879 | static int i915_vblank_pipe_get(struct drm_device *dev, void *data, |
880 | struct drm_file *file_priv) | |
881 | { | |
882 | drm_i915_private_t *dev_priv = dev->dev_private; | |
883 | drm_i915_vblank_pipe_t *pipe = data; | |
884 | ||
885 | if (drm_core_check_feature(dev, DRIVER_MODESET)) | |
886 | return -ENODEV; | |
887 | ||
888 | if (!dev_priv) { | |
889 | DRM_ERROR("called with no initialization\n"); | |
890 | return -EINVAL; | |
891 | } | |
892 | ||
893 | pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B; | |
894 | ||
895 | return 0; | |
896 | } | |
897 | ||
898 | /** | |
899 | * Schedule buffer swap at given vertical blank. | |
900 | */ | |
901 | static int i915_vblank_swap(struct drm_device *dev, void *data, | |
902 | struct drm_file *file_priv) | |
903 | { | |
904 | /* The delayed swap mechanism was fundamentally racy, and has been | |
905 | * removed. The model was that the client requested a delayed flip/swap | |
906 | * from the kernel, then waited for vblank before continuing to perform | |
907 | * rendering. The problem was that the kernel might wake the client | |
908 | * up before it dispatched the vblank swap (since the lock has to be | |
909 | * held while touching the ringbuffer), in which case the client would | |
910 | * clear and start the next frame before the swap occurred, and | |
911 | * flicker would occur in addition to likely missing the vblank. | |
912 | * | |
913 | * In the absence of this ioctl, userland falls back to a correct path | |
914 | * of waiting for a vblank, then dispatching the swap on its own. | |
915 | * Context switching to userland and back is plenty fast enough for | |
916 | * meeting the requirements of vblank swapping. | |
917 | */ | |
918 | return -EINVAL; | |
919 | } | |
920 | ||
c153f45f EA |
921 | static int i915_flip_bufs(struct drm_device *dev, void *data, |
922 | struct drm_file *file_priv) | |
1da177e4 | 923 | { |
546b0974 EA |
924 | int ret; |
925 | ||
cd9d4e9f DV |
926 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
927 | return -ENODEV; | |
928 | ||
8a4c47f3 | 929 | DRM_DEBUG_DRIVER("%s\n", __func__); |
1da177e4 | 930 | |
546b0974 | 931 | RING_LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 | 932 | |
546b0974 EA |
933 | mutex_lock(&dev->struct_mutex); |
934 | ret = i915_dispatch_flip(dev); | |
935 | mutex_unlock(&dev->struct_mutex); | |
936 | ||
937 | return ret; | |
1da177e4 LT |
938 | } |
939 | ||
c153f45f EA |
940 | static int i915_getparam(struct drm_device *dev, void *data, |
941 | struct drm_file *file_priv) | |
1da177e4 | 942 | { |
1da177e4 | 943 | drm_i915_private_t *dev_priv = dev->dev_private; |
c153f45f | 944 | drm_i915_getparam_t *param = data; |
1da177e4 LT |
945 | int value; |
946 | ||
947 | if (!dev_priv) { | |
3e684eae | 948 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 949 | return -EINVAL; |
1da177e4 LT |
950 | } |
951 | ||
c153f45f | 952 | switch (param->param) { |
1da177e4 | 953 | case I915_PARAM_IRQ_ACTIVE: |
0a3e67a4 | 954 | value = dev->pdev->irq ? 1 : 0; |
1da177e4 LT |
955 | break; |
956 | case I915_PARAM_ALLOW_BATCHBUFFER: | |
8781342d | 957 | value = dev_priv->dri1.allow_batchbuffer ? 1 : 0; |
1da177e4 | 958 | break; |
0d6aa60b DA |
959 | case I915_PARAM_LAST_DISPATCH: |
960 | value = READ_BREADCRUMB(dev_priv); | |
961 | break; | |
ed4c9c4a KH |
962 | case I915_PARAM_CHIPSET_ID: |
963 | value = dev->pci_device; | |
964 | break; | |
673a394b | 965 | case I915_PARAM_HAS_GEM: |
2e895b17 | 966 | value = 1; |
673a394b | 967 | break; |
0f973f27 JB |
968 | case I915_PARAM_NUM_FENCES_AVAIL: |
969 | value = dev_priv->num_fence_regs - dev_priv->fence_reg_start; | |
970 | break; | |
02e792fb DV |
971 | case I915_PARAM_HAS_OVERLAY: |
972 | value = dev_priv->overlay ? 1 : 0; | |
973 | break; | |
e9560f7c JB |
974 | case I915_PARAM_HAS_PAGEFLIPPING: |
975 | value = 1; | |
976 | break; | |
76446cac JB |
977 | case I915_PARAM_HAS_EXECBUF2: |
978 | /* depends on GEM */ | |
2e895b17 | 979 | value = 1; |
76446cac | 980 | break; |
e3a815fc | 981 | case I915_PARAM_HAS_BSD: |
edc912f5 | 982 | value = intel_ring_initialized(&dev_priv->ring[VCS]); |
e3a815fc | 983 | break; |
549f7365 | 984 | case I915_PARAM_HAS_BLT: |
edc912f5 | 985 | value = intel_ring_initialized(&dev_priv->ring[BCS]); |
549f7365 | 986 | break; |
a00b10c3 CW |
987 | case I915_PARAM_HAS_RELAXED_FENCING: |
988 | value = 1; | |
989 | break; | |
bbf0c6b3 DV |
990 | case I915_PARAM_HAS_COHERENT_RINGS: |
991 | value = 1; | |
992 | break; | |
72bfa19c CW |
993 | case I915_PARAM_HAS_EXEC_CONSTANTS: |
994 | value = INTEL_INFO(dev)->gen >= 4; | |
995 | break; | |
271d81b8 CW |
996 | case I915_PARAM_HAS_RELAXED_DELTA: |
997 | value = 1; | |
998 | break; | |
ae662d31 EA |
999 | case I915_PARAM_HAS_GEN7_SOL_RESET: |
1000 | value = 1; | |
1001 | break; | |
3d29b842 ED |
1002 | case I915_PARAM_HAS_LLC: |
1003 | value = HAS_LLC(dev); | |
1004 | break; | |
777ee96f DV |
1005 | case I915_PARAM_HAS_ALIASING_PPGTT: |
1006 | value = dev_priv->mm.aliasing_ppgtt ? 1 : 0; | |
1007 | break; | |
172cf15d BW |
1008 | case I915_PARAM_HAS_WAIT_TIMEOUT: |
1009 | value = 1; | |
1010 | break; | |
2fedbff9 CW |
1011 | case I915_PARAM_HAS_SEMAPHORES: |
1012 | value = i915_semaphore_is_enabled(dev); | |
1013 | break; | |
ec6f1bb9 DA |
1014 | case I915_PARAM_HAS_PRIME_VMAP_FLUSH: |
1015 | value = 1; | |
1016 | break; | |
1da177e4 | 1017 | default: |
8a4c47f3 | 1018 | DRM_DEBUG_DRIVER("Unknown parameter %d\n", |
76446cac | 1019 | param->param); |
20caafa6 | 1020 | return -EINVAL; |
1da177e4 LT |
1021 | } |
1022 | ||
c153f45f | 1023 | if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) { |
1da177e4 | 1024 | DRM_ERROR("DRM_COPY_TO_USER failed\n"); |
20caafa6 | 1025 | return -EFAULT; |
1da177e4 LT |
1026 | } |
1027 | ||
1028 | return 0; | |
1029 | } | |
1030 | ||
c153f45f EA |
1031 | static int i915_setparam(struct drm_device *dev, void *data, |
1032 | struct drm_file *file_priv) | |
1da177e4 | 1033 | { |
1da177e4 | 1034 | drm_i915_private_t *dev_priv = dev->dev_private; |
c153f45f | 1035 | drm_i915_setparam_t *param = data; |
1da177e4 LT |
1036 | |
1037 | if (!dev_priv) { | |
3e684eae | 1038 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 1039 | return -EINVAL; |
1da177e4 LT |
1040 | } |
1041 | ||
c153f45f | 1042 | switch (param->param) { |
1da177e4 | 1043 | case I915_SETPARAM_USE_MI_BATCHBUFFER_START: |
1da177e4 LT |
1044 | break; |
1045 | case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY: | |
1da177e4 LT |
1046 | break; |
1047 | case I915_SETPARAM_ALLOW_BATCHBUFFER: | |
8781342d | 1048 | dev_priv->dri1.allow_batchbuffer = param->value ? 1 : 0; |
1da177e4 | 1049 | break; |
0f973f27 JB |
1050 | case I915_SETPARAM_NUM_USED_FENCES: |
1051 | if (param->value > dev_priv->num_fence_regs || | |
1052 | param->value < 0) | |
1053 | return -EINVAL; | |
1054 | /* Userspace can use first N regs */ | |
1055 | dev_priv->fence_reg_start = param->value; | |
1056 | break; | |
1da177e4 | 1057 | default: |
8a4c47f3 | 1058 | DRM_DEBUG_DRIVER("unknown parameter %d\n", |
be25ed9c | 1059 | param->param); |
20caafa6 | 1060 | return -EINVAL; |
1da177e4 LT |
1061 | } |
1062 | ||
1063 | return 0; | |
1064 | } | |
1065 | ||
c153f45f EA |
1066 | static int i915_set_status_page(struct drm_device *dev, void *data, |
1067 | struct drm_file *file_priv) | |
dc7a9319 | 1068 | { |
dc7a9319 | 1069 | drm_i915_private_t *dev_priv = dev->dev_private; |
c153f45f | 1070 | drm_i915_hws_addr_t *hws = data; |
1ec14ad3 | 1071 | struct intel_ring_buffer *ring = LP_RING(dev_priv); |
b39d50e5 | 1072 | |
cd9d4e9f DV |
1073 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
1074 | return -ENODEV; | |
1075 | ||
b39d50e5 ZW |
1076 | if (!I915_NEED_GFX_HWS(dev)) |
1077 | return -EINVAL; | |
dc7a9319 WZ |
1078 | |
1079 | if (!dev_priv) { | |
3e684eae | 1080 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 1081 | return -EINVAL; |
dc7a9319 | 1082 | } |
dc7a9319 | 1083 | |
79e53945 JB |
1084 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
1085 | WARN(1, "tried to set status page when mode setting active\n"); | |
1086 | return 0; | |
1087 | } | |
1088 | ||
8a4c47f3 | 1089 | DRM_DEBUG_DRIVER("set status page addr 0x%08x\n", (u32)hws->addr); |
c153f45f | 1090 | |
8187a2b7 | 1091 | ring->status_page.gfx_addr = hws->addr & (0x1ffff<<12); |
dc7a9319 | 1092 | |
dd2757f8 DV |
1093 | dev_priv->dri1.gfx_hws_cpu_addr = |
1094 | ioremap_wc(dev_priv->mm.gtt_base_addr + hws->addr, 4096); | |
316d3884 | 1095 | if (dev_priv->dri1.gfx_hws_cpu_addr == NULL) { |
dc7a9319 | 1096 | i915_dma_cleanup(dev); |
e20f9c64 | 1097 | ring->status_page.gfx_addr = 0; |
dc7a9319 WZ |
1098 | DRM_ERROR("can not ioremap virtual address for" |
1099 | " G33 hw status page\n"); | |
20caafa6 | 1100 | return -ENOMEM; |
dc7a9319 | 1101 | } |
316d3884 DV |
1102 | |
1103 | memset_io(dev_priv->dri1.gfx_hws_cpu_addr, 0, PAGE_SIZE); | |
8187a2b7 | 1104 | I915_WRITE(HWS_PGA, ring->status_page.gfx_addr); |
dc7a9319 | 1105 | |
8a4c47f3 | 1106 | DRM_DEBUG_DRIVER("load hws HWS_PGA with gfx mem 0x%x\n", |
e20f9c64 | 1107 | ring->status_page.gfx_addr); |
8a4c47f3 | 1108 | DRM_DEBUG_DRIVER("load hws at %p\n", |
e20f9c64 | 1109 | ring->status_page.page_addr); |
dc7a9319 WZ |
1110 | return 0; |
1111 | } | |
1112 | ||
ec2a4c3f DA |
1113 | static int i915_get_bridge_dev(struct drm_device *dev) |
1114 | { | |
1115 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1116 | ||
0206e353 | 1117 | dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0)); |
ec2a4c3f DA |
1118 | if (!dev_priv->bridge_dev) { |
1119 | DRM_ERROR("bridge device not found\n"); | |
1120 | return -1; | |
1121 | } | |
1122 | return 0; | |
1123 | } | |
1124 | ||
c4804411 ZW |
1125 | #define MCHBAR_I915 0x44 |
1126 | #define MCHBAR_I965 0x48 | |
1127 | #define MCHBAR_SIZE (4*4096) | |
1128 | ||
1129 | #define DEVEN_REG 0x54 | |
1130 | #define DEVEN_MCHBAR_EN (1 << 28) | |
1131 | ||
1132 | /* Allocate space for the MCH regs if needed, return nonzero on error */ | |
1133 | static int | |
1134 | intel_alloc_mchbar_resource(struct drm_device *dev) | |
1135 | { | |
1136 | drm_i915_private_t *dev_priv = dev->dev_private; | |
a6c45cf0 | 1137 | int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915; |
c4804411 ZW |
1138 | u32 temp_lo, temp_hi = 0; |
1139 | u64 mchbar_addr; | |
a25c25c2 | 1140 | int ret; |
c4804411 | 1141 | |
a6c45cf0 | 1142 | if (INTEL_INFO(dev)->gen >= 4) |
c4804411 ZW |
1143 | pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi); |
1144 | pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo); | |
1145 | mchbar_addr = ((u64)temp_hi << 32) | temp_lo; | |
1146 | ||
1147 | /* If ACPI doesn't have it, assume we need to allocate it ourselves */ | |
1148 | #ifdef CONFIG_PNP | |
1149 | if (mchbar_addr && | |
a25c25c2 CW |
1150 | pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE)) |
1151 | return 0; | |
c4804411 ZW |
1152 | #endif |
1153 | ||
1154 | /* Get some space for it */ | |
a25c25c2 CW |
1155 | dev_priv->mch_res.name = "i915 MCHBAR"; |
1156 | dev_priv->mch_res.flags = IORESOURCE_MEM; | |
1157 | ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus, | |
1158 | &dev_priv->mch_res, | |
c4804411 ZW |
1159 | MCHBAR_SIZE, MCHBAR_SIZE, |
1160 | PCIBIOS_MIN_MEM, | |
a25c25c2 | 1161 | 0, pcibios_align_resource, |
c4804411 ZW |
1162 | dev_priv->bridge_dev); |
1163 | if (ret) { | |
1164 | DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret); | |
1165 | dev_priv->mch_res.start = 0; | |
a25c25c2 | 1166 | return ret; |
c4804411 ZW |
1167 | } |
1168 | ||
a6c45cf0 | 1169 | if (INTEL_INFO(dev)->gen >= 4) |
c4804411 ZW |
1170 | pci_write_config_dword(dev_priv->bridge_dev, reg + 4, |
1171 | upper_32_bits(dev_priv->mch_res.start)); | |
1172 | ||
1173 | pci_write_config_dword(dev_priv->bridge_dev, reg, | |
1174 | lower_32_bits(dev_priv->mch_res.start)); | |
a25c25c2 | 1175 | return 0; |
c4804411 ZW |
1176 | } |
1177 | ||
1178 | /* Setup MCHBAR if possible, return true if we should disable it again */ | |
1179 | static void | |
1180 | intel_setup_mchbar(struct drm_device *dev) | |
1181 | { | |
1182 | drm_i915_private_t *dev_priv = dev->dev_private; | |
a6c45cf0 | 1183 | int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915; |
c4804411 ZW |
1184 | u32 temp; |
1185 | bool enabled; | |
1186 | ||
1187 | dev_priv->mchbar_need_disable = false; | |
1188 | ||
1189 | if (IS_I915G(dev) || IS_I915GM(dev)) { | |
1190 | pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp); | |
1191 | enabled = !!(temp & DEVEN_MCHBAR_EN); | |
1192 | } else { | |
1193 | pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); | |
1194 | enabled = temp & 1; | |
1195 | } | |
1196 | ||
1197 | /* If it's already enabled, don't have to do anything */ | |
1198 | if (enabled) | |
1199 | return; | |
1200 | ||
1201 | if (intel_alloc_mchbar_resource(dev)) | |
1202 | return; | |
1203 | ||
1204 | dev_priv->mchbar_need_disable = true; | |
1205 | ||
1206 | /* Space is allocated or reserved, so enable it. */ | |
1207 | if (IS_I915G(dev) || IS_I915GM(dev)) { | |
1208 | pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, | |
1209 | temp | DEVEN_MCHBAR_EN); | |
1210 | } else { | |
1211 | pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); | |
1212 | pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1); | |
1213 | } | |
1214 | } | |
1215 | ||
1216 | static void | |
1217 | intel_teardown_mchbar(struct drm_device *dev) | |
1218 | { | |
1219 | drm_i915_private_t *dev_priv = dev->dev_private; | |
a6c45cf0 | 1220 | int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915; |
c4804411 ZW |
1221 | u32 temp; |
1222 | ||
1223 | if (dev_priv->mchbar_need_disable) { | |
1224 | if (IS_I915G(dev) || IS_I915GM(dev)) { | |
1225 | pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp); | |
1226 | temp &= ~DEVEN_MCHBAR_EN; | |
1227 | pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp); | |
1228 | } else { | |
1229 | pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); | |
1230 | temp &= ~1; | |
1231 | pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp); | |
1232 | } | |
1233 | } | |
1234 | ||
1235 | if (dev_priv->mch_res.start) | |
1236 | release_resource(&dev_priv->mch_res); | |
1237 | } | |
1238 | ||
28d52043 DA |
1239 | /* true = enable decode, false = disable decoder */ |
1240 | static unsigned int i915_vga_set_decode(void *cookie, bool state) | |
1241 | { | |
1242 | struct drm_device *dev = cookie; | |
1243 | ||
1244 | intel_modeset_vga_set_state(dev, state); | |
1245 | if (state) | |
1246 | return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | | |
1247 | VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
1248 | else | |
1249 | return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
1250 | } | |
1251 | ||
6a9ee8af DA |
1252 | static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state) |
1253 | { | |
1254 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1255 | pm_message_t pmm = { .event = PM_EVENT_SUSPEND }; | |
1256 | if (state == VGA_SWITCHEROO_ON) { | |
a70491cc | 1257 | pr_info("switched on\n"); |
5bcf719b | 1258 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; |
6a9ee8af DA |
1259 | /* i915 resume handler doesn't set to D0 */ |
1260 | pci_set_power_state(dev->pdev, PCI_D0); | |
1261 | i915_resume(dev); | |
5bcf719b | 1262 | dev->switch_power_state = DRM_SWITCH_POWER_ON; |
6a9ee8af | 1263 | } else { |
a70491cc | 1264 | pr_err("switched off\n"); |
5bcf719b | 1265 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; |
6a9ee8af | 1266 | i915_suspend(dev, pmm); |
5bcf719b | 1267 | dev->switch_power_state = DRM_SWITCH_POWER_OFF; |
6a9ee8af DA |
1268 | } |
1269 | } | |
1270 | ||
1271 | static bool i915_switcheroo_can_switch(struct pci_dev *pdev) | |
1272 | { | |
1273 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1274 | bool can_switch; | |
1275 | ||
1276 | spin_lock(&dev->count_lock); | |
1277 | can_switch = (dev->open_count == 0); | |
1278 | spin_unlock(&dev->count_lock); | |
1279 | return can_switch; | |
1280 | } | |
1281 | ||
26ec685f TI |
1282 | static const struct vga_switcheroo_client_ops i915_switcheroo_ops = { |
1283 | .set_gpu_state = i915_switcheroo_set_state, | |
1284 | .reprobe = NULL, | |
1285 | .can_switch = i915_switcheroo_can_switch, | |
1286 | }; | |
1287 | ||
2c7111db CW |
1288 | static int i915_load_modeset_init(struct drm_device *dev) |
1289 | { | |
1290 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1291 | int ret; | |
79e53945 | 1292 | |
6d139a87 | 1293 | ret = intel_parse_bios(dev); |
79e53945 JB |
1294 | if (ret) |
1295 | DRM_INFO("failed to find VBIOS tables\n"); | |
1296 | ||
934f992c CW |
1297 | /* If we have > 1 VGA cards, then we need to arbitrate access |
1298 | * to the common VGA resources. | |
1299 | * | |
1300 | * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA), | |
1301 | * then we do not take part in VGA arbitration and the | |
1302 | * vga_client_register() fails with -ENODEV. | |
1303 | */ | |
28d52043 | 1304 | ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode); |
934f992c | 1305 | if (ret && ret != -ENODEV) |
2c7111db | 1306 | goto out; |
28d52043 | 1307 | |
723bfd70 JB |
1308 | intel_register_dsm_handler(); |
1309 | ||
26ec685f | 1310 | ret = vga_switcheroo_register_client(dev->pdev, &i915_switcheroo_ops); |
6a9ee8af | 1311 | if (ret) |
5a79395b | 1312 | goto cleanup_vga_client; |
6a9ee8af | 1313 | |
9797fbfb CW |
1314 | /* Initialise stolen first so that we may reserve preallocated |
1315 | * objects for the BIOS to KMS transition. | |
1316 | */ | |
1317 | ret = i915_gem_init_stolen(dev); | |
1318 | if (ret) | |
1319 | goto cleanup_vga_switcheroo; | |
1320 | ||
b01f2c3a JB |
1321 | intel_modeset_init(dev); |
1322 | ||
1070a42b | 1323 | ret = i915_gem_init(dev); |
79e53945 | 1324 | if (ret) |
9797fbfb | 1325 | goto cleanup_gem_stolen; |
79e53945 | 1326 | |
2c7111db CW |
1327 | intel_modeset_gem_init(dev); |
1328 | ||
1329 | ret = drm_irq_install(dev); | |
1330 | if (ret) | |
1331 | goto cleanup_gem; | |
1332 | ||
79e53945 JB |
1333 | /* Always safe in the mode setting case. */ |
1334 | /* FIXME: do pre/post-mode set stuff in core KMS code */ | |
1335 | dev->vblank_disable_allowed = 1; | |
1336 | ||
5a79395b CW |
1337 | ret = intel_fbdev_init(dev); |
1338 | if (ret) | |
1339 | goto cleanup_irq; | |
1340 | ||
eb1f8e4f | 1341 | drm_kms_helper_poll_init(dev); |
87acb0a5 CW |
1342 | |
1343 | /* We're off and running w/KMS */ | |
1344 | dev_priv->mm.suspended = 0; | |
1345 | ||
79e53945 JB |
1346 | return 0; |
1347 | ||
5a79395b CW |
1348 | cleanup_irq: |
1349 | drm_irq_uninstall(dev); | |
2c7111db CW |
1350 | cleanup_gem: |
1351 | mutex_lock(&dev->struct_mutex); | |
1352 | i915_gem_cleanup_ringbuffer(dev); | |
1353 | mutex_unlock(&dev->struct_mutex); | |
1d2a314c | 1354 | i915_gem_cleanup_aliasing_ppgtt(dev); |
9797fbfb CW |
1355 | cleanup_gem_stolen: |
1356 | i915_gem_cleanup_stolen(dev); | |
5a79395b CW |
1357 | cleanup_vga_switcheroo: |
1358 | vga_switcheroo_unregister_client(dev->pdev); | |
1359 | cleanup_vga_client: | |
1360 | vga_client_register(dev->pdev, NULL, NULL, NULL); | |
79e53945 JB |
1361 | out: |
1362 | return ret; | |
1363 | } | |
1364 | ||
7c1c2871 DA |
1365 | int i915_master_create(struct drm_device *dev, struct drm_master *master) |
1366 | { | |
1367 | struct drm_i915_master_private *master_priv; | |
1368 | ||
9a298b2a | 1369 | master_priv = kzalloc(sizeof(*master_priv), GFP_KERNEL); |
7c1c2871 DA |
1370 | if (!master_priv) |
1371 | return -ENOMEM; | |
1372 | ||
1373 | master->driver_priv = master_priv; | |
1374 | return 0; | |
1375 | } | |
1376 | ||
1377 | void i915_master_destroy(struct drm_device *dev, struct drm_master *master) | |
1378 | { | |
1379 | struct drm_i915_master_private *master_priv = master->driver_priv; | |
1380 | ||
1381 | if (!master_priv) | |
1382 | return; | |
1383 | ||
9a298b2a | 1384 | kfree(master_priv); |
7c1c2871 DA |
1385 | |
1386 | master->driver_priv = NULL; | |
1387 | } | |
1388 | ||
e2b665c4 AJ |
1389 | static void |
1390 | i915_mtrr_setup(struct drm_i915_private *dev_priv, unsigned long base, | |
1391 | unsigned long size) | |
1392 | { | |
23f54bea CW |
1393 | dev_priv->mm.gtt_mtrr = -1; |
1394 | ||
9e984bc1 AJ |
1395 | #if defined(CONFIG_X86_PAT) |
1396 | if (cpu_has_pat) | |
1397 | return; | |
1398 | #endif | |
1399 | ||
e2b665c4 AJ |
1400 | /* Set up a WC MTRR for non-PAT systems. This is more common than |
1401 | * one would think, because the kernel disables PAT on first | |
1402 | * generation Core chips because WC PAT gets overridden by a UC | |
1403 | * MTRR if present. Even if a UC MTRR isn't present. | |
1404 | */ | |
1405 | dev_priv->mm.gtt_mtrr = mtrr_add(base, size, MTRR_TYPE_WRCOMB, 1); | |
1406 | if (dev_priv->mm.gtt_mtrr < 0) { | |
1407 | DRM_INFO("MTRR allocation failed. Graphics " | |
1408 | "performance may suffer.\n"); | |
1409 | } | |
1410 | } | |
1411 | ||
e188719a DV |
1412 | static void i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv) |
1413 | { | |
1414 | struct apertures_struct *ap; | |
1415 | struct pci_dev *pdev = dev_priv->dev->pdev; | |
1416 | bool primary; | |
1417 | ||
1418 | ap = alloc_apertures(1); | |
1419 | if (!ap) | |
1420 | return; | |
1421 | ||
87207ca2 | 1422 | ap->ranges[0].base = dev_priv->mm.gtt->gma_bus_addr; |
e188719a DV |
1423 | ap->ranges[0].size = |
1424 | dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT; | |
1425 | primary = | |
1426 | pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW; | |
1427 | ||
1428 | remove_conflicting_framebuffers(ap, "inteldrmfb", primary); | |
1429 | ||
1430 | kfree(ap); | |
1431 | } | |
1432 | ||
c96ea64e DV |
1433 | static void i915_dump_device_info(struct drm_i915_private *dev_priv) |
1434 | { | |
1435 | const struct intel_device_info *info = dev_priv->info; | |
1436 | ||
1437 | #define DEV_INFO_FLAG(name) info->name ? #name "," : "" | |
1438 | #define DEV_INFO_SEP , | |
1439 | DRM_DEBUG_DRIVER("i915 device info: gen=%i, pciid=0x%04x flags=" | |
1440 | "%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s", | |
1441 | info->gen, | |
1442 | dev_priv->dev->pdev->device, | |
1443 | DEV_INFO_FLAGS); | |
1444 | #undef DEV_INFO_FLAG | |
1445 | #undef DEV_INFO_SEP | |
1446 | } | |
1447 | ||
79e53945 JB |
1448 | /** |
1449 | * i915_driver_load - setup chip and create an initial config | |
1450 | * @dev: DRM device | |
1451 | * @flags: startup flags | |
1452 | * | |
1453 | * The driver load routine has to do several things: | |
1454 | * - drive output discovery via intel_modeset_init() | |
1455 | * - initialize the memory manager | |
1456 | * - allocate initial config memory | |
1457 | * - setup the DRM framebuffer with the allocated memory | |
1458 | */ | |
84b1fd10 | 1459 | int i915_driver_load(struct drm_device *dev, unsigned long flags) |
22eae947 | 1460 | { |
ea059a1e | 1461 | struct drm_i915_private *dev_priv; |
26394d92 | 1462 | struct intel_device_info *info; |
934d6086 | 1463 | int ret = 0, mmio_bar, mmio_size; |
9021f284 | 1464 | uint32_t aperture_size; |
fe669bf8 | 1465 | |
26394d92 DV |
1466 | info = (struct intel_device_info *) flags; |
1467 | ||
1468 | /* Refuse to load on gen6+ without kms enabled. */ | |
1469 | if (info->gen >= 6 && !drm_core_check_feature(dev, DRIVER_MODESET)) | |
1470 | return -ENODEV; | |
1471 | ||
22eae947 DA |
1472 | /* i915 has 4 more counters */ |
1473 | dev->counters += 4; | |
1474 | dev->types[6] = _DRM_STAT_IRQ; | |
1475 | dev->types[7] = _DRM_STAT_PRIMARY; | |
1476 | dev->types[8] = _DRM_STAT_SECONDARY; | |
1477 | dev->types[9] = _DRM_STAT_DMA; | |
1478 | ||
9a298b2a | 1479 | dev_priv = kzalloc(sizeof(drm_i915_private_t), GFP_KERNEL); |
ba8bbcf6 JB |
1480 | if (dev_priv == NULL) |
1481 | return -ENOMEM; | |
1482 | ||
ba8bbcf6 | 1483 | dev->dev_private = (void *)dev_priv; |
673a394b | 1484 | dev_priv->dev = dev; |
26394d92 | 1485 | dev_priv->info = info; |
ba8bbcf6 | 1486 | |
c96ea64e DV |
1487 | i915_dump_device_info(dev_priv); |
1488 | ||
ec2a4c3f DA |
1489 | if (i915_get_bridge_dev(dev)) { |
1490 | ret = -EIO; | |
1491 | goto free_priv; | |
1492 | } | |
1493 | ||
e188719a DV |
1494 | ret = intel_gmch_probe(dev_priv->bridge_dev, dev->pdev, NULL); |
1495 | if (!ret) { | |
1496 | DRM_ERROR("failed to set up gmch\n"); | |
1497 | ret = -EIO; | |
1498 | goto put_bridge; | |
1499 | } | |
1500 | ||
1501 | dev_priv->mm.gtt = intel_gtt_get(); | |
1502 | if (!dev_priv->mm.gtt) { | |
1503 | DRM_ERROR("Failed to initialize GTT\n"); | |
1504 | ret = -ENODEV; | |
1505 | goto put_gmch; | |
1506 | } | |
1507 | ||
1508 | i915_kick_out_firmware_fb(dev_priv); | |
1509 | ||
466e69b8 DA |
1510 | pci_set_master(dev->pdev); |
1511 | ||
9f82d238 DV |
1512 | /* overlay on gen2 is broken and can't address above 1G */ |
1513 | if (IS_GEN2(dev)) | |
1514 | dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30)); | |
1515 | ||
6927faf3 JN |
1516 | /* 965GM sometimes incorrectly writes to hardware status page (HWS) |
1517 | * using 32bit addressing, overwriting memory if HWS is located | |
1518 | * above 4GB. | |
1519 | * | |
1520 | * The documentation also mentions an issue with undefined | |
1521 | * behaviour if any general state is accessed within a page above 4GB, | |
1522 | * which also needs to be handled carefully. | |
1523 | */ | |
1524 | if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) | |
1525 | dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(32)); | |
1526 | ||
b4ce0f85 | 1527 | mmio_bar = IS_GEN2(dev) ? 1 : 0; |
934d6086 CW |
1528 | /* Before gen4, the registers and the GTT are behind different BARs. |
1529 | * However, from gen4 onwards, the registers and the GTT are shared | |
1530 | * in the same BAR, so we want to restrict this ioremap from | |
1531 | * clobbering the GTT which we want ioremap_wc instead. Fortunately, | |
1532 | * the register BAR remains the same size for all the earlier | |
1533 | * generations up to Ironlake. | |
1534 | */ | |
1535 | if (info->gen < 5) | |
1536 | mmio_size = 512*1024; | |
1537 | else | |
1538 | mmio_size = 2*1024*1024; | |
1539 | ||
1540 | dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, mmio_size); | |
b4ce0f85 CW |
1541 | if (!dev_priv->regs) { |
1542 | DRM_ERROR("failed to map registers\n"); | |
1543 | ret = -EIO; | |
14be93dd | 1544 | goto put_gmch; |
71e9339c CW |
1545 | } |
1546 | ||
9021f284 | 1547 | aperture_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT; |
dd2757f8 | 1548 | dev_priv->mm.gtt_base_addr = dev_priv->mm.gtt->gma_bus_addr; |
71e9339c | 1549 | |
0206e353 | 1550 | dev_priv->mm.gtt_mapping = |
dd2757f8 DV |
1551 | io_mapping_create_wc(dev_priv->mm.gtt_base_addr, |
1552 | aperture_size); | |
6644107d VP |
1553 | if (dev_priv->mm.gtt_mapping == NULL) { |
1554 | ret = -EIO; | |
e188719a | 1555 | goto out_rmmap; |
6644107d VP |
1556 | } |
1557 | ||
dd2757f8 DV |
1558 | i915_mtrr_setup(dev_priv, dev_priv->mm.gtt_base_addr, |
1559 | aperture_size); | |
19966754 | 1560 | |
e642abbf CW |
1561 | /* The i915 workqueue is primarily used for batched retirement of |
1562 | * requests (and thus managing bo) once the task has been completed | |
1563 | * by the GPU. i915_gem_retire_requests() is called directly when we | |
1564 | * need high-priority retirement, such as waiting for an explicit | |
1565 | * bo. | |
1566 | * | |
1567 | * It is also used for periodic low-priority events, such as | |
df9c2042 | 1568 | * idle-timers and recording error state. |
e642abbf CW |
1569 | * |
1570 | * All tasks on the workqueue are expected to acquire the dev mutex | |
1571 | * so there is no point in running more than one instance of the | |
53621860 | 1572 | * workqueue at any time. Use an ordered one. |
e642abbf | 1573 | */ |
53621860 | 1574 | dev_priv->wq = alloc_ordered_workqueue("i915", 0); |
9c9fe1f8 EA |
1575 | if (dev_priv->wq == NULL) { |
1576 | DRM_ERROR("Failed to create our workqueue.\n"); | |
1577 | ret = -ENOMEM; | |
a7b85d2a | 1578 | goto out_mtrrfree; |
9c9fe1f8 EA |
1579 | } |
1580 | ||
45e6e3a1 PZ |
1581 | /* This must be called before any calls to HAS_PCH_* */ |
1582 | intel_detect_pch(dev); | |
1583 | ||
f71d4af4 | 1584 | intel_irq_init(dev); |
990bbdad | 1585 | intel_gt_init(dev); |
9880b7a5 | 1586 | |
c4804411 ZW |
1587 | /* Try to make sure MCHBAR is enabled before poking at it */ |
1588 | intel_setup_mchbar(dev); | |
f899fc64 | 1589 | intel_setup_gmbus(dev); |
44834a67 | 1590 | intel_opregion_setup(dev); |
c4804411 | 1591 | |
6d139a87 BF |
1592 | /* Make sure the bios did its job and set up vital registers */ |
1593 | intel_setup_bios(dev); | |
1594 | ||
673a394b EA |
1595 | i915_gem_load(dev); |
1596 | ||
398c9cb2 KP |
1597 | /* Init HWS */ |
1598 | if (!I915_NEED_GFX_HWS(dev)) { | |
1599 | ret = i915_init_phys_hws(dev); | |
56e2ea34 CW |
1600 | if (ret) |
1601 | goto out_gem_unload; | |
398c9cb2 | 1602 | } |
ed4cb414 EA |
1603 | |
1604 | /* On the 945G/GM, the chipset reports the MSI capability on the | |
1605 | * integrated graphics even though the support isn't actually there | |
1606 | * according to the published specs. It doesn't appear to function | |
1607 | * correctly in testing on 945G. | |
1608 | * This may be a side effect of MSI having been made available for PEG | |
1609 | * and the registers being closely associated. | |
d1ed629f KP |
1610 | * |
1611 | * According to chipset errata, on the 965GM, MSI interrupts may | |
b60678a7 KP |
1612 | * be lost or delayed, but we use them anyways to avoid |
1613 | * stuck interrupts on some machines. | |
ed4cb414 | 1614 | */ |
b60678a7 | 1615 | if (!IS_I945G(dev) && !IS_I945GM(dev)) |
d3e74d02 | 1616 | pci_enable_msi(dev->pdev); |
ed4cb414 | 1617 | |
1ec14ad3 | 1618 | spin_lock_init(&dev_priv->irq_lock); |
63eeaf38 | 1619 | spin_lock_init(&dev_priv->error_lock); |
c6a828d3 | 1620 | spin_lock_init(&dev_priv->rps.lock); |
99d0b1db | 1621 | spin_lock_init(&dev_priv->dpio_lock); |
ed4cb414 | 1622 | |
c51ed787 | 1623 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) |
27f8227b JB |
1624 | dev_priv->num_pipe = 3; |
1625 | else if (IS_MOBILE(dev) || !IS_GEN2(dev)) | |
9db4a9c7 JB |
1626 | dev_priv->num_pipe = 2; |
1627 | else | |
1628 | dev_priv->num_pipe = 1; | |
1629 | ||
1630 | ret = drm_vblank_init(dev, dev_priv->num_pipe); | |
56e2ea34 CW |
1631 | if (ret) |
1632 | goto out_gem_unload; | |
52440211 | 1633 | |
11ed50ec BG |
1634 | /* Start out suspended */ |
1635 | dev_priv->mm.suspended = 1; | |
1636 | ||
79e53945 | 1637 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
53984635 | 1638 | ret = i915_load_modeset_init(dev); |
79e53945 JB |
1639 | if (ret < 0) { |
1640 | DRM_ERROR("failed to init modeset\n"); | |
56e2ea34 | 1641 | goto out_gem_unload; |
79e53945 JB |
1642 | } |
1643 | } | |
1644 | ||
0136db58 BW |
1645 | i915_setup_sysfs(dev); |
1646 | ||
74a365b3 | 1647 | /* Must be done after probing outputs */ |
44834a67 CW |
1648 | intel_opregion_init(dev); |
1649 | acpi_video_register(); | |
74a365b3 | 1650 | |
f65d9421 BG |
1651 | setup_timer(&dev_priv->hangcheck_timer, i915_hangcheck_elapsed, |
1652 | (unsigned long) dev); | |
7648fa99 | 1653 | |
eb48eb00 DV |
1654 | if (IS_GEN5(dev)) |
1655 | intel_gpu_ips_init(dev_priv); | |
63ee41d7 | 1656 | |
79e53945 JB |
1657 | return 0; |
1658 | ||
56e2ea34 | 1659 | out_gem_unload: |
a7b85d2a KP |
1660 | if (dev_priv->mm.inactive_shrinker.shrink) |
1661 | unregister_shrinker(&dev_priv->mm.inactive_shrinker); | |
1662 | ||
56e2ea34 CW |
1663 | if (dev->pdev->msi_enabled) |
1664 | pci_disable_msi(dev->pdev); | |
1665 | ||
1666 | intel_teardown_gmbus(dev); | |
1667 | intel_teardown_mchbar(dev); | |
9c9fe1f8 | 1668 | destroy_workqueue(dev_priv->wq); |
a7b85d2a KP |
1669 | out_mtrrfree: |
1670 | if (dev_priv->mm.gtt_mtrr >= 0) { | |
dd2757f8 DV |
1671 | mtrr_del(dev_priv->mm.gtt_mtrr, |
1672 | dev_priv->mm.gtt_base_addr, | |
1673 | aperture_size); | |
a7b85d2a KP |
1674 | dev_priv->mm.gtt_mtrr = -1; |
1675 | } | |
6644107d | 1676 | io_mapping_free(dev_priv->mm.gtt_mapping); |
79e53945 | 1677 | out_rmmap: |
6dda569f | 1678 | pci_iounmap(dev->pdev, dev_priv->regs); |
e188719a DV |
1679 | put_gmch: |
1680 | intel_gmch_remove(); | |
ec2a4c3f DA |
1681 | put_bridge: |
1682 | pci_dev_put(dev_priv->bridge_dev); | |
79e53945 | 1683 | free_priv: |
9a298b2a | 1684 | kfree(dev_priv); |
ba8bbcf6 JB |
1685 | return ret; |
1686 | } | |
1687 | ||
1688 | int i915_driver_unload(struct drm_device *dev) | |
1689 | { | |
1690 | struct drm_i915_private *dev_priv = dev->dev_private; | |
c911fc1c | 1691 | int ret; |
ba8bbcf6 | 1692 | |
eb48eb00 | 1693 | intel_gpu_ips_teardown(); |
7648fa99 | 1694 | |
0136db58 BW |
1695 | i915_teardown_sysfs(dev); |
1696 | ||
17250b71 CW |
1697 | if (dev_priv->mm.inactive_shrinker.shrink) |
1698 | unregister_shrinker(&dev_priv->mm.inactive_shrinker); | |
1699 | ||
c911fc1c | 1700 | mutex_lock(&dev->struct_mutex); |
b2da9fe5 | 1701 | ret = i915_gpu_idle(dev); |
c911fc1c DV |
1702 | if (ret) |
1703 | DRM_ERROR("failed to idle hardware: %d\n", ret); | |
b2da9fe5 | 1704 | i915_gem_retire_requests(dev); |
c911fc1c DV |
1705 | mutex_unlock(&dev->struct_mutex); |
1706 | ||
75ef9da2 DV |
1707 | /* Cancel the retire work handler, which should be idle now. */ |
1708 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); | |
1709 | ||
ab657db1 EA |
1710 | io_mapping_free(dev_priv->mm.gtt_mapping); |
1711 | if (dev_priv->mm.gtt_mtrr >= 0) { | |
dd2757f8 DV |
1712 | mtrr_del(dev_priv->mm.gtt_mtrr, |
1713 | dev_priv->mm.gtt_base_addr, | |
1714 | dev_priv->mm.gtt->gtt_mappable_entries * PAGE_SIZE); | |
ab657db1 EA |
1715 | dev_priv->mm.gtt_mtrr = -1; |
1716 | } | |
1717 | ||
44834a67 CW |
1718 | acpi_video_unregister(); |
1719 | ||
79e53945 | 1720 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
7b4f3990 | 1721 | intel_fbdev_fini(dev); |
3d8620cc JB |
1722 | intel_modeset_cleanup(dev); |
1723 | ||
6363ee6f ZY |
1724 | /* |
1725 | * free the memory space allocated for the child device | |
1726 | * config parsed from VBT | |
1727 | */ | |
1728 | if (dev_priv->child_dev && dev_priv->child_dev_num) { | |
1729 | kfree(dev_priv->child_dev); | |
1730 | dev_priv->child_dev = NULL; | |
1731 | dev_priv->child_dev_num = 0; | |
1732 | } | |
6c0d9350 | 1733 | |
6a9ee8af | 1734 | vga_switcheroo_unregister_client(dev->pdev); |
28d52043 | 1735 | vga_client_register(dev->pdev, NULL, NULL, NULL); |
79e53945 JB |
1736 | } |
1737 | ||
a8b4899e | 1738 | /* Free error state after interrupts are fully disabled. */ |
bc0c7f14 DV |
1739 | del_timer_sync(&dev_priv->hangcheck_timer); |
1740 | cancel_work_sync(&dev_priv->error_work); | |
a8b4899e | 1741 | i915_destroy_error_state(dev); |
bc0c7f14 | 1742 | |
ed4cb414 EA |
1743 | if (dev->pdev->msi_enabled) |
1744 | pci_disable_msi(dev->pdev); | |
1745 | ||
44834a67 | 1746 | intel_opregion_fini(dev); |
8ee1c3db | 1747 | |
79e53945 | 1748 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
67e77c5a DV |
1749 | /* Flush any outstanding unpin_work. */ |
1750 | flush_workqueue(dev_priv->wq); | |
1751 | ||
79e53945 | 1752 | mutex_lock(&dev->struct_mutex); |
ecbec53b | 1753 | i915_gem_free_all_phys_object(dev); |
79e53945 | 1754 | i915_gem_cleanup_ringbuffer(dev); |
55a66628 | 1755 | i915_gem_context_fini(dev); |
79e53945 | 1756 | mutex_unlock(&dev->struct_mutex); |
1d2a314c | 1757 | i915_gem_cleanup_aliasing_ppgtt(dev); |
9797fbfb | 1758 | i915_gem_cleanup_stolen(dev); |
fe669bf8 | 1759 | drm_mm_takedown(&dev_priv->mm.stolen); |
02e792fb DV |
1760 | |
1761 | intel_cleanup_overlay(dev); | |
c2873e96 KP |
1762 | |
1763 | if (!I915_NEED_GFX_HWS(dev)) | |
1764 | i915_free_hws(dev); | |
79e53945 JB |
1765 | } |
1766 | ||
701394cc | 1767 | if (dev_priv->regs != NULL) |
6dda569f | 1768 | pci_iounmap(dev->pdev, dev_priv->regs); |
701394cc | 1769 | |
f899fc64 | 1770 | intel_teardown_gmbus(dev); |
c4804411 ZW |
1771 | intel_teardown_mchbar(dev); |
1772 | ||
bc0c7f14 DV |
1773 | destroy_workqueue(dev_priv->wq); |
1774 | ||
ec2a4c3f | 1775 | pci_dev_put(dev_priv->bridge_dev); |
9a298b2a | 1776 | kfree(dev->dev_private); |
ba8bbcf6 | 1777 | |
22eae947 DA |
1778 | return 0; |
1779 | } | |
1780 | ||
f787a5f5 | 1781 | int i915_driver_open(struct drm_device *dev, struct drm_file *file) |
673a394b | 1782 | { |
f787a5f5 | 1783 | struct drm_i915_file_private *file_priv; |
673a394b | 1784 | |
8a4c47f3 | 1785 | DRM_DEBUG_DRIVER("\n"); |
f787a5f5 CW |
1786 | file_priv = kmalloc(sizeof(*file_priv), GFP_KERNEL); |
1787 | if (!file_priv) | |
673a394b EA |
1788 | return -ENOMEM; |
1789 | ||
f787a5f5 | 1790 | file->driver_priv = file_priv; |
673a394b | 1791 | |
1c25595f | 1792 | spin_lock_init(&file_priv->mm.lock); |
f787a5f5 | 1793 | INIT_LIST_HEAD(&file_priv->mm.request_list); |
673a394b | 1794 | |
df12c6d5 | 1795 | idr_init(&file_priv->context_idr); |
254f965c | 1796 | |
673a394b EA |
1797 | return 0; |
1798 | } | |
1799 | ||
79e53945 JB |
1800 | /** |
1801 | * i915_driver_lastclose - clean up after all DRM clients have exited | |
1802 | * @dev: DRM device | |
1803 | * | |
1804 | * Take care of cleaning up after all DRM clients have exited. In the | |
1805 | * mode setting case, we want to restore the kernel's initial mode (just | |
1806 | * in case the last client left us in a bad state). | |
1807 | * | |
9021f284 | 1808 | * Additionally, in the non-mode setting case, we'll tear down the GTT |
79e53945 JB |
1809 | * and DMA structures, since the kernel won't be using them, and clea |
1810 | * up any GEM state. | |
1811 | */ | |
84b1fd10 | 1812 | void i915_driver_lastclose(struct drm_device * dev) |
1da177e4 | 1813 | { |
ba8bbcf6 JB |
1814 | drm_i915_private_t *dev_priv = dev->dev_private; |
1815 | ||
e8aeaee7 DV |
1816 | /* On gen6+ we refuse to init without kms enabled, but then the drm core |
1817 | * goes right around and calls lastclose. Check for this and don't clean | |
1818 | * up anything. */ | |
1819 | if (!dev_priv) | |
1820 | return; | |
1821 | ||
1822 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { | |
e8e7a2b8 | 1823 | intel_fb_restore_mode(dev); |
6a9ee8af | 1824 | vga_switcheroo_process_delayed_switch(); |
144a75fa | 1825 | return; |
79e53945 | 1826 | } |
144a75fa | 1827 | |
673a394b EA |
1828 | i915_gem_lastclose(dev); |
1829 | ||
b5e89ed5 | 1830 | i915_dma_cleanup(dev); |
1da177e4 LT |
1831 | } |
1832 | ||
6c340eac | 1833 | void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv) |
1da177e4 | 1834 | { |
254f965c | 1835 | i915_gem_context_close(dev, file_priv); |
b962442e | 1836 | i915_gem_release(dev, file_priv); |
1da177e4 LT |
1837 | } |
1838 | ||
f787a5f5 | 1839 | void i915_driver_postclose(struct drm_device *dev, struct drm_file *file) |
673a394b | 1840 | { |
f787a5f5 | 1841 | struct drm_i915_file_private *file_priv = file->driver_priv; |
673a394b | 1842 | |
f787a5f5 | 1843 | kfree(file_priv); |
673a394b EA |
1844 | } |
1845 | ||
c153f45f | 1846 | struct drm_ioctl_desc i915_ioctls[] = { |
1b2f1489 DA |
1847 | DRM_IOCTL_DEF_DRV(I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
1848 | DRM_IOCTL_DEF_DRV(I915_FLUSH, i915_flush_ioctl, DRM_AUTH), | |
1849 | DRM_IOCTL_DEF_DRV(I915_FLIP, i915_flip_bufs, DRM_AUTH), | |
1850 | DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH), | |
1851 | DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH), | |
1852 | DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH), | |
1853 | DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH), | |
1854 | DRM_IOCTL_DEF_DRV(I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
b2c606fe DV |
1855 | DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH), |
1856 | DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH), | |
1857 | DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
1b2f1489 | 1858 | DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH), |
b2c606fe | 1859 | DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
d1c1edbc | 1860 | DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
1b2f1489 DA |
1861 | DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, i915_vblank_pipe_get, DRM_AUTH), |
1862 | DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH), | |
1863 | DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
1864 | DRM_IOCTL_DEF_DRV(I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED), | |
1865 | DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH|DRM_UNLOCKED), | |
1866 | DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_UNLOCKED), | |
1867 | DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED), | |
1868 | DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED), | |
1869 | DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED), | |
199adf40 BW |
1870 | DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_UNLOCKED), |
1871 | DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_UNLOCKED), | |
1b2f1489 DA |
1872 | DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_UNLOCKED), |
1873 | DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED), | |
1874 | DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED), | |
1875 | DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_UNLOCKED), | |
1876 | DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED), | |
1877 | DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED), | |
1878 | DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_UNLOCKED), | |
1879 | DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED), | |
1880 | DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED), | |
1881 | DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED), | |
1882 | DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_UNLOCKED), | |
1883 | DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_UNLOCKED), | |
1884 | DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED), | |
1885 | DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED), | |
1886 | DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED), | |
1887 | DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED), | |
1888 | DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED), | |
8ea30864 JB |
1889 | DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED), |
1890 | DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, intel_sprite_get_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED), | |
23ba4fd0 | 1891 | DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_UNLOCKED), |
84624813 BW |
1892 | DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_UNLOCKED), |
1893 | DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_UNLOCKED), | |
c0c7babc | 1894 | DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_UNLOCKED), |
c94f7029 DA |
1895 | }; |
1896 | ||
1897 | int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls); | |
cda17380 | 1898 | |
9021f284 DV |
1899 | /* |
1900 | * This is really ugly: Because old userspace abused the linux agp interface to | |
1901 | * manage the gtt, we need to claim that all intel devices are agp. For | |
1902 | * otherwise the drm core refuses to initialize the agp support code. | |
cda17380 | 1903 | */ |
84b1fd10 | 1904 | int i915_driver_device_is_agp(struct drm_device * dev) |
cda17380 DA |
1905 | { |
1906 | return 1; | |
1907 | } |