Commit | Line | Data |
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1da177e4 LT |
1 | /* i915_dma.c -- DMA support for the I915 -*- linux-c -*- |
2 | */ | |
0d6aa60b | 3 | /* |
1da177e4 LT |
4 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
5 | * All Rights Reserved. | |
bc54fd1a DA |
6 | * |
7 | * Permission is hereby granted, free of charge, to any person obtaining a | |
8 | * copy of this software and associated documentation files (the | |
9 | * "Software"), to deal in the Software without restriction, including | |
10 | * without limitation the rights to use, copy, modify, merge, publish, | |
11 | * distribute, sub license, and/or sell copies of the Software, and to | |
12 | * permit persons to whom the Software is furnished to do so, subject to | |
13 | * the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice (including the | |
16 | * next paragraph) shall be included in all copies or substantial portions | |
17 | * of the Software. | |
18 | * | |
19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
20 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
21 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
22 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
23 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
24 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
25 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
26 | * | |
0d6aa60b | 27 | */ |
1da177e4 | 28 | |
a70491cc JP |
29 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
30 | ||
760285e7 DH |
31 | #include <drm/drmP.h> |
32 | #include <drm/drm_crtc_helper.h> | |
33 | #include <drm/drm_fb_helper.h> | |
79e53945 | 34 | #include "intel_drv.h" |
760285e7 | 35 | #include <drm/i915_drm.h> |
1da177e4 | 36 | #include "i915_drv.h" |
1c5d22f7 | 37 | #include "i915_trace.h" |
dcdb1674 | 38 | #include <linux/pci.h> |
28d52043 | 39 | #include <linux/vgaarb.h> |
c4804411 ZW |
40 | #include <linux/acpi.h> |
41 | #include <linux/pnp.h> | |
6a9ee8af | 42 | #include <linux/vga_switcheroo.h> |
5a0e3ad6 | 43 | #include <linux/slab.h> |
44834a67 | 44 | #include <acpi/video.h> |
8a187455 PZ |
45 | #include <linux/pm.h> |
46 | #include <linux/pm_runtime.h> | |
4bdc7293 | 47 | #include <linux/oom.h> |
1da177e4 | 48 | |
09422b2e DV |
49 | #define LP_RING(d) (&((struct drm_i915_private *)(d))->ring[RCS]) |
50 | ||
51 | #define BEGIN_LP_RING(n) \ | |
52 | intel_ring_begin(LP_RING(dev_priv), (n)) | |
53 | ||
54 | #define OUT_RING(x) \ | |
55 | intel_ring_emit(LP_RING(dev_priv), x) | |
56 | ||
57 | #define ADVANCE_LP_RING() \ | |
09246732 | 58 | __intel_ring_advance(LP_RING(dev_priv)) |
09422b2e DV |
59 | |
60 | /** | |
61 | * Lock test for when it's just for synchronization of ring access. | |
62 | * | |
63 | * In that case, we don't need to do it when GEM is initialized as nobody else | |
64 | * has access to the ring. | |
65 | */ | |
66 | #define RING_LOCK_TEST_WITH_RETURN(dev, file) do { \ | |
ee1b1e5e | 67 | if (LP_RING(dev->dev_private)->buffer->obj == NULL) \ |
09422b2e DV |
68 | LOCK_TEST_WITH_RETURN(dev, file); \ |
69 | } while (0) | |
70 | ||
316d3884 DV |
71 | static inline u32 |
72 | intel_read_legacy_status_page(struct drm_i915_private *dev_priv, int reg) | |
73 | { | |
74 | if (I915_NEED_GFX_HWS(dev_priv->dev)) | |
75 | return ioread32(dev_priv->dri1.gfx_hws_cpu_addr + reg); | |
76 | else | |
77 | return intel_read_status_page(LP_RING(dev_priv), reg); | |
78 | } | |
79 | ||
80 | #define READ_HWSP(dev_priv, reg) intel_read_legacy_status_page(dev_priv, reg) | |
09422b2e DV |
81 | #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX) |
82 | #define I915_BREADCRUMB_INDEX 0x21 | |
83 | ||
d05c617e DV |
84 | void i915_update_dri1_breadcrumb(struct drm_device *dev) |
85 | { | |
4c8a4be9 | 86 | struct drm_i915_private *dev_priv = dev->dev_private; |
d05c617e DV |
87 | struct drm_i915_master_private *master_priv; |
88 | ||
6c719fac DV |
89 | /* |
90 | * The dri breadcrumb update races against the drm master disappearing. | |
91 | * Instead of trying to fix this (this is by far not the only ums issue) | |
92 | * just don't do the update in kms mode. | |
93 | */ | |
94 | if (drm_core_check_feature(dev, DRIVER_MODESET)) | |
95 | return; | |
96 | ||
d05c617e DV |
97 | if (dev->primary->master) { |
98 | master_priv = dev->primary->master->driver_priv; | |
99 | if (master_priv->sarea_priv) | |
100 | master_priv->sarea_priv->last_dispatch = | |
101 | READ_BREADCRUMB(dev_priv); | |
102 | } | |
103 | } | |
104 | ||
4cbf74cc CW |
105 | static void i915_write_hws_pga(struct drm_device *dev) |
106 | { | |
4c8a4be9 | 107 | struct drm_i915_private *dev_priv = dev->dev_private; |
4cbf74cc CW |
108 | u32 addr; |
109 | ||
110 | addr = dev_priv->status_page_dmah->busaddr; | |
111 | if (INTEL_INFO(dev)->gen >= 4) | |
112 | addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0; | |
113 | I915_WRITE(HWS_PGA, addr); | |
114 | } | |
115 | ||
398c9cb2 KP |
116 | /** |
117 | * Frees the hardware status page, whether it's a physical address or a virtual | |
118 | * address set up by the X Server. | |
119 | */ | |
3043c60c | 120 | static void i915_free_hws(struct drm_device *dev) |
398c9cb2 | 121 | { |
4c8a4be9 | 122 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 123 | struct intel_engine_cs *ring = LP_RING(dev_priv); |
1ec14ad3 | 124 | |
398c9cb2 KP |
125 | if (dev_priv->status_page_dmah) { |
126 | drm_pci_free(dev, dev_priv->status_page_dmah); | |
127 | dev_priv->status_page_dmah = NULL; | |
128 | } | |
129 | ||
1ec14ad3 CW |
130 | if (ring->status_page.gfx_addr) { |
131 | ring->status_page.gfx_addr = 0; | |
316d3884 | 132 | iounmap(dev_priv->dri1.gfx_hws_cpu_addr); |
398c9cb2 KP |
133 | } |
134 | ||
135 | /* Need to rewrite hardware status page */ | |
136 | I915_WRITE(HWS_PGA, 0x1ffff000); | |
137 | } | |
138 | ||
84b1fd10 | 139 | void i915_kernel_lost_context(struct drm_device * dev) |
1da177e4 | 140 | { |
4c8a4be9 | 141 | struct drm_i915_private *dev_priv = dev->dev_private; |
7c1c2871 | 142 | struct drm_i915_master_private *master_priv; |
a4872ba6 | 143 | struct intel_engine_cs *ring = LP_RING(dev_priv); |
1da177e4 | 144 | |
79e53945 JB |
145 | /* |
146 | * We should never lose context on the ring with modesetting | |
147 | * as we don't expose it to userspace | |
148 | */ | |
149 | if (drm_core_check_feature(dev, DRIVER_MODESET)) | |
150 | return; | |
151 | ||
ee1b1e5e OM |
152 | ring->buffer->head = I915_READ_HEAD(ring) & HEAD_ADDR; |
153 | ring->buffer->tail = I915_READ_TAIL(ring) & TAIL_ADDR; | |
154 | ring->buffer->space = ring->buffer->head - (ring->buffer->tail + I915_RING_FREE_SPACE); | |
155 | if (ring->buffer->space < 0) | |
156 | ring->buffer->space += ring->buffer->size; | |
1da177e4 | 157 | |
7c1c2871 DA |
158 | if (!dev->primary->master) |
159 | return; | |
160 | ||
161 | master_priv = dev->primary->master->driver_priv; | |
ee1b1e5e | 162 | if (ring->buffer->head == ring->buffer->tail && master_priv->sarea_priv) |
7c1c2871 | 163 | master_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY; |
1da177e4 LT |
164 | } |
165 | ||
84b1fd10 | 166 | static int i915_dma_cleanup(struct drm_device * dev) |
1da177e4 | 167 | { |
4c8a4be9 | 168 | struct drm_i915_private *dev_priv = dev->dev_private; |
1ec14ad3 CW |
169 | int i; |
170 | ||
1da177e4 LT |
171 | /* Make sure interrupts are disabled here because the uninstall ioctl |
172 | * may not have been called from userspace and after dev_private | |
173 | * is freed, it's too late. | |
174 | */ | |
ed4cb414 | 175 | if (dev->irq_enabled) |
b5e89ed5 | 176 | drm_irq_uninstall(dev); |
1da177e4 | 177 | |
ee0c6bfb | 178 | mutex_lock(&dev->struct_mutex); |
1ec14ad3 CW |
179 | for (i = 0; i < I915_NUM_RINGS; i++) |
180 | intel_cleanup_ring_buffer(&dev_priv->ring[i]); | |
ee0c6bfb | 181 | mutex_unlock(&dev->struct_mutex); |
dc7a9319 | 182 | |
398c9cb2 KP |
183 | /* Clear the HWS virtual address at teardown */ |
184 | if (I915_NEED_GFX_HWS(dev)) | |
185 | i915_free_hws(dev); | |
1da177e4 LT |
186 | |
187 | return 0; | |
188 | } | |
189 | ||
ba8bbcf6 | 190 | static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init) |
1da177e4 | 191 | { |
4c8a4be9 | 192 | struct drm_i915_private *dev_priv = dev->dev_private; |
7c1c2871 | 193 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
e8616b6c | 194 | int ret; |
1da177e4 | 195 | |
3a03ac1a DA |
196 | master_priv->sarea = drm_getsarea(dev); |
197 | if (master_priv->sarea) { | |
198 | master_priv->sarea_priv = (drm_i915_sarea_t *) | |
199 | ((u8 *)master_priv->sarea->handle + init->sarea_priv_offset); | |
200 | } else { | |
8a4c47f3 | 201 | DRM_DEBUG_DRIVER("sarea not found assuming DRI2 userspace\n"); |
3a03ac1a DA |
202 | } |
203 | ||
673a394b | 204 | if (init->ring_size != 0) { |
ee1b1e5e | 205 | if (LP_RING(dev_priv)->buffer->obj != NULL) { |
673a394b EA |
206 | i915_dma_cleanup(dev); |
207 | DRM_ERROR("Client tried to initialize ringbuffer in " | |
208 | "GEM mode\n"); | |
209 | return -EINVAL; | |
210 | } | |
1da177e4 | 211 | |
e8616b6c CW |
212 | ret = intel_render_ring_init_dri(dev, |
213 | init->ring_start, | |
214 | init->ring_size); | |
215 | if (ret) { | |
673a394b | 216 | i915_dma_cleanup(dev); |
e8616b6c | 217 | return ret; |
673a394b | 218 | } |
1da177e4 LT |
219 | } |
220 | ||
5d985ac8 DV |
221 | dev_priv->dri1.cpp = init->cpp; |
222 | dev_priv->dri1.back_offset = init->back_offset; | |
223 | dev_priv->dri1.front_offset = init->front_offset; | |
224 | dev_priv->dri1.current_page = 0; | |
7c1c2871 DA |
225 | if (master_priv->sarea_priv) |
226 | master_priv->sarea_priv->pf_current_page = 0; | |
1da177e4 | 227 | |
1da177e4 LT |
228 | /* Allow hardware batchbuffers unless told otherwise. |
229 | */ | |
8781342d | 230 | dev_priv->dri1.allow_batchbuffer = 1; |
1da177e4 | 231 | |
1da177e4 LT |
232 | return 0; |
233 | } | |
234 | ||
84b1fd10 | 235 | static int i915_dma_resume(struct drm_device * dev) |
1da177e4 | 236 | { |
4c8a4be9 | 237 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 238 | struct intel_engine_cs *ring = LP_RING(dev_priv); |
1da177e4 | 239 | |
8a4c47f3 | 240 | DRM_DEBUG_DRIVER("%s\n", __func__); |
1da177e4 | 241 | |
ee1b1e5e | 242 | if (ring->buffer->virtual_start == NULL) { |
1da177e4 LT |
243 | DRM_ERROR("can not ioremap virtual address for" |
244 | " ring buffer\n"); | |
20caafa6 | 245 | return -ENOMEM; |
1da177e4 LT |
246 | } |
247 | ||
248 | /* Program Hardware Status Page */ | |
8187a2b7 | 249 | if (!ring->status_page.page_addr) { |
1da177e4 | 250 | DRM_ERROR("Can not find hardware status page\n"); |
20caafa6 | 251 | return -EINVAL; |
1da177e4 | 252 | } |
8a4c47f3 | 253 | DRM_DEBUG_DRIVER("hw status page @ %p\n", |
8187a2b7 ZN |
254 | ring->status_page.page_addr); |
255 | if (ring->status_page.gfx_addr != 0) | |
78501eac | 256 | intel_ring_setup_status_page(ring); |
dc7a9319 | 257 | else |
4cbf74cc | 258 | i915_write_hws_pga(dev); |
8187a2b7 | 259 | |
8a4c47f3 | 260 | DRM_DEBUG_DRIVER("Enabled hardware status page\n"); |
1da177e4 LT |
261 | |
262 | return 0; | |
263 | } | |
264 | ||
c153f45f EA |
265 | static int i915_dma_init(struct drm_device *dev, void *data, |
266 | struct drm_file *file_priv) | |
1da177e4 | 267 | { |
c153f45f | 268 | drm_i915_init_t *init = data; |
1da177e4 LT |
269 | int retcode = 0; |
270 | ||
cd9d4e9f DV |
271 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
272 | return -ENODEV; | |
273 | ||
c153f45f | 274 | switch (init->func) { |
1da177e4 | 275 | case I915_INIT_DMA: |
ba8bbcf6 | 276 | retcode = i915_initialize(dev, init); |
1da177e4 LT |
277 | break; |
278 | case I915_CLEANUP_DMA: | |
279 | retcode = i915_dma_cleanup(dev); | |
280 | break; | |
281 | case I915_RESUME_DMA: | |
0d6aa60b | 282 | retcode = i915_dma_resume(dev); |
1da177e4 LT |
283 | break; |
284 | default: | |
20caafa6 | 285 | retcode = -EINVAL; |
1da177e4 LT |
286 | break; |
287 | } | |
288 | ||
289 | return retcode; | |
290 | } | |
291 | ||
292 | /* Implement basically the same security restrictions as hardware does | |
293 | * for MI_BATCH_NON_SECURE. These can be made stricter at any time. | |
294 | * | |
295 | * Most of the calculations below involve calculating the size of a | |
296 | * particular instruction. It's important to get the size right as | |
297 | * that tells us where the next instruction to check is. Any illegal | |
298 | * instruction detected will be given a size of zero, which is a | |
299 | * signal to abort the rest of the buffer. | |
300 | */ | |
e1f99ce6 | 301 | static int validate_cmd(int cmd) |
1da177e4 LT |
302 | { |
303 | switch (((cmd >> 29) & 0x7)) { | |
304 | case 0x0: | |
305 | switch ((cmd >> 23) & 0x3f) { | |
306 | case 0x0: | |
307 | return 1; /* MI_NOOP */ | |
308 | case 0x4: | |
309 | return 1; /* MI_FLUSH */ | |
310 | default: | |
311 | return 0; /* disallow everything else */ | |
312 | } | |
313 | break; | |
314 | case 0x1: | |
315 | return 0; /* reserved */ | |
316 | case 0x2: | |
317 | return (cmd & 0xff) + 2; /* 2d commands */ | |
318 | case 0x3: | |
319 | if (((cmd >> 24) & 0x1f) <= 0x18) | |
320 | return 1; | |
321 | ||
322 | switch ((cmd >> 24) & 0x1f) { | |
323 | case 0x1c: | |
324 | return 1; | |
325 | case 0x1d: | |
b5e89ed5 | 326 | switch ((cmd >> 16) & 0xff) { |
1da177e4 LT |
327 | case 0x3: |
328 | return (cmd & 0x1f) + 2; | |
329 | case 0x4: | |
330 | return (cmd & 0xf) + 2; | |
331 | default: | |
332 | return (cmd & 0xffff) + 2; | |
333 | } | |
334 | case 0x1e: | |
335 | if (cmd & (1 << 23)) | |
336 | return (cmd & 0xffff) + 1; | |
337 | else | |
338 | return 1; | |
339 | case 0x1f: | |
340 | if ((cmd & (1 << 23)) == 0) /* inline vertices */ | |
341 | return (cmd & 0x1ffff) + 2; | |
342 | else if (cmd & (1 << 17)) /* indirect random */ | |
343 | if ((cmd & 0xffff) == 0) | |
344 | return 0; /* unknown length, too hard */ | |
345 | else | |
346 | return (((cmd & 0xffff) + 1) / 2) + 1; | |
347 | else | |
348 | return 2; /* indirect sequential */ | |
349 | default: | |
350 | return 0; | |
351 | } | |
352 | default: | |
353 | return 0; | |
354 | } | |
355 | ||
356 | return 0; | |
357 | } | |
358 | ||
201361a5 | 359 | static int i915_emit_cmds(struct drm_device * dev, int *buffer, int dwords) |
1da177e4 | 360 | { |
4c8a4be9 | 361 | struct drm_i915_private *dev_priv = dev->dev_private; |
e1f99ce6 | 362 | int i, ret; |
1da177e4 | 363 | |
ee1b1e5e | 364 | if ((dwords+1) * sizeof(int) >= LP_RING(dev_priv)->buffer->size - 8) |
20caafa6 | 365 | return -EINVAL; |
de227f5f | 366 | |
1da177e4 | 367 | for (i = 0; i < dwords;) { |
e1f99ce6 CW |
368 | int sz = validate_cmd(buffer[i]); |
369 | if (sz == 0 || i + sz > dwords) | |
20caafa6 | 370 | return -EINVAL; |
e1f99ce6 | 371 | i += sz; |
1da177e4 LT |
372 | } |
373 | ||
e1f99ce6 CW |
374 | ret = BEGIN_LP_RING((dwords+1)&~1); |
375 | if (ret) | |
376 | return ret; | |
377 | ||
378 | for (i = 0; i < dwords; i++) | |
379 | OUT_RING(buffer[i]); | |
de227f5f DA |
380 | if (dwords & 1) |
381 | OUT_RING(0); | |
382 | ||
383 | ADVANCE_LP_RING(); | |
384 | ||
1da177e4 LT |
385 | return 0; |
386 | } | |
387 | ||
673a394b EA |
388 | int |
389 | i915_emit_box(struct drm_device *dev, | |
c4e7a414 CW |
390 | struct drm_clip_rect *box, |
391 | int DR1, int DR4) | |
1da177e4 | 392 | { |
e1f99ce6 | 393 | struct drm_i915_private *dev_priv = dev->dev_private; |
e1f99ce6 | 394 | int ret; |
1da177e4 | 395 | |
c4e7a414 CW |
396 | if (box->y2 <= box->y1 || box->x2 <= box->x1 || |
397 | box->y2 <= 0 || box->x2 <= 0) { | |
1da177e4 | 398 | DRM_ERROR("Bad box %d,%d..%d,%d\n", |
c4e7a414 | 399 | box->x1, box->y1, box->x2, box->y2); |
20caafa6 | 400 | return -EINVAL; |
1da177e4 LT |
401 | } |
402 | ||
a6c45cf0 | 403 | if (INTEL_INFO(dev)->gen >= 4) { |
e1f99ce6 CW |
404 | ret = BEGIN_LP_RING(4); |
405 | if (ret) | |
406 | return ret; | |
407 | ||
c29b669c | 408 | OUT_RING(GFX_OP_DRAWRECT_INFO_I965); |
c4e7a414 CW |
409 | OUT_RING((box->x1 & 0xffff) | (box->y1 << 16)); |
410 | OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16)); | |
c29b669c | 411 | OUT_RING(DR4); |
c29b669c | 412 | } else { |
e1f99ce6 CW |
413 | ret = BEGIN_LP_RING(6); |
414 | if (ret) | |
415 | return ret; | |
416 | ||
c29b669c AH |
417 | OUT_RING(GFX_OP_DRAWRECT_INFO); |
418 | OUT_RING(DR1); | |
c4e7a414 CW |
419 | OUT_RING((box->x1 & 0xffff) | (box->y1 << 16)); |
420 | OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16)); | |
c29b669c AH |
421 | OUT_RING(DR4); |
422 | OUT_RING(0); | |
c29b669c | 423 | } |
e1f99ce6 | 424 | ADVANCE_LP_RING(); |
1da177e4 LT |
425 | |
426 | return 0; | |
427 | } | |
428 | ||
c29b669c AH |
429 | /* XXX: Emitting the counter should really be moved to part of the IRQ |
430 | * emit. For now, do it in both places: | |
431 | */ | |
432 | ||
84b1fd10 | 433 | static void i915_emit_breadcrumb(struct drm_device *dev) |
de227f5f | 434 | { |
4c8a4be9 | 435 | struct drm_i915_private *dev_priv = dev->dev_private; |
7c1c2871 | 436 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
de227f5f | 437 | |
231f42a4 DV |
438 | dev_priv->dri1.counter++; |
439 | if (dev_priv->dri1.counter > 0x7FFFFFFFUL) | |
440 | dev_priv->dri1.counter = 0; | |
7c1c2871 | 441 | if (master_priv->sarea_priv) |
231f42a4 | 442 | master_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter; |
de227f5f | 443 | |
e1f99ce6 CW |
444 | if (BEGIN_LP_RING(4) == 0) { |
445 | OUT_RING(MI_STORE_DWORD_INDEX); | |
446 | OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
231f42a4 | 447 | OUT_RING(dev_priv->dri1.counter); |
e1f99ce6 CW |
448 | OUT_RING(0); |
449 | ADVANCE_LP_RING(); | |
450 | } | |
de227f5f DA |
451 | } |
452 | ||
84b1fd10 | 453 | static int i915_dispatch_cmdbuffer(struct drm_device * dev, |
201361a5 EA |
454 | drm_i915_cmdbuffer_t *cmd, |
455 | struct drm_clip_rect *cliprects, | |
456 | void *cmdbuf) | |
1da177e4 LT |
457 | { |
458 | int nbox = cmd->num_cliprects; | |
459 | int i = 0, count, ret; | |
460 | ||
461 | if (cmd->sz & 0x3) { | |
462 | DRM_ERROR("alignment"); | |
20caafa6 | 463 | return -EINVAL; |
1da177e4 LT |
464 | } |
465 | ||
466 | i915_kernel_lost_context(dev); | |
467 | ||
468 | count = nbox ? nbox : 1; | |
469 | ||
470 | for (i = 0; i < count; i++) { | |
471 | if (i < nbox) { | |
c4e7a414 | 472 | ret = i915_emit_box(dev, &cliprects[i], |
1da177e4 LT |
473 | cmd->DR1, cmd->DR4); |
474 | if (ret) | |
475 | return ret; | |
476 | } | |
477 | ||
201361a5 | 478 | ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4); |
1da177e4 LT |
479 | if (ret) |
480 | return ret; | |
481 | } | |
482 | ||
de227f5f | 483 | i915_emit_breadcrumb(dev); |
1da177e4 LT |
484 | return 0; |
485 | } | |
486 | ||
84b1fd10 | 487 | static int i915_dispatch_batchbuffer(struct drm_device * dev, |
201361a5 EA |
488 | drm_i915_batchbuffer_t * batch, |
489 | struct drm_clip_rect *cliprects) | |
1da177e4 | 490 | { |
e1f99ce6 | 491 | struct drm_i915_private *dev_priv = dev->dev_private; |
1da177e4 | 492 | int nbox = batch->num_cliprects; |
e1f99ce6 | 493 | int i, count, ret; |
1da177e4 LT |
494 | |
495 | if ((batch->start | batch->used) & 0x7) { | |
496 | DRM_ERROR("alignment"); | |
20caafa6 | 497 | return -EINVAL; |
1da177e4 LT |
498 | } |
499 | ||
500 | i915_kernel_lost_context(dev); | |
501 | ||
502 | count = nbox ? nbox : 1; | |
1da177e4 LT |
503 | for (i = 0; i < count; i++) { |
504 | if (i < nbox) { | |
c4e7a414 | 505 | ret = i915_emit_box(dev, &cliprects[i], |
e1f99ce6 | 506 | batch->DR1, batch->DR4); |
1da177e4 LT |
507 | if (ret) |
508 | return ret; | |
509 | } | |
510 | ||
0790d5e1 | 511 | if (!IS_I830(dev) && !IS_845G(dev)) { |
e1f99ce6 CW |
512 | ret = BEGIN_LP_RING(2); |
513 | if (ret) | |
514 | return ret; | |
515 | ||
a6c45cf0 | 516 | if (INTEL_INFO(dev)->gen >= 4) { |
21f16289 DA |
517 | OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965); |
518 | OUT_RING(batch->start); | |
519 | } else { | |
520 | OUT_RING(MI_BATCH_BUFFER_START | (2 << 6)); | |
521 | OUT_RING(batch->start | MI_BATCH_NON_SECURE); | |
522 | } | |
1da177e4 | 523 | } else { |
e1f99ce6 CW |
524 | ret = BEGIN_LP_RING(4); |
525 | if (ret) | |
526 | return ret; | |
527 | ||
1da177e4 LT |
528 | OUT_RING(MI_BATCH_BUFFER); |
529 | OUT_RING(batch->start | MI_BATCH_NON_SECURE); | |
530 | OUT_RING(batch->start + batch->used - 4); | |
531 | OUT_RING(0); | |
1da177e4 | 532 | } |
e1f99ce6 | 533 | ADVANCE_LP_RING(); |
1da177e4 LT |
534 | } |
535 | ||
1cafd347 | 536 | |
f00a3ddf | 537 | if (IS_G4X(dev) || IS_GEN5(dev)) { |
e1f99ce6 CW |
538 | if (BEGIN_LP_RING(2) == 0) { |
539 | OUT_RING(MI_FLUSH | MI_NO_WRITE_FLUSH | MI_INVALIDATE_ISP); | |
540 | OUT_RING(MI_NOOP); | |
541 | ADVANCE_LP_RING(); | |
542 | } | |
1cafd347 | 543 | } |
1da177e4 | 544 | |
e1f99ce6 | 545 | i915_emit_breadcrumb(dev); |
1da177e4 LT |
546 | return 0; |
547 | } | |
548 | ||
af6061af | 549 | static int i915_dispatch_flip(struct drm_device * dev) |
1da177e4 | 550 | { |
4c8a4be9 | 551 | struct drm_i915_private *dev_priv = dev->dev_private; |
7c1c2871 DA |
552 | struct drm_i915_master_private *master_priv = |
553 | dev->primary->master->driver_priv; | |
e1f99ce6 | 554 | int ret; |
1da177e4 | 555 | |
7c1c2871 | 556 | if (!master_priv->sarea_priv) |
c99b058f KH |
557 | return -EINVAL; |
558 | ||
8a4c47f3 | 559 | DRM_DEBUG_DRIVER("%s: page=%d pfCurrentPage=%d\n", |
be25ed9c | 560 | __func__, |
5d985ac8 | 561 | dev_priv->dri1.current_page, |
be25ed9c | 562 | master_priv->sarea_priv->pf_current_page); |
1da177e4 | 563 | |
af6061af DA |
564 | i915_kernel_lost_context(dev); |
565 | ||
e1f99ce6 CW |
566 | ret = BEGIN_LP_RING(10); |
567 | if (ret) | |
568 | return ret; | |
569 | ||
585fb111 | 570 | OUT_RING(MI_FLUSH | MI_READ_FLUSH); |
af6061af | 571 | OUT_RING(0); |
1da177e4 | 572 | |
af6061af DA |
573 | OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP); |
574 | OUT_RING(0); | |
5d985ac8 DV |
575 | if (dev_priv->dri1.current_page == 0) { |
576 | OUT_RING(dev_priv->dri1.back_offset); | |
577 | dev_priv->dri1.current_page = 1; | |
1da177e4 | 578 | } else { |
5d985ac8 DV |
579 | OUT_RING(dev_priv->dri1.front_offset); |
580 | dev_priv->dri1.current_page = 0; | |
1da177e4 | 581 | } |
af6061af | 582 | OUT_RING(0); |
1da177e4 | 583 | |
af6061af DA |
584 | OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP); |
585 | OUT_RING(0); | |
e1f99ce6 | 586 | |
af6061af | 587 | ADVANCE_LP_RING(); |
1da177e4 | 588 | |
231f42a4 | 589 | master_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter++; |
1da177e4 | 590 | |
e1f99ce6 CW |
591 | if (BEGIN_LP_RING(4) == 0) { |
592 | OUT_RING(MI_STORE_DWORD_INDEX); | |
593 | OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
231f42a4 | 594 | OUT_RING(dev_priv->dri1.counter); |
e1f99ce6 CW |
595 | OUT_RING(0); |
596 | ADVANCE_LP_RING(); | |
597 | } | |
1da177e4 | 598 | |
5d985ac8 | 599 | master_priv->sarea_priv->pf_current_page = dev_priv->dri1.current_page; |
af6061af | 600 | return 0; |
1da177e4 LT |
601 | } |
602 | ||
1ec14ad3 | 603 | static int i915_quiescent(struct drm_device *dev) |
1da177e4 | 604 | { |
1da177e4 | 605 | i915_kernel_lost_context(dev); |
3e960501 | 606 | return intel_ring_idle(LP_RING(dev->dev_private)); |
1da177e4 LT |
607 | } |
608 | ||
c153f45f EA |
609 | static int i915_flush_ioctl(struct drm_device *dev, void *data, |
610 | struct drm_file *file_priv) | |
1da177e4 | 611 | { |
546b0974 EA |
612 | int ret; |
613 | ||
cd9d4e9f DV |
614 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
615 | return -ENODEV; | |
616 | ||
546b0974 | 617 | RING_LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 | 618 | |
546b0974 EA |
619 | mutex_lock(&dev->struct_mutex); |
620 | ret = i915_quiescent(dev); | |
621 | mutex_unlock(&dev->struct_mutex); | |
622 | ||
623 | return ret; | |
1da177e4 LT |
624 | } |
625 | ||
c153f45f EA |
626 | static int i915_batchbuffer(struct drm_device *dev, void *data, |
627 | struct drm_file *file_priv) | |
1da177e4 | 628 | { |
4c8a4be9 | 629 | struct drm_i915_private *dev_priv = dev->dev_private; |
4d10cc0f DV |
630 | struct drm_i915_master_private *master_priv; |
631 | drm_i915_sarea_t *sarea_priv; | |
c153f45f | 632 | drm_i915_batchbuffer_t *batch = data; |
1da177e4 | 633 | int ret; |
201361a5 | 634 | struct drm_clip_rect *cliprects = NULL; |
1da177e4 | 635 | |
cd9d4e9f DV |
636 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
637 | return -ENODEV; | |
638 | ||
4d10cc0f DV |
639 | master_priv = dev->primary->master->driver_priv; |
640 | sarea_priv = (drm_i915_sarea_t *) master_priv->sarea_priv; | |
641 | ||
8781342d | 642 | if (!dev_priv->dri1.allow_batchbuffer) { |
1da177e4 | 643 | DRM_ERROR("Batchbuffer ioctl disabled\n"); |
20caafa6 | 644 | return -EINVAL; |
1da177e4 LT |
645 | } |
646 | ||
8a4c47f3 | 647 | DRM_DEBUG_DRIVER("i915 batchbuffer, start %x used %d cliprects %d\n", |
be25ed9c | 648 | batch->start, batch->used, batch->num_cliprects); |
1da177e4 | 649 | |
546b0974 | 650 | RING_LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 | 651 | |
201361a5 EA |
652 | if (batch->num_cliprects < 0) |
653 | return -EINVAL; | |
654 | ||
655 | if (batch->num_cliprects) { | |
9a298b2a | 656 | cliprects = kcalloc(batch->num_cliprects, |
b14c5679 | 657 | sizeof(*cliprects), |
9a298b2a | 658 | GFP_KERNEL); |
201361a5 EA |
659 | if (cliprects == NULL) |
660 | return -ENOMEM; | |
661 | ||
662 | ret = copy_from_user(cliprects, batch->cliprects, | |
663 | batch->num_cliprects * | |
664 | sizeof(struct drm_clip_rect)); | |
9927a403 DC |
665 | if (ret != 0) { |
666 | ret = -EFAULT; | |
201361a5 | 667 | goto fail_free; |
9927a403 | 668 | } |
201361a5 | 669 | } |
1da177e4 | 670 | |
546b0974 | 671 | mutex_lock(&dev->struct_mutex); |
201361a5 | 672 | ret = i915_dispatch_batchbuffer(dev, batch, cliprects); |
546b0974 | 673 | mutex_unlock(&dev->struct_mutex); |
1da177e4 | 674 | |
c99b058f | 675 | if (sarea_priv) |
0baf823a | 676 | sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv); |
201361a5 EA |
677 | |
678 | fail_free: | |
9a298b2a | 679 | kfree(cliprects); |
201361a5 | 680 | |
1da177e4 LT |
681 | return ret; |
682 | } | |
683 | ||
c153f45f EA |
684 | static int i915_cmdbuffer(struct drm_device *dev, void *data, |
685 | struct drm_file *file_priv) | |
1da177e4 | 686 | { |
4c8a4be9 | 687 | struct drm_i915_private *dev_priv = dev->dev_private; |
4d10cc0f DV |
688 | struct drm_i915_master_private *master_priv; |
689 | drm_i915_sarea_t *sarea_priv; | |
c153f45f | 690 | drm_i915_cmdbuffer_t *cmdbuf = data; |
201361a5 EA |
691 | struct drm_clip_rect *cliprects = NULL; |
692 | void *batch_data; | |
1da177e4 LT |
693 | int ret; |
694 | ||
8a4c47f3 | 695 | DRM_DEBUG_DRIVER("i915 cmdbuffer, buf %p sz %d cliprects %d\n", |
be25ed9c | 696 | cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects); |
1da177e4 | 697 | |
cd9d4e9f DV |
698 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
699 | return -ENODEV; | |
700 | ||
4d10cc0f DV |
701 | master_priv = dev->primary->master->driver_priv; |
702 | sarea_priv = (drm_i915_sarea_t *) master_priv->sarea_priv; | |
703 | ||
546b0974 | 704 | RING_LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 | 705 | |
201361a5 EA |
706 | if (cmdbuf->num_cliprects < 0) |
707 | return -EINVAL; | |
708 | ||
9a298b2a | 709 | batch_data = kmalloc(cmdbuf->sz, GFP_KERNEL); |
201361a5 EA |
710 | if (batch_data == NULL) |
711 | return -ENOMEM; | |
712 | ||
713 | ret = copy_from_user(batch_data, cmdbuf->buf, cmdbuf->sz); | |
9927a403 DC |
714 | if (ret != 0) { |
715 | ret = -EFAULT; | |
201361a5 | 716 | goto fail_batch_free; |
9927a403 | 717 | } |
201361a5 EA |
718 | |
719 | if (cmdbuf->num_cliprects) { | |
9a298b2a | 720 | cliprects = kcalloc(cmdbuf->num_cliprects, |
b14c5679 | 721 | sizeof(*cliprects), GFP_KERNEL); |
a40e8d31 OA |
722 | if (cliprects == NULL) { |
723 | ret = -ENOMEM; | |
201361a5 | 724 | goto fail_batch_free; |
a40e8d31 | 725 | } |
201361a5 EA |
726 | |
727 | ret = copy_from_user(cliprects, cmdbuf->cliprects, | |
728 | cmdbuf->num_cliprects * | |
729 | sizeof(struct drm_clip_rect)); | |
9927a403 DC |
730 | if (ret != 0) { |
731 | ret = -EFAULT; | |
201361a5 | 732 | goto fail_clip_free; |
9927a403 | 733 | } |
1da177e4 LT |
734 | } |
735 | ||
546b0974 | 736 | mutex_lock(&dev->struct_mutex); |
201361a5 | 737 | ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data); |
546b0974 | 738 | mutex_unlock(&dev->struct_mutex); |
1da177e4 LT |
739 | if (ret) { |
740 | DRM_ERROR("i915_dispatch_cmdbuffer failed\n"); | |
355d7f37 | 741 | goto fail_clip_free; |
1da177e4 LT |
742 | } |
743 | ||
c99b058f | 744 | if (sarea_priv) |
0baf823a | 745 | sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv); |
201361a5 | 746 | |
201361a5 | 747 | fail_clip_free: |
9a298b2a | 748 | kfree(cliprects); |
355d7f37 | 749 | fail_batch_free: |
9a298b2a | 750 | kfree(batch_data); |
201361a5 EA |
751 | |
752 | return ret; | |
1da177e4 LT |
753 | } |
754 | ||
9488867a DV |
755 | static int i915_emit_irq(struct drm_device * dev) |
756 | { | |
4c8a4be9 | 757 | struct drm_i915_private *dev_priv = dev->dev_private; |
9488867a DV |
758 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
759 | ||
760 | i915_kernel_lost_context(dev); | |
761 | ||
762 | DRM_DEBUG_DRIVER("\n"); | |
763 | ||
231f42a4 DV |
764 | dev_priv->dri1.counter++; |
765 | if (dev_priv->dri1.counter > 0x7FFFFFFFUL) | |
766 | dev_priv->dri1.counter = 1; | |
9488867a | 767 | if (master_priv->sarea_priv) |
231f42a4 | 768 | master_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter; |
9488867a DV |
769 | |
770 | if (BEGIN_LP_RING(4) == 0) { | |
771 | OUT_RING(MI_STORE_DWORD_INDEX); | |
772 | OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
231f42a4 | 773 | OUT_RING(dev_priv->dri1.counter); |
9488867a DV |
774 | OUT_RING(MI_USER_INTERRUPT); |
775 | ADVANCE_LP_RING(); | |
776 | } | |
777 | ||
231f42a4 | 778 | return dev_priv->dri1.counter; |
9488867a DV |
779 | } |
780 | ||
781 | static int i915_wait_irq(struct drm_device * dev, int irq_nr) | |
782 | { | |
4c8a4be9 | 783 | struct drm_i915_private *dev_priv = dev->dev_private; |
9488867a DV |
784 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
785 | int ret = 0; | |
a4872ba6 | 786 | struct intel_engine_cs *ring = LP_RING(dev_priv); |
9488867a DV |
787 | |
788 | DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr, | |
789 | READ_BREADCRUMB(dev_priv)); | |
790 | ||
791 | if (READ_BREADCRUMB(dev_priv) >= irq_nr) { | |
792 | if (master_priv->sarea_priv) | |
793 | master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv); | |
794 | return 0; | |
795 | } | |
796 | ||
797 | if (master_priv->sarea_priv) | |
798 | master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT; | |
799 | ||
800 | if (ring->irq_get(ring)) { | |
bfd8303a | 801 | DRM_WAIT_ON(ret, ring->irq_queue, 3 * HZ, |
9488867a DV |
802 | READ_BREADCRUMB(dev_priv) >= irq_nr); |
803 | ring->irq_put(ring); | |
804 | } else if (wait_for(READ_BREADCRUMB(dev_priv) >= irq_nr, 3000)) | |
805 | ret = -EBUSY; | |
806 | ||
807 | if (ret == -EBUSY) { | |
808 | DRM_ERROR("EBUSY -- rec: %d emitted: %d\n", | |
231f42a4 | 809 | READ_BREADCRUMB(dev_priv), (int)dev_priv->dri1.counter); |
9488867a DV |
810 | } |
811 | ||
812 | return ret; | |
813 | } | |
814 | ||
815 | /* Needs the lock as it touches the ring. | |
816 | */ | |
817 | static int i915_irq_emit(struct drm_device *dev, void *data, | |
818 | struct drm_file *file_priv) | |
819 | { | |
4c8a4be9 | 820 | struct drm_i915_private *dev_priv = dev->dev_private; |
9488867a DV |
821 | drm_i915_irq_emit_t *emit = data; |
822 | int result; | |
823 | ||
824 | if (drm_core_check_feature(dev, DRIVER_MODESET)) | |
825 | return -ENODEV; | |
826 | ||
ee1b1e5e | 827 | if (!dev_priv || !LP_RING(dev_priv)->buffer->virtual_start) { |
9488867a DV |
828 | DRM_ERROR("called with no initialization\n"); |
829 | return -EINVAL; | |
830 | } | |
831 | ||
832 | RING_LOCK_TEST_WITH_RETURN(dev, file_priv); | |
833 | ||
834 | mutex_lock(&dev->struct_mutex); | |
835 | result = i915_emit_irq(dev); | |
836 | mutex_unlock(&dev->struct_mutex); | |
837 | ||
1d6ac185 | 838 | if (copy_to_user(emit->irq_seq, &result, sizeof(int))) { |
9488867a DV |
839 | DRM_ERROR("copy_to_user\n"); |
840 | return -EFAULT; | |
841 | } | |
842 | ||
843 | return 0; | |
844 | } | |
845 | ||
846 | /* Doesn't need the hardware lock. | |
847 | */ | |
848 | static int i915_irq_wait(struct drm_device *dev, void *data, | |
849 | struct drm_file *file_priv) | |
850 | { | |
4c8a4be9 | 851 | struct drm_i915_private *dev_priv = dev->dev_private; |
9488867a DV |
852 | drm_i915_irq_wait_t *irqwait = data; |
853 | ||
854 | if (drm_core_check_feature(dev, DRIVER_MODESET)) | |
855 | return -ENODEV; | |
856 | ||
857 | if (!dev_priv) { | |
858 | DRM_ERROR("called with no initialization\n"); | |
859 | return -EINVAL; | |
860 | } | |
861 | ||
862 | return i915_wait_irq(dev, irqwait->irq_seq); | |
863 | } | |
864 | ||
d1c1edbc DV |
865 | static int i915_vblank_pipe_get(struct drm_device *dev, void *data, |
866 | struct drm_file *file_priv) | |
867 | { | |
4c8a4be9 | 868 | struct drm_i915_private *dev_priv = dev->dev_private; |
d1c1edbc DV |
869 | drm_i915_vblank_pipe_t *pipe = data; |
870 | ||
871 | if (drm_core_check_feature(dev, DRIVER_MODESET)) | |
872 | return -ENODEV; | |
873 | ||
874 | if (!dev_priv) { | |
875 | DRM_ERROR("called with no initialization\n"); | |
876 | return -EINVAL; | |
877 | } | |
878 | ||
879 | pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B; | |
880 | ||
881 | return 0; | |
882 | } | |
883 | ||
884 | /** | |
885 | * Schedule buffer swap at given vertical blank. | |
886 | */ | |
887 | static int i915_vblank_swap(struct drm_device *dev, void *data, | |
888 | struct drm_file *file_priv) | |
889 | { | |
890 | /* The delayed swap mechanism was fundamentally racy, and has been | |
891 | * removed. The model was that the client requested a delayed flip/swap | |
892 | * from the kernel, then waited for vblank before continuing to perform | |
893 | * rendering. The problem was that the kernel might wake the client | |
894 | * up before it dispatched the vblank swap (since the lock has to be | |
895 | * held while touching the ringbuffer), in which case the client would | |
896 | * clear and start the next frame before the swap occurred, and | |
897 | * flicker would occur in addition to likely missing the vblank. | |
898 | * | |
899 | * In the absence of this ioctl, userland falls back to a correct path | |
900 | * of waiting for a vblank, then dispatching the swap on its own. | |
901 | * Context switching to userland and back is plenty fast enough for | |
902 | * meeting the requirements of vblank swapping. | |
903 | */ | |
904 | return -EINVAL; | |
905 | } | |
906 | ||
c153f45f EA |
907 | static int i915_flip_bufs(struct drm_device *dev, void *data, |
908 | struct drm_file *file_priv) | |
1da177e4 | 909 | { |
546b0974 EA |
910 | int ret; |
911 | ||
cd9d4e9f DV |
912 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
913 | return -ENODEV; | |
914 | ||
8a4c47f3 | 915 | DRM_DEBUG_DRIVER("%s\n", __func__); |
1da177e4 | 916 | |
546b0974 | 917 | RING_LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 | 918 | |
546b0974 EA |
919 | mutex_lock(&dev->struct_mutex); |
920 | ret = i915_dispatch_flip(dev); | |
921 | mutex_unlock(&dev->struct_mutex); | |
922 | ||
923 | return ret; | |
1da177e4 LT |
924 | } |
925 | ||
c153f45f EA |
926 | static int i915_getparam(struct drm_device *dev, void *data, |
927 | struct drm_file *file_priv) | |
1da177e4 | 928 | { |
4c8a4be9 | 929 | struct drm_i915_private *dev_priv = dev->dev_private; |
c153f45f | 930 | drm_i915_getparam_t *param = data; |
1da177e4 LT |
931 | int value; |
932 | ||
933 | if (!dev_priv) { | |
3e684eae | 934 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 935 | return -EINVAL; |
1da177e4 LT |
936 | } |
937 | ||
c153f45f | 938 | switch (param->param) { |
1da177e4 | 939 | case I915_PARAM_IRQ_ACTIVE: |
0a3e67a4 | 940 | value = dev->pdev->irq ? 1 : 0; |
1da177e4 LT |
941 | break; |
942 | case I915_PARAM_ALLOW_BATCHBUFFER: | |
8781342d | 943 | value = dev_priv->dri1.allow_batchbuffer ? 1 : 0; |
1da177e4 | 944 | break; |
0d6aa60b DA |
945 | case I915_PARAM_LAST_DISPATCH: |
946 | value = READ_BREADCRUMB(dev_priv); | |
947 | break; | |
ed4c9c4a | 948 | case I915_PARAM_CHIPSET_ID: |
ffbab09b | 949 | value = dev->pdev->device; |
ed4c9c4a | 950 | break; |
673a394b | 951 | case I915_PARAM_HAS_GEM: |
2e895b17 | 952 | value = 1; |
673a394b | 953 | break; |
0f973f27 JB |
954 | case I915_PARAM_NUM_FENCES_AVAIL: |
955 | value = dev_priv->num_fence_regs - dev_priv->fence_reg_start; | |
956 | break; | |
02e792fb DV |
957 | case I915_PARAM_HAS_OVERLAY: |
958 | value = dev_priv->overlay ? 1 : 0; | |
959 | break; | |
e9560f7c JB |
960 | case I915_PARAM_HAS_PAGEFLIPPING: |
961 | value = 1; | |
962 | break; | |
76446cac JB |
963 | case I915_PARAM_HAS_EXECBUF2: |
964 | /* depends on GEM */ | |
2e895b17 | 965 | value = 1; |
76446cac | 966 | break; |
e3a815fc | 967 | case I915_PARAM_HAS_BSD: |
edc912f5 | 968 | value = intel_ring_initialized(&dev_priv->ring[VCS]); |
e3a815fc | 969 | break; |
549f7365 | 970 | case I915_PARAM_HAS_BLT: |
edc912f5 | 971 | value = intel_ring_initialized(&dev_priv->ring[BCS]); |
549f7365 | 972 | break; |
a1f2cc73 XH |
973 | case I915_PARAM_HAS_VEBOX: |
974 | value = intel_ring_initialized(&dev_priv->ring[VECS]); | |
975 | break; | |
a00b10c3 CW |
976 | case I915_PARAM_HAS_RELAXED_FENCING: |
977 | value = 1; | |
978 | break; | |
bbf0c6b3 DV |
979 | case I915_PARAM_HAS_COHERENT_RINGS: |
980 | value = 1; | |
981 | break; | |
72bfa19c CW |
982 | case I915_PARAM_HAS_EXEC_CONSTANTS: |
983 | value = INTEL_INFO(dev)->gen >= 4; | |
984 | break; | |
271d81b8 CW |
985 | case I915_PARAM_HAS_RELAXED_DELTA: |
986 | value = 1; | |
987 | break; | |
ae662d31 EA |
988 | case I915_PARAM_HAS_GEN7_SOL_RESET: |
989 | value = 1; | |
990 | break; | |
3d29b842 ED |
991 | case I915_PARAM_HAS_LLC: |
992 | value = HAS_LLC(dev); | |
993 | break; | |
651d794f CW |
994 | case I915_PARAM_HAS_WT: |
995 | value = HAS_WT(dev); | |
996 | break; | |
777ee96f | 997 | case I915_PARAM_HAS_ALIASING_PPGTT: |
7d9c4779 | 998 | value = dev_priv->mm.aliasing_ppgtt || USES_FULL_PPGTT(dev); |
777ee96f | 999 | break; |
172cf15d BW |
1000 | case I915_PARAM_HAS_WAIT_TIMEOUT: |
1001 | value = 1; | |
1002 | break; | |
2fedbff9 CW |
1003 | case I915_PARAM_HAS_SEMAPHORES: |
1004 | value = i915_semaphore_is_enabled(dev); | |
1005 | break; | |
ec6f1bb9 DA |
1006 | case I915_PARAM_HAS_PRIME_VMAP_FLUSH: |
1007 | value = 1; | |
1008 | break; | |
d7d4eedd CW |
1009 | case I915_PARAM_HAS_SECURE_BATCHES: |
1010 | value = capable(CAP_SYS_ADMIN); | |
1011 | break; | |
b45305fc DV |
1012 | case I915_PARAM_HAS_PINNED_BATCHES: |
1013 | value = 1; | |
1014 | break; | |
ed5982e6 DV |
1015 | case I915_PARAM_HAS_EXEC_NO_RELOC: |
1016 | value = 1; | |
1017 | break; | |
eef90ccb CW |
1018 | case I915_PARAM_HAS_EXEC_HANDLE_LUT: |
1019 | value = 1; | |
1020 | break; | |
d728c8ef BV |
1021 | case I915_PARAM_CMD_PARSER_VERSION: |
1022 | value = i915_cmd_parser_get_version(); | |
1023 | break; | |
1da177e4 | 1024 | default: |
e29c32da | 1025 | DRM_DEBUG("Unknown parameter %d\n", param->param); |
20caafa6 | 1026 | return -EINVAL; |
1da177e4 LT |
1027 | } |
1028 | ||
1d6ac185 DV |
1029 | if (copy_to_user(param->value, &value, sizeof(int))) { |
1030 | DRM_ERROR("copy_to_user failed\n"); | |
20caafa6 | 1031 | return -EFAULT; |
1da177e4 LT |
1032 | } |
1033 | ||
1034 | return 0; | |
1035 | } | |
1036 | ||
c153f45f EA |
1037 | static int i915_setparam(struct drm_device *dev, void *data, |
1038 | struct drm_file *file_priv) | |
1da177e4 | 1039 | { |
4c8a4be9 | 1040 | struct drm_i915_private *dev_priv = dev->dev_private; |
c153f45f | 1041 | drm_i915_setparam_t *param = data; |
1da177e4 LT |
1042 | |
1043 | if (!dev_priv) { | |
3e684eae | 1044 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 1045 | return -EINVAL; |
1da177e4 LT |
1046 | } |
1047 | ||
c153f45f | 1048 | switch (param->param) { |
1da177e4 | 1049 | case I915_SETPARAM_USE_MI_BATCHBUFFER_START: |
1da177e4 LT |
1050 | break; |
1051 | case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY: | |
1da177e4 LT |
1052 | break; |
1053 | case I915_SETPARAM_ALLOW_BATCHBUFFER: | |
8781342d | 1054 | dev_priv->dri1.allow_batchbuffer = param->value ? 1 : 0; |
1da177e4 | 1055 | break; |
0f973f27 JB |
1056 | case I915_SETPARAM_NUM_USED_FENCES: |
1057 | if (param->value > dev_priv->num_fence_regs || | |
1058 | param->value < 0) | |
1059 | return -EINVAL; | |
1060 | /* Userspace can use first N regs */ | |
1061 | dev_priv->fence_reg_start = param->value; | |
1062 | break; | |
1da177e4 | 1063 | default: |
8a4c47f3 | 1064 | DRM_DEBUG_DRIVER("unknown parameter %d\n", |
be25ed9c | 1065 | param->param); |
20caafa6 | 1066 | return -EINVAL; |
1da177e4 LT |
1067 | } |
1068 | ||
1069 | return 0; | |
1070 | } | |
1071 | ||
c153f45f EA |
1072 | static int i915_set_status_page(struct drm_device *dev, void *data, |
1073 | struct drm_file *file_priv) | |
dc7a9319 | 1074 | { |
4c8a4be9 | 1075 | struct drm_i915_private *dev_priv = dev->dev_private; |
c153f45f | 1076 | drm_i915_hws_addr_t *hws = data; |
a4872ba6 | 1077 | struct intel_engine_cs *ring; |
b39d50e5 | 1078 | |
cd9d4e9f DV |
1079 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
1080 | return -ENODEV; | |
1081 | ||
b39d50e5 ZW |
1082 | if (!I915_NEED_GFX_HWS(dev)) |
1083 | return -EINVAL; | |
dc7a9319 WZ |
1084 | |
1085 | if (!dev_priv) { | |
3e684eae | 1086 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 1087 | return -EINVAL; |
dc7a9319 | 1088 | } |
dc7a9319 | 1089 | |
79e53945 JB |
1090 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
1091 | WARN(1, "tried to set status page when mode setting active\n"); | |
1092 | return 0; | |
1093 | } | |
1094 | ||
8a4c47f3 | 1095 | DRM_DEBUG_DRIVER("set status page addr 0x%08x\n", (u32)hws->addr); |
c153f45f | 1096 | |
4f1ba0f8 | 1097 | ring = LP_RING(dev_priv); |
8187a2b7 | 1098 | ring->status_page.gfx_addr = hws->addr & (0x1ffff<<12); |
dc7a9319 | 1099 | |
dd2757f8 | 1100 | dev_priv->dri1.gfx_hws_cpu_addr = |
5d4545ae | 1101 | ioremap_wc(dev_priv->gtt.mappable_base + hws->addr, 4096); |
316d3884 | 1102 | if (dev_priv->dri1.gfx_hws_cpu_addr == NULL) { |
dc7a9319 | 1103 | i915_dma_cleanup(dev); |
e20f9c64 | 1104 | ring->status_page.gfx_addr = 0; |
dc7a9319 WZ |
1105 | DRM_ERROR("can not ioremap virtual address for" |
1106 | " G33 hw status page\n"); | |
20caafa6 | 1107 | return -ENOMEM; |
dc7a9319 | 1108 | } |
316d3884 DV |
1109 | |
1110 | memset_io(dev_priv->dri1.gfx_hws_cpu_addr, 0, PAGE_SIZE); | |
8187a2b7 | 1111 | I915_WRITE(HWS_PGA, ring->status_page.gfx_addr); |
dc7a9319 | 1112 | |
8a4c47f3 | 1113 | DRM_DEBUG_DRIVER("load hws HWS_PGA with gfx mem 0x%x\n", |
e20f9c64 | 1114 | ring->status_page.gfx_addr); |
8a4c47f3 | 1115 | DRM_DEBUG_DRIVER("load hws at %p\n", |
e20f9c64 | 1116 | ring->status_page.page_addr); |
dc7a9319 WZ |
1117 | return 0; |
1118 | } | |
1119 | ||
ec2a4c3f DA |
1120 | static int i915_get_bridge_dev(struct drm_device *dev) |
1121 | { | |
1122 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1123 | ||
0206e353 | 1124 | dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0)); |
ec2a4c3f DA |
1125 | if (!dev_priv->bridge_dev) { |
1126 | DRM_ERROR("bridge device not found\n"); | |
1127 | return -1; | |
1128 | } | |
1129 | return 0; | |
1130 | } | |
1131 | ||
c4804411 ZW |
1132 | #define MCHBAR_I915 0x44 |
1133 | #define MCHBAR_I965 0x48 | |
1134 | #define MCHBAR_SIZE (4*4096) | |
1135 | ||
1136 | #define DEVEN_REG 0x54 | |
1137 | #define DEVEN_MCHBAR_EN (1 << 28) | |
1138 | ||
1139 | /* Allocate space for the MCH regs if needed, return nonzero on error */ | |
1140 | static int | |
1141 | intel_alloc_mchbar_resource(struct drm_device *dev) | |
1142 | { | |
4c8a4be9 | 1143 | struct drm_i915_private *dev_priv = dev->dev_private; |
a6c45cf0 | 1144 | int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915; |
c4804411 ZW |
1145 | u32 temp_lo, temp_hi = 0; |
1146 | u64 mchbar_addr; | |
a25c25c2 | 1147 | int ret; |
c4804411 | 1148 | |
a6c45cf0 | 1149 | if (INTEL_INFO(dev)->gen >= 4) |
c4804411 ZW |
1150 | pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi); |
1151 | pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo); | |
1152 | mchbar_addr = ((u64)temp_hi << 32) | temp_lo; | |
1153 | ||
1154 | /* If ACPI doesn't have it, assume we need to allocate it ourselves */ | |
1155 | #ifdef CONFIG_PNP | |
1156 | if (mchbar_addr && | |
a25c25c2 CW |
1157 | pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE)) |
1158 | return 0; | |
c4804411 ZW |
1159 | #endif |
1160 | ||
1161 | /* Get some space for it */ | |
a25c25c2 CW |
1162 | dev_priv->mch_res.name = "i915 MCHBAR"; |
1163 | dev_priv->mch_res.flags = IORESOURCE_MEM; | |
1164 | ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus, | |
1165 | &dev_priv->mch_res, | |
c4804411 ZW |
1166 | MCHBAR_SIZE, MCHBAR_SIZE, |
1167 | PCIBIOS_MIN_MEM, | |
a25c25c2 | 1168 | 0, pcibios_align_resource, |
c4804411 ZW |
1169 | dev_priv->bridge_dev); |
1170 | if (ret) { | |
1171 | DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret); | |
1172 | dev_priv->mch_res.start = 0; | |
a25c25c2 | 1173 | return ret; |
c4804411 ZW |
1174 | } |
1175 | ||
a6c45cf0 | 1176 | if (INTEL_INFO(dev)->gen >= 4) |
c4804411 ZW |
1177 | pci_write_config_dword(dev_priv->bridge_dev, reg + 4, |
1178 | upper_32_bits(dev_priv->mch_res.start)); | |
1179 | ||
1180 | pci_write_config_dword(dev_priv->bridge_dev, reg, | |
1181 | lower_32_bits(dev_priv->mch_res.start)); | |
a25c25c2 | 1182 | return 0; |
c4804411 ZW |
1183 | } |
1184 | ||
1185 | /* Setup MCHBAR if possible, return true if we should disable it again */ | |
1186 | static void | |
1187 | intel_setup_mchbar(struct drm_device *dev) | |
1188 | { | |
4c8a4be9 | 1189 | struct drm_i915_private *dev_priv = dev->dev_private; |
a6c45cf0 | 1190 | int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915; |
c4804411 ZW |
1191 | u32 temp; |
1192 | bool enabled; | |
1193 | ||
11ea8b7d JB |
1194 | if (IS_VALLEYVIEW(dev)) |
1195 | return; | |
1196 | ||
c4804411 ZW |
1197 | dev_priv->mchbar_need_disable = false; |
1198 | ||
1199 | if (IS_I915G(dev) || IS_I915GM(dev)) { | |
1200 | pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp); | |
1201 | enabled = !!(temp & DEVEN_MCHBAR_EN); | |
1202 | } else { | |
1203 | pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); | |
1204 | enabled = temp & 1; | |
1205 | } | |
1206 | ||
1207 | /* If it's already enabled, don't have to do anything */ | |
1208 | if (enabled) | |
1209 | return; | |
1210 | ||
1211 | if (intel_alloc_mchbar_resource(dev)) | |
1212 | return; | |
1213 | ||
1214 | dev_priv->mchbar_need_disable = true; | |
1215 | ||
1216 | /* Space is allocated or reserved, so enable it. */ | |
1217 | if (IS_I915G(dev) || IS_I915GM(dev)) { | |
1218 | pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, | |
1219 | temp | DEVEN_MCHBAR_EN); | |
1220 | } else { | |
1221 | pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); | |
1222 | pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1); | |
1223 | } | |
1224 | } | |
1225 | ||
1226 | static void | |
1227 | intel_teardown_mchbar(struct drm_device *dev) | |
1228 | { | |
4c8a4be9 | 1229 | struct drm_i915_private *dev_priv = dev->dev_private; |
a6c45cf0 | 1230 | int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915; |
c4804411 ZW |
1231 | u32 temp; |
1232 | ||
1233 | if (dev_priv->mchbar_need_disable) { | |
1234 | if (IS_I915G(dev) || IS_I915GM(dev)) { | |
1235 | pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp); | |
1236 | temp &= ~DEVEN_MCHBAR_EN; | |
1237 | pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp); | |
1238 | } else { | |
1239 | pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); | |
1240 | temp &= ~1; | |
1241 | pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp); | |
1242 | } | |
1243 | } | |
1244 | ||
1245 | if (dev_priv->mch_res.start) | |
1246 | release_resource(&dev_priv->mch_res); | |
1247 | } | |
1248 | ||
28d52043 DA |
1249 | /* true = enable decode, false = disable decoder */ |
1250 | static unsigned int i915_vga_set_decode(void *cookie, bool state) | |
1251 | { | |
1252 | struct drm_device *dev = cookie; | |
1253 | ||
1254 | intel_modeset_vga_set_state(dev, state); | |
1255 | if (state) | |
1256 | return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | | |
1257 | VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
1258 | else | |
1259 | return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
1260 | } | |
1261 | ||
6a9ee8af DA |
1262 | static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state) |
1263 | { | |
1264 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1265 | pm_message_t pmm = { .event = PM_EVENT_SUSPEND }; | |
1266 | if (state == VGA_SWITCHEROO_ON) { | |
a70491cc | 1267 | pr_info("switched on\n"); |
5bcf719b | 1268 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; |
6a9ee8af DA |
1269 | /* i915 resume handler doesn't set to D0 */ |
1270 | pci_set_power_state(dev->pdev, PCI_D0); | |
1271 | i915_resume(dev); | |
5bcf719b | 1272 | dev->switch_power_state = DRM_SWITCH_POWER_ON; |
6a9ee8af | 1273 | } else { |
a70491cc | 1274 | pr_err("switched off\n"); |
5bcf719b | 1275 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; |
6a9ee8af | 1276 | i915_suspend(dev, pmm); |
5bcf719b | 1277 | dev->switch_power_state = DRM_SWITCH_POWER_OFF; |
6a9ee8af DA |
1278 | } |
1279 | } | |
1280 | ||
1281 | static bool i915_switcheroo_can_switch(struct pci_dev *pdev) | |
1282 | { | |
1283 | struct drm_device *dev = pci_get_drvdata(pdev); | |
6a9ee8af | 1284 | |
fc8fd40e DV |
1285 | /* |
1286 | * FIXME: open_count is protected by drm_global_mutex but that would lead to | |
1287 | * locking inversion with the driver load path. And the access here is | |
1288 | * completely racy anyway. So don't bother with locking for now. | |
1289 | */ | |
1290 | return dev->open_count == 0; | |
6a9ee8af DA |
1291 | } |
1292 | ||
26ec685f TI |
1293 | static const struct vga_switcheroo_client_ops i915_switcheroo_ops = { |
1294 | .set_gpu_state = i915_switcheroo_set_state, | |
1295 | .reprobe = NULL, | |
1296 | .can_switch = i915_switcheroo_can_switch, | |
1297 | }; | |
1298 | ||
2c7111db CW |
1299 | static int i915_load_modeset_init(struct drm_device *dev) |
1300 | { | |
1301 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1302 | int ret; | |
79e53945 | 1303 | |
6d139a87 | 1304 | ret = intel_parse_bios(dev); |
79e53945 JB |
1305 | if (ret) |
1306 | DRM_INFO("failed to find VBIOS tables\n"); | |
1307 | ||
934f992c CW |
1308 | /* If we have > 1 VGA cards, then we need to arbitrate access |
1309 | * to the common VGA resources. | |
1310 | * | |
1311 | * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA), | |
1312 | * then we do not take part in VGA arbitration and the | |
1313 | * vga_client_register() fails with -ENODEV. | |
1314 | */ | |
ebff5fa9 DA |
1315 | ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode); |
1316 | if (ret && ret != -ENODEV) | |
1317 | goto out; | |
28d52043 | 1318 | |
723bfd70 JB |
1319 | intel_register_dsm_handler(); |
1320 | ||
0d69704a | 1321 | ret = vga_switcheroo_register_client(dev->pdev, &i915_switcheroo_ops, false); |
6a9ee8af | 1322 | if (ret) |
5a79395b | 1323 | goto cleanup_vga_client; |
6a9ee8af | 1324 | |
9797fbfb CW |
1325 | /* Initialise stolen first so that we may reserve preallocated |
1326 | * objects for the BIOS to KMS transition. | |
1327 | */ | |
1328 | ret = i915_gem_init_stolen(dev); | |
1329 | if (ret) | |
1330 | goto cleanup_vga_switcheroo; | |
1331 | ||
e13192f6 ID |
1332 | intel_power_domains_init_hw(dev_priv); |
1333 | ||
bb0f1b5c | 1334 | ret = drm_irq_install(dev, dev->pdev->irq); |
52d7eced DV |
1335 | if (ret) |
1336 | goto cleanup_gem_stolen; | |
1337 | ||
1338 | /* Important: The output setup functions called by modeset_init need | |
1339 | * working irqs for e.g. gmbus and dp aux transfers. */ | |
b01f2c3a JB |
1340 | intel_modeset_init(dev); |
1341 | ||
1070a42b | 1342 | ret = i915_gem_init(dev); |
79e53945 | 1343 | if (ret) |
713028b3 | 1344 | goto cleanup_irq; |
2c7111db | 1345 | |
073f34d9 JB |
1346 | INIT_WORK(&dev_priv->console_resume_work, intel_console_resume); |
1347 | ||
52d7eced | 1348 | intel_modeset_gem_init(dev); |
2c7111db | 1349 | |
79e53945 JB |
1350 | /* Always safe in the mode setting case. */ |
1351 | /* FIXME: do pre/post-mode set stuff in core KMS code */ | |
ba0bf120 | 1352 | dev->vblank_disable_allowed = true; |
713028b3 | 1353 | if (INTEL_INFO(dev)->num_pipes == 0) |
e3c74757 | 1354 | return 0; |
79e53945 | 1355 | |
5a79395b CW |
1356 | ret = intel_fbdev_init(dev); |
1357 | if (ret) | |
52d7eced DV |
1358 | goto cleanup_gem; |
1359 | ||
20afbda2 DV |
1360 | /* Only enable hotplug handling once the fbdev is fully set up. */ |
1361 | intel_hpd_init(dev); | |
1362 | ||
1363 | /* | |
1364 | * Some ports require correctly set-up hpd registers for detection to | |
1365 | * work properly (leading to ghost connected connector status), e.g. VGA | |
1366 | * on gm45. Hence we can only set up the initial fbdev config after hpd | |
1367 | * irqs are fully enabled. Now we should scan for the initial config | |
1368 | * only once hotplug handling is enabled, but due to screwed-up locking | |
1369 | * around kms/fbdev init we can't protect the fdbev initial config | |
1370 | * scanning against hotplug events. Hence do this first and ignore the | |
1371 | * tiny window where we will loose hotplug notifactions. | |
1372 | */ | |
1373 | intel_fbdev_initial_config(dev); | |
1374 | ||
52d7eced DV |
1375 | /* Only enable hotplug handling once the fbdev is fully set up. */ |
1376 | dev_priv->enable_hotplug_processing = true; | |
5a79395b | 1377 | |
eb1f8e4f | 1378 | drm_kms_helper_poll_init(dev); |
87acb0a5 | 1379 | |
79e53945 JB |
1380 | return 0; |
1381 | ||
2c7111db CW |
1382 | cleanup_gem: |
1383 | mutex_lock(&dev->struct_mutex); | |
1384 | i915_gem_cleanup_ringbuffer(dev); | |
55d23285 | 1385 | i915_gem_context_fini(dev); |
2c7111db | 1386 | mutex_unlock(&dev->struct_mutex); |
bdf4fd7e | 1387 | WARN_ON(dev_priv->mm.aliasing_ppgtt); |
93bd8649 | 1388 | drm_mm_takedown(&dev_priv->gtt.base.mm); |
713028b3 | 1389 | cleanup_irq: |
52d7eced | 1390 | drm_irq_uninstall(dev); |
9797fbfb CW |
1391 | cleanup_gem_stolen: |
1392 | i915_gem_cleanup_stolen(dev); | |
5a79395b CW |
1393 | cleanup_vga_switcheroo: |
1394 | vga_switcheroo_unregister_client(dev->pdev); | |
1395 | cleanup_vga_client: | |
1396 | vga_client_register(dev->pdev, NULL, NULL, NULL); | |
79e53945 JB |
1397 | out: |
1398 | return ret; | |
1399 | } | |
1400 | ||
7c1c2871 DA |
1401 | int i915_master_create(struct drm_device *dev, struct drm_master *master) |
1402 | { | |
1403 | struct drm_i915_master_private *master_priv; | |
1404 | ||
9a298b2a | 1405 | master_priv = kzalloc(sizeof(*master_priv), GFP_KERNEL); |
7c1c2871 DA |
1406 | if (!master_priv) |
1407 | return -ENOMEM; | |
1408 | ||
1409 | master->driver_priv = master_priv; | |
1410 | return 0; | |
1411 | } | |
1412 | ||
1413 | void i915_master_destroy(struct drm_device *dev, struct drm_master *master) | |
1414 | { | |
1415 | struct drm_i915_master_private *master_priv = master->driver_priv; | |
1416 | ||
1417 | if (!master_priv) | |
1418 | return; | |
1419 | ||
9a298b2a | 1420 | kfree(master_priv); |
7c1c2871 DA |
1421 | |
1422 | master->driver_priv = NULL; | |
1423 | } | |
1424 | ||
243eaf38 | 1425 | #if IS_ENABLED(CONFIG_FB) |
e188719a DV |
1426 | static void i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv) |
1427 | { | |
1428 | struct apertures_struct *ap; | |
1429 | struct pci_dev *pdev = dev_priv->dev->pdev; | |
1430 | bool primary; | |
1431 | ||
1432 | ap = alloc_apertures(1); | |
1433 | if (!ap) | |
1434 | return; | |
1435 | ||
dabb7a91 | 1436 | ap->ranges[0].base = dev_priv->gtt.mappable_base; |
f64e2922 | 1437 | ap->ranges[0].size = dev_priv->gtt.mappable_end; |
93d18799 | 1438 | |
e188719a DV |
1439 | primary = |
1440 | pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW; | |
1441 | ||
1442 | remove_conflicting_framebuffers(ap, "inteldrmfb", primary); | |
1443 | ||
1444 | kfree(ap); | |
1445 | } | |
4520f53a DV |
1446 | #else |
1447 | static void i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv) | |
1448 | { | |
1449 | } | |
1450 | #endif | |
e188719a | 1451 | |
c96ea64e DV |
1452 | static void i915_dump_device_info(struct drm_i915_private *dev_priv) |
1453 | { | |
5c969aa7 | 1454 | const struct intel_device_info *info = &dev_priv->info; |
c96ea64e | 1455 | |
e2a5800a DL |
1456 | #define PRINT_S(name) "%s" |
1457 | #define SEP_EMPTY | |
79fc46df DL |
1458 | #define PRINT_FLAG(name) info->name ? #name "," : "" |
1459 | #define SEP_COMMA , | |
c96ea64e | 1460 | DRM_DEBUG_DRIVER("i915 device info: gen=%i, pciid=0x%04x flags=" |
e2a5800a | 1461 | DEV_INFO_FOR_EACH_FLAG(PRINT_S, SEP_EMPTY), |
c96ea64e DV |
1462 | info->gen, |
1463 | dev_priv->dev->pdev->device, | |
79fc46df | 1464 | DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_COMMA)); |
e2a5800a DL |
1465 | #undef PRINT_S |
1466 | #undef SEP_EMPTY | |
79fc46df DL |
1467 | #undef PRINT_FLAG |
1468 | #undef SEP_COMMA | |
c96ea64e DV |
1469 | } |
1470 | ||
22d3fd46 DL |
1471 | /* |
1472 | * Determine various intel_device_info fields at runtime. | |
1473 | * | |
1474 | * Use it when either: | |
1475 | * - it's judged too laborious to fill n static structures with the limit | |
1476 | * when a simple if statement does the job, | |
1477 | * - run-time checks (eg read fuse/strap registers) are needed. | |
658ac4c6 DL |
1478 | * |
1479 | * This function needs to be called: | |
1480 | * - after the MMIO has been setup as we are reading registers, | |
1481 | * - after the PCH has been detected, | |
1482 | * - before the first usage of the fields it can tweak. | |
22d3fd46 DL |
1483 | */ |
1484 | static void intel_device_info_runtime_init(struct drm_device *dev) | |
1485 | { | |
658ac4c6 | 1486 | struct drm_i915_private *dev_priv = dev->dev_private; |
22d3fd46 | 1487 | struct intel_device_info *info; |
d615a166 | 1488 | enum pipe pipe; |
22d3fd46 | 1489 | |
658ac4c6 | 1490 | info = (struct intel_device_info *)&dev_priv->info; |
22d3fd46 | 1491 | |
22d3fd46 | 1492 | if (IS_VALLEYVIEW(dev)) |
d615a166 DL |
1493 | for_each_pipe(pipe) |
1494 | info->num_sprites[pipe] = 2; | |
1495 | else | |
1496 | for_each_pipe(pipe) | |
1497 | info->num_sprites[pipe] = 1; | |
658ac4c6 | 1498 | |
a0bae57f DL |
1499 | if (i915.disable_display) { |
1500 | DRM_INFO("Display disabled (module parameter)\n"); | |
1501 | info->num_pipes = 0; | |
1502 | } else if (info->num_pipes > 0 && | |
1503 | (INTEL_INFO(dev)->gen == 7 || INTEL_INFO(dev)->gen == 8) && | |
1504 | !IS_VALLEYVIEW(dev)) { | |
658ac4c6 DL |
1505 | u32 fuse_strap = I915_READ(FUSE_STRAP); |
1506 | u32 sfuse_strap = I915_READ(SFUSE_STRAP); | |
1507 | ||
1508 | /* | |
1509 | * SFUSE_STRAP is supposed to have a bit signalling the display | |
1510 | * is fused off. Unfortunately it seems that, at least in | |
1511 | * certain cases, fused off display means that PCH display | |
1512 | * reads don't land anywhere. In that case, we read 0s. | |
1513 | * | |
1514 | * On CPT/PPT, we can detect this case as SFUSE_STRAP_FUSE_LOCK | |
1515 | * should be set when taking over after the firmware. | |
1516 | */ | |
1517 | if (fuse_strap & ILK_INTERNAL_DISPLAY_DISABLE || | |
1518 | sfuse_strap & SFUSE_STRAP_DISPLAY_DISABLED || | |
1519 | (dev_priv->pch_type == PCH_CPT && | |
1520 | !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) { | |
1521 | DRM_INFO("Display fused off, disabling\n"); | |
1522 | info->num_pipes = 0; | |
1523 | } | |
1524 | } | |
22d3fd46 DL |
1525 | } |
1526 | ||
79e53945 JB |
1527 | /** |
1528 | * i915_driver_load - setup chip and create an initial config | |
1529 | * @dev: DRM device | |
1530 | * @flags: startup flags | |
1531 | * | |
1532 | * The driver load routine has to do several things: | |
1533 | * - drive output discovery via intel_modeset_init() | |
1534 | * - initialize the memory manager | |
1535 | * - allocate initial config memory | |
1536 | * - setup the DRM framebuffer with the allocated memory | |
1537 | */ | |
84b1fd10 | 1538 | int i915_driver_load(struct drm_device *dev, unsigned long flags) |
22eae947 | 1539 | { |
ea059a1e | 1540 | struct drm_i915_private *dev_priv; |
5c969aa7 | 1541 | struct intel_device_info *info, *device_info; |
934d6086 | 1542 | int ret = 0, mmio_bar, mmio_size; |
9021f284 | 1543 | uint32_t aperture_size; |
fe669bf8 | 1544 | |
26394d92 DV |
1545 | info = (struct intel_device_info *) flags; |
1546 | ||
1547 | /* Refuse to load on gen6+ without kms enabled. */ | |
e147accb JN |
1548 | if (info->gen >= 6 && !drm_core_check_feature(dev, DRIVER_MODESET)) { |
1549 | DRM_INFO("Your hardware requires kernel modesetting (KMS)\n"); | |
1550 | DRM_INFO("See CONFIG_DRM_I915_KMS, nomodeset, and i915.modeset parameters\n"); | |
26394d92 | 1551 | return -ENODEV; |
e147accb | 1552 | } |
26394d92 | 1553 | |
24986ee0 DV |
1554 | /* UMS needs agp support. */ |
1555 | if (!drm_core_check_feature(dev, DRIVER_MODESET) && !dev->agp) | |
1556 | return -EINVAL; | |
1557 | ||
b14c5679 | 1558 | dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL); |
ba8bbcf6 JB |
1559 | if (dev_priv == NULL) |
1560 | return -ENOMEM; | |
1561 | ||
ba8bbcf6 | 1562 | dev->dev_private = (void *)dev_priv; |
673a394b | 1563 | dev_priv->dev = dev; |
5c969aa7 DL |
1564 | |
1565 | /* copy initial configuration to dev_priv->info */ | |
1566 | device_info = (struct intel_device_info *)&dev_priv->info; | |
1567 | *device_info = *info; | |
ba8bbcf6 | 1568 | |
7dcd2677 KK |
1569 | spin_lock_init(&dev_priv->irq_lock); |
1570 | spin_lock_init(&dev_priv->gpu_error.lock); | |
58c68779 | 1571 | spin_lock_init(&dev_priv->backlight_lock); |
907b28c5 | 1572 | spin_lock_init(&dev_priv->uncore.lock); |
c20e8355 | 1573 | spin_lock_init(&dev_priv->mm.object_stat_lock); |
7dcd2677 | 1574 | mutex_init(&dev_priv->dpio_lock); |
7dcd2677 KK |
1575 | mutex_init(&dev_priv->modeset_restore_lock); |
1576 | ||
f742a552 | 1577 | intel_pm_setup(dev); |
c67a470b | 1578 | |
07144428 DL |
1579 | intel_display_crc_init(dev); |
1580 | ||
c96ea64e DV |
1581 | i915_dump_device_info(dev_priv); |
1582 | ||
ed1c9e2c PZ |
1583 | /* Not all pre-production machines fall into this category, only the |
1584 | * very first ones. Almost everything should work, except for maybe | |
1585 | * suspend/resume. And we don't implement workarounds that affect only | |
1586 | * pre-production machines. */ | |
1587 | if (IS_HSW_EARLY_SDV(dev)) | |
1588 | DRM_INFO("This is an early pre-production Haswell machine. " | |
1589 | "It may not be fully functional.\n"); | |
1590 | ||
ec2a4c3f DA |
1591 | if (i915_get_bridge_dev(dev)) { |
1592 | ret = -EIO; | |
1593 | goto free_priv; | |
1594 | } | |
1595 | ||
1e1bd0fd BW |
1596 | mmio_bar = IS_GEN2(dev) ? 1 : 0; |
1597 | /* Before gen4, the registers and the GTT are behind different BARs. | |
1598 | * However, from gen4 onwards, the registers and the GTT are shared | |
1599 | * in the same BAR, so we want to restrict this ioremap from | |
1600 | * clobbering the GTT which we want ioremap_wc instead. Fortunately, | |
1601 | * the register BAR remains the same size for all the earlier | |
1602 | * generations up to Ironlake. | |
1603 | */ | |
1604 | if (info->gen < 5) | |
1605 | mmio_size = 512*1024; | |
1606 | else | |
1607 | mmio_size = 2*1024*1024; | |
1608 | ||
1609 | dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, mmio_size); | |
1610 | if (!dev_priv->regs) { | |
1611 | DRM_ERROR("failed to map registers\n"); | |
1612 | ret = -EIO; | |
1613 | goto put_bridge; | |
1614 | } | |
1615 | ||
c3d685a7 BW |
1616 | /* This must be called before any calls to HAS_PCH_* */ |
1617 | intel_detect_pch(dev); | |
1618 | ||
1619 | intel_uncore_init(dev); | |
1620 | ||
e76e9aeb BW |
1621 | ret = i915_gem_gtt_init(dev); |
1622 | if (ret) | |
cbb47d17 | 1623 | goto out_regs; |
e188719a | 1624 | |
1623392a CW |
1625 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
1626 | i915_kick_out_firmware_fb(dev_priv); | |
e188719a | 1627 | |
466e69b8 DA |
1628 | pci_set_master(dev->pdev); |
1629 | ||
9f82d238 DV |
1630 | /* overlay on gen2 is broken and can't address above 1G */ |
1631 | if (IS_GEN2(dev)) | |
1632 | dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30)); | |
1633 | ||
6927faf3 JN |
1634 | /* 965GM sometimes incorrectly writes to hardware status page (HWS) |
1635 | * using 32bit addressing, overwriting memory if HWS is located | |
1636 | * above 4GB. | |
1637 | * | |
1638 | * The documentation also mentions an issue with undefined | |
1639 | * behaviour if any general state is accessed within a page above 4GB, | |
1640 | * which also needs to be handled carefully. | |
1641 | */ | |
1642 | if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) | |
1643 | dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(32)); | |
1644 | ||
93d18799 | 1645 | aperture_size = dev_priv->gtt.mappable_end; |
71e9339c | 1646 | |
5d4545ae BW |
1647 | dev_priv->gtt.mappable = |
1648 | io_mapping_create_wc(dev_priv->gtt.mappable_base, | |
dd2757f8 | 1649 | aperture_size); |
5d4545ae | 1650 | if (dev_priv->gtt.mappable == NULL) { |
6644107d | 1651 | ret = -EIO; |
cbb47d17 | 1652 | goto out_gtt; |
6644107d VP |
1653 | } |
1654 | ||
911bdf0a BW |
1655 | dev_priv->gtt.mtrr = arch_phys_wc_add(dev_priv->gtt.mappable_base, |
1656 | aperture_size); | |
19966754 | 1657 | |
e642abbf CW |
1658 | /* The i915 workqueue is primarily used for batched retirement of |
1659 | * requests (and thus managing bo) once the task has been completed | |
1660 | * by the GPU. i915_gem_retire_requests() is called directly when we | |
1661 | * need high-priority retirement, such as waiting for an explicit | |
1662 | * bo. | |
1663 | * | |
1664 | * It is also used for periodic low-priority events, such as | |
df9c2042 | 1665 | * idle-timers and recording error state. |
e642abbf CW |
1666 | * |
1667 | * All tasks on the workqueue are expected to acquire the dev mutex | |
1668 | * so there is no point in running more than one instance of the | |
53621860 | 1669 | * workqueue at any time. Use an ordered one. |
e642abbf | 1670 | */ |
53621860 | 1671 | dev_priv->wq = alloc_ordered_workqueue("i915", 0); |
9c9fe1f8 EA |
1672 | if (dev_priv->wq == NULL) { |
1673 | DRM_ERROR("Failed to create our workqueue.\n"); | |
1674 | ret = -ENOMEM; | |
a7b85d2a | 1675 | goto out_mtrrfree; |
9c9fe1f8 EA |
1676 | } |
1677 | ||
f71d4af4 | 1678 | intel_irq_init(dev); |
78511f2a | 1679 | intel_uncore_sanitize(dev); |
9880b7a5 | 1680 | |
c4804411 ZW |
1681 | /* Try to make sure MCHBAR is enabled before poking at it */ |
1682 | intel_setup_mchbar(dev); | |
f899fc64 | 1683 | intel_setup_gmbus(dev); |
44834a67 | 1684 | intel_opregion_setup(dev); |
c4804411 | 1685 | |
6d139a87 BF |
1686 | intel_setup_bios(dev); |
1687 | ||
673a394b EA |
1688 | i915_gem_load(dev); |
1689 | ||
ed4cb414 EA |
1690 | /* On the 945G/GM, the chipset reports the MSI capability on the |
1691 | * integrated graphics even though the support isn't actually there | |
1692 | * according to the published specs. It doesn't appear to function | |
1693 | * correctly in testing on 945G. | |
1694 | * This may be a side effect of MSI having been made available for PEG | |
1695 | * and the registers being closely associated. | |
d1ed629f KP |
1696 | * |
1697 | * According to chipset errata, on the 965GM, MSI interrupts may | |
b60678a7 KP |
1698 | * be lost or delayed, but we use them anyways to avoid |
1699 | * stuck interrupts on some machines. | |
ed4cb414 | 1700 | */ |
b60678a7 | 1701 | if (!IS_I945G(dev) && !IS_I945GM(dev)) |
d3e74d02 | 1702 | pci_enable_msi(dev->pdev); |
ed4cb414 | 1703 | |
22d3fd46 | 1704 | intel_device_info_runtime_init(dev); |
7f1f3851 | 1705 | |
e3c74757 BW |
1706 | if (INTEL_INFO(dev)->num_pipes) { |
1707 | ret = drm_vblank_init(dev, INTEL_INFO(dev)->num_pipes); | |
1708 | if (ret) | |
1709 | goto out_gem_unload; | |
1710 | } | |
52440211 | 1711 | |
da7e29bd | 1712 | intel_power_domains_init(dev_priv); |
a38911a3 | 1713 | |
79e53945 | 1714 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
53984635 | 1715 | ret = i915_load_modeset_init(dev); |
79e53945 JB |
1716 | if (ret < 0) { |
1717 | DRM_ERROR("failed to init modeset\n"); | |
cbb47d17 | 1718 | goto out_power_well; |
79e53945 | 1719 | } |
db1b76ca DV |
1720 | } else { |
1721 | /* Start out suspended in ums mode. */ | |
1722 | dev_priv->ums.mm_suspended = 1; | |
79e53945 JB |
1723 | } |
1724 | ||
0136db58 BW |
1725 | i915_setup_sysfs(dev); |
1726 | ||
e3c74757 BW |
1727 | if (INTEL_INFO(dev)->num_pipes) { |
1728 | /* Must be done after probing outputs */ | |
1729 | intel_opregion_init(dev); | |
8e5c2b77 | 1730 | acpi_video_register(); |
e3c74757 | 1731 | } |
74a365b3 | 1732 | |
eb48eb00 DV |
1733 | if (IS_GEN5(dev)) |
1734 | intel_gpu_ips_init(dev_priv); | |
63ee41d7 | 1735 | |
8a187455 PZ |
1736 | intel_init_runtime_pm(dev_priv); |
1737 | ||
79e53945 JB |
1738 | return 0; |
1739 | ||
cbb47d17 | 1740 | out_power_well: |
da7e29bd | 1741 | intel_power_domains_remove(dev_priv); |
cbb47d17 | 1742 | drm_vblank_cleanup(dev); |
56e2ea34 | 1743 | out_gem_unload: |
4bdc7293 ID |
1744 | WARN_ON(unregister_oom_notifier(&dev_priv->mm.oom_notifier)); |
1745 | unregister_shrinker(&dev_priv->mm.shrinker); | |
a7b85d2a | 1746 | |
56e2ea34 CW |
1747 | if (dev->pdev->msi_enabled) |
1748 | pci_disable_msi(dev->pdev); | |
1749 | ||
1750 | intel_teardown_gmbus(dev); | |
1751 | intel_teardown_mchbar(dev); | |
22accca0 | 1752 | pm_qos_remove_request(&dev_priv->pm_qos); |
9c9fe1f8 | 1753 | destroy_workqueue(dev_priv->wq); |
a7b85d2a | 1754 | out_mtrrfree: |
911bdf0a | 1755 | arch_phys_wc_del(dev_priv->gtt.mtrr); |
5d4545ae | 1756 | io_mapping_free(dev_priv->gtt.mappable); |
cbb47d17 CW |
1757 | out_gtt: |
1758 | list_del(&dev_priv->gtt.base.global_link); | |
1759 | drm_mm_takedown(&dev_priv->gtt.base.mm); | |
853ba5d2 | 1760 | dev_priv->gtt.base.cleanup(&dev_priv->gtt.base); |
cbb47d17 | 1761 | out_regs: |
c3d685a7 | 1762 | intel_uncore_fini(dev); |
6dda569f | 1763 | pci_iounmap(dev->pdev, dev_priv->regs); |
ec2a4c3f DA |
1764 | put_bridge: |
1765 | pci_dev_put(dev_priv->bridge_dev); | |
79e53945 | 1766 | free_priv: |
cbb47d17 CW |
1767 | if (dev_priv->slab) |
1768 | kmem_cache_destroy(dev_priv->slab); | |
9a298b2a | 1769 | kfree(dev_priv); |
ba8bbcf6 JB |
1770 | return ret; |
1771 | } | |
1772 | ||
1773 | int i915_driver_unload(struct drm_device *dev) | |
1774 | { | |
1775 | struct drm_i915_private *dev_priv = dev->dev_private; | |
c911fc1c | 1776 | int ret; |
ba8bbcf6 | 1777 | |
ce58c32b CW |
1778 | ret = i915_gem_suspend(dev); |
1779 | if (ret) { | |
1780 | DRM_ERROR("failed to idle hardware: %d\n", ret); | |
1781 | return ret; | |
1782 | } | |
1783 | ||
8a187455 PZ |
1784 | intel_fini_runtime_pm(dev_priv); |
1785 | ||
eb48eb00 | 1786 | intel_gpu_ips_teardown(); |
7648fa99 | 1787 | |
1c2256df ID |
1788 | /* The i915.ko module is still not prepared to be loaded when |
1789 | * the power well is not enabled, so just enable it in case | |
1790 | * we're going to unload/reload. */ | |
da7e29bd ID |
1791 | intel_display_set_init_power(dev_priv, true); |
1792 | intel_power_domains_remove(dev_priv); | |
a38911a3 | 1793 | |
0136db58 BW |
1794 | i915_teardown_sysfs(dev); |
1795 | ||
4bdc7293 ID |
1796 | WARN_ON(unregister_oom_notifier(&dev_priv->mm.oom_notifier)); |
1797 | unregister_shrinker(&dev_priv->mm.shrinker); | |
17250b71 | 1798 | |
5d4545ae | 1799 | io_mapping_free(dev_priv->gtt.mappable); |
911bdf0a | 1800 | arch_phys_wc_del(dev_priv->gtt.mtrr); |
ab657db1 | 1801 | |
44834a67 CW |
1802 | acpi_video_unregister(); |
1803 | ||
79e53945 | 1804 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
7b4f3990 | 1805 | intel_fbdev_fini(dev); |
3d8620cc | 1806 | intel_modeset_cleanup(dev); |
073f34d9 | 1807 | cancel_work_sync(&dev_priv->console_resume_work); |
3d8620cc | 1808 | |
6363ee6f ZY |
1809 | /* |
1810 | * free the memory space allocated for the child device | |
1811 | * config parsed from VBT | |
1812 | */ | |
41aa3448 RV |
1813 | if (dev_priv->vbt.child_dev && dev_priv->vbt.child_dev_num) { |
1814 | kfree(dev_priv->vbt.child_dev); | |
1815 | dev_priv->vbt.child_dev = NULL; | |
1816 | dev_priv->vbt.child_dev_num = 0; | |
6363ee6f | 1817 | } |
6c0d9350 | 1818 | |
6a9ee8af | 1819 | vga_switcheroo_unregister_client(dev->pdev); |
28d52043 | 1820 | vga_client_register(dev->pdev, NULL, NULL, NULL); |
79e53945 JB |
1821 | } |
1822 | ||
a8b4899e | 1823 | /* Free error state after interrupts are fully disabled. */ |
99584db3 DV |
1824 | del_timer_sync(&dev_priv->gpu_error.hangcheck_timer); |
1825 | cancel_work_sync(&dev_priv->gpu_error.work); | |
a8b4899e | 1826 | i915_destroy_error_state(dev); |
bc0c7f14 | 1827 | |
ed4cb414 EA |
1828 | if (dev->pdev->msi_enabled) |
1829 | pci_disable_msi(dev->pdev); | |
1830 | ||
44834a67 | 1831 | intel_opregion_fini(dev); |
8ee1c3db | 1832 | |
79e53945 | 1833 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
67e77c5a DV |
1834 | /* Flush any outstanding unpin_work. */ |
1835 | flush_workqueue(dev_priv->wq); | |
1836 | ||
79e53945 | 1837 | mutex_lock(&dev->struct_mutex); |
ecbec53b | 1838 | i915_gem_free_all_phys_object(dev); |
79e53945 | 1839 | i915_gem_cleanup_ringbuffer(dev); |
55a66628 | 1840 | i915_gem_context_fini(dev); |
bdf4fd7e | 1841 | WARN_ON(dev_priv->mm.aliasing_ppgtt); |
79e53945 | 1842 | mutex_unlock(&dev->struct_mutex); |
9797fbfb | 1843 | i915_gem_cleanup_stolen(dev); |
c2873e96 KP |
1844 | |
1845 | if (!I915_NEED_GFX_HWS(dev)) | |
1846 | i915_free_hws(dev); | |
79e53945 JB |
1847 | } |
1848 | ||
a7bbbd63 BW |
1849 | list_del(&dev_priv->gtt.base.global_link); |
1850 | WARN_ON(!list_empty(&dev_priv->vm_list)); | |
701394cc | 1851 | |
cbb47d17 CW |
1852 | drm_vblank_cleanup(dev); |
1853 | ||
f899fc64 | 1854 | intel_teardown_gmbus(dev); |
c4804411 ZW |
1855 | intel_teardown_mchbar(dev); |
1856 | ||
bc0c7f14 | 1857 | destroy_workqueue(dev_priv->wq); |
9ee32fea | 1858 | pm_qos_remove_request(&dev_priv->pm_qos); |
bc0c7f14 | 1859 | |
853ba5d2 | 1860 | dev_priv->gtt.base.cleanup(&dev_priv->gtt.base); |
6640aab6 | 1861 | |
aec347ab CW |
1862 | intel_uncore_fini(dev); |
1863 | if (dev_priv->regs != NULL) | |
1864 | pci_iounmap(dev->pdev, dev_priv->regs); | |
1865 | ||
42dcedd4 CW |
1866 | if (dev_priv->slab) |
1867 | kmem_cache_destroy(dev_priv->slab); | |
bc0c7f14 | 1868 | |
ec2a4c3f | 1869 | pci_dev_put(dev_priv->bridge_dev); |
2206e6a1 | 1870 | kfree(dev_priv); |
ba8bbcf6 | 1871 | |
22eae947 DA |
1872 | return 0; |
1873 | } | |
1874 | ||
f787a5f5 | 1875 | int i915_driver_open(struct drm_device *dev, struct drm_file *file) |
673a394b | 1876 | { |
b29c19b6 | 1877 | int ret; |
673a394b | 1878 | |
b29c19b6 CW |
1879 | ret = i915_gem_open(dev, file); |
1880 | if (ret) | |
1881 | return ret; | |
254f965c | 1882 | |
673a394b EA |
1883 | return 0; |
1884 | } | |
1885 | ||
79e53945 JB |
1886 | /** |
1887 | * i915_driver_lastclose - clean up after all DRM clients have exited | |
1888 | * @dev: DRM device | |
1889 | * | |
1890 | * Take care of cleaning up after all DRM clients have exited. In the | |
1891 | * mode setting case, we want to restore the kernel's initial mode (just | |
1892 | * in case the last client left us in a bad state). | |
1893 | * | |
9021f284 | 1894 | * Additionally, in the non-mode setting case, we'll tear down the GTT |
79e53945 JB |
1895 | * and DMA structures, since the kernel won't be using them, and clea |
1896 | * up any GEM state. | |
1897 | */ | |
84b1fd10 | 1898 | void i915_driver_lastclose(struct drm_device * dev) |
1da177e4 | 1899 | { |
4c8a4be9 | 1900 | struct drm_i915_private *dev_priv = dev->dev_private; |
ba8bbcf6 | 1901 | |
e8aeaee7 DV |
1902 | /* On gen6+ we refuse to init without kms enabled, but then the drm core |
1903 | * goes right around and calls lastclose. Check for this and don't clean | |
1904 | * up anything. */ | |
1905 | if (!dev_priv) | |
1906 | return; | |
1907 | ||
1908 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { | |
0632fef6 | 1909 | intel_fbdev_restore_mode(dev); |
6a9ee8af | 1910 | vga_switcheroo_process_delayed_switch(); |
144a75fa | 1911 | return; |
79e53945 | 1912 | } |
144a75fa | 1913 | |
673a394b EA |
1914 | i915_gem_lastclose(dev); |
1915 | ||
b5e89ed5 | 1916 | i915_dma_cleanup(dev); |
1da177e4 LT |
1917 | } |
1918 | ||
6c340eac | 1919 | void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv) |
1da177e4 | 1920 | { |
0d1430a3 | 1921 | mutex_lock(&dev->struct_mutex); |
254f965c | 1922 | i915_gem_context_close(dev, file_priv); |
b962442e | 1923 | i915_gem_release(dev, file_priv); |
0d1430a3 | 1924 | mutex_unlock(&dev->struct_mutex); |
1da177e4 LT |
1925 | } |
1926 | ||
f787a5f5 | 1927 | void i915_driver_postclose(struct drm_device *dev, struct drm_file *file) |
673a394b | 1928 | { |
f787a5f5 | 1929 | struct drm_i915_file_private *file_priv = file->driver_priv; |
673a394b | 1930 | |
a8ebba75 ZY |
1931 | if (file_priv && file_priv->bsd_ring) |
1932 | file_priv->bsd_ring = NULL; | |
f787a5f5 | 1933 | kfree(file_priv); |
673a394b EA |
1934 | } |
1935 | ||
baa70943 | 1936 | const struct drm_ioctl_desc i915_ioctls[] = { |
1b2f1489 DA |
1937 | DRM_IOCTL_DEF_DRV(I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
1938 | DRM_IOCTL_DEF_DRV(I915_FLUSH, i915_flush_ioctl, DRM_AUTH), | |
1939 | DRM_IOCTL_DEF_DRV(I915_FLIP, i915_flip_bufs, DRM_AUTH), | |
1940 | DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH), | |
1941 | DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH), | |
1942 | DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH), | |
10ba5012 | 1943 | DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH|DRM_RENDER_ALLOW), |
1b2f1489 | 1944 | DRM_IOCTL_DEF_DRV(I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
b2c606fe DV |
1945 | DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH), |
1946 | DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH), | |
1947 | DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
1b2f1489 | 1948 | DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH), |
b2c606fe | 1949 | DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
d1c1edbc | 1950 | DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
1b2f1489 DA |
1951 | DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, i915_vblank_pipe_get, DRM_AUTH), |
1952 | DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH), | |
1953 | DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
1954 | DRM_IOCTL_DEF_DRV(I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED), | |
1955 | DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH|DRM_UNLOCKED), | |
10ba5012 | 1956 | DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), |
1b2f1489 DA |
1957 | DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED), |
1958 | DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED), | |
10ba5012 KH |
1959 | DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), |
1960 | DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
1961 | DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
1962 | DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
1b2f1489 DA |
1963 | DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED), |
1964 | DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED), | |
10ba5012 KH |
1965 | DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), |
1966 | DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
1967 | DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
1968 | DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
1969 | DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
1970 | DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
1971 | DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
1972 | DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
1973 | DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
1974 | DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
1b2f1489 | 1975 | DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED), |
10ba5012 | 1976 | DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), |
1b2f1489 DA |
1977 | DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED), |
1978 | DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED), | |
8ea30864 JB |
1979 | DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED), |
1980 | DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, intel_sprite_get_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED), | |
10ba5012 KH |
1981 | DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), |
1982 | DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
1983 | DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
1984 | DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
b6359918 | 1985 | DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_get_reset_stats_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), |
5cc9ed4b | 1986 | DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), |
c94f7029 DA |
1987 | }; |
1988 | ||
1989 | int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls); | |
cda17380 | 1990 | |
9021f284 DV |
1991 | /* |
1992 | * This is really ugly: Because old userspace abused the linux agp interface to | |
1993 | * manage the gtt, we need to claim that all intel devices are agp. For | |
1994 | * otherwise the drm core refuses to initialize the agp support code. | |
cda17380 | 1995 | */ |
84b1fd10 | 1996 | int i915_driver_device_is_agp(struct drm_device * dev) |
cda17380 DA |
1997 | { |
1998 | return 1; | |
1999 | } |