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drm/i915: Turn HAS_FPGA_DBG_UNCLAIMED into a device_info flag
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_drv.c
CommitLineData
1da177e4
LT		 1/* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
2 */
0d6aa60b 3/*
bc54fd1a 4 *
1da177e4
LT		 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
bc54fd1a
DA		 7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
0d6aa60b 28 */
1da177e4 29
5669fcac 30#include <linux/device.h>
760285e7
DH		 31#include <drm/drmP.h>
32#include <drm/i915_drm.h>
1da177e4 33#include "i915_drv.h"
990bbdad 34#include "i915_trace.h"
f49f0586 35#include "intel_drv.h"
1da177e4 36
79e53945 37#include <linux/console.h>
e0cd3608 38#include <linux/module.h>
760285e7 39#include <drm/drm_crtc_helper.h>
79e53945 40
a35d9d3c 41static int i915_modeset __read_mostly = -1;
79e53945 42module_param_named(modeset, i915_modeset, int, 0400);
6e96e775
BW		 43MODULE_PARM_DESC(modeset,
44 "Use kernel modesetting [KMS] (0=DRM_I915_KMS from .config, "
45 "1=on, -1=force vga console preference [default])");
79e53945 46
a35d9d3c 47unsigned int i915_fbpercrtc __always_unused = 0;
79e53945 48module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400);
1da177e4 49
a726915c 50int i915_panel_ignore_lid __read_mostly = 1;
fca87409 51module_param_named(panel_ignore_lid, i915_panel_ignore_lid, int, 0600);
6e96e775 52MODULE_PARM_DESC(panel_ignore_lid,
a726915c
DV		 53 "Override lid status (0=autodetect, 1=autodetect disabled [default], "
54 "-1=force lid closed, -2=force lid open)");
fca87409 55
a35d9d3c 56unsigned int i915_powersave __read_mostly = 1;
0aa99277 57module_param_named(powersave, i915_powersave, int, 0600);
6e96e775
BW		 58MODULE_PARM_DESC(powersave,
59 "Enable powersavings, fbc, downclocking, etc. (default: true)");
652c393a 60
f45b5557 61int i915_semaphores __read_mostly = -1;
a1656b90 62module_param_named(semaphores, i915_semaphores, int, 0600);
6e96e775 63MODULE_PARM_DESC(semaphores,
f45b5557 64 "Use semaphores for inter-ring sync (default: -1 (use per-chip defaults))");
a1656b90 65
c0f372b3 66int i915_enable_rc6 __read_mostly = -1;
f57f9c16 67module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0400);
6e96e775 68MODULE_PARM_DESC(i915_enable_rc6,
83b7f9ac
ED		 69 "Enable power-saving render C-state 6. "
70 "Different stages can be selected via bitmask values "
71 "(0 = disable; 1 = enable rc6; 2 = enable deep rc6; 4 = enable deepest rc6). "
72 "For example, 3 would enable rc6 and deep rc6, and 7 would enable everything. "
73 "default: -1 (use per-chip default)");
ac668088 74
4415e63b 75int i915_enable_fbc __read_mostly = -1;
c1a9f047 76module_param_named(i915_enable_fbc, i915_enable_fbc, int, 0600);
6e96e775
BW		 77MODULE_PARM_DESC(i915_enable_fbc,
78 "Enable frame buffer compression for power savings "
cd0de039 79 "(default: -1 (use per-chip default))");
c1a9f047 80
a35d9d3c 81unsigned int i915_lvds_downclock __read_mostly = 0;
33814341 82module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400);
6e96e775
BW		 83MODULE_PARM_DESC(lvds_downclock,
84 "Use panel (LVDS/eDP) downclocking for power savings "
85 "(default: false)");
33814341 86
121d527a
TI		 87int i915_lvds_channel_mode __read_mostly;
88module_param_named(lvds_channel_mode, i915_lvds_channel_mode, int, 0600);
89MODULE_PARM_DESC(lvds_channel_mode,
90 "Specify LVDS channel mode "
91 "(0=probe BIOS [default], 1=single-channel, 2=dual-channel)");
92
4415e63b 93int i915_panel_use_ssc __read_mostly = -1;
a7615030 94module_param_named(lvds_use_ssc, i915_panel_use_ssc, int, 0600);
6e96e775
BW		 95MODULE_PARM_DESC(lvds_use_ssc,
96 "Use Spread Spectrum Clock with panels [LVDS/eDP] "
72bbe58c 97 "(default: auto from VBT)");
a7615030 98
a35d9d3c 99int i915_vbt_sdvo_panel_type __read_mostly = -1;
5a1e5b6c 100module_param_named(vbt_sdvo_panel_type, i915_vbt_sdvo_panel_type, int, 0600);
6e96e775 101MODULE_PARM_DESC(vbt_sdvo_panel_type,
c10e408a
MF		 102 "Override/Ignore selection of SDVO panel mode in the VBT "
103 "(-2=ignore, -1=auto [default], index in VBT BIOS table)");
5a1e5b6c 104
a35d9d3c 105static bool i915_try_reset __read_mostly = true;
d78cb50b 106module_param_named(reset, i915_try_reset, bool, 0600);
6e96e775 107MODULE_PARM_DESC(reset, "Attempt GPU resets (default: true)");
d78cb50b 108
a35d9d3c 109bool i915_enable_hangcheck __read_mostly = true;
3e0dc6b0 110module_param_named(enable_hangcheck, i915_enable_hangcheck, bool, 0644);
6e96e775
BW		 111MODULE_PARM_DESC(enable_hangcheck,
112 "Periodically check GPU activity for detecting hangs. "
113 "WARNING: Disabling this can cause system wide hangs. "
114 "(default: true)");
3e0dc6b0 115
650dc07e
DV		 116int i915_enable_ppgtt __read_mostly = -1;
117module_param_named(i915_enable_ppgtt, i915_enable_ppgtt, int, 0600);
e21af88d
DV		 118MODULE_PARM_DESC(i915_enable_ppgtt,
119 "Enable PPGTT (default: true)");
120
0a3af268
RV		 121unsigned int i915_preliminary_hw_support __read_mostly = 0;
122module_param_named(preliminary_hw_support, i915_preliminary_hw_support, int, 0600);
123MODULE_PARM_DESC(preliminary_hw_support,
c4aaf350 124 "Enable preliminary hardware support. (default: false)");
0a3af268 125
2124b72e
PZ		 126int i915_disable_power_well __read_mostly = 0;
127module_param_named(disable_power_well, i915_disable_power_well, int, 0600);
128MODULE_PARM_DESC(disable_power_well,
129 "Disable the power well when possible (default: false)");
130
112b715e 131static struct drm_driver driver;
1f7a6e37 132extern int intel_agp_enabled;
112b715e 133
cfdf1fa2 134#define INTEL_VGA_DEVICE(id, info) { \
80a2901d 135 .class = PCI_BASE_CLASS_DISPLAY << 16, \
934f992c 136 .class_mask = 0xff0000, \
49ae35f2
KH		 137 .vendor = 0x8086, \
138 .device = id, \
139 .subvendor = PCI_ANY_ID, \
140 .subdevice = PCI_ANY_ID, \
cfdf1fa2
KH		 141 .driver_data = (unsigned long) info }
142
999bcdea
BW		 143#define INTEL_QUANTA_VGA_DEVICE(info) { \
144 .class = PCI_BASE_CLASS_DISPLAY << 16, \
145 .class_mask = 0xff0000, \
146 .vendor = 0x8086, \
147 .device = 0x16a, \
148 .subvendor = 0x152d, \
149 .subdevice = 0x8990, \
150 .driver_data = (unsigned long) info }
151
152
9a7e8492 153static const struct intel_device_info intel_i830_info = {
7eb552ae 154 .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2,
31578148 155 .has_overlay = 1, .overlay_needs_physical = 1,
cfdf1fa2
KH		 156};
157
9a7e8492 158static const struct intel_device_info intel_845g_info = {
7eb552ae 159 .gen = 2, .num_pipes = 1,
31578148 160 .has_overlay = 1, .overlay_needs_physical = 1,
cfdf1fa2
KH		 161};
162
9a7e8492 163static const struct intel_device_info intel_i85x_info = {
7eb552ae 164 .gen = 2, .is_i85x = 1, .is_mobile = 1, .num_pipes = 2,
5ce8ba7c 165 .cursor_needs_physical = 1,
31578148 166 .has_overlay = 1, .overlay_needs_physical = 1,
cfdf1fa2
KH		 167};
168
9a7e8492 169static const struct intel_device_info intel_i865g_info = {
7eb552ae 170 .gen = 2, .num_pipes = 1,
31578148 171 .has_overlay = 1, .overlay_needs_physical = 1,
cfdf1fa2
KH		 172};
173
9a7e8492 174static const struct intel_device_info intel_i915g_info = {
7eb552ae 175 .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2,
31578148 176 .has_overlay = 1, .overlay_needs_physical = 1,
cfdf1fa2 177};
9a7e8492 178static const struct intel_device_info intel_i915gm_info = {
7eb552ae 179 .gen = 3, .is_mobile = 1, .num_pipes = 2,
b295d1b6 180 .cursor_needs_physical = 1,
31578148 181 .has_overlay = 1, .overlay_needs_physical = 1,
a6c45cf0 182 .supports_tv = 1,
cfdf1fa2 183};
9a7e8492 184static const struct intel_device_info intel_i945g_info = {
7eb552ae 185 .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2,
31578148 186 .has_overlay = 1, .overlay_needs_physical = 1,
cfdf1fa2 187};
9a7e8492 188static const struct intel_device_info intel_i945gm_info = {
7eb552ae 189 .gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2,
b295d1b6 190 .has_hotplug = 1, .cursor_needs_physical = 1,
31578148 191 .has_overlay = 1, .overlay_needs_physical = 1,
a6c45cf0 192 .supports_tv = 1,
cfdf1fa2
KH		 193};
194
9a7e8492 195static const struct intel_device_info intel_i965g_info = {
7eb552ae 196 .gen = 4, .is_broadwater = 1, .num_pipes = 2,
c96c3a8c 197 .has_hotplug = 1,
31578148 198 .has_overlay = 1,
cfdf1fa2
KH		 199};
200
9a7e8492 201static const struct intel_device_info intel_i965gm_info = {
7eb552ae 202 .gen = 4, .is_crestline = 1, .num_pipes = 2,
e3c4e5dd 203 .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
31578148 204 .has_overlay = 1,
a6c45cf0 205 .supports_tv = 1,
cfdf1fa2
KH		 206};
207
9a7e8492 208static const struct intel_device_info intel_g33_info = {
7eb552ae 209 .gen = 3, .is_g33 = 1, .num_pipes = 2,
c96c3a8c 210 .need_gfx_hws = 1, .has_hotplug = 1,
31578148 211 .has_overlay = 1,
cfdf1fa2
KH		 212};
213
9a7e8492 214static const struct intel_device_info intel_g45_info = {
7eb552ae 215 .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2,
c96c3a8c 216 .has_pipe_cxsr = 1, .has_hotplug = 1,
92f49d9c 217 .has_bsd_ring = 1,
cfdf1fa2
KH		 218};
219
9a7e8492 220static const struct intel_device_info intel_gm45_info = {
7eb552ae 221 .gen = 4, .is_g4x = 1, .num_pipes = 2,
e3c4e5dd 222 .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
c96c3a8c 223 .has_pipe_cxsr = 1, .has_hotplug = 1,
a6c45cf0 224 .supports_tv = 1,
92f49d9c 225 .has_bsd_ring = 1,
cfdf1fa2
KH		 226};
227
9a7e8492 228static const struct intel_device_info intel_pineview_info = {
7eb552ae 229 .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2,
c96c3a8c 230 .need_gfx_hws = 1, .has_hotplug = 1,
31578148 231 .has_overlay = 1,
cfdf1fa2
KH		 232};
233
9a7e8492 234static const struct intel_device_info intel_ironlake_d_info = {
7eb552ae 235 .gen = 5, .num_pipes = 2,
5a117db7 236 .need_gfx_hws = 1, .has_hotplug = 1,
92f49d9c 237 .has_bsd_ring = 1,
cfdf1fa2
KH		 238};
239
9a7e8492 240static const struct intel_device_info intel_ironlake_m_info = {
7eb552ae 241 .gen = 5, .is_mobile = 1, .num_pipes = 2,
e3c4e5dd 242 .need_gfx_hws = 1, .has_hotplug = 1,
c1a9f047 243 .has_fbc = 1,
92f49d9c 244 .has_bsd_ring = 1,
cfdf1fa2
KH		 245};
246
9a7e8492 247static const struct intel_device_info intel_sandybridge_d_info = {
7eb552ae 248 .gen = 6, .num_pipes = 2,
c96c3a8c 249 .need_gfx_hws = 1, .has_hotplug = 1,
881f47b6 250 .has_bsd_ring = 1,
549f7365 251 .has_blt_ring = 1,
3d29b842 252 .has_llc = 1,
b7884eb4 253 .has_force_wake = 1,
f6e450a6
EA		 254};
255
9a7e8492 256static const struct intel_device_info intel_sandybridge_m_info = {
7eb552ae 257 .gen = 6, .is_mobile = 1, .num_pipes = 2,
c96c3a8c 258 .need_gfx_hws = 1, .has_hotplug = 1,
9c04f015 259 .has_fbc = 1,
881f47b6 260 .has_bsd_ring = 1,
549f7365 261 .has_blt_ring = 1,
3d29b842 262 .has_llc = 1,
b7884eb4 263 .has_force_wake = 1,
a13e4093
EA		 264};
265
219f4fdb
BW		 266#define GEN7_FEATURES \
267 .gen = 7, .num_pipes = 3, \
268 .need_gfx_hws = 1, .has_hotplug = 1, \
269 .has_bsd_ring = 1, \
270 .has_blt_ring = 1, \
271 .has_llc = 1, \
272 .has_force_wake = 1
273
c76b615c 274static const struct intel_device_info intel_ivybridge_d_info = {
219f4fdb
BW		 275 GEN7_FEATURES,
276 .is_ivybridge = 1,
c76b615c
JB		 277};
278
279static const struct intel_device_info intel_ivybridge_m_info = {
219f4fdb
BW		 280 GEN7_FEATURES,
281 .is_ivybridge = 1,
282 .is_mobile = 1,
c76b615c
JB		 283};
284
999bcdea
BW		 285static const struct intel_device_info intel_ivybridge_q_info = {
286 GEN7_FEATURES,
287 .is_ivybridge = 1,
288 .num_pipes = 0, /* legal, last one wins */
289};
290
70a3eb7a 291static const struct intel_device_info intel_valleyview_m_info = {
219f4fdb
BW		 292 GEN7_FEATURES,
293 .is_mobile = 1,
294 .num_pipes = 2,
70a3eb7a 295 .is_valleyview = 1,
fba5d532 296 .display_mmio_offset = VLV_DISPLAY_BASE,
30ccd964 297 .has_llc = 0, /* legal, last one wins */
70a3eb7a
JB		 298};
299
300static const struct intel_device_info intel_valleyview_d_info = {
219f4fdb
BW		 301 GEN7_FEATURES,
302 .num_pipes = 2,
70a3eb7a 303 .is_valleyview = 1,
fba5d532 304 .display_mmio_offset = VLV_DISPLAY_BASE,
30ccd964 305 .has_llc = 0, /* legal, last one wins */
70a3eb7a
JB		 306};
307
4cae9ae0 308static const struct intel_device_info intel_haswell_d_info = {
219f4fdb
BW		 309 GEN7_FEATURES,
310 .is_haswell = 1,
dd93be58 311 .has_ddi = 1,
30568c45 312 .has_fpga_dbg = 1,
4cae9ae0
ED		 313};
314
315static const struct intel_device_info intel_haswell_m_info = {
219f4fdb
BW		 316 GEN7_FEATURES,
317 .is_haswell = 1,
318 .is_mobile = 1,
dd93be58 319 .has_ddi = 1,
30568c45 320 .has_fpga_dbg = 1,
c76b615c
JB		 321};
322
6103da0d
CW		 323static const struct pci_device_id pciidlist[] = { /* aka */
324 INTEL_VGA_DEVICE(0x3577, &intel_i830_info), /* I830_M */
325 INTEL_VGA_DEVICE(0x2562, &intel_845g_info), /* 845_G */
326 INTEL_VGA_DEVICE(0x3582, &intel_i85x_info), /* I855_GM */
5ce8ba7c 327 INTEL_VGA_DEVICE(0x358e, &intel_i85x_info),
6103da0d
CW		 328 INTEL_VGA_DEVICE(0x2572, &intel_i865g_info), /* I865_G */
329 INTEL_VGA_DEVICE(0x2582, &intel_i915g_info), /* I915_G */
330 INTEL_VGA_DEVICE(0x258a, &intel_i915g_info), /* E7221_G */
331 INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info), /* I915_GM */
332 INTEL_VGA_DEVICE(0x2772, &intel_i945g_info), /* I945_G */
333 INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info), /* I945_GM */
334 INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info), /* I945_GME */
335 INTEL_VGA_DEVICE(0x2972, &intel_i965g_info), /* I946_GZ */
336 INTEL_VGA_DEVICE(0x2982, &intel_i965g_info), /* G35_G */
337 INTEL_VGA_DEVICE(0x2992, &intel_i965g_info), /* I965_Q */
338 INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info), /* I965_G */
339 INTEL_VGA_DEVICE(0x29b2, &intel_g33_info), /* Q35_G */
340 INTEL_VGA_DEVICE(0x29c2, &intel_g33_info), /* G33_G */
341 INTEL_VGA_DEVICE(0x29d2, &intel_g33_info), /* Q33_G */
342 INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info), /* I965_GM */
343 INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info), /* I965_GME */
344 INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info), /* GM45_G */
345 INTEL_VGA_DEVICE(0x2e02, &intel_g45_info), /* IGD_E_G */
346 INTEL_VGA_DEVICE(0x2e12, &intel_g45_info), /* Q45_G */
347 INTEL_VGA_DEVICE(0x2e22, &intel_g45_info), /* G45_G */
348 INTEL_VGA_DEVICE(0x2e32, &intel_g45_info), /* G41_G */
349 INTEL_VGA_DEVICE(0x2e42, &intel_g45_info), /* B43_G */
41a51428 350 INTEL_VGA_DEVICE(0x2e92, &intel_g45_info), /* B43_G.1 */
cfdf1fa2
KH		 351 INTEL_VGA_DEVICE(0xa001, &intel_pineview_info),
352 INTEL_VGA_DEVICE(0xa011, &intel_pineview_info),
353 INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info),
354 INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info),
f6e450a6 355 INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info),
85540480
ZW		 356 INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info),
357 INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info),
a13e4093 358 INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info),
85540480 359 INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info),
4fefe435 360 INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info),
85540480 361 INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info),
c76b615c
JB		 362 INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info), /* GT1 mobile */
363 INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info), /* GT2 mobile */
364 INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */
365 INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */
366 INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */
999bcdea 367 INTEL_QUANTA_VGA_DEVICE(&intel_ivybridge_q_info), /* Quanta transcode */
cc22a938 368 INTEL_VGA_DEVICE(0x016a, &intel_ivybridge_d_info), /* GT2 server */
c14f5286
ED		 369 INTEL_VGA_DEVICE(0x0402, &intel_haswell_d_info), /* GT1 desktop */
370 INTEL_VGA_DEVICE(0x0412, &intel_haswell_d_info), /* GT2 desktop */
da612d88 371 INTEL_VGA_DEVICE(0x0422, &intel_haswell_d_info), /* GT2 desktop */
c14f5286
ED		 372 INTEL_VGA_DEVICE(0x040a, &intel_haswell_d_info), /* GT1 server */
373 INTEL_VGA_DEVICE(0x041a, &intel_haswell_d_info), /* GT2 server */
da612d88 374 INTEL_VGA_DEVICE(0x042a, &intel_haswell_d_info), /* GT2 server */
c14f5286
ED		 375 INTEL_VGA_DEVICE(0x0406, &intel_haswell_m_info), /* GT1 mobile */
376 INTEL_VGA_DEVICE(0x0416, &intel_haswell_m_info), /* GT2 mobile */
da612d88
PZ		 377 INTEL_VGA_DEVICE(0x0426, &intel_haswell_m_info), /* GT2 mobile */
378 INTEL_VGA_DEVICE(0x0C02, &intel_haswell_d_info), /* SDV GT1 desktop */
379 INTEL_VGA_DEVICE(0x0C12, &intel_haswell_d_info), /* SDV GT2 desktop */
380 INTEL_VGA_DEVICE(0x0C22, &intel_haswell_d_info), /* SDV GT2 desktop */
381 INTEL_VGA_DEVICE(0x0C0A, &intel_haswell_d_info), /* SDV GT1 server */
382 INTEL_VGA_DEVICE(0x0C1A, &intel_haswell_d_info), /* SDV GT2 server */
383 INTEL_VGA_DEVICE(0x0C2A, &intel_haswell_d_info), /* SDV GT2 server */
384 INTEL_VGA_DEVICE(0x0C06, &intel_haswell_m_info), /* SDV GT1 mobile */
385 INTEL_VGA_DEVICE(0x0C16, &intel_haswell_m_info), /* SDV GT2 mobile */
386 INTEL_VGA_DEVICE(0x0C26, &intel_haswell_m_info), /* SDV GT2 mobile */
387 INTEL_VGA_DEVICE(0x0A02, &intel_haswell_d_info), /* ULT GT1 desktop */
388 INTEL_VGA_DEVICE(0x0A12, &intel_haswell_d_info), /* ULT GT2 desktop */
389 INTEL_VGA_DEVICE(0x0A22, &intel_haswell_d_info), /* ULT GT2 desktop */
390 INTEL_VGA_DEVICE(0x0A0A, &intel_haswell_d_info), /* ULT GT1 server */
391 INTEL_VGA_DEVICE(0x0A1A, &intel_haswell_d_info), /* ULT GT2 server */
392 INTEL_VGA_DEVICE(0x0A2A, &intel_haswell_d_info), /* ULT GT2 server */
393 INTEL_VGA_DEVICE(0x0A06, &intel_haswell_m_info), /* ULT GT1 mobile */
394 INTEL_VGA_DEVICE(0x0A16, &intel_haswell_m_info), /* ULT GT2 mobile */
395 INTEL_VGA_DEVICE(0x0A26, &intel_haswell_m_info), /* ULT GT2 mobile */
86c268ed
KG		 396 INTEL_VGA_DEVICE(0x0D02, &intel_haswell_d_info), /* CRW GT1 desktop */
397 INTEL_VGA_DEVICE(0x0D12, &intel_haswell_d_info), /* CRW GT2 desktop */
da612d88 398 INTEL_VGA_DEVICE(0x0D22, &intel_haswell_d_info), /* CRW GT2 desktop */
86c268ed
KG		 399 INTEL_VGA_DEVICE(0x0D0A, &intel_haswell_d_info), /* CRW GT1 server */
400 INTEL_VGA_DEVICE(0x0D1A, &intel_haswell_d_info), /* CRW GT2 server */
da612d88 401 INTEL_VGA_DEVICE(0x0D2A, &intel_haswell_d_info), /* CRW GT2 server */
86c268ed
KG		 402 INTEL_VGA_DEVICE(0x0D06, &intel_haswell_m_info), /* CRW GT1 mobile */
403 INTEL_VGA_DEVICE(0x0D16, &intel_haswell_m_info), /* CRW GT2 mobile */
da612d88 404 INTEL_VGA_DEVICE(0x0D26, &intel_haswell_m_info), /* CRW GT2 mobile */
ff049b6c 405 INTEL_VGA_DEVICE(0x0f30, &intel_valleyview_m_info),
d7fee5f6
JB		 406 INTEL_VGA_DEVICE(0x0f31, &intel_valleyview_m_info),
407 INTEL_VGA_DEVICE(0x0f32, &intel_valleyview_m_info),
408 INTEL_VGA_DEVICE(0x0f33, &intel_valleyview_m_info),
ff049b6c
JB		 409 INTEL_VGA_DEVICE(0x0157, &intel_valleyview_m_info),
410 INTEL_VGA_DEVICE(0x0155, &intel_valleyview_d_info),
49ae35f2 411 {0, 0, 0}
1da177e4
LT		 412};
413
79e53945
JB		 414#if defined(CONFIG_DRM_I915_KMS)
415MODULE_DEVICE_TABLE(pci, pciidlist);
416#endif
417
0206e353 418void intel_detect_pch(struct drm_device *dev)
3bad0781
ZW		 419{
420 struct drm_i915_private *dev_priv = dev->dev_private;
421 struct pci_dev *pch;
422
ce1bb329
BW		 423 /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
424 * (which really amounts to a PCH but no South Display).
425 */
426 if (INTEL_INFO(dev)->num_pipes == 0) {
427 dev_priv->pch_type = PCH_NOP;
428 dev_priv->num_pch_pll = 0;
429 return;
430 }
431
3bad0781
ZW		 432 /*
433 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
434 * make graphics device passthrough work easy for VMM, that only
435 * need to expose ISA bridge to let driver know the real hardware
436 * underneath. This is a requirement from virtualization team.
437 */
438 pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
439 if (pch) {
440 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
17a303ec 441 unsigned short id;
3bad0781 442 id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
17a303ec 443 dev_priv->pch_id = id;
3bad0781 444
90711d50
JB		 445 if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
446 dev_priv->pch_type = PCH_IBX;
ee7b9f93 447 dev_priv->num_pch_pll = 2;
90711d50 448 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
7fcb83cd 449 WARN_ON(!IS_GEN5(dev));
90711d50 450 } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
3bad0781 451 dev_priv->pch_type = PCH_CPT;
ee7b9f93 452 dev_priv->num_pch_pll = 2;
3bad0781 453 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
7fcb83cd 454 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
c792513b
JB		 455 } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
456 /* PantherPoint is CPT compatible */
457 dev_priv->pch_type = PCH_CPT;
ee7b9f93 458 dev_priv->num_pch_pll = 2;
c792513b 459 DRM_DEBUG_KMS("Found PatherPoint PCH\n");
7fcb83cd 460 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
eb877ebf
ED		 461 } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
462 dev_priv->pch_type = PCH_LPT;
ee7b9f93 463 dev_priv->num_pch_pll = 0;
eb877ebf 464 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
7fcb83cd 465 WARN_ON(!IS_HASWELL(dev));
08e1413d 466 WARN_ON(IS_ULT(dev));
ae6935dd
WSC		 467 } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
468 dev_priv->pch_type = PCH_LPT;
469 dev_priv->num_pch_pll = 0;
470 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
471 WARN_ON(!IS_HASWELL(dev));
08e1413d 472 WARN_ON(!IS_ULT(dev));
3bad0781 473 }
ee7b9f93 474 BUG_ON(dev_priv->num_pch_pll > I915_NUM_PLLS);
3bad0781
ZW		 475 }
476 pci_dev_put(pch);
477 }
478}
479
2911a35b
BW		 480bool i915_semaphore_is_enabled(struct drm_device *dev)
481{
482 if (INTEL_INFO(dev)->gen < 6)
483 return 0;
484
485 if (i915_semaphores >= 0)
486 return i915_semaphores;
487
59de3295 488#ifdef CONFIG_INTEL_IOMMU
2911a35b 489 /* Enable semaphores on SNB when IO remapping is off */
59de3295
DV		 490 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
491 return false;
492#endif
2911a35b
BW		 493
494 return 1;
495}
496
84b79f8d 497static int i915_drm_freeze(struct drm_device *dev)
ba8bbcf6 498{
61caf87c 499 struct drm_i915_private *dev_priv = dev->dev_private;
24576d23 500 struct drm_crtc *crtc;
61caf87c 501
b8efb17b
ZR		 502 /* ignore lid events during suspend */
503 mutex_lock(&dev_priv->modeset_restore_lock);
504 dev_priv->modeset_restore = MODESET_SUSPENDED;
505 mutex_unlock(&dev_priv->modeset_restore_lock);
506
cb10799c
PZ		 507 intel_set_power_well(dev, true);
508
5bcf719b
DA		 509 drm_kms_helper_poll_disable(dev);
510
ba8bbcf6 511 pci_save_state(dev->pdev);
ba8bbcf6 512
5669fcac 513 /* If KMS is active, we do the leavevt stuff here */
226485e9 514 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
84b79f8d
RW		 515 int error = i915_gem_idle(dev);
516 if (error) {
226485e9 517 dev_err(&dev->pdev->dev,
84b79f8d
RW		 518 "GEM idle failed, resume might fail\n");
519 return error;
520 }
a261b246 521
1a01ab3b
JB		 522 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
523
226485e9 524 drm_irq_uninstall(dev);
15239099 525 dev_priv->enable_hotplug_processing = false;
24576d23
JB		 526 /*
527 * Disable CRTCs directly since we want to preserve sw state
528 * for _thaw.
529 */
530 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
531 dev_priv->display.crtc_disable(crtc);
5669fcac
JB		 532 }
533
9e06dd39
JB		 534 i915_save_state(dev);
535
44834a67 536 intel_opregion_fini(dev);
8ee1c3db 537
3fa016a0
DA		 538 console_lock();
539 intel_fbdev_set_suspend(dev, 1);
540 console_unlock();
541
61caf87c 542 return 0;
84b79f8d
RW		 543}
544
6a9ee8af 545int i915_suspend(struct drm_device *dev, pm_message_t state)
84b79f8d
RW		 546{
547 int error;
548
549 if (!dev || !dev->dev_private) {
550 DRM_ERROR("dev: %p\n", dev);
551 DRM_ERROR("DRM not initialized, aborting suspend.\n");
552 return -ENODEV;
553 }
554
555 if (state.event == PM_EVENT_PRETHAW)
556 return 0;
557
5bcf719b
DA		 558
559 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
560 return 0;
6eecba33 561
84b79f8d
RW		 562 error = i915_drm_freeze(dev);
563 if (error)
564 return error;
565
b932ccb5
DA		 566 if (state.event == PM_EVENT_SUSPEND) {
567 /* Shut down the device */
568 pci_disable_device(dev->pdev);
569 pci_set_power_state(dev->pdev, PCI_D3hot);
570 }
ba8bbcf6
JB		 571
572 return 0;
573}
574
073f34d9
JB		 575void intel_console_resume(struct work_struct *work)
576{
577 struct drm_i915_private *dev_priv =
578 container_of(work, struct drm_i915_private,
579 console_resume_work);
580 struct drm_device *dev = dev_priv->dev;
581
582 console_lock();
583 intel_fbdev_set_suspend(dev, 0);
584 console_unlock();
585}
586
bb60b969
JB		 587static void intel_resume_hotplug(struct drm_device *dev)
588{
589 struct drm_mode_config *mode_config = &dev->mode_config;
590 struct intel_encoder *encoder;
591
592 mutex_lock(&mode_config->mutex);
593 DRM_DEBUG_KMS("running encoder hotplug functions\n");
594
595 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
596 if (encoder->hot_plug)
597 encoder->hot_plug(encoder);
598
599 mutex_unlock(&mode_config->mutex);
600
601 /* Just fire off a uevent and let userspace tell us what to do */
602 drm_helper_hpd_irq_event(dev);
603}
604
1abd02e2 605static int __i915_drm_thaw(struct drm_device *dev)
ba8bbcf6 606{
5669fcac 607 struct drm_i915_private *dev_priv = dev->dev_private;
84b79f8d 608 int error = 0;
8ee1c3db 609
61caf87c 610 i915_restore_state(dev);
44834a67 611 intel_opregion_setup(dev);
61caf87c 612
5669fcac
JB		 613 /* KMS EnterVT equivalent */
614 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
dde86e2d 615 intel_init_pch_refclk(dev);
1833b134 616
5669fcac
JB		 617 mutex_lock(&dev->struct_mutex);
618 dev_priv->mm.suspended = 0;
619
f691e2f4 620 error = i915_gem_init_hw(dev);
5669fcac 621 mutex_unlock(&dev->struct_mutex);
226485e9 622
15239099
DV		 623 /* We need working interrupts for modeset enabling ... */
624 drm_irq_install(dev);
625
1833b134 626 intel_modeset_init_hw(dev);
24576d23
JB		 627
628 drm_modeset_lock_all(dev);
629 intel_modeset_setup_hw_state(dev, true);
630 drm_modeset_unlock_all(dev);
15239099
DV		 631
632 /*
633 * ... but also need to make sure that hotplug processing
634 * doesn't cause havoc. Like in the driver load code we don't
635 * bother with the tiny race here where we might loose hotplug
636 * notifications.
637 * */
20afbda2 638 intel_hpd_init(dev);
15239099 639 dev_priv->enable_hotplug_processing = true;
bb60b969
JB		 640 /* Config may have changed between suspend and resume */
641 intel_resume_hotplug(dev);
d5bb081b 642 }
1daed3fb 643
44834a67
CW		 644 intel_opregion_init(dev);
645
073f34d9
JB		 646 /*
647 * The console lock can be pretty contented on resume due
648 * to all the printk activity. Try to keep it out of the hot
649 * path of resume if possible.
650 */
651 if (console_trylock()) {
652 intel_fbdev_set_suspend(dev, 0);
653 console_unlock();
654 } else {
655 schedule_work(&dev_priv->console_resume_work);
656 }
657
b8efb17b
ZR		 658 mutex_lock(&dev_priv->modeset_restore_lock);
659 dev_priv->modeset_restore = MODESET_DONE;
660 mutex_unlock(&dev_priv->modeset_restore_lock);
84b79f8d
RW		 661 return error;
662}
663
1abd02e2
JB		 664static int i915_drm_thaw(struct drm_device *dev)
665{
666 int error = 0;
667
668 intel_gt_reset(dev);
669
670 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
671 mutex_lock(&dev->struct_mutex);
672 i915_gem_restore_gtt_mappings(dev);
673 mutex_unlock(&dev->struct_mutex);
674 }
675
676 __i915_drm_thaw(dev);
677
84b79f8d
RW		 678 return error;
679}
680
6a9ee8af 681int i915_resume(struct drm_device *dev)
84b79f8d 682{
1abd02e2 683 struct drm_i915_private *dev_priv = dev->dev_private;
6eecba33
CW		 684 int ret;
685
5bcf719b
DA		 686 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
687 return 0;
688
84b79f8d
RW		 689 if (pci_enable_device(dev->pdev))
690 return -EIO;
691
692 pci_set_master(dev->pdev);
693
1abd02e2
JB		 694 intel_gt_reset(dev);
695
696 /*
697 * Platforms with opregion should have sane BIOS, older ones (gen3 and
698 * earlier) need this since the BIOS might clear all our scratch PTEs.
699 */
700 if (drm_core_check_feature(dev, DRIVER_MODESET) &&
701 !dev_priv->opregion.header) {
702 mutex_lock(&dev->struct_mutex);
703 i915_gem_restore_gtt_mappings(dev);
704 mutex_unlock(&dev->struct_mutex);
705 }
706
707 ret = __i915_drm_thaw(dev);
6eecba33
CW		 708 if (ret)
709 return ret;
710
711 drm_kms_helper_poll_enable(dev);
712 return 0;
ba8bbcf6
JB		 713}
714
d4b8bb2a 715static int i8xx_do_reset(struct drm_device *dev)
dc96e9b8
CW		 716{
717 struct drm_i915_private *dev_priv = dev->dev_private;
718
719 if (IS_I85X(dev))
720 return -ENODEV;
721
722 I915_WRITE(D_STATE, I915_READ(D_STATE) | DSTATE_GFX_RESET_I830);
723 POSTING_READ(D_STATE);
724
725 if (IS_I830(dev) || IS_845G(dev)) {
726 I915_WRITE(DEBUG_RESET_I830,
727 DEBUG_RESET_DISPLAY |
728 DEBUG_RESET_RENDER |
729 DEBUG_RESET_FULL);
730 POSTING_READ(DEBUG_RESET_I830);
731 msleep(1);
732
733 I915_WRITE(DEBUG_RESET_I830, 0);
734 POSTING_READ(DEBUG_RESET_I830);
735 }
736
737 msleep(1);
738
739 I915_WRITE(D_STATE, I915_READ(D_STATE) & ~DSTATE_GFX_RESET_I830);
740 POSTING_READ(D_STATE);
741
742 return 0;
743}
744
f49f0586
KG		 745static int i965_reset_complete(struct drm_device *dev)
746{
747 u8 gdrst;
eeccdcac 748 pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
5fe9fe8c 749 return (gdrst & GRDOM_RESET_ENABLE) == 0;
f49f0586
KG		 750}
751
d4b8bb2a 752static int i965_do_reset(struct drm_device *dev)
0573ed4a 753{
5ccce180 754 int ret;
0573ed4a
KG		 755 u8 gdrst;
756
ae681d96
CW		 757 /*
758 * Set the domains we want to reset (GRDOM/bits 2 and 3) as
759 * well as the reset bit (GR/bit 0). Setting the GR bit
760 * triggers the reset; when done, the hardware will clear it.
761 */
0573ed4a 762 pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
d4b8bb2a 763 pci_write_config_byte(dev->pdev, I965_GDRST,
5ccce180
DV		 764 gdrst | GRDOM_RENDER |
765 GRDOM_RESET_ENABLE);
766 ret = wait_for(i965_reset_complete(dev), 500);
767 if (ret)
768 return ret;
769
770 /* We can't reset render&media without also resetting display ... */
771 pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
772 pci_write_config_byte(dev->pdev, I965_GDRST,
773 gdrst | GRDOM_MEDIA |
774 GRDOM_RESET_ENABLE);
0573ed4a
KG		 775
776 return wait_for(i965_reset_complete(dev), 500);
777}
778
d4b8bb2a 779static int ironlake_do_reset(struct drm_device *dev)
0573ed4a
KG		 780{
781 struct drm_i915_private *dev_priv = dev->dev_private;
5ccce180
DV		 782 u32 gdrst;
783 int ret;
784
785 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
8a5c2ae7 786 gdrst &= ~GRDOM_MASK;
5ccce180
DV		 787 I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
788 gdrst | GRDOM_RENDER | GRDOM_RESET_ENABLE);
789 ret = wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
790 if (ret)
791 return ret;
792
793 /* We can't reset render&media without also resetting display ... */
794 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
8a5c2ae7 795 gdrst &= ~GRDOM_MASK;
d4b8bb2a 796 I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
5ccce180 797 gdrst | GRDOM_MEDIA | GRDOM_RESET_ENABLE);
0573ed4a 798 return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
ba8bbcf6
JB		 799}
800
d4b8bb2a 801static int gen6_do_reset(struct drm_device *dev)
cff458c2
EA		 802{
803 struct drm_i915_private *dev_priv = dev->dev_private;
b6e45f86
KP		 804 int ret;
805 unsigned long irqflags;
cff458c2 806
286fed41
KP		 807 /* Hold gt_lock across reset to prevent any register access
808 * with forcewake not set correctly
809 */
b6e45f86 810 spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
286fed41
KP		 811
812 /* Reset the chip */
813
814 /* GEN6_GDRST is not in the gt power well, no need to check
815 * for fifo space for the write or forcewake the chip for
816 * the read
817 */
818 I915_WRITE_NOTRACE(GEN6_GDRST, GEN6_GRDOM_FULL);
819
820 /* Spin waiting for the device to ack the reset request */
821 ret = wait_for((I915_READ_NOTRACE(GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500);
822
823 /* If reset with a user forcewake, try to restore, otherwise turn it off */
b6e45f86 824 if (dev_priv->forcewake_count)
990bbdad 825 dev_priv->gt.force_wake_get(dev_priv);
286fed41 826 else
990bbdad 827 dev_priv->gt.force_wake_put(dev_priv);
286fed41
KP		 828
829 /* Restore fifo count */
830 dev_priv->gt_fifo_count = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
831
b6e45f86
KP		 832 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
833 return ret;
cff458c2
EA		 834}
835
8e96d9c4 836int intel_gpu_reset(struct drm_device *dev)
350d2706 837{
2b9dc9a2 838 struct drm_i915_private *dev_priv = dev->dev_private;
350d2706
DV		 839 int ret = -ENODEV;
840
841 switch (INTEL_INFO(dev)->gen) {
842 case 7:
843 case 6:
d4b8bb2a 844 ret = gen6_do_reset(dev);
350d2706
DV		 845 break;
846 case 5:
d4b8bb2a 847 ret = ironlake_do_reset(dev);
350d2706
DV		 848 break;
849 case 4:
d4b8bb2a 850 ret = i965_do_reset(dev);
350d2706
DV		 851 break;
852 case 2:
d4b8bb2a 853 ret = i8xx_do_reset(dev);
350d2706
DV		 854 break;
855 }
856
2b9dc9a2 857 /* Also reset the gpu hangman. */
99584db3 858 if (dev_priv->gpu_error.stop_rings) {
bae36991 859 DRM_INFO("Simulated gpu hang, resetting stop_rings\n");
99584db3 860 dev_priv->gpu_error.stop_rings = 0;
2b9dc9a2
DV		 861 if (ret == -ENODEV) {
862 DRM_ERROR("Reset not implemented, but ignoring "
863 "error for simulated gpu hangs\n");
864 ret = 0;
865 }
866 }
867
350d2706
DV		 868 return ret;
869}
870
11ed50ec 871/**
f3953dcb 872 * i915_reset - reset chip after a hang
11ed50ec 873 * @dev: drm device to reset
11ed50ec
BG		 874 *
875 * Reset the chip. Useful if a hang is detected. Returns zero on successful
876 * reset or otherwise an error code.
877 *
878 * Procedure is fairly simple:
879 * - reset the chip using the reset reg
880 * - re-init context state
881 * - re-init hardware status page
882 * - re-init ring buffer
883 * - re-init interrupt state
884 * - re-init display
885 */
d4b8bb2a 886int i915_reset(struct drm_device *dev)
11ed50ec
BG		 887{
888 drm_i915_private_t *dev_priv = dev->dev_private;
0573ed4a 889 int ret;
11ed50ec 890
d78cb50b
CW		 891 if (!i915_try_reset)
892 return 0;
893
d54a02c0 894 mutex_lock(&dev->struct_mutex);
11ed50ec 895
069efc1d 896 i915_gem_reset(dev);
77f01230 897
f803aa55 898 ret = -ENODEV;
99584db3 899 if (get_seconds() - dev_priv->gpu_error.last_reset < 5)
ae681d96 900 DRM_ERROR("GPU hanging too fast, declaring wedged!\n");
350d2706 901 else
d4b8bb2a 902 ret = intel_gpu_reset(dev);
350d2706 903
99584db3 904 dev_priv->gpu_error.last_reset = get_seconds();
0573ed4a 905 if (ret) {
f803aa55 906 DRM_ERROR("Failed to reset chip.\n");
f953c935 907 mutex_unlock(&dev->struct_mutex);
f803aa55 908 return ret;
11ed50ec
BG		 909 }
910
911 /* Ok, now get things going again... */
912
913 /*
914 * Everything depends on having the GTT running, so we need to start
915 * there. Fortunately we don't need to do this unless we reset the
916 * chip at a PCI level.
917 *
918 * Next we need to restore the context, but we don't use those
919 * yet either...
920 *
921 * Ring buffer needs to be re-initialized in the KMS case, or if X
922 * was running at the time of the reset (i.e. we weren't VT
923 * switched away).
924 */
925 if (drm_core_check_feature(dev, DRIVER_MODESET) ||
8187a2b7 926 !dev_priv->mm.suspended) {
b4519513
CW		 927 struct intel_ring_buffer *ring;
928 int i;
929
11ed50ec 930 dev_priv->mm.suspended = 0;
75a6898f 931
f691e2f4
DV		 932 i915_gem_init_swizzling(dev);
933
b4519513
CW		 934 for_each_ring(ring, dev_priv, i)
935 ring->init(ring);
75a6898f 936
254f965c 937 i915_gem_context_init(dev);
b7c36d25
BW		 938 if (dev_priv->mm.aliasing_ppgtt) {
939 ret = dev_priv->mm.aliasing_ppgtt->enable(dev);
940 if (ret)
941 i915_gem_cleanup_aliasing_ppgtt(dev);
942 }
e21af88d 943
8e88a2bd
DV		 944 /*
945 * It would make sense to re-init all the other hw state, at
946 * least the rps/rc6/emon init done within modeset_init_hw. For
947 * some unknown reason, this blows up my ilk, so don't.
948 */
f817586c 949
8e88a2bd 950 mutex_unlock(&dev->struct_mutex);
f817586c 951
11ed50ec
BG		 952 drm_irq_uninstall(dev);
953 drm_irq_install(dev);
20afbda2 954 intel_hpd_init(dev);
bcbc324a
DV		 955 } else {
956 mutex_unlock(&dev->struct_mutex);
11ed50ec
BG		 957 }
958
11ed50ec
BG		 959 return 0;
960}
961
56550d94 962static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
112b715e 963{
01a06850
DV		 964 struct intel_device_info *intel_info =
965 (struct intel_device_info *) ent->driver_data;
966
70b12bb4 967 if (intel_info->is_valleyview)
0a3af268
RV		 968 if(!i915_preliminary_hw_support) {
969 DRM_ERROR("Preliminary hardware support disabled\n");
970 return -ENODEV;
971 }
972
5fe49d86
CW		 973 /* Only bind to function 0 of the device. Early generations
974 * used function 1 as a placeholder for multi-head. This causes
975 * us confusion instead, especially on the systems where both
976 * functions have the same PCI-ID!
977 */
978 if (PCI_FUNC(pdev->devfn))
979 return -ENODEV;
980
01a06850
DV		 981 /* We've managed to ship a kms-enabled ddx that shipped with an XvMC
982 * implementation for gen3 (and only gen3) that used legacy drm maps
983 * (gasp!) to share buffers between X and the client. Hence we need to
984 * keep around the fake agp stuff for gen3, even when kms is enabled. */
985 if (intel_info->gen != 3) {
986 driver.driver_features &=
987 ~(DRIVER_USE_AGP | DRIVER_REQUIRE_AGP);
988 } else if (!intel_agp_enabled) {
989 DRM_ERROR("drm/i915 can't work without intel_agp module!\n");
990 return -ENODEV;
991 }
992
dcdb1674 993 return drm_get_pci_dev(pdev, ent, &driver);
112b715e
KH		 994}
995
996static void
997i915_pci_remove(struct pci_dev *pdev)
998{
999 struct drm_device *dev = pci_get_drvdata(pdev);
1000
1001 drm_put_dev(dev);
1002}
1003
84b79f8d 1004static int i915_pm_suspend(struct device *dev)
112b715e 1005{
84b79f8d
RW		 1006 struct pci_dev *pdev = to_pci_dev(dev);
1007 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1008 int error;
112b715e 1009
84b79f8d
RW		 1010 if (!drm_dev || !drm_dev->dev_private) {
1011 dev_err(dev, "DRM not initialized, aborting suspend.\n");
1012 return -ENODEV;
1013 }
112b715e 1014
5bcf719b
DA		 1015 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1016 return 0;
1017
84b79f8d
RW		 1018 error = i915_drm_freeze(drm_dev);
1019 if (error)
1020 return error;
112b715e 1021
84b79f8d
RW		 1022 pci_disable_device(pdev);
1023 pci_set_power_state(pdev, PCI_D3hot);
cbda12d7 1024
84b79f8d 1025 return 0;
cbda12d7
ZW		 1026}
1027
84b79f8d 1028static int i915_pm_resume(struct device *dev)
cbda12d7 1029{
84b79f8d
RW		 1030 struct pci_dev *pdev = to_pci_dev(dev);
1031 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1032
1033 return i915_resume(drm_dev);
cbda12d7
ZW		 1034}
1035
84b79f8d 1036static int i915_pm_freeze(struct device *dev)
cbda12d7 1037{
84b79f8d
RW		 1038 struct pci_dev *pdev = to_pci_dev(dev);
1039 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1040
1041 if (!drm_dev || !drm_dev->dev_private) {
1042 dev_err(dev, "DRM not initialized, aborting suspend.\n");
1043 return -ENODEV;
1044 }
1045
1046 return i915_drm_freeze(drm_dev);
cbda12d7
ZW		 1047}
1048
84b79f8d 1049static int i915_pm_thaw(struct device *dev)
cbda12d7 1050{
84b79f8d
RW		 1051 struct pci_dev *pdev = to_pci_dev(dev);
1052 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1053
1054 return i915_drm_thaw(drm_dev);
cbda12d7
ZW		 1055}
1056
84b79f8d 1057static int i915_pm_poweroff(struct device *dev)
cbda12d7 1058{
84b79f8d
RW		 1059 struct pci_dev *pdev = to_pci_dev(dev);
1060 struct drm_device *drm_dev = pci_get_drvdata(pdev);
84b79f8d 1061
61caf87c 1062 return i915_drm_freeze(drm_dev);
cbda12d7
ZW		 1063}
1064
b4b78d12 1065static const struct dev_pm_ops i915_pm_ops = {
0206e353
AJ		 1066 .suspend = i915_pm_suspend,
1067 .resume = i915_pm_resume,
1068 .freeze = i915_pm_freeze,
1069 .thaw = i915_pm_thaw,
1070 .poweroff = i915_pm_poweroff,
1071 .restore = i915_pm_resume,
cbda12d7
ZW		 1072};
1073
78b68556 1074static const struct vm_operations_struct i915_gem_vm_ops = {
de151cf6 1075 .fault = i915_gem_fault,
ab00b3e5
JB		 1076 .open = drm_gem_vm_open,
1077 .close = drm_gem_vm_close,
de151cf6
JB		 1078};
1079
e08e96de
AV		 1080static const struct file_operations i915_driver_fops = {
1081 .owner = THIS_MODULE,
1082 .open = drm_open,
1083 .release = drm_release,
1084 .unlocked_ioctl = drm_ioctl,
1085 .mmap = drm_gem_mmap,
1086 .poll = drm_poll,
1087 .fasync = drm_fasync,
1088 .read = drm_read,
1089#ifdef CONFIG_COMPAT
1090 .compat_ioctl = i915_compat_ioctl,
1091#endif
1092 .llseek = noop_llseek,
1093};
1094
1da177e4 1095static struct drm_driver driver = {
0c54781b
MW		 1096 /* Don't use MTRRs here; the Xserver or userspace app should
1097 * deal with them for Intel hardware.
792d2b9a 1098 */
673a394b
EA		 1099 .driver_features =
1100 DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR |*/
1286ff73 1101 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME,
22eae947 1102 .load = i915_driver_load,
ba8bbcf6 1103 .unload = i915_driver_unload,
673a394b 1104 .open = i915_driver_open,
22eae947
DA		 1105 .lastclose = i915_driver_lastclose,
1106 .preclose = i915_driver_preclose,
673a394b 1107 .postclose = i915_driver_postclose,
d8e29209
RW		 1108
1109 /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
1110 .suspend = i915_suspend,
1111 .resume = i915_resume,
1112
cda17380 1113 .device_is_agp = i915_driver_device_is_agp,
7c1c2871
DA		 1114 .master_create = i915_master_create,
1115 .master_destroy = i915_master_destroy,
955b12de 1116#if defined(CONFIG_DEBUG_FS)
27c202ad
BG		 1117 .debugfs_init = i915_debugfs_init,
1118 .debugfs_cleanup = i915_debugfs_cleanup,
955b12de 1119#endif
673a394b
EA		 1120 .gem_init_object = i915_gem_init_object,
1121 .gem_free_object = i915_gem_free_object,
de151cf6 1122 .gem_vm_ops = &i915_gem_vm_ops,
1286ff73
DV		 1123
1124 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1125 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1126 .gem_prime_export = i915_gem_prime_export,
1127 .gem_prime_import = i915_gem_prime_import,
1128
ff72145b
DA		 1129 .dumb_create = i915_gem_dumb_create,
1130 .dumb_map_offset = i915_gem_mmap_gtt,
1131 .dumb_destroy = i915_gem_dumb_destroy,
1da177e4 1132 .ioctls = i915_ioctls,
e08e96de 1133 .fops = &i915_driver_fops,
22eae947
DA		 1134 .name = DRIVER_NAME,
1135 .desc = DRIVER_DESC,
1136 .date = DRIVER_DATE,
1137 .major = DRIVER_MAJOR,
1138 .minor = DRIVER_MINOR,
1139 .patchlevel = DRIVER_PATCHLEVEL,
1da177e4
LT		 1140};
1141
8410ea3b
DA		 1142static struct pci_driver i915_pci_driver = {
1143 .name = DRIVER_NAME,
1144 .id_table = pciidlist,
1145 .probe = i915_pci_probe,
1146 .remove = i915_pci_remove,
1147 .driver.pm = &i915_pm_ops,
1148};
1149
1da177e4
LT		 1150static int __init i915_init(void)
1151{
1152 driver.num_ioctls = i915_max_ioctl;
79e53945
JB		 1153
1154 /*
1155 * If CONFIG_DRM_I915_KMS is set, default to KMS unless
1156 * explicitly disabled with the module pararmeter.
1157 *
1158 * Otherwise, just follow the parameter (defaulting to off).
1159 *
1160 * Allow optional vga_text_mode_force boot option to override
1161 * the default behavior.
1162 */
1163#if defined(CONFIG_DRM_I915_KMS)
1164 if (i915_modeset != 0)
1165 driver.driver_features |= DRIVER_MODESET;
1166#endif
1167 if (i915_modeset == 1)
1168 driver.driver_features |= DRIVER_MODESET;
1169
1170#ifdef CONFIG_VGA_CONSOLE
1171 if (vgacon_text_force() && i915_modeset == -1)
1172 driver.driver_features &= ~DRIVER_MODESET;
1173#endif
1174
3885c6bb
CW		 1175 if (!(driver.driver_features & DRIVER_MODESET))
1176 driver.get_vblank_timestamp = NULL;
1177
8410ea3b 1178 return drm_pci_init(&driver, &i915_pci_driver);
1da177e4
LT		 1179}
1180
1181static void __exit i915_exit(void)
1182{
8410ea3b 1183 drm_pci_exit(&driver, &i915_pci_driver);
1da177e4
LT		 1184}
1185
1186module_init(i915_init);
1187module_exit(i915_exit);
1188
b5e89ed5
DA		 1189MODULE_AUTHOR(DRIVER_AUTHOR);
1190MODULE_DESCRIPTION(DRIVER_DESC);
1da177e4 1191MODULE_LICENSE("GPL and additional rights");
f7000883 1192
b7d84096
JB		 1193/* We give fast paths for the really cool registers */
1194#define NEEDS_FORCE_WAKE(dev_priv, reg) \
b7884eb4
DV		 1195 ((HAS_FORCE_WAKE((dev_priv)->dev)) && \
1196 ((reg) < 0x40000) && \
1197 ((reg) != FORCEWAKE))
a8b1397d
DV		 1198static void
1199ilk_dummy_write(struct drm_i915_private *dev_priv)
1200{
1201 /* WaIssueDummyWriteToWakeupFromRC6: Issue a dummy write to wake up the
1202 * chip from rc6 before touching it for real. MI_MODE is masked, hence
1203 * harmless to write 0 into. */
1204 I915_WRITE_NOTRACE(MI_MODE, 0);
1205}
1206
115bc2de
PZ		 1207static void
1208hsw_unclaimed_reg_clear(struct drm_i915_private *dev_priv, u32 reg)
1209{
e76ebff8 1210 if (HAS_FPGA_DBG_UNCLAIMED(dev_priv->dev) &&
3f1e109a 1211 (I915_READ_NOTRACE(FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) {
115bc2de
PZ		 1212 DRM_ERROR("Unknown unclaimed register before writing to %x\n",
1213 reg);
3f1e109a 1214 I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
115bc2de
PZ		 1215 }
1216}
1217
1218static void
1219hsw_unclaimed_reg_check(struct drm_i915_private *dev_priv, u32 reg)
1220{
e76ebff8 1221 if (HAS_FPGA_DBG_UNCLAIMED(dev_priv->dev) &&
3f1e109a 1222 (I915_READ_NOTRACE(FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) {
115bc2de 1223 DRM_ERROR("Unclaimed write to %x\n", reg);
3f1e109a 1224 I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
115bc2de
PZ		 1225 }
1226}
1227
f7000883
AK		 1228#define __i915_read(x, y) \
1229u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
1230 u##x val = 0; \
a8b1397d
DV		 1231 if (IS_GEN5(dev_priv->dev)) \
1232 ilk_dummy_write(dev_priv); \
f7000883 1233 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
c937504e
KP		 1234 unsigned long irqflags; \
1235 spin_lock_irqsave(&dev_priv->gt_lock, irqflags); \
1236 if (dev_priv->forcewake_count == 0) \
990bbdad 1237 dev_priv->gt.force_wake_get(dev_priv); \
f7000883 1238 val = read##y(dev_priv->regs + reg); \
c937504e 1239 if (dev_priv->forcewake_count == 0) \
990bbdad 1240 dev_priv->gt.force_wake_put(dev_priv); \
c937504e 1241 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); \
f7000883
AK		 1242 } else { \
1243 val = read##y(dev_priv->regs + reg); \
1244 } \
1245 trace_i915_reg_rw(false, reg, val, sizeof(val)); \
1246 return val; \
1247}
1248
1249__i915_read(8, b)
1250__i915_read(16, w)
1251__i915_read(32, l)
1252__i915_read(64, q)
1253#undef __i915_read
1254
1255#define __i915_write(x, y) \
1256void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
67a3744f 1257 u32 __fifo_ret = 0; \
f7000883
AK		 1258 trace_i915_reg_rw(true, reg, val, sizeof(val)); \
1259 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
67a3744f 1260 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
f7000883 1261 } \
a8b1397d
DV		 1262 if (IS_GEN5(dev_priv->dev)) \
1263 ilk_dummy_write(dev_priv); \
115bc2de 1264 hsw_unclaimed_reg_clear(dev_priv, reg); \
fe31b574 1265 write##y(val, dev_priv->regs + reg); \
67a3744f
BW		 1266 if (unlikely(__fifo_ret)) { \
1267 gen6_gt_check_fifodbg(dev_priv); \
1268 } \
115bc2de 1269 hsw_unclaimed_reg_check(dev_priv, reg); \
f7000883
AK		 1270}
1271__i915_write(8, b)
1272__i915_write(16, w)
1273__i915_write(32, l)
1274__i915_write(64, q)
1275#undef __i915_write
c0c7babc
BW		 1276
1277static const struct register_whitelist {
1278 uint64_t offset;
1279 uint32_t size;
1280 uint32_t gen_bitmask; /* support gens, 0x10 for 4, 0x30 for 4 and 5, etc. */
1281} whitelist[] = {
1282 { RING_TIMESTAMP(RENDER_RING_BASE), 8, 0xF0 },
1283};
1284
1285int i915_reg_read_ioctl(struct drm_device *dev,
1286 void *data, struct drm_file *file)
1287{
1288 struct drm_i915_private *dev_priv = dev->dev_private;
1289 struct drm_i915_reg_read *reg = data;
1290 struct register_whitelist const *entry = whitelist;
1291 int i;
1292
1293 for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) {
1294 if (entry->offset == reg->offset &&
1295 (1 << INTEL_INFO(dev)->gen & entry->gen_bitmask))
1296 break;
1297 }
1298
1299 if (i == ARRAY_SIZE(whitelist))
1300 return -EINVAL;
1301
1302 switch (entry->size) {
1303 case 8:
1304 reg->val = I915_READ64(reg->offset);
1305 break;
1306 case 4:
1307 reg->val = I915_READ(reg->offset);
1308 break;
1309 case 2:
1310 reg->val = I915_READ16(reg->offset);
1311 break;
1312 case 1:
1313 reg->val = I915_READ8(reg->offset);
1314 break;
1315 default:
1316 WARN_ON(1);
1317 return -EINVAL;
1318 }
1319
1320 return 0;
1321}
Linux kernel - Deliverables
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