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1da177e4 LT |
1 | /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*- |
2 | */ | |
0d6aa60b | 3 | /* |
bc54fd1a | 4 | * |
1da177e4 LT |
5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
6 | * All Rights Reserved. | |
bc54fd1a DA |
7 | * |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the | |
10 | * "Software"), to deal in the Software without restriction, including | |
11 | * without limitation the rights to use, copy, modify, merge, publish, | |
12 | * distribute, sub license, and/or sell copies of the Software, and to | |
13 | * permit persons to whom the Software is furnished to do so, subject to | |
14 | * the following conditions: | |
15 | * | |
16 | * The above copyright notice and this permission notice (including the | |
17 | * next paragraph) shall be included in all copies or substantial portions | |
18 | * of the Software. | |
19 | * | |
20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
27 | * | |
0d6aa60b | 28 | */ |
1da177e4 | 29 | |
5669fcac | 30 | #include <linux/device.h> |
760285e7 DH |
31 | #include <drm/drmP.h> |
32 | #include <drm/i915_drm.h> | |
1da177e4 | 33 | #include "i915_drv.h" |
990bbdad | 34 | #include "i915_trace.h" |
f49f0586 | 35 | #include "intel_drv.h" |
1da177e4 | 36 | |
79e53945 | 37 | #include <linux/console.h> |
e0cd3608 | 38 | #include <linux/module.h> |
d6102977 | 39 | #include <linux/pm_runtime.h> |
760285e7 | 40 | #include <drm/drm_crtc_helper.h> |
79e53945 | 41 | |
112b715e KH |
42 | static struct drm_driver driver; |
43 | ||
a57c774a AK |
44 | #define GEN_DEFAULT_PIPEOFFSETS \ |
45 | .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \ | |
46 | PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \ | |
47 | .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \ | |
48 | TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \ | |
a57c774a AK |
49 | .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET } |
50 | ||
84fd4f4e RB |
51 | #define GEN_CHV_PIPEOFFSETS \ |
52 | .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \ | |
53 | CHV_PIPE_C_OFFSET }, \ | |
54 | .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \ | |
55 | CHV_TRANSCODER_C_OFFSET, }, \ | |
84fd4f4e RB |
56 | .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \ |
57 | CHV_PALETTE_C_OFFSET } | |
a57c774a | 58 | |
5efb3e28 VS |
59 | #define CURSOR_OFFSETS \ |
60 | .cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET } | |
61 | ||
62 | #define IVB_CURSOR_OFFSETS \ | |
63 | .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET } | |
64 | ||
9a7e8492 | 65 | static const struct intel_device_info intel_i830_info = { |
7eb552ae | 66 | .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2, |
31578148 | 67 | .has_overlay = 1, .overlay_needs_physical = 1, |
73ae478c | 68 | .ring_mask = RENDER_RING, |
a57c774a | 69 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 70 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
71 | }; |
72 | ||
9a7e8492 | 73 | static const struct intel_device_info intel_845g_info = { |
7eb552ae | 74 | .gen = 2, .num_pipes = 1, |
31578148 | 75 | .has_overlay = 1, .overlay_needs_physical = 1, |
73ae478c | 76 | .ring_mask = RENDER_RING, |
a57c774a | 77 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 78 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
79 | }; |
80 | ||
9a7e8492 | 81 | static const struct intel_device_info intel_i85x_info = { |
7eb552ae | 82 | .gen = 2, .is_i85x = 1, .is_mobile = 1, .num_pipes = 2, |
5ce8ba7c | 83 | .cursor_needs_physical = 1, |
31578148 | 84 | .has_overlay = 1, .overlay_needs_physical = 1, |
fd70d52a | 85 | .has_fbc = 1, |
73ae478c | 86 | .ring_mask = RENDER_RING, |
a57c774a | 87 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 88 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
89 | }; |
90 | ||
9a7e8492 | 91 | static const struct intel_device_info intel_i865g_info = { |
7eb552ae | 92 | .gen = 2, .num_pipes = 1, |
31578148 | 93 | .has_overlay = 1, .overlay_needs_physical = 1, |
73ae478c | 94 | .ring_mask = RENDER_RING, |
a57c774a | 95 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 96 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
97 | }; |
98 | ||
9a7e8492 | 99 | static const struct intel_device_info intel_i915g_info = { |
7eb552ae | 100 | .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2, |
31578148 | 101 | .has_overlay = 1, .overlay_needs_physical = 1, |
73ae478c | 102 | .ring_mask = RENDER_RING, |
a57c774a | 103 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 104 | CURSOR_OFFSETS, |
cfdf1fa2 | 105 | }; |
9a7e8492 | 106 | static const struct intel_device_info intel_i915gm_info = { |
7eb552ae | 107 | .gen = 3, .is_mobile = 1, .num_pipes = 2, |
b295d1b6 | 108 | .cursor_needs_physical = 1, |
31578148 | 109 | .has_overlay = 1, .overlay_needs_physical = 1, |
a6c45cf0 | 110 | .supports_tv = 1, |
fd70d52a | 111 | .has_fbc = 1, |
73ae478c | 112 | .ring_mask = RENDER_RING, |
a57c774a | 113 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 114 | CURSOR_OFFSETS, |
cfdf1fa2 | 115 | }; |
9a7e8492 | 116 | static const struct intel_device_info intel_i945g_info = { |
7eb552ae | 117 | .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2, |
31578148 | 118 | .has_overlay = 1, .overlay_needs_physical = 1, |
73ae478c | 119 | .ring_mask = RENDER_RING, |
a57c774a | 120 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 121 | CURSOR_OFFSETS, |
cfdf1fa2 | 122 | }; |
9a7e8492 | 123 | static const struct intel_device_info intel_i945gm_info = { |
7eb552ae | 124 | .gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2, |
b295d1b6 | 125 | .has_hotplug = 1, .cursor_needs_physical = 1, |
31578148 | 126 | .has_overlay = 1, .overlay_needs_physical = 1, |
a6c45cf0 | 127 | .supports_tv = 1, |
fd70d52a | 128 | .has_fbc = 1, |
73ae478c | 129 | .ring_mask = RENDER_RING, |
a57c774a | 130 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 131 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
132 | }; |
133 | ||
9a7e8492 | 134 | static const struct intel_device_info intel_i965g_info = { |
7eb552ae | 135 | .gen = 4, .is_broadwater = 1, .num_pipes = 2, |
c96c3a8c | 136 | .has_hotplug = 1, |
31578148 | 137 | .has_overlay = 1, |
73ae478c | 138 | .ring_mask = RENDER_RING, |
a57c774a | 139 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 140 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
141 | }; |
142 | ||
9a7e8492 | 143 | static const struct intel_device_info intel_i965gm_info = { |
7eb552ae | 144 | .gen = 4, .is_crestline = 1, .num_pipes = 2, |
e3c4e5dd | 145 | .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1, |
31578148 | 146 | .has_overlay = 1, |
a6c45cf0 | 147 | .supports_tv = 1, |
73ae478c | 148 | .ring_mask = RENDER_RING, |
a57c774a | 149 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 150 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
151 | }; |
152 | ||
9a7e8492 | 153 | static const struct intel_device_info intel_g33_info = { |
7eb552ae | 154 | .gen = 3, .is_g33 = 1, .num_pipes = 2, |
c96c3a8c | 155 | .need_gfx_hws = 1, .has_hotplug = 1, |
31578148 | 156 | .has_overlay = 1, |
73ae478c | 157 | .ring_mask = RENDER_RING, |
a57c774a | 158 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 159 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
160 | }; |
161 | ||
9a7e8492 | 162 | static const struct intel_device_info intel_g45_info = { |
7eb552ae | 163 | .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2, |
c96c3a8c | 164 | .has_pipe_cxsr = 1, .has_hotplug = 1, |
73ae478c | 165 | .ring_mask = RENDER_RING | BSD_RING, |
a57c774a | 166 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 167 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
168 | }; |
169 | ||
9a7e8492 | 170 | static const struct intel_device_info intel_gm45_info = { |
7eb552ae | 171 | .gen = 4, .is_g4x = 1, .num_pipes = 2, |
e3c4e5dd | 172 | .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1, |
c96c3a8c | 173 | .has_pipe_cxsr = 1, .has_hotplug = 1, |
a6c45cf0 | 174 | .supports_tv = 1, |
73ae478c | 175 | .ring_mask = RENDER_RING | BSD_RING, |
a57c774a | 176 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 177 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
178 | }; |
179 | ||
9a7e8492 | 180 | static const struct intel_device_info intel_pineview_info = { |
7eb552ae | 181 | .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2, |
c96c3a8c | 182 | .need_gfx_hws = 1, .has_hotplug = 1, |
31578148 | 183 | .has_overlay = 1, |
a57c774a | 184 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 185 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
186 | }; |
187 | ||
9a7e8492 | 188 | static const struct intel_device_info intel_ironlake_d_info = { |
7eb552ae | 189 | .gen = 5, .num_pipes = 2, |
5a117db7 | 190 | .need_gfx_hws = 1, .has_hotplug = 1, |
73ae478c | 191 | .ring_mask = RENDER_RING | BSD_RING, |
a57c774a | 192 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 193 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
194 | }; |
195 | ||
9a7e8492 | 196 | static const struct intel_device_info intel_ironlake_m_info = { |
7eb552ae | 197 | .gen = 5, .is_mobile = 1, .num_pipes = 2, |
e3c4e5dd | 198 | .need_gfx_hws = 1, .has_hotplug = 1, |
c1a9f047 | 199 | .has_fbc = 1, |
73ae478c | 200 | .ring_mask = RENDER_RING | BSD_RING, |
a57c774a | 201 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 202 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
203 | }; |
204 | ||
9a7e8492 | 205 | static const struct intel_device_info intel_sandybridge_d_info = { |
7eb552ae | 206 | .gen = 6, .num_pipes = 2, |
c96c3a8c | 207 | .need_gfx_hws = 1, .has_hotplug = 1, |
cbaef0f1 | 208 | .has_fbc = 1, |
73ae478c | 209 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING, |
3d29b842 | 210 | .has_llc = 1, |
a57c774a | 211 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 212 | CURSOR_OFFSETS, |
f6e450a6 EA |
213 | }; |
214 | ||
9a7e8492 | 215 | static const struct intel_device_info intel_sandybridge_m_info = { |
7eb552ae | 216 | .gen = 6, .is_mobile = 1, .num_pipes = 2, |
c96c3a8c | 217 | .need_gfx_hws = 1, .has_hotplug = 1, |
9c04f015 | 218 | .has_fbc = 1, |
73ae478c | 219 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING, |
3d29b842 | 220 | .has_llc = 1, |
a57c774a | 221 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 222 | CURSOR_OFFSETS, |
a13e4093 EA |
223 | }; |
224 | ||
219f4fdb BW |
225 | #define GEN7_FEATURES \ |
226 | .gen = 7, .num_pipes = 3, \ | |
227 | .need_gfx_hws = 1, .has_hotplug = 1, \ | |
cbaef0f1 | 228 | .has_fbc = 1, \ |
73ae478c | 229 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \ |
ab484f8f | 230 | .has_llc = 1 |
219f4fdb | 231 | |
c76b615c | 232 | static const struct intel_device_info intel_ivybridge_d_info = { |
219f4fdb BW |
233 | GEN7_FEATURES, |
234 | .is_ivybridge = 1, | |
a57c774a | 235 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 236 | IVB_CURSOR_OFFSETS, |
c76b615c JB |
237 | }; |
238 | ||
239 | static const struct intel_device_info intel_ivybridge_m_info = { | |
219f4fdb BW |
240 | GEN7_FEATURES, |
241 | .is_ivybridge = 1, | |
242 | .is_mobile = 1, | |
a57c774a | 243 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 244 | IVB_CURSOR_OFFSETS, |
c76b615c JB |
245 | }; |
246 | ||
999bcdea BW |
247 | static const struct intel_device_info intel_ivybridge_q_info = { |
248 | GEN7_FEATURES, | |
249 | .is_ivybridge = 1, | |
250 | .num_pipes = 0, /* legal, last one wins */ | |
a57c774a | 251 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 252 | IVB_CURSOR_OFFSETS, |
999bcdea BW |
253 | }; |
254 | ||
70a3eb7a | 255 | static const struct intel_device_info intel_valleyview_m_info = { |
219f4fdb BW |
256 | GEN7_FEATURES, |
257 | .is_mobile = 1, | |
258 | .num_pipes = 2, | |
70a3eb7a | 259 | .is_valleyview = 1, |
fba5d532 | 260 | .display_mmio_offset = VLV_DISPLAY_BASE, |
cbaef0f1 | 261 | .has_fbc = 0, /* legal, last one wins */ |
30ccd964 | 262 | .has_llc = 0, /* legal, last one wins */ |
a57c774a | 263 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 264 | CURSOR_OFFSETS, |
70a3eb7a JB |
265 | }; |
266 | ||
267 | static const struct intel_device_info intel_valleyview_d_info = { | |
219f4fdb BW |
268 | GEN7_FEATURES, |
269 | .num_pipes = 2, | |
70a3eb7a | 270 | .is_valleyview = 1, |
fba5d532 | 271 | .display_mmio_offset = VLV_DISPLAY_BASE, |
cbaef0f1 | 272 | .has_fbc = 0, /* legal, last one wins */ |
30ccd964 | 273 | .has_llc = 0, /* legal, last one wins */ |
a57c774a | 274 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 275 | CURSOR_OFFSETS, |
70a3eb7a JB |
276 | }; |
277 | ||
4cae9ae0 | 278 | static const struct intel_device_info intel_haswell_d_info = { |
219f4fdb BW |
279 | GEN7_FEATURES, |
280 | .is_haswell = 1, | |
dd93be58 | 281 | .has_ddi = 1, |
30568c45 | 282 | .has_fpga_dbg = 1, |
73ae478c | 283 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, |
a57c774a | 284 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 285 | IVB_CURSOR_OFFSETS, |
4cae9ae0 ED |
286 | }; |
287 | ||
288 | static const struct intel_device_info intel_haswell_m_info = { | |
219f4fdb BW |
289 | GEN7_FEATURES, |
290 | .is_haswell = 1, | |
291 | .is_mobile = 1, | |
dd93be58 | 292 | .has_ddi = 1, |
30568c45 | 293 | .has_fpga_dbg = 1, |
73ae478c | 294 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, |
a57c774a | 295 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 296 | IVB_CURSOR_OFFSETS, |
c76b615c JB |
297 | }; |
298 | ||
4d4dead6 | 299 | static const struct intel_device_info intel_broadwell_d_info = { |
4b30553d | 300 | .gen = 8, .num_pipes = 3, |
4d4dead6 BW |
301 | .need_gfx_hws = 1, .has_hotplug = 1, |
302 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, | |
303 | .has_llc = 1, | |
304 | .has_ddi = 1, | |
8f94d24b | 305 | .has_fbc = 1, |
a57c774a | 306 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 307 | IVB_CURSOR_OFFSETS, |
4d4dead6 BW |
308 | }; |
309 | ||
310 | static const struct intel_device_info intel_broadwell_m_info = { | |
4b30553d | 311 | .gen = 8, .is_mobile = 1, .num_pipes = 3, |
4d4dead6 BW |
312 | .need_gfx_hws = 1, .has_hotplug = 1, |
313 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, | |
314 | .has_llc = 1, | |
315 | .has_ddi = 1, | |
8f94d24b | 316 | .has_fbc = 1, |
a57c774a | 317 | GEN_DEFAULT_PIPEOFFSETS, |
15d24aa5 | 318 | IVB_CURSOR_OFFSETS, |
4d4dead6 BW |
319 | }; |
320 | ||
fd3c269f ZY |
321 | static const struct intel_device_info intel_broadwell_gt3d_info = { |
322 | .gen = 8, .num_pipes = 3, | |
323 | .need_gfx_hws = 1, .has_hotplug = 1, | |
845f74a7 | 324 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, |
fd3c269f ZY |
325 | .has_llc = 1, |
326 | .has_ddi = 1, | |
327 | .has_fbc = 1, | |
328 | GEN_DEFAULT_PIPEOFFSETS, | |
15d24aa5 | 329 | IVB_CURSOR_OFFSETS, |
fd3c269f ZY |
330 | }; |
331 | ||
332 | static const struct intel_device_info intel_broadwell_gt3m_info = { | |
333 | .gen = 8, .is_mobile = 1, .num_pipes = 3, | |
334 | .need_gfx_hws = 1, .has_hotplug = 1, | |
845f74a7 | 335 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, |
fd3c269f ZY |
336 | .has_llc = 1, |
337 | .has_ddi = 1, | |
338 | .has_fbc = 1, | |
339 | GEN_DEFAULT_PIPEOFFSETS, | |
5efb3e28 | 340 | IVB_CURSOR_OFFSETS, |
fd3c269f ZY |
341 | }; |
342 | ||
7d87a7f7 VS |
343 | static const struct intel_device_info intel_cherryview_info = { |
344 | .is_preliminary = 1, | |
07fddb14 | 345 | .gen = 8, .num_pipes = 3, |
7d87a7f7 VS |
346 | .need_gfx_hws = 1, .has_hotplug = 1, |
347 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, | |
348 | .is_valleyview = 1, | |
349 | .display_mmio_offset = VLV_DISPLAY_BASE, | |
84fd4f4e | 350 | GEN_CHV_PIPEOFFSETS, |
5efb3e28 | 351 | CURSOR_OFFSETS, |
7d87a7f7 VS |
352 | }; |
353 | ||
a0a18075 JB |
354 | /* |
355 | * Make sure any device matches here are from most specific to most | |
356 | * general. For example, since the Quanta match is based on the subsystem | |
357 | * and subvendor IDs, we need it to come before the more general IVB | |
358 | * PCI ID matches, otherwise we'll use the wrong info struct above. | |
359 | */ | |
360 | #define INTEL_PCI_IDS \ | |
361 | INTEL_I830_IDS(&intel_i830_info), \ | |
362 | INTEL_I845G_IDS(&intel_845g_info), \ | |
363 | INTEL_I85X_IDS(&intel_i85x_info), \ | |
364 | INTEL_I865G_IDS(&intel_i865g_info), \ | |
365 | INTEL_I915G_IDS(&intel_i915g_info), \ | |
366 | INTEL_I915GM_IDS(&intel_i915gm_info), \ | |
367 | INTEL_I945G_IDS(&intel_i945g_info), \ | |
368 | INTEL_I945GM_IDS(&intel_i945gm_info), \ | |
369 | INTEL_I965G_IDS(&intel_i965g_info), \ | |
370 | INTEL_G33_IDS(&intel_g33_info), \ | |
371 | INTEL_I965GM_IDS(&intel_i965gm_info), \ | |
372 | INTEL_GM45_IDS(&intel_gm45_info), \ | |
373 | INTEL_G45_IDS(&intel_g45_info), \ | |
374 | INTEL_PINEVIEW_IDS(&intel_pineview_info), \ | |
375 | INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info), \ | |
376 | INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info), \ | |
377 | INTEL_SNB_D_IDS(&intel_sandybridge_d_info), \ | |
378 | INTEL_SNB_M_IDS(&intel_sandybridge_m_info), \ | |
379 | INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */ \ | |
380 | INTEL_IVB_M_IDS(&intel_ivybridge_m_info), \ | |
381 | INTEL_IVB_D_IDS(&intel_ivybridge_d_info), \ | |
382 | INTEL_HSW_D_IDS(&intel_haswell_d_info), \ | |
383 | INTEL_HSW_M_IDS(&intel_haswell_m_info), \ | |
384 | INTEL_VLV_M_IDS(&intel_valleyview_m_info), \ | |
4d4dead6 | 385 | INTEL_VLV_D_IDS(&intel_valleyview_d_info), \ |
fd3c269f ZY |
386 | INTEL_BDW_GT12M_IDS(&intel_broadwell_m_info), \ |
387 | INTEL_BDW_GT12D_IDS(&intel_broadwell_d_info), \ | |
388 | INTEL_BDW_GT3M_IDS(&intel_broadwell_gt3m_info), \ | |
7d87a7f7 VS |
389 | INTEL_BDW_GT3D_IDS(&intel_broadwell_gt3d_info), \ |
390 | INTEL_CHV_IDS(&intel_cherryview_info) | |
a0a18075 | 391 | |
6103da0d | 392 | static const struct pci_device_id pciidlist[] = { /* aka */ |
a0a18075 | 393 | INTEL_PCI_IDS, |
49ae35f2 | 394 | {0, 0, 0} |
1da177e4 LT |
395 | }; |
396 | ||
79e53945 JB |
397 | #if defined(CONFIG_DRM_I915_KMS) |
398 | MODULE_DEVICE_TABLE(pci, pciidlist); | |
399 | #endif | |
400 | ||
0206e353 | 401 | void intel_detect_pch(struct drm_device *dev) |
3bad0781 ZW |
402 | { |
403 | struct drm_i915_private *dev_priv = dev->dev_private; | |
bcdb72ac | 404 | struct pci_dev *pch = NULL; |
3bad0781 | 405 | |
ce1bb329 BW |
406 | /* In all current cases, num_pipes is equivalent to the PCH_NOP setting |
407 | * (which really amounts to a PCH but no South Display). | |
408 | */ | |
409 | if (INTEL_INFO(dev)->num_pipes == 0) { | |
410 | dev_priv->pch_type = PCH_NOP; | |
ce1bb329 BW |
411 | return; |
412 | } | |
413 | ||
3bad0781 ZW |
414 | /* |
415 | * The reason to probe ISA bridge instead of Dev31:Fun0 is to | |
416 | * make graphics device passthrough work easy for VMM, that only | |
417 | * need to expose ISA bridge to let driver know the real hardware | |
418 | * underneath. This is a requirement from virtualization team. | |
6a9c4b35 RG |
419 | * |
420 | * In some virtualized environments (e.g. XEN), there is irrelevant | |
421 | * ISA bridge in the system. To work reliably, we should scan trhough | |
422 | * all the ISA bridge devices and check for the first match, instead | |
423 | * of only checking the first one. | |
3bad0781 | 424 | */ |
bcdb72ac | 425 | while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) { |
3bad0781 | 426 | if (pch->vendor == PCI_VENDOR_ID_INTEL) { |
bcdb72ac | 427 | unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK; |
17a303ec | 428 | dev_priv->pch_id = id; |
3bad0781 | 429 | |
90711d50 JB |
430 | if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) { |
431 | dev_priv->pch_type = PCH_IBX; | |
432 | DRM_DEBUG_KMS("Found Ibex Peak PCH\n"); | |
7fcb83cd | 433 | WARN_ON(!IS_GEN5(dev)); |
90711d50 | 434 | } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) { |
3bad0781 ZW |
435 | dev_priv->pch_type = PCH_CPT; |
436 | DRM_DEBUG_KMS("Found CougarPoint PCH\n"); | |
7fcb83cd | 437 | WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev))); |
c792513b JB |
438 | } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) { |
439 | /* PantherPoint is CPT compatible */ | |
440 | dev_priv->pch_type = PCH_CPT; | |
492ab669 | 441 | DRM_DEBUG_KMS("Found PantherPoint PCH\n"); |
7fcb83cd | 442 | WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev))); |
eb877ebf ED |
443 | } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) { |
444 | dev_priv->pch_type = PCH_LPT; | |
445 | DRM_DEBUG_KMS("Found LynxPoint PCH\n"); | |
7fcb83cd | 446 | WARN_ON(!IS_HASWELL(dev)); |
08e1413d | 447 | WARN_ON(IS_ULT(dev)); |
018f52c9 PZ |
448 | } else if (IS_BROADWELL(dev)) { |
449 | dev_priv->pch_type = PCH_LPT; | |
450 | dev_priv->pch_id = | |
451 | INTEL_PCH_LPT_LP_DEVICE_ID_TYPE; | |
452 | DRM_DEBUG_KMS("This is Broadwell, assuming " | |
453 | "LynxPoint LP PCH\n"); | |
e76e0634 BW |
454 | } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { |
455 | dev_priv->pch_type = PCH_LPT; | |
456 | DRM_DEBUG_KMS("Found LynxPoint LP PCH\n"); | |
457 | WARN_ON(!IS_HASWELL(dev)); | |
458 | WARN_ON(!IS_ULT(dev)); | |
bcdb72ac ID |
459 | } else |
460 | continue; | |
461 | ||
6a9c4b35 | 462 | break; |
3bad0781 | 463 | } |
3bad0781 | 464 | } |
6a9c4b35 | 465 | if (!pch) |
bcdb72ac ID |
466 | DRM_DEBUG_KMS("No PCH found.\n"); |
467 | ||
468 | pci_dev_put(pch); | |
3bad0781 ZW |
469 | } |
470 | ||
2911a35b BW |
471 | bool i915_semaphore_is_enabled(struct drm_device *dev) |
472 | { | |
473 | if (INTEL_INFO(dev)->gen < 6) | |
a08acaf2 | 474 | return false; |
2911a35b | 475 | |
d330a953 JN |
476 | if (i915.semaphores >= 0) |
477 | return i915.semaphores; | |
2911a35b | 478 | |
c923facd JN |
479 | /* Until we get further testing... */ |
480 | if (IS_GEN8(dev)) | |
481 | return false; | |
482 | ||
59de3295 | 483 | #ifdef CONFIG_INTEL_IOMMU |
2911a35b | 484 | /* Enable semaphores on SNB when IO remapping is off */ |
59de3295 DV |
485 | if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) |
486 | return false; | |
487 | #endif | |
2911a35b | 488 | |
a08acaf2 | 489 | return true; |
2911a35b BW |
490 | } |
491 | ||
84b79f8d | 492 | static int i915_drm_freeze(struct drm_device *dev) |
ba8bbcf6 | 493 | { |
61caf87c | 494 | struct drm_i915_private *dev_priv = dev->dev_private; |
24576d23 | 495 | struct drm_crtc *crtc; |
61caf87c | 496 | |
8a187455 PZ |
497 | intel_runtime_pm_get(dev_priv); |
498 | ||
b8efb17b ZR |
499 | /* ignore lid events during suspend */ |
500 | mutex_lock(&dev_priv->modeset_restore_lock); | |
501 | dev_priv->modeset_restore = MODESET_SUSPENDED; | |
502 | mutex_unlock(&dev_priv->modeset_restore_lock); | |
503 | ||
c67a470b PZ |
504 | /* We do a lot of poking in a lot of registers, make sure they work |
505 | * properly. */ | |
da7e29bd | 506 | intel_display_set_init_power(dev_priv, true); |
cb10799c | 507 | |
5bcf719b DA |
508 | drm_kms_helper_poll_disable(dev); |
509 | ||
ba8bbcf6 | 510 | pci_save_state(dev->pdev); |
ba8bbcf6 | 511 | |
5669fcac | 512 | /* If KMS is active, we do the leavevt stuff here */ |
226485e9 | 513 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
db1b76ca DV |
514 | int error; |
515 | ||
45c5f202 | 516 | error = i915_gem_suspend(dev); |
84b79f8d | 517 | if (error) { |
226485e9 | 518 | dev_err(&dev->pdev->dev, |
84b79f8d RW |
519 | "GEM idle failed, resume might fail\n"); |
520 | return error; | |
521 | } | |
a261b246 | 522 | |
226485e9 | 523 | drm_irq_uninstall(dev); |
15239099 | 524 | dev_priv->enable_hotplug_processing = false; |
fe5b1886 ID |
525 | |
526 | intel_disable_gt_powersave(dev); | |
527 | ||
24576d23 JB |
528 | /* |
529 | * Disable CRTCs directly since we want to preserve sw state | |
530 | * for _thaw. | |
531 | */ | |
6e9f798d | 532 | drm_modeset_lock_all(dev); |
f7ef3fa7 | 533 | for_each_crtc(dev, crtc) { |
24576d23 | 534 | dev_priv->display.crtc_disable(crtc); |
f7ef3fa7 | 535 | } |
6e9f798d | 536 | drm_modeset_unlock_all(dev); |
7d708ee4 ID |
537 | |
538 | intel_modeset_suspend_hw(dev); | |
5669fcac JB |
539 | } |
540 | ||
828c7908 BW |
541 | i915_gem_suspend_gtt_mappings(dev); |
542 | ||
9e06dd39 JB |
543 | i915_save_state(dev); |
544 | ||
44834a67 | 545 | intel_opregion_fini(dev); |
28d85cd3 | 546 | intel_uncore_fini(dev); |
8ee1c3db | 547 | |
3fa016a0 | 548 | console_lock(); |
b6f3eff7 | 549 | intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED); |
3fa016a0 DA |
550 | console_unlock(); |
551 | ||
62d5d69b MK |
552 | dev_priv->suspend_count++; |
553 | ||
61caf87c | 554 | return 0; |
84b79f8d RW |
555 | } |
556 | ||
6a9ee8af | 557 | int i915_suspend(struct drm_device *dev, pm_message_t state) |
84b79f8d RW |
558 | { |
559 | int error; | |
560 | ||
561 | if (!dev || !dev->dev_private) { | |
562 | DRM_ERROR("dev: %p\n", dev); | |
563 | DRM_ERROR("DRM not initialized, aborting suspend.\n"); | |
564 | return -ENODEV; | |
565 | } | |
566 | ||
567 | if (state.event == PM_EVENT_PRETHAW) | |
568 | return 0; | |
569 | ||
5bcf719b DA |
570 | |
571 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) | |
572 | return 0; | |
6eecba33 | 573 | |
84b79f8d RW |
574 | error = i915_drm_freeze(dev); |
575 | if (error) | |
576 | return error; | |
577 | ||
b932ccb5 DA |
578 | if (state.event == PM_EVENT_SUSPEND) { |
579 | /* Shut down the device */ | |
580 | pci_disable_device(dev->pdev); | |
581 | pci_set_power_state(dev->pdev, PCI_D3hot); | |
582 | } | |
ba8bbcf6 JB |
583 | |
584 | return 0; | |
585 | } | |
586 | ||
073f34d9 JB |
587 | void intel_console_resume(struct work_struct *work) |
588 | { | |
589 | struct drm_i915_private *dev_priv = | |
590 | container_of(work, struct drm_i915_private, | |
591 | console_resume_work); | |
592 | struct drm_device *dev = dev_priv->dev; | |
593 | ||
594 | console_lock(); | |
b6f3eff7 | 595 | intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING); |
073f34d9 JB |
596 | console_unlock(); |
597 | } | |
598 | ||
76c4b250 | 599 | static int i915_drm_thaw_early(struct drm_device *dev) |
ba8bbcf6 | 600 | { |
5669fcac | 601 | struct drm_i915_private *dev_priv = dev->dev_private; |
8ee1c3db | 602 | |
10018603 | 603 | intel_uncore_early_sanitize(dev, true); |
9d49c0ef | 604 | intel_uncore_sanitize(dev); |
76c4b250 ID |
605 | intel_power_domains_init_hw(dev_priv); |
606 | ||
607 | return 0; | |
608 | } | |
609 | ||
610 | static int __i915_drm_thaw(struct drm_device *dev, bool restore_gtt_mappings) | |
611 | { | |
612 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9d49c0ef PZ |
613 | |
614 | if (drm_core_check_feature(dev, DRIVER_MODESET) && | |
615 | restore_gtt_mappings) { | |
616 | mutex_lock(&dev->struct_mutex); | |
617 | i915_gem_restore_gtt_mappings(dev); | |
618 | mutex_unlock(&dev->struct_mutex); | |
619 | } | |
620 | ||
61caf87c | 621 | i915_restore_state(dev); |
44834a67 | 622 | intel_opregion_setup(dev); |
61caf87c | 623 | |
5669fcac JB |
624 | /* KMS EnterVT equivalent */ |
625 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { | |
dde86e2d | 626 | intel_init_pch_refclk(dev); |
754970ee | 627 | drm_mode_config_reset(dev); |
1833b134 | 628 | |
5669fcac | 629 | mutex_lock(&dev->struct_mutex); |
074c6ada CW |
630 | if (i915_gem_init_hw(dev)) { |
631 | DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n"); | |
632 | atomic_set_mask(I915_WEDGED, &dev_priv->gpu_error.reset_counter); | |
633 | } | |
5669fcac | 634 | mutex_unlock(&dev->struct_mutex); |
226485e9 | 635 | |
15239099 | 636 | /* We need working interrupts for modeset enabling ... */ |
bb0f1b5c | 637 | drm_irq_install(dev, dev->pdev->irq); |
15239099 | 638 | |
1833b134 | 639 | intel_modeset_init_hw(dev); |
24576d23 JB |
640 | |
641 | drm_modeset_lock_all(dev); | |
642 | intel_modeset_setup_hw_state(dev, true); | |
643 | drm_modeset_unlock_all(dev); | |
15239099 DV |
644 | |
645 | /* | |
646 | * ... but also need to make sure that hotplug processing | |
647 | * doesn't cause havoc. Like in the driver load code we don't | |
648 | * bother with the tiny race here where we might loose hotplug | |
649 | * notifications. | |
650 | * */ | |
20afbda2 | 651 | intel_hpd_init(dev); |
15239099 | 652 | dev_priv->enable_hotplug_processing = true; |
bb60b969 | 653 | /* Config may have changed between suspend and resume */ |
1ff74cf1 | 654 | drm_helper_hpd_irq_event(dev); |
d5bb081b | 655 | } |
1daed3fb | 656 | |
44834a67 CW |
657 | intel_opregion_init(dev); |
658 | ||
073f34d9 JB |
659 | /* |
660 | * The console lock can be pretty contented on resume due | |
661 | * to all the printk activity. Try to keep it out of the hot | |
662 | * path of resume if possible. | |
663 | */ | |
664 | if (console_trylock()) { | |
b6f3eff7 | 665 | intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING); |
073f34d9 JB |
666 | console_unlock(); |
667 | } else { | |
668 | schedule_work(&dev_priv->console_resume_work); | |
669 | } | |
670 | ||
b8efb17b ZR |
671 | mutex_lock(&dev_priv->modeset_restore_lock); |
672 | dev_priv->modeset_restore = MODESET_DONE; | |
673 | mutex_unlock(&dev_priv->modeset_restore_lock); | |
8a187455 PZ |
674 | |
675 | intel_runtime_pm_put(dev_priv); | |
074c6ada | 676 | return 0; |
84b79f8d RW |
677 | } |
678 | ||
1abd02e2 JB |
679 | static int i915_drm_thaw(struct drm_device *dev) |
680 | { | |
7f16e5c1 | 681 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
828c7908 | 682 | i915_check_and_clear_faults(dev); |
1abd02e2 | 683 | |
9d49c0ef | 684 | return __i915_drm_thaw(dev, true); |
84b79f8d RW |
685 | } |
686 | ||
76c4b250 | 687 | static int i915_resume_early(struct drm_device *dev) |
84b79f8d | 688 | { |
5bcf719b DA |
689 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
690 | return 0; | |
691 | ||
76c4b250 ID |
692 | /* |
693 | * We have a resume ordering issue with the snd-hda driver also | |
694 | * requiring our device to be power up. Due to the lack of a | |
695 | * parent/child relationship we currently solve this with an early | |
696 | * resume hook. | |
697 | * | |
698 | * FIXME: This should be solved with a special hdmi sink device or | |
699 | * similar so that power domains can be employed. | |
700 | */ | |
84b79f8d RW |
701 | if (pci_enable_device(dev->pdev)) |
702 | return -EIO; | |
703 | ||
704 | pci_set_master(dev->pdev); | |
705 | ||
76c4b250 ID |
706 | return i915_drm_thaw_early(dev); |
707 | } | |
708 | ||
709 | int i915_resume(struct drm_device *dev) | |
710 | { | |
711 | struct drm_i915_private *dev_priv = dev->dev_private; | |
712 | int ret; | |
713 | ||
1abd02e2 JB |
714 | /* |
715 | * Platforms with opregion should have sane BIOS, older ones (gen3 and | |
9d49c0ef PZ |
716 | * earlier) need to restore the GTT mappings since the BIOS might clear |
717 | * all our scratch PTEs. | |
1abd02e2 | 718 | */ |
9d49c0ef | 719 | ret = __i915_drm_thaw(dev, !dev_priv->opregion.header); |
6eecba33 CW |
720 | if (ret) |
721 | return ret; | |
722 | ||
723 | drm_kms_helper_poll_enable(dev); | |
724 | return 0; | |
ba8bbcf6 JB |
725 | } |
726 | ||
76c4b250 ID |
727 | static int i915_resume_legacy(struct drm_device *dev) |
728 | { | |
729 | i915_resume_early(dev); | |
730 | i915_resume(dev); | |
731 | ||
732 | return 0; | |
733 | } | |
734 | ||
11ed50ec | 735 | /** |
f3953dcb | 736 | * i915_reset - reset chip after a hang |
11ed50ec | 737 | * @dev: drm device to reset |
11ed50ec BG |
738 | * |
739 | * Reset the chip. Useful if a hang is detected. Returns zero on successful | |
740 | * reset or otherwise an error code. | |
741 | * | |
742 | * Procedure is fairly simple: | |
743 | * - reset the chip using the reset reg | |
744 | * - re-init context state | |
745 | * - re-init hardware status page | |
746 | * - re-init ring buffer | |
747 | * - re-init interrupt state | |
748 | * - re-init display | |
749 | */ | |
d4b8bb2a | 750 | int i915_reset(struct drm_device *dev) |
11ed50ec | 751 | { |
50227e1c | 752 | struct drm_i915_private *dev_priv = dev->dev_private; |
2e7c8ee7 | 753 | bool simulated; |
0573ed4a | 754 | int ret; |
11ed50ec | 755 | |
d330a953 | 756 | if (!i915.reset) |
d78cb50b CW |
757 | return 0; |
758 | ||
d54a02c0 | 759 | mutex_lock(&dev->struct_mutex); |
11ed50ec | 760 | |
069efc1d | 761 | i915_gem_reset(dev); |
77f01230 | 762 | |
2e7c8ee7 CW |
763 | simulated = dev_priv->gpu_error.stop_rings != 0; |
764 | ||
be62acb4 MK |
765 | ret = intel_gpu_reset(dev); |
766 | ||
767 | /* Also reset the gpu hangman. */ | |
768 | if (simulated) { | |
769 | DRM_INFO("Simulated gpu hang, resetting stop_rings\n"); | |
770 | dev_priv->gpu_error.stop_rings = 0; | |
771 | if (ret == -ENODEV) { | |
f2d91a2c DV |
772 | DRM_INFO("Reset not implemented, but ignoring " |
773 | "error for simulated gpu hangs\n"); | |
be62acb4 MK |
774 | ret = 0; |
775 | } | |
2e7c8ee7 | 776 | } |
be62acb4 | 777 | |
0573ed4a | 778 | if (ret) { |
f2d91a2c | 779 | DRM_ERROR("Failed to reset chip: %i\n", ret); |
f953c935 | 780 | mutex_unlock(&dev->struct_mutex); |
f803aa55 | 781 | return ret; |
11ed50ec BG |
782 | } |
783 | ||
784 | /* Ok, now get things going again... */ | |
785 | ||
786 | /* | |
787 | * Everything depends on having the GTT running, so we need to start | |
788 | * there. Fortunately we don't need to do this unless we reset the | |
789 | * chip at a PCI level. | |
790 | * | |
791 | * Next we need to restore the context, but we don't use those | |
792 | * yet either... | |
793 | * | |
794 | * Ring buffer needs to be re-initialized in the KMS case, or if X | |
795 | * was running at the time of the reset (i.e. we weren't VT | |
796 | * switched away). | |
797 | */ | |
798 | if (drm_core_check_feature(dev, DRIVER_MODESET) || | |
db1b76ca | 799 | !dev_priv->ums.mm_suspended) { |
db1b76ca | 800 | dev_priv->ums.mm_suspended = 0; |
75a6898f | 801 | |
3d57e5bd | 802 | ret = i915_gem_init_hw(dev); |
8e88a2bd | 803 | mutex_unlock(&dev->struct_mutex); |
3d57e5bd BW |
804 | if (ret) { |
805 | DRM_ERROR("Failed hw init on reset %d\n", ret); | |
806 | return ret; | |
807 | } | |
f817586c | 808 | |
e090c53b | 809 | /* |
78ad455f DV |
810 | * FIXME: This races pretty badly against concurrent holders of |
811 | * ring interrupts. This is possible since we've started to drop | |
812 | * dev->struct_mutex in select places when waiting for the gpu. | |
e090c53b | 813 | */ |
dd0a1aa1 | 814 | |
78ad455f DV |
815 | /* |
816 | * rps/rc6 re-init is necessary to restore state lost after the | |
817 | * reset and the re-install of gt irqs. Skip for ironlake per | |
dd0a1aa1 | 818 | * previous concerns that it doesn't respond well to some forms |
78ad455f DV |
819 | * of re-init after reset. |
820 | */ | |
dc1d0136 | 821 | if (INTEL_INFO(dev)->gen > 5) |
c6df39b5 | 822 | intel_reset_gt_powersave(dev); |
dd0a1aa1 | 823 | |
20afbda2 | 824 | intel_hpd_init(dev); |
bcbc324a DV |
825 | } else { |
826 | mutex_unlock(&dev->struct_mutex); | |
11ed50ec BG |
827 | } |
828 | ||
11ed50ec BG |
829 | return 0; |
830 | } | |
831 | ||
56550d94 | 832 | static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) |
112b715e | 833 | { |
01a06850 DV |
834 | struct intel_device_info *intel_info = |
835 | (struct intel_device_info *) ent->driver_data; | |
836 | ||
d330a953 | 837 | if (IS_PRELIMINARY_HW(intel_info) && !i915.preliminary_hw_support) { |
b833d685 BW |
838 | DRM_INFO("This hardware requires preliminary hardware support.\n" |
839 | "See CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT, and/or modparam preliminary_hw_support\n"); | |
840 | return -ENODEV; | |
841 | } | |
842 | ||
5fe49d86 CW |
843 | /* Only bind to function 0 of the device. Early generations |
844 | * used function 1 as a placeholder for multi-head. This causes | |
845 | * us confusion instead, especially on the systems where both | |
846 | * functions have the same PCI-ID! | |
847 | */ | |
848 | if (PCI_FUNC(pdev->devfn)) | |
849 | return -ENODEV; | |
850 | ||
24986ee0 | 851 | driver.driver_features &= ~(DRIVER_USE_AGP); |
01a06850 | 852 | |
dcdb1674 | 853 | return drm_get_pci_dev(pdev, ent, &driver); |
112b715e KH |
854 | } |
855 | ||
856 | static void | |
857 | i915_pci_remove(struct pci_dev *pdev) | |
858 | { | |
859 | struct drm_device *dev = pci_get_drvdata(pdev); | |
860 | ||
861 | drm_put_dev(dev); | |
862 | } | |
863 | ||
84b79f8d | 864 | static int i915_pm_suspend(struct device *dev) |
112b715e | 865 | { |
84b79f8d RW |
866 | struct pci_dev *pdev = to_pci_dev(dev); |
867 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
112b715e | 868 | |
84b79f8d RW |
869 | if (!drm_dev || !drm_dev->dev_private) { |
870 | dev_err(dev, "DRM not initialized, aborting suspend.\n"); | |
871 | return -ENODEV; | |
872 | } | |
112b715e | 873 | |
5bcf719b DA |
874 | if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
875 | return 0; | |
876 | ||
76c4b250 ID |
877 | return i915_drm_freeze(drm_dev); |
878 | } | |
879 | ||
880 | static int i915_pm_suspend_late(struct device *dev) | |
881 | { | |
882 | struct pci_dev *pdev = to_pci_dev(dev); | |
883 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
884 | ||
885 | /* | |
886 | * We have a suspedn ordering issue with the snd-hda driver also | |
887 | * requiring our device to be power up. Due to the lack of a | |
888 | * parent/child relationship we currently solve this with an late | |
889 | * suspend hook. | |
890 | * | |
891 | * FIXME: This should be solved with a special hdmi sink device or | |
892 | * similar so that power domains can be employed. | |
893 | */ | |
894 | if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF) | |
895 | return 0; | |
112b715e | 896 | |
84b79f8d RW |
897 | pci_disable_device(pdev); |
898 | pci_set_power_state(pdev, PCI_D3hot); | |
cbda12d7 | 899 | |
84b79f8d | 900 | return 0; |
cbda12d7 ZW |
901 | } |
902 | ||
76c4b250 ID |
903 | static int i915_pm_resume_early(struct device *dev) |
904 | { | |
905 | struct pci_dev *pdev = to_pci_dev(dev); | |
906 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
907 | ||
908 | return i915_resume_early(drm_dev); | |
909 | } | |
910 | ||
84b79f8d | 911 | static int i915_pm_resume(struct device *dev) |
cbda12d7 | 912 | { |
84b79f8d RW |
913 | struct pci_dev *pdev = to_pci_dev(dev); |
914 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
915 | ||
916 | return i915_resume(drm_dev); | |
cbda12d7 ZW |
917 | } |
918 | ||
84b79f8d | 919 | static int i915_pm_freeze(struct device *dev) |
cbda12d7 | 920 | { |
84b79f8d RW |
921 | struct pci_dev *pdev = to_pci_dev(dev); |
922 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
923 | ||
924 | if (!drm_dev || !drm_dev->dev_private) { | |
925 | dev_err(dev, "DRM not initialized, aborting suspend.\n"); | |
926 | return -ENODEV; | |
927 | } | |
928 | ||
929 | return i915_drm_freeze(drm_dev); | |
cbda12d7 ZW |
930 | } |
931 | ||
76c4b250 ID |
932 | static int i915_pm_thaw_early(struct device *dev) |
933 | { | |
934 | struct pci_dev *pdev = to_pci_dev(dev); | |
935 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
936 | ||
937 | return i915_drm_thaw_early(drm_dev); | |
938 | } | |
939 | ||
84b79f8d | 940 | static int i915_pm_thaw(struct device *dev) |
cbda12d7 | 941 | { |
84b79f8d RW |
942 | struct pci_dev *pdev = to_pci_dev(dev); |
943 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
944 | ||
945 | return i915_drm_thaw(drm_dev); | |
cbda12d7 ZW |
946 | } |
947 | ||
84b79f8d | 948 | static int i915_pm_poweroff(struct device *dev) |
cbda12d7 | 949 | { |
84b79f8d RW |
950 | struct pci_dev *pdev = to_pci_dev(dev); |
951 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
84b79f8d | 952 | |
61caf87c | 953 | return i915_drm_freeze(drm_dev); |
cbda12d7 ZW |
954 | } |
955 | ||
0ab9cfeb | 956 | static int hsw_runtime_suspend(struct drm_i915_private *dev_priv) |
97bea207 | 957 | { |
414de7a0 | 958 | hsw_enable_pc8(dev_priv); |
0ab9cfeb ID |
959 | |
960 | return 0; | |
97bea207 PZ |
961 | } |
962 | ||
0ab9cfeb | 963 | static int snb_runtime_resume(struct drm_i915_private *dev_priv) |
9a952a0d PZ |
964 | { |
965 | struct drm_device *dev = dev_priv->dev; | |
966 | ||
9a952a0d | 967 | intel_init_pch_refclk(dev); |
0ab9cfeb ID |
968 | |
969 | return 0; | |
9a952a0d PZ |
970 | } |
971 | ||
0ab9cfeb | 972 | static int hsw_runtime_resume(struct drm_i915_private *dev_priv) |
97bea207 | 973 | { |
414de7a0 | 974 | hsw_disable_pc8(dev_priv); |
0ab9cfeb ID |
975 | |
976 | return 0; | |
97bea207 PZ |
977 | } |
978 | ||
ddeea5b0 ID |
979 | /* |
980 | * Save all Gunit registers that may be lost after a D3 and a subsequent | |
981 | * S0i[R123] transition. The list of registers needing a save/restore is | |
982 | * defined in the VLV2_S0IXRegs document. This documents marks all Gunit | |
983 | * registers in the following way: | |
984 | * - Driver: saved/restored by the driver | |
985 | * - Punit : saved/restored by the Punit firmware | |
986 | * - No, w/o marking: no need to save/restore, since the register is R/O or | |
987 | * used internally by the HW in a way that doesn't depend | |
988 | * keeping the content across a suspend/resume. | |
989 | * - Debug : used for debugging | |
990 | * | |
991 | * We save/restore all registers marked with 'Driver', with the following | |
992 | * exceptions: | |
993 | * - Registers out of use, including also registers marked with 'Debug'. | |
994 | * These have no effect on the driver's operation, so we don't save/restore | |
995 | * them to reduce the overhead. | |
996 | * - Registers that are fully setup by an initialization function called from | |
997 | * the resume path. For example many clock gating and RPS/RC6 registers. | |
998 | * - Registers that provide the right functionality with their reset defaults. | |
999 | * | |
1000 | * TODO: Except for registers that based on the above 3 criteria can be safely | |
1001 | * ignored, we save/restore all others, practically treating the HW context as | |
1002 | * a black-box for the driver. Further investigation is needed to reduce the | |
1003 | * saved/restored registers even further, by following the same 3 criteria. | |
1004 | */ | |
1005 | static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv) | |
1006 | { | |
1007 | struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state; | |
1008 | int i; | |
1009 | ||
1010 | /* GAM 0x4000-0x4770 */ | |
1011 | s->wr_watermark = I915_READ(GEN7_WR_WATERMARK); | |
1012 | s->gfx_prio_ctrl = I915_READ(GEN7_GFX_PRIO_CTRL); | |
1013 | s->arb_mode = I915_READ(ARB_MODE); | |
1014 | s->gfx_pend_tlb0 = I915_READ(GEN7_GFX_PEND_TLB0); | |
1015 | s->gfx_pend_tlb1 = I915_READ(GEN7_GFX_PEND_TLB1); | |
1016 | ||
1017 | for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++) | |
1018 | s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS_BASE + i * 4); | |
1019 | ||
1020 | s->media_max_req_count = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT); | |
1021 | s->gfx_max_req_count = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT); | |
1022 | ||
1023 | s->render_hwsp = I915_READ(RENDER_HWS_PGA_GEN7); | |
1024 | s->ecochk = I915_READ(GAM_ECOCHK); | |
1025 | s->bsd_hwsp = I915_READ(BSD_HWS_PGA_GEN7); | |
1026 | s->blt_hwsp = I915_READ(BLT_HWS_PGA_GEN7); | |
1027 | ||
1028 | s->tlb_rd_addr = I915_READ(GEN7_TLB_RD_ADDR); | |
1029 | ||
1030 | /* MBC 0x9024-0x91D0, 0x8500 */ | |
1031 | s->g3dctl = I915_READ(VLV_G3DCTL); | |
1032 | s->gsckgctl = I915_READ(VLV_GSCKGCTL); | |
1033 | s->mbctl = I915_READ(GEN6_MBCTL); | |
1034 | ||
1035 | /* GCP 0x9400-0x9424, 0x8100-0x810C */ | |
1036 | s->ucgctl1 = I915_READ(GEN6_UCGCTL1); | |
1037 | s->ucgctl3 = I915_READ(GEN6_UCGCTL3); | |
1038 | s->rcgctl1 = I915_READ(GEN6_RCGCTL1); | |
1039 | s->rcgctl2 = I915_READ(GEN6_RCGCTL2); | |
1040 | s->rstctl = I915_READ(GEN6_RSTCTL); | |
1041 | s->misccpctl = I915_READ(GEN7_MISCCPCTL); | |
1042 | ||
1043 | /* GPM 0xA000-0xAA84, 0x8000-0x80FC */ | |
1044 | s->gfxpause = I915_READ(GEN6_GFXPAUSE); | |
1045 | s->rpdeuhwtc = I915_READ(GEN6_RPDEUHWTC); | |
1046 | s->rpdeuc = I915_READ(GEN6_RPDEUC); | |
1047 | s->ecobus = I915_READ(ECOBUS); | |
1048 | s->pwrdwnupctl = I915_READ(VLV_PWRDWNUPCTL); | |
1049 | s->rp_down_timeout = I915_READ(GEN6_RP_DOWN_TIMEOUT); | |
1050 | s->rp_deucsw = I915_READ(GEN6_RPDEUCSW); | |
1051 | s->rcubmabdtmr = I915_READ(GEN6_RCUBMABDTMR); | |
1052 | s->rcedata = I915_READ(VLV_RCEDATA); | |
1053 | s->spare2gh = I915_READ(VLV_SPAREG2H); | |
1054 | ||
1055 | /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */ | |
1056 | s->gt_imr = I915_READ(GTIMR); | |
1057 | s->gt_ier = I915_READ(GTIER); | |
1058 | s->pm_imr = I915_READ(GEN6_PMIMR); | |
1059 | s->pm_ier = I915_READ(GEN6_PMIER); | |
1060 | ||
1061 | for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++) | |
1062 | s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH_BASE + i * 4); | |
1063 | ||
1064 | /* GT SA CZ domain, 0x100000-0x138124 */ | |
1065 | s->tilectl = I915_READ(TILECTL); | |
1066 | s->gt_fifoctl = I915_READ(GTFIFOCTL); | |
1067 | s->gtlc_wake_ctrl = I915_READ(VLV_GTLC_WAKE_CTRL); | |
1068 | s->gtlc_survive = I915_READ(VLV_GTLC_SURVIVABILITY_REG); | |
1069 | s->pmwgicz = I915_READ(VLV_PMWGICZ); | |
1070 | ||
1071 | /* Gunit-Display CZ domain, 0x182028-0x1821CF */ | |
1072 | s->gu_ctl0 = I915_READ(VLV_GU_CTL0); | |
1073 | s->gu_ctl1 = I915_READ(VLV_GU_CTL1); | |
1074 | s->clock_gate_dis2 = I915_READ(VLV_GUNIT_CLOCK_GATE2); | |
1075 | ||
1076 | /* | |
1077 | * Not saving any of: | |
1078 | * DFT, 0x9800-0x9EC0 | |
1079 | * SARB, 0xB000-0xB1FC | |
1080 | * GAC, 0x5208-0x524C, 0x14000-0x14C000 | |
1081 | * PCI CFG | |
1082 | */ | |
1083 | } | |
1084 | ||
1085 | static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv) | |
1086 | { | |
1087 | struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state; | |
1088 | u32 val; | |
1089 | int i; | |
1090 | ||
1091 | /* GAM 0x4000-0x4770 */ | |
1092 | I915_WRITE(GEN7_WR_WATERMARK, s->wr_watermark); | |
1093 | I915_WRITE(GEN7_GFX_PRIO_CTRL, s->gfx_prio_ctrl); | |
1094 | I915_WRITE(ARB_MODE, s->arb_mode | (0xffff << 16)); | |
1095 | I915_WRITE(GEN7_GFX_PEND_TLB0, s->gfx_pend_tlb0); | |
1096 | I915_WRITE(GEN7_GFX_PEND_TLB1, s->gfx_pend_tlb1); | |
1097 | ||
1098 | for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++) | |
1099 | I915_WRITE(GEN7_LRA_LIMITS_BASE + i * 4, s->lra_limits[i]); | |
1100 | ||
1101 | I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count); | |
1102 | I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->gfx_max_req_count); | |
1103 | ||
1104 | I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp); | |
1105 | I915_WRITE(GAM_ECOCHK, s->ecochk); | |
1106 | I915_WRITE(BSD_HWS_PGA_GEN7, s->bsd_hwsp); | |
1107 | I915_WRITE(BLT_HWS_PGA_GEN7, s->blt_hwsp); | |
1108 | ||
1109 | I915_WRITE(GEN7_TLB_RD_ADDR, s->tlb_rd_addr); | |
1110 | ||
1111 | /* MBC 0x9024-0x91D0, 0x8500 */ | |
1112 | I915_WRITE(VLV_G3DCTL, s->g3dctl); | |
1113 | I915_WRITE(VLV_GSCKGCTL, s->gsckgctl); | |
1114 | I915_WRITE(GEN6_MBCTL, s->mbctl); | |
1115 | ||
1116 | /* GCP 0x9400-0x9424, 0x8100-0x810C */ | |
1117 | I915_WRITE(GEN6_UCGCTL1, s->ucgctl1); | |
1118 | I915_WRITE(GEN6_UCGCTL3, s->ucgctl3); | |
1119 | I915_WRITE(GEN6_RCGCTL1, s->rcgctl1); | |
1120 | I915_WRITE(GEN6_RCGCTL2, s->rcgctl2); | |
1121 | I915_WRITE(GEN6_RSTCTL, s->rstctl); | |
1122 | I915_WRITE(GEN7_MISCCPCTL, s->misccpctl); | |
1123 | ||
1124 | /* GPM 0xA000-0xAA84, 0x8000-0x80FC */ | |
1125 | I915_WRITE(GEN6_GFXPAUSE, s->gfxpause); | |
1126 | I915_WRITE(GEN6_RPDEUHWTC, s->rpdeuhwtc); | |
1127 | I915_WRITE(GEN6_RPDEUC, s->rpdeuc); | |
1128 | I915_WRITE(ECOBUS, s->ecobus); | |
1129 | I915_WRITE(VLV_PWRDWNUPCTL, s->pwrdwnupctl); | |
1130 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout); | |
1131 | I915_WRITE(GEN6_RPDEUCSW, s->rp_deucsw); | |
1132 | I915_WRITE(GEN6_RCUBMABDTMR, s->rcubmabdtmr); | |
1133 | I915_WRITE(VLV_RCEDATA, s->rcedata); | |
1134 | I915_WRITE(VLV_SPAREG2H, s->spare2gh); | |
1135 | ||
1136 | /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */ | |
1137 | I915_WRITE(GTIMR, s->gt_imr); | |
1138 | I915_WRITE(GTIER, s->gt_ier); | |
1139 | I915_WRITE(GEN6_PMIMR, s->pm_imr); | |
1140 | I915_WRITE(GEN6_PMIER, s->pm_ier); | |
1141 | ||
1142 | for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++) | |
1143 | I915_WRITE(GEN7_GT_SCRATCH_BASE + i * 4, s->gt_scratch[i]); | |
1144 | ||
1145 | /* GT SA CZ domain, 0x100000-0x138124 */ | |
1146 | I915_WRITE(TILECTL, s->tilectl); | |
1147 | I915_WRITE(GTFIFOCTL, s->gt_fifoctl); | |
1148 | /* | |
1149 | * Preserve the GT allow wake and GFX force clock bit, they are not | |
1150 | * be restored, as they are used to control the s0ix suspend/resume | |
1151 | * sequence by the caller. | |
1152 | */ | |
1153 | val = I915_READ(VLV_GTLC_WAKE_CTRL); | |
1154 | val &= VLV_GTLC_ALLOWWAKEREQ; | |
1155 | val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ; | |
1156 | I915_WRITE(VLV_GTLC_WAKE_CTRL, val); | |
1157 | ||
1158 | val = I915_READ(VLV_GTLC_SURVIVABILITY_REG); | |
1159 | val &= VLV_GFX_CLK_FORCE_ON_BIT; | |
1160 | val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT; | |
1161 | I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val); | |
1162 | ||
1163 | I915_WRITE(VLV_PMWGICZ, s->pmwgicz); | |
1164 | ||
1165 | /* Gunit-Display CZ domain, 0x182028-0x1821CF */ | |
1166 | I915_WRITE(VLV_GU_CTL0, s->gu_ctl0); | |
1167 | I915_WRITE(VLV_GU_CTL1, s->gu_ctl1); | |
1168 | I915_WRITE(VLV_GUNIT_CLOCK_GATE2, s->clock_gate_dis2); | |
1169 | } | |
1170 | ||
650ad970 ID |
1171 | int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on) |
1172 | { | |
1173 | u32 val; | |
1174 | int err; | |
1175 | ||
1176 | val = I915_READ(VLV_GTLC_SURVIVABILITY_REG); | |
1177 | WARN_ON(!!(val & VLV_GFX_CLK_FORCE_ON_BIT) == force_on); | |
1178 | ||
1179 | #define COND (I915_READ(VLV_GTLC_SURVIVABILITY_REG) & VLV_GFX_CLK_STATUS_BIT) | |
1180 | /* Wait for a previous force-off to settle */ | |
1181 | if (force_on) { | |
8d4eee9c | 1182 | err = wait_for(!COND, 20); |
650ad970 ID |
1183 | if (err) { |
1184 | DRM_ERROR("timeout waiting for GFX clock force-off (%08x)\n", | |
1185 | I915_READ(VLV_GTLC_SURVIVABILITY_REG)); | |
1186 | return err; | |
1187 | } | |
1188 | } | |
1189 | ||
1190 | val = I915_READ(VLV_GTLC_SURVIVABILITY_REG); | |
1191 | val &= ~VLV_GFX_CLK_FORCE_ON_BIT; | |
1192 | if (force_on) | |
1193 | val |= VLV_GFX_CLK_FORCE_ON_BIT; | |
1194 | I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val); | |
1195 | ||
1196 | if (!force_on) | |
1197 | return 0; | |
1198 | ||
8d4eee9c | 1199 | err = wait_for(COND, 20); |
650ad970 ID |
1200 | if (err) |
1201 | DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n", | |
1202 | I915_READ(VLV_GTLC_SURVIVABILITY_REG)); | |
1203 | ||
1204 | return err; | |
1205 | #undef COND | |
1206 | } | |
1207 | ||
ddeea5b0 ID |
1208 | static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow) |
1209 | { | |
1210 | u32 val; | |
1211 | int err = 0; | |
1212 | ||
1213 | val = I915_READ(VLV_GTLC_WAKE_CTRL); | |
1214 | val &= ~VLV_GTLC_ALLOWWAKEREQ; | |
1215 | if (allow) | |
1216 | val |= VLV_GTLC_ALLOWWAKEREQ; | |
1217 | I915_WRITE(VLV_GTLC_WAKE_CTRL, val); | |
1218 | POSTING_READ(VLV_GTLC_WAKE_CTRL); | |
1219 | ||
1220 | #define COND (!!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEACK) == \ | |
1221 | allow) | |
1222 | err = wait_for(COND, 1); | |
1223 | if (err) | |
1224 | DRM_ERROR("timeout disabling GT waking\n"); | |
1225 | return err; | |
1226 | #undef COND | |
1227 | } | |
1228 | ||
1229 | static int vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv, | |
1230 | bool wait_for_on) | |
1231 | { | |
1232 | u32 mask; | |
1233 | u32 val; | |
1234 | int err; | |
1235 | ||
1236 | mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK; | |
1237 | val = wait_for_on ? mask : 0; | |
1238 | #define COND ((I915_READ(VLV_GTLC_PW_STATUS) & mask) == val) | |
1239 | if (COND) | |
1240 | return 0; | |
1241 | ||
1242 | DRM_DEBUG_KMS("waiting for GT wells to go %s (%08x)\n", | |
1243 | wait_for_on ? "on" : "off", | |
1244 | I915_READ(VLV_GTLC_PW_STATUS)); | |
1245 | ||
1246 | /* | |
1247 | * RC6 transitioning can be delayed up to 2 msec (see | |
1248 | * valleyview_enable_rps), use 3 msec for safety. | |
1249 | */ | |
1250 | err = wait_for(COND, 3); | |
1251 | if (err) | |
1252 | DRM_ERROR("timeout waiting for GT wells to go %s\n", | |
1253 | wait_for_on ? "on" : "off"); | |
1254 | ||
1255 | return err; | |
1256 | #undef COND | |
1257 | } | |
1258 | ||
1259 | static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv) | |
1260 | { | |
1261 | if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR)) | |
1262 | return; | |
1263 | ||
1264 | DRM_ERROR("GT register access while GT waking disabled\n"); | |
1265 | I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR); | |
1266 | } | |
1267 | ||
1268 | static int vlv_runtime_suspend(struct drm_i915_private *dev_priv) | |
1269 | { | |
1270 | u32 mask; | |
1271 | int err; | |
1272 | ||
1273 | /* | |
1274 | * Bspec defines the following GT well on flags as debug only, so | |
1275 | * don't treat them as hard failures. | |
1276 | */ | |
1277 | (void)vlv_wait_for_gt_wells(dev_priv, false); | |
1278 | ||
1279 | mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS; | |
1280 | WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask); | |
1281 | ||
1282 | vlv_check_no_gt_access(dev_priv); | |
1283 | ||
1284 | err = vlv_force_gfx_clock(dev_priv, true); | |
1285 | if (err) | |
1286 | goto err1; | |
1287 | ||
1288 | err = vlv_allow_gt_wake(dev_priv, false); | |
1289 | if (err) | |
1290 | goto err2; | |
1291 | vlv_save_gunit_s0ix_state(dev_priv); | |
1292 | ||
1293 | err = vlv_force_gfx_clock(dev_priv, false); | |
1294 | if (err) | |
1295 | goto err2; | |
1296 | ||
1297 | return 0; | |
1298 | ||
1299 | err2: | |
1300 | /* For safety always re-enable waking and disable gfx clock forcing */ | |
1301 | vlv_allow_gt_wake(dev_priv, true); | |
1302 | err1: | |
1303 | vlv_force_gfx_clock(dev_priv, false); | |
1304 | ||
1305 | return err; | |
1306 | } | |
1307 | ||
1308 | static int vlv_runtime_resume(struct drm_i915_private *dev_priv) | |
1309 | { | |
1310 | struct drm_device *dev = dev_priv->dev; | |
1311 | int err; | |
1312 | int ret; | |
1313 | ||
1314 | /* | |
1315 | * If any of the steps fail just try to continue, that's the best we | |
1316 | * can do at this point. Return the first error code (which will also | |
1317 | * leave RPM permanently disabled). | |
1318 | */ | |
1319 | ret = vlv_force_gfx_clock(dev_priv, true); | |
1320 | ||
1321 | vlv_restore_gunit_s0ix_state(dev_priv); | |
1322 | ||
1323 | err = vlv_allow_gt_wake(dev_priv, true); | |
1324 | if (!ret) | |
1325 | ret = err; | |
1326 | ||
1327 | err = vlv_force_gfx_clock(dev_priv, false); | |
1328 | if (!ret) | |
1329 | ret = err; | |
1330 | ||
1331 | vlv_check_no_gt_access(dev_priv); | |
1332 | ||
1333 | intel_init_clock_gating(dev); | |
1334 | i915_gem_restore_fences(dev); | |
1335 | ||
1336 | return ret; | |
1337 | } | |
1338 | ||
97bea207 | 1339 | static int intel_runtime_suspend(struct device *device) |
8a187455 PZ |
1340 | { |
1341 | struct pci_dev *pdev = to_pci_dev(device); | |
1342 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1343 | struct drm_i915_private *dev_priv = dev->dev_private; | |
0ab9cfeb | 1344 | int ret; |
8a187455 | 1345 | |
aeab0b5a | 1346 | if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6(dev)))) |
c6df39b5 ID |
1347 | return -ENODEV; |
1348 | ||
8a187455 | 1349 | WARN_ON(!HAS_RUNTIME_PM(dev)); |
e998c40f | 1350 | assert_force_wake_inactive(dev_priv); |
8a187455 PZ |
1351 | |
1352 | DRM_DEBUG_KMS("Suspending device\n"); | |
1353 | ||
d6102977 ID |
1354 | /* |
1355 | * We could deadlock here in case another thread holding struct_mutex | |
1356 | * calls RPM suspend concurrently, since the RPM suspend will wait | |
1357 | * first for this RPM suspend to finish. In this case the concurrent | |
1358 | * RPM resume will be followed by its RPM suspend counterpart. Still | |
1359 | * for consistency return -EAGAIN, which will reschedule this suspend. | |
1360 | */ | |
1361 | if (!mutex_trylock(&dev->struct_mutex)) { | |
1362 | DRM_DEBUG_KMS("device lock contention, deffering suspend\n"); | |
1363 | /* | |
1364 | * Bump the expiration timestamp, otherwise the suspend won't | |
1365 | * be rescheduled. | |
1366 | */ | |
1367 | pm_runtime_mark_last_busy(device); | |
1368 | ||
1369 | return -EAGAIN; | |
1370 | } | |
1371 | /* | |
1372 | * We are safe here against re-faults, since the fault handler takes | |
1373 | * an RPM reference. | |
1374 | */ | |
1375 | i915_gem_release_all_mmaps(dev_priv); | |
1376 | mutex_unlock(&dev->struct_mutex); | |
1377 | ||
9486db61 ID |
1378 | /* |
1379 | * rps.work can't be rearmed here, since we get here only after making | |
1380 | * sure the GPU is idle and the RPS freq is set to the minimum. See | |
1381 | * intel_mark_idle(). | |
1382 | */ | |
1383 | cancel_work_sync(&dev_priv->rps.work); | |
b5478bcd ID |
1384 | intel_runtime_pm_disable_interrupts(dev); |
1385 | ||
0ab9cfeb ID |
1386 | if (IS_GEN6(dev)) { |
1387 | ret = 0; | |
1388 | } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { | |
1389 | ret = hsw_runtime_suspend(dev_priv); | |
ddeea5b0 ID |
1390 | } else if (IS_VALLEYVIEW(dev)) { |
1391 | ret = vlv_runtime_suspend(dev_priv); | |
0ab9cfeb ID |
1392 | } else { |
1393 | ret = -ENODEV; | |
6157d3c8 | 1394 | WARN_ON(1); |
0ab9cfeb ID |
1395 | } |
1396 | ||
1397 | if (ret) { | |
1398 | DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret); | |
1399 | intel_runtime_pm_restore_interrupts(dev); | |
1400 | ||
1401 | return ret; | |
1402 | } | |
a8a8bd54 | 1403 | |
16a3d6ef | 1404 | del_timer_sync(&dev_priv->gpu_error.hangcheck_timer); |
8a187455 | 1405 | dev_priv->pm.suspended = true; |
1fb2362b KCA |
1406 | |
1407 | /* | |
1408 | * current versions of firmware which depend on this opregion | |
1409 | * notification have repurposed the D1 definition to mean | |
1410 | * "runtime suspended" vs. what you would normally expect (D3) | |
1411 | * to distinguish it from notifications that might be sent | |
1412 | * via the suspend path. | |
1413 | */ | |
1414 | intel_opregion_notify_adapter(dev, PCI_D1); | |
8a187455 | 1415 | |
a8a8bd54 | 1416 | DRM_DEBUG_KMS("Device suspended\n"); |
8a187455 PZ |
1417 | return 0; |
1418 | } | |
1419 | ||
97bea207 | 1420 | static int intel_runtime_resume(struct device *device) |
8a187455 PZ |
1421 | { |
1422 | struct pci_dev *pdev = to_pci_dev(device); | |
1423 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1424 | struct drm_i915_private *dev_priv = dev->dev_private; | |
0ab9cfeb | 1425 | int ret; |
8a187455 PZ |
1426 | |
1427 | WARN_ON(!HAS_RUNTIME_PM(dev)); | |
1428 | ||
1429 | DRM_DEBUG_KMS("Resuming device\n"); | |
1430 | ||
cd2e9e90 | 1431 | intel_opregion_notify_adapter(dev, PCI_D0); |
8a187455 PZ |
1432 | dev_priv->pm.suspended = false; |
1433 | ||
0ab9cfeb ID |
1434 | if (IS_GEN6(dev)) { |
1435 | ret = snb_runtime_resume(dev_priv); | |
1436 | } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { | |
1437 | ret = hsw_runtime_resume(dev_priv); | |
ddeea5b0 ID |
1438 | } else if (IS_VALLEYVIEW(dev)) { |
1439 | ret = vlv_runtime_resume(dev_priv); | |
0ab9cfeb | 1440 | } else { |
6157d3c8 | 1441 | WARN_ON(1); |
0ab9cfeb ID |
1442 | ret = -ENODEV; |
1443 | } | |
a8a8bd54 | 1444 | |
0ab9cfeb ID |
1445 | /* |
1446 | * No point of rolling back things in case of an error, as the best | |
1447 | * we can do is to hope that things will still work (and disable RPM). | |
1448 | */ | |
92b806d3 ID |
1449 | i915_gem_init_swizzling(dev); |
1450 | gen6_update_ring_freq(dev); | |
1451 | ||
b5478bcd | 1452 | intel_runtime_pm_restore_interrupts(dev); |
9486db61 | 1453 | intel_reset_gt_powersave(dev); |
b5478bcd | 1454 | |
0ab9cfeb ID |
1455 | if (ret) |
1456 | DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret); | |
1457 | else | |
1458 | DRM_DEBUG_KMS("Device resumed\n"); | |
1459 | ||
1460 | return ret; | |
8a187455 PZ |
1461 | } |
1462 | ||
b4b78d12 | 1463 | static const struct dev_pm_ops i915_pm_ops = { |
0206e353 | 1464 | .suspend = i915_pm_suspend, |
76c4b250 ID |
1465 | .suspend_late = i915_pm_suspend_late, |
1466 | .resume_early = i915_pm_resume_early, | |
0206e353 AJ |
1467 | .resume = i915_pm_resume, |
1468 | .freeze = i915_pm_freeze, | |
76c4b250 | 1469 | .thaw_early = i915_pm_thaw_early, |
0206e353 AJ |
1470 | .thaw = i915_pm_thaw, |
1471 | .poweroff = i915_pm_poweroff, | |
76c4b250 | 1472 | .restore_early = i915_pm_resume_early, |
0206e353 | 1473 | .restore = i915_pm_resume, |
97bea207 PZ |
1474 | .runtime_suspend = intel_runtime_suspend, |
1475 | .runtime_resume = intel_runtime_resume, | |
cbda12d7 ZW |
1476 | }; |
1477 | ||
78b68556 | 1478 | static const struct vm_operations_struct i915_gem_vm_ops = { |
de151cf6 | 1479 | .fault = i915_gem_fault, |
ab00b3e5 JB |
1480 | .open = drm_gem_vm_open, |
1481 | .close = drm_gem_vm_close, | |
de151cf6 JB |
1482 | }; |
1483 | ||
e08e96de AV |
1484 | static const struct file_operations i915_driver_fops = { |
1485 | .owner = THIS_MODULE, | |
1486 | .open = drm_open, | |
1487 | .release = drm_release, | |
1488 | .unlocked_ioctl = drm_ioctl, | |
1489 | .mmap = drm_gem_mmap, | |
1490 | .poll = drm_poll, | |
e08e96de AV |
1491 | .read = drm_read, |
1492 | #ifdef CONFIG_COMPAT | |
1493 | .compat_ioctl = i915_compat_ioctl, | |
1494 | #endif | |
1495 | .llseek = noop_llseek, | |
1496 | }; | |
1497 | ||
1da177e4 | 1498 | static struct drm_driver driver = { |
0c54781b MW |
1499 | /* Don't use MTRRs here; the Xserver or userspace app should |
1500 | * deal with them for Intel hardware. | |
792d2b9a | 1501 | */ |
673a394b | 1502 | .driver_features = |
24986ee0 | 1503 | DRIVER_USE_AGP | |
10ba5012 KH |
1504 | DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME | |
1505 | DRIVER_RENDER, | |
22eae947 | 1506 | .load = i915_driver_load, |
ba8bbcf6 | 1507 | .unload = i915_driver_unload, |
673a394b | 1508 | .open = i915_driver_open, |
22eae947 DA |
1509 | .lastclose = i915_driver_lastclose, |
1510 | .preclose = i915_driver_preclose, | |
673a394b | 1511 | .postclose = i915_driver_postclose, |
d8e29209 RW |
1512 | |
1513 | /* Used in place of i915_pm_ops for non-DRIVER_MODESET */ | |
1514 | .suspend = i915_suspend, | |
76c4b250 | 1515 | .resume = i915_resume_legacy, |
d8e29209 | 1516 | |
cda17380 | 1517 | .device_is_agp = i915_driver_device_is_agp, |
7c1c2871 DA |
1518 | .master_create = i915_master_create, |
1519 | .master_destroy = i915_master_destroy, | |
955b12de | 1520 | #if defined(CONFIG_DEBUG_FS) |
27c202ad BG |
1521 | .debugfs_init = i915_debugfs_init, |
1522 | .debugfs_cleanup = i915_debugfs_cleanup, | |
955b12de | 1523 | #endif |
673a394b | 1524 | .gem_free_object = i915_gem_free_object, |
de151cf6 | 1525 | .gem_vm_ops = &i915_gem_vm_ops, |
1286ff73 DV |
1526 | |
1527 | .prime_handle_to_fd = drm_gem_prime_handle_to_fd, | |
1528 | .prime_fd_to_handle = drm_gem_prime_fd_to_handle, | |
1529 | .gem_prime_export = i915_gem_prime_export, | |
1530 | .gem_prime_import = i915_gem_prime_import, | |
1531 | ||
ff72145b DA |
1532 | .dumb_create = i915_gem_dumb_create, |
1533 | .dumb_map_offset = i915_gem_mmap_gtt, | |
43387b37 | 1534 | .dumb_destroy = drm_gem_dumb_destroy, |
1da177e4 | 1535 | .ioctls = i915_ioctls, |
e08e96de | 1536 | .fops = &i915_driver_fops, |
22eae947 DA |
1537 | .name = DRIVER_NAME, |
1538 | .desc = DRIVER_DESC, | |
1539 | .date = DRIVER_DATE, | |
1540 | .major = DRIVER_MAJOR, | |
1541 | .minor = DRIVER_MINOR, | |
1542 | .patchlevel = DRIVER_PATCHLEVEL, | |
1da177e4 LT |
1543 | }; |
1544 | ||
8410ea3b DA |
1545 | static struct pci_driver i915_pci_driver = { |
1546 | .name = DRIVER_NAME, | |
1547 | .id_table = pciidlist, | |
1548 | .probe = i915_pci_probe, | |
1549 | .remove = i915_pci_remove, | |
1550 | .driver.pm = &i915_pm_ops, | |
1551 | }; | |
1552 | ||
1da177e4 LT |
1553 | static int __init i915_init(void) |
1554 | { | |
1555 | driver.num_ioctls = i915_max_ioctl; | |
79e53945 JB |
1556 | |
1557 | /* | |
1558 | * If CONFIG_DRM_I915_KMS is set, default to KMS unless | |
1559 | * explicitly disabled with the module pararmeter. | |
1560 | * | |
1561 | * Otherwise, just follow the parameter (defaulting to off). | |
1562 | * | |
1563 | * Allow optional vga_text_mode_force boot option to override | |
1564 | * the default behavior. | |
1565 | */ | |
1566 | #if defined(CONFIG_DRM_I915_KMS) | |
d330a953 | 1567 | if (i915.modeset != 0) |
79e53945 JB |
1568 | driver.driver_features |= DRIVER_MODESET; |
1569 | #endif | |
d330a953 | 1570 | if (i915.modeset == 1) |
79e53945 JB |
1571 | driver.driver_features |= DRIVER_MODESET; |
1572 | ||
1573 | #ifdef CONFIG_VGA_CONSOLE | |
d330a953 | 1574 | if (vgacon_text_force() && i915.modeset == -1) |
79e53945 JB |
1575 | driver.driver_features &= ~DRIVER_MODESET; |
1576 | #endif | |
1577 | ||
b30324ad | 1578 | if (!(driver.driver_features & DRIVER_MODESET)) { |
3885c6bb | 1579 | driver.get_vblank_timestamp = NULL; |
b30324ad DV |
1580 | #ifndef CONFIG_DRM_I915_UMS |
1581 | /* Silently fail loading to not upset userspace. */ | |
c9cd7b65 | 1582 | DRM_DEBUG_DRIVER("KMS and UMS disabled.\n"); |
b30324ad DV |
1583 | return 0; |
1584 | #endif | |
1585 | } | |
3885c6bb | 1586 | |
8410ea3b | 1587 | return drm_pci_init(&driver, &i915_pci_driver); |
1da177e4 LT |
1588 | } |
1589 | ||
1590 | static void __exit i915_exit(void) | |
1591 | { | |
b33ecdd1 DV |
1592 | #ifndef CONFIG_DRM_I915_UMS |
1593 | if (!(driver.driver_features & DRIVER_MODESET)) | |
1594 | return; /* Never loaded a driver. */ | |
1595 | #endif | |
1596 | ||
8410ea3b | 1597 | drm_pci_exit(&driver, &i915_pci_driver); |
1da177e4 LT |
1598 | } |
1599 | ||
1600 | module_init(i915_init); | |
1601 | module_exit(i915_exit); | |
1602 | ||
b5e89ed5 DA |
1603 | MODULE_AUTHOR(DRIVER_AUTHOR); |
1604 | MODULE_DESCRIPTION(DRIVER_DESC); | |
1da177e4 | 1605 | MODULE_LICENSE("GPL and additional rights"); |