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1da177e4 LT |
1 | /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*- |
2 | */ | |
0d6aa60b | 3 | /* |
bc54fd1a | 4 | * |
1da177e4 LT |
5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
6 | * All Rights Reserved. | |
bc54fd1a DA |
7 | * |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the | |
10 | * "Software"), to deal in the Software without restriction, including | |
11 | * without limitation the rights to use, copy, modify, merge, publish, | |
12 | * distribute, sub license, and/or sell copies of the Software, and to | |
13 | * permit persons to whom the Software is furnished to do so, subject to | |
14 | * the following conditions: | |
15 | * | |
16 | * The above copyright notice and this permission notice (including the | |
17 | * next paragraph) shall be included in all copies or substantial portions | |
18 | * of the Software. | |
19 | * | |
20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
27 | * | |
0d6aa60b | 28 | */ |
1da177e4 | 29 | |
5669fcac | 30 | #include <linux/device.h> |
e5747e3a | 31 | #include <linux/acpi.h> |
760285e7 DH |
32 | #include <drm/drmP.h> |
33 | #include <drm/i915_drm.h> | |
1da177e4 | 34 | #include "i915_drv.h" |
990bbdad | 35 | #include "i915_trace.h" |
f49f0586 | 36 | #include "intel_drv.h" |
1da177e4 | 37 | |
79e53945 | 38 | #include <linux/console.h> |
e0cd3608 | 39 | #include <linux/module.h> |
d6102977 | 40 | #include <linux/pm_runtime.h> |
704ab614 | 41 | #include <linux/vga_switcheroo.h> |
760285e7 | 42 | #include <drm/drm_crtc_helper.h> |
79e53945 | 43 | |
112b715e KH |
44 | static struct drm_driver driver; |
45 | ||
a57c774a AK |
46 | #define GEN_DEFAULT_PIPEOFFSETS \ |
47 | .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \ | |
48 | PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \ | |
49 | .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \ | |
50 | TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \ | |
a57c774a AK |
51 | .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET } |
52 | ||
84fd4f4e RB |
53 | #define GEN_CHV_PIPEOFFSETS \ |
54 | .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \ | |
55 | CHV_PIPE_C_OFFSET }, \ | |
56 | .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \ | |
57 | CHV_TRANSCODER_C_OFFSET, }, \ | |
84fd4f4e RB |
58 | .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \ |
59 | CHV_PALETTE_C_OFFSET } | |
a57c774a | 60 | |
5efb3e28 VS |
61 | #define CURSOR_OFFSETS \ |
62 | .cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET } | |
63 | ||
64 | #define IVB_CURSOR_OFFSETS \ | |
65 | .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET } | |
66 | ||
82cf435b LL |
67 | #define BDW_COLORS \ |
68 | .color = { .degamma_lut_size = 512, .gamma_lut_size = 512 } | |
29dc3739 LL |
69 | #define CHV_COLORS \ |
70 | .color = { .degamma_lut_size = 65, .gamma_lut_size = 257 } | |
82cf435b | 71 | |
9a7e8492 | 72 | static const struct intel_device_info intel_i830_info = { |
7eb552ae | 73 | .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2, |
31578148 | 74 | .has_overlay = 1, .overlay_needs_physical = 1, |
73ae478c | 75 | .ring_mask = RENDER_RING, |
a57c774a | 76 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 77 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
78 | }; |
79 | ||
9a7e8492 | 80 | static const struct intel_device_info intel_845g_info = { |
7eb552ae | 81 | .gen = 2, .num_pipes = 1, |
31578148 | 82 | .has_overlay = 1, .overlay_needs_physical = 1, |
73ae478c | 83 | .ring_mask = RENDER_RING, |
a57c774a | 84 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 85 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
86 | }; |
87 | ||
9a7e8492 | 88 | static const struct intel_device_info intel_i85x_info = { |
7eb552ae | 89 | .gen = 2, .is_i85x = 1, .is_mobile = 1, .num_pipes = 2, |
5ce8ba7c | 90 | .cursor_needs_physical = 1, |
31578148 | 91 | .has_overlay = 1, .overlay_needs_physical = 1, |
fd70d52a | 92 | .has_fbc = 1, |
73ae478c | 93 | .ring_mask = RENDER_RING, |
a57c774a | 94 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 95 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
96 | }; |
97 | ||
9a7e8492 | 98 | static const struct intel_device_info intel_i865g_info = { |
7eb552ae | 99 | .gen = 2, .num_pipes = 1, |
31578148 | 100 | .has_overlay = 1, .overlay_needs_physical = 1, |
73ae478c | 101 | .ring_mask = RENDER_RING, |
a57c774a | 102 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 103 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
104 | }; |
105 | ||
9a7e8492 | 106 | static const struct intel_device_info intel_i915g_info = { |
7eb552ae | 107 | .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2, |
31578148 | 108 | .has_overlay = 1, .overlay_needs_physical = 1, |
73ae478c | 109 | .ring_mask = RENDER_RING, |
a57c774a | 110 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 111 | CURSOR_OFFSETS, |
cfdf1fa2 | 112 | }; |
9a7e8492 | 113 | static const struct intel_device_info intel_i915gm_info = { |
7eb552ae | 114 | .gen = 3, .is_mobile = 1, .num_pipes = 2, |
b295d1b6 | 115 | .cursor_needs_physical = 1, |
31578148 | 116 | .has_overlay = 1, .overlay_needs_physical = 1, |
a6c45cf0 | 117 | .supports_tv = 1, |
fd70d52a | 118 | .has_fbc = 1, |
73ae478c | 119 | .ring_mask = RENDER_RING, |
a57c774a | 120 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 121 | CURSOR_OFFSETS, |
cfdf1fa2 | 122 | }; |
9a7e8492 | 123 | static const struct intel_device_info intel_i945g_info = { |
7eb552ae | 124 | .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2, |
31578148 | 125 | .has_overlay = 1, .overlay_needs_physical = 1, |
73ae478c | 126 | .ring_mask = RENDER_RING, |
a57c774a | 127 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 128 | CURSOR_OFFSETS, |
cfdf1fa2 | 129 | }; |
9a7e8492 | 130 | static const struct intel_device_info intel_i945gm_info = { |
7eb552ae | 131 | .gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2, |
b295d1b6 | 132 | .has_hotplug = 1, .cursor_needs_physical = 1, |
31578148 | 133 | .has_overlay = 1, .overlay_needs_physical = 1, |
a6c45cf0 | 134 | .supports_tv = 1, |
fd70d52a | 135 | .has_fbc = 1, |
73ae478c | 136 | .ring_mask = RENDER_RING, |
a57c774a | 137 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 138 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
139 | }; |
140 | ||
9a7e8492 | 141 | static const struct intel_device_info intel_i965g_info = { |
7eb552ae | 142 | .gen = 4, .is_broadwater = 1, .num_pipes = 2, |
c96c3a8c | 143 | .has_hotplug = 1, |
31578148 | 144 | .has_overlay = 1, |
73ae478c | 145 | .ring_mask = RENDER_RING, |
a57c774a | 146 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 147 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
148 | }; |
149 | ||
9a7e8492 | 150 | static const struct intel_device_info intel_i965gm_info = { |
7eb552ae | 151 | .gen = 4, .is_crestline = 1, .num_pipes = 2, |
e3c4e5dd | 152 | .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1, |
31578148 | 153 | .has_overlay = 1, |
a6c45cf0 | 154 | .supports_tv = 1, |
73ae478c | 155 | .ring_mask = RENDER_RING, |
a57c774a | 156 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 157 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
158 | }; |
159 | ||
9a7e8492 | 160 | static const struct intel_device_info intel_g33_info = { |
7eb552ae | 161 | .gen = 3, .is_g33 = 1, .num_pipes = 2, |
c96c3a8c | 162 | .need_gfx_hws = 1, .has_hotplug = 1, |
31578148 | 163 | .has_overlay = 1, |
73ae478c | 164 | .ring_mask = RENDER_RING, |
a57c774a | 165 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 166 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
167 | }; |
168 | ||
9a7e8492 | 169 | static const struct intel_device_info intel_g45_info = { |
7eb552ae | 170 | .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2, |
c96c3a8c | 171 | .has_pipe_cxsr = 1, .has_hotplug = 1, |
73ae478c | 172 | .ring_mask = RENDER_RING | BSD_RING, |
a57c774a | 173 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 174 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
175 | }; |
176 | ||
9a7e8492 | 177 | static const struct intel_device_info intel_gm45_info = { |
7eb552ae | 178 | .gen = 4, .is_g4x = 1, .num_pipes = 2, |
e3c4e5dd | 179 | .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1, |
c96c3a8c | 180 | .has_pipe_cxsr = 1, .has_hotplug = 1, |
a6c45cf0 | 181 | .supports_tv = 1, |
73ae478c | 182 | .ring_mask = RENDER_RING | BSD_RING, |
a57c774a | 183 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 184 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
185 | }; |
186 | ||
9a7e8492 | 187 | static const struct intel_device_info intel_pineview_info = { |
7eb552ae | 188 | .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2, |
c96c3a8c | 189 | .need_gfx_hws = 1, .has_hotplug = 1, |
31578148 | 190 | .has_overlay = 1, |
a57c774a | 191 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 192 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
193 | }; |
194 | ||
9a7e8492 | 195 | static const struct intel_device_info intel_ironlake_d_info = { |
7eb552ae | 196 | .gen = 5, .num_pipes = 2, |
5a117db7 | 197 | .need_gfx_hws = 1, .has_hotplug = 1, |
73ae478c | 198 | .ring_mask = RENDER_RING | BSD_RING, |
a57c774a | 199 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 200 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
201 | }; |
202 | ||
9a7e8492 | 203 | static const struct intel_device_info intel_ironlake_m_info = { |
7eb552ae | 204 | .gen = 5, .is_mobile = 1, .num_pipes = 2, |
e3c4e5dd | 205 | .need_gfx_hws = 1, .has_hotplug = 1, |
c1a9f047 | 206 | .has_fbc = 1, |
73ae478c | 207 | .ring_mask = RENDER_RING | BSD_RING, |
a57c774a | 208 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 209 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
210 | }; |
211 | ||
9a7e8492 | 212 | static const struct intel_device_info intel_sandybridge_d_info = { |
7eb552ae | 213 | .gen = 6, .num_pipes = 2, |
c96c3a8c | 214 | .need_gfx_hws = 1, .has_hotplug = 1, |
cbaef0f1 | 215 | .has_fbc = 1, |
73ae478c | 216 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING, |
3d29b842 | 217 | .has_llc = 1, |
a57c774a | 218 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 219 | CURSOR_OFFSETS, |
f6e450a6 EA |
220 | }; |
221 | ||
9a7e8492 | 222 | static const struct intel_device_info intel_sandybridge_m_info = { |
7eb552ae | 223 | .gen = 6, .is_mobile = 1, .num_pipes = 2, |
c96c3a8c | 224 | .need_gfx_hws = 1, .has_hotplug = 1, |
9c04f015 | 225 | .has_fbc = 1, |
73ae478c | 226 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING, |
3d29b842 | 227 | .has_llc = 1, |
a57c774a | 228 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 229 | CURSOR_OFFSETS, |
a13e4093 EA |
230 | }; |
231 | ||
219f4fdb BW |
232 | #define GEN7_FEATURES \ |
233 | .gen = 7, .num_pipes = 3, \ | |
234 | .need_gfx_hws = 1, .has_hotplug = 1, \ | |
cbaef0f1 | 235 | .has_fbc = 1, \ |
73ae478c | 236 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \ |
6a8beeff WB |
237 | .has_llc = 1, \ |
238 | GEN_DEFAULT_PIPEOFFSETS, \ | |
239 | IVB_CURSOR_OFFSETS | |
219f4fdb | 240 | |
c76b615c | 241 | static const struct intel_device_info intel_ivybridge_d_info = { |
219f4fdb BW |
242 | GEN7_FEATURES, |
243 | .is_ivybridge = 1, | |
c76b615c JB |
244 | }; |
245 | ||
246 | static const struct intel_device_info intel_ivybridge_m_info = { | |
219f4fdb BW |
247 | GEN7_FEATURES, |
248 | .is_ivybridge = 1, | |
249 | .is_mobile = 1, | |
c76b615c JB |
250 | }; |
251 | ||
999bcdea BW |
252 | static const struct intel_device_info intel_ivybridge_q_info = { |
253 | GEN7_FEATURES, | |
254 | .is_ivybridge = 1, | |
255 | .num_pipes = 0, /* legal, last one wins */ | |
256 | }; | |
257 | ||
6a8beeff WB |
258 | #define VLV_FEATURES \ |
259 | .gen = 7, .num_pipes = 2, \ | |
260 | .need_gfx_hws = 1, .has_hotplug = 1, \ | |
261 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \ | |
262 | .display_mmio_offset = VLV_DISPLAY_BASE, \ | |
263 | GEN_DEFAULT_PIPEOFFSETS, \ | |
264 | CURSOR_OFFSETS | |
265 | ||
70a3eb7a | 266 | static const struct intel_device_info intel_valleyview_m_info = { |
6a8beeff | 267 | VLV_FEATURES, |
70a3eb7a | 268 | .is_valleyview = 1, |
6a8beeff | 269 | .is_mobile = 1, |
70a3eb7a JB |
270 | }; |
271 | ||
272 | static const struct intel_device_info intel_valleyview_d_info = { | |
6a8beeff | 273 | VLV_FEATURES, |
70a3eb7a JB |
274 | .is_valleyview = 1, |
275 | }; | |
276 | ||
6a8beeff WB |
277 | #define HSW_FEATURES \ |
278 | GEN7_FEATURES, \ | |
279 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \ | |
280 | .has_ddi = 1, \ | |
281 | .has_fpga_dbg = 1 | |
282 | ||
4cae9ae0 | 283 | static const struct intel_device_info intel_haswell_d_info = { |
6a8beeff | 284 | HSW_FEATURES, |
219f4fdb | 285 | .is_haswell = 1, |
4cae9ae0 ED |
286 | }; |
287 | ||
288 | static const struct intel_device_info intel_haswell_m_info = { | |
6a8beeff | 289 | HSW_FEATURES, |
219f4fdb BW |
290 | .is_haswell = 1, |
291 | .is_mobile = 1, | |
c76b615c JB |
292 | }; |
293 | ||
82cf435b LL |
294 | #define BDW_FEATURES \ |
295 | HSW_FEATURES, \ | |
296 | BDW_COLORS | |
297 | ||
4d4dead6 | 298 | static const struct intel_device_info intel_broadwell_d_info = { |
82cf435b | 299 | BDW_FEATURES, |
6a8beeff | 300 | .gen = 8, |
ab0d24ac | 301 | .is_broadwell = 1, |
4d4dead6 BW |
302 | }; |
303 | ||
304 | static const struct intel_device_info intel_broadwell_m_info = { | |
82cf435b | 305 | BDW_FEATURES, |
6a8beeff | 306 | .gen = 8, .is_mobile = 1, |
ab0d24ac | 307 | .is_broadwell = 1, |
4d4dead6 BW |
308 | }; |
309 | ||
fd3c269f | 310 | static const struct intel_device_info intel_broadwell_gt3d_info = { |
82cf435b | 311 | BDW_FEATURES, |
6a8beeff | 312 | .gen = 8, |
ab0d24ac | 313 | .is_broadwell = 1, |
845f74a7 | 314 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, |
fd3c269f ZY |
315 | }; |
316 | ||
317 | static const struct intel_device_info intel_broadwell_gt3m_info = { | |
82cf435b | 318 | BDW_FEATURES, |
6a8beeff | 319 | .gen = 8, .is_mobile = 1, |
ab0d24ac | 320 | .is_broadwell = 1, |
845f74a7 | 321 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, |
fd3c269f ZY |
322 | }; |
323 | ||
7d87a7f7 | 324 | static const struct intel_device_info intel_cherryview_info = { |
07fddb14 | 325 | .gen = 8, .num_pipes = 3, |
7d87a7f7 VS |
326 | .need_gfx_hws = 1, .has_hotplug = 1, |
327 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, | |
666a4537 | 328 | .is_cherryview = 1, |
7d87a7f7 | 329 | .display_mmio_offset = VLV_DISPLAY_BASE, |
84fd4f4e | 330 | GEN_CHV_PIPEOFFSETS, |
5efb3e28 | 331 | CURSOR_OFFSETS, |
29dc3739 | 332 | CHV_COLORS, |
7d87a7f7 VS |
333 | }; |
334 | ||
72bbf0af | 335 | static const struct intel_device_info intel_skylake_info = { |
82cf435b | 336 | BDW_FEATURES, |
7201c0b3 | 337 | .is_skylake = 1, |
6a8beeff | 338 | .gen = 9, |
72bbf0af DL |
339 | }; |
340 | ||
719388e1 | 341 | static const struct intel_device_info intel_skylake_gt3_info = { |
82cf435b | 342 | BDW_FEATURES, |
719388e1 | 343 | .is_skylake = 1, |
6a8beeff | 344 | .gen = 9, |
719388e1 | 345 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, |
719388e1 DL |
346 | }; |
347 | ||
1347f5b4 DL |
348 | static const struct intel_device_info intel_broxton_info = { |
349 | .is_preliminary = 1, | |
7526ac19 | 350 | .is_broxton = 1, |
1347f5b4 DL |
351 | .gen = 9, |
352 | .need_gfx_hws = 1, .has_hotplug = 1, | |
353 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, | |
354 | .num_pipes = 3, | |
355 | .has_ddi = 1, | |
6c908bf4 | 356 | .has_fpga_dbg = 1, |
ce89db2e | 357 | .has_fbc = 1, |
e015dd69 | 358 | .has_pooled_eu = 0, |
1347f5b4 DL |
359 | GEN_DEFAULT_PIPEOFFSETS, |
360 | IVB_CURSOR_OFFSETS, | |
82cf435b | 361 | BDW_COLORS, |
1347f5b4 DL |
362 | }; |
363 | ||
ef11bdb3 | 364 | static const struct intel_device_info intel_kabylake_info = { |
82cf435b | 365 | BDW_FEATURES, |
ef11bdb3 RV |
366 | .is_kabylake = 1, |
367 | .gen = 9, | |
ef11bdb3 RV |
368 | }; |
369 | ||
370 | static const struct intel_device_info intel_kabylake_gt3_info = { | |
82cf435b | 371 | BDW_FEATURES, |
ef11bdb3 RV |
372 | .is_kabylake = 1, |
373 | .gen = 9, | |
ef11bdb3 | 374 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, |
ef11bdb3 RV |
375 | }; |
376 | ||
a0a18075 JB |
377 | /* |
378 | * Make sure any device matches here are from most specific to most | |
379 | * general. For example, since the Quanta match is based on the subsystem | |
380 | * and subvendor IDs, we need it to come before the more general IVB | |
381 | * PCI ID matches, otherwise we'll use the wrong info struct above. | |
382 | */ | |
3cb27f38 JN |
383 | static const struct pci_device_id pciidlist[] = { |
384 | INTEL_I830_IDS(&intel_i830_info), | |
385 | INTEL_I845G_IDS(&intel_845g_info), | |
386 | INTEL_I85X_IDS(&intel_i85x_info), | |
387 | INTEL_I865G_IDS(&intel_i865g_info), | |
388 | INTEL_I915G_IDS(&intel_i915g_info), | |
389 | INTEL_I915GM_IDS(&intel_i915gm_info), | |
390 | INTEL_I945G_IDS(&intel_i945g_info), | |
391 | INTEL_I945GM_IDS(&intel_i945gm_info), | |
392 | INTEL_I965G_IDS(&intel_i965g_info), | |
393 | INTEL_G33_IDS(&intel_g33_info), | |
394 | INTEL_I965GM_IDS(&intel_i965gm_info), | |
395 | INTEL_GM45_IDS(&intel_gm45_info), | |
396 | INTEL_G45_IDS(&intel_g45_info), | |
397 | INTEL_PINEVIEW_IDS(&intel_pineview_info), | |
398 | INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info), | |
399 | INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info), | |
400 | INTEL_SNB_D_IDS(&intel_sandybridge_d_info), | |
401 | INTEL_SNB_M_IDS(&intel_sandybridge_m_info), | |
402 | INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */ | |
403 | INTEL_IVB_M_IDS(&intel_ivybridge_m_info), | |
404 | INTEL_IVB_D_IDS(&intel_ivybridge_d_info), | |
405 | INTEL_HSW_D_IDS(&intel_haswell_d_info), | |
406 | INTEL_HSW_M_IDS(&intel_haswell_m_info), | |
407 | INTEL_VLV_M_IDS(&intel_valleyview_m_info), | |
408 | INTEL_VLV_D_IDS(&intel_valleyview_d_info), | |
409 | INTEL_BDW_GT12M_IDS(&intel_broadwell_m_info), | |
410 | INTEL_BDW_GT12D_IDS(&intel_broadwell_d_info), | |
411 | INTEL_BDW_GT3M_IDS(&intel_broadwell_gt3m_info), | |
412 | INTEL_BDW_GT3D_IDS(&intel_broadwell_gt3d_info), | |
413 | INTEL_CHV_IDS(&intel_cherryview_info), | |
414 | INTEL_SKL_GT1_IDS(&intel_skylake_info), | |
415 | INTEL_SKL_GT2_IDS(&intel_skylake_info), | |
416 | INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info), | |
15620206 | 417 | INTEL_SKL_GT4_IDS(&intel_skylake_gt3_info), |
3cb27f38 | 418 | INTEL_BXT_IDS(&intel_broxton_info), |
d97044b6 D |
419 | INTEL_KBL_GT1_IDS(&intel_kabylake_info), |
420 | INTEL_KBL_GT2_IDS(&intel_kabylake_info), | |
421 | INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info), | |
8b10c0cf | 422 | INTEL_KBL_GT4_IDS(&intel_kabylake_gt3_info), |
49ae35f2 | 423 | {0, 0, 0} |
1da177e4 LT |
424 | }; |
425 | ||
79e53945 | 426 | MODULE_DEVICE_TABLE(pci, pciidlist); |
79e53945 | 427 | |
30c964a6 RB |
428 | static enum intel_pch intel_virt_detect_pch(struct drm_device *dev) |
429 | { | |
430 | enum intel_pch ret = PCH_NOP; | |
431 | ||
432 | /* | |
433 | * In a virtualized passthrough environment we can be in a | |
434 | * setup where the ISA bridge is not able to be passed through. | |
435 | * In this case, a south bridge can be emulated and we have to | |
436 | * make an educated guess as to which PCH is really there. | |
437 | */ | |
438 | ||
439 | if (IS_GEN5(dev)) { | |
440 | ret = PCH_IBX; | |
441 | DRM_DEBUG_KMS("Assuming Ibex Peak PCH\n"); | |
442 | } else if (IS_GEN6(dev) || IS_IVYBRIDGE(dev)) { | |
443 | ret = PCH_CPT; | |
444 | DRM_DEBUG_KMS("Assuming CouarPoint PCH\n"); | |
445 | } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { | |
446 | ret = PCH_LPT; | |
447 | DRM_DEBUG_KMS("Assuming LynxPoint PCH\n"); | |
ef11bdb3 | 448 | } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { |
30c964a6 RB |
449 | ret = PCH_SPT; |
450 | DRM_DEBUG_KMS("Assuming SunrisePoint PCH\n"); | |
451 | } | |
452 | ||
453 | return ret; | |
454 | } | |
455 | ||
0206e353 | 456 | void intel_detect_pch(struct drm_device *dev) |
3bad0781 ZW |
457 | { |
458 | struct drm_i915_private *dev_priv = dev->dev_private; | |
bcdb72ac | 459 | struct pci_dev *pch = NULL; |
3bad0781 | 460 | |
ce1bb329 BW |
461 | /* In all current cases, num_pipes is equivalent to the PCH_NOP setting |
462 | * (which really amounts to a PCH but no South Display). | |
463 | */ | |
464 | if (INTEL_INFO(dev)->num_pipes == 0) { | |
465 | dev_priv->pch_type = PCH_NOP; | |
ce1bb329 BW |
466 | return; |
467 | } | |
468 | ||
3bad0781 ZW |
469 | /* |
470 | * The reason to probe ISA bridge instead of Dev31:Fun0 is to | |
471 | * make graphics device passthrough work easy for VMM, that only | |
472 | * need to expose ISA bridge to let driver know the real hardware | |
473 | * underneath. This is a requirement from virtualization team. | |
6a9c4b35 RG |
474 | * |
475 | * In some virtualized environments (e.g. XEN), there is irrelevant | |
476 | * ISA bridge in the system. To work reliably, we should scan trhough | |
477 | * all the ISA bridge devices and check for the first match, instead | |
478 | * of only checking the first one. | |
3bad0781 | 479 | */ |
bcdb72ac | 480 | while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) { |
3bad0781 | 481 | if (pch->vendor == PCI_VENDOR_ID_INTEL) { |
bcdb72ac | 482 | unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK; |
17a303ec | 483 | dev_priv->pch_id = id; |
3bad0781 | 484 | |
90711d50 JB |
485 | if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) { |
486 | dev_priv->pch_type = PCH_IBX; | |
487 | DRM_DEBUG_KMS("Found Ibex Peak PCH\n"); | |
7fcb83cd | 488 | WARN_ON(!IS_GEN5(dev)); |
90711d50 | 489 | } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) { |
3bad0781 ZW |
490 | dev_priv->pch_type = PCH_CPT; |
491 | DRM_DEBUG_KMS("Found CougarPoint PCH\n"); | |
7fcb83cd | 492 | WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev))); |
c792513b JB |
493 | } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) { |
494 | /* PantherPoint is CPT compatible */ | |
495 | dev_priv->pch_type = PCH_CPT; | |
492ab669 | 496 | DRM_DEBUG_KMS("Found PantherPoint PCH\n"); |
7fcb83cd | 497 | WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev))); |
eb877ebf ED |
498 | } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) { |
499 | dev_priv->pch_type = PCH_LPT; | |
500 | DRM_DEBUG_KMS("Found LynxPoint PCH\n"); | |
a35cc9d0 RV |
501 | WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev)); |
502 | WARN_ON(IS_HSW_ULT(dev) || IS_BDW_ULT(dev)); | |
e76e0634 BW |
503 | } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { |
504 | dev_priv->pch_type = PCH_LPT; | |
505 | DRM_DEBUG_KMS("Found LynxPoint LP PCH\n"); | |
a35cc9d0 RV |
506 | WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev)); |
507 | WARN_ON(!IS_HSW_ULT(dev) && !IS_BDW_ULT(dev)); | |
e7e7ea20 S |
508 | } else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) { |
509 | dev_priv->pch_type = PCH_SPT; | |
510 | DRM_DEBUG_KMS("Found SunrisePoint PCH\n"); | |
ef11bdb3 RV |
511 | WARN_ON(!IS_SKYLAKE(dev) && |
512 | !IS_KABYLAKE(dev)); | |
e7e7ea20 S |
513 | } else if (id == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) { |
514 | dev_priv->pch_type = PCH_SPT; | |
515 | DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n"); | |
ef11bdb3 RV |
516 | WARN_ON(!IS_SKYLAKE(dev) && |
517 | !IS_KABYLAKE(dev)); | |
39bfcd52 | 518 | } else if ((id == INTEL_PCH_P2X_DEVICE_ID_TYPE) || |
1844a66b | 519 | (id == INTEL_PCH_P3X_DEVICE_ID_TYPE) || |
f2e30510 | 520 | ((id == INTEL_PCH_QEMU_DEVICE_ID_TYPE) && |
94bb489c GH |
521 | pch->subsystem_vendor == |
522 | PCI_SUBVENDOR_ID_REDHAT_QUMRANET && | |
523 | pch->subsystem_device == | |
524 | PCI_SUBDEVICE_ID_QEMU)) { | |
30c964a6 | 525 | dev_priv->pch_type = intel_virt_detect_pch(dev); |
bcdb72ac ID |
526 | } else |
527 | continue; | |
528 | ||
6a9c4b35 | 529 | break; |
3bad0781 | 530 | } |
3bad0781 | 531 | } |
6a9c4b35 | 532 | if (!pch) |
bcdb72ac ID |
533 | DRM_DEBUG_KMS("No PCH found.\n"); |
534 | ||
535 | pci_dev_put(pch); | |
3bad0781 ZW |
536 | } |
537 | ||
c033666a | 538 | bool i915_semaphore_is_enabled(struct drm_i915_private *dev_priv) |
2911a35b | 539 | { |
c033666a | 540 | if (INTEL_GEN(dev_priv) < 6) |
a08acaf2 | 541 | return false; |
2911a35b | 542 | |
d330a953 JN |
543 | if (i915.semaphores >= 0) |
544 | return i915.semaphores; | |
2911a35b | 545 | |
71386ef9 OM |
546 | /* TODO: make semaphores and Execlists play nicely together */ |
547 | if (i915.enable_execlists) | |
548 | return false; | |
549 | ||
59de3295 | 550 | #ifdef CONFIG_INTEL_IOMMU |
2911a35b | 551 | /* Enable semaphores on SNB when IO remapping is off */ |
c033666a | 552 | if (IS_GEN6(dev_priv) && intel_iommu_gfx_mapped) |
59de3295 DV |
553 | return false; |
554 | #endif | |
2911a35b | 555 | |
a08acaf2 | 556 | return true; |
2911a35b BW |
557 | } |
558 | ||
07f9cd0b ID |
559 | static void intel_suspend_encoders(struct drm_i915_private *dev_priv) |
560 | { | |
561 | struct drm_device *dev = dev_priv->dev; | |
19c8054c | 562 | struct intel_encoder *encoder; |
07f9cd0b ID |
563 | |
564 | drm_modeset_lock_all(dev); | |
19c8054c JN |
565 | for_each_intel_encoder(dev, encoder) |
566 | if (encoder->suspend) | |
567 | encoder->suspend(encoder); | |
07f9cd0b ID |
568 | drm_modeset_unlock_all(dev); |
569 | } | |
570 | ||
1a5df187 PZ |
571 | static int vlv_resume_prepare(struct drm_i915_private *dev_priv, |
572 | bool rpm_resume); | |
507e126e | 573 | static int vlv_suspend_complete(struct drm_i915_private *dev_priv); |
f75a1985 | 574 | |
bc87229f ID |
575 | static bool suspend_to_idle(struct drm_i915_private *dev_priv) |
576 | { | |
577 | #if IS_ENABLED(CONFIG_ACPI_SLEEP) | |
578 | if (acpi_target_system_state() < ACPI_STATE_S3) | |
579 | return true; | |
580 | #endif | |
581 | return false; | |
582 | } | |
ebc32824 | 583 | |
5e365c39 | 584 | static int i915_drm_suspend(struct drm_device *dev) |
ba8bbcf6 | 585 | { |
61caf87c | 586 | struct drm_i915_private *dev_priv = dev->dev_private; |
e5747e3a | 587 | pci_power_t opregion_target_state; |
d5818938 | 588 | int error; |
61caf87c | 589 | |
b8efb17b ZR |
590 | /* ignore lid events during suspend */ |
591 | mutex_lock(&dev_priv->modeset_restore_lock); | |
592 | dev_priv->modeset_restore = MODESET_SUSPENDED; | |
593 | mutex_unlock(&dev_priv->modeset_restore_lock); | |
594 | ||
1f814dac ID |
595 | disable_rpm_wakeref_asserts(dev_priv); |
596 | ||
c67a470b PZ |
597 | /* We do a lot of poking in a lot of registers, make sure they work |
598 | * properly. */ | |
da7e29bd | 599 | intel_display_set_init_power(dev_priv, true); |
cb10799c | 600 | |
5bcf719b DA |
601 | drm_kms_helper_poll_disable(dev); |
602 | ||
ba8bbcf6 | 603 | pci_save_state(dev->pdev); |
ba8bbcf6 | 604 | |
d5818938 DV |
605 | error = i915_gem_suspend(dev); |
606 | if (error) { | |
607 | dev_err(&dev->pdev->dev, | |
608 | "GEM idle failed, resume might fail\n"); | |
1f814dac | 609 | goto out; |
d5818938 | 610 | } |
db1b76ca | 611 | |
a1c41994 AD |
612 | intel_guc_suspend(dev); |
613 | ||
dc97997a | 614 | intel_suspend_gt_powersave(dev_priv); |
a261b246 | 615 | |
6b72d486 | 616 | intel_display_suspend(dev); |
2eb5252e | 617 | |
d5818938 | 618 | intel_dp_mst_suspend(dev); |
7d708ee4 | 619 | |
d5818938 DV |
620 | intel_runtime_pm_disable_interrupts(dev_priv); |
621 | intel_hpd_cancel_work(dev_priv); | |
09b64267 | 622 | |
d5818938 | 623 | intel_suspend_encoders(dev_priv); |
0e32b39c | 624 | |
d5818938 | 625 | intel_suspend_hw(dev); |
5669fcac | 626 | |
828c7908 BW |
627 | i915_gem_suspend_gtt_mappings(dev); |
628 | ||
9e06dd39 JB |
629 | i915_save_state(dev); |
630 | ||
bc87229f | 631 | opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold; |
6f9f4b7a | 632 | intel_opregion_notify_adapter(dev_priv, opregion_target_state); |
e5747e3a | 633 | |
dc97997a | 634 | intel_uncore_forcewake_reset(dev_priv, false); |
03d92e47 | 635 | intel_opregion_unregister(dev_priv); |
8ee1c3db | 636 | |
82e3b8c1 | 637 | intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true); |
3fa016a0 | 638 | |
62d5d69b MK |
639 | dev_priv->suspend_count++; |
640 | ||
85e90679 KCA |
641 | intel_display_set_init_power(dev_priv, false); |
642 | ||
f74ed08d | 643 | intel_csr_ucode_suspend(dev_priv); |
f514c2d8 | 644 | |
1f814dac ID |
645 | out: |
646 | enable_rpm_wakeref_asserts(dev_priv); | |
647 | ||
648 | return error; | |
84b79f8d RW |
649 | } |
650 | ||
ab3be73f | 651 | static int i915_drm_suspend_late(struct drm_device *drm_dev, bool hibernation) |
c3c09c95 ID |
652 | { |
653 | struct drm_i915_private *dev_priv = drm_dev->dev_private; | |
bc87229f | 654 | bool fw_csr; |
c3c09c95 ID |
655 | int ret; |
656 | ||
1f814dac ID |
657 | disable_rpm_wakeref_asserts(dev_priv); |
658 | ||
a7c8125f ID |
659 | fw_csr = !IS_BROXTON(dev_priv) && |
660 | suspend_to_idle(dev_priv) && dev_priv->csr.dmc_payload; | |
bc87229f ID |
661 | /* |
662 | * In case of firmware assisted context save/restore don't manually | |
663 | * deinit the power domains. This also means the CSR/DMC firmware will | |
664 | * stay active, it will power down any HW resources as required and | |
665 | * also enable deeper system power states that would be blocked if the | |
666 | * firmware was inactive. | |
667 | */ | |
668 | if (!fw_csr) | |
669 | intel_power_domains_suspend(dev_priv); | |
73dfc227 | 670 | |
507e126e | 671 | ret = 0; |
b8aea3d1 | 672 | if (IS_BROXTON(dev_priv)) |
507e126e | 673 | bxt_enable_dc9(dev_priv); |
b8aea3d1 | 674 | else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
507e126e ID |
675 | hsw_enable_pc8(dev_priv); |
676 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
677 | ret = vlv_suspend_complete(dev_priv); | |
c3c09c95 ID |
678 | |
679 | if (ret) { | |
680 | DRM_ERROR("Suspend complete failed: %d\n", ret); | |
bc87229f ID |
681 | if (!fw_csr) |
682 | intel_power_domains_init_hw(dev_priv, true); | |
c3c09c95 | 683 | |
1f814dac | 684 | goto out; |
c3c09c95 ID |
685 | } |
686 | ||
687 | pci_disable_device(drm_dev->pdev); | |
ab3be73f | 688 | /* |
54875571 | 689 | * During hibernation on some platforms the BIOS may try to access |
ab3be73f ID |
690 | * the device even though it's already in D3 and hang the machine. So |
691 | * leave the device in D0 on those platforms and hope the BIOS will | |
54875571 ID |
692 | * power down the device properly. The issue was seen on multiple old |
693 | * GENs with different BIOS vendors, so having an explicit blacklist | |
694 | * is inpractical; apply the workaround on everything pre GEN6. The | |
695 | * platforms where the issue was seen: | |
696 | * Lenovo Thinkpad X301, X61s, X60, T60, X41 | |
697 | * Fujitsu FSC S7110 | |
698 | * Acer Aspire 1830T | |
ab3be73f | 699 | */ |
54875571 | 700 | if (!(hibernation && INTEL_INFO(dev_priv)->gen < 6)) |
ab3be73f | 701 | pci_set_power_state(drm_dev->pdev, PCI_D3hot); |
c3c09c95 | 702 | |
bc87229f ID |
703 | dev_priv->suspended_to_idle = suspend_to_idle(dev_priv); |
704 | ||
1f814dac ID |
705 | out: |
706 | enable_rpm_wakeref_asserts(dev_priv); | |
707 | ||
708 | return ret; | |
c3c09c95 ID |
709 | } |
710 | ||
1751fcf9 | 711 | int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state) |
84b79f8d RW |
712 | { |
713 | int error; | |
714 | ||
715 | if (!dev || !dev->dev_private) { | |
716 | DRM_ERROR("dev: %p\n", dev); | |
717 | DRM_ERROR("DRM not initialized, aborting suspend.\n"); | |
718 | return -ENODEV; | |
719 | } | |
720 | ||
0b14cbd2 ID |
721 | if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND && |
722 | state.event != PM_EVENT_FREEZE)) | |
723 | return -EINVAL; | |
5bcf719b DA |
724 | |
725 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) | |
726 | return 0; | |
6eecba33 | 727 | |
5e365c39 | 728 | error = i915_drm_suspend(dev); |
84b79f8d RW |
729 | if (error) |
730 | return error; | |
731 | ||
ab3be73f | 732 | return i915_drm_suspend_late(dev, false); |
ba8bbcf6 JB |
733 | } |
734 | ||
5e365c39 | 735 | static int i915_drm_resume(struct drm_device *dev) |
76c4b250 ID |
736 | { |
737 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ac840ae5 | 738 | int ret; |
9d49c0ef | 739 | |
1f814dac ID |
740 | disable_rpm_wakeref_asserts(dev_priv); |
741 | ||
ac840ae5 VS |
742 | ret = i915_ggtt_enable_hw(dev); |
743 | if (ret) | |
744 | DRM_ERROR("failed to re-enable GGTT\n"); | |
745 | ||
f74ed08d ID |
746 | intel_csr_ucode_resume(dev_priv); |
747 | ||
d5818938 DV |
748 | mutex_lock(&dev->struct_mutex); |
749 | i915_gem_restore_gtt_mappings(dev); | |
750 | mutex_unlock(&dev->struct_mutex); | |
9d49c0ef | 751 | |
61caf87c | 752 | i915_restore_state(dev); |
6f9f4b7a | 753 | intel_opregion_setup(dev_priv); |
61caf87c | 754 | |
d5818938 DV |
755 | intel_init_pch_refclk(dev); |
756 | drm_mode_config_reset(dev); | |
1833b134 | 757 | |
364aece0 PA |
758 | /* |
759 | * Interrupts have to be enabled before any batches are run. If not the | |
760 | * GPU will hang. i915_gem_init_hw() will initiate batches to | |
761 | * update/restore the context. | |
762 | * | |
763 | * Modeset enabling in intel_modeset_init_hw() also needs working | |
764 | * interrupts. | |
765 | */ | |
766 | intel_runtime_pm_enable_interrupts(dev_priv); | |
767 | ||
d5818938 DV |
768 | mutex_lock(&dev->struct_mutex); |
769 | if (i915_gem_init_hw(dev)) { | |
770 | DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n"); | |
805de8f4 | 771 | atomic_or(I915_WEDGED, &dev_priv->gpu_error.reset_counter); |
d5818938 DV |
772 | } |
773 | mutex_unlock(&dev->struct_mutex); | |
226485e9 | 774 | |
a1c41994 AD |
775 | intel_guc_resume(dev); |
776 | ||
d5818938 | 777 | intel_modeset_init_hw(dev); |
24576d23 | 778 | |
d5818938 DV |
779 | spin_lock_irq(&dev_priv->irq_lock); |
780 | if (dev_priv->display.hpd_irq_setup) | |
91d14251 | 781 | dev_priv->display.hpd_irq_setup(dev_priv); |
d5818938 | 782 | spin_unlock_irq(&dev_priv->irq_lock); |
0e32b39c | 783 | |
d5818938 | 784 | intel_dp_mst_resume(dev); |
e7d6f7d7 | 785 | |
a16b7658 L |
786 | intel_display_resume(dev); |
787 | ||
d5818938 DV |
788 | /* |
789 | * ... but also need to make sure that hotplug processing | |
790 | * doesn't cause havoc. Like in the driver load code we don't | |
791 | * bother with the tiny race here where we might loose hotplug | |
792 | * notifications. | |
793 | * */ | |
794 | intel_hpd_init(dev_priv); | |
795 | /* Config may have changed between suspend and resume */ | |
796 | drm_helper_hpd_irq_event(dev); | |
1daed3fb | 797 | |
03d92e47 | 798 | intel_opregion_register(dev_priv); |
44834a67 | 799 | |
82e3b8c1 | 800 | intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false); |
073f34d9 | 801 | |
b8efb17b ZR |
802 | mutex_lock(&dev_priv->modeset_restore_lock); |
803 | dev_priv->modeset_restore = MODESET_DONE; | |
804 | mutex_unlock(&dev_priv->modeset_restore_lock); | |
8a187455 | 805 | |
6f9f4b7a | 806 | intel_opregion_notify_adapter(dev_priv, PCI_D0); |
e5747e3a | 807 | |
ee6f280e ID |
808 | drm_kms_helper_poll_enable(dev); |
809 | ||
1f814dac ID |
810 | enable_rpm_wakeref_asserts(dev_priv); |
811 | ||
074c6ada | 812 | return 0; |
84b79f8d RW |
813 | } |
814 | ||
5e365c39 | 815 | static int i915_drm_resume_early(struct drm_device *dev) |
84b79f8d | 816 | { |
36d61e67 | 817 | struct drm_i915_private *dev_priv = dev->dev_private; |
44410cd0 | 818 | int ret; |
36d61e67 | 819 | |
76c4b250 ID |
820 | /* |
821 | * We have a resume ordering issue with the snd-hda driver also | |
822 | * requiring our device to be power up. Due to the lack of a | |
823 | * parent/child relationship we currently solve this with an early | |
824 | * resume hook. | |
825 | * | |
826 | * FIXME: This should be solved with a special hdmi sink device or | |
827 | * similar so that power domains can be employed. | |
828 | */ | |
44410cd0 ID |
829 | |
830 | /* | |
831 | * Note that we need to set the power state explicitly, since we | |
832 | * powered off the device during freeze and the PCI core won't power | |
833 | * it back up for us during thaw. Powering off the device during | |
834 | * freeze is not a hard requirement though, and during the | |
835 | * suspend/resume phases the PCI core makes sure we get here with the | |
836 | * device powered on. So in case we change our freeze logic and keep | |
837 | * the device powered we can also remove the following set power state | |
838 | * call. | |
839 | */ | |
840 | ret = pci_set_power_state(dev->pdev, PCI_D0); | |
841 | if (ret) { | |
842 | DRM_ERROR("failed to set PCI D0 power state (%d)\n", ret); | |
843 | goto out; | |
844 | } | |
845 | ||
846 | /* | |
847 | * Note that pci_enable_device() first enables any parent bridge | |
848 | * device and only then sets the power state for this device. The | |
849 | * bridge enabling is a nop though, since bridge devices are resumed | |
850 | * first. The order of enabling power and enabling the device is | |
851 | * imposed by the PCI core as described above, so here we preserve the | |
852 | * same order for the freeze/thaw phases. | |
853 | * | |
854 | * TODO: eventually we should remove pci_disable_device() / | |
855 | * pci_enable_enable_device() from suspend/resume. Due to how they | |
856 | * depend on the device enable refcount we can't anyway depend on them | |
857 | * disabling/enabling the device. | |
858 | */ | |
bc87229f ID |
859 | if (pci_enable_device(dev->pdev)) { |
860 | ret = -EIO; | |
861 | goto out; | |
862 | } | |
84b79f8d RW |
863 | |
864 | pci_set_master(dev->pdev); | |
865 | ||
1f814dac ID |
866 | disable_rpm_wakeref_asserts(dev_priv); |
867 | ||
666a4537 | 868 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
1a5df187 | 869 | ret = vlv_resume_prepare(dev_priv, false); |
36d61e67 | 870 | if (ret) |
ff0b187f DL |
871 | DRM_ERROR("Resume prepare failed: %d, continuing anyway\n", |
872 | ret); | |
36d61e67 | 873 | |
dc97997a | 874 | intel_uncore_early_sanitize(dev_priv, true); |
efee833a | 875 | |
dc97997a | 876 | if (IS_BROXTON(dev_priv)) { |
da2f41d1 ID |
877 | if (!dev_priv->suspended_to_idle) |
878 | gen9_sanitize_dc_state(dev_priv); | |
507e126e | 879 | bxt_disable_dc9(dev_priv); |
da2f41d1 | 880 | } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
a9a6b73a | 881 | hsw_disable_pc8(dev_priv); |
da2f41d1 | 882 | } |
efee833a | 883 | |
dc97997a | 884 | intel_uncore_sanitize(dev_priv); |
bc87229f | 885 | |
a7c8125f ID |
886 | if (IS_BROXTON(dev_priv) || |
887 | !(dev_priv->suspended_to_idle && dev_priv->csr.dmc_payload)) | |
bc87229f ID |
888 | intel_power_domains_init_hw(dev_priv, true); |
889 | ||
6e35e8ab ID |
890 | enable_rpm_wakeref_asserts(dev_priv); |
891 | ||
bc87229f ID |
892 | out: |
893 | dev_priv->suspended_to_idle = false; | |
36d61e67 ID |
894 | |
895 | return ret; | |
76c4b250 ID |
896 | } |
897 | ||
1751fcf9 | 898 | int i915_resume_switcheroo(struct drm_device *dev) |
76c4b250 | 899 | { |
50a0072f | 900 | int ret; |
76c4b250 | 901 | |
097dd837 ID |
902 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
903 | return 0; | |
904 | ||
5e365c39 | 905 | ret = i915_drm_resume_early(dev); |
50a0072f ID |
906 | if (ret) |
907 | return ret; | |
908 | ||
5a17514e ID |
909 | return i915_drm_resume(dev); |
910 | } | |
911 | ||
11ed50ec | 912 | /** |
f3953dcb | 913 | * i915_reset - reset chip after a hang |
11ed50ec | 914 | * @dev: drm device to reset |
11ed50ec BG |
915 | * |
916 | * Reset the chip. Useful if a hang is detected. Returns zero on successful | |
917 | * reset or otherwise an error code. | |
918 | * | |
919 | * Procedure is fairly simple: | |
920 | * - reset the chip using the reset reg | |
921 | * - re-init context state | |
922 | * - re-init hardware status page | |
923 | * - re-init ring buffer | |
924 | * - re-init interrupt state | |
925 | * - re-init display | |
926 | */ | |
c033666a | 927 | int i915_reset(struct drm_i915_private *dev_priv) |
11ed50ec | 928 | { |
c033666a | 929 | struct drm_device *dev = dev_priv->dev; |
d98c52cf CW |
930 | struct i915_gpu_error *error = &dev_priv->gpu_error; |
931 | unsigned reset_counter; | |
0573ed4a | 932 | int ret; |
11ed50ec | 933 | |
dc97997a | 934 | intel_reset_gt_powersave(dev_priv); |
dbea3cea | 935 | |
d54a02c0 | 936 | mutex_lock(&dev->struct_mutex); |
11ed50ec | 937 | |
d98c52cf CW |
938 | /* Clear any previous failed attempts at recovery. Time to try again. */ |
939 | atomic_andnot(I915_WEDGED, &error->reset_counter); | |
77f01230 | 940 | |
d98c52cf CW |
941 | /* Clear the reset-in-progress flag and increment the reset epoch. */ |
942 | reset_counter = atomic_inc_return(&error->reset_counter); | |
943 | if (WARN_ON(__i915_reset_in_progress(reset_counter))) { | |
944 | ret = -EIO; | |
945 | goto error; | |
946 | } | |
947 | ||
948 | i915_gem_reset(dev); | |
2e7c8ee7 | 949 | |
dc97997a | 950 | ret = intel_gpu_reset(dev_priv, ALL_ENGINES); |
be62acb4 MK |
951 | |
952 | /* Also reset the gpu hangman. */ | |
d98c52cf | 953 | if (error->stop_rings != 0) { |
be62acb4 | 954 | DRM_INFO("Simulated gpu hang, resetting stop_rings\n"); |
d98c52cf | 955 | error->stop_rings = 0; |
be62acb4 | 956 | if (ret == -ENODEV) { |
f2d91a2c DV |
957 | DRM_INFO("Reset not implemented, but ignoring " |
958 | "error for simulated gpu hangs\n"); | |
be62acb4 MK |
959 | ret = 0; |
960 | } | |
2e7c8ee7 | 961 | } |
be62acb4 | 962 | |
d8f2716a DV |
963 | if (i915_stop_ring_allow_warn(dev_priv)) |
964 | pr_notice("drm/i915: Resetting chip after gpu hang\n"); | |
965 | ||
0573ed4a | 966 | if (ret) { |
804e59a8 CW |
967 | if (ret != -ENODEV) |
968 | DRM_ERROR("Failed to reset chip: %i\n", ret); | |
969 | else | |
970 | DRM_DEBUG_DRIVER("GPU reset disabled\n"); | |
d98c52cf | 971 | goto error; |
11ed50ec BG |
972 | } |
973 | ||
1362b776 VS |
974 | intel_overlay_reset(dev_priv); |
975 | ||
11ed50ec BG |
976 | /* Ok, now get things going again... */ |
977 | ||
978 | /* | |
979 | * Everything depends on having the GTT running, so we need to start | |
980 | * there. Fortunately we don't need to do this unless we reset the | |
981 | * chip at a PCI level. | |
982 | * | |
983 | * Next we need to restore the context, but we don't use those | |
984 | * yet either... | |
985 | * | |
986 | * Ring buffer needs to be re-initialized in the KMS case, or if X | |
987 | * was running at the time of the reset (i.e. we weren't VT | |
988 | * switched away). | |
989 | */ | |
33d30a9c | 990 | ret = i915_gem_init_hw(dev); |
33d30a9c DV |
991 | if (ret) { |
992 | DRM_ERROR("Failed hw init on reset %d\n", ret); | |
d98c52cf | 993 | goto error; |
11ed50ec BG |
994 | } |
995 | ||
d98c52cf CW |
996 | mutex_unlock(&dev->struct_mutex); |
997 | ||
33d30a9c DV |
998 | /* |
999 | * rps/rc6 re-init is necessary to restore state lost after the | |
1000 | * reset and the re-install of gt irqs. Skip for ironlake per | |
1001 | * previous concerns that it doesn't respond well to some forms | |
1002 | * of re-init after reset. | |
1003 | */ | |
1004 | if (INTEL_INFO(dev)->gen > 5) | |
dc97997a | 1005 | intel_enable_gt_powersave(dev_priv); |
33d30a9c | 1006 | |
11ed50ec | 1007 | return 0; |
d98c52cf CW |
1008 | |
1009 | error: | |
1010 | atomic_or(I915_WEDGED, &error->reset_counter); | |
1011 | mutex_unlock(&dev->struct_mutex); | |
1012 | return ret; | |
11ed50ec BG |
1013 | } |
1014 | ||
56550d94 | 1015 | static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) |
112b715e | 1016 | { |
01a06850 DV |
1017 | struct intel_device_info *intel_info = |
1018 | (struct intel_device_info *) ent->driver_data; | |
1019 | ||
d330a953 | 1020 | if (IS_PRELIMINARY_HW(intel_info) && !i915.preliminary_hw_support) { |
b833d685 BW |
1021 | DRM_INFO("This hardware requires preliminary hardware support.\n" |
1022 | "See CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT, and/or modparam preliminary_hw_support\n"); | |
1023 | return -ENODEV; | |
1024 | } | |
1025 | ||
5fe49d86 CW |
1026 | /* Only bind to function 0 of the device. Early generations |
1027 | * used function 1 as a placeholder for multi-head. This causes | |
1028 | * us confusion instead, especially on the systems where both | |
1029 | * functions have the same PCI-ID! | |
1030 | */ | |
1031 | if (PCI_FUNC(pdev->devfn)) | |
1032 | return -ENODEV; | |
1033 | ||
b00e5334 | 1034 | if (vga_switcheroo_client_probe_defer(pdev)) |
704ab614 LW |
1035 | return -EPROBE_DEFER; |
1036 | ||
dcdb1674 | 1037 | return drm_get_pci_dev(pdev, ent, &driver); |
112b715e KH |
1038 | } |
1039 | ||
1040 | static void | |
1041 | i915_pci_remove(struct pci_dev *pdev) | |
1042 | { | |
1043 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1044 | ||
1045 | drm_put_dev(dev); | |
1046 | } | |
1047 | ||
84b79f8d | 1048 | static int i915_pm_suspend(struct device *dev) |
112b715e | 1049 | { |
84b79f8d RW |
1050 | struct pci_dev *pdev = to_pci_dev(dev); |
1051 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
112b715e | 1052 | |
84b79f8d RW |
1053 | if (!drm_dev || !drm_dev->dev_private) { |
1054 | dev_err(dev, "DRM not initialized, aborting suspend.\n"); | |
1055 | return -ENODEV; | |
1056 | } | |
112b715e | 1057 | |
5bcf719b DA |
1058 | if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
1059 | return 0; | |
1060 | ||
5e365c39 | 1061 | return i915_drm_suspend(drm_dev); |
76c4b250 ID |
1062 | } |
1063 | ||
1064 | static int i915_pm_suspend_late(struct device *dev) | |
1065 | { | |
888d0d42 | 1066 | struct drm_device *drm_dev = dev_to_i915(dev)->dev; |
76c4b250 ID |
1067 | |
1068 | /* | |
c965d995 | 1069 | * We have a suspend ordering issue with the snd-hda driver also |
76c4b250 ID |
1070 | * requiring our device to be power up. Due to the lack of a |
1071 | * parent/child relationship we currently solve this with an late | |
1072 | * suspend hook. | |
1073 | * | |
1074 | * FIXME: This should be solved with a special hdmi sink device or | |
1075 | * similar so that power domains can be employed. | |
1076 | */ | |
1077 | if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF) | |
1078 | return 0; | |
112b715e | 1079 | |
ab3be73f ID |
1080 | return i915_drm_suspend_late(drm_dev, false); |
1081 | } | |
1082 | ||
1083 | static int i915_pm_poweroff_late(struct device *dev) | |
1084 | { | |
1085 | struct drm_device *drm_dev = dev_to_i915(dev)->dev; | |
1086 | ||
1087 | if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF) | |
1088 | return 0; | |
1089 | ||
1090 | return i915_drm_suspend_late(drm_dev, true); | |
cbda12d7 ZW |
1091 | } |
1092 | ||
76c4b250 ID |
1093 | static int i915_pm_resume_early(struct device *dev) |
1094 | { | |
888d0d42 | 1095 | struct drm_device *drm_dev = dev_to_i915(dev)->dev; |
76c4b250 | 1096 | |
097dd837 ID |
1097 | if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
1098 | return 0; | |
1099 | ||
5e365c39 | 1100 | return i915_drm_resume_early(drm_dev); |
76c4b250 ID |
1101 | } |
1102 | ||
84b79f8d | 1103 | static int i915_pm_resume(struct device *dev) |
cbda12d7 | 1104 | { |
888d0d42 | 1105 | struct drm_device *drm_dev = dev_to_i915(dev)->dev; |
84b79f8d | 1106 | |
097dd837 ID |
1107 | if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
1108 | return 0; | |
1109 | ||
5a17514e | 1110 | return i915_drm_resume(drm_dev); |
cbda12d7 ZW |
1111 | } |
1112 | ||
1f19ac2a CW |
1113 | /* freeze: before creating the hibernation_image */ |
1114 | static int i915_pm_freeze(struct device *dev) | |
1115 | { | |
1116 | return i915_pm_suspend(dev); | |
1117 | } | |
1118 | ||
1119 | static int i915_pm_freeze_late(struct device *dev) | |
1120 | { | |
461fb99c CW |
1121 | int ret; |
1122 | ||
1123 | ret = i915_pm_suspend_late(dev); | |
1124 | if (ret) | |
1125 | return ret; | |
1126 | ||
1127 | ret = i915_gem_freeze_late(dev_to_i915(dev)); | |
1128 | if (ret) | |
1129 | return ret; | |
1130 | ||
1131 | return 0; | |
1f19ac2a CW |
1132 | } |
1133 | ||
1134 | /* thaw: called after creating the hibernation image, but before turning off. */ | |
1135 | static int i915_pm_thaw_early(struct device *dev) | |
1136 | { | |
1137 | return i915_pm_resume_early(dev); | |
1138 | } | |
1139 | ||
1140 | static int i915_pm_thaw(struct device *dev) | |
1141 | { | |
1142 | return i915_pm_resume(dev); | |
1143 | } | |
1144 | ||
1145 | /* restore: called after loading the hibernation image. */ | |
1146 | static int i915_pm_restore_early(struct device *dev) | |
1147 | { | |
1148 | return i915_pm_resume_early(dev); | |
1149 | } | |
1150 | ||
1151 | static int i915_pm_restore(struct device *dev) | |
1152 | { | |
1153 | return i915_pm_resume(dev); | |
1154 | } | |
1155 | ||
ddeea5b0 ID |
1156 | /* |
1157 | * Save all Gunit registers that may be lost after a D3 and a subsequent | |
1158 | * S0i[R123] transition. The list of registers needing a save/restore is | |
1159 | * defined in the VLV2_S0IXRegs document. This documents marks all Gunit | |
1160 | * registers in the following way: | |
1161 | * - Driver: saved/restored by the driver | |
1162 | * - Punit : saved/restored by the Punit firmware | |
1163 | * - No, w/o marking: no need to save/restore, since the register is R/O or | |
1164 | * used internally by the HW in a way that doesn't depend | |
1165 | * keeping the content across a suspend/resume. | |
1166 | * - Debug : used for debugging | |
1167 | * | |
1168 | * We save/restore all registers marked with 'Driver', with the following | |
1169 | * exceptions: | |
1170 | * - Registers out of use, including also registers marked with 'Debug'. | |
1171 | * These have no effect on the driver's operation, so we don't save/restore | |
1172 | * them to reduce the overhead. | |
1173 | * - Registers that are fully setup by an initialization function called from | |
1174 | * the resume path. For example many clock gating and RPS/RC6 registers. | |
1175 | * - Registers that provide the right functionality with their reset defaults. | |
1176 | * | |
1177 | * TODO: Except for registers that based on the above 3 criteria can be safely | |
1178 | * ignored, we save/restore all others, practically treating the HW context as | |
1179 | * a black-box for the driver. Further investigation is needed to reduce the | |
1180 | * saved/restored registers even further, by following the same 3 criteria. | |
1181 | */ | |
1182 | static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv) | |
1183 | { | |
1184 | struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state; | |
1185 | int i; | |
1186 | ||
1187 | /* GAM 0x4000-0x4770 */ | |
1188 | s->wr_watermark = I915_READ(GEN7_WR_WATERMARK); | |
1189 | s->gfx_prio_ctrl = I915_READ(GEN7_GFX_PRIO_CTRL); | |
1190 | s->arb_mode = I915_READ(ARB_MODE); | |
1191 | s->gfx_pend_tlb0 = I915_READ(GEN7_GFX_PEND_TLB0); | |
1192 | s->gfx_pend_tlb1 = I915_READ(GEN7_GFX_PEND_TLB1); | |
1193 | ||
1194 | for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++) | |
22dfe79f | 1195 | s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i)); |
ddeea5b0 ID |
1196 | |
1197 | s->media_max_req_count = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT); | |
b5f1c97f | 1198 | s->gfx_max_req_count = I915_READ(GEN7_GFX_MAX_REQ_COUNT); |
ddeea5b0 ID |
1199 | |
1200 | s->render_hwsp = I915_READ(RENDER_HWS_PGA_GEN7); | |
1201 | s->ecochk = I915_READ(GAM_ECOCHK); | |
1202 | s->bsd_hwsp = I915_READ(BSD_HWS_PGA_GEN7); | |
1203 | s->blt_hwsp = I915_READ(BLT_HWS_PGA_GEN7); | |
1204 | ||
1205 | s->tlb_rd_addr = I915_READ(GEN7_TLB_RD_ADDR); | |
1206 | ||
1207 | /* MBC 0x9024-0x91D0, 0x8500 */ | |
1208 | s->g3dctl = I915_READ(VLV_G3DCTL); | |
1209 | s->gsckgctl = I915_READ(VLV_GSCKGCTL); | |
1210 | s->mbctl = I915_READ(GEN6_MBCTL); | |
1211 | ||
1212 | /* GCP 0x9400-0x9424, 0x8100-0x810C */ | |
1213 | s->ucgctl1 = I915_READ(GEN6_UCGCTL1); | |
1214 | s->ucgctl3 = I915_READ(GEN6_UCGCTL3); | |
1215 | s->rcgctl1 = I915_READ(GEN6_RCGCTL1); | |
1216 | s->rcgctl2 = I915_READ(GEN6_RCGCTL2); | |
1217 | s->rstctl = I915_READ(GEN6_RSTCTL); | |
1218 | s->misccpctl = I915_READ(GEN7_MISCCPCTL); | |
1219 | ||
1220 | /* GPM 0xA000-0xAA84, 0x8000-0x80FC */ | |
1221 | s->gfxpause = I915_READ(GEN6_GFXPAUSE); | |
1222 | s->rpdeuhwtc = I915_READ(GEN6_RPDEUHWTC); | |
1223 | s->rpdeuc = I915_READ(GEN6_RPDEUC); | |
1224 | s->ecobus = I915_READ(ECOBUS); | |
1225 | s->pwrdwnupctl = I915_READ(VLV_PWRDWNUPCTL); | |
1226 | s->rp_down_timeout = I915_READ(GEN6_RP_DOWN_TIMEOUT); | |
1227 | s->rp_deucsw = I915_READ(GEN6_RPDEUCSW); | |
1228 | s->rcubmabdtmr = I915_READ(GEN6_RCUBMABDTMR); | |
1229 | s->rcedata = I915_READ(VLV_RCEDATA); | |
1230 | s->spare2gh = I915_READ(VLV_SPAREG2H); | |
1231 | ||
1232 | /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */ | |
1233 | s->gt_imr = I915_READ(GTIMR); | |
1234 | s->gt_ier = I915_READ(GTIER); | |
1235 | s->pm_imr = I915_READ(GEN6_PMIMR); | |
1236 | s->pm_ier = I915_READ(GEN6_PMIER); | |
1237 | ||
1238 | for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++) | |
22dfe79f | 1239 | s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i)); |
ddeea5b0 ID |
1240 | |
1241 | /* GT SA CZ domain, 0x100000-0x138124 */ | |
1242 | s->tilectl = I915_READ(TILECTL); | |
1243 | s->gt_fifoctl = I915_READ(GTFIFOCTL); | |
1244 | s->gtlc_wake_ctrl = I915_READ(VLV_GTLC_WAKE_CTRL); | |
1245 | s->gtlc_survive = I915_READ(VLV_GTLC_SURVIVABILITY_REG); | |
1246 | s->pmwgicz = I915_READ(VLV_PMWGICZ); | |
1247 | ||
1248 | /* Gunit-Display CZ domain, 0x182028-0x1821CF */ | |
1249 | s->gu_ctl0 = I915_READ(VLV_GU_CTL0); | |
1250 | s->gu_ctl1 = I915_READ(VLV_GU_CTL1); | |
9c25210f | 1251 | s->pcbr = I915_READ(VLV_PCBR); |
ddeea5b0 ID |
1252 | s->clock_gate_dis2 = I915_READ(VLV_GUNIT_CLOCK_GATE2); |
1253 | ||
1254 | /* | |
1255 | * Not saving any of: | |
1256 | * DFT, 0x9800-0x9EC0 | |
1257 | * SARB, 0xB000-0xB1FC | |
1258 | * GAC, 0x5208-0x524C, 0x14000-0x14C000 | |
1259 | * PCI CFG | |
1260 | */ | |
1261 | } | |
1262 | ||
1263 | static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv) | |
1264 | { | |
1265 | struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state; | |
1266 | u32 val; | |
1267 | int i; | |
1268 | ||
1269 | /* GAM 0x4000-0x4770 */ | |
1270 | I915_WRITE(GEN7_WR_WATERMARK, s->wr_watermark); | |
1271 | I915_WRITE(GEN7_GFX_PRIO_CTRL, s->gfx_prio_ctrl); | |
1272 | I915_WRITE(ARB_MODE, s->arb_mode | (0xffff << 16)); | |
1273 | I915_WRITE(GEN7_GFX_PEND_TLB0, s->gfx_pend_tlb0); | |
1274 | I915_WRITE(GEN7_GFX_PEND_TLB1, s->gfx_pend_tlb1); | |
1275 | ||
1276 | for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++) | |
22dfe79f | 1277 | I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]); |
ddeea5b0 ID |
1278 | |
1279 | I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count); | |
b5f1c97f | 1280 | I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count); |
ddeea5b0 ID |
1281 | |
1282 | I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp); | |
1283 | I915_WRITE(GAM_ECOCHK, s->ecochk); | |
1284 | I915_WRITE(BSD_HWS_PGA_GEN7, s->bsd_hwsp); | |
1285 | I915_WRITE(BLT_HWS_PGA_GEN7, s->blt_hwsp); | |
1286 | ||
1287 | I915_WRITE(GEN7_TLB_RD_ADDR, s->tlb_rd_addr); | |
1288 | ||
1289 | /* MBC 0x9024-0x91D0, 0x8500 */ | |
1290 | I915_WRITE(VLV_G3DCTL, s->g3dctl); | |
1291 | I915_WRITE(VLV_GSCKGCTL, s->gsckgctl); | |
1292 | I915_WRITE(GEN6_MBCTL, s->mbctl); | |
1293 | ||
1294 | /* GCP 0x9400-0x9424, 0x8100-0x810C */ | |
1295 | I915_WRITE(GEN6_UCGCTL1, s->ucgctl1); | |
1296 | I915_WRITE(GEN6_UCGCTL3, s->ucgctl3); | |
1297 | I915_WRITE(GEN6_RCGCTL1, s->rcgctl1); | |
1298 | I915_WRITE(GEN6_RCGCTL2, s->rcgctl2); | |
1299 | I915_WRITE(GEN6_RSTCTL, s->rstctl); | |
1300 | I915_WRITE(GEN7_MISCCPCTL, s->misccpctl); | |
1301 | ||
1302 | /* GPM 0xA000-0xAA84, 0x8000-0x80FC */ | |
1303 | I915_WRITE(GEN6_GFXPAUSE, s->gfxpause); | |
1304 | I915_WRITE(GEN6_RPDEUHWTC, s->rpdeuhwtc); | |
1305 | I915_WRITE(GEN6_RPDEUC, s->rpdeuc); | |
1306 | I915_WRITE(ECOBUS, s->ecobus); | |
1307 | I915_WRITE(VLV_PWRDWNUPCTL, s->pwrdwnupctl); | |
1308 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout); | |
1309 | I915_WRITE(GEN6_RPDEUCSW, s->rp_deucsw); | |
1310 | I915_WRITE(GEN6_RCUBMABDTMR, s->rcubmabdtmr); | |
1311 | I915_WRITE(VLV_RCEDATA, s->rcedata); | |
1312 | I915_WRITE(VLV_SPAREG2H, s->spare2gh); | |
1313 | ||
1314 | /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */ | |
1315 | I915_WRITE(GTIMR, s->gt_imr); | |
1316 | I915_WRITE(GTIER, s->gt_ier); | |
1317 | I915_WRITE(GEN6_PMIMR, s->pm_imr); | |
1318 | I915_WRITE(GEN6_PMIER, s->pm_ier); | |
1319 | ||
1320 | for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++) | |
22dfe79f | 1321 | I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]); |
ddeea5b0 ID |
1322 | |
1323 | /* GT SA CZ domain, 0x100000-0x138124 */ | |
1324 | I915_WRITE(TILECTL, s->tilectl); | |
1325 | I915_WRITE(GTFIFOCTL, s->gt_fifoctl); | |
1326 | /* | |
1327 | * Preserve the GT allow wake and GFX force clock bit, they are not | |
1328 | * be restored, as they are used to control the s0ix suspend/resume | |
1329 | * sequence by the caller. | |
1330 | */ | |
1331 | val = I915_READ(VLV_GTLC_WAKE_CTRL); | |
1332 | val &= VLV_GTLC_ALLOWWAKEREQ; | |
1333 | val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ; | |
1334 | I915_WRITE(VLV_GTLC_WAKE_CTRL, val); | |
1335 | ||
1336 | val = I915_READ(VLV_GTLC_SURVIVABILITY_REG); | |
1337 | val &= VLV_GFX_CLK_FORCE_ON_BIT; | |
1338 | val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT; | |
1339 | I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val); | |
1340 | ||
1341 | I915_WRITE(VLV_PMWGICZ, s->pmwgicz); | |
1342 | ||
1343 | /* Gunit-Display CZ domain, 0x182028-0x1821CF */ | |
1344 | I915_WRITE(VLV_GU_CTL0, s->gu_ctl0); | |
1345 | I915_WRITE(VLV_GU_CTL1, s->gu_ctl1); | |
9c25210f | 1346 | I915_WRITE(VLV_PCBR, s->pcbr); |
ddeea5b0 ID |
1347 | I915_WRITE(VLV_GUNIT_CLOCK_GATE2, s->clock_gate_dis2); |
1348 | } | |
1349 | ||
650ad970 ID |
1350 | int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on) |
1351 | { | |
1352 | u32 val; | |
1353 | int err; | |
1354 | ||
650ad970 | 1355 | #define COND (I915_READ(VLV_GTLC_SURVIVABILITY_REG) & VLV_GFX_CLK_STATUS_BIT) |
650ad970 ID |
1356 | |
1357 | val = I915_READ(VLV_GTLC_SURVIVABILITY_REG); | |
1358 | val &= ~VLV_GFX_CLK_FORCE_ON_BIT; | |
1359 | if (force_on) | |
1360 | val |= VLV_GFX_CLK_FORCE_ON_BIT; | |
1361 | I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val); | |
1362 | ||
1363 | if (!force_on) | |
1364 | return 0; | |
1365 | ||
8d4eee9c | 1366 | err = wait_for(COND, 20); |
650ad970 ID |
1367 | if (err) |
1368 | DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n", | |
1369 | I915_READ(VLV_GTLC_SURVIVABILITY_REG)); | |
1370 | ||
1371 | return err; | |
1372 | #undef COND | |
1373 | } | |
1374 | ||
ddeea5b0 ID |
1375 | static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow) |
1376 | { | |
1377 | u32 val; | |
1378 | int err = 0; | |
1379 | ||
1380 | val = I915_READ(VLV_GTLC_WAKE_CTRL); | |
1381 | val &= ~VLV_GTLC_ALLOWWAKEREQ; | |
1382 | if (allow) | |
1383 | val |= VLV_GTLC_ALLOWWAKEREQ; | |
1384 | I915_WRITE(VLV_GTLC_WAKE_CTRL, val); | |
1385 | POSTING_READ(VLV_GTLC_WAKE_CTRL); | |
1386 | ||
1387 | #define COND (!!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEACK) == \ | |
1388 | allow) | |
1389 | err = wait_for(COND, 1); | |
1390 | if (err) | |
1391 | DRM_ERROR("timeout disabling GT waking\n"); | |
1392 | return err; | |
1393 | #undef COND | |
1394 | } | |
1395 | ||
1396 | static int vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv, | |
1397 | bool wait_for_on) | |
1398 | { | |
1399 | u32 mask; | |
1400 | u32 val; | |
1401 | int err; | |
1402 | ||
1403 | mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK; | |
1404 | val = wait_for_on ? mask : 0; | |
1405 | #define COND ((I915_READ(VLV_GTLC_PW_STATUS) & mask) == val) | |
1406 | if (COND) | |
1407 | return 0; | |
1408 | ||
1409 | DRM_DEBUG_KMS("waiting for GT wells to go %s (%08x)\n", | |
87ad3212 JN |
1410 | onoff(wait_for_on), |
1411 | I915_READ(VLV_GTLC_PW_STATUS)); | |
ddeea5b0 ID |
1412 | |
1413 | /* | |
1414 | * RC6 transitioning can be delayed up to 2 msec (see | |
1415 | * valleyview_enable_rps), use 3 msec for safety. | |
1416 | */ | |
1417 | err = wait_for(COND, 3); | |
1418 | if (err) | |
1419 | DRM_ERROR("timeout waiting for GT wells to go %s\n", | |
87ad3212 | 1420 | onoff(wait_for_on)); |
ddeea5b0 ID |
1421 | |
1422 | return err; | |
1423 | #undef COND | |
1424 | } | |
1425 | ||
1426 | static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv) | |
1427 | { | |
1428 | if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR)) | |
1429 | return; | |
1430 | ||
6fa283b0 | 1431 | DRM_DEBUG_DRIVER("GT register access while GT waking disabled\n"); |
ddeea5b0 ID |
1432 | I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR); |
1433 | } | |
1434 | ||
ebc32824 | 1435 | static int vlv_suspend_complete(struct drm_i915_private *dev_priv) |
ddeea5b0 ID |
1436 | { |
1437 | u32 mask; | |
1438 | int err; | |
1439 | ||
1440 | /* | |
1441 | * Bspec defines the following GT well on flags as debug only, so | |
1442 | * don't treat them as hard failures. | |
1443 | */ | |
1444 | (void)vlv_wait_for_gt_wells(dev_priv, false); | |
1445 | ||
1446 | mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS; | |
1447 | WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask); | |
1448 | ||
1449 | vlv_check_no_gt_access(dev_priv); | |
1450 | ||
1451 | err = vlv_force_gfx_clock(dev_priv, true); | |
1452 | if (err) | |
1453 | goto err1; | |
1454 | ||
1455 | err = vlv_allow_gt_wake(dev_priv, false); | |
1456 | if (err) | |
1457 | goto err2; | |
98711167 | 1458 | |
2d1fe073 | 1459 | if (!IS_CHERRYVIEW(dev_priv)) |
98711167 | 1460 | vlv_save_gunit_s0ix_state(dev_priv); |
ddeea5b0 ID |
1461 | |
1462 | err = vlv_force_gfx_clock(dev_priv, false); | |
1463 | if (err) | |
1464 | goto err2; | |
1465 | ||
1466 | return 0; | |
1467 | ||
1468 | err2: | |
1469 | /* For safety always re-enable waking and disable gfx clock forcing */ | |
1470 | vlv_allow_gt_wake(dev_priv, true); | |
1471 | err1: | |
1472 | vlv_force_gfx_clock(dev_priv, false); | |
1473 | ||
1474 | return err; | |
1475 | } | |
1476 | ||
016970be SK |
1477 | static int vlv_resume_prepare(struct drm_i915_private *dev_priv, |
1478 | bool rpm_resume) | |
ddeea5b0 ID |
1479 | { |
1480 | struct drm_device *dev = dev_priv->dev; | |
1481 | int err; | |
1482 | int ret; | |
1483 | ||
1484 | /* | |
1485 | * If any of the steps fail just try to continue, that's the best we | |
1486 | * can do at this point. Return the first error code (which will also | |
1487 | * leave RPM permanently disabled). | |
1488 | */ | |
1489 | ret = vlv_force_gfx_clock(dev_priv, true); | |
1490 | ||
2d1fe073 | 1491 | if (!IS_CHERRYVIEW(dev_priv)) |
98711167 | 1492 | vlv_restore_gunit_s0ix_state(dev_priv); |
ddeea5b0 ID |
1493 | |
1494 | err = vlv_allow_gt_wake(dev_priv, true); | |
1495 | if (!ret) | |
1496 | ret = err; | |
1497 | ||
1498 | err = vlv_force_gfx_clock(dev_priv, false); | |
1499 | if (!ret) | |
1500 | ret = err; | |
1501 | ||
1502 | vlv_check_no_gt_access(dev_priv); | |
1503 | ||
016970be SK |
1504 | if (rpm_resume) { |
1505 | intel_init_clock_gating(dev); | |
1506 | i915_gem_restore_fences(dev); | |
1507 | } | |
ddeea5b0 ID |
1508 | |
1509 | return ret; | |
1510 | } | |
1511 | ||
97bea207 | 1512 | static int intel_runtime_suspend(struct device *device) |
8a187455 PZ |
1513 | { |
1514 | struct pci_dev *pdev = to_pci_dev(device); | |
1515 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1516 | struct drm_i915_private *dev_priv = dev->dev_private; | |
0ab9cfeb | 1517 | int ret; |
8a187455 | 1518 | |
dc97997a | 1519 | if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6()))) |
c6df39b5 ID |
1520 | return -ENODEV; |
1521 | ||
604effb7 ID |
1522 | if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev))) |
1523 | return -ENODEV; | |
1524 | ||
8a187455 PZ |
1525 | DRM_DEBUG_KMS("Suspending device\n"); |
1526 | ||
d6102977 ID |
1527 | /* |
1528 | * We could deadlock here in case another thread holding struct_mutex | |
1529 | * calls RPM suspend concurrently, since the RPM suspend will wait | |
1530 | * first for this RPM suspend to finish. In this case the concurrent | |
1531 | * RPM resume will be followed by its RPM suspend counterpart. Still | |
1532 | * for consistency return -EAGAIN, which will reschedule this suspend. | |
1533 | */ | |
1534 | if (!mutex_trylock(&dev->struct_mutex)) { | |
1535 | DRM_DEBUG_KMS("device lock contention, deffering suspend\n"); | |
1536 | /* | |
1537 | * Bump the expiration timestamp, otherwise the suspend won't | |
1538 | * be rescheduled. | |
1539 | */ | |
1540 | pm_runtime_mark_last_busy(device); | |
1541 | ||
1542 | return -EAGAIN; | |
1543 | } | |
1f814dac ID |
1544 | |
1545 | disable_rpm_wakeref_asserts(dev_priv); | |
1546 | ||
d6102977 ID |
1547 | /* |
1548 | * We are safe here against re-faults, since the fault handler takes | |
1549 | * an RPM reference. | |
1550 | */ | |
1551 | i915_gem_release_all_mmaps(dev_priv); | |
1552 | mutex_unlock(&dev->struct_mutex); | |
1553 | ||
825f2728 JL |
1554 | cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work); |
1555 | ||
a1c41994 AD |
1556 | intel_guc_suspend(dev); |
1557 | ||
dc97997a | 1558 | intel_suspend_gt_powersave(dev_priv); |
2eb5252e | 1559 | intel_runtime_pm_disable_interrupts(dev_priv); |
b5478bcd | 1560 | |
507e126e ID |
1561 | ret = 0; |
1562 | if (IS_BROXTON(dev_priv)) { | |
1563 | bxt_display_core_uninit(dev_priv); | |
1564 | bxt_enable_dc9(dev_priv); | |
1565 | } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { | |
1566 | hsw_enable_pc8(dev_priv); | |
1567 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { | |
1568 | ret = vlv_suspend_complete(dev_priv); | |
1569 | } | |
1570 | ||
0ab9cfeb ID |
1571 | if (ret) { |
1572 | DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret); | |
b963291c | 1573 | intel_runtime_pm_enable_interrupts(dev_priv); |
0ab9cfeb | 1574 | |
1f814dac ID |
1575 | enable_rpm_wakeref_asserts(dev_priv); |
1576 | ||
0ab9cfeb ID |
1577 | return ret; |
1578 | } | |
a8a8bd54 | 1579 | |
dc97997a | 1580 | intel_uncore_forcewake_reset(dev_priv, false); |
1f814dac ID |
1581 | |
1582 | enable_rpm_wakeref_asserts(dev_priv); | |
1583 | WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count)); | |
55ec45c2 | 1584 | |
bc3b9346 | 1585 | if (intel_uncore_arm_unclaimed_mmio_detection(dev_priv)) |
55ec45c2 MK |
1586 | DRM_ERROR("Unclaimed access detected prior to suspending\n"); |
1587 | ||
8a187455 | 1588 | dev_priv->pm.suspended = true; |
1fb2362b KCA |
1589 | |
1590 | /* | |
c8a0bd42 PZ |
1591 | * FIXME: We really should find a document that references the arguments |
1592 | * used below! | |
1fb2362b | 1593 | */ |
6f9f4b7a | 1594 | if (IS_BROADWELL(dev_priv)) { |
d37ae19a PZ |
1595 | /* |
1596 | * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop | |
1597 | * being detected, and the call we do at intel_runtime_resume() | |
1598 | * won't be able to restore them. Since PCI_D3hot matches the | |
1599 | * actual specification and appears to be working, use it. | |
1600 | */ | |
6f9f4b7a | 1601 | intel_opregion_notify_adapter(dev_priv, PCI_D3hot); |
d37ae19a | 1602 | } else { |
c8a0bd42 PZ |
1603 | /* |
1604 | * current versions of firmware which depend on this opregion | |
1605 | * notification have repurposed the D1 definition to mean | |
1606 | * "runtime suspended" vs. what you would normally expect (D3) | |
1607 | * to distinguish it from notifications that might be sent via | |
1608 | * the suspend path. | |
1609 | */ | |
6f9f4b7a | 1610 | intel_opregion_notify_adapter(dev_priv, PCI_D1); |
c8a0bd42 | 1611 | } |
8a187455 | 1612 | |
59bad947 | 1613 | assert_forcewakes_inactive(dev_priv); |
dc9fb09c | 1614 | |
a8a8bd54 | 1615 | DRM_DEBUG_KMS("Device suspended\n"); |
8a187455 PZ |
1616 | return 0; |
1617 | } | |
1618 | ||
97bea207 | 1619 | static int intel_runtime_resume(struct device *device) |
8a187455 PZ |
1620 | { |
1621 | struct pci_dev *pdev = to_pci_dev(device); | |
1622 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1623 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1a5df187 | 1624 | int ret = 0; |
8a187455 | 1625 | |
604effb7 ID |
1626 | if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev))) |
1627 | return -ENODEV; | |
8a187455 PZ |
1628 | |
1629 | DRM_DEBUG_KMS("Resuming device\n"); | |
1630 | ||
1f814dac ID |
1631 | WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count)); |
1632 | disable_rpm_wakeref_asserts(dev_priv); | |
1633 | ||
6f9f4b7a | 1634 | intel_opregion_notify_adapter(dev_priv, PCI_D0); |
8a187455 | 1635 | dev_priv->pm.suspended = false; |
55ec45c2 MK |
1636 | if (intel_uncore_unclaimed_mmio(dev_priv)) |
1637 | DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n"); | |
8a187455 | 1638 | |
a1c41994 AD |
1639 | intel_guc_resume(dev); |
1640 | ||
1a5df187 PZ |
1641 | if (IS_GEN6(dev_priv)) |
1642 | intel_init_pch_refclk(dev); | |
31335cec | 1643 | |
507e126e ID |
1644 | if (IS_BROXTON(dev)) { |
1645 | bxt_disable_dc9(dev_priv); | |
1646 | bxt_display_core_init(dev_priv, true); | |
f62c79b3 ID |
1647 | if (dev_priv->csr.dmc_payload && |
1648 | (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5)) | |
1649 | gen9_enable_dc5(dev_priv); | |
507e126e | 1650 | } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
1a5df187 | 1651 | hsw_disable_pc8(dev_priv); |
507e126e | 1652 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
1a5df187 | 1653 | ret = vlv_resume_prepare(dev_priv, true); |
507e126e | 1654 | } |
1a5df187 | 1655 | |
0ab9cfeb ID |
1656 | /* |
1657 | * No point of rolling back things in case of an error, as the best | |
1658 | * we can do is to hope that things will still work (and disable RPM). | |
1659 | */ | |
92b806d3 | 1660 | i915_gem_init_swizzling(dev); |
dc97997a | 1661 | gen6_update_ring_freq(dev_priv); |
92b806d3 | 1662 | |
b963291c | 1663 | intel_runtime_pm_enable_interrupts(dev_priv); |
08d8a232 VS |
1664 | |
1665 | /* | |
1666 | * On VLV/CHV display interrupts are part of the display | |
1667 | * power well, so hpd is reinitialized from there. For | |
1668 | * everyone else do it here. | |
1669 | */ | |
666a4537 | 1670 | if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) |
08d8a232 VS |
1671 | intel_hpd_init(dev_priv); |
1672 | ||
dc97997a | 1673 | intel_enable_gt_powersave(dev_priv); |
b5478bcd | 1674 | |
1f814dac ID |
1675 | enable_rpm_wakeref_asserts(dev_priv); |
1676 | ||
0ab9cfeb ID |
1677 | if (ret) |
1678 | DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret); | |
1679 | else | |
1680 | DRM_DEBUG_KMS("Device resumed\n"); | |
1681 | ||
1682 | return ret; | |
8a187455 PZ |
1683 | } |
1684 | ||
b4b78d12 | 1685 | static const struct dev_pm_ops i915_pm_ops = { |
5545dbbf ID |
1686 | /* |
1687 | * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND, | |
1688 | * PMSG_RESUME] | |
1689 | */ | |
0206e353 | 1690 | .suspend = i915_pm_suspend, |
76c4b250 ID |
1691 | .suspend_late = i915_pm_suspend_late, |
1692 | .resume_early = i915_pm_resume_early, | |
0206e353 | 1693 | .resume = i915_pm_resume, |
5545dbbf ID |
1694 | |
1695 | /* | |
1696 | * S4 event handlers | |
1697 | * @freeze, @freeze_late : called (1) before creating the | |
1698 | * hibernation image [PMSG_FREEZE] and | |
1699 | * (2) after rebooting, before restoring | |
1700 | * the image [PMSG_QUIESCE] | |
1701 | * @thaw, @thaw_early : called (1) after creating the hibernation | |
1702 | * image, before writing it [PMSG_THAW] | |
1703 | * and (2) after failing to create or | |
1704 | * restore the image [PMSG_RECOVER] | |
1705 | * @poweroff, @poweroff_late: called after writing the hibernation | |
1706 | * image, before rebooting [PMSG_HIBERNATE] | |
1707 | * @restore, @restore_early : called after rebooting and restoring the | |
1708 | * hibernation image [PMSG_RESTORE] | |
1709 | */ | |
1f19ac2a CW |
1710 | .freeze = i915_pm_freeze, |
1711 | .freeze_late = i915_pm_freeze_late, | |
1712 | .thaw_early = i915_pm_thaw_early, | |
1713 | .thaw = i915_pm_thaw, | |
36d61e67 | 1714 | .poweroff = i915_pm_suspend, |
ab3be73f | 1715 | .poweroff_late = i915_pm_poweroff_late, |
1f19ac2a CW |
1716 | .restore_early = i915_pm_restore_early, |
1717 | .restore = i915_pm_restore, | |
5545dbbf ID |
1718 | |
1719 | /* S0ix (via runtime suspend) event handlers */ | |
97bea207 PZ |
1720 | .runtime_suspend = intel_runtime_suspend, |
1721 | .runtime_resume = intel_runtime_resume, | |
cbda12d7 ZW |
1722 | }; |
1723 | ||
78b68556 | 1724 | static const struct vm_operations_struct i915_gem_vm_ops = { |
de151cf6 | 1725 | .fault = i915_gem_fault, |
ab00b3e5 JB |
1726 | .open = drm_gem_vm_open, |
1727 | .close = drm_gem_vm_close, | |
de151cf6 JB |
1728 | }; |
1729 | ||
e08e96de AV |
1730 | static const struct file_operations i915_driver_fops = { |
1731 | .owner = THIS_MODULE, | |
1732 | .open = drm_open, | |
1733 | .release = drm_release, | |
1734 | .unlocked_ioctl = drm_ioctl, | |
1735 | .mmap = drm_gem_mmap, | |
1736 | .poll = drm_poll, | |
e08e96de AV |
1737 | .read = drm_read, |
1738 | #ifdef CONFIG_COMPAT | |
1739 | .compat_ioctl = i915_compat_ioctl, | |
1740 | #endif | |
1741 | .llseek = noop_llseek, | |
1742 | }; | |
1743 | ||
1da177e4 | 1744 | static struct drm_driver driver = { |
0c54781b MW |
1745 | /* Don't use MTRRs here; the Xserver or userspace app should |
1746 | * deal with them for Intel hardware. | |
792d2b9a | 1747 | */ |
673a394b | 1748 | .driver_features = |
10ba5012 | 1749 | DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME | |
1751fcf9 | 1750 | DRIVER_RENDER | DRIVER_MODESET, |
22eae947 | 1751 | .load = i915_driver_load, |
ba8bbcf6 | 1752 | .unload = i915_driver_unload, |
673a394b | 1753 | .open = i915_driver_open, |
22eae947 DA |
1754 | .lastclose = i915_driver_lastclose, |
1755 | .preclose = i915_driver_preclose, | |
673a394b | 1756 | .postclose = i915_driver_postclose, |
915b4d11 | 1757 | .set_busid = drm_pci_set_busid, |
d8e29209 | 1758 | |
673a394b | 1759 | .gem_free_object = i915_gem_free_object, |
de151cf6 | 1760 | .gem_vm_ops = &i915_gem_vm_ops, |
1286ff73 DV |
1761 | |
1762 | .prime_handle_to_fd = drm_gem_prime_handle_to_fd, | |
1763 | .prime_fd_to_handle = drm_gem_prime_fd_to_handle, | |
1764 | .gem_prime_export = i915_gem_prime_export, | |
1765 | .gem_prime_import = i915_gem_prime_import, | |
1766 | ||
ff72145b | 1767 | .dumb_create = i915_gem_dumb_create, |
da6b51d0 | 1768 | .dumb_map_offset = i915_gem_mmap_gtt, |
43387b37 | 1769 | .dumb_destroy = drm_gem_dumb_destroy, |
1da177e4 | 1770 | .ioctls = i915_ioctls, |
e08e96de | 1771 | .fops = &i915_driver_fops, |
22eae947 DA |
1772 | .name = DRIVER_NAME, |
1773 | .desc = DRIVER_DESC, | |
1774 | .date = DRIVER_DATE, | |
1775 | .major = DRIVER_MAJOR, | |
1776 | .minor = DRIVER_MINOR, | |
1777 | .patchlevel = DRIVER_PATCHLEVEL, | |
1da177e4 LT |
1778 | }; |
1779 | ||
8410ea3b DA |
1780 | static struct pci_driver i915_pci_driver = { |
1781 | .name = DRIVER_NAME, | |
1782 | .id_table = pciidlist, | |
1783 | .probe = i915_pci_probe, | |
1784 | .remove = i915_pci_remove, | |
1785 | .driver.pm = &i915_pm_ops, | |
1786 | }; | |
1787 | ||
1da177e4 LT |
1788 | static int __init i915_init(void) |
1789 | { | |
1790 | driver.num_ioctls = i915_max_ioctl; | |
79e53945 JB |
1791 | |
1792 | /* | |
fd930478 CW |
1793 | * Enable KMS by default, unless explicitly overriden by |
1794 | * either the i915.modeset prarameter or by the | |
1795 | * vga_text_mode_force boot option. | |
79e53945 | 1796 | */ |
fd930478 CW |
1797 | |
1798 | if (i915.modeset == 0) | |
1799 | driver.driver_features &= ~DRIVER_MODESET; | |
79e53945 | 1800 | |
d330a953 | 1801 | if (vgacon_text_force() && i915.modeset == -1) |
79e53945 | 1802 | driver.driver_features &= ~DRIVER_MODESET; |
79e53945 | 1803 | |
b30324ad | 1804 | if (!(driver.driver_features & DRIVER_MODESET)) { |
b30324ad | 1805 | /* Silently fail loading to not upset userspace. */ |
c9cd7b65 | 1806 | DRM_DEBUG_DRIVER("KMS and UMS disabled.\n"); |
b30324ad | 1807 | return 0; |
b30324ad | 1808 | } |
3885c6bb | 1809 | |
c5b852f3 | 1810 | if (i915.nuclear_pageflip) |
b2e7723b MR |
1811 | driver.driver_features |= DRIVER_ATOMIC; |
1812 | ||
8410ea3b | 1813 | return drm_pci_init(&driver, &i915_pci_driver); |
1da177e4 LT |
1814 | } |
1815 | ||
1816 | static void __exit i915_exit(void) | |
1817 | { | |
b33ecdd1 DV |
1818 | if (!(driver.driver_features & DRIVER_MODESET)) |
1819 | return; /* Never loaded a driver. */ | |
b33ecdd1 | 1820 | |
8410ea3b | 1821 | drm_pci_exit(&driver, &i915_pci_driver); |
1da177e4 LT |
1822 | } |
1823 | ||
1824 | module_init(i915_init); | |
1825 | module_exit(i915_exit); | |
1826 | ||
0a6d1631 | 1827 | MODULE_AUTHOR("Tungsten Graphics, Inc."); |
1eab9234 | 1828 | MODULE_AUTHOR("Intel Corporation"); |
0a6d1631 | 1829 | |
b5e89ed5 | 1830 | MODULE_DESCRIPTION(DRIVER_DESC); |
1da177e4 | 1831 | MODULE_LICENSE("GPL and additional rights"); |