Commit | Line | Data |
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1da177e4 LT |
1 | /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*- |
2 | */ | |
0d6aa60b | 3 | /* |
bc54fd1a | 4 | * |
1da177e4 LT |
5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
6 | * All Rights Reserved. | |
bc54fd1a DA |
7 | * |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the | |
10 | * "Software"), to deal in the Software without restriction, including | |
11 | * without limitation the rights to use, copy, modify, merge, publish, | |
12 | * distribute, sub license, and/or sell copies of the Software, and to | |
13 | * permit persons to whom the Software is furnished to do so, subject to | |
14 | * the following conditions: | |
15 | * | |
16 | * The above copyright notice and this permission notice (including the | |
17 | * next paragraph) shall be included in all copies or substantial portions | |
18 | * of the Software. | |
19 | * | |
20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
27 | * | |
0d6aa60b | 28 | */ |
1da177e4 | 29 | |
5669fcac | 30 | #include <linux/device.h> |
1da177e4 LT |
31 | #include "drmP.h" |
32 | #include "drm.h" | |
33 | #include "i915_drm.h" | |
34 | #include "i915_drv.h" | |
f49f0586 | 35 | #include "intel_drv.h" |
1da177e4 | 36 | |
79e53945 | 37 | #include <linux/console.h> |
354ff967 | 38 | #include "drm_crtc_helper.h" |
79e53945 | 39 | |
d6073d77 | 40 | static int i915_modeset = -1; |
79e53945 JB |
41 | module_param_named(modeset, i915_modeset, int, 0400); |
42 | ||
43 | unsigned int i915_fbpercrtc = 0; | |
44 | module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400); | |
1da177e4 | 45 | |
fca87409 CW |
46 | int i915_panel_ignore_lid = 0; |
47 | module_param_named(panel_ignore_lid, i915_panel_ignore_lid, int, 0600); | |
48 | ||
652c393a | 49 | unsigned int i915_powersave = 1; |
0aa99277 | 50 | module_param_named(powersave, i915_powersave, int, 0600); |
652c393a | 51 | |
087fbc99 | 52 | unsigned int i915_semaphores = 0; |
a1656b90 CW |
53 | module_param_named(semaphores, i915_semaphores, int, 0600); |
54 | ||
a51f7a66 | 55 | unsigned int i915_enable_rc6 = 1; |
ac668088 CW |
56 | module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0600); |
57 | ||
c1a9f047 JB |
58 | unsigned int i915_enable_fbc = 0; |
59 | module_param_named(i915_enable_fbc, i915_enable_fbc, int, 0600); | |
60 | ||
33814341 JB |
61 | unsigned int i915_lvds_downclock = 0; |
62 | module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400); | |
63 | ||
a7615030 CW |
64 | unsigned int i915_panel_use_ssc = 1; |
65 | module_param_named(lvds_use_ssc, i915_panel_use_ssc, int, 0600); | |
66 | ||
5a1e5b6c CW |
67 | int i915_vbt_sdvo_panel_type = -1; |
68 | module_param_named(vbt_sdvo_panel_type, i915_vbt_sdvo_panel_type, int, 0600); | |
69 | ||
311bd68e | 70 | static bool i915_try_reset = true; |
d78cb50b CW |
71 | module_param_named(reset, i915_try_reset, bool, 0600); |
72 | ||
112b715e | 73 | static struct drm_driver driver; |
1f7a6e37 | 74 | extern int intel_agp_enabled; |
112b715e | 75 | |
cfdf1fa2 | 76 | #define INTEL_VGA_DEVICE(id, info) { \ |
49ae35f2 | 77 | .class = PCI_CLASS_DISPLAY_VGA << 8, \ |
934f992c | 78 | .class_mask = 0xff0000, \ |
49ae35f2 KH |
79 | .vendor = 0x8086, \ |
80 | .device = id, \ | |
81 | .subvendor = PCI_ANY_ID, \ | |
82 | .subdevice = PCI_ANY_ID, \ | |
cfdf1fa2 KH |
83 | .driver_data = (unsigned long) info } |
84 | ||
9a7e8492 | 85 | static const struct intel_device_info intel_i830_info = { |
a6c45cf0 | 86 | .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, |
31578148 | 87 | .has_overlay = 1, .overlay_needs_physical = 1, |
cfdf1fa2 KH |
88 | }; |
89 | ||
9a7e8492 | 90 | static const struct intel_device_info intel_845g_info = { |
a6c45cf0 | 91 | .gen = 2, |
31578148 | 92 | .has_overlay = 1, .overlay_needs_physical = 1, |
cfdf1fa2 KH |
93 | }; |
94 | ||
9a7e8492 | 95 | static const struct intel_device_info intel_i85x_info = { |
a6c45cf0 | 96 | .gen = 2, .is_i85x = 1, .is_mobile = 1, |
5ce8ba7c | 97 | .cursor_needs_physical = 1, |
31578148 | 98 | .has_overlay = 1, .overlay_needs_physical = 1, |
cfdf1fa2 KH |
99 | }; |
100 | ||
9a7e8492 | 101 | static const struct intel_device_info intel_i865g_info = { |
a6c45cf0 | 102 | .gen = 2, |
31578148 | 103 | .has_overlay = 1, .overlay_needs_physical = 1, |
cfdf1fa2 KH |
104 | }; |
105 | ||
9a7e8492 | 106 | static const struct intel_device_info intel_i915g_info = { |
a6c45cf0 | 107 | .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, |
31578148 | 108 | .has_overlay = 1, .overlay_needs_physical = 1, |
cfdf1fa2 | 109 | }; |
9a7e8492 | 110 | static const struct intel_device_info intel_i915gm_info = { |
a6c45cf0 | 111 | .gen = 3, .is_mobile = 1, |
b295d1b6 | 112 | .cursor_needs_physical = 1, |
31578148 | 113 | .has_overlay = 1, .overlay_needs_physical = 1, |
a6c45cf0 | 114 | .supports_tv = 1, |
cfdf1fa2 | 115 | }; |
9a7e8492 | 116 | static const struct intel_device_info intel_i945g_info = { |
a6c45cf0 | 117 | .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, |
31578148 | 118 | .has_overlay = 1, .overlay_needs_physical = 1, |
cfdf1fa2 | 119 | }; |
9a7e8492 | 120 | static const struct intel_device_info intel_i945gm_info = { |
a6c45cf0 | 121 | .gen = 3, .is_i945gm = 1, .is_mobile = 1, |
b295d1b6 | 122 | .has_hotplug = 1, .cursor_needs_physical = 1, |
31578148 | 123 | .has_overlay = 1, .overlay_needs_physical = 1, |
a6c45cf0 | 124 | .supports_tv = 1, |
cfdf1fa2 KH |
125 | }; |
126 | ||
9a7e8492 | 127 | static const struct intel_device_info intel_i965g_info = { |
a6c45cf0 | 128 | .gen = 4, .is_broadwater = 1, |
c96c3a8c | 129 | .has_hotplug = 1, |
31578148 | 130 | .has_overlay = 1, |
cfdf1fa2 KH |
131 | }; |
132 | ||
9a7e8492 | 133 | static const struct intel_device_info intel_i965gm_info = { |
a6c45cf0 | 134 | .gen = 4, .is_crestline = 1, |
e3c4e5dd | 135 | .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1, |
31578148 | 136 | .has_overlay = 1, |
a6c45cf0 | 137 | .supports_tv = 1, |
cfdf1fa2 KH |
138 | }; |
139 | ||
9a7e8492 | 140 | static const struct intel_device_info intel_g33_info = { |
a6c45cf0 | 141 | .gen = 3, .is_g33 = 1, |
c96c3a8c | 142 | .need_gfx_hws = 1, .has_hotplug = 1, |
31578148 | 143 | .has_overlay = 1, |
cfdf1fa2 KH |
144 | }; |
145 | ||
9a7e8492 | 146 | static const struct intel_device_info intel_g45_info = { |
a6c45cf0 | 147 | .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, |
c96c3a8c | 148 | .has_pipe_cxsr = 1, .has_hotplug = 1, |
92f49d9c | 149 | .has_bsd_ring = 1, |
cfdf1fa2 KH |
150 | }; |
151 | ||
9a7e8492 | 152 | static const struct intel_device_info intel_gm45_info = { |
a6c45cf0 | 153 | .gen = 4, .is_g4x = 1, |
e3c4e5dd | 154 | .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1, |
c96c3a8c | 155 | .has_pipe_cxsr = 1, .has_hotplug = 1, |
a6c45cf0 | 156 | .supports_tv = 1, |
92f49d9c | 157 | .has_bsd_ring = 1, |
cfdf1fa2 KH |
158 | }; |
159 | ||
9a7e8492 | 160 | static const struct intel_device_info intel_pineview_info = { |
a6c45cf0 | 161 | .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, |
c96c3a8c | 162 | .need_gfx_hws = 1, .has_hotplug = 1, |
31578148 | 163 | .has_overlay = 1, |
cfdf1fa2 KH |
164 | }; |
165 | ||
9a7e8492 | 166 | static const struct intel_device_info intel_ironlake_d_info = { |
f00a3ddf | 167 | .gen = 5, |
c96c3a8c | 168 | .need_gfx_hws = 1, .has_pipe_cxsr = 1, .has_hotplug = 1, |
92f49d9c | 169 | .has_bsd_ring = 1, |
cfdf1fa2 KH |
170 | }; |
171 | ||
9a7e8492 | 172 | static const struct intel_device_info intel_ironlake_m_info = { |
f00a3ddf | 173 | .gen = 5, .is_mobile = 1, |
e3c4e5dd | 174 | .need_gfx_hws = 1, .has_hotplug = 1, |
c1a9f047 | 175 | .has_fbc = 1, |
92f49d9c | 176 | .has_bsd_ring = 1, |
cfdf1fa2 KH |
177 | }; |
178 | ||
9a7e8492 | 179 | static const struct intel_device_info intel_sandybridge_d_info = { |
a6c45cf0 | 180 | .gen = 6, |
c96c3a8c | 181 | .need_gfx_hws = 1, .has_hotplug = 1, |
881f47b6 | 182 | .has_bsd_ring = 1, |
549f7365 | 183 | .has_blt_ring = 1, |
f6e450a6 EA |
184 | }; |
185 | ||
9a7e8492 | 186 | static const struct intel_device_info intel_sandybridge_m_info = { |
a6c45cf0 | 187 | .gen = 6, .is_mobile = 1, |
c96c3a8c | 188 | .need_gfx_hws = 1, .has_hotplug = 1, |
9c04f015 | 189 | .has_fbc = 1, |
881f47b6 | 190 | .has_bsd_ring = 1, |
549f7365 | 191 | .has_blt_ring = 1, |
a13e4093 EA |
192 | }; |
193 | ||
c76b615c JB |
194 | static const struct intel_device_info intel_ivybridge_d_info = { |
195 | .is_ivybridge = 1, .gen = 7, | |
196 | .need_gfx_hws = 1, .has_hotplug = 1, | |
197 | .has_bsd_ring = 1, | |
198 | .has_blt_ring = 1, | |
199 | }; | |
200 | ||
201 | static const struct intel_device_info intel_ivybridge_m_info = { | |
202 | .is_ivybridge = 1, .gen = 7, .is_mobile = 1, | |
203 | .need_gfx_hws = 1, .has_hotplug = 1, | |
204 | .has_fbc = 0, /* FBC is not enabled on Ivybridge mobile yet */ | |
205 | .has_bsd_ring = 1, | |
206 | .has_blt_ring = 1, | |
207 | }; | |
208 | ||
6103da0d CW |
209 | static const struct pci_device_id pciidlist[] = { /* aka */ |
210 | INTEL_VGA_DEVICE(0x3577, &intel_i830_info), /* I830_M */ | |
211 | INTEL_VGA_DEVICE(0x2562, &intel_845g_info), /* 845_G */ | |
212 | INTEL_VGA_DEVICE(0x3582, &intel_i85x_info), /* I855_GM */ | |
5ce8ba7c | 213 | INTEL_VGA_DEVICE(0x358e, &intel_i85x_info), |
6103da0d CW |
214 | INTEL_VGA_DEVICE(0x2572, &intel_i865g_info), /* I865_G */ |
215 | INTEL_VGA_DEVICE(0x2582, &intel_i915g_info), /* I915_G */ | |
216 | INTEL_VGA_DEVICE(0x258a, &intel_i915g_info), /* E7221_G */ | |
217 | INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info), /* I915_GM */ | |
218 | INTEL_VGA_DEVICE(0x2772, &intel_i945g_info), /* I945_G */ | |
219 | INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info), /* I945_GM */ | |
220 | INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info), /* I945_GME */ | |
221 | INTEL_VGA_DEVICE(0x2972, &intel_i965g_info), /* I946_GZ */ | |
222 | INTEL_VGA_DEVICE(0x2982, &intel_i965g_info), /* G35_G */ | |
223 | INTEL_VGA_DEVICE(0x2992, &intel_i965g_info), /* I965_Q */ | |
224 | INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info), /* I965_G */ | |
225 | INTEL_VGA_DEVICE(0x29b2, &intel_g33_info), /* Q35_G */ | |
226 | INTEL_VGA_DEVICE(0x29c2, &intel_g33_info), /* G33_G */ | |
227 | INTEL_VGA_DEVICE(0x29d2, &intel_g33_info), /* Q33_G */ | |
228 | INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info), /* I965_GM */ | |
229 | INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info), /* I965_GME */ | |
230 | INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info), /* GM45_G */ | |
231 | INTEL_VGA_DEVICE(0x2e02, &intel_g45_info), /* IGD_E_G */ | |
232 | INTEL_VGA_DEVICE(0x2e12, &intel_g45_info), /* Q45_G */ | |
233 | INTEL_VGA_DEVICE(0x2e22, &intel_g45_info), /* G45_G */ | |
234 | INTEL_VGA_DEVICE(0x2e32, &intel_g45_info), /* G41_G */ | |
235 | INTEL_VGA_DEVICE(0x2e42, &intel_g45_info), /* B43_G */ | |
41a51428 | 236 | INTEL_VGA_DEVICE(0x2e92, &intel_g45_info), /* B43_G.1 */ |
cfdf1fa2 KH |
237 | INTEL_VGA_DEVICE(0xa001, &intel_pineview_info), |
238 | INTEL_VGA_DEVICE(0xa011, &intel_pineview_info), | |
239 | INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info), | |
240 | INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info), | |
f6e450a6 | 241 | INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info), |
85540480 ZW |
242 | INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info), |
243 | INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info), | |
a13e4093 | 244 | INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info), |
85540480 | 245 | INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info), |
4fefe435 | 246 | INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info), |
85540480 | 247 | INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info), |
c76b615c JB |
248 | INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info), /* GT1 mobile */ |
249 | INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info), /* GT2 mobile */ | |
250 | INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */ | |
251 | INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */ | |
252 | INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */ | |
49ae35f2 | 253 | {0, 0, 0} |
1da177e4 LT |
254 | }; |
255 | ||
79e53945 JB |
256 | #if defined(CONFIG_DRM_I915_KMS) |
257 | MODULE_DEVICE_TABLE(pci, pciidlist); | |
258 | #endif | |
259 | ||
3bad0781 | 260 | #define INTEL_PCH_DEVICE_ID_MASK 0xff00 |
90711d50 | 261 | #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00 |
3bad0781 | 262 | #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00 |
c792513b | 263 | #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00 |
3bad0781 ZW |
264 | |
265 | void intel_detect_pch (struct drm_device *dev) | |
266 | { | |
267 | struct drm_i915_private *dev_priv = dev->dev_private; | |
268 | struct pci_dev *pch; | |
269 | ||
270 | /* | |
271 | * The reason to probe ISA bridge instead of Dev31:Fun0 is to | |
272 | * make graphics device passthrough work easy for VMM, that only | |
273 | * need to expose ISA bridge to let driver know the real hardware | |
274 | * underneath. This is a requirement from virtualization team. | |
275 | */ | |
276 | pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL); | |
277 | if (pch) { | |
278 | if (pch->vendor == PCI_VENDOR_ID_INTEL) { | |
279 | int id; | |
280 | id = pch->device & INTEL_PCH_DEVICE_ID_MASK; | |
281 | ||
90711d50 JB |
282 | if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) { |
283 | dev_priv->pch_type = PCH_IBX; | |
284 | DRM_DEBUG_KMS("Found Ibex Peak PCH\n"); | |
285 | } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) { | |
3bad0781 ZW |
286 | dev_priv->pch_type = PCH_CPT; |
287 | DRM_DEBUG_KMS("Found CougarPoint PCH\n"); | |
c792513b JB |
288 | } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) { |
289 | /* PantherPoint is CPT compatible */ | |
290 | dev_priv->pch_type = PCH_CPT; | |
291 | DRM_DEBUG_KMS("Found PatherPoint PCH\n"); | |
3bad0781 ZW |
292 | } |
293 | } | |
294 | pci_dev_put(pch); | |
295 | } | |
296 | } | |
297 | ||
fcca7926 | 298 | static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv) |
eb43f4af CW |
299 | { |
300 | int count; | |
301 | ||
302 | count = 0; | |
303 | while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1)) | |
304 | udelay(10); | |
305 | ||
306 | I915_WRITE_NOTRACE(FORCEWAKE, 1); | |
307 | POSTING_READ(FORCEWAKE); | |
308 | ||
309 | count = 0; | |
310 | while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1) == 0) | |
311 | udelay(10); | |
312 | } | |
313 | ||
fcca7926 BW |
314 | /* |
315 | * Generally this is called implicitly by the register read function. However, | |
316 | * if some sequence requires the GT to not power down then this function should | |
317 | * be called at the beginning of the sequence followed by a call to | |
318 | * gen6_gt_force_wake_put() at the end of the sequence. | |
319 | */ | |
320 | void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv) | |
321 | { | |
322 | WARN_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex)); | |
323 | ||
324 | /* Forcewake is atomic in case we get in here without the lock */ | |
325 | if (atomic_add_return(1, &dev_priv->forcewake_count) == 1) | |
326 | __gen6_gt_force_wake_get(dev_priv); | |
327 | } | |
328 | ||
329 | static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv) | |
eb43f4af CW |
330 | { |
331 | I915_WRITE_NOTRACE(FORCEWAKE, 0); | |
332 | POSTING_READ(FORCEWAKE); | |
333 | } | |
334 | ||
fcca7926 BW |
335 | /* |
336 | * see gen6_gt_force_wake_get() | |
337 | */ | |
338 | void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv) | |
339 | { | |
340 | WARN_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex)); | |
341 | ||
342 | if (atomic_dec_and_test(&dev_priv->forcewake_count)) | |
343 | __gen6_gt_force_wake_put(dev_priv); | |
344 | } | |
345 | ||
91355834 CW |
346 | void __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv) |
347 | { | |
348 | int loop = 500; | |
349 | u32 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES); | |
350 | while (fifo < 20 && loop--) { | |
351 | udelay(10); | |
352 | fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES); | |
353 | } | |
354 | } | |
355 | ||
84b79f8d | 356 | static int i915_drm_freeze(struct drm_device *dev) |
ba8bbcf6 | 357 | { |
61caf87c RW |
358 | struct drm_i915_private *dev_priv = dev->dev_private; |
359 | ||
5bcf719b DA |
360 | drm_kms_helper_poll_disable(dev); |
361 | ||
ba8bbcf6 | 362 | pci_save_state(dev->pdev); |
ba8bbcf6 | 363 | |
5669fcac | 364 | /* If KMS is active, we do the leavevt stuff here */ |
226485e9 | 365 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
84b79f8d RW |
366 | int error = i915_gem_idle(dev); |
367 | if (error) { | |
226485e9 | 368 | dev_err(&dev->pdev->dev, |
84b79f8d RW |
369 | "GEM idle failed, resume might fail\n"); |
370 | return error; | |
371 | } | |
226485e9 | 372 | drm_irq_uninstall(dev); |
5669fcac JB |
373 | } |
374 | ||
9e06dd39 JB |
375 | i915_save_state(dev); |
376 | ||
44834a67 | 377 | intel_opregion_fini(dev); |
8ee1c3db | 378 | |
84b79f8d RW |
379 | /* Modeset on resume, not lid events */ |
380 | dev_priv->modeset_on_lid = 0; | |
61caf87c RW |
381 | |
382 | return 0; | |
84b79f8d RW |
383 | } |
384 | ||
6a9ee8af | 385 | int i915_suspend(struct drm_device *dev, pm_message_t state) |
84b79f8d RW |
386 | { |
387 | int error; | |
388 | ||
389 | if (!dev || !dev->dev_private) { | |
390 | DRM_ERROR("dev: %p\n", dev); | |
391 | DRM_ERROR("DRM not initialized, aborting suspend.\n"); | |
392 | return -ENODEV; | |
393 | } | |
394 | ||
395 | if (state.event == PM_EVENT_PRETHAW) | |
396 | return 0; | |
397 | ||
5bcf719b DA |
398 | |
399 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) | |
400 | return 0; | |
6eecba33 | 401 | |
84b79f8d RW |
402 | error = i915_drm_freeze(dev); |
403 | if (error) | |
404 | return error; | |
405 | ||
b932ccb5 DA |
406 | if (state.event == PM_EVENT_SUSPEND) { |
407 | /* Shut down the device */ | |
408 | pci_disable_device(dev->pdev); | |
409 | pci_set_power_state(dev->pdev, PCI_D3hot); | |
410 | } | |
ba8bbcf6 JB |
411 | |
412 | return 0; | |
413 | } | |
414 | ||
84b79f8d | 415 | static int i915_drm_thaw(struct drm_device *dev) |
ba8bbcf6 | 416 | { |
5669fcac | 417 | struct drm_i915_private *dev_priv = dev->dev_private; |
84b79f8d | 418 | int error = 0; |
8ee1c3db | 419 | |
d1c3b177 CW |
420 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
421 | mutex_lock(&dev->struct_mutex); | |
422 | i915_gem_restore_gtt_mappings(dev); | |
423 | mutex_unlock(&dev->struct_mutex); | |
424 | } | |
425 | ||
61caf87c | 426 | i915_restore_state(dev); |
44834a67 | 427 | intel_opregion_setup(dev); |
61caf87c | 428 | |
5669fcac JB |
429 | /* KMS EnterVT equivalent */ |
430 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { | |
431 | mutex_lock(&dev->struct_mutex); | |
432 | dev_priv->mm.suspended = 0; | |
433 | ||
84b79f8d | 434 | error = i915_gem_init_ringbuffer(dev); |
5669fcac | 435 | mutex_unlock(&dev->struct_mutex); |
226485e9 | 436 | |
500f7147 | 437 | drm_mode_config_reset(dev); |
226485e9 | 438 | drm_irq_install(dev); |
84b79f8d | 439 | |
354ff967 ZY |
440 | /* Resume the modeset for every activated CRTC */ |
441 | drm_helper_resume_force_mode(dev); | |
5669fcac | 442 | |
ac668088 | 443 | if (IS_IRONLAKE_M(dev)) |
d5bb081b JB |
444 | ironlake_enable_rc6(dev); |
445 | } | |
1daed3fb | 446 | |
44834a67 CW |
447 | intel_opregion_init(dev); |
448 | ||
c9354c85 | 449 | dev_priv->modeset_on_lid = 0; |
06891e27 | 450 | |
84b79f8d RW |
451 | return error; |
452 | } | |
453 | ||
6a9ee8af | 454 | int i915_resume(struct drm_device *dev) |
84b79f8d | 455 | { |
6eecba33 CW |
456 | int ret; |
457 | ||
5bcf719b DA |
458 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
459 | return 0; | |
460 | ||
84b79f8d RW |
461 | if (pci_enable_device(dev->pdev)) |
462 | return -EIO; | |
463 | ||
464 | pci_set_master(dev->pdev); | |
465 | ||
6eecba33 CW |
466 | ret = i915_drm_thaw(dev); |
467 | if (ret) | |
468 | return ret; | |
469 | ||
470 | drm_kms_helper_poll_enable(dev); | |
471 | return 0; | |
ba8bbcf6 JB |
472 | } |
473 | ||
dc96e9b8 CW |
474 | static int i8xx_do_reset(struct drm_device *dev, u8 flags) |
475 | { | |
476 | struct drm_i915_private *dev_priv = dev->dev_private; | |
477 | ||
478 | if (IS_I85X(dev)) | |
479 | return -ENODEV; | |
480 | ||
481 | I915_WRITE(D_STATE, I915_READ(D_STATE) | DSTATE_GFX_RESET_I830); | |
482 | POSTING_READ(D_STATE); | |
483 | ||
484 | if (IS_I830(dev) || IS_845G(dev)) { | |
485 | I915_WRITE(DEBUG_RESET_I830, | |
486 | DEBUG_RESET_DISPLAY | | |
487 | DEBUG_RESET_RENDER | | |
488 | DEBUG_RESET_FULL); | |
489 | POSTING_READ(DEBUG_RESET_I830); | |
490 | msleep(1); | |
491 | ||
492 | I915_WRITE(DEBUG_RESET_I830, 0); | |
493 | POSTING_READ(DEBUG_RESET_I830); | |
494 | } | |
495 | ||
496 | msleep(1); | |
497 | ||
498 | I915_WRITE(D_STATE, I915_READ(D_STATE) & ~DSTATE_GFX_RESET_I830); | |
499 | POSTING_READ(D_STATE); | |
500 | ||
501 | return 0; | |
502 | } | |
503 | ||
f49f0586 KG |
504 | static int i965_reset_complete(struct drm_device *dev) |
505 | { | |
506 | u8 gdrst; | |
eeccdcac | 507 | pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst); |
f49f0586 KG |
508 | return gdrst & 0x1; |
509 | } | |
510 | ||
0573ed4a KG |
511 | static int i965_do_reset(struct drm_device *dev, u8 flags) |
512 | { | |
513 | u8 gdrst; | |
514 | ||
ae681d96 CW |
515 | /* |
516 | * Set the domains we want to reset (GRDOM/bits 2 and 3) as | |
517 | * well as the reset bit (GR/bit 0). Setting the GR bit | |
518 | * triggers the reset; when done, the hardware will clear it. | |
519 | */ | |
0573ed4a KG |
520 | pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst); |
521 | pci_write_config_byte(dev->pdev, I965_GDRST, gdrst | flags | 0x1); | |
522 | ||
523 | return wait_for(i965_reset_complete(dev), 500); | |
524 | } | |
525 | ||
526 | static int ironlake_do_reset(struct drm_device *dev, u8 flags) | |
527 | { | |
528 | struct drm_i915_private *dev_priv = dev->dev_private; | |
529 | u32 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR); | |
530 | I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, gdrst | flags | 0x1); | |
531 | return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500); | |
ba8bbcf6 JB |
532 | } |
533 | ||
cff458c2 EA |
534 | static int gen6_do_reset(struct drm_device *dev, u8 flags) |
535 | { | |
536 | struct drm_i915_private *dev_priv = dev->dev_private; | |
537 | ||
538 | I915_WRITE(GEN6_GDRST, GEN6_GRDOM_FULL); | |
539 | return wait_for((I915_READ(GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500); | |
540 | } | |
541 | ||
11ed50ec BG |
542 | /** |
543 | * i965_reset - reset chip after a hang | |
544 | * @dev: drm device to reset | |
545 | * @flags: reset domains | |
546 | * | |
547 | * Reset the chip. Useful if a hang is detected. Returns zero on successful | |
548 | * reset or otherwise an error code. | |
549 | * | |
550 | * Procedure is fairly simple: | |
551 | * - reset the chip using the reset reg | |
552 | * - re-init context state | |
553 | * - re-init hardware status page | |
554 | * - re-init ring buffer | |
555 | * - re-init interrupt state | |
556 | * - re-init display | |
557 | */ | |
f803aa55 | 558 | int i915_reset(struct drm_device *dev, u8 flags) |
11ed50ec BG |
559 | { |
560 | drm_i915_private_t *dev_priv = dev->dev_private; | |
11ed50ec BG |
561 | /* |
562 | * We really should only reset the display subsystem if we actually | |
563 | * need to | |
564 | */ | |
565 | bool need_display = true; | |
0573ed4a | 566 | int ret; |
11ed50ec | 567 | |
d78cb50b CW |
568 | if (!i915_try_reset) |
569 | return 0; | |
570 | ||
340479aa CW |
571 | if (!mutex_trylock(&dev->struct_mutex)) |
572 | return -EBUSY; | |
11ed50ec | 573 | |
069efc1d | 574 | i915_gem_reset(dev); |
77f01230 | 575 | |
f803aa55 | 576 | ret = -ENODEV; |
ae681d96 CW |
577 | if (get_seconds() - dev_priv->last_gpu_reset < 5) { |
578 | DRM_ERROR("GPU hanging too fast, declaring wedged!\n"); | |
579 | } else switch (INTEL_INFO(dev)->gen) { | |
cff458c2 EA |
580 | case 6: |
581 | ret = gen6_do_reset(dev, flags); | |
25732821 BW |
582 | /* If reset with a user forcewake, try to restore */ |
583 | if (atomic_read(&dev_priv->forcewake_count)) | |
584 | __gen6_gt_force_wake_get(dev_priv); | |
cff458c2 | 585 | break; |
f803aa55 | 586 | case 5: |
0573ed4a | 587 | ret = ironlake_do_reset(dev, flags); |
f803aa55 CW |
588 | break; |
589 | case 4: | |
0573ed4a | 590 | ret = i965_do_reset(dev, flags); |
f803aa55 | 591 | break; |
dc96e9b8 CW |
592 | case 2: |
593 | ret = i8xx_do_reset(dev, flags); | |
594 | break; | |
f803aa55 | 595 | } |
ae681d96 | 596 | dev_priv->last_gpu_reset = get_seconds(); |
0573ed4a | 597 | if (ret) { |
f803aa55 | 598 | DRM_ERROR("Failed to reset chip.\n"); |
f953c935 | 599 | mutex_unlock(&dev->struct_mutex); |
f803aa55 | 600 | return ret; |
11ed50ec BG |
601 | } |
602 | ||
603 | /* Ok, now get things going again... */ | |
604 | ||
605 | /* | |
606 | * Everything depends on having the GTT running, so we need to start | |
607 | * there. Fortunately we don't need to do this unless we reset the | |
608 | * chip at a PCI level. | |
609 | * | |
610 | * Next we need to restore the context, but we don't use those | |
611 | * yet either... | |
612 | * | |
613 | * Ring buffer needs to be re-initialized in the KMS case, or if X | |
614 | * was running at the time of the reset (i.e. we weren't VT | |
615 | * switched away). | |
616 | */ | |
617 | if (drm_core_check_feature(dev, DRIVER_MODESET) || | |
8187a2b7 | 618 | !dev_priv->mm.suspended) { |
11ed50ec | 619 | dev_priv->mm.suspended = 0; |
75a6898f | 620 | |
1ec14ad3 | 621 | dev_priv->ring[RCS].init(&dev_priv->ring[RCS]); |
75a6898f | 622 | if (HAS_BSD(dev)) |
1ec14ad3 | 623 | dev_priv->ring[VCS].init(&dev_priv->ring[VCS]); |
75a6898f | 624 | if (HAS_BLT(dev)) |
1ec14ad3 | 625 | dev_priv->ring[BCS].init(&dev_priv->ring[BCS]); |
75a6898f | 626 | |
11ed50ec BG |
627 | mutex_unlock(&dev->struct_mutex); |
628 | drm_irq_uninstall(dev); | |
500f7147 | 629 | drm_mode_config_reset(dev); |
11ed50ec BG |
630 | drm_irq_install(dev); |
631 | mutex_lock(&dev->struct_mutex); | |
632 | } | |
633 | ||
9fd98141 CW |
634 | mutex_unlock(&dev->struct_mutex); |
635 | ||
11ed50ec | 636 | /* |
9fd98141 CW |
637 | * Perform a full modeset as on later generations, e.g. Ironlake, we may |
638 | * need to retrain the display link and cannot just restore the register | |
639 | * values. | |
11ed50ec | 640 | */ |
9fd98141 CW |
641 | if (need_display) { |
642 | mutex_lock(&dev->mode_config.mutex); | |
643 | drm_helper_resume_force_mode(dev); | |
644 | mutex_unlock(&dev->mode_config.mutex); | |
645 | } | |
11ed50ec | 646 | |
11ed50ec BG |
647 | return 0; |
648 | } | |
649 | ||
650 | ||
112b715e KH |
651 | static int __devinit |
652 | i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) | |
653 | { | |
5fe49d86 CW |
654 | /* Only bind to function 0 of the device. Early generations |
655 | * used function 1 as a placeholder for multi-head. This causes | |
656 | * us confusion instead, especially on the systems where both | |
657 | * functions have the same PCI-ID! | |
658 | */ | |
659 | if (PCI_FUNC(pdev->devfn)) | |
660 | return -ENODEV; | |
661 | ||
dcdb1674 | 662 | return drm_get_pci_dev(pdev, ent, &driver); |
112b715e KH |
663 | } |
664 | ||
665 | static void | |
666 | i915_pci_remove(struct pci_dev *pdev) | |
667 | { | |
668 | struct drm_device *dev = pci_get_drvdata(pdev); | |
669 | ||
670 | drm_put_dev(dev); | |
671 | } | |
672 | ||
84b79f8d | 673 | static int i915_pm_suspend(struct device *dev) |
112b715e | 674 | { |
84b79f8d RW |
675 | struct pci_dev *pdev = to_pci_dev(dev); |
676 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
677 | int error; | |
112b715e | 678 | |
84b79f8d RW |
679 | if (!drm_dev || !drm_dev->dev_private) { |
680 | dev_err(dev, "DRM not initialized, aborting suspend.\n"); | |
681 | return -ENODEV; | |
682 | } | |
112b715e | 683 | |
5bcf719b DA |
684 | if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
685 | return 0; | |
686 | ||
84b79f8d RW |
687 | error = i915_drm_freeze(drm_dev); |
688 | if (error) | |
689 | return error; | |
112b715e | 690 | |
84b79f8d RW |
691 | pci_disable_device(pdev); |
692 | pci_set_power_state(pdev, PCI_D3hot); | |
cbda12d7 | 693 | |
84b79f8d | 694 | return 0; |
cbda12d7 ZW |
695 | } |
696 | ||
84b79f8d | 697 | static int i915_pm_resume(struct device *dev) |
cbda12d7 | 698 | { |
84b79f8d RW |
699 | struct pci_dev *pdev = to_pci_dev(dev); |
700 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
701 | ||
702 | return i915_resume(drm_dev); | |
cbda12d7 ZW |
703 | } |
704 | ||
84b79f8d | 705 | static int i915_pm_freeze(struct device *dev) |
cbda12d7 | 706 | { |
84b79f8d RW |
707 | struct pci_dev *pdev = to_pci_dev(dev); |
708 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
709 | ||
710 | if (!drm_dev || !drm_dev->dev_private) { | |
711 | dev_err(dev, "DRM not initialized, aborting suspend.\n"); | |
712 | return -ENODEV; | |
713 | } | |
714 | ||
715 | return i915_drm_freeze(drm_dev); | |
cbda12d7 ZW |
716 | } |
717 | ||
84b79f8d | 718 | static int i915_pm_thaw(struct device *dev) |
cbda12d7 | 719 | { |
84b79f8d RW |
720 | struct pci_dev *pdev = to_pci_dev(dev); |
721 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
722 | ||
723 | return i915_drm_thaw(drm_dev); | |
cbda12d7 ZW |
724 | } |
725 | ||
84b79f8d | 726 | static int i915_pm_poweroff(struct device *dev) |
cbda12d7 | 727 | { |
84b79f8d RW |
728 | struct pci_dev *pdev = to_pci_dev(dev); |
729 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
84b79f8d | 730 | |
61caf87c | 731 | return i915_drm_freeze(drm_dev); |
cbda12d7 ZW |
732 | } |
733 | ||
b4b78d12 | 734 | static const struct dev_pm_ops i915_pm_ops = { |
cbda12d7 ZW |
735 | .suspend = i915_pm_suspend, |
736 | .resume = i915_pm_resume, | |
737 | .freeze = i915_pm_freeze, | |
738 | .thaw = i915_pm_thaw, | |
739 | .poweroff = i915_pm_poweroff, | |
84b79f8d | 740 | .restore = i915_pm_resume, |
cbda12d7 ZW |
741 | }; |
742 | ||
de151cf6 JB |
743 | static struct vm_operations_struct i915_gem_vm_ops = { |
744 | .fault = i915_gem_fault, | |
ab00b3e5 JB |
745 | .open = drm_gem_vm_open, |
746 | .close = drm_gem_vm_close, | |
de151cf6 JB |
747 | }; |
748 | ||
1da177e4 | 749 | static struct drm_driver driver = { |
792d2b9a DA |
750 | /* don't use mtrr's here, the Xserver or user space app should |
751 | * deal with them for intel hardware. | |
752 | */ | |
673a394b EA |
753 | .driver_features = |
754 | DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR |*/ | |
755 | DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM, | |
22eae947 | 756 | .load = i915_driver_load, |
ba8bbcf6 | 757 | .unload = i915_driver_unload, |
673a394b | 758 | .open = i915_driver_open, |
22eae947 DA |
759 | .lastclose = i915_driver_lastclose, |
760 | .preclose = i915_driver_preclose, | |
673a394b | 761 | .postclose = i915_driver_postclose, |
d8e29209 RW |
762 | |
763 | /* Used in place of i915_pm_ops for non-DRIVER_MODESET */ | |
764 | .suspend = i915_suspend, | |
765 | .resume = i915_resume, | |
766 | ||
cda17380 | 767 | .device_is_agp = i915_driver_device_is_agp, |
0a3e67a4 JB |
768 | .enable_vblank = i915_enable_vblank, |
769 | .disable_vblank = i915_disable_vblank, | |
0af7e4df MK |
770 | .get_vblank_timestamp = i915_get_vblank_timestamp, |
771 | .get_scanout_position = i915_get_crtc_scanoutpos, | |
1da177e4 LT |
772 | .irq_preinstall = i915_driver_irq_preinstall, |
773 | .irq_postinstall = i915_driver_irq_postinstall, | |
774 | .irq_uninstall = i915_driver_irq_uninstall, | |
775 | .irq_handler = i915_driver_irq_handler, | |
776 | .reclaim_buffers = drm_core_reclaim_buffers, | |
7c1c2871 DA |
777 | .master_create = i915_master_create, |
778 | .master_destroy = i915_master_destroy, | |
955b12de | 779 | #if defined(CONFIG_DEBUG_FS) |
27c202ad BG |
780 | .debugfs_init = i915_debugfs_init, |
781 | .debugfs_cleanup = i915_debugfs_cleanup, | |
955b12de | 782 | #endif |
673a394b EA |
783 | .gem_init_object = i915_gem_init_object, |
784 | .gem_free_object = i915_gem_free_object, | |
de151cf6 | 785 | .gem_vm_ops = &i915_gem_vm_ops, |
ff72145b DA |
786 | .dumb_create = i915_gem_dumb_create, |
787 | .dumb_map_offset = i915_gem_mmap_gtt, | |
788 | .dumb_destroy = i915_gem_dumb_destroy, | |
1da177e4 LT |
789 | .ioctls = i915_ioctls, |
790 | .fops = { | |
b5e89ed5 DA |
791 | .owner = THIS_MODULE, |
792 | .open = drm_open, | |
793 | .release = drm_release, | |
ed8b6704 | 794 | .unlocked_ioctl = drm_ioctl, |
de151cf6 | 795 | .mmap = drm_gem_mmap, |
b5e89ed5 DA |
796 | .poll = drm_poll, |
797 | .fasync = drm_fasync, | |
c9a9c5e0 | 798 | .read = drm_read, |
8ca7c1df | 799 | #ifdef CONFIG_COMPAT |
b5e89ed5 | 800 | .compat_ioctl = i915_compat_ioctl, |
8ca7c1df | 801 | #endif |
dc880abe | 802 | .llseek = noop_llseek, |
22eae947 DA |
803 | }, |
804 | ||
22eae947 DA |
805 | .name = DRIVER_NAME, |
806 | .desc = DRIVER_DESC, | |
807 | .date = DRIVER_DATE, | |
808 | .major = DRIVER_MAJOR, | |
809 | .minor = DRIVER_MINOR, | |
810 | .patchlevel = DRIVER_PATCHLEVEL, | |
1da177e4 LT |
811 | }; |
812 | ||
8410ea3b DA |
813 | static struct pci_driver i915_pci_driver = { |
814 | .name = DRIVER_NAME, | |
815 | .id_table = pciidlist, | |
816 | .probe = i915_pci_probe, | |
817 | .remove = i915_pci_remove, | |
818 | .driver.pm = &i915_pm_ops, | |
819 | }; | |
820 | ||
1da177e4 LT |
821 | static int __init i915_init(void) |
822 | { | |
1f7a6e37 ZW |
823 | if (!intel_agp_enabled) { |
824 | DRM_ERROR("drm/i915 can't work without intel_agp module!\n"); | |
825 | return -ENODEV; | |
826 | } | |
827 | ||
1da177e4 | 828 | driver.num_ioctls = i915_max_ioctl; |
79e53945 JB |
829 | |
830 | /* | |
831 | * If CONFIG_DRM_I915_KMS is set, default to KMS unless | |
832 | * explicitly disabled with the module pararmeter. | |
833 | * | |
834 | * Otherwise, just follow the parameter (defaulting to off). | |
835 | * | |
836 | * Allow optional vga_text_mode_force boot option to override | |
837 | * the default behavior. | |
838 | */ | |
839 | #if defined(CONFIG_DRM_I915_KMS) | |
840 | if (i915_modeset != 0) | |
841 | driver.driver_features |= DRIVER_MODESET; | |
842 | #endif | |
843 | if (i915_modeset == 1) | |
844 | driver.driver_features |= DRIVER_MODESET; | |
845 | ||
846 | #ifdef CONFIG_VGA_CONSOLE | |
847 | if (vgacon_text_force() && i915_modeset == -1) | |
848 | driver.driver_features &= ~DRIVER_MODESET; | |
849 | #endif | |
850 | ||
3885c6bb CW |
851 | if (!(driver.driver_features & DRIVER_MODESET)) |
852 | driver.get_vblank_timestamp = NULL; | |
853 | ||
8410ea3b | 854 | return drm_pci_init(&driver, &i915_pci_driver); |
1da177e4 LT |
855 | } |
856 | ||
857 | static void __exit i915_exit(void) | |
858 | { | |
8410ea3b | 859 | drm_pci_exit(&driver, &i915_pci_driver); |
1da177e4 LT |
860 | } |
861 | ||
862 | module_init(i915_init); | |
863 | module_exit(i915_exit); | |
864 | ||
b5e89ed5 DA |
865 | MODULE_AUTHOR(DRIVER_AUTHOR); |
866 | MODULE_DESCRIPTION(DRIVER_DESC); | |
1da177e4 | 867 | MODULE_LICENSE("GPL and additional rights"); |