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1da177e4 LT |
1 | /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*- |
2 | */ | |
0d6aa60b | 3 | /* |
bc54fd1a | 4 | * |
1da177e4 LT |
5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
6 | * All Rights Reserved. | |
bc54fd1a DA |
7 | * |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the | |
10 | * "Software"), to deal in the Software without restriction, including | |
11 | * without limitation the rights to use, copy, modify, merge, publish, | |
12 | * distribute, sub license, and/or sell copies of the Software, and to | |
13 | * permit persons to whom the Software is furnished to do so, subject to | |
14 | * the following conditions: | |
15 | * | |
16 | * The above copyright notice and this permission notice (including the | |
17 | * next paragraph) shall be included in all copies or substantial portions | |
18 | * of the Software. | |
19 | * | |
20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
27 | * | |
0d6aa60b | 28 | */ |
1da177e4 | 29 | |
5669fcac | 30 | #include <linux/device.h> |
1da177e4 LT |
31 | #include "drmP.h" |
32 | #include "drm.h" | |
33 | #include "i915_drm.h" | |
34 | #include "i915_drv.h" | |
35 | ||
79e53945 | 36 | #include <linux/console.h> |
354ff967 | 37 | #include "drm_crtc_helper.h" |
79e53945 | 38 | |
d6073d77 | 39 | static int i915_modeset = -1; |
79e53945 JB |
40 | module_param_named(modeset, i915_modeset, int, 0400); |
41 | ||
42 | unsigned int i915_fbpercrtc = 0; | |
43 | module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400); | |
1da177e4 | 44 | |
652c393a JB |
45 | unsigned int i915_powersave = 1; |
46 | module_param_named(powersave, i915_powersave, int, 0400); | |
47 | ||
33814341 JB |
48 | unsigned int i915_lvds_downclock = 0; |
49 | module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400); | |
50 | ||
112b715e | 51 | static struct drm_driver driver; |
1f7a6e37 | 52 | extern int intel_agp_enabled; |
112b715e | 53 | |
cfdf1fa2 | 54 | #define INTEL_VGA_DEVICE(id, info) { \ |
49ae35f2 KH |
55 | .class = PCI_CLASS_DISPLAY_VGA << 8, \ |
56 | .class_mask = 0xffff00, \ | |
57 | .vendor = 0x8086, \ | |
58 | .device = id, \ | |
59 | .subvendor = PCI_ANY_ID, \ | |
60 | .subdevice = PCI_ANY_ID, \ | |
cfdf1fa2 KH |
61 | .driver_data = (unsigned long) info } |
62 | ||
9a7e8492 | 63 | static const struct intel_device_info intel_i830_info = { |
b295d1b6 | 64 | .is_i8xx = 1, .is_mobile = 1, .cursor_needs_physical = 1, |
cfdf1fa2 KH |
65 | }; |
66 | ||
9a7e8492 | 67 | static const struct intel_device_info intel_845g_info = { |
cfdf1fa2 KH |
68 | .is_i8xx = 1, |
69 | }; | |
70 | ||
9a7e8492 | 71 | static const struct intel_device_info intel_i85x_info = { |
5ce8ba7c AJ |
72 | .is_i8xx = 1, .is_i85x = 1, .is_mobile = 1, |
73 | .cursor_needs_physical = 1, | |
cfdf1fa2 KH |
74 | }; |
75 | ||
9a7e8492 | 76 | static const struct intel_device_info intel_i865g_info = { |
cfdf1fa2 KH |
77 | .is_i8xx = 1, |
78 | }; | |
79 | ||
9a7e8492 | 80 | static const struct intel_device_info intel_i915g_info = { |
b295d1b6 | 81 | .is_i915g = 1, .is_i9xx = 1, .cursor_needs_physical = 1, |
cfdf1fa2 | 82 | }; |
9a7e8492 | 83 | static const struct intel_device_info intel_i915gm_info = { |
8d06a1e1 | 84 | .is_i9xx = 1, .is_mobile = 1, |
b295d1b6 | 85 | .cursor_needs_physical = 1, |
cfdf1fa2 | 86 | }; |
9a7e8492 | 87 | static const struct intel_device_info intel_i945g_info = { |
b295d1b6 | 88 | .is_i9xx = 1, .has_hotplug = 1, .cursor_needs_physical = 1, |
cfdf1fa2 | 89 | }; |
9a7e8492 | 90 | static const struct intel_device_info intel_i945gm_info = { |
8d06a1e1 | 91 | .is_i945gm = 1, .is_i9xx = 1, .is_mobile = 1, |
b295d1b6 | 92 | .has_hotplug = 1, .cursor_needs_physical = 1, |
cfdf1fa2 KH |
93 | }; |
94 | ||
9a7e8492 | 95 | static const struct intel_device_info intel_i965g_info = { |
cfdf1fa2 KH |
96 | .is_i965g = 1, .is_i9xx = 1, .has_hotplug = 1, |
97 | }; | |
98 | ||
9a7e8492 | 99 | static const struct intel_device_info intel_i965gm_info = { |
2d3fa0de | 100 | .is_i965g = 1, .is_i965gm = 1, .is_i9xx = 1, |
cfdf1fa2 KH |
101 | .is_mobile = 1, .has_fbc = 1, .has_rc6 = 1, |
102 | .has_hotplug = 1, | |
103 | }; | |
104 | ||
9a7e8492 | 105 | static const struct intel_device_info intel_g33_info = { |
cfdf1fa2 KH |
106 | .is_g33 = 1, .is_i9xx = 1, .need_gfx_hws = 1, |
107 | .has_hotplug = 1, | |
108 | }; | |
109 | ||
9a7e8492 | 110 | static const struct intel_device_info intel_g45_info = { |
cfdf1fa2 KH |
111 | .is_i965g = 1, .is_g4x = 1, .is_i9xx = 1, .need_gfx_hws = 1, |
112 | .has_pipe_cxsr = 1, | |
113 | .has_hotplug = 1, | |
114 | }; | |
115 | ||
9a7e8492 | 116 | static const struct intel_device_info intel_gm45_info = { |
2d3fa0de | 117 | .is_i965g = 1, .is_g4x = 1, .is_i9xx = 1, |
cfdf1fa2 KH |
118 | .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1, .has_rc6 = 1, |
119 | .has_pipe_cxsr = 1, | |
120 | .has_hotplug = 1, | |
121 | }; | |
122 | ||
9a7e8492 | 123 | static const struct intel_device_info intel_pineview_info = { |
cfdf1fa2 | 124 | .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .is_i9xx = 1, |
8a6c77d6 | 125 | .need_gfx_hws = 1, |
cfdf1fa2 KH |
126 | .has_hotplug = 1, |
127 | }; | |
128 | ||
9a7e8492 | 129 | static const struct intel_device_info intel_ironlake_d_info = { |
cfdf1fa2 KH |
130 | .is_ironlake = 1, .is_i965g = 1, .is_i9xx = 1, .need_gfx_hws = 1, |
131 | .has_pipe_cxsr = 1, | |
132 | .has_hotplug = 1, | |
133 | }; | |
134 | ||
9a7e8492 | 135 | static const struct intel_device_info intel_ironlake_m_info = { |
cfdf1fa2 | 136 | .is_ironlake = 1, .is_mobile = 1, .is_i965g = 1, .is_i9xx = 1, |
b52eb4dc | 137 | .need_gfx_hws = 1, .has_fbc = 1, .has_rc6 = 1, |
cfdf1fa2 KH |
138 | .has_hotplug = 1, |
139 | }; | |
140 | ||
9a7e8492 | 141 | static const struct intel_device_info intel_sandybridge_d_info = { |
f6e450a6 | 142 | .is_i965g = 1, .is_i9xx = 1, .need_gfx_hws = 1, |
59f2d0fc | 143 | .has_hotplug = 1, .is_gen6 = 1, |
f6e450a6 EA |
144 | }; |
145 | ||
9a7e8492 | 146 | static const struct intel_device_info intel_sandybridge_m_info = { |
faa7bde6 | 147 | .is_i965g = 1, .is_mobile = 1, .is_i9xx = 1, .need_gfx_hws = 1, |
59f2d0fc | 148 | .has_hotplug = 1, .is_gen6 = 1, |
a13e4093 EA |
149 | }; |
150 | ||
9a7e8492 | 151 | static const struct pci_device_id pciidlist[] = { |
cfdf1fa2 KH |
152 | INTEL_VGA_DEVICE(0x3577, &intel_i830_info), |
153 | INTEL_VGA_DEVICE(0x2562, &intel_845g_info), | |
154 | INTEL_VGA_DEVICE(0x3582, &intel_i85x_info), | |
5ce8ba7c | 155 | INTEL_VGA_DEVICE(0x358e, &intel_i85x_info), |
cfdf1fa2 KH |
156 | INTEL_VGA_DEVICE(0x2572, &intel_i865g_info), |
157 | INTEL_VGA_DEVICE(0x2582, &intel_i915g_info), | |
158 | INTEL_VGA_DEVICE(0x258a, &intel_i915g_info), | |
159 | INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info), | |
160 | INTEL_VGA_DEVICE(0x2772, &intel_i945g_info), | |
161 | INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info), | |
162 | INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info), | |
163 | INTEL_VGA_DEVICE(0x2972, &intel_i965g_info), | |
164 | INTEL_VGA_DEVICE(0x2982, &intel_i965g_info), | |
165 | INTEL_VGA_DEVICE(0x2992, &intel_i965g_info), | |
166 | INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info), | |
167 | INTEL_VGA_DEVICE(0x29b2, &intel_g33_info), | |
168 | INTEL_VGA_DEVICE(0x29c2, &intel_g33_info), | |
169 | INTEL_VGA_DEVICE(0x29d2, &intel_g33_info), | |
170 | INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info), | |
171 | INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info), | |
172 | INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info), | |
173 | INTEL_VGA_DEVICE(0x2e02, &intel_g45_info), | |
174 | INTEL_VGA_DEVICE(0x2e12, &intel_g45_info), | |
175 | INTEL_VGA_DEVICE(0x2e22, &intel_g45_info), | |
176 | INTEL_VGA_DEVICE(0x2e32, &intel_g45_info), | |
177 | INTEL_VGA_DEVICE(0x2e42, &intel_g45_info), | |
178 | INTEL_VGA_DEVICE(0xa001, &intel_pineview_info), | |
179 | INTEL_VGA_DEVICE(0xa011, &intel_pineview_info), | |
180 | INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info), | |
181 | INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info), | |
f6e450a6 | 182 | INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info), |
a13e4093 | 183 | INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info), |
49ae35f2 | 184 | {0, 0, 0} |
1da177e4 LT |
185 | }; |
186 | ||
79e53945 JB |
187 | #if defined(CONFIG_DRM_I915_KMS) |
188 | MODULE_DEVICE_TABLE(pci, pciidlist); | |
189 | #endif | |
190 | ||
3bad0781 ZW |
191 | #define INTEL_PCH_DEVICE_ID_MASK 0xff00 |
192 | #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00 | |
193 | ||
194 | void intel_detect_pch (struct drm_device *dev) | |
195 | { | |
196 | struct drm_i915_private *dev_priv = dev->dev_private; | |
197 | struct pci_dev *pch; | |
198 | ||
199 | /* | |
200 | * The reason to probe ISA bridge instead of Dev31:Fun0 is to | |
201 | * make graphics device passthrough work easy for VMM, that only | |
202 | * need to expose ISA bridge to let driver know the real hardware | |
203 | * underneath. This is a requirement from virtualization team. | |
204 | */ | |
205 | pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL); | |
206 | if (pch) { | |
207 | if (pch->vendor == PCI_VENDOR_ID_INTEL) { | |
208 | int id; | |
209 | id = pch->device & INTEL_PCH_DEVICE_ID_MASK; | |
210 | ||
211 | if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) { | |
212 | dev_priv->pch_type = PCH_CPT; | |
213 | DRM_DEBUG_KMS("Found CougarPoint PCH\n"); | |
214 | } | |
215 | } | |
216 | pci_dev_put(pch); | |
217 | } | |
218 | } | |
219 | ||
84b79f8d | 220 | static int i915_drm_freeze(struct drm_device *dev) |
ba8bbcf6 | 221 | { |
61caf87c RW |
222 | struct drm_i915_private *dev_priv = dev->dev_private; |
223 | ||
ba8bbcf6 | 224 | pci_save_state(dev->pdev); |
ba8bbcf6 | 225 | |
5669fcac | 226 | /* If KMS is active, we do the leavevt stuff here */ |
226485e9 | 227 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
84b79f8d RW |
228 | int error = i915_gem_idle(dev); |
229 | if (error) { | |
226485e9 | 230 | dev_err(&dev->pdev->dev, |
84b79f8d RW |
231 | "GEM idle failed, resume might fail\n"); |
232 | return error; | |
233 | } | |
226485e9 | 234 | drm_irq_uninstall(dev); |
5669fcac JB |
235 | } |
236 | ||
9e06dd39 JB |
237 | i915_save_state(dev); |
238 | ||
3b1c1c11 | 239 | intel_opregion_free(dev, 1); |
8ee1c3db | 240 | |
84b79f8d RW |
241 | /* Modeset on resume, not lid events */ |
242 | dev_priv->modeset_on_lid = 0; | |
61caf87c RW |
243 | |
244 | return 0; | |
84b79f8d RW |
245 | } |
246 | ||
6a9ee8af | 247 | int i915_suspend(struct drm_device *dev, pm_message_t state) |
84b79f8d RW |
248 | { |
249 | int error; | |
250 | ||
251 | if (!dev || !dev->dev_private) { | |
252 | DRM_ERROR("dev: %p\n", dev); | |
253 | DRM_ERROR("DRM not initialized, aborting suspend.\n"); | |
254 | return -ENODEV; | |
255 | } | |
256 | ||
257 | if (state.event == PM_EVENT_PRETHAW) | |
258 | return 0; | |
259 | ||
260 | error = i915_drm_freeze(dev); | |
261 | if (error) | |
262 | return error; | |
263 | ||
b932ccb5 DA |
264 | if (state.event == PM_EVENT_SUSPEND) { |
265 | /* Shut down the device */ | |
266 | pci_disable_device(dev->pdev); | |
267 | pci_set_power_state(dev->pdev, PCI_D3hot); | |
268 | } | |
ba8bbcf6 JB |
269 | |
270 | return 0; | |
271 | } | |
272 | ||
84b79f8d | 273 | static int i915_drm_thaw(struct drm_device *dev) |
ba8bbcf6 | 274 | { |
5669fcac | 275 | struct drm_i915_private *dev_priv = dev->dev_private; |
84b79f8d | 276 | int error = 0; |
8ee1c3db | 277 | |
61caf87c RW |
278 | i915_restore_state(dev); |
279 | ||
280 | intel_opregion_init(dev, 1); | |
281 | ||
5669fcac JB |
282 | /* KMS EnterVT equivalent */ |
283 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { | |
284 | mutex_lock(&dev->struct_mutex); | |
285 | dev_priv->mm.suspended = 0; | |
286 | ||
84b79f8d | 287 | error = i915_gem_init_ringbuffer(dev); |
5669fcac | 288 | mutex_unlock(&dev->struct_mutex); |
226485e9 JB |
289 | |
290 | drm_irq_install(dev); | |
84b79f8d | 291 | |
354ff967 ZY |
292 | /* Resume the modeset for every activated CRTC */ |
293 | drm_helper_resume_force_mode(dev); | |
294 | } | |
5669fcac | 295 | |
c9354c85 | 296 | dev_priv->modeset_on_lid = 0; |
06891e27 | 297 | |
84b79f8d RW |
298 | return error; |
299 | } | |
300 | ||
6a9ee8af | 301 | int i915_resume(struct drm_device *dev) |
84b79f8d RW |
302 | { |
303 | if (pci_enable_device(dev->pdev)) | |
304 | return -EIO; | |
305 | ||
306 | pci_set_master(dev->pdev); | |
307 | ||
84b79f8d | 308 | return i915_drm_thaw(dev); |
ba8bbcf6 JB |
309 | } |
310 | ||
11ed50ec BG |
311 | /** |
312 | * i965_reset - reset chip after a hang | |
313 | * @dev: drm device to reset | |
314 | * @flags: reset domains | |
315 | * | |
316 | * Reset the chip. Useful if a hang is detected. Returns zero on successful | |
317 | * reset or otherwise an error code. | |
318 | * | |
319 | * Procedure is fairly simple: | |
320 | * - reset the chip using the reset reg | |
321 | * - re-init context state | |
322 | * - re-init hardware status page | |
323 | * - re-init ring buffer | |
324 | * - re-init interrupt state | |
325 | * - re-init display | |
326 | */ | |
327 | int i965_reset(struct drm_device *dev, u8 flags) | |
328 | { | |
329 | drm_i915_private_t *dev_priv = dev->dev_private; | |
330 | unsigned long timeout; | |
331 | u8 gdrst; | |
332 | /* | |
333 | * We really should only reset the display subsystem if we actually | |
334 | * need to | |
335 | */ | |
336 | bool need_display = true; | |
337 | ||
338 | mutex_lock(&dev->struct_mutex); | |
339 | ||
340 | /* | |
341 | * Clear request list | |
342 | */ | |
852835f3 | 343 | i915_gem_retire_requests(dev, &dev_priv->render_ring); |
11ed50ec BG |
344 | |
345 | if (need_display) | |
346 | i915_save_display(dev); | |
347 | ||
348 | if (IS_I965G(dev) || IS_G4X(dev)) { | |
349 | /* | |
350 | * Set the domains we want to reset, then the reset bit (bit 0). | |
351 | * Clear the reset bit after a while and wait for hardware status | |
352 | * bit (bit 1) to be set | |
353 | */ | |
354 | pci_read_config_byte(dev->pdev, GDRST, &gdrst); | |
355 | pci_write_config_byte(dev->pdev, GDRST, gdrst | flags | ((flags == GDRST_FULL) ? 0x1 : 0x0)); | |
356 | udelay(50); | |
357 | pci_write_config_byte(dev->pdev, GDRST, gdrst & 0xfe); | |
358 | ||
359 | /* ...we don't want to loop forever though, 500ms should be plenty */ | |
360 | timeout = jiffies + msecs_to_jiffies(500); | |
361 | do { | |
362 | udelay(100); | |
363 | pci_read_config_byte(dev->pdev, GDRST, &gdrst); | |
364 | } while ((gdrst & 0x1) && time_after(timeout, jiffies)); | |
365 | ||
366 | if (gdrst & 0x1) { | |
367 | WARN(true, "i915: Failed to reset chip\n"); | |
368 | mutex_unlock(&dev->struct_mutex); | |
369 | return -EIO; | |
370 | } | |
371 | } else { | |
372 | DRM_ERROR("Error occurred. Don't know how to reset this chip.\n"); | |
f953c935 | 373 | mutex_unlock(&dev->struct_mutex); |
11ed50ec BG |
374 | return -ENODEV; |
375 | } | |
376 | ||
377 | /* Ok, now get things going again... */ | |
378 | ||
379 | /* | |
380 | * Everything depends on having the GTT running, so we need to start | |
381 | * there. Fortunately we don't need to do this unless we reset the | |
382 | * chip at a PCI level. | |
383 | * | |
384 | * Next we need to restore the context, but we don't use those | |
385 | * yet either... | |
386 | * | |
387 | * Ring buffer needs to be re-initialized in the KMS case, or if X | |
388 | * was running at the time of the reset (i.e. we weren't VT | |
389 | * switched away). | |
390 | */ | |
391 | if (drm_core_check_feature(dev, DRIVER_MODESET) || | |
8187a2b7 ZN |
392 | !dev_priv->mm.suspended) { |
393 | struct intel_ring_buffer *ring = &dev_priv->render_ring; | |
11ed50ec | 394 | dev_priv->mm.suspended = 0; |
8187a2b7 | 395 | ring->init(dev, ring); |
11ed50ec BG |
396 | mutex_unlock(&dev->struct_mutex); |
397 | drm_irq_uninstall(dev); | |
398 | drm_irq_install(dev); | |
399 | mutex_lock(&dev->struct_mutex); | |
400 | } | |
401 | ||
402 | /* | |
403 | * Display needs restore too... | |
404 | */ | |
405 | if (need_display) | |
406 | i915_restore_display(dev); | |
407 | ||
408 | mutex_unlock(&dev->struct_mutex); | |
409 | return 0; | |
410 | } | |
411 | ||
412 | ||
112b715e KH |
413 | static int __devinit |
414 | i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) | |
415 | { | |
dcdb1674 | 416 | return drm_get_pci_dev(pdev, ent, &driver); |
112b715e KH |
417 | } |
418 | ||
419 | static void | |
420 | i915_pci_remove(struct pci_dev *pdev) | |
421 | { | |
422 | struct drm_device *dev = pci_get_drvdata(pdev); | |
423 | ||
424 | drm_put_dev(dev); | |
425 | } | |
426 | ||
84b79f8d | 427 | static int i915_pm_suspend(struct device *dev) |
112b715e | 428 | { |
84b79f8d RW |
429 | struct pci_dev *pdev = to_pci_dev(dev); |
430 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
431 | int error; | |
112b715e | 432 | |
84b79f8d RW |
433 | if (!drm_dev || !drm_dev->dev_private) { |
434 | dev_err(dev, "DRM not initialized, aborting suspend.\n"); | |
435 | return -ENODEV; | |
436 | } | |
112b715e | 437 | |
84b79f8d RW |
438 | error = i915_drm_freeze(drm_dev); |
439 | if (error) | |
440 | return error; | |
112b715e | 441 | |
84b79f8d RW |
442 | pci_disable_device(pdev); |
443 | pci_set_power_state(pdev, PCI_D3hot); | |
cbda12d7 | 444 | |
84b79f8d | 445 | return 0; |
cbda12d7 ZW |
446 | } |
447 | ||
84b79f8d | 448 | static int i915_pm_resume(struct device *dev) |
cbda12d7 | 449 | { |
84b79f8d RW |
450 | struct pci_dev *pdev = to_pci_dev(dev); |
451 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
452 | ||
453 | return i915_resume(drm_dev); | |
cbda12d7 ZW |
454 | } |
455 | ||
84b79f8d | 456 | static int i915_pm_freeze(struct device *dev) |
cbda12d7 | 457 | { |
84b79f8d RW |
458 | struct pci_dev *pdev = to_pci_dev(dev); |
459 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
460 | ||
461 | if (!drm_dev || !drm_dev->dev_private) { | |
462 | dev_err(dev, "DRM not initialized, aborting suspend.\n"); | |
463 | return -ENODEV; | |
464 | } | |
465 | ||
466 | return i915_drm_freeze(drm_dev); | |
cbda12d7 ZW |
467 | } |
468 | ||
84b79f8d | 469 | static int i915_pm_thaw(struct device *dev) |
cbda12d7 | 470 | { |
84b79f8d RW |
471 | struct pci_dev *pdev = to_pci_dev(dev); |
472 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
473 | ||
474 | return i915_drm_thaw(drm_dev); | |
cbda12d7 ZW |
475 | } |
476 | ||
84b79f8d | 477 | static int i915_pm_poweroff(struct device *dev) |
cbda12d7 | 478 | { |
84b79f8d RW |
479 | struct pci_dev *pdev = to_pci_dev(dev); |
480 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
84b79f8d | 481 | |
61caf87c | 482 | return i915_drm_freeze(drm_dev); |
cbda12d7 ZW |
483 | } |
484 | ||
485 | const struct dev_pm_ops i915_pm_ops = { | |
486 | .suspend = i915_pm_suspend, | |
487 | .resume = i915_pm_resume, | |
488 | .freeze = i915_pm_freeze, | |
489 | .thaw = i915_pm_thaw, | |
490 | .poweroff = i915_pm_poweroff, | |
84b79f8d | 491 | .restore = i915_pm_resume, |
cbda12d7 ZW |
492 | }; |
493 | ||
de151cf6 JB |
494 | static struct vm_operations_struct i915_gem_vm_ops = { |
495 | .fault = i915_gem_fault, | |
ab00b3e5 JB |
496 | .open = drm_gem_vm_open, |
497 | .close = drm_gem_vm_close, | |
de151cf6 JB |
498 | }; |
499 | ||
1da177e4 | 500 | static struct drm_driver driver = { |
792d2b9a DA |
501 | /* don't use mtrr's here, the Xserver or user space app should |
502 | * deal with them for intel hardware. | |
503 | */ | |
673a394b EA |
504 | .driver_features = |
505 | DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR |*/ | |
506 | DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM, | |
22eae947 | 507 | .load = i915_driver_load, |
ba8bbcf6 | 508 | .unload = i915_driver_unload, |
673a394b | 509 | .open = i915_driver_open, |
22eae947 DA |
510 | .lastclose = i915_driver_lastclose, |
511 | .preclose = i915_driver_preclose, | |
673a394b | 512 | .postclose = i915_driver_postclose, |
d8e29209 RW |
513 | |
514 | /* Used in place of i915_pm_ops for non-DRIVER_MODESET */ | |
515 | .suspend = i915_suspend, | |
516 | .resume = i915_resume, | |
517 | ||
cda17380 | 518 | .device_is_agp = i915_driver_device_is_agp, |
0a3e67a4 JB |
519 | .enable_vblank = i915_enable_vblank, |
520 | .disable_vblank = i915_disable_vblank, | |
1da177e4 LT |
521 | .irq_preinstall = i915_driver_irq_preinstall, |
522 | .irq_postinstall = i915_driver_irq_postinstall, | |
523 | .irq_uninstall = i915_driver_irq_uninstall, | |
524 | .irq_handler = i915_driver_irq_handler, | |
525 | .reclaim_buffers = drm_core_reclaim_buffers, | |
526 | .get_map_ofs = drm_core_get_map_ofs, | |
527 | .get_reg_ofs = drm_core_get_reg_ofs, | |
7c1c2871 DA |
528 | .master_create = i915_master_create, |
529 | .master_destroy = i915_master_destroy, | |
955b12de | 530 | #if defined(CONFIG_DEBUG_FS) |
27c202ad BG |
531 | .debugfs_init = i915_debugfs_init, |
532 | .debugfs_cleanup = i915_debugfs_cleanup, | |
955b12de | 533 | #endif |
673a394b EA |
534 | .gem_init_object = i915_gem_init_object, |
535 | .gem_free_object = i915_gem_free_object, | |
de151cf6 | 536 | .gem_vm_ops = &i915_gem_vm_ops, |
1da177e4 LT |
537 | .ioctls = i915_ioctls, |
538 | .fops = { | |
b5e89ed5 DA |
539 | .owner = THIS_MODULE, |
540 | .open = drm_open, | |
541 | .release = drm_release, | |
ed8b6704 | 542 | .unlocked_ioctl = drm_ioctl, |
de151cf6 | 543 | .mmap = drm_gem_mmap, |
b5e89ed5 DA |
544 | .poll = drm_poll, |
545 | .fasync = drm_fasync, | |
c9a9c5e0 | 546 | .read = drm_read, |
8ca7c1df | 547 | #ifdef CONFIG_COMPAT |
b5e89ed5 | 548 | .compat_ioctl = i915_compat_ioctl, |
8ca7c1df | 549 | #endif |
22eae947 DA |
550 | }, |
551 | ||
1da177e4 | 552 | .pci_driver = { |
22eae947 DA |
553 | .name = DRIVER_NAME, |
554 | .id_table = pciidlist, | |
112b715e KH |
555 | .probe = i915_pci_probe, |
556 | .remove = i915_pci_remove, | |
cbda12d7 | 557 | .driver.pm = &i915_pm_ops, |
22eae947 | 558 | }, |
bc5f4523 | 559 | |
22eae947 DA |
560 | .name = DRIVER_NAME, |
561 | .desc = DRIVER_DESC, | |
562 | .date = DRIVER_DATE, | |
563 | .major = DRIVER_MAJOR, | |
564 | .minor = DRIVER_MINOR, | |
565 | .patchlevel = DRIVER_PATCHLEVEL, | |
1da177e4 LT |
566 | }; |
567 | ||
568 | static int __init i915_init(void) | |
569 | { | |
1f7a6e37 ZW |
570 | if (!intel_agp_enabled) { |
571 | DRM_ERROR("drm/i915 can't work without intel_agp module!\n"); | |
572 | return -ENODEV; | |
573 | } | |
574 | ||
1da177e4 | 575 | driver.num_ioctls = i915_max_ioctl; |
79e53945 | 576 | |
31169714 CW |
577 | i915_gem_shrinker_init(); |
578 | ||
79e53945 JB |
579 | /* |
580 | * If CONFIG_DRM_I915_KMS is set, default to KMS unless | |
581 | * explicitly disabled with the module pararmeter. | |
582 | * | |
583 | * Otherwise, just follow the parameter (defaulting to off). | |
584 | * | |
585 | * Allow optional vga_text_mode_force boot option to override | |
586 | * the default behavior. | |
587 | */ | |
588 | #if defined(CONFIG_DRM_I915_KMS) | |
589 | if (i915_modeset != 0) | |
590 | driver.driver_features |= DRIVER_MODESET; | |
591 | #endif | |
592 | if (i915_modeset == 1) | |
593 | driver.driver_features |= DRIVER_MODESET; | |
594 | ||
595 | #ifdef CONFIG_VGA_CONSOLE | |
596 | if (vgacon_text_force() && i915_modeset == -1) | |
597 | driver.driver_features &= ~DRIVER_MODESET; | |
598 | #endif | |
599 | ||
f97108d1 JB |
600 | if (!(driver.driver_features & DRIVER_MODESET)) { |
601 | driver.suspend = i915_suspend; | |
602 | driver.resume = i915_resume; | |
603 | } | |
604 | ||
1da177e4 LT |
605 | return drm_init(&driver); |
606 | } | |
607 | ||
608 | static void __exit i915_exit(void) | |
609 | { | |
31169714 | 610 | i915_gem_shrinker_exit(); |
1da177e4 LT |
611 | drm_exit(&driver); |
612 | } | |
613 | ||
614 | module_init(i915_init); | |
615 | module_exit(i915_exit); | |
616 | ||
b5e89ed5 DA |
617 | MODULE_AUTHOR(DRIVER_AUTHOR); |
618 | MODULE_DESCRIPTION(DRIVER_DESC); | |
1da177e4 | 619 | MODULE_LICENSE("GPL and additional rights"); |