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1da177e4 LT |
1 | /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*- |
2 | */ | |
0d6aa60b | 3 | /* |
bc54fd1a | 4 | * |
1da177e4 LT |
5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
6 | * All Rights Reserved. | |
bc54fd1a DA |
7 | * |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the | |
10 | * "Software"), to deal in the Software without restriction, including | |
11 | * without limitation the rights to use, copy, modify, merge, publish, | |
12 | * distribute, sub license, and/or sell copies of the Software, and to | |
13 | * permit persons to whom the Software is furnished to do so, subject to | |
14 | * the following conditions: | |
15 | * | |
16 | * The above copyright notice and this permission notice (including the | |
17 | * next paragraph) shall be included in all copies or substantial portions | |
18 | * of the Software. | |
19 | * | |
20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
27 | * | |
0d6aa60b | 28 | */ |
1da177e4 | 29 | |
5669fcac | 30 | #include <linux/device.h> |
760285e7 DH |
31 | #include <drm/drmP.h> |
32 | #include <drm/i915_drm.h> | |
1da177e4 | 33 | #include "i915_drv.h" |
990bbdad | 34 | #include "i915_trace.h" |
f49f0586 | 35 | #include "intel_drv.h" |
1da177e4 | 36 | |
79e53945 | 37 | #include <linux/console.h> |
e0cd3608 | 38 | #include <linux/module.h> |
760285e7 | 39 | #include <drm/drm_crtc_helper.h> |
79e53945 | 40 | |
a35d9d3c | 41 | static int i915_modeset __read_mostly = -1; |
79e53945 | 42 | module_param_named(modeset, i915_modeset, int, 0400); |
6e96e775 BW |
43 | MODULE_PARM_DESC(modeset, |
44 | "Use kernel modesetting [KMS] (0=DRM_I915_KMS from .config, " | |
45 | "1=on, -1=force vga console preference [default])"); | |
79e53945 | 46 | |
a35d9d3c | 47 | unsigned int i915_fbpercrtc __always_unused = 0; |
79e53945 | 48 | module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400); |
1da177e4 | 49 | |
a726915c | 50 | int i915_panel_ignore_lid __read_mostly = 1; |
fca87409 | 51 | module_param_named(panel_ignore_lid, i915_panel_ignore_lid, int, 0600); |
6e96e775 | 52 | MODULE_PARM_DESC(panel_ignore_lid, |
a726915c DV |
53 | "Override lid status (0=autodetect, 1=autodetect disabled [default], " |
54 | "-1=force lid closed, -2=force lid open)"); | |
fca87409 | 55 | |
a35d9d3c | 56 | unsigned int i915_powersave __read_mostly = 1; |
0aa99277 | 57 | module_param_named(powersave, i915_powersave, int, 0600); |
6e96e775 BW |
58 | MODULE_PARM_DESC(powersave, |
59 | "Enable powersavings, fbc, downclocking, etc. (default: true)"); | |
652c393a | 60 | |
f45b5557 | 61 | int i915_semaphores __read_mostly = -1; |
a1656b90 | 62 | module_param_named(semaphores, i915_semaphores, int, 0600); |
6e96e775 | 63 | MODULE_PARM_DESC(semaphores, |
f45b5557 | 64 | "Use semaphores for inter-ring sync (default: -1 (use per-chip defaults))"); |
a1656b90 | 65 | |
c0f372b3 | 66 | int i915_enable_rc6 __read_mostly = -1; |
f57f9c16 | 67 | module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0400); |
6e96e775 | 68 | MODULE_PARM_DESC(i915_enable_rc6, |
83b7f9ac ED |
69 | "Enable power-saving render C-state 6. " |
70 | "Different stages can be selected via bitmask values " | |
71 | "(0 = disable; 1 = enable rc6; 2 = enable deep rc6; 4 = enable deepest rc6). " | |
72 | "For example, 3 would enable rc6 and deep rc6, and 7 would enable everything. " | |
73 | "default: -1 (use per-chip default)"); | |
ac668088 | 74 | |
4415e63b | 75 | int i915_enable_fbc __read_mostly = -1; |
c1a9f047 | 76 | module_param_named(i915_enable_fbc, i915_enable_fbc, int, 0600); |
6e96e775 BW |
77 | MODULE_PARM_DESC(i915_enable_fbc, |
78 | "Enable frame buffer compression for power savings " | |
cd0de039 | 79 | "(default: -1 (use per-chip default))"); |
c1a9f047 | 80 | |
a35d9d3c | 81 | unsigned int i915_lvds_downclock __read_mostly = 0; |
33814341 | 82 | module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400); |
6e96e775 BW |
83 | MODULE_PARM_DESC(lvds_downclock, |
84 | "Use panel (LVDS/eDP) downclocking for power savings " | |
85 | "(default: false)"); | |
33814341 | 86 | |
121d527a TI |
87 | int i915_lvds_channel_mode __read_mostly; |
88 | module_param_named(lvds_channel_mode, i915_lvds_channel_mode, int, 0600); | |
89 | MODULE_PARM_DESC(lvds_channel_mode, | |
90 | "Specify LVDS channel mode " | |
91 | "(0=probe BIOS [default], 1=single-channel, 2=dual-channel)"); | |
92 | ||
4415e63b | 93 | int i915_panel_use_ssc __read_mostly = -1; |
a7615030 | 94 | module_param_named(lvds_use_ssc, i915_panel_use_ssc, int, 0600); |
6e96e775 BW |
95 | MODULE_PARM_DESC(lvds_use_ssc, |
96 | "Use Spread Spectrum Clock with panels [LVDS/eDP] " | |
72bbe58c | 97 | "(default: auto from VBT)"); |
a7615030 | 98 | |
a35d9d3c | 99 | int i915_vbt_sdvo_panel_type __read_mostly = -1; |
5a1e5b6c | 100 | module_param_named(vbt_sdvo_panel_type, i915_vbt_sdvo_panel_type, int, 0600); |
6e96e775 | 101 | MODULE_PARM_DESC(vbt_sdvo_panel_type, |
c10e408a MF |
102 | "Override/Ignore selection of SDVO panel mode in the VBT " |
103 | "(-2=ignore, -1=auto [default], index in VBT BIOS table)"); | |
5a1e5b6c | 104 | |
a35d9d3c | 105 | static bool i915_try_reset __read_mostly = true; |
d78cb50b | 106 | module_param_named(reset, i915_try_reset, bool, 0600); |
6e96e775 | 107 | MODULE_PARM_DESC(reset, "Attempt GPU resets (default: true)"); |
d78cb50b | 108 | |
a35d9d3c | 109 | bool i915_enable_hangcheck __read_mostly = true; |
3e0dc6b0 | 110 | module_param_named(enable_hangcheck, i915_enable_hangcheck, bool, 0644); |
6e96e775 BW |
111 | MODULE_PARM_DESC(enable_hangcheck, |
112 | "Periodically check GPU activity for detecting hangs. " | |
113 | "WARNING: Disabling this can cause system wide hangs. " | |
114 | "(default: true)"); | |
3e0dc6b0 | 115 | |
650dc07e DV |
116 | int i915_enable_ppgtt __read_mostly = -1; |
117 | module_param_named(i915_enable_ppgtt, i915_enable_ppgtt, int, 0600); | |
e21af88d DV |
118 | MODULE_PARM_DESC(i915_enable_ppgtt, |
119 | "Enable PPGTT (default: true)"); | |
120 | ||
0a3af268 RV |
121 | unsigned int i915_preliminary_hw_support __read_mostly = 0; |
122 | module_param_named(preliminary_hw_support, i915_preliminary_hw_support, int, 0600); | |
123 | MODULE_PARM_DESC(preliminary_hw_support, | |
c4aaf350 | 124 | "Enable preliminary hardware support. (default: false)"); |
0a3af268 | 125 | |
bf51d5e2 | 126 | int i915_disable_power_well __read_mostly = 1; |
2124b72e PZ |
127 | module_param_named(disable_power_well, i915_disable_power_well, int, 0600); |
128 | MODULE_PARM_DESC(disable_power_well, | |
bf51d5e2 | 129 | "Disable the power well when possible (default: true)"); |
2124b72e | 130 | |
3c4ca58c PZ |
131 | int i915_enable_ips __read_mostly = 1; |
132 | module_param_named(enable_ips, i915_enable_ips, int, 0600); | |
133 | MODULE_PARM_DESC(enable_ips, "Enable IPS (default: true)"); | |
134 | ||
112b715e | 135 | static struct drm_driver driver; |
1f7a6e37 | 136 | extern int intel_agp_enabled; |
112b715e | 137 | |
cfdf1fa2 | 138 | #define INTEL_VGA_DEVICE(id, info) { \ |
80a2901d | 139 | .class = PCI_BASE_CLASS_DISPLAY << 16, \ |
934f992c | 140 | .class_mask = 0xff0000, \ |
49ae35f2 KH |
141 | .vendor = 0x8086, \ |
142 | .device = id, \ | |
143 | .subvendor = PCI_ANY_ID, \ | |
144 | .subdevice = PCI_ANY_ID, \ | |
cfdf1fa2 KH |
145 | .driver_data = (unsigned long) info } |
146 | ||
999bcdea BW |
147 | #define INTEL_QUANTA_VGA_DEVICE(info) { \ |
148 | .class = PCI_BASE_CLASS_DISPLAY << 16, \ | |
149 | .class_mask = 0xff0000, \ | |
150 | .vendor = 0x8086, \ | |
151 | .device = 0x16a, \ | |
152 | .subvendor = 0x152d, \ | |
153 | .subdevice = 0x8990, \ | |
154 | .driver_data = (unsigned long) info } | |
155 | ||
156 | ||
9a7e8492 | 157 | static const struct intel_device_info intel_i830_info = { |
7eb552ae | 158 | .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2, |
31578148 | 159 | .has_overlay = 1, .overlay_needs_physical = 1, |
cfdf1fa2 KH |
160 | }; |
161 | ||
9a7e8492 | 162 | static const struct intel_device_info intel_845g_info = { |
7eb552ae | 163 | .gen = 2, .num_pipes = 1, |
31578148 | 164 | .has_overlay = 1, .overlay_needs_physical = 1, |
cfdf1fa2 KH |
165 | }; |
166 | ||
9a7e8492 | 167 | static const struct intel_device_info intel_i85x_info = { |
7eb552ae | 168 | .gen = 2, .is_i85x = 1, .is_mobile = 1, .num_pipes = 2, |
5ce8ba7c | 169 | .cursor_needs_physical = 1, |
31578148 | 170 | .has_overlay = 1, .overlay_needs_physical = 1, |
cfdf1fa2 KH |
171 | }; |
172 | ||
9a7e8492 | 173 | static const struct intel_device_info intel_i865g_info = { |
7eb552ae | 174 | .gen = 2, .num_pipes = 1, |
31578148 | 175 | .has_overlay = 1, .overlay_needs_physical = 1, |
cfdf1fa2 KH |
176 | }; |
177 | ||
9a7e8492 | 178 | static const struct intel_device_info intel_i915g_info = { |
7eb552ae | 179 | .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2, |
31578148 | 180 | .has_overlay = 1, .overlay_needs_physical = 1, |
cfdf1fa2 | 181 | }; |
9a7e8492 | 182 | static const struct intel_device_info intel_i915gm_info = { |
7eb552ae | 183 | .gen = 3, .is_mobile = 1, .num_pipes = 2, |
b295d1b6 | 184 | .cursor_needs_physical = 1, |
31578148 | 185 | .has_overlay = 1, .overlay_needs_physical = 1, |
a6c45cf0 | 186 | .supports_tv = 1, |
cfdf1fa2 | 187 | }; |
9a7e8492 | 188 | static const struct intel_device_info intel_i945g_info = { |
7eb552ae | 189 | .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2, |
31578148 | 190 | .has_overlay = 1, .overlay_needs_physical = 1, |
cfdf1fa2 | 191 | }; |
9a7e8492 | 192 | static const struct intel_device_info intel_i945gm_info = { |
7eb552ae | 193 | .gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2, |
b295d1b6 | 194 | .has_hotplug = 1, .cursor_needs_physical = 1, |
31578148 | 195 | .has_overlay = 1, .overlay_needs_physical = 1, |
a6c45cf0 | 196 | .supports_tv = 1, |
cfdf1fa2 KH |
197 | }; |
198 | ||
9a7e8492 | 199 | static const struct intel_device_info intel_i965g_info = { |
7eb552ae | 200 | .gen = 4, .is_broadwater = 1, .num_pipes = 2, |
c96c3a8c | 201 | .has_hotplug = 1, |
31578148 | 202 | .has_overlay = 1, |
cfdf1fa2 KH |
203 | }; |
204 | ||
9a7e8492 | 205 | static const struct intel_device_info intel_i965gm_info = { |
7eb552ae | 206 | .gen = 4, .is_crestline = 1, .num_pipes = 2, |
e3c4e5dd | 207 | .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1, |
31578148 | 208 | .has_overlay = 1, |
a6c45cf0 | 209 | .supports_tv = 1, |
cfdf1fa2 KH |
210 | }; |
211 | ||
9a7e8492 | 212 | static const struct intel_device_info intel_g33_info = { |
7eb552ae | 213 | .gen = 3, .is_g33 = 1, .num_pipes = 2, |
c96c3a8c | 214 | .need_gfx_hws = 1, .has_hotplug = 1, |
31578148 | 215 | .has_overlay = 1, |
cfdf1fa2 KH |
216 | }; |
217 | ||
9a7e8492 | 218 | static const struct intel_device_info intel_g45_info = { |
7eb552ae | 219 | .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2, |
c96c3a8c | 220 | .has_pipe_cxsr = 1, .has_hotplug = 1, |
92f49d9c | 221 | .has_bsd_ring = 1, |
cfdf1fa2 KH |
222 | }; |
223 | ||
9a7e8492 | 224 | static const struct intel_device_info intel_gm45_info = { |
7eb552ae | 225 | .gen = 4, .is_g4x = 1, .num_pipes = 2, |
e3c4e5dd | 226 | .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1, |
c96c3a8c | 227 | .has_pipe_cxsr = 1, .has_hotplug = 1, |
a6c45cf0 | 228 | .supports_tv = 1, |
92f49d9c | 229 | .has_bsd_ring = 1, |
cfdf1fa2 KH |
230 | }; |
231 | ||
9a7e8492 | 232 | static const struct intel_device_info intel_pineview_info = { |
7eb552ae | 233 | .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2, |
c96c3a8c | 234 | .need_gfx_hws = 1, .has_hotplug = 1, |
31578148 | 235 | .has_overlay = 1, |
cfdf1fa2 KH |
236 | }; |
237 | ||
9a7e8492 | 238 | static const struct intel_device_info intel_ironlake_d_info = { |
7eb552ae | 239 | .gen = 5, .num_pipes = 2, |
5a117db7 | 240 | .need_gfx_hws = 1, .has_hotplug = 1, |
92f49d9c | 241 | .has_bsd_ring = 1, |
cfdf1fa2 KH |
242 | }; |
243 | ||
9a7e8492 | 244 | static const struct intel_device_info intel_ironlake_m_info = { |
7eb552ae | 245 | .gen = 5, .is_mobile = 1, .num_pipes = 2, |
e3c4e5dd | 246 | .need_gfx_hws = 1, .has_hotplug = 1, |
c1a9f047 | 247 | .has_fbc = 1, |
92f49d9c | 248 | .has_bsd_ring = 1, |
cfdf1fa2 KH |
249 | }; |
250 | ||
9a7e8492 | 251 | static const struct intel_device_info intel_sandybridge_d_info = { |
7eb552ae | 252 | .gen = 6, .num_pipes = 2, |
c96c3a8c | 253 | .need_gfx_hws = 1, .has_hotplug = 1, |
881f47b6 | 254 | .has_bsd_ring = 1, |
549f7365 | 255 | .has_blt_ring = 1, |
3d29b842 | 256 | .has_llc = 1, |
b7884eb4 | 257 | .has_force_wake = 1, |
f6e450a6 EA |
258 | }; |
259 | ||
9a7e8492 | 260 | static const struct intel_device_info intel_sandybridge_m_info = { |
7eb552ae | 261 | .gen = 6, .is_mobile = 1, .num_pipes = 2, |
c96c3a8c | 262 | .need_gfx_hws = 1, .has_hotplug = 1, |
9c04f015 | 263 | .has_fbc = 1, |
881f47b6 | 264 | .has_bsd_ring = 1, |
549f7365 | 265 | .has_blt_ring = 1, |
3d29b842 | 266 | .has_llc = 1, |
b7884eb4 | 267 | .has_force_wake = 1, |
a13e4093 EA |
268 | }; |
269 | ||
219f4fdb BW |
270 | #define GEN7_FEATURES \ |
271 | .gen = 7, .num_pipes = 3, \ | |
272 | .need_gfx_hws = 1, .has_hotplug = 1, \ | |
273 | .has_bsd_ring = 1, \ | |
274 | .has_blt_ring = 1, \ | |
275 | .has_llc = 1, \ | |
276 | .has_force_wake = 1 | |
277 | ||
c76b615c | 278 | static const struct intel_device_info intel_ivybridge_d_info = { |
219f4fdb BW |
279 | GEN7_FEATURES, |
280 | .is_ivybridge = 1, | |
c76b615c JB |
281 | }; |
282 | ||
283 | static const struct intel_device_info intel_ivybridge_m_info = { | |
219f4fdb BW |
284 | GEN7_FEATURES, |
285 | .is_ivybridge = 1, | |
286 | .is_mobile = 1, | |
abe959c7 | 287 | .has_fbc = 1, |
c76b615c JB |
288 | }; |
289 | ||
999bcdea BW |
290 | static const struct intel_device_info intel_ivybridge_q_info = { |
291 | GEN7_FEATURES, | |
292 | .is_ivybridge = 1, | |
293 | .num_pipes = 0, /* legal, last one wins */ | |
294 | }; | |
295 | ||
70a3eb7a | 296 | static const struct intel_device_info intel_valleyview_m_info = { |
219f4fdb BW |
297 | GEN7_FEATURES, |
298 | .is_mobile = 1, | |
299 | .num_pipes = 2, | |
70a3eb7a | 300 | .is_valleyview = 1, |
fba5d532 | 301 | .display_mmio_offset = VLV_DISPLAY_BASE, |
30ccd964 | 302 | .has_llc = 0, /* legal, last one wins */ |
70a3eb7a JB |
303 | }; |
304 | ||
305 | static const struct intel_device_info intel_valleyview_d_info = { | |
219f4fdb BW |
306 | GEN7_FEATURES, |
307 | .num_pipes = 2, | |
70a3eb7a | 308 | .is_valleyview = 1, |
fba5d532 | 309 | .display_mmio_offset = VLV_DISPLAY_BASE, |
30ccd964 | 310 | .has_llc = 0, /* legal, last one wins */ |
70a3eb7a JB |
311 | }; |
312 | ||
4cae9ae0 | 313 | static const struct intel_device_info intel_haswell_d_info = { |
219f4fdb BW |
314 | GEN7_FEATURES, |
315 | .is_haswell = 1, | |
dd93be58 | 316 | .has_ddi = 1, |
30568c45 | 317 | .has_fpga_dbg = 1, |
f72a1183 | 318 | .has_vebox_ring = 1, |
4cae9ae0 ED |
319 | }; |
320 | ||
321 | static const struct intel_device_info intel_haswell_m_info = { | |
219f4fdb BW |
322 | GEN7_FEATURES, |
323 | .is_haswell = 1, | |
324 | .is_mobile = 1, | |
dd93be58 | 325 | .has_ddi = 1, |
30568c45 | 326 | .has_fpga_dbg = 1, |
891348b2 | 327 | .has_fbc = 1, |
f72a1183 | 328 | .has_vebox_ring = 1, |
c76b615c JB |
329 | }; |
330 | ||
6103da0d CW |
331 | static const struct pci_device_id pciidlist[] = { /* aka */ |
332 | INTEL_VGA_DEVICE(0x3577, &intel_i830_info), /* I830_M */ | |
333 | INTEL_VGA_DEVICE(0x2562, &intel_845g_info), /* 845_G */ | |
334 | INTEL_VGA_DEVICE(0x3582, &intel_i85x_info), /* I855_GM */ | |
5ce8ba7c | 335 | INTEL_VGA_DEVICE(0x358e, &intel_i85x_info), |
6103da0d CW |
336 | INTEL_VGA_DEVICE(0x2572, &intel_i865g_info), /* I865_G */ |
337 | INTEL_VGA_DEVICE(0x2582, &intel_i915g_info), /* I915_G */ | |
338 | INTEL_VGA_DEVICE(0x258a, &intel_i915g_info), /* E7221_G */ | |
339 | INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info), /* I915_GM */ | |
340 | INTEL_VGA_DEVICE(0x2772, &intel_i945g_info), /* I945_G */ | |
341 | INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info), /* I945_GM */ | |
342 | INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info), /* I945_GME */ | |
343 | INTEL_VGA_DEVICE(0x2972, &intel_i965g_info), /* I946_GZ */ | |
344 | INTEL_VGA_DEVICE(0x2982, &intel_i965g_info), /* G35_G */ | |
345 | INTEL_VGA_DEVICE(0x2992, &intel_i965g_info), /* I965_Q */ | |
346 | INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info), /* I965_G */ | |
347 | INTEL_VGA_DEVICE(0x29b2, &intel_g33_info), /* Q35_G */ | |
348 | INTEL_VGA_DEVICE(0x29c2, &intel_g33_info), /* G33_G */ | |
349 | INTEL_VGA_DEVICE(0x29d2, &intel_g33_info), /* Q33_G */ | |
350 | INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info), /* I965_GM */ | |
351 | INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info), /* I965_GME */ | |
352 | INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info), /* GM45_G */ | |
353 | INTEL_VGA_DEVICE(0x2e02, &intel_g45_info), /* IGD_E_G */ | |
354 | INTEL_VGA_DEVICE(0x2e12, &intel_g45_info), /* Q45_G */ | |
355 | INTEL_VGA_DEVICE(0x2e22, &intel_g45_info), /* G45_G */ | |
356 | INTEL_VGA_DEVICE(0x2e32, &intel_g45_info), /* G41_G */ | |
357 | INTEL_VGA_DEVICE(0x2e42, &intel_g45_info), /* B43_G */ | |
41a51428 | 358 | INTEL_VGA_DEVICE(0x2e92, &intel_g45_info), /* B43_G.1 */ |
cfdf1fa2 KH |
359 | INTEL_VGA_DEVICE(0xa001, &intel_pineview_info), |
360 | INTEL_VGA_DEVICE(0xa011, &intel_pineview_info), | |
361 | INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info), | |
362 | INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info), | |
f6e450a6 | 363 | INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info), |
85540480 ZW |
364 | INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info), |
365 | INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info), | |
a13e4093 | 366 | INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info), |
85540480 | 367 | INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info), |
4fefe435 | 368 | INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info), |
85540480 | 369 | INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info), |
c76b615c JB |
370 | INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info), /* GT1 mobile */ |
371 | INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info), /* GT2 mobile */ | |
372 | INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */ | |
373 | INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */ | |
374 | INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */ | |
999bcdea | 375 | INTEL_QUANTA_VGA_DEVICE(&intel_ivybridge_q_info), /* Quanta transcode */ |
cc22a938 | 376 | INTEL_VGA_DEVICE(0x016a, &intel_ivybridge_d_info), /* GT2 server */ |
c14f5286 ED |
377 | INTEL_VGA_DEVICE(0x0402, &intel_haswell_d_info), /* GT1 desktop */ |
378 | INTEL_VGA_DEVICE(0x0412, &intel_haswell_d_info), /* GT2 desktop */ | |
1c98b487 | 379 | INTEL_VGA_DEVICE(0x0422, &intel_haswell_d_info), /* GT3 desktop */ |
c14f5286 ED |
380 | INTEL_VGA_DEVICE(0x040a, &intel_haswell_d_info), /* GT1 server */ |
381 | INTEL_VGA_DEVICE(0x041a, &intel_haswell_d_info), /* GT2 server */ | |
1c98b487 | 382 | INTEL_VGA_DEVICE(0x042a, &intel_haswell_d_info), /* GT3 server */ |
c14f5286 ED |
383 | INTEL_VGA_DEVICE(0x0406, &intel_haswell_m_info), /* GT1 mobile */ |
384 | INTEL_VGA_DEVICE(0x0416, &intel_haswell_m_info), /* GT2 mobile */ | |
da612d88 | 385 | INTEL_VGA_DEVICE(0x0426, &intel_haswell_m_info), /* GT2 mobile */ |
1c98b487 RV |
386 | INTEL_VGA_DEVICE(0x040B, &intel_haswell_d_info), /* GT1 reserved */ |
387 | INTEL_VGA_DEVICE(0x041B, &intel_haswell_d_info), /* GT2 reserved */ | |
388 | INTEL_VGA_DEVICE(0x042B, &intel_haswell_d_info), /* GT3 reserved */ | |
389 | INTEL_VGA_DEVICE(0x040E, &intel_haswell_d_info), /* GT1 reserved */ | |
390 | INTEL_VGA_DEVICE(0x041E, &intel_haswell_d_info), /* GT2 reserved */ | |
391 | INTEL_VGA_DEVICE(0x042E, &intel_haswell_d_info), /* GT3 reserved */ | |
da612d88 PZ |
392 | INTEL_VGA_DEVICE(0x0C02, &intel_haswell_d_info), /* SDV GT1 desktop */ |
393 | INTEL_VGA_DEVICE(0x0C12, &intel_haswell_d_info), /* SDV GT2 desktop */ | |
1c98b487 | 394 | INTEL_VGA_DEVICE(0x0C22, &intel_haswell_d_info), /* SDV GT3 desktop */ |
da612d88 PZ |
395 | INTEL_VGA_DEVICE(0x0C0A, &intel_haswell_d_info), /* SDV GT1 server */ |
396 | INTEL_VGA_DEVICE(0x0C1A, &intel_haswell_d_info), /* SDV GT2 server */ | |
1c98b487 | 397 | INTEL_VGA_DEVICE(0x0C2A, &intel_haswell_d_info), /* SDV GT3 server */ |
da612d88 PZ |
398 | INTEL_VGA_DEVICE(0x0C06, &intel_haswell_m_info), /* SDV GT1 mobile */ |
399 | INTEL_VGA_DEVICE(0x0C16, &intel_haswell_m_info), /* SDV GT2 mobile */ | |
1c98b487 RV |
400 | INTEL_VGA_DEVICE(0x0C26, &intel_haswell_m_info), /* SDV GT3 mobile */ |
401 | INTEL_VGA_DEVICE(0x0C0B, &intel_haswell_d_info), /* SDV GT1 reserved */ | |
402 | INTEL_VGA_DEVICE(0x0C1B, &intel_haswell_d_info), /* SDV GT2 reserved */ | |
403 | INTEL_VGA_DEVICE(0x0C2B, &intel_haswell_d_info), /* SDV GT3 reserved */ | |
404 | INTEL_VGA_DEVICE(0x0C0E, &intel_haswell_d_info), /* SDV GT1 reserved */ | |
405 | INTEL_VGA_DEVICE(0x0C1E, &intel_haswell_d_info), /* SDV GT2 reserved */ | |
406 | INTEL_VGA_DEVICE(0x0C2E, &intel_haswell_d_info), /* SDV GT3 reserved */ | |
da612d88 PZ |
407 | INTEL_VGA_DEVICE(0x0A02, &intel_haswell_d_info), /* ULT GT1 desktop */ |
408 | INTEL_VGA_DEVICE(0x0A12, &intel_haswell_d_info), /* ULT GT2 desktop */ | |
1c98b487 | 409 | INTEL_VGA_DEVICE(0x0A22, &intel_haswell_d_info), /* ULT GT3 desktop */ |
da612d88 PZ |
410 | INTEL_VGA_DEVICE(0x0A0A, &intel_haswell_d_info), /* ULT GT1 server */ |
411 | INTEL_VGA_DEVICE(0x0A1A, &intel_haswell_d_info), /* ULT GT2 server */ | |
1c98b487 | 412 | INTEL_VGA_DEVICE(0x0A2A, &intel_haswell_d_info), /* ULT GT3 server */ |
da612d88 PZ |
413 | INTEL_VGA_DEVICE(0x0A06, &intel_haswell_m_info), /* ULT GT1 mobile */ |
414 | INTEL_VGA_DEVICE(0x0A16, &intel_haswell_m_info), /* ULT GT2 mobile */ | |
1c98b487 RV |
415 | INTEL_VGA_DEVICE(0x0A26, &intel_haswell_m_info), /* ULT GT3 mobile */ |
416 | INTEL_VGA_DEVICE(0x0A0B, &intel_haswell_d_info), /* ULT GT1 reserved */ | |
417 | INTEL_VGA_DEVICE(0x0A1B, &intel_haswell_d_info), /* ULT GT2 reserved */ | |
418 | INTEL_VGA_DEVICE(0x0A2B, &intel_haswell_d_info), /* ULT GT3 reserved */ | |
419 | INTEL_VGA_DEVICE(0x0A0E, &intel_haswell_m_info), /* ULT GT1 reserved */ | |
420 | INTEL_VGA_DEVICE(0x0A1E, &intel_haswell_m_info), /* ULT GT2 reserved */ | |
421 | INTEL_VGA_DEVICE(0x0A2E, &intel_haswell_m_info), /* ULT GT3 reserved */ | |
86c268ed KG |
422 | INTEL_VGA_DEVICE(0x0D02, &intel_haswell_d_info), /* CRW GT1 desktop */ |
423 | INTEL_VGA_DEVICE(0x0D12, &intel_haswell_d_info), /* CRW GT2 desktop */ | |
1c98b487 | 424 | INTEL_VGA_DEVICE(0x0D22, &intel_haswell_d_info), /* CRW GT3 desktop */ |
86c268ed KG |
425 | INTEL_VGA_DEVICE(0x0D0A, &intel_haswell_d_info), /* CRW GT1 server */ |
426 | INTEL_VGA_DEVICE(0x0D1A, &intel_haswell_d_info), /* CRW GT2 server */ | |
1c98b487 | 427 | INTEL_VGA_DEVICE(0x0D2A, &intel_haswell_d_info), /* CRW GT3 server */ |
86c268ed KG |
428 | INTEL_VGA_DEVICE(0x0D06, &intel_haswell_m_info), /* CRW GT1 mobile */ |
429 | INTEL_VGA_DEVICE(0x0D16, &intel_haswell_m_info), /* CRW GT2 mobile */ | |
1c98b487 RV |
430 | INTEL_VGA_DEVICE(0x0D26, &intel_haswell_m_info), /* CRW GT3 mobile */ |
431 | INTEL_VGA_DEVICE(0x0D0B, &intel_haswell_d_info), /* CRW GT1 reserved */ | |
432 | INTEL_VGA_DEVICE(0x0D1B, &intel_haswell_d_info), /* CRW GT2 reserved */ | |
433 | INTEL_VGA_DEVICE(0x0D2B, &intel_haswell_d_info), /* CRW GT3 reserved */ | |
434 | INTEL_VGA_DEVICE(0x0D0E, &intel_haswell_d_info), /* CRW GT1 reserved */ | |
435 | INTEL_VGA_DEVICE(0x0D1E, &intel_haswell_d_info), /* CRW GT2 reserved */ | |
436 | INTEL_VGA_DEVICE(0x0D2E, &intel_haswell_d_info), /* CRW GT3 reserved */ | |
ff049b6c | 437 | INTEL_VGA_DEVICE(0x0f30, &intel_valleyview_m_info), |
d7fee5f6 JB |
438 | INTEL_VGA_DEVICE(0x0f31, &intel_valleyview_m_info), |
439 | INTEL_VGA_DEVICE(0x0f32, &intel_valleyview_m_info), | |
440 | INTEL_VGA_DEVICE(0x0f33, &intel_valleyview_m_info), | |
ff049b6c JB |
441 | INTEL_VGA_DEVICE(0x0157, &intel_valleyview_m_info), |
442 | INTEL_VGA_DEVICE(0x0155, &intel_valleyview_d_info), | |
49ae35f2 | 443 | {0, 0, 0} |
1da177e4 LT |
444 | }; |
445 | ||
79e53945 JB |
446 | #if defined(CONFIG_DRM_I915_KMS) |
447 | MODULE_DEVICE_TABLE(pci, pciidlist); | |
448 | #endif | |
449 | ||
0206e353 | 450 | void intel_detect_pch(struct drm_device *dev) |
3bad0781 ZW |
451 | { |
452 | struct drm_i915_private *dev_priv = dev->dev_private; | |
453 | struct pci_dev *pch; | |
454 | ||
ce1bb329 BW |
455 | /* In all current cases, num_pipes is equivalent to the PCH_NOP setting |
456 | * (which really amounts to a PCH but no South Display). | |
457 | */ | |
458 | if (INTEL_INFO(dev)->num_pipes == 0) { | |
459 | dev_priv->pch_type = PCH_NOP; | |
ce1bb329 BW |
460 | return; |
461 | } | |
462 | ||
3bad0781 ZW |
463 | /* |
464 | * The reason to probe ISA bridge instead of Dev31:Fun0 is to | |
465 | * make graphics device passthrough work easy for VMM, that only | |
466 | * need to expose ISA bridge to let driver know the real hardware | |
467 | * underneath. This is a requirement from virtualization team. | |
6a9c4b35 RG |
468 | * |
469 | * In some virtualized environments (e.g. XEN), there is irrelevant | |
470 | * ISA bridge in the system. To work reliably, we should scan trhough | |
471 | * all the ISA bridge devices and check for the first match, instead | |
472 | * of only checking the first one. | |
3bad0781 ZW |
473 | */ |
474 | pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL); | |
6a9c4b35 RG |
475 | while (pch) { |
476 | struct pci_dev *curr = pch; | |
3bad0781 | 477 | if (pch->vendor == PCI_VENDOR_ID_INTEL) { |
17a303ec | 478 | unsigned short id; |
3bad0781 | 479 | id = pch->device & INTEL_PCH_DEVICE_ID_MASK; |
17a303ec | 480 | dev_priv->pch_id = id; |
3bad0781 | 481 | |
90711d50 JB |
482 | if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) { |
483 | dev_priv->pch_type = PCH_IBX; | |
484 | DRM_DEBUG_KMS("Found Ibex Peak PCH\n"); | |
7fcb83cd | 485 | WARN_ON(!IS_GEN5(dev)); |
90711d50 | 486 | } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) { |
3bad0781 ZW |
487 | dev_priv->pch_type = PCH_CPT; |
488 | DRM_DEBUG_KMS("Found CougarPoint PCH\n"); | |
7fcb83cd | 489 | WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev))); |
c792513b JB |
490 | } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) { |
491 | /* PantherPoint is CPT compatible */ | |
492 | dev_priv->pch_type = PCH_CPT; | |
493 | DRM_DEBUG_KMS("Found PatherPoint PCH\n"); | |
7fcb83cd | 494 | WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev))); |
eb877ebf ED |
495 | } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) { |
496 | dev_priv->pch_type = PCH_LPT; | |
497 | DRM_DEBUG_KMS("Found LynxPoint PCH\n"); | |
7fcb83cd | 498 | WARN_ON(!IS_HASWELL(dev)); |
08e1413d | 499 | WARN_ON(IS_ULT(dev)); |
ae6935dd WSC |
500 | } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { |
501 | dev_priv->pch_type = PCH_LPT; | |
ae6935dd WSC |
502 | DRM_DEBUG_KMS("Found LynxPoint LP PCH\n"); |
503 | WARN_ON(!IS_HASWELL(dev)); | |
08e1413d | 504 | WARN_ON(!IS_ULT(dev)); |
6a9c4b35 RG |
505 | } else { |
506 | goto check_next; | |
3bad0781 | 507 | } |
6a9c4b35 RG |
508 | pci_dev_put(pch); |
509 | break; | |
3bad0781 | 510 | } |
6a9c4b35 RG |
511 | check_next: |
512 | pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, curr); | |
513 | pci_dev_put(curr); | |
3bad0781 | 514 | } |
6a9c4b35 RG |
515 | if (!pch) |
516 | DRM_DEBUG_KMS("No PCH found?\n"); | |
3bad0781 ZW |
517 | } |
518 | ||
2911a35b BW |
519 | bool i915_semaphore_is_enabled(struct drm_device *dev) |
520 | { | |
521 | if (INTEL_INFO(dev)->gen < 6) | |
522 | return 0; | |
523 | ||
524 | if (i915_semaphores >= 0) | |
525 | return i915_semaphores; | |
526 | ||
59de3295 | 527 | #ifdef CONFIG_INTEL_IOMMU |
2911a35b | 528 | /* Enable semaphores on SNB when IO remapping is off */ |
59de3295 DV |
529 | if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) |
530 | return false; | |
531 | #endif | |
2911a35b BW |
532 | |
533 | return 1; | |
534 | } | |
535 | ||
84b79f8d | 536 | static int i915_drm_freeze(struct drm_device *dev) |
ba8bbcf6 | 537 | { |
61caf87c | 538 | struct drm_i915_private *dev_priv = dev->dev_private; |
24576d23 | 539 | struct drm_crtc *crtc; |
61caf87c | 540 | |
b8efb17b ZR |
541 | /* ignore lid events during suspend */ |
542 | mutex_lock(&dev_priv->modeset_restore_lock); | |
543 | dev_priv->modeset_restore = MODESET_SUSPENDED; | |
544 | mutex_unlock(&dev_priv->modeset_restore_lock); | |
545 | ||
cb10799c PZ |
546 | intel_set_power_well(dev, true); |
547 | ||
5bcf719b DA |
548 | drm_kms_helper_poll_disable(dev); |
549 | ||
ba8bbcf6 | 550 | pci_save_state(dev->pdev); |
ba8bbcf6 | 551 | |
5669fcac | 552 | /* If KMS is active, we do the leavevt stuff here */ |
226485e9 | 553 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
84b79f8d RW |
554 | int error = i915_gem_idle(dev); |
555 | if (error) { | |
226485e9 | 556 | dev_err(&dev->pdev->dev, |
84b79f8d RW |
557 | "GEM idle failed, resume might fail\n"); |
558 | return error; | |
559 | } | |
a261b246 | 560 | |
1a01ab3b JB |
561 | cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work); |
562 | ||
226485e9 | 563 | drm_irq_uninstall(dev); |
15239099 | 564 | dev_priv->enable_hotplug_processing = false; |
24576d23 JB |
565 | /* |
566 | * Disable CRTCs directly since we want to preserve sw state | |
567 | * for _thaw. | |
568 | */ | |
569 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) | |
570 | dev_priv->display.crtc_disable(crtc); | |
7d708ee4 ID |
571 | |
572 | intel_modeset_suspend_hw(dev); | |
5669fcac JB |
573 | } |
574 | ||
9e06dd39 JB |
575 | i915_save_state(dev); |
576 | ||
44834a67 | 577 | intel_opregion_fini(dev); |
8ee1c3db | 578 | |
3fa016a0 | 579 | console_lock(); |
b6f3eff7 | 580 | intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED); |
3fa016a0 DA |
581 | console_unlock(); |
582 | ||
61caf87c | 583 | return 0; |
84b79f8d RW |
584 | } |
585 | ||
6a9ee8af | 586 | int i915_suspend(struct drm_device *dev, pm_message_t state) |
84b79f8d RW |
587 | { |
588 | int error; | |
589 | ||
590 | if (!dev || !dev->dev_private) { | |
591 | DRM_ERROR("dev: %p\n", dev); | |
592 | DRM_ERROR("DRM not initialized, aborting suspend.\n"); | |
593 | return -ENODEV; | |
594 | } | |
595 | ||
596 | if (state.event == PM_EVENT_PRETHAW) | |
597 | return 0; | |
598 | ||
5bcf719b DA |
599 | |
600 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) | |
601 | return 0; | |
6eecba33 | 602 | |
84b79f8d RW |
603 | error = i915_drm_freeze(dev); |
604 | if (error) | |
605 | return error; | |
606 | ||
b932ccb5 DA |
607 | if (state.event == PM_EVENT_SUSPEND) { |
608 | /* Shut down the device */ | |
609 | pci_disable_device(dev->pdev); | |
610 | pci_set_power_state(dev->pdev, PCI_D3hot); | |
611 | } | |
ba8bbcf6 JB |
612 | |
613 | return 0; | |
614 | } | |
615 | ||
073f34d9 JB |
616 | void intel_console_resume(struct work_struct *work) |
617 | { | |
618 | struct drm_i915_private *dev_priv = | |
619 | container_of(work, struct drm_i915_private, | |
620 | console_resume_work); | |
621 | struct drm_device *dev = dev_priv->dev; | |
622 | ||
623 | console_lock(); | |
b6f3eff7 | 624 | intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING); |
073f34d9 JB |
625 | console_unlock(); |
626 | } | |
627 | ||
bb60b969 JB |
628 | static void intel_resume_hotplug(struct drm_device *dev) |
629 | { | |
630 | struct drm_mode_config *mode_config = &dev->mode_config; | |
631 | struct intel_encoder *encoder; | |
632 | ||
633 | mutex_lock(&mode_config->mutex); | |
634 | DRM_DEBUG_KMS("running encoder hotplug functions\n"); | |
635 | ||
636 | list_for_each_entry(encoder, &mode_config->encoder_list, base.head) | |
637 | if (encoder->hot_plug) | |
638 | encoder->hot_plug(encoder); | |
639 | ||
640 | mutex_unlock(&mode_config->mutex); | |
641 | ||
642 | /* Just fire off a uevent and let userspace tell us what to do */ | |
643 | drm_helper_hpd_irq_event(dev); | |
644 | } | |
645 | ||
1abd02e2 | 646 | static int __i915_drm_thaw(struct drm_device *dev) |
ba8bbcf6 | 647 | { |
5669fcac | 648 | struct drm_i915_private *dev_priv = dev->dev_private; |
84b79f8d | 649 | int error = 0; |
8ee1c3db | 650 | |
61caf87c | 651 | i915_restore_state(dev); |
44834a67 | 652 | intel_opregion_setup(dev); |
61caf87c | 653 | |
5669fcac JB |
654 | /* KMS EnterVT equivalent */ |
655 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { | |
dde86e2d | 656 | intel_init_pch_refclk(dev); |
1833b134 | 657 | |
5669fcac JB |
658 | mutex_lock(&dev->struct_mutex); |
659 | dev_priv->mm.suspended = 0; | |
660 | ||
f691e2f4 | 661 | error = i915_gem_init_hw(dev); |
5669fcac | 662 | mutex_unlock(&dev->struct_mutex); |
226485e9 | 663 | |
15239099 DV |
664 | /* We need working interrupts for modeset enabling ... */ |
665 | drm_irq_install(dev); | |
666 | ||
1833b134 | 667 | intel_modeset_init_hw(dev); |
24576d23 JB |
668 | |
669 | drm_modeset_lock_all(dev); | |
670 | intel_modeset_setup_hw_state(dev, true); | |
671 | drm_modeset_unlock_all(dev); | |
15239099 DV |
672 | |
673 | /* | |
674 | * ... but also need to make sure that hotplug processing | |
675 | * doesn't cause havoc. Like in the driver load code we don't | |
676 | * bother with the tiny race here where we might loose hotplug | |
677 | * notifications. | |
678 | * */ | |
20afbda2 | 679 | intel_hpd_init(dev); |
15239099 | 680 | dev_priv->enable_hotplug_processing = true; |
bb60b969 JB |
681 | /* Config may have changed between suspend and resume */ |
682 | intel_resume_hotplug(dev); | |
d5bb081b | 683 | } |
1daed3fb | 684 | |
44834a67 CW |
685 | intel_opregion_init(dev); |
686 | ||
073f34d9 JB |
687 | /* |
688 | * The console lock can be pretty contented on resume due | |
689 | * to all the printk activity. Try to keep it out of the hot | |
690 | * path of resume if possible. | |
691 | */ | |
692 | if (console_trylock()) { | |
b6f3eff7 | 693 | intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING); |
073f34d9 JB |
694 | console_unlock(); |
695 | } else { | |
696 | schedule_work(&dev_priv->console_resume_work); | |
697 | } | |
698 | ||
b8efb17b ZR |
699 | mutex_lock(&dev_priv->modeset_restore_lock); |
700 | dev_priv->modeset_restore = MODESET_DONE; | |
701 | mutex_unlock(&dev_priv->modeset_restore_lock); | |
84b79f8d RW |
702 | return error; |
703 | } | |
704 | ||
1abd02e2 JB |
705 | static int i915_drm_thaw(struct drm_device *dev) |
706 | { | |
707 | int error = 0; | |
708 | ||
181d1b9e | 709 | intel_gt_sanitize(dev); |
1abd02e2 JB |
710 | |
711 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { | |
712 | mutex_lock(&dev->struct_mutex); | |
713 | i915_gem_restore_gtt_mappings(dev); | |
714 | mutex_unlock(&dev->struct_mutex); | |
715 | } | |
716 | ||
717 | __i915_drm_thaw(dev); | |
718 | ||
84b79f8d RW |
719 | return error; |
720 | } | |
721 | ||
6a9ee8af | 722 | int i915_resume(struct drm_device *dev) |
84b79f8d | 723 | { |
1abd02e2 | 724 | struct drm_i915_private *dev_priv = dev->dev_private; |
6eecba33 CW |
725 | int ret; |
726 | ||
5bcf719b DA |
727 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
728 | return 0; | |
729 | ||
84b79f8d RW |
730 | if (pci_enable_device(dev->pdev)) |
731 | return -EIO; | |
732 | ||
733 | pci_set_master(dev->pdev); | |
734 | ||
181d1b9e | 735 | intel_gt_sanitize(dev); |
1abd02e2 JB |
736 | |
737 | /* | |
738 | * Platforms with opregion should have sane BIOS, older ones (gen3 and | |
739 | * earlier) need this since the BIOS might clear all our scratch PTEs. | |
740 | */ | |
741 | if (drm_core_check_feature(dev, DRIVER_MODESET) && | |
742 | !dev_priv->opregion.header) { | |
743 | mutex_lock(&dev->struct_mutex); | |
744 | i915_gem_restore_gtt_mappings(dev); | |
745 | mutex_unlock(&dev->struct_mutex); | |
746 | } | |
747 | ||
748 | ret = __i915_drm_thaw(dev); | |
6eecba33 CW |
749 | if (ret) |
750 | return ret; | |
751 | ||
752 | drm_kms_helper_poll_enable(dev); | |
753 | return 0; | |
ba8bbcf6 JB |
754 | } |
755 | ||
d4b8bb2a | 756 | static int i8xx_do_reset(struct drm_device *dev) |
dc96e9b8 CW |
757 | { |
758 | struct drm_i915_private *dev_priv = dev->dev_private; | |
759 | ||
760 | if (IS_I85X(dev)) | |
761 | return -ENODEV; | |
762 | ||
763 | I915_WRITE(D_STATE, I915_READ(D_STATE) | DSTATE_GFX_RESET_I830); | |
764 | POSTING_READ(D_STATE); | |
765 | ||
766 | if (IS_I830(dev) || IS_845G(dev)) { | |
767 | I915_WRITE(DEBUG_RESET_I830, | |
768 | DEBUG_RESET_DISPLAY | | |
769 | DEBUG_RESET_RENDER | | |
770 | DEBUG_RESET_FULL); | |
771 | POSTING_READ(DEBUG_RESET_I830); | |
772 | msleep(1); | |
773 | ||
774 | I915_WRITE(DEBUG_RESET_I830, 0); | |
775 | POSTING_READ(DEBUG_RESET_I830); | |
776 | } | |
777 | ||
778 | msleep(1); | |
779 | ||
780 | I915_WRITE(D_STATE, I915_READ(D_STATE) & ~DSTATE_GFX_RESET_I830); | |
781 | POSTING_READ(D_STATE); | |
782 | ||
783 | return 0; | |
784 | } | |
785 | ||
f49f0586 KG |
786 | static int i965_reset_complete(struct drm_device *dev) |
787 | { | |
788 | u8 gdrst; | |
eeccdcac | 789 | pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst); |
5fe9fe8c | 790 | return (gdrst & GRDOM_RESET_ENABLE) == 0; |
f49f0586 KG |
791 | } |
792 | ||
d4b8bb2a | 793 | static int i965_do_reset(struct drm_device *dev) |
0573ed4a | 794 | { |
5ccce180 | 795 | int ret; |
0573ed4a KG |
796 | u8 gdrst; |
797 | ||
ae681d96 CW |
798 | /* |
799 | * Set the domains we want to reset (GRDOM/bits 2 and 3) as | |
800 | * well as the reset bit (GR/bit 0). Setting the GR bit | |
801 | * triggers the reset; when done, the hardware will clear it. | |
802 | */ | |
0573ed4a | 803 | pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst); |
d4b8bb2a | 804 | pci_write_config_byte(dev->pdev, I965_GDRST, |
5ccce180 DV |
805 | gdrst | GRDOM_RENDER | |
806 | GRDOM_RESET_ENABLE); | |
807 | ret = wait_for(i965_reset_complete(dev), 500); | |
808 | if (ret) | |
809 | return ret; | |
810 | ||
811 | /* We can't reset render&media without also resetting display ... */ | |
812 | pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst); | |
813 | pci_write_config_byte(dev->pdev, I965_GDRST, | |
814 | gdrst | GRDOM_MEDIA | | |
815 | GRDOM_RESET_ENABLE); | |
0573ed4a KG |
816 | |
817 | return wait_for(i965_reset_complete(dev), 500); | |
818 | } | |
819 | ||
d4b8bb2a | 820 | static int ironlake_do_reset(struct drm_device *dev) |
0573ed4a KG |
821 | { |
822 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5ccce180 DV |
823 | u32 gdrst; |
824 | int ret; | |
825 | ||
826 | gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR); | |
8a5c2ae7 | 827 | gdrst &= ~GRDOM_MASK; |
5ccce180 DV |
828 | I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, |
829 | gdrst | GRDOM_RENDER | GRDOM_RESET_ENABLE); | |
830 | ret = wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500); | |
831 | if (ret) | |
832 | return ret; | |
833 | ||
834 | /* We can't reset render&media without also resetting display ... */ | |
835 | gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR); | |
8a5c2ae7 | 836 | gdrst &= ~GRDOM_MASK; |
d4b8bb2a | 837 | I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, |
5ccce180 | 838 | gdrst | GRDOM_MEDIA | GRDOM_RESET_ENABLE); |
0573ed4a | 839 | return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500); |
ba8bbcf6 JB |
840 | } |
841 | ||
d4b8bb2a | 842 | static int gen6_do_reset(struct drm_device *dev) |
cff458c2 EA |
843 | { |
844 | struct drm_i915_private *dev_priv = dev->dev_private; | |
b6e45f86 KP |
845 | int ret; |
846 | unsigned long irqflags; | |
cff458c2 | 847 | |
286fed41 KP |
848 | /* Hold gt_lock across reset to prevent any register access |
849 | * with forcewake not set correctly | |
850 | */ | |
b6e45f86 | 851 | spin_lock_irqsave(&dev_priv->gt_lock, irqflags); |
286fed41 KP |
852 | |
853 | /* Reset the chip */ | |
854 | ||
855 | /* GEN6_GDRST is not in the gt power well, no need to check | |
856 | * for fifo space for the write or forcewake the chip for | |
857 | * the read | |
858 | */ | |
859 | I915_WRITE_NOTRACE(GEN6_GDRST, GEN6_GRDOM_FULL); | |
860 | ||
861 | /* Spin waiting for the device to ack the reset request */ | |
862 | ret = wait_for((I915_READ_NOTRACE(GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500); | |
863 | ||
864 | /* If reset with a user forcewake, try to restore, otherwise turn it off */ | |
b6e45f86 | 865 | if (dev_priv->forcewake_count) |
990bbdad | 866 | dev_priv->gt.force_wake_get(dev_priv); |
286fed41 | 867 | else |
990bbdad | 868 | dev_priv->gt.force_wake_put(dev_priv); |
286fed41 KP |
869 | |
870 | /* Restore fifo count */ | |
871 | dev_priv->gt_fifo_count = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES); | |
872 | ||
b6e45f86 KP |
873 | spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); |
874 | return ret; | |
cff458c2 EA |
875 | } |
876 | ||
8e96d9c4 | 877 | int intel_gpu_reset(struct drm_device *dev) |
350d2706 | 878 | { |
350d2706 DV |
879 | switch (INTEL_INFO(dev)->gen) { |
880 | case 7: | |
2e7c8ee7 CW |
881 | case 6: return gen6_do_reset(dev); |
882 | case 5: return ironlake_do_reset(dev); | |
883 | case 4: return i965_do_reset(dev); | |
884 | case 2: return i8xx_do_reset(dev); | |
885 | default: return -ENODEV; | |
350d2706 | 886 | } |
350d2706 DV |
887 | } |
888 | ||
11ed50ec | 889 | /** |
f3953dcb | 890 | * i915_reset - reset chip after a hang |
11ed50ec | 891 | * @dev: drm device to reset |
11ed50ec BG |
892 | * |
893 | * Reset the chip. Useful if a hang is detected. Returns zero on successful | |
894 | * reset or otherwise an error code. | |
895 | * | |
896 | * Procedure is fairly simple: | |
897 | * - reset the chip using the reset reg | |
898 | * - re-init context state | |
899 | * - re-init hardware status page | |
900 | * - re-init ring buffer | |
901 | * - re-init interrupt state | |
902 | * - re-init display | |
903 | */ | |
d4b8bb2a | 904 | int i915_reset(struct drm_device *dev) |
11ed50ec BG |
905 | { |
906 | drm_i915_private_t *dev_priv = dev->dev_private; | |
2e7c8ee7 | 907 | bool simulated; |
0573ed4a | 908 | int ret; |
11ed50ec | 909 | |
d78cb50b CW |
910 | if (!i915_try_reset) |
911 | return 0; | |
912 | ||
d54a02c0 | 913 | mutex_lock(&dev->struct_mutex); |
11ed50ec | 914 | |
069efc1d | 915 | i915_gem_reset(dev); |
77f01230 | 916 | |
2e7c8ee7 CW |
917 | simulated = dev_priv->gpu_error.stop_rings != 0; |
918 | ||
919 | if (!simulated && get_seconds() - dev_priv->gpu_error.last_reset < 5) { | |
ae681d96 | 920 | DRM_ERROR("GPU hanging too fast, declaring wedged!\n"); |
2e7c8ee7 CW |
921 | ret = -ENODEV; |
922 | } else { | |
d4b8bb2a | 923 | ret = intel_gpu_reset(dev); |
350d2706 | 924 | |
2e7c8ee7 CW |
925 | /* Also reset the gpu hangman. */ |
926 | if (simulated) { | |
927 | DRM_INFO("Simulated gpu hang, resetting stop_rings\n"); | |
928 | dev_priv->gpu_error.stop_rings = 0; | |
929 | if (ret == -ENODEV) { | |
930 | DRM_ERROR("Reset not implemented, but ignoring " | |
931 | "error for simulated gpu hangs\n"); | |
932 | ret = 0; | |
933 | } | |
934 | } else | |
935 | dev_priv->gpu_error.last_reset = get_seconds(); | |
936 | } | |
0573ed4a | 937 | if (ret) { |
f803aa55 | 938 | DRM_ERROR("Failed to reset chip.\n"); |
f953c935 | 939 | mutex_unlock(&dev->struct_mutex); |
f803aa55 | 940 | return ret; |
11ed50ec BG |
941 | } |
942 | ||
943 | /* Ok, now get things going again... */ | |
944 | ||
945 | /* | |
946 | * Everything depends on having the GTT running, so we need to start | |
947 | * there. Fortunately we don't need to do this unless we reset the | |
948 | * chip at a PCI level. | |
949 | * | |
950 | * Next we need to restore the context, but we don't use those | |
951 | * yet either... | |
952 | * | |
953 | * Ring buffer needs to be re-initialized in the KMS case, or if X | |
954 | * was running at the time of the reset (i.e. we weren't VT | |
955 | * switched away). | |
956 | */ | |
957 | if (drm_core_check_feature(dev, DRIVER_MODESET) || | |
8187a2b7 | 958 | !dev_priv->mm.suspended) { |
b4519513 CW |
959 | struct intel_ring_buffer *ring; |
960 | int i; | |
961 | ||
11ed50ec | 962 | dev_priv->mm.suspended = 0; |
75a6898f | 963 | |
f691e2f4 DV |
964 | i915_gem_init_swizzling(dev); |
965 | ||
b4519513 CW |
966 | for_each_ring(ring, dev_priv, i) |
967 | ring->init(ring); | |
75a6898f | 968 | |
254f965c | 969 | i915_gem_context_init(dev); |
b7c36d25 BW |
970 | if (dev_priv->mm.aliasing_ppgtt) { |
971 | ret = dev_priv->mm.aliasing_ppgtt->enable(dev); | |
972 | if (ret) | |
973 | i915_gem_cleanup_aliasing_ppgtt(dev); | |
974 | } | |
e21af88d | 975 | |
8e88a2bd DV |
976 | /* |
977 | * It would make sense to re-init all the other hw state, at | |
978 | * least the rps/rc6/emon init done within modeset_init_hw. For | |
979 | * some unknown reason, this blows up my ilk, so don't. | |
980 | */ | |
f817586c | 981 | |
8e88a2bd | 982 | mutex_unlock(&dev->struct_mutex); |
f817586c | 983 | |
11ed50ec BG |
984 | drm_irq_uninstall(dev); |
985 | drm_irq_install(dev); | |
20afbda2 | 986 | intel_hpd_init(dev); |
bcbc324a DV |
987 | } else { |
988 | mutex_unlock(&dev->struct_mutex); | |
11ed50ec BG |
989 | } |
990 | ||
11ed50ec BG |
991 | return 0; |
992 | } | |
993 | ||
56550d94 | 994 | static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) |
112b715e | 995 | { |
01a06850 DV |
996 | struct intel_device_info *intel_info = |
997 | (struct intel_device_info *) ent->driver_data; | |
998 | ||
5fe49d86 CW |
999 | /* Only bind to function 0 of the device. Early generations |
1000 | * used function 1 as a placeholder for multi-head. This causes | |
1001 | * us confusion instead, especially on the systems where both | |
1002 | * functions have the same PCI-ID! | |
1003 | */ | |
1004 | if (PCI_FUNC(pdev->devfn)) | |
1005 | return -ENODEV; | |
1006 | ||
01a06850 DV |
1007 | /* We've managed to ship a kms-enabled ddx that shipped with an XvMC |
1008 | * implementation for gen3 (and only gen3) that used legacy drm maps | |
1009 | * (gasp!) to share buffers between X and the client. Hence we need to | |
1010 | * keep around the fake agp stuff for gen3, even when kms is enabled. */ | |
1011 | if (intel_info->gen != 3) { | |
1012 | driver.driver_features &= | |
1013 | ~(DRIVER_USE_AGP | DRIVER_REQUIRE_AGP); | |
1014 | } else if (!intel_agp_enabled) { | |
1015 | DRM_ERROR("drm/i915 can't work without intel_agp module!\n"); | |
1016 | return -ENODEV; | |
1017 | } | |
1018 | ||
dcdb1674 | 1019 | return drm_get_pci_dev(pdev, ent, &driver); |
112b715e KH |
1020 | } |
1021 | ||
1022 | static void | |
1023 | i915_pci_remove(struct pci_dev *pdev) | |
1024 | { | |
1025 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1026 | ||
1027 | drm_put_dev(dev); | |
1028 | } | |
1029 | ||
84b79f8d | 1030 | static int i915_pm_suspend(struct device *dev) |
112b715e | 1031 | { |
84b79f8d RW |
1032 | struct pci_dev *pdev = to_pci_dev(dev); |
1033 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
1034 | int error; | |
112b715e | 1035 | |
84b79f8d RW |
1036 | if (!drm_dev || !drm_dev->dev_private) { |
1037 | dev_err(dev, "DRM not initialized, aborting suspend.\n"); | |
1038 | return -ENODEV; | |
1039 | } | |
112b715e | 1040 | |
5bcf719b DA |
1041 | if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
1042 | return 0; | |
1043 | ||
84b79f8d RW |
1044 | error = i915_drm_freeze(drm_dev); |
1045 | if (error) | |
1046 | return error; | |
112b715e | 1047 | |
84b79f8d RW |
1048 | pci_disable_device(pdev); |
1049 | pci_set_power_state(pdev, PCI_D3hot); | |
cbda12d7 | 1050 | |
84b79f8d | 1051 | return 0; |
cbda12d7 ZW |
1052 | } |
1053 | ||
84b79f8d | 1054 | static int i915_pm_resume(struct device *dev) |
cbda12d7 | 1055 | { |
84b79f8d RW |
1056 | struct pci_dev *pdev = to_pci_dev(dev); |
1057 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
1058 | ||
1059 | return i915_resume(drm_dev); | |
cbda12d7 ZW |
1060 | } |
1061 | ||
84b79f8d | 1062 | static int i915_pm_freeze(struct device *dev) |
cbda12d7 | 1063 | { |
84b79f8d RW |
1064 | struct pci_dev *pdev = to_pci_dev(dev); |
1065 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
1066 | ||
1067 | if (!drm_dev || !drm_dev->dev_private) { | |
1068 | dev_err(dev, "DRM not initialized, aborting suspend.\n"); | |
1069 | return -ENODEV; | |
1070 | } | |
1071 | ||
1072 | return i915_drm_freeze(drm_dev); | |
cbda12d7 ZW |
1073 | } |
1074 | ||
84b79f8d | 1075 | static int i915_pm_thaw(struct device *dev) |
cbda12d7 | 1076 | { |
84b79f8d RW |
1077 | struct pci_dev *pdev = to_pci_dev(dev); |
1078 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
1079 | ||
1080 | return i915_drm_thaw(drm_dev); | |
cbda12d7 ZW |
1081 | } |
1082 | ||
84b79f8d | 1083 | static int i915_pm_poweroff(struct device *dev) |
cbda12d7 | 1084 | { |
84b79f8d RW |
1085 | struct pci_dev *pdev = to_pci_dev(dev); |
1086 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
84b79f8d | 1087 | |
61caf87c | 1088 | return i915_drm_freeze(drm_dev); |
cbda12d7 ZW |
1089 | } |
1090 | ||
b4b78d12 | 1091 | static const struct dev_pm_ops i915_pm_ops = { |
0206e353 AJ |
1092 | .suspend = i915_pm_suspend, |
1093 | .resume = i915_pm_resume, | |
1094 | .freeze = i915_pm_freeze, | |
1095 | .thaw = i915_pm_thaw, | |
1096 | .poweroff = i915_pm_poweroff, | |
1097 | .restore = i915_pm_resume, | |
cbda12d7 ZW |
1098 | }; |
1099 | ||
78b68556 | 1100 | static const struct vm_operations_struct i915_gem_vm_ops = { |
de151cf6 | 1101 | .fault = i915_gem_fault, |
ab00b3e5 JB |
1102 | .open = drm_gem_vm_open, |
1103 | .close = drm_gem_vm_close, | |
de151cf6 JB |
1104 | }; |
1105 | ||
e08e96de AV |
1106 | static const struct file_operations i915_driver_fops = { |
1107 | .owner = THIS_MODULE, | |
1108 | .open = drm_open, | |
1109 | .release = drm_release, | |
1110 | .unlocked_ioctl = drm_ioctl, | |
1111 | .mmap = drm_gem_mmap, | |
1112 | .poll = drm_poll, | |
1113 | .fasync = drm_fasync, | |
1114 | .read = drm_read, | |
1115 | #ifdef CONFIG_COMPAT | |
1116 | .compat_ioctl = i915_compat_ioctl, | |
1117 | #endif | |
1118 | .llseek = noop_llseek, | |
1119 | }; | |
1120 | ||
1da177e4 | 1121 | static struct drm_driver driver = { |
0c54781b MW |
1122 | /* Don't use MTRRs here; the Xserver or userspace app should |
1123 | * deal with them for Intel hardware. | |
792d2b9a | 1124 | */ |
673a394b EA |
1125 | .driver_features = |
1126 | DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR |*/ | |
1286ff73 | 1127 | DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME, |
22eae947 | 1128 | .load = i915_driver_load, |
ba8bbcf6 | 1129 | .unload = i915_driver_unload, |
673a394b | 1130 | .open = i915_driver_open, |
22eae947 DA |
1131 | .lastclose = i915_driver_lastclose, |
1132 | .preclose = i915_driver_preclose, | |
673a394b | 1133 | .postclose = i915_driver_postclose, |
d8e29209 RW |
1134 | |
1135 | /* Used in place of i915_pm_ops for non-DRIVER_MODESET */ | |
1136 | .suspend = i915_suspend, | |
1137 | .resume = i915_resume, | |
1138 | ||
cda17380 | 1139 | .device_is_agp = i915_driver_device_is_agp, |
7c1c2871 DA |
1140 | .master_create = i915_master_create, |
1141 | .master_destroy = i915_master_destroy, | |
955b12de | 1142 | #if defined(CONFIG_DEBUG_FS) |
27c202ad BG |
1143 | .debugfs_init = i915_debugfs_init, |
1144 | .debugfs_cleanup = i915_debugfs_cleanup, | |
955b12de | 1145 | #endif |
673a394b EA |
1146 | .gem_init_object = i915_gem_init_object, |
1147 | .gem_free_object = i915_gem_free_object, | |
de151cf6 | 1148 | .gem_vm_ops = &i915_gem_vm_ops, |
1286ff73 DV |
1149 | |
1150 | .prime_handle_to_fd = drm_gem_prime_handle_to_fd, | |
1151 | .prime_fd_to_handle = drm_gem_prime_fd_to_handle, | |
1152 | .gem_prime_export = i915_gem_prime_export, | |
1153 | .gem_prime_import = i915_gem_prime_import, | |
1154 | ||
ff72145b DA |
1155 | .dumb_create = i915_gem_dumb_create, |
1156 | .dumb_map_offset = i915_gem_mmap_gtt, | |
1157 | .dumb_destroy = i915_gem_dumb_destroy, | |
1da177e4 | 1158 | .ioctls = i915_ioctls, |
e08e96de | 1159 | .fops = &i915_driver_fops, |
22eae947 DA |
1160 | .name = DRIVER_NAME, |
1161 | .desc = DRIVER_DESC, | |
1162 | .date = DRIVER_DATE, | |
1163 | .major = DRIVER_MAJOR, | |
1164 | .minor = DRIVER_MINOR, | |
1165 | .patchlevel = DRIVER_PATCHLEVEL, | |
1da177e4 LT |
1166 | }; |
1167 | ||
8410ea3b DA |
1168 | static struct pci_driver i915_pci_driver = { |
1169 | .name = DRIVER_NAME, | |
1170 | .id_table = pciidlist, | |
1171 | .probe = i915_pci_probe, | |
1172 | .remove = i915_pci_remove, | |
1173 | .driver.pm = &i915_pm_ops, | |
1174 | }; | |
1175 | ||
1da177e4 LT |
1176 | static int __init i915_init(void) |
1177 | { | |
1178 | driver.num_ioctls = i915_max_ioctl; | |
79e53945 JB |
1179 | |
1180 | /* | |
1181 | * If CONFIG_DRM_I915_KMS is set, default to KMS unless | |
1182 | * explicitly disabled with the module pararmeter. | |
1183 | * | |
1184 | * Otherwise, just follow the parameter (defaulting to off). | |
1185 | * | |
1186 | * Allow optional vga_text_mode_force boot option to override | |
1187 | * the default behavior. | |
1188 | */ | |
1189 | #if defined(CONFIG_DRM_I915_KMS) | |
1190 | if (i915_modeset != 0) | |
1191 | driver.driver_features |= DRIVER_MODESET; | |
1192 | #endif | |
1193 | if (i915_modeset == 1) | |
1194 | driver.driver_features |= DRIVER_MODESET; | |
1195 | ||
1196 | #ifdef CONFIG_VGA_CONSOLE | |
1197 | if (vgacon_text_force() && i915_modeset == -1) | |
1198 | driver.driver_features &= ~DRIVER_MODESET; | |
1199 | #endif | |
1200 | ||
3885c6bb CW |
1201 | if (!(driver.driver_features & DRIVER_MODESET)) |
1202 | driver.get_vblank_timestamp = NULL; | |
1203 | ||
8410ea3b | 1204 | return drm_pci_init(&driver, &i915_pci_driver); |
1da177e4 LT |
1205 | } |
1206 | ||
1207 | static void __exit i915_exit(void) | |
1208 | { | |
8410ea3b | 1209 | drm_pci_exit(&driver, &i915_pci_driver); |
1da177e4 LT |
1210 | } |
1211 | ||
1212 | module_init(i915_init); | |
1213 | module_exit(i915_exit); | |
1214 | ||
b5e89ed5 DA |
1215 | MODULE_AUTHOR(DRIVER_AUTHOR); |
1216 | MODULE_DESCRIPTION(DRIVER_DESC); | |
1da177e4 | 1217 | MODULE_LICENSE("GPL and additional rights"); |
f7000883 | 1218 | |
b7d84096 JB |
1219 | /* We give fast paths for the really cool registers */ |
1220 | #define NEEDS_FORCE_WAKE(dev_priv, reg) \ | |
b7884eb4 DV |
1221 | ((HAS_FORCE_WAKE((dev_priv)->dev)) && \ |
1222 | ((reg) < 0x40000) && \ | |
1223 | ((reg) != FORCEWAKE)) | |
a8b1397d DV |
1224 | static void |
1225 | ilk_dummy_write(struct drm_i915_private *dev_priv) | |
1226 | { | |
ecdb4eb7 DL |
1227 | /* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up |
1228 | * the chip from rc6 before touching it for real. MI_MODE is masked, | |
1229 | * hence harmless to write 0 into. */ | |
a8b1397d DV |
1230 | I915_WRITE_NOTRACE(MI_MODE, 0); |
1231 | } | |
1232 | ||
115bc2de PZ |
1233 | static void |
1234 | hsw_unclaimed_reg_clear(struct drm_i915_private *dev_priv, u32 reg) | |
1235 | { | |
e76ebff8 | 1236 | if (HAS_FPGA_DBG_UNCLAIMED(dev_priv->dev) && |
3f1e109a | 1237 | (I915_READ_NOTRACE(FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) { |
115bc2de PZ |
1238 | DRM_ERROR("Unknown unclaimed register before writing to %x\n", |
1239 | reg); | |
3f1e109a | 1240 | I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM); |
115bc2de PZ |
1241 | } |
1242 | } | |
1243 | ||
1244 | static void | |
1245 | hsw_unclaimed_reg_check(struct drm_i915_private *dev_priv, u32 reg) | |
1246 | { | |
e76ebff8 | 1247 | if (HAS_FPGA_DBG_UNCLAIMED(dev_priv->dev) && |
3f1e109a | 1248 | (I915_READ_NOTRACE(FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) { |
115bc2de | 1249 | DRM_ERROR("Unclaimed write to %x\n", reg); |
3f1e109a | 1250 | I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM); |
115bc2de PZ |
1251 | } |
1252 | } | |
1253 | ||
f7000883 AK |
1254 | #define __i915_read(x, y) \ |
1255 | u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \ | |
a7cd1b8f | 1256 | unsigned long irqflags; \ |
f7000883 | 1257 | u##x val = 0; \ |
a7cd1b8f | 1258 | spin_lock_irqsave(&dev_priv->gt_lock, irqflags); \ |
a8b1397d DV |
1259 | if (IS_GEN5(dev_priv->dev)) \ |
1260 | ilk_dummy_write(dev_priv); \ | |
f7000883 | 1261 | if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ |
c937504e | 1262 | if (dev_priv->forcewake_count == 0) \ |
990bbdad | 1263 | dev_priv->gt.force_wake_get(dev_priv); \ |
f7000883 | 1264 | val = read##y(dev_priv->regs + reg); \ |
c937504e | 1265 | if (dev_priv->forcewake_count == 0) \ |
990bbdad | 1266 | dev_priv->gt.force_wake_put(dev_priv); \ |
f7000883 AK |
1267 | } else { \ |
1268 | val = read##y(dev_priv->regs + reg); \ | |
1269 | } \ | |
a7cd1b8f | 1270 | spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); \ |
f7000883 AK |
1271 | trace_i915_reg_rw(false, reg, val, sizeof(val)); \ |
1272 | return val; \ | |
1273 | } | |
1274 | ||
1275 | __i915_read(8, b) | |
1276 | __i915_read(16, w) | |
1277 | __i915_read(32, l) | |
1278 | __i915_read(64, q) | |
1279 | #undef __i915_read | |
1280 | ||
1281 | #define __i915_write(x, y) \ | |
1282 | void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \ | |
a7cd1b8f | 1283 | unsigned long irqflags; \ |
67a3744f | 1284 | u32 __fifo_ret = 0; \ |
f7000883 | 1285 | trace_i915_reg_rw(true, reg, val, sizeof(val)); \ |
a7cd1b8f | 1286 | spin_lock_irqsave(&dev_priv->gt_lock, irqflags); \ |
f7000883 | 1287 | if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ |
67a3744f | 1288 | __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \ |
f7000883 | 1289 | } \ |
a8b1397d DV |
1290 | if (IS_GEN5(dev_priv->dev)) \ |
1291 | ilk_dummy_write(dev_priv); \ | |
115bc2de | 1292 | hsw_unclaimed_reg_clear(dev_priv, reg); \ |
fe31b574 | 1293 | write##y(val, dev_priv->regs + reg); \ |
67a3744f BW |
1294 | if (unlikely(__fifo_ret)) { \ |
1295 | gen6_gt_check_fifodbg(dev_priv); \ | |
1296 | } \ | |
115bc2de | 1297 | hsw_unclaimed_reg_check(dev_priv, reg); \ |
a7cd1b8f | 1298 | spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); \ |
f7000883 AK |
1299 | } |
1300 | __i915_write(8, b) | |
1301 | __i915_write(16, w) | |
1302 | __i915_write(32, l) | |
1303 | __i915_write(64, q) | |
1304 | #undef __i915_write | |
c0c7babc BW |
1305 | |
1306 | static const struct register_whitelist { | |
1307 | uint64_t offset; | |
1308 | uint32_t size; | |
1309 | uint32_t gen_bitmask; /* support gens, 0x10 for 4, 0x30 for 4 and 5, etc. */ | |
1310 | } whitelist[] = { | |
1311 | { RING_TIMESTAMP(RENDER_RING_BASE), 8, 0xF0 }, | |
1312 | }; | |
1313 | ||
1314 | int i915_reg_read_ioctl(struct drm_device *dev, | |
1315 | void *data, struct drm_file *file) | |
1316 | { | |
1317 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1318 | struct drm_i915_reg_read *reg = data; | |
1319 | struct register_whitelist const *entry = whitelist; | |
1320 | int i; | |
1321 | ||
1322 | for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) { | |
1323 | if (entry->offset == reg->offset && | |
1324 | (1 << INTEL_INFO(dev)->gen & entry->gen_bitmask)) | |
1325 | break; | |
1326 | } | |
1327 | ||
1328 | if (i == ARRAY_SIZE(whitelist)) | |
1329 | return -EINVAL; | |
1330 | ||
1331 | switch (entry->size) { | |
1332 | case 8: | |
1333 | reg->val = I915_READ64(reg->offset); | |
1334 | break; | |
1335 | case 4: | |
1336 | reg->val = I915_READ(reg->offset); | |
1337 | break; | |
1338 | case 2: | |
1339 | reg->val = I915_READ16(reg->offset); | |
1340 | break; | |
1341 | case 1: | |
1342 | reg->val = I915_READ8(reg->offset); | |
1343 | break; | |
1344 | default: | |
1345 | WARN_ON(1); | |
1346 | return -EINVAL; | |
1347 | } | |
1348 | ||
1349 | return 0; | |
1350 | } |