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Merge branch 'for-airlied' of git://people.freedesktop.org/~danvet/drm-intel into...
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_drv.c
CommitLineData
1da177e4
LT		 1/* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
2 */
0d6aa60b 3/*
bc54fd1a 4 *
1da177e4
LT		 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
bc54fd1a
DA		 7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
0d6aa60b 28 */
1da177e4 29
5669fcac 30#include <linux/device.h>
1da177e4
LT		 31#include "drmP.h"
32#include "drm.h"
33#include "i915_drm.h"
34#include "i915_drv.h"
990bbdad 35#include "i915_trace.h"
f49f0586 36#include "intel_drv.h"
1da177e4 37
79e53945 38#include <linux/console.h>
e0cd3608 39#include <linux/module.h>
354ff967 40#include "drm_crtc_helper.h"
79e53945 41
a35d9d3c 42static int i915_modeset __read_mostly = -1;
79e53945 43module_param_named(modeset, i915_modeset, int, 0400);
6e96e775
BW		 44MODULE_PARM_DESC(modeset,
45 "Use kernel modesetting [KMS] (0=DRM_I915_KMS from .config, "
46 "1=on, -1=force vga console preference [default])");
79e53945 47
a35d9d3c 48unsigned int i915_fbpercrtc __always_unused = 0;
79e53945 49module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400);
1da177e4 50
a35d9d3c 51int i915_panel_ignore_lid __read_mostly = 0;
fca87409 52module_param_named(panel_ignore_lid, i915_panel_ignore_lid, int, 0600);
6e96e775
BW		 53MODULE_PARM_DESC(panel_ignore_lid,
54 "Override lid status (0=autodetect [default], 1=lid open, "
55 "-1=lid closed)");
fca87409 56
a35d9d3c 57unsigned int i915_powersave __read_mostly = 1;
0aa99277 58module_param_named(powersave, i915_powersave, int, 0600);
6e96e775
BW		 59MODULE_PARM_DESC(powersave,
60 "Enable powersavings, fbc, downclocking, etc. (default: true)");
652c393a 61
f45b5557 62int i915_semaphores __read_mostly = -1;
a1656b90 63module_param_named(semaphores, i915_semaphores, int, 0600);
6e96e775 64MODULE_PARM_DESC(semaphores,
f45b5557 65 "Use semaphores for inter-ring sync (default: -1 (use per-chip defaults))");
a1656b90 66
c0f372b3 67int i915_enable_rc6 __read_mostly = -1;
f57f9c16 68module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0400);
6e96e775 69MODULE_PARM_DESC(i915_enable_rc6,
83b7f9ac
ED		 70 "Enable power-saving render C-state 6. "
71 "Different stages can be selected via bitmask values "
72 "(0 = disable; 1 = enable rc6; 2 = enable deep rc6; 4 = enable deepest rc6). "
73 "For example, 3 would enable rc6 and deep rc6, and 7 would enable everything. "
74 "default: -1 (use per-chip default)");
ac668088 75
4415e63b 76int i915_enable_fbc __read_mostly = -1;
c1a9f047 77module_param_named(i915_enable_fbc, i915_enable_fbc, int, 0600);
6e96e775
BW		 78MODULE_PARM_DESC(i915_enable_fbc,
79 "Enable frame buffer compression for power savings "
cd0de039 80 "(default: -1 (use per-chip default))");
c1a9f047 81
a35d9d3c 82unsigned int i915_lvds_downclock __read_mostly = 0;
33814341 83module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400);
6e96e775
BW		 84MODULE_PARM_DESC(lvds_downclock,
85 "Use panel (LVDS/eDP) downclocking for power savings "
86 "(default: false)");
33814341 87
121d527a
TI		 88int i915_lvds_channel_mode __read_mostly;
89module_param_named(lvds_channel_mode, i915_lvds_channel_mode, int, 0600);
90MODULE_PARM_DESC(lvds_channel_mode,
91 "Specify LVDS channel mode "
92 "(0=probe BIOS [default], 1=single-channel, 2=dual-channel)");
93
4415e63b 94int i915_panel_use_ssc __read_mostly = -1;
a7615030 95module_param_named(lvds_use_ssc, i915_panel_use_ssc, int, 0600);
6e96e775
BW		 96MODULE_PARM_DESC(lvds_use_ssc,
97 "Use Spread Spectrum Clock with panels [LVDS/eDP] "
72bbe58c 98 "(default: auto from VBT)");
a7615030 99
a35d9d3c 100int i915_vbt_sdvo_panel_type __read_mostly = -1;
5a1e5b6c 101module_param_named(vbt_sdvo_panel_type, i915_vbt_sdvo_panel_type, int, 0600);
6e96e775 102MODULE_PARM_DESC(vbt_sdvo_panel_type,
c10e408a
MF		 103 "Override/Ignore selection of SDVO panel mode in the VBT "
104 "(-2=ignore, -1=auto [default], index in VBT BIOS table)");
5a1e5b6c 105
a35d9d3c 106static bool i915_try_reset __read_mostly = true;
d78cb50b 107module_param_named(reset, i915_try_reset, bool, 0600);
6e96e775 108MODULE_PARM_DESC(reset, "Attempt GPU resets (default: true)");
d78cb50b 109
a35d9d3c 110bool i915_enable_hangcheck __read_mostly = true;
3e0dc6b0 111module_param_named(enable_hangcheck, i915_enable_hangcheck, bool, 0644);
6e96e775
BW		 112MODULE_PARM_DESC(enable_hangcheck,
113 "Periodically check GPU activity for detecting hangs. "
114 "WARNING: Disabling this can cause system wide hangs. "
115 "(default: true)");
3e0dc6b0 116
650dc07e
DV		 117int i915_enable_ppgtt __read_mostly = -1;
118module_param_named(i915_enable_ppgtt, i915_enable_ppgtt, int, 0600);
e21af88d
DV		 119MODULE_PARM_DESC(i915_enable_ppgtt,
120 "Enable PPGTT (default: true)");
121
112b715e 122static struct drm_driver driver;
1f7a6e37 123extern int intel_agp_enabled;
112b715e 124
cfdf1fa2 125#define INTEL_VGA_DEVICE(id, info) { \
80a2901d 126 .class = PCI_BASE_CLASS_DISPLAY << 16, \
934f992c 127 .class_mask = 0xff0000, \
49ae35f2
KH		 128 .vendor = 0x8086, \
129 .device = id, \
130 .subvendor = PCI_ANY_ID, \
131 .subdevice = PCI_ANY_ID, \
cfdf1fa2
KH		 132 .driver_data = (unsigned long) info }
133
9a7e8492 134static const struct intel_device_info intel_i830_info = {
a6c45cf0 135 .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1,
31578148 136 .has_overlay = 1, .overlay_needs_physical = 1,
cfdf1fa2
KH		 137};
138
9a7e8492 139static const struct intel_device_info intel_845g_info = {
a6c45cf0 140 .gen = 2,
31578148 141 .has_overlay = 1, .overlay_needs_physical = 1,
cfdf1fa2
KH		 142};
143
9a7e8492 144static const struct intel_device_info intel_i85x_info = {
a6c45cf0 145 .gen = 2, .is_i85x = 1, .is_mobile = 1,
5ce8ba7c 146 .cursor_needs_physical = 1,
31578148 147 .has_overlay = 1, .overlay_needs_physical = 1,
cfdf1fa2
KH		 148};
149
9a7e8492 150static const struct intel_device_info intel_i865g_info = {
a6c45cf0 151 .gen = 2,
31578148 152 .has_overlay = 1, .overlay_needs_physical = 1,
cfdf1fa2
KH		 153};
154
9a7e8492 155static const struct intel_device_info intel_i915g_info = {
a6c45cf0 156 .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1,
31578148 157 .has_overlay = 1, .overlay_needs_physical = 1,
cfdf1fa2 158};
9a7e8492 159static const struct intel_device_info intel_i915gm_info = {
a6c45cf0 160 .gen = 3, .is_mobile = 1,
b295d1b6 161 .cursor_needs_physical = 1,
31578148 162 .has_overlay = 1, .overlay_needs_physical = 1,
a6c45cf0 163 .supports_tv = 1,
cfdf1fa2 164};
9a7e8492 165static const struct intel_device_info intel_i945g_info = {
a6c45cf0 166 .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1,
31578148 167 .has_overlay = 1, .overlay_needs_physical = 1,
cfdf1fa2 168};
9a7e8492 169static const struct intel_device_info intel_i945gm_info = {
a6c45cf0 170 .gen = 3, .is_i945gm = 1, .is_mobile = 1,
b295d1b6 171 .has_hotplug = 1, .cursor_needs_physical = 1,
31578148 172 .has_overlay = 1, .overlay_needs_physical = 1,
a6c45cf0 173 .supports_tv = 1,
cfdf1fa2
KH		 174};
175
9a7e8492 176static const struct intel_device_info intel_i965g_info = {
a6c45cf0 177 .gen = 4, .is_broadwater = 1,
c96c3a8c 178 .has_hotplug = 1,
31578148 179 .has_overlay = 1,
cfdf1fa2
KH		 180};
181
9a7e8492 182static const struct intel_device_info intel_i965gm_info = {
a6c45cf0 183 .gen = 4, .is_crestline = 1,
e3c4e5dd 184 .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
31578148 185 .has_overlay = 1,
a6c45cf0 186 .supports_tv = 1,
cfdf1fa2
KH		 187};
188
9a7e8492 189static const struct intel_device_info intel_g33_info = {
a6c45cf0 190 .gen = 3, .is_g33 = 1,
c96c3a8c 191 .need_gfx_hws = 1, .has_hotplug = 1,
31578148 192 .has_overlay = 1,
cfdf1fa2
KH		 193};
194
9a7e8492 195static const struct intel_device_info intel_g45_info = {
a6c45cf0 196 .gen = 4, .is_g4x = 1, .need_gfx_hws = 1,
c96c3a8c 197 .has_pipe_cxsr = 1, .has_hotplug = 1,
92f49d9c 198 .has_bsd_ring = 1,
cfdf1fa2
KH		 199};
200
9a7e8492 201static const struct intel_device_info intel_gm45_info = {
a6c45cf0 202 .gen = 4, .is_g4x = 1,
e3c4e5dd 203 .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
c96c3a8c 204 .has_pipe_cxsr = 1, .has_hotplug = 1,
a6c45cf0 205 .supports_tv = 1,
92f49d9c 206 .has_bsd_ring = 1,
cfdf1fa2
KH		 207};
208
9a7e8492 209static const struct intel_device_info intel_pineview_info = {
a6c45cf0 210 .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1,
c96c3a8c 211 .need_gfx_hws = 1, .has_hotplug = 1,
31578148 212 .has_overlay = 1,
cfdf1fa2
KH		 213};
214
9a7e8492 215static const struct intel_device_info intel_ironlake_d_info = {
f00a3ddf 216 .gen = 5,
5a117db7 217 .need_gfx_hws = 1, .has_hotplug = 1,
92f49d9c 218 .has_bsd_ring = 1,
cfdf1fa2
KH		 219};
220
9a7e8492 221static const struct intel_device_info intel_ironlake_m_info = {
f00a3ddf 222 .gen = 5, .is_mobile = 1,
e3c4e5dd 223 .need_gfx_hws = 1, .has_hotplug = 1,
c1a9f047 224 .has_fbc = 1,
92f49d9c 225 .has_bsd_ring = 1,
cfdf1fa2
KH		 226};
227
9a7e8492 228static const struct intel_device_info intel_sandybridge_d_info = {
a6c45cf0 229 .gen = 6,
c96c3a8c 230 .need_gfx_hws = 1, .has_hotplug = 1,
881f47b6 231 .has_bsd_ring = 1,
549f7365 232 .has_blt_ring = 1,
3d29b842 233 .has_llc = 1,
b7884eb4 234 .has_force_wake = 1,
f6e450a6
EA		 235};
236
9a7e8492 237static const struct intel_device_info intel_sandybridge_m_info = {
a6c45cf0 238 .gen = 6, .is_mobile = 1,
c96c3a8c 239 .need_gfx_hws = 1, .has_hotplug = 1,
9c04f015 240 .has_fbc = 1,
881f47b6 241 .has_bsd_ring = 1,
549f7365 242 .has_blt_ring = 1,
3d29b842 243 .has_llc = 1,
b7884eb4 244 .has_force_wake = 1,
a13e4093
EA		 245};
246
c76b615c
JB		 247static const struct intel_device_info intel_ivybridge_d_info = {
248 .is_ivybridge = 1, .gen = 7,
249 .need_gfx_hws = 1, .has_hotplug = 1,
250 .has_bsd_ring = 1,
251 .has_blt_ring = 1,
3d29b842 252 .has_llc = 1,
b7884eb4 253 .has_force_wake = 1,
c76b615c
JB		 254};
255
256static const struct intel_device_info intel_ivybridge_m_info = {
257 .is_ivybridge = 1, .gen = 7, .is_mobile = 1,
258 .need_gfx_hws = 1, .has_hotplug = 1,
259 .has_fbc = 0, /* FBC is not enabled on Ivybridge mobile yet */
260 .has_bsd_ring = 1,
261 .has_blt_ring = 1,
3d29b842 262 .has_llc = 1,
b7884eb4 263 .has_force_wake = 1,
c76b615c
JB		 264};
265
70a3eb7a
JB		 266static const struct intel_device_info intel_valleyview_m_info = {
267 .gen = 7, .is_mobile = 1,
268 .need_gfx_hws = 1, .has_hotplug = 1,
269 .has_fbc = 0,
270 .has_bsd_ring = 1,
271 .has_blt_ring = 1,
272 .is_valleyview = 1,
273};
274
275static const struct intel_device_info intel_valleyview_d_info = {
276 .gen = 7,
277 .need_gfx_hws = 1, .has_hotplug = 1,
278 .has_fbc = 0,
279 .has_bsd_ring = 1,
280 .has_blt_ring = 1,
281 .is_valleyview = 1,
282};
283
4cae9ae0
ED		 284static const struct intel_device_info intel_haswell_d_info = {
285 .is_haswell = 1, .gen = 7,
286 .need_gfx_hws = 1, .has_hotplug = 1,
287 .has_bsd_ring = 1,
288 .has_blt_ring = 1,
289 .has_llc = 1,
b7884eb4 290 .has_force_wake = 1,
4cae9ae0
ED		 291};
292
293static const struct intel_device_info intel_haswell_m_info = {
294 .is_haswell = 1, .gen = 7, .is_mobile = 1,
295 .need_gfx_hws = 1, .has_hotplug = 1,
296 .has_bsd_ring = 1,
297 .has_blt_ring = 1,
298 .has_llc = 1,
b7884eb4 299 .has_force_wake = 1,
c76b615c
JB		 300};
301
6103da0d
CW		 302static const struct pci_device_id pciidlist[] = { /* aka */
303 INTEL_VGA_DEVICE(0x3577, &intel_i830_info), /* I830_M */
304 INTEL_VGA_DEVICE(0x2562, &intel_845g_info), /* 845_G */
305 INTEL_VGA_DEVICE(0x3582, &intel_i85x_info), /* I855_GM */
5ce8ba7c 306 INTEL_VGA_DEVICE(0x358e, &intel_i85x_info),
6103da0d
CW		 307 INTEL_VGA_DEVICE(0x2572, &intel_i865g_info), /* I865_G */
308 INTEL_VGA_DEVICE(0x2582, &intel_i915g_info), /* I915_G */
309 INTEL_VGA_DEVICE(0x258a, &intel_i915g_info), /* E7221_G */
310 INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info), /* I915_GM */
311 INTEL_VGA_DEVICE(0x2772, &intel_i945g_info), /* I945_G */
312 INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info), /* I945_GM */
313 INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info), /* I945_GME */
314 INTEL_VGA_DEVICE(0x2972, &intel_i965g_info), /* I946_GZ */
315 INTEL_VGA_DEVICE(0x2982, &intel_i965g_info), /* G35_G */
316 INTEL_VGA_DEVICE(0x2992, &intel_i965g_info), /* I965_Q */
317 INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info), /* I965_G */
318 INTEL_VGA_DEVICE(0x29b2, &intel_g33_info), /* Q35_G */
319 INTEL_VGA_DEVICE(0x29c2, &intel_g33_info), /* G33_G */
320 INTEL_VGA_DEVICE(0x29d2, &intel_g33_info), /* Q33_G */
321 INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info), /* I965_GM */
322 INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info), /* I965_GME */
323 INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info), /* GM45_G */
324 INTEL_VGA_DEVICE(0x2e02, &intel_g45_info), /* IGD_E_G */
325 INTEL_VGA_DEVICE(0x2e12, &intel_g45_info), /* Q45_G */
326 INTEL_VGA_DEVICE(0x2e22, &intel_g45_info), /* G45_G */
327 INTEL_VGA_DEVICE(0x2e32, &intel_g45_info), /* G41_G */
328 INTEL_VGA_DEVICE(0x2e42, &intel_g45_info), /* B43_G */
41a51428 329 INTEL_VGA_DEVICE(0x2e92, &intel_g45_info), /* B43_G.1 */
cfdf1fa2
KH		 330 INTEL_VGA_DEVICE(0xa001, &intel_pineview_info),
331 INTEL_VGA_DEVICE(0xa011, &intel_pineview_info),
332 INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info),
333 INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info),
f6e450a6 334 INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info),
85540480
ZW		 335 INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info),
336 INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info),
a13e4093 337 INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info),
85540480 338 INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info),
4fefe435 339 INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info),
85540480 340 INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info),
c76b615c
JB		 341 INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info), /* GT1 mobile */
342 INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info), /* GT2 mobile */
343 INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */
344 INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */
345 INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */
cc22a938 346 INTEL_VGA_DEVICE(0x016a, &intel_ivybridge_d_info), /* GT2 server */
c14f5286
ED		 347 INTEL_VGA_DEVICE(0x0402, &intel_haswell_d_info), /* GT1 desktop */
348 INTEL_VGA_DEVICE(0x0412, &intel_haswell_d_info), /* GT2 desktop */
da612d88 349 INTEL_VGA_DEVICE(0x0422, &intel_haswell_d_info), /* GT2 desktop */
c14f5286
ED		 350 INTEL_VGA_DEVICE(0x040a, &intel_haswell_d_info), /* GT1 server */
351 INTEL_VGA_DEVICE(0x041a, &intel_haswell_d_info), /* GT2 server */
da612d88 352 INTEL_VGA_DEVICE(0x042a, &intel_haswell_d_info), /* GT2 server */
c14f5286
ED		 353 INTEL_VGA_DEVICE(0x0406, &intel_haswell_m_info), /* GT1 mobile */
354 INTEL_VGA_DEVICE(0x0416, &intel_haswell_m_info), /* GT2 mobile */
da612d88
PZ		 355 INTEL_VGA_DEVICE(0x0426, &intel_haswell_m_info), /* GT2 mobile */
356 INTEL_VGA_DEVICE(0x0C02, &intel_haswell_d_info), /* SDV GT1 desktop */
357 INTEL_VGA_DEVICE(0x0C12, &intel_haswell_d_info), /* SDV GT2 desktop */
358 INTEL_VGA_DEVICE(0x0C22, &intel_haswell_d_info), /* SDV GT2 desktop */
359 INTEL_VGA_DEVICE(0x0C0A, &intel_haswell_d_info), /* SDV GT1 server */
360 INTEL_VGA_DEVICE(0x0C1A, &intel_haswell_d_info), /* SDV GT2 server */
361 INTEL_VGA_DEVICE(0x0C2A, &intel_haswell_d_info), /* SDV GT2 server */
362 INTEL_VGA_DEVICE(0x0C06, &intel_haswell_m_info), /* SDV GT1 mobile */
363 INTEL_VGA_DEVICE(0x0C16, &intel_haswell_m_info), /* SDV GT2 mobile */
364 INTEL_VGA_DEVICE(0x0C26, &intel_haswell_m_info), /* SDV GT2 mobile */
365 INTEL_VGA_DEVICE(0x0A02, &intel_haswell_d_info), /* ULT GT1 desktop */
366 INTEL_VGA_DEVICE(0x0A12, &intel_haswell_d_info), /* ULT GT2 desktop */
367 INTEL_VGA_DEVICE(0x0A22, &intel_haswell_d_info), /* ULT GT2 desktop */
368 INTEL_VGA_DEVICE(0x0A0A, &intel_haswell_d_info), /* ULT GT1 server */
369 INTEL_VGA_DEVICE(0x0A1A, &intel_haswell_d_info), /* ULT GT2 server */
370 INTEL_VGA_DEVICE(0x0A2A, &intel_haswell_d_info), /* ULT GT2 server */
371 INTEL_VGA_DEVICE(0x0A06, &intel_haswell_m_info), /* ULT GT1 mobile */
372 INTEL_VGA_DEVICE(0x0A16, &intel_haswell_m_info), /* ULT GT2 mobile */
373 INTEL_VGA_DEVICE(0x0A26, &intel_haswell_m_info), /* ULT GT2 mobile */
374 INTEL_VGA_DEVICE(0x0D12, &intel_haswell_d_info), /* CRW GT1 desktop */
375 INTEL_VGA_DEVICE(0x0D22, &intel_haswell_d_info), /* CRW GT2 desktop */
376 INTEL_VGA_DEVICE(0x0D32, &intel_haswell_d_info), /* CRW GT2 desktop */
377 INTEL_VGA_DEVICE(0x0D1A, &intel_haswell_d_info), /* CRW GT1 server */
378 INTEL_VGA_DEVICE(0x0D2A, &intel_haswell_d_info), /* CRW GT2 server */
379 INTEL_VGA_DEVICE(0x0D3A, &intel_haswell_d_info), /* CRW GT2 server */
380 INTEL_VGA_DEVICE(0x0D16, &intel_haswell_m_info), /* CRW GT1 mobile */
381 INTEL_VGA_DEVICE(0x0D26, &intel_haswell_m_info), /* CRW GT2 mobile */
382 INTEL_VGA_DEVICE(0x0D36, &intel_haswell_m_info), /* CRW GT2 mobile */
ff049b6c
JB		 383 INTEL_VGA_DEVICE(0x0f30, &intel_valleyview_m_info),
384 INTEL_VGA_DEVICE(0x0157, &intel_valleyview_m_info),
385 INTEL_VGA_DEVICE(0x0155, &intel_valleyview_d_info),
49ae35f2 386 {0, 0, 0}
1da177e4
LT		 387};
388
79e53945
JB		 389#if defined(CONFIG_DRM_I915_KMS)
390MODULE_DEVICE_TABLE(pci, pciidlist);
391#endif
392
3bad0781 393#define INTEL_PCH_DEVICE_ID_MASK 0xff00
90711d50 394#define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
3bad0781 395#define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
c792513b 396#define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
eb877ebf 397#define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
3bad0781 398
0206e353 399void intel_detect_pch(struct drm_device *dev)
3bad0781
ZW		 400{
401 struct drm_i915_private *dev_priv = dev->dev_private;
402 struct pci_dev *pch;
403
404 /*
405 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
406 * make graphics device passthrough work easy for VMM, that only
407 * need to expose ISA bridge to let driver know the real hardware
408 * underneath. This is a requirement from virtualization team.
409 */
410 pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
411 if (pch) {
412 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
413 int id;
414 id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
415
90711d50
JB		 416 if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
417 dev_priv->pch_type = PCH_IBX;
ee7b9f93 418 dev_priv->num_pch_pll = 2;
90711d50
JB		 419 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
420 } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
3bad0781 421 dev_priv->pch_type = PCH_CPT;
ee7b9f93 422 dev_priv->num_pch_pll = 2;
3bad0781 423 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
c792513b
JB		 424 } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
425 /* PantherPoint is CPT compatible */
426 dev_priv->pch_type = PCH_CPT;
ee7b9f93 427 dev_priv->num_pch_pll = 2;
c792513b 428 DRM_DEBUG_KMS("Found PatherPoint PCH\n");
eb877ebf
ED		 429 } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
430 dev_priv->pch_type = PCH_LPT;
ee7b9f93 431 dev_priv->num_pch_pll = 0;
eb877ebf 432 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
3bad0781 433 }
ee7b9f93 434 BUG_ON(dev_priv->num_pch_pll > I915_NUM_PLLS);
3bad0781
ZW		 435 }
436 pci_dev_put(pch);
437 }
438}
439
2911a35b
BW		 440bool i915_semaphore_is_enabled(struct drm_device *dev)
441{
442 if (INTEL_INFO(dev)->gen < 6)
443 return 0;
444
445 if (i915_semaphores >= 0)
446 return i915_semaphores;
447
59de3295 448#ifdef CONFIG_INTEL_IOMMU
2911a35b 449 /* Enable semaphores on SNB when IO remapping is off */
59de3295
DV		 450 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
451 return false;
452#endif
2911a35b
BW		 453
454 return 1;
455}
456
84b79f8d 457static int i915_drm_freeze(struct drm_device *dev)
ba8bbcf6 458{
61caf87c
RW		 459 struct drm_i915_private *dev_priv = dev->dev_private;
460
5bcf719b
DA		 461 drm_kms_helper_poll_disable(dev);
462
ba8bbcf6 463 pci_save_state(dev->pdev);
ba8bbcf6 464
5669fcac 465 /* If KMS is active, we do the leavevt stuff here */
226485e9 466 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
84b79f8d
RW		 467 int error = i915_gem_idle(dev);
468 if (error) {
226485e9 469 dev_err(&dev->pdev->dev,
84b79f8d
RW		 470 "GEM idle failed, resume might fail\n");
471 return error;
472 }
a261b246
DV		 473
474 intel_modeset_disable(dev);
475
226485e9 476 drm_irq_uninstall(dev);
5669fcac
JB		 477 }
478
9e06dd39
JB		 479 i915_save_state(dev);
480
44834a67 481 intel_opregion_fini(dev);
8ee1c3db 482
84b79f8d
RW		 483 /* Modeset on resume, not lid events */
484 dev_priv->modeset_on_lid = 0;
61caf87c 485
3fa016a0
DA		 486 console_lock();
487 intel_fbdev_set_suspend(dev, 1);
488 console_unlock();
489
61caf87c 490 return 0;
84b79f8d
RW		 491}
492
6a9ee8af 493int i915_suspend(struct drm_device *dev, pm_message_t state)
84b79f8d
RW		 494{
495 int error;
496
497 if (!dev || !dev->dev_private) {
498 DRM_ERROR("dev: %p\n", dev);
499 DRM_ERROR("DRM not initialized, aborting suspend.\n");
500 return -ENODEV;
501 }
502
503 if (state.event == PM_EVENT_PRETHAW)
504 return 0;
505
5bcf719b
DA		 506
507 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
508 return 0;
6eecba33 509
84b79f8d
RW		 510 error = i915_drm_freeze(dev);
511 if (error)
512 return error;
513
b932ccb5
DA		 514 if (state.event == PM_EVENT_SUSPEND) {
515 /* Shut down the device */
516 pci_disable_device(dev->pdev);
517 pci_set_power_state(dev->pdev, PCI_D3hot);
518 }
ba8bbcf6
JB		 519
520 return 0;
521}
522
84b79f8d 523static int i915_drm_thaw(struct drm_device *dev)
ba8bbcf6 524{
5669fcac 525 struct drm_i915_private *dev_priv = dev->dev_private;
84b79f8d 526 int error = 0;
8ee1c3db 527
d1c3b177
CW		 528 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
529 mutex_lock(&dev->struct_mutex);
530 i915_gem_restore_gtt_mappings(dev);
531 mutex_unlock(&dev->struct_mutex);
532 }
533
61caf87c 534 i915_restore_state(dev);
44834a67 535 intel_opregion_setup(dev);
61caf87c 536
5669fcac
JB		 537 /* KMS EnterVT equivalent */
538 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
40579abe 539 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
1833b134
CW		 540 ironlake_init_pch_refclk(dev);
541
5669fcac
JB		 542 mutex_lock(&dev->struct_mutex);
543 dev_priv->mm.suspended = 0;
544
f691e2f4 545 error = i915_gem_init_hw(dev);
5669fcac 546 mutex_unlock(&dev->struct_mutex);
226485e9 547
1833b134 548 intel_modeset_init_hw(dev);
24929352 549 intel_modeset_setup_hw_state(dev);
500f7147 550 drm_mode_config_reset(dev);
226485e9 551 drm_irq_install(dev);
d5bb081b 552 }
1daed3fb 553
44834a67
CW		 554 intel_opregion_init(dev);
555
c9354c85 556 dev_priv->modeset_on_lid = 0;
06891e27 557
3fa016a0
DA		 558 console_lock();
559 intel_fbdev_set_suspend(dev, 0);
560 console_unlock();
84b79f8d
RW		 561 return error;
562}
563
6a9ee8af 564int i915_resume(struct drm_device *dev)
84b79f8d 565{
6eecba33
CW		 566 int ret;
567
5bcf719b
DA		 568 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
569 return 0;
570
84b79f8d
RW		 571 if (pci_enable_device(dev->pdev))
572 return -EIO;
573
574 pci_set_master(dev->pdev);
575
6eecba33
CW		 576 ret = i915_drm_thaw(dev);
577 if (ret)
578 return ret;
579
580 drm_kms_helper_poll_enable(dev);
581 return 0;
ba8bbcf6
JB		 582}
583
d4b8bb2a 584static int i8xx_do_reset(struct drm_device *dev)
dc96e9b8
CW		 585{
586 struct drm_i915_private *dev_priv = dev->dev_private;
587
588 if (IS_I85X(dev))
589 return -ENODEV;
590
591 I915_WRITE(D_STATE, I915_READ(D_STATE) | DSTATE_GFX_RESET_I830);
592 POSTING_READ(D_STATE);
593
594 if (IS_I830(dev) || IS_845G(dev)) {
595 I915_WRITE(DEBUG_RESET_I830,
596 DEBUG_RESET_DISPLAY |
597 DEBUG_RESET_RENDER |
598 DEBUG_RESET_FULL);
599 POSTING_READ(DEBUG_RESET_I830);
600 msleep(1);
601
602 I915_WRITE(DEBUG_RESET_I830, 0);
603 POSTING_READ(DEBUG_RESET_I830);
604 }
605
606 msleep(1);
607
608 I915_WRITE(D_STATE, I915_READ(D_STATE) & ~DSTATE_GFX_RESET_I830);
609 POSTING_READ(D_STATE);
610
611 return 0;
612}
613
f49f0586
KG		 614static int i965_reset_complete(struct drm_device *dev)
615{
616 u8 gdrst;
eeccdcac 617 pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
5fe9fe8c 618 return (gdrst & GRDOM_RESET_ENABLE) == 0;
f49f0586
KG		 619}
620
d4b8bb2a 621static int i965_do_reset(struct drm_device *dev)
0573ed4a 622{
5ccce180 623 int ret;
0573ed4a
KG		 624 u8 gdrst;
625
ae681d96
CW		 626 /*
627 * Set the domains we want to reset (GRDOM/bits 2 and 3) as
628 * well as the reset bit (GR/bit 0). Setting the GR bit
629 * triggers the reset; when done, the hardware will clear it.
630 */
0573ed4a 631 pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
d4b8bb2a 632 pci_write_config_byte(dev->pdev, I965_GDRST,
5ccce180
DV		 633 gdrst | GRDOM_RENDER |
634 GRDOM_RESET_ENABLE);
635 ret = wait_for(i965_reset_complete(dev), 500);
636 if (ret)
637 return ret;
638
639 /* We can't reset render&media without also resetting display ... */
640 pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
641 pci_write_config_byte(dev->pdev, I965_GDRST,
642 gdrst | GRDOM_MEDIA |
643 GRDOM_RESET_ENABLE);
0573ed4a
KG		 644
645 return wait_for(i965_reset_complete(dev), 500);
646}
647
d4b8bb2a 648static int ironlake_do_reset(struct drm_device *dev)
0573ed4a
KG		 649{
650 struct drm_i915_private *dev_priv = dev->dev_private;
5ccce180
DV		 651 u32 gdrst;
652 int ret;
653
654 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
655 I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
656 gdrst | GRDOM_RENDER | GRDOM_RESET_ENABLE);
657 ret = wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
658 if (ret)
659 return ret;
660
661 /* We can't reset render&media without also resetting display ... */
662 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
d4b8bb2a 663 I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
5ccce180 664 gdrst | GRDOM_MEDIA | GRDOM_RESET_ENABLE);
0573ed4a 665 return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
ba8bbcf6
JB		 666}
667
d4b8bb2a 668static int gen6_do_reset(struct drm_device *dev)
cff458c2
EA		 669{
670 struct drm_i915_private *dev_priv = dev->dev_private;
b6e45f86
KP		 671 int ret;
672 unsigned long irqflags;
cff458c2 673
286fed41
KP		 674 /* Hold gt_lock across reset to prevent any register access
675 * with forcewake not set correctly
676 */
b6e45f86 677 spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
286fed41
KP		 678
679 /* Reset the chip */
680
681 /* GEN6_GDRST is not in the gt power well, no need to check
682 * for fifo space for the write or forcewake the chip for
683 * the read
684 */
685 I915_WRITE_NOTRACE(GEN6_GDRST, GEN6_GRDOM_FULL);
686
687 /* Spin waiting for the device to ack the reset request */
688 ret = wait_for((I915_READ_NOTRACE(GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500);
689
690 /* If reset with a user forcewake, try to restore, otherwise turn it off */
b6e45f86 691 if (dev_priv->forcewake_count)
990bbdad 692 dev_priv->gt.force_wake_get(dev_priv);
286fed41 693 else
990bbdad 694 dev_priv->gt.force_wake_put(dev_priv);
286fed41
KP		 695
696 /* Restore fifo count */
697 dev_priv->gt_fifo_count = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
698
b6e45f86
KP		 699 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
700 return ret;
cff458c2
EA		 701}
702
8e96d9c4 703int intel_gpu_reset(struct drm_device *dev)
350d2706 704{
2b9dc9a2 705 struct drm_i915_private *dev_priv = dev->dev_private;
350d2706
DV		 706 int ret = -ENODEV;
707
708 switch (INTEL_INFO(dev)->gen) {
709 case 7:
710 case 6:
d4b8bb2a 711 ret = gen6_do_reset(dev);
350d2706
DV		 712 break;
713 case 5:
d4b8bb2a 714 ret = ironlake_do_reset(dev);
350d2706
DV		 715 break;
716 case 4:
d4b8bb2a 717 ret = i965_do_reset(dev);
350d2706
DV		 718 break;
719 case 2:
d4b8bb2a 720 ret = i8xx_do_reset(dev);
350d2706
DV		 721 break;
722 }
723
2b9dc9a2
DV		 724 /* Also reset the gpu hangman. */
725 if (dev_priv->stop_rings) {
726 DRM_DEBUG("Simulated gpu hang, resetting stop_rings\n");
727 dev_priv->stop_rings = 0;
728 if (ret == -ENODEV) {
729 DRM_ERROR("Reset not implemented, but ignoring "
730 "error for simulated gpu hangs\n");
731 ret = 0;
732 }
733 }
734
350d2706
DV		 735 return ret;
736}
737
11ed50ec 738/**
f3953dcb 739 * i915_reset - reset chip after a hang
11ed50ec 740 * @dev: drm device to reset
11ed50ec
BG		 741 *
742 * Reset the chip. Useful if a hang is detected. Returns zero on successful
743 * reset or otherwise an error code.
744 *
745 * Procedure is fairly simple:
746 * - reset the chip using the reset reg
747 * - re-init context state
748 * - re-init hardware status page
749 * - re-init ring buffer
750 * - re-init interrupt state
751 * - re-init display
752 */
d4b8bb2a 753int i915_reset(struct drm_device *dev)
11ed50ec
BG		 754{
755 drm_i915_private_t *dev_priv = dev->dev_private;
0573ed4a 756 int ret;
11ed50ec 757
d78cb50b
CW		 758 if (!i915_try_reset)
759 return 0;
760
d54a02c0 761 mutex_lock(&dev->struct_mutex);
11ed50ec 762
069efc1d 763 i915_gem_reset(dev);
77f01230 764
f803aa55 765 ret = -ENODEV;
350d2706 766 if (get_seconds() - dev_priv->last_gpu_reset < 5)
ae681d96 767 DRM_ERROR("GPU hanging too fast, declaring wedged!\n");
350d2706 768 else
d4b8bb2a 769 ret = intel_gpu_reset(dev);
350d2706 770
ae681d96 771 dev_priv->last_gpu_reset = get_seconds();
0573ed4a 772 if (ret) {
f803aa55 773 DRM_ERROR("Failed to reset chip.\n");
f953c935 774 mutex_unlock(&dev->struct_mutex);
f803aa55 775 return ret;
11ed50ec
BG		 776 }
777
778 /* Ok, now get things going again... */
779
780 /*
781 * Everything depends on having the GTT running, so we need to start
782 * there. Fortunately we don't need to do this unless we reset the
783 * chip at a PCI level.
784 *
785 * Next we need to restore the context, but we don't use those
786 * yet either...
787 *
788 * Ring buffer needs to be re-initialized in the KMS case, or if X
789 * was running at the time of the reset (i.e. we weren't VT
790 * switched away).
791 */
792 if (drm_core_check_feature(dev, DRIVER_MODESET) ||
8187a2b7 793 !dev_priv->mm.suspended) {
b4519513
CW		 794 struct intel_ring_buffer *ring;
795 int i;
796
11ed50ec 797 dev_priv->mm.suspended = 0;
75a6898f 798
f691e2f4
DV		 799 i915_gem_init_swizzling(dev);
800
b4519513
CW		 801 for_each_ring(ring, dev_priv, i)
802 ring->init(ring);
75a6898f 803
254f965c 804 i915_gem_context_init(dev);
e21af88d
DV		 805 i915_gem_init_ppgtt(dev);
806
8e88a2bd
DV		 807 /*
808 * It would make sense to re-init all the other hw state, at
809 * least the rps/rc6/emon init done within modeset_init_hw. For
810 * some unknown reason, this blows up my ilk, so don't.
811 */
f817586c 812
8e88a2bd 813 mutex_unlock(&dev->struct_mutex);
f817586c 814
11ed50ec
BG		 815 drm_irq_uninstall(dev);
816 drm_irq_install(dev);
bcbc324a
DV		 817 } else {
818 mutex_unlock(&dev->struct_mutex);
11ed50ec
BG		 819 }
820
11ed50ec
BG		 821 return 0;
822}
823
112b715e
KH		 824static int __devinit
825i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
826{
01a06850
DV		 827 struct intel_device_info *intel_info =
828 (struct intel_device_info *) ent->driver_data;
829
5fe49d86
CW		 830 /* Only bind to function 0 of the device. Early generations
831 * used function 1 as a placeholder for multi-head. This causes
832 * us confusion instead, especially on the systems where both
833 * functions have the same PCI-ID!
834 */
835 if (PCI_FUNC(pdev->devfn))
836 return -ENODEV;
837
01a06850
DV		 838 /* We've managed to ship a kms-enabled ddx that shipped with an XvMC
839 * implementation for gen3 (and only gen3) that used legacy drm maps
840 * (gasp!) to share buffers between X and the client. Hence we need to
841 * keep around the fake agp stuff for gen3, even when kms is enabled. */
842 if (intel_info->gen != 3) {
843 driver.driver_features &=
844 ~(DRIVER_USE_AGP | DRIVER_REQUIRE_AGP);
845 } else if (!intel_agp_enabled) {
846 DRM_ERROR("drm/i915 can't work without intel_agp module!\n");
847 return -ENODEV;
848 }
849
dcdb1674 850 return drm_get_pci_dev(pdev, ent, &driver);
112b715e
KH		 851}
852
853static void
854i915_pci_remove(struct pci_dev *pdev)
855{
856 struct drm_device *dev = pci_get_drvdata(pdev);
857
858 drm_put_dev(dev);
859}
860
84b79f8d 861static int i915_pm_suspend(struct device *dev)
112b715e 862{
84b79f8d
RW		 863 struct pci_dev *pdev = to_pci_dev(dev);
864 struct drm_device *drm_dev = pci_get_drvdata(pdev);
865 int error;
112b715e 866
84b79f8d
RW		 867 if (!drm_dev || !drm_dev->dev_private) {
868 dev_err(dev, "DRM not initialized, aborting suspend.\n");
869 return -ENODEV;
870 }
112b715e 871
5bcf719b
DA		 872 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
873 return 0;
874
84b79f8d
RW		 875 error = i915_drm_freeze(drm_dev);
876 if (error)
877 return error;
112b715e 878
84b79f8d
RW		 879 pci_disable_device(pdev);
880 pci_set_power_state(pdev, PCI_D3hot);
cbda12d7 881
84b79f8d 882 return 0;
cbda12d7
ZW		 883}
884
84b79f8d 885static int i915_pm_resume(struct device *dev)
cbda12d7 886{
84b79f8d
RW		 887 struct pci_dev *pdev = to_pci_dev(dev);
888 struct drm_device *drm_dev = pci_get_drvdata(pdev);
889
890 return i915_resume(drm_dev);
cbda12d7
ZW		 891}
892
84b79f8d 893static int i915_pm_freeze(struct device *dev)
cbda12d7 894{
84b79f8d
RW		 895 struct pci_dev *pdev = to_pci_dev(dev);
896 struct drm_device *drm_dev = pci_get_drvdata(pdev);
897
898 if (!drm_dev || !drm_dev->dev_private) {
899 dev_err(dev, "DRM not initialized, aborting suspend.\n");
900 return -ENODEV;
901 }
902
903 return i915_drm_freeze(drm_dev);
cbda12d7
ZW		 904}
905
84b79f8d 906static int i915_pm_thaw(struct device *dev)
cbda12d7 907{
84b79f8d
RW		 908 struct pci_dev *pdev = to_pci_dev(dev);
909 struct drm_device *drm_dev = pci_get_drvdata(pdev);
910
911 return i915_drm_thaw(drm_dev);
cbda12d7
ZW		 912}
913
84b79f8d 914static int i915_pm_poweroff(struct device *dev)
cbda12d7 915{
84b79f8d
RW		 916 struct pci_dev *pdev = to_pci_dev(dev);
917 struct drm_device *drm_dev = pci_get_drvdata(pdev);
84b79f8d 918
61caf87c 919 return i915_drm_freeze(drm_dev);
cbda12d7
ZW		 920}
921
b4b78d12 922static const struct dev_pm_ops i915_pm_ops = {
0206e353
AJ		 923 .suspend = i915_pm_suspend,
924 .resume = i915_pm_resume,
925 .freeze = i915_pm_freeze,
926 .thaw = i915_pm_thaw,
927 .poweroff = i915_pm_poweroff,
928 .restore = i915_pm_resume,
cbda12d7
ZW		 929};
930
78b68556 931static const struct vm_operations_struct i915_gem_vm_ops = {
de151cf6 932 .fault = i915_gem_fault,
ab00b3e5
JB		 933 .open = drm_gem_vm_open,
934 .close = drm_gem_vm_close,
de151cf6
JB		 935};
936
e08e96de
AV		 937static const struct file_operations i915_driver_fops = {
938 .owner = THIS_MODULE,
939 .open = drm_open,
940 .release = drm_release,
941 .unlocked_ioctl = drm_ioctl,
942 .mmap = drm_gem_mmap,
943 .poll = drm_poll,
944 .fasync = drm_fasync,
945 .read = drm_read,
946#ifdef CONFIG_COMPAT
947 .compat_ioctl = i915_compat_ioctl,
948#endif
949 .llseek = noop_llseek,
950};
951
1da177e4 952static struct drm_driver driver = {
0c54781b
MW		 953 /* Don't use MTRRs here; the Xserver or userspace app should
954 * deal with them for Intel hardware.
792d2b9a 955 */
673a394b
EA		 956 .driver_features =
957 DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR |*/
1286ff73 958 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME,
22eae947 959 .load = i915_driver_load,
ba8bbcf6 960 .unload = i915_driver_unload,
673a394b 961 .open = i915_driver_open,
22eae947
DA		 962 .lastclose = i915_driver_lastclose,
963 .preclose = i915_driver_preclose,
673a394b 964 .postclose = i915_driver_postclose,
d8e29209
RW		 965
966 /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
967 .suspend = i915_suspend,
968 .resume = i915_resume,
969
cda17380 970 .device_is_agp = i915_driver_device_is_agp,
7c1c2871
DA		 971 .master_create = i915_master_create,
972 .master_destroy = i915_master_destroy,
955b12de 973#if defined(CONFIG_DEBUG_FS)
27c202ad
BG		 974 .debugfs_init = i915_debugfs_init,
975 .debugfs_cleanup = i915_debugfs_cleanup,
955b12de 976#endif
673a394b
EA		 977 .gem_init_object = i915_gem_init_object,
978 .gem_free_object = i915_gem_free_object,
de151cf6 979 .gem_vm_ops = &i915_gem_vm_ops,
1286ff73
DV		 980
981 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
982 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
983 .gem_prime_export = i915_gem_prime_export,
984 .gem_prime_import = i915_gem_prime_import,
985
ff72145b
DA		 986 .dumb_create = i915_gem_dumb_create,
987 .dumb_map_offset = i915_gem_mmap_gtt,
988 .dumb_destroy = i915_gem_dumb_destroy,
1da177e4 989 .ioctls = i915_ioctls,
e08e96de 990 .fops = &i915_driver_fops,
22eae947
DA		 991 .name = DRIVER_NAME,
992 .desc = DRIVER_DESC,
993 .date = DRIVER_DATE,
994 .major = DRIVER_MAJOR,
995 .minor = DRIVER_MINOR,
996 .patchlevel = DRIVER_PATCHLEVEL,
1da177e4
LT		 997};
998
8410ea3b
DA		 999static struct pci_driver i915_pci_driver = {
1000 .name = DRIVER_NAME,
1001 .id_table = pciidlist,
1002 .probe = i915_pci_probe,
1003 .remove = i915_pci_remove,
1004 .driver.pm = &i915_pm_ops,
1005};
1006
1da177e4
LT		 1007static int __init i915_init(void)
1008{
1009 driver.num_ioctls = i915_max_ioctl;
79e53945
JB		 1010
1011 /*
1012 * If CONFIG_DRM_I915_KMS is set, default to KMS unless
1013 * explicitly disabled with the module pararmeter.
1014 *
1015 * Otherwise, just follow the parameter (defaulting to off).
1016 *
1017 * Allow optional vga_text_mode_force boot option to override
1018 * the default behavior.
1019 */
1020#if defined(CONFIG_DRM_I915_KMS)
1021 if (i915_modeset != 0)
1022 driver.driver_features |= DRIVER_MODESET;
1023#endif
1024 if (i915_modeset == 1)
1025 driver.driver_features |= DRIVER_MODESET;
1026
1027#ifdef CONFIG_VGA_CONSOLE
1028 if (vgacon_text_force() && i915_modeset == -1)
1029 driver.driver_features &= ~DRIVER_MODESET;
1030#endif
1031
3885c6bb
CW		 1032 if (!(driver.driver_features & DRIVER_MODESET))
1033 driver.get_vblank_timestamp = NULL;
1034
8410ea3b 1035 return drm_pci_init(&driver, &i915_pci_driver);
1da177e4
LT		 1036}
1037
1038static void __exit i915_exit(void)
1039{
8410ea3b 1040 drm_pci_exit(&driver, &i915_pci_driver);
1da177e4
LT		 1041}
1042
1043module_init(i915_init);
1044module_exit(i915_exit);
1045
b5e89ed5
DA		 1046MODULE_AUTHOR(DRIVER_AUTHOR);
1047MODULE_DESCRIPTION(DRIVER_DESC);
1da177e4 1048MODULE_LICENSE("GPL and additional rights");
f7000883 1049
b7d84096
JB		 1050/* We give fast paths for the really cool registers */
1051#define NEEDS_FORCE_WAKE(dev_priv, reg) \
b7884eb4
DV		 1052 ((HAS_FORCE_WAKE((dev_priv)->dev)) && \
1053 ((reg) < 0x40000) && \
1054 ((reg) != FORCEWAKE))
b7d84096 1055
f7dff0c9
JB		 1056static bool IS_DISPLAYREG(u32 reg)
1057{
1058 /*
1059 * This should make it easier to transition modules over to the
1060 * new register block scheme, since we can do it incrementally.
1061 */
a7e806de 1062 if (reg >= VLV_DISPLAY_BASE)
f7dff0c9
JB		 1063 return false;
1064
1065 if (reg >= RENDER_RING_BASE &&
1066 reg < RENDER_RING_BASE + 0xff)
1067 return false;
1068 if (reg >= GEN6_BSD_RING_BASE &&
1069 reg < GEN6_BSD_RING_BASE + 0xff)
1070 return false;
1071 if (reg >= BLT_RING_BASE &&
1072 reg < BLT_RING_BASE + 0xff)
1073 return false;
1074
1075 if (reg == PGTBL_ER)
1076 return false;
1077
1078 if (reg >= IPEIR_I965 &&
1079 reg < HWSTAM)
1080 return false;
1081
1082 if (reg == MI_MODE)
1083 return false;
1084
1085 if (reg == GFX_MODE_GEN7)
1086 return false;
1087
1088 if (reg == RENDER_HWS_PGA_GEN7 ||
1089 reg == BSD_HWS_PGA_GEN7 ||
1090 reg == BLT_HWS_PGA_GEN7)
1091 return false;
1092
1093 if (reg == GEN6_BSD_SLEEP_PSMI_CONTROL ||
1094 reg == GEN6_BSD_RNCID)
1095 return false;
1096
1097 if (reg == GEN6_BLITTER_ECOSKPD)
1098 return false;
1099
1100 if (reg >= 0x4000c &&
1101 reg <= 0x4002c)
1102 return false;
1103
1104 if (reg >= 0x4f000 &&
1105 reg <= 0x4f08f)
1106 return false;
1107
1108 if (reg >= 0x4f100 &&
1109 reg <= 0x4f11f)
1110 return false;
1111
1112 if (reg >= VLV_MASTER_IER &&
1113 reg <= GEN6_PMIER)
1114 return false;
1115
1116 if (reg >= FENCE_REG_SANDYBRIDGE_0 &&
1117 reg < (FENCE_REG_SANDYBRIDGE_0 + (16*8)))
1118 return false;
1119
1120 if (reg >= VLV_IIR_RW &&
1121 reg <= VLV_ISR)
1122 return false;
1123
1124 if (reg == FORCEWAKE_VLV ||
1125 reg == FORCEWAKE_ACK_VLV)
1126 return false;
1127
1128 if (reg == GEN6_GDRST)
1129 return false;
1130
1131 return true;
1132}
1133
f7000883
AK		 1134#define __i915_read(x, y) \
1135u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
1136 u##x val = 0; \
1137 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
c937504e
KP		 1138 unsigned long irqflags; \
1139 spin_lock_irqsave(&dev_priv->gt_lock, irqflags); \
1140 if (dev_priv->forcewake_count == 0) \
990bbdad 1141 dev_priv->gt.force_wake_get(dev_priv); \
f7000883 1142 val = read##y(dev_priv->regs + reg); \
c937504e 1143 if (dev_priv->forcewake_count == 0) \
990bbdad 1144 dev_priv->gt.force_wake_put(dev_priv); \
c937504e 1145 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); \
f7dff0c9
JB		 1146 } else if (IS_VALLEYVIEW(dev_priv->dev) && IS_DISPLAYREG(reg)) { \
1147 val = read##y(dev_priv->regs + reg + 0x180000); \
f7000883
AK		 1148 } else { \
1149 val = read##y(dev_priv->regs + reg); \
1150 } \
1151 trace_i915_reg_rw(false, reg, val, sizeof(val)); \
1152 return val; \
1153}
1154
1155__i915_read(8, b)
1156__i915_read(16, w)
1157__i915_read(32, l)
1158__i915_read(64, q)
1159#undef __i915_read
1160
1161#define __i915_write(x, y) \
1162void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
67a3744f 1163 u32 __fifo_ret = 0; \
f7000883
AK		 1164 trace_i915_reg_rw(true, reg, val, sizeof(val)); \
1165 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
67a3744f 1166 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
f7000883 1167 } \
f7dff0c9
JB		 1168 if (IS_VALLEYVIEW(dev_priv->dev) && IS_DISPLAYREG(reg)) { \
1169 write##y(val, dev_priv->regs + reg + 0x180000); \
1170 } else { \
1171 write##y(val, dev_priv->regs + reg); \
1172 } \
67a3744f
BW		 1173 if (unlikely(__fifo_ret)) { \
1174 gen6_gt_check_fifodbg(dev_priv); \
1175 } \
b4c145c1
BW		 1176 if (IS_HASWELL(dev_priv->dev) && (I915_READ_NOTRACE(GEN7_ERR_INT) & ERR_INT_MMIO_UNCLAIMED)) { \
1177 DRM_ERROR("Unclaimed write to %x\n", reg); \
1178 writel(ERR_INT_MMIO_UNCLAIMED, dev_priv->regs + GEN7_ERR_INT); \
1179 } \
f7000883
AK		 1180}
1181__i915_write(8, b)
1182__i915_write(16, w)
1183__i915_write(32, l)
1184__i915_write(64, q)
1185#undef __i915_write
c0c7babc
BW		 1186
1187static const struct register_whitelist {
1188 uint64_t offset;
1189 uint32_t size;
1190 uint32_t gen_bitmask; /* support gens, 0x10 for 4, 0x30 for 4 and 5, etc. */
1191} whitelist[] = {
1192 { RING_TIMESTAMP(RENDER_RING_BASE), 8, 0xF0 },
1193};
1194
1195int i915_reg_read_ioctl(struct drm_device *dev,
1196 void *data, struct drm_file *file)
1197{
1198 struct drm_i915_private *dev_priv = dev->dev_private;
1199 struct drm_i915_reg_read *reg = data;
1200 struct register_whitelist const *entry = whitelist;
1201 int i;
1202
1203 for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) {
1204 if (entry->offset == reg->offset &&
1205 (1 << INTEL_INFO(dev)->gen & entry->gen_bitmask))
1206 break;
1207 }
1208
1209 if (i == ARRAY_SIZE(whitelist))
1210 return -EINVAL;
1211
1212 switch (entry->size) {
1213 case 8:
1214 reg->val = I915_READ64(reg->offset);
1215 break;
1216 case 4:
1217 reg->val = I915_READ(reg->offset);
1218 break;
1219 case 2:
1220 reg->val = I915_READ16(reg->offset);
1221 break;
1222 case 1:
1223 reg->val = I915_READ8(reg->offset);
1224 break;
1225 default:
1226 WARN_ON(1);
1227 return -EINVAL;
1228 }
1229
1230 return 0;
1231}
Linux kernel - Deliverables
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