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1da177e4 LT |
1 | /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*- |
2 | */ | |
0d6aa60b | 3 | /* |
bc54fd1a | 4 | * |
1da177e4 LT |
5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
6 | * All Rights Reserved. | |
bc54fd1a DA |
7 | * |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the | |
10 | * "Software"), to deal in the Software without restriction, including | |
11 | * without limitation the rights to use, copy, modify, merge, publish, | |
12 | * distribute, sub license, and/or sell copies of the Software, and to | |
13 | * permit persons to whom the Software is furnished to do so, subject to | |
14 | * the following conditions: | |
15 | * | |
16 | * The above copyright notice and this permission notice (including the | |
17 | * next paragraph) shall be included in all copies or substantial portions | |
18 | * of the Software. | |
19 | * | |
20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
27 | * | |
0d6aa60b | 28 | */ |
1da177e4 | 29 | |
5669fcac | 30 | #include <linux/device.h> |
760285e7 DH |
31 | #include <drm/drmP.h> |
32 | #include <drm/i915_drm.h> | |
1da177e4 | 33 | #include "i915_drv.h" |
990bbdad | 34 | #include "i915_trace.h" |
f49f0586 | 35 | #include "intel_drv.h" |
1da177e4 | 36 | |
79e53945 | 37 | #include <linux/console.h> |
e0cd3608 | 38 | #include <linux/module.h> |
760285e7 | 39 | #include <drm/drm_crtc_helper.h> |
79e53945 | 40 | |
a35d9d3c | 41 | static int i915_modeset __read_mostly = -1; |
79e53945 | 42 | module_param_named(modeset, i915_modeset, int, 0400); |
6e96e775 BW |
43 | MODULE_PARM_DESC(modeset, |
44 | "Use kernel modesetting [KMS] (0=DRM_I915_KMS from .config, " | |
45 | "1=on, -1=force vga console preference [default])"); | |
79e53945 | 46 | |
a35d9d3c | 47 | unsigned int i915_fbpercrtc __always_unused = 0; |
79e53945 | 48 | module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400); |
1da177e4 | 49 | |
a726915c | 50 | int i915_panel_ignore_lid __read_mostly = 1; |
fca87409 | 51 | module_param_named(panel_ignore_lid, i915_panel_ignore_lid, int, 0600); |
6e96e775 | 52 | MODULE_PARM_DESC(panel_ignore_lid, |
a726915c DV |
53 | "Override lid status (0=autodetect, 1=autodetect disabled [default], " |
54 | "-1=force lid closed, -2=force lid open)"); | |
fca87409 | 55 | |
a35d9d3c | 56 | unsigned int i915_powersave __read_mostly = 1; |
0aa99277 | 57 | module_param_named(powersave, i915_powersave, int, 0600); |
6e96e775 BW |
58 | MODULE_PARM_DESC(powersave, |
59 | "Enable powersavings, fbc, downclocking, etc. (default: true)"); | |
652c393a | 60 | |
f45b5557 | 61 | int i915_semaphores __read_mostly = -1; |
a1656b90 | 62 | module_param_named(semaphores, i915_semaphores, int, 0600); |
6e96e775 | 63 | MODULE_PARM_DESC(semaphores, |
f45b5557 | 64 | "Use semaphores for inter-ring sync (default: -1 (use per-chip defaults))"); |
a1656b90 | 65 | |
c0f372b3 | 66 | int i915_enable_rc6 __read_mostly = -1; |
f57f9c16 | 67 | module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0400); |
6e96e775 | 68 | MODULE_PARM_DESC(i915_enable_rc6, |
83b7f9ac ED |
69 | "Enable power-saving render C-state 6. " |
70 | "Different stages can be selected via bitmask values " | |
71 | "(0 = disable; 1 = enable rc6; 2 = enable deep rc6; 4 = enable deepest rc6). " | |
72 | "For example, 3 would enable rc6 and deep rc6, and 7 would enable everything. " | |
73 | "default: -1 (use per-chip default)"); | |
ac668088 | 74 | |
4415e63b | 75 | int i915_enable_fbc __read_mostly = -1; |
c1a9f047 | 76 | module_param_named(i915_enable_fbc, i915_enable_fbc, int, 0600); |
6e96e775 BW |
77 | MODULE_PARM_DESC(i915_enable_fbc, |
78 | "Enable frame buffer compression for power savings " | |
cd0de039 | 79 | "(default: -1 (use per-chip default))"); |
c1a9f047 | 80 | |
a35d9d3c | 81 | unsigned int i915_lvds_downclock __read_mostly = 0; |
33814341 | 82 | module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400); |
6e96e775 BW |
83 | MODULE_PARM_DESC(lvds_downclock, |
84 | "Use panel (LVDS/eDP) downclocking for power savings " | |
85 | "(default: false)"); | |
33814341 | 86 | |
121d527a TI |
87 | int i915_lvds_channel_mode __read_mostly; |
88 | module_param_named(lvds_channel_mode, i915_lvds_channel_mode, int, 0600); | |
89 | MODULE_PARM_DESC(lvds_channel_mode, | |
90 | "Specify LVDS channel mode " | |
91 | "(0=probe BIOS [default], 1=single-channel, 2=dual-channel)"); | |
92 | ||
4415e63b | 93 | int i915_panel_use_ssc __read_mostly = -1; |
a7615030 | 94 | module_param_named(lvds_use_ssc, i915_panel_use_ssc, int, 0600); |
6e96e775 BW |
95 | MODULE_PARM_DESC(lvds_use_ssc, |
96 | "Use Spread Spectrum Clock with panels [LVDS/eDP] " | |
72bbe58c | 97 | "(default: auto from VBT)"); |
a7615030 | 98 | |
a35d9d3c | 99 | int i915_vbt_sdvo_panel_type __read_mostly = -1; |
5a1e5b6c | 100 | module_param_named(vbt_sdvo_panel_type, i915_vbt_sdvo_panel_type, int, 0600); |
6e96e775 | 101 | MODULE_PARM_DESC(vbt_sdvo_panel_type, |
c10e408a MF |
102 | "Override/Ignore selection of SDVO panel mode in the VBT " |
103 | "(-2=ignore, -1=auto [default], index in VBT BIOS table)"); | |
5a1e5b6c | 104 | |
a35d9d3c | 105 | static bool i915_try_reset __read_mostly = true; |
d78cb50b | 106 | module_param_named(reset, i915_try_reset, bool, 0600); |
6e96e775 | 107 | MODULE_PARM_DESC(reset, "Attempt GPU resets (default: true)"); |
d78cb50b | 108 | |
a35d9d3c | 109 | bool i915_enable_hangcheck __read_mostly = true; |
3e0dc6b0 | 110 | module_param_named(enable_hangcheck, i915_enable_hangcheck, bool, 0644); |
6e96e775 BW |
111 | MODULE_PARM_DESC(enable_hangcheck, |
112 | "Periodically check GPU activity for detecting hangs. " | |
113 | "WARNING: Disabling this can cause system wide hangs. " | |
114 | "(default: true)"); | |
3e0dc6b0 | 115 | |
650dc07e DV |
116 | int i915_enable_ppgtt __read_mostly = -1; |
117 | module_param_named(i915_enable_ppgtt, i915_enable_ppgtt, int, 0600); | |
e21af88d DV |
118 | MODULE_PARM_DESC(i915_enable_ppgtt, |
119 | "Enable PPGTT (default: true)"); | |
120 | ||
105b7c11 RV |
121 | int i915_enable_psr __read_mostly = 0; |
122 | module_param_named(enable_psr, i915_enable_psr, int, 0600); | |
123 | MODULE_PARM_DESC(enable_psr, "Enable PSR (default: false)"); | |
124 | ||
99486b8e | 125 | unsigned int i915_preliminary_hw_support __read_mostly = IS_ENABLED(CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT); |
0a3af268 RV |
126 | module_param_named(preliminary_hw_support, i915_preliminary_hw_support, int, 0600); |
127 | MODULE_PARM_DESC(preliminary_hw_support, | |
99486b8e | 128 | "Enable preliminary hardware support."); |
0a3af268 | 129 | |
bf51d5e2 | 130 | int i915_disable_power_well __read_mostly = 1; |
2124b72e PZ |
131 | module_param_named(disable_power_well, i915_disable_power_well, int, 0600); |
132 | MODULE_PARM_DESC(disable_power_well, | |
bf51d5e2 | 133 | "Disable the power well when possible (default: true)"); |
2124b72e | 134 | |
3c4ca58c PZ |
135 | int i915_enable_ips __read_mostly = 1; |
136 | module_param_named(enable_ips, i915_enable_ips, int, 0600); | |
137 | MODULE_PARM_DESC(enable_ips, "Enable IPS (default: true)"); | |
138 | ||
2385bdf0 JB |
139 | bool i915_fastboot __read_mostly = 0; |
140 | module_param_named(fastboot, i915_fastboot, bool, 0600); | |
141 | MODULE_PARM_DESC(fastboot, "Try to skip unnecessary mode sets at boot time " | |
142 | "(default: false)"); | |
143 | ||
e27e9708 | 144 | int i915_enable_pc8 __read_mostly = 1; |
c67a470b | 145 | module_param_named(enable_pc8, i915_enable_pc8, int, 0600); |
e27e9708 | 146 | MODULE_PARM_DESC(enable_pc8, "Enable support for low power package C states (PC8+) (default: true)"); |
c67a470b | 147 | |
90058745 PZ |
148 | int i915_pc8_timeout __read_mostly = 5000; |
149 | module_param_named(pc8_timeout, i915_pc8_timeout, int, 0600); | |
150 | MODULE_PARM_DESC(pc8_timeout, "Number of msecs of idleness required to enter PC8+ (default: 5000)"); | |
151 | ||
0b74b508 XZ |
152 | bool i915_prefault_disable __read_mostly; |
153 | module_param_named(prefault_disable, i915_prefault_disable, bool, 0600); | |
154 | MODULE_PARM_DESC(prefault_disable, | |
155 | "Disable page prefaulting for pread/pwrite/reloc (default:false). For developers only."); | |
156 | ||
112b715e | 157 | static struct drm_driver driver; |
1f7a6e37 | 158 | extern int intel_agp_enabled; |
112b715e | 159 | |
9a7e8492 | 160 | static const struct intel_device_info intel_i830_info = { |
7eb552ae | 161 | .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2, |
31578148 | 162 | .has_overlay = 1, .overlay_needs_physical = 1, |
73ae478c | 163 | .ring_mask = RENDER_RING, |
cfdf1fa2 KH |
164 | }; |
165 | ||
9a7e8492 | 166 | static const struct intel_device_info intel_845g_info = { |
7eb552ae | 167 | .gen = 2, .num_pipes = 1, |
31578148 | 168 | .has_overlay = 1, .overlay_needs_physical = 1, |
73ae478c | 169 | .ring_mask = RENDER_RING, |
cfdf1fa2 KH |
170 | }; |
171 | ||
9a7e8492 | 172 | static const struct intel_device_info intel_i85x_info = { |
7eb552ae | 173 | .gen = 2, .is_i85x = 1, .is_mobile = 1, .num_pipes = 2, |
5ce8ba7c | 174 | .cursor_needs_physical = 1, |
31578148 | 175 | .has_overlay = 1, .overlay_needs_physical = 1, |
73ae478c | 176 | .ring_mask = RENDER_RING, |
cfdf1fa2 KH |
177 | }; |
178 | ||
9a7e8492 | 179 | static const struct intel_device_info intel_i865g_info = { |
7eb552ae | 180 | .gen = 2, .num_pipes = 1, |
31578148 | 181 | .has_overlay = 1, .overlay_needs_physical = 1, |
73ae478c | 182 | .ring_mask = RENDER_RING, |
cfdf1fa2 KH |
183 | }; |
184 | ||
9a7e8492 | 185 | static const struct intel_device_info intel_i915g_info = { |
7eb552ae | 186 | .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2, |
31578148 | 187 | .has_overlay = 1, .overlay_needs_physical = 1, |
73ae478c | 188 | .ring_mask = RENDER_RING, |
cfdf1fa2 | 189 | }; |
9a7e8492 | 190 | static const struct intel_device_info intel_i915gm_info = { |
7eb552ae | 191 | .gen = 3, .is_mobile = 1, .num_pipes = 2, |
b295d1b6 | 192 | .cursor_needs_physical = 1, |
31578148 | 193 | .has_overlay = 1, .overlay_needs_physical = 1, |
a6c45cf0 | 194 | .supports_tv = 1, |
73ae478c | 195 | .ring_mask = RENDER_RING, |
cfdf1fa2 | 196 | }; |
9a7e8492 | 197 | static const struct intel_device_info intel_i945g_info = { |
7eb552ae | 198 | .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2, |
31578148 | 199 | .has_overlay = 1, .overlay_needs_physical = 1, |
73ae478c | 200 | .ring_mask = RENDER_RING, |
cfdf1fa2 | 201 | }; |
9a7e8492 | 202 | static const struct intel_device_info intel_i945gm_info = { |
7eb552ae | 203 | .gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2, |
b295d1b6 | 204 | .has_hotplug = 1, .cursor_needs_physical = 1, |
31578148 | 205 | .has_overlay = 1, .overlay_needs_physical = 1, |
a6c45cf0 | 206 | .supports_tv = 1, |
73ae478c | 207 | .ring_mask = RENDER_RING, |
cfdf1fa2 KH |
208 | }; |
209 | ||
9a7e8492 | 210 | static const struct intel_device_info intel_i965g_info = { |
7eb552ae | 211 | .gen = 4, .is_broadwater = 1, .num_pipes = 2, |
c96c3a8c | 212 | .has_hotplug = 1, |
31578148 | 213 | .has_overlay = 1, |
73ae478c | 214 | .ring_mask = RENDER_RING, |
cfdf1fa2 KH |
215 | }; |
216 | ||
9a7e8492 | 217 | static const struct intel_device_info intel_i965gm_info = { |
7eb552ae | 218 | .gen = 4, .is_crestline = 1, .num_pipes = 2, |
e3c4e5dd | 219 | .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1, |
31578148 | 220 | .has_overlay = 1, |
a6c45cf0 | 221 | .supports_tv = 1, |
73ae478c | 222 | .ring_mask = RENDER_RING, |
cfdf1fa2 KH |
223 | }; |
224 | ||
9a7e8492 | 225 | static const struct intel_device_info intel_g33_info = { |
7eb552ae | 226 | .gen = 3, .is_g33 = 1, .num_pipes = 2, |
c96c3a8c | 227 | .need_gfx_hws = 1, .has_hotplug = 1, |
31578148 | 228 | .has_overlay = 1, |
73ae478c | 229 | .ring_mask = RENDER_RING, |
cfdf1fa2 KH |
230 | }; |
231 | ||
9a7e8492 | 232 | static const struct intel_device_info intel_g45_info = { |
7eb552ae | 233 | .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2, |
c96c3a8c | 234 | .has_pipe_cxsr = 1, .has_hotplug = 1, |
73ae478c | 235 | .ring_mask = RENDER_RING | BSD_RING, |
cfdf1fa2 KH |
236 | }; |
237 | ||
9a7e8492 | 238 | static const struct intel_device_info intel_gm45_info = { |
7eb552ae | 239 | .gen = 4, .is_g4x = 1, .num_pipes = 2, |
e3c4e5dd | 240 | .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1, |
c96c3a8c | 241 | .has_pipe_cxsr = 1, .has_hotplug = 1, |
a6c45cf0 | 242 | .supports_tv = 1, |
73ae478c | 243 | .ring_mask = RENDER_RING | BSD_RING, |
cfdf1fa2 KH |
244 | }; |
245 | ||
9a7e8492 | 246 | static const struct intel_device_info intel_pineview_info = { |
7eb552ae | 247 | .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2, |
c96c3a8c | 248 | .need_gfx_hws = 1, .has_hotplug = 1, |
31578148 | 249 | .has_overlay = 1, |
cfdf1fa2 KH |
250 | }; |
251 | ||
9a7e8492 | 252 | static const struct intel_device_info intel_ironlake_d_info = { |
7eb552ae | 253 | .gen = 5, .num_pipes = 2, |
5a117db7 | 254 | .need_gfx_hws = 1, .has_hotplug = 1, |
73ae478c | 255 | .ring_mask = RENDER_RING | BSD_RING, |
cfdf1fa2 KH |
256 | }; |
257 | ||
9a7e8492 | 258 | static const struct intel_device_info intel_ironlake_m_info = { |
7eb552ae | 259 | .gen = 5, .is_mobile = 1, .num_pipes = 2, |
e3c4e5dd | 260 | .need_gfx_hws = 1, .has_hotplug = 1, |
c1a9f047 | 261 | .has_fbc = 1, |
73ae478c | 262 | .ring_mask = RENDER_RING | BSD_RING, |
cfdf1fa2 KH |
263 | }; |
264 | ||
9a7e8492 | 265 | static const struct intel_device_info intel_sandybridge_d_info = { |
7eb552ae | 266 | .gen = 6, .num_pipes = 2, |
c96c3a8c | 267 | .need_gfx_hws = 1, .has_hotplug = 1, |
73ae478c | 268 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING, |
3d29b842 | 269 | .has_llc = 1, |
f6e450a6 EA |
270 | }; |
271 | ||
9a7e8492 | 272 | static const struct intel_device_info intel_sandybridge_m_info = { |
7eb552ae | 273 | .gen = 6, .is_mobile = 1, .num_pipes = 2, |
c96c3a8c | 274 | .need_gfx_hws = 1, .has_hotplug = 1, |
9c04f015 | 275 | .has_fbc = 1, |
73ae478c | 276 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING, |
3d29b842 | 277 | .has_llc = 1, |
a13e4093 EA |
278 | }; |
279 | ||
219f4fdb BW |
280 | #define GEN7_FEATURES \ |
281 | .gen = 7, .num_pipes = 3, \ | |
282 | .need_gfx_hws = 1, .has_hotplug = 1, \ | |
73ae478c | 283 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \ |
ab484f8f | 284 | .has_llc = 1 |
219f4fdb | 285 | |
c76b615c | 286 | static const struct intel_device_info intel_ivybridge_d_info = { |
219f4fdb BW |
287 | GEN7_FEATURES, |
288 | .is_ivybridge = 1, | |
c76b615c JB |
289 | }; |
290 | ||
291 | static const struct intel_device_info intel_ivybridge_m_info = { | |
219f4fdb BW |
292 | GEN7_FEATURES, |
293 | .is_ivybridge = 1, | |
294 | .is_mobile = 1, | |
abe959c7 | 295 | .has_fbc = 1, |
c76b615c JB |
296 | }; |
297 | ||
999bcdea BW |
298 | static const struct intel_device_info intel_ivybridge_q_info = { |
299 | GEN7_FEATURES, | |
300 | .is_ivybridge = 1, | |
301 | .num_pipes = 0, /* legal, last one wins */ | |
302 | }; | |
303 | ||
70a3eb7a | 304 | static const struct intel_device_info intel_valleyview_m_info = { |
219f4fdb BW |
305 | GEN7_FEATURES, |
306 | .is_mobile = 1, | |
307 | .num_pipes = 2, | |
70a3eb7a | 308 | .is_valleyview = 1, |
fba5d532 | 309 | .display_mmio_offset = VLV_DISPLAY_BASE, |
30ccd964 | 310 | .has_llc = 0, /* legal, last one wins */ |
70a3eb7a JB |
311 | }; |
312 | ||
313 | static const struct intel_device_info intel_valleyview_d_info = { | |
219f4fdb BW |
314 | GEN7_FEATURES, |
315 | .num_pipes = 2, | |
70a3eb7a | 316 | .is_valleyview = 1, |
fba5d532 | 317 | .display_mmio_offset = VLV_DISPLAY_BASE, |
30ccd964 | 318 | .has_llc = 0, /* legal, last one wins */ |
70a3eb7a JB |
319 | }; |
320 | ||
4cae9ae0 | 321 | static const struct intel_device_info intel_haswell_d_info = { |
219f4fdb BW |
322 | GEN7_FEATURES, |
323 | .is_haswell = 1, | |
dd93be58 | 324 | .has_ddi = 1, |
30568c45 | 325 | .has_fpga_dbg = 1, |
73ae478c | 326 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, |
4cae9ae0 ED |
327 | }; |
328 | ||
329 | static const struct intel_device_info intel_haswell_m_info = { | |
219f4fdb BW |
330 | GEN7_FEATURES, |
331 | .is_haswell = 1, | |
332 | .is_mobile = 1, | |
dd93be58 | 333 | .has_ddi = 1, |
30568c45 | 334 | .has_fpga_dbg = 1, |
891348b2 | 335 | .has_fbc = 1, |
73ae478c | 336 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, |
c76b615c JB |
337 | }; |
338 | ||
a0a18075 JB |
339 | /* |
340 | * Make sure any device matches here are from most specific to most | |
341 | * general. For example, since the Quanta match is based on the subsystem | |
342 | * and subvendor IDs, we need it to come before the more general IVB | |
343 | * PCI ID matches, otherwise we'll use the wrong info struct above. | |
344 | */ | |
345 | #define INTEL_PCI_IDS \ | |
346 | INTEL_I830_IDS(&intel_i830_info), \ | |
347 | INTEL_I845G_IDS(&intel_845g_info), \ | |
348 | INTEL_I85X_IDS(&intel_i85x_info), \ | |
349 | INTEL_I865G_IDS(&intel_i865g_info), \ | |
350 | INTEL_I915G_IDS(&intel_i915g_info), \ | |
351 | INTEL_I915GM_IDS(&intel_i915gm_info), \ | |
352 | INTEL_I945G_IDS(&intel_i945g_info), \ | |
353 | INTEL_I945GM_IDS(&intel_i945gm_info), \ | |
354 | INTEL_I965G_IDS(&intel_i965g_info), \ | |
355 | INTEL_G33_IDS(&intel_g33_info), \ | |
356 | INTEL_I965GM_IDS(&intel_i965gm_info), \ | |
357 | INTEL_GM45_IDS(&intel_gm45_info), \ | |
358 | INTEL_G45_IDS(&intel_g45_info), \ | |
359 | INTEL_PINEVIEW_IDS(&intel_pineview_info), \ | |
360 | INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info), \ | |
361 | INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info), \ | |
362 | INTEL_SNB_D_IDS(&intel_sandybridge_d_info), \ | |
363 | INTEL_SNB_M_IDS(&intel_sandybridge_m_info), \ | |
364 | INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */ \ | |
365 | INTEL_IVB_M_IDS(&intel_ivybridge_m_info), \ | |
366 | INTEL_IVB_D_IDS(&intel_ivybridge_d_info), \ | |
367 | INTEL_HSW_D_IDS(&intel_haswell_d_info), \ | |
368 | INTEL_HSW_M_IDS(&intel_haswell_m_info), \ | |
369 | INTEL_VLV_M_IDS(&intel_valleyview_m_info), \ | |
370 | INTEL_VLV_D_IDS(&intel_valleyview_d_info) | |
371 | ||
6103da0d | 372 | static const struct pci_device_id pciidlist[] = { /* aka */ |
a0a18075 | 373 | INTEL_PCI_IDS, |
49ae35f2 | 374 | {0, 0, 0} |
1da177e4 LT |
375 | }; |
376 | ||
79e53945 JB |
377 | #if defined(CONFIG_DRM_I915_KMS) |
378 | MODULE_DEVICE_TABLE(pci, pciidlist); | |
379 | #endif | |
380 | ||
0206e353 | 381 | void intel_detect_pch(struct drm_device *dev) |
3bad0781 ZW |
382 | { |
383 | struct drm_i915_private *dev_priv = dev->dev_private; | |
384 | struct pci_dev *pch; | |
385 | ||
ce1bb329 BW |
386 | /* In all current cases, num_pipes is equivalent to the PCH_NOP setting |
387 | * (which really amounts to a PCH but no South Display). | |
388 | */ | |
389 | if (INTEL_INFO(dev)->num_pipes == 0) { | |
390 | dev_priv->pch_type = PCH_NOP; | |
ce1bb329 BW |
391 | return; |
392 | } | |
393 | ||
3bad0781 ZW |
394 | /* |
395 | * The reason to probe ISA bridge instead of Dev31:Fun0 is to | |
396 | * make graphics device passthrough work easy for VMM, that only | |
397 | * need to expose ISA bridge to let driver know the real hardware | |
398 | * underneath. This is a requirement from virtualization team. | |
6a9c4b35 RG |
399 | * |
400 | * In some virtualized environments (e.g. XEN), there is irrelevant | |
401 | * ISA bridge in the system. To work reliably, we should scan trhough | |
402 | * all the ISA bridge devices and check for the first match, instead | |
403 | * of only checking the first one. | |
3bad0781 ZW |
404 | */ |
405 | pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL); | |
6a9c4b35 RG |
406 | while (pch) { |
407 | struct pci_dev *curr = pch; | |
3bad0781 | 408 | if (pch->vendor == PCI_VENDOR_ID_INTEL) { |
17a303ec | 409 | unsigned short id; |
3bad0781 | 410 | id = pch->device & INTEL_PCH_DEVICE_ID_MASK; |
17a303ec | 411 | dev_priv->pch_id = id; |
3bad0781 | 412 | |
90711d50 JB |
413 | if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) { |
414 | dev_priv->pch_type = PCH_IBX; | |
415 | DRM_DEBUG_KMS("Found Ibex Peak PCH\n"); | |
7fcb83cd | 416 | WARN_ON(!IS_GEN5(dev)); |
90711d50 | 417 | } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) { |
3bad0781 ZW |
418 | dev_priv->pch_type = PCH_CPT; |
419 | DRM_DEBUG_KMS("Found CougarPoint PCH\n"); | |
7fcb83cd | 420 | WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev))); |
c792513b JB |
421 | } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) { |
422 | /* PantherPoint is CPT compatible */ | |
423 | dev_priv->pch_type = PCH_CPT; | |
492ab669 | 424 | DRM_DEBUG_KMS("Found PantherPoint PCH\n"); |
7fcb83cd | 425 | WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev))); |
eb877ebf ED |
426 | } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) { |
427 | dev_priv->pch_type = PCH_LPT; | |
428 | DRM_DEBUG_KMS("Found LynxPoint PCH\n"); | |
7fcb83cd | 429 | WARN_ON(!IS_HASWELL(dev)); |
08e1413d | 430 | WARN_ON(IS_ULT(dev)); |
ae6935dd WSC |
431 | } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { |
432 | dev_priv->pch_type = PCH_LPT; | |
ae6935dd WSC |
433 | DRM_DEBUG_KMS("Found LynxPoint LP PCH\n"); |
434 | WARN_ON(!IS_HASWELL(dev)); | |
08e1413d | 435 | WARN_ON(!IS_ULT(dev)); |
6a9c4b35 RG |
436 | } else { |
437 | goto check_next; | |
3bad0781 | 438 | } |
6a9c4b35 RG |
439 | pci_dev_put(pch); |
440 | break; | |
3bad0781 | 441 | } |
6a9c4b35 RG |
442 | check_next: |
443 | pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, curr); | |
444 | pci_dev_put(curr); | |
3bad0781 | 445 | } |
6a9c4b35 RG |
446 | if (!pch) |
447 | DRM_DEBUG_KMS("No PCH found?\n"); | |
3bad0781 ZW |
448 | } |
449 | ||
2911a35b BW |
450 | bool i915_semaphore_is_enabled(struct drm_device *dev) |
451 | { | |
452 | if (INTEL_INFO(dev)->gen < 6) | |
453 | return 0; | |
454 | ||
455 | if (i915_semaphores >= 0) | |
456 | return i915_semaphores; | |
457 | ||
59de3295 | 458 | #ifdef CONFIG_INTEL_IOMMU |
2911a35b | 459 | /* Enable semaphores on SNB when IO remapping is off */ |
59de3295 DV |
460 | if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) |
461 | return false; | |
462 | #endif | |
2911a35b BW |
463 | |
464 | return 1; | |
465 | } | |
466 | ||
84b79f8d | 467 | static int i915_drm_freeze(struct drm_device *dev) |
ba8bbcf6 | 468 | { |
61caf87c | 469 | struct drm_i915_private *dev_priv = dev->dev_private; |
24576d23 | 470 | struct drm_crtc *crtc; |
61caf87c | 471 | |
b8efb17b ZR |
472 | /* ignore lid events during suspend */ |
473 | mutex_lock(&dev_priv->modeset_restore_lock); | |
474 | dev_priv->modeset_restore = MODESET_SUSPENDED; | |
475 | mutex_unlock(&dev_priv->modeset_restore_lock); | |
476 | ||
c67a470b PZ |
477 | /* We do a lot of poking in a lot of registers, make sure they work |
478 | * properly. */ | |
479 | hsw_disable_package_c8(dev_priv); | |
cb10799c PZ |
480 | intel_set_power_well(dev, true); |
481 | ||
5bcf719b DA |
482 | drm_kms_helper_poll_disable(dev); |
483 | ||
ba8bbcf6 | 484 | pci_save_state(dev->pdev); |
ba8bbcf6 | 485 | |
5669fcac | 486 | /* If KMS is active, we do the leavevt stuff here */ |
226485e9 | 487 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
db1b76ca DV |
488 | int error; |
489 | ||
490 | mutex_lock(&dev->struct_mutex); | |
491 | error = i915_gem_idle(dev); | |
492 | mutex_unlock(&dev->struct_mutex); | |
84b79f8d | 493 | if (error) { |
226485e9 | 494 | dev_err(&dev->pdev->dev, |
84b79f8d RW |
495 | "GEM idle failed, resume might fail\n"); |
496 | return error; | |
497 | } | |
a261b246 | 498 | |
1a01ab3b JB |
499 | cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work); |
500 | ||
226485e9 | 501 | drm_irq_uninstall(dev); |
15239099 | 502 | dev_priv->enable_hotplug_processing = false; |
24576d23 JB |
503 | /* |
504 | * Disable CRTCs directly since we want to preserve sw state | |
505 | * for _thaw. | |
506 | */ | |
507 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) | |
508 | dev_priv->display.crtc_disable(crtc); | |
7d708ee4 ID |
509 | |
510 | intel_modeset_suspend_hw(dev); | |
5669fcac JB |
511 | } |
512 | ||
9e06dd39 JB |
513 | i915_save_state(dev); |
514 | ||
44834a67 | 515 | intel_opregion_fini(dev); |
8ee1c3db | 516 | |
3fa016a0 | 517 | console_lock(); |
b6f3eff7 | 518 | intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED); |
3fa016a0 DA |
519 | console_unlock(); |
520 | ||
61caf87c | 521 | return 0; |
84b79f8d RW |
522 | } |
523 | ||
6a9ee8af | 524 | int i915_suspend(struct drm_device *dev, pm_message_t state) |
84b79f8d RW |
525 | { |
526 | int error; | |
527 | ||
528 | if (!dev || !dev->dev_private) { | |
529 | DRM_ERROR("dev: %p\n", dev); | |
530 | DRM_ERROR("DRM not initialized, aborting suspend.\n"); | |
531 | return -ENODEV; | |
532 | } | |
533 | ||
534 | if (state.event == PM_EVENT_PRETHAW) | |
535 | return 0; | |
536 | ||
5bcf719b DA |
537 | |
538 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) | |
539 | return 0; | |
6eecba33 | 540 | |
84b79f8d RW |
541 | error = i915_drm_freeze(dev); |
542 | if (error) | |
543 | return error; | |
544 | ||
b932ccb5 DA |
545 | if (state.event == PM_EVENT_SUSPEND) { |
546 | /* Shut down the device */ | |
547 | pci_disable_device(dev->pdev); | |
548 | pci_set_power_state(dev->pdev, PCI_D3hot); | |
549 | } | |
ba8bbcf6 JB |
550 | |
551 | return 0; | |
552 | } | |
553 | ||
073f34d9 JB |
554 | void intel_console_resume(struct work_struct *work) |
555 | { | |
556 | struct drm_i915_private *dev_priv = | |
557 | container_of(work, struct drm_i915_private, | |
558 | console_resume_work); | |
559 | struct drm_device *dev = dev_priv->dev; | |
560 | ||
561 | console_lock(); | |
b6f3eff7 | 562 | intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING); |
073f34d9 JB |
563 | console_unlock(); |
564 | } | |
565 | ||
bb60b969 JB |
566 | static void intel_resume_hotplug(struct drm_device *dev) |
567 | { | |
568 | struct drm_mode_config *mode_config = &dev->mode_config; | |
569 | struct intel_encoder *encoder; | |
570 | ||
571 | mutex_lock(&mode_config->mutex); | |
572 | DRM_DEBUG_KMS("running encoder hotplug functions\n"); | |
573 | ||
574 | list_for_each_entry(encoder, &mode_config->encoder_list, base.head) | |
575 | if (encoder->hot_plug) | |
576 | encoder->hot_plug(encoder); | |
577 | ||
578 | mutex_unlock(&mode_config->mutex); | |
579 | ||
580 | /* Just fire off a uevent and let userspace tell us what to do */ | |
581 | drm_helper_hpd_irq_event(dev); | |
582 | } | |
583 | ||
9d49c0ef | 584 | static int __i915_drm_thaw(struct drm_device *dev, bool restore_gtt_mappings) |
ba8bbcf6 | 585 | { |
5669fcac | 586 | struct drm_i915_private *dev_priv = dev->dev_private; |
84b79f8d | 587 | int error = 0; |
8ee1c3db | 588 | |
c9f7fbf9 VS |
589 | intel_uncore_early_sanitize(dev); |
590 | ||
9d49c0ef PZ |
591 | intel_uncore_sanitize(dev); |
592 | ||
593 | if (drm_core_check_feature(dev, DRIVER_MODESET) && | |
594 | restore_gtt_mappings) { | |
595 | mutex_lock(&dev->struct_mutex); | |
596 | i915_gem_restore_gtt_mappings(dev); | |
597 | mutex_unlock(&dev->struct_mutex); | |
598 | } | |
599 | ||
ebdcefc6 VS |
600 | intel_init_power_well(dev); |
601 | ||
61caf87c | 602 | i915_restore_state(dev); |
44834a67 | 603 | intel_opregion_setup(dev); |
61caf87c | 604 | |
5669fcac JB |
605 | /* KMS EnterVT equivalent */ |
606 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { | |
dde86e2d | 607 | intel_init_pch_refclk(dev); |
1833b134 | 608 | |
5669fcac | 609 | mutex_lock(&dev->struct_mutex); |
5669fcac | 610 | |
f691e2f4 | 611 | error = i915_gem_init_hw(dev); |
5669fcac | 612 | mutex_unlock(&dev->struct_mutex); |
226485e9 | 613 | |
15239099 DV |
614 | /* We need working interrupts for modeset enabling ... */ |
615 | drm_irq_install(dev); | |
616 | ||
1833b134 | 617 | intel_modeset_init_hw(dev); |
24576d23 JB |
618 | |
619 | drm_modeset_lock_all(dev); | |
620 | intel_modeset_setup_hw_state(dev, true); | |
621 | drm_modeset_unlock_all(dev); | |
15239099 DV |
622 | |
623 | /* | |
624 | * ... but also need to make sure that hotplug processing | |
625 | * doesn't cause havoc. Like in the driver load code we don't | |
626 | * bother with the tiny race here where we might loose hotplug | |
627 | * notifications. | |
628 | * */ | |
20afbda2 | 629 | intel_hpd_init(dev); |
15239099 | 630 | dev_priv->enable_hotplug_processing = true; |
bb60b969 JB |
631 | /* Config may have changed between suspend and resume */ |
632 | intel_resume_hotplug(dev); | |
d5bb081b | 633 | } |
1daed3fb | 634 | |
44834a67 CW |
635 | intel_opregion_init(dev); |
636 | ||
073f34d9 JB |
637 | /* |
638 | * The console lock can be pretty contented on resume due | |
639 | * to all the printk activity. Try to keep it out of the hot | |
640 | * path of resume if possible. | |
641 | */ | |
642 | if (console_trylock()) { | |
b6f3eff7 | 643 | intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING); |
073f34d9 JB |
644 | console_unlock(); |
645 | } else { | |
646 | schedule_work(&dev_priv->console_resume_work); | |
647 | } | |
648 | ||
c67a470b PZ |
649 | /* Undo what we did at i915_drm_freeze so the refcount goes back to the |
650 | * expected level. */ | |
651 | hsw_enable_package_c8(dev_priv); | |
652 | ||
b8efb17b ZR |
653 | mutex_lock(&dev_priv->modeset_restore_lock); |
654 | dev_priv->modeset_restore = MODESET_DONE; | |
655 | mutex_unlock(&dev_priv->modeset_restore_lock); | |
84b79f8d RW |
656 | return error; |
657 | } | |
658 | ||
1abd02e2 JB |
659 | static int i915_drm_thaw(struct drm_device *dev) |
660 | { | |
9d49c0ef | 661 | return __i915_drm_thaw(dev, true); |
84b79f8d RW |
662 | } |
663 | ||
6a9ee8af | 664 | int i915_resume(struct drm_device *dev) |
84b79f8d | 665 | { |
1abd02e2 | 666 | struct drm_i915_private *dev_priv = dev->dev_private; |
6eecba33 CW |
667 | int ret; |
668 | ||
5bcf719b DA |
669 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
670 | return 0; | |
671 | ||
84b79f8d RW |
672 | if (pci_enable_device(dev->pdev)) |
673 | return -EIO; | |
674 | ||
675 | pci_set_master(dev->pdev); | |
676 | ||
1abd02e2 JB |
677 | /* |
678 | * Platforms with opregion should have sane BIOS, older ones (gen3 and | |
9d49c0ef PZ |
679 | * earlier) need to restore the GTT mappings since the BIOS might clear |
680 | * all our scratch PTEs. | |
1abd02e2 | 681 | */ |
9d49c0ef | 682 | ret = __i915_drm_thaw(dev, !dev_priv->opregion.header); |
6eecba33 CW |
683 | if (ret) |
684 | return ret; | |
685 | ||
686 | drm_kms_helper_poll_enable(dev); | |
687 | return 0; | |
ba8bbcf6 JB |
688 | } |
689 | ||
11ed50ec | 690 | /** |
f3953dcb | 691 | * i915_reset - reset chip after a hang |
11ed50ec | 692 | * @dev: drm device to reset |
11ed50ec BG |
693 | * |
694 | * Reset the chip. Useful if a hang is detected. Returns zero on successful | |
695 | * reset or otherwise an error code. | |
696 | * | |
697 | * Procedure is fairly simple: | |
698 | * - reset the chip using the reset reg | |
699 | * - re-init context state | |
700 | * - re-init hardware status page | |
701 | * - re-init ring buffer | |
702 | * - re-init interrupt state | |
703 | * - re-init display | |
704 | */ | |
d4b8bb2a | 705 | int i915_reset(struct drm_device *dev) |
11ed50ec BG |
706 | { |
707 | drm_i915_private_t *dev_priv = dev->dev_private; | |
2e7c8ee7 | 708 | bool simulated; |
0573ed4a | 709 | int ret; |
11ed50ec | 710 | |
d78cb50b CW |
711 | if (!i915_try_reset) |
712 | return 0; | |
713 | ||
d54a02c0 | 714 | mutex_lock(&dev->struct_mutex); |
11ed50ec | 715 | |
069efc1d | 716 | i915_gem_reset(dev); |
77f01230 | 717 | |
2e7c8ee7 CW |
718 | simulated = dev_priv->gpu_error.stop_rings != 0; |
719 | ||
be62acb4 MK |
720 | ret = intel_gpu_reset(dev); |
721 | ||
722 | /* Also reset the gpu hangman. */ | |
723 | if (simulated) { | |
724 | DRM_INFO("Simulated gpu hang, resetting stop_rings\n"); | |
725 | dev_priv->gpu_error.stop_rings = 0; | |
726 | if (ret == -ENODEV) { | |
727 | DRM_ERROR("Reset not implemented, but ignoring " | |
728 | "error for simulated gpu hangs\n"); | |
729 | ret = 0; | |
730 | } | |
2e7c8ee7 | 731 | } |
be62acb4 | 732 | |
0573ed4a | 733 | if (ret) { |
f803aa55 | 734 | DRM_ERROR("Failed to reset chip.\n"); |
f953c935 | 735 | mutex_unlock(&dev->struct_mutex); |
f803aa55 | 736 | return ret; |
11ed50ec BG |
737 | } |
738 | ||
739 | /* Ok, now get things going again... */ | |
740 | ||
741 | /* | |
742 | * Everything depends on having the GTT running, so we need to start | |
743 | * there. Fortunately we don't need to do this unless we reset the | |
744 | * chip at a PCI level. | |
745 | * | |
746 | * Next we need to restore the context, but we don't use those | |
747 | * yet either... | |
748 | * | |
749 | * Ring buffer needs to be re-initialized in the KMS case, or if X | |
750 | * was running at the time of the reset (i.e. we weren't VT | |
751 | * switched away). | |
752 | */ | |
753 | if (drm_core_check_feature(dev, DRIVER_MODESET) || | |
db1b76ca | 754 | !dev_priv->ums.mm_suspended) { |
3d57e5bd | 755 | bool hw_contexts_disabled = dev_priv->hw_contexts_disabled; |
db1b76ca | 756 | dev_priv->ums.mm_suspended = 0; |
75a6898f | 757 | |
3d57e5bd BW |
758 | ret = i915_gem_init_hw(dev); |
759 | if (!hw_contexts_disabled && dev_priv->hw_contexts_disabled) | |
760 | DRM_ERROR("HW contexts didn't survive reset\n"); | |
8e88a2bd | 761 | mutex_unlock(&dev->struct_mutex); |
3d57e5bd BW |
762 | if (ret) { |
763 | DRM_ERROR("Failed hw init on reset %d\n", ret); | |
764 | return ret; | |
765 | } | |
f817586c | 766 | |
11ed50ec BG |
767 | drm_irq_uninstall(dev); |
768 | drm_irq_install(dev); | |
20afbda2 | 769 | intel_hpd_init(dev); |
bcbc324a DV |
770 | } else { |
771 | mutex_unlock(&dev->struct_mutex); | |
11ed50ec BG |
772 | } |
773 | ||
11ed50ec BG |
774 | return 0; |
775 | } | |
776 | ||
56550d94 | 777 | static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) |
112b715e | 778 | { |
01a06850 DV |
779 | struct intel_device_info *intel_info = |
780 | (struct intel_device_info *) ent->driver_data; | |
781 | ||
b833d685 BW |
782 | if (IS_PRELIMINARY_HW(intel_info) && !i915_preliminary_hw_support) { |
783 | DRM_INFO("This hardware requires preliminary hardware support.\n" | |
784 | "See CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT, and/or modparam preliminary_hw_support\n"); | |
785 | return -ENODEV; | |
786 | } | |
787 | ||
5fe49d86 CW |
788 | /* Only bind to function 0 of the device. Early generations |
789 | * used function 1 as a placeholder for multi-head. This causes | |
790 | * us confusion instead, especially on the systems where both | |
791 | * functions have the same PCI-ID! | |
792 | */ | |
793 | if (PCI_FUNC(pdev->devfn)) | |
794 | return -ENODEV; | |
795 | ||
01a06850 DV |
796 | /* We've managed to ship a kms-enabled ddx that shipped with an XvMC |
797 | * implementation for gen3 (and only gen3) that used legacy drm maps | |
798 | * (gasp!) to share buffers between X and the client. Hence we need to | |
799 | * keep around the fake agp stuff for gen3, even when kms is enabled. */ | |
800 | if (intel_info->gen != 3) { | |
801 | driver.driver_features &= | |
802 | ~(DRIVER_USE_AGP | DRIVER_REQUIRE_AGP); | |
803 | } else if (!intel_agp_enabled) { | |
804 | DRM_ERROR("drm/i915 can't work without intel_agp module!\n"); | |
805 | return -ENODEV; | |
806 | } | |
807 | ||
dcdb1674 | 808 | return drm_get_pci_dev(pdev, ent, &driver); |
112b715e KH |
809 | } |
810 | ||
811 | static void | |
812 | i915_pci_remove(struct pci_dev *pdev) | |
813 | { | |
814 | struct drm_device *dev = pci_get_drvdata(pdev); | |
815 | ||
816 | drm_put_dev(dev); | |
817 | } | |
818 | ||
84b79f8d | 819 | static int i915_pm_suspend(struct device *dev) |
112b715e | 820 | { |
84b79f8d RW |
821 | struct pci_dev *pdev = to_pci_dev(dev); |
822 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
823 | int error; | |
112b715e | 824 | |
84b79f8d RW |
825 | if (!drm_dev || !drm_dev->dev_private) { |
826 | dev_err(dev, "DRM not initialized, aborting suspend.\n"); | |
827 | return -ENODEV; | |
828 | } | |
112b715e | 829 | |
5bcf719b DA |
830 | if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
831 | return 0; | |
832 | ||
84b79f8d RW |
833 | error = i915_drm_freeze(drm_dev); |
834 | if (error) | |
835 | return error; | |
112b715e | 836 | |
84b79f8d RW |
837 | pci_disable_device(pdev); |
838 | pci_set_power_state(pdev, PCI_D3hot); | |
cbda12d7 | 839 | |
84b79f8d | 840 | return 0; |
cbda12d7 ZW |
841 | } |
842 | ||
84b79f8d | 843 | static int i915_pm_resume(struct device *dev) |
cbda12d7 | 844 | { |
84b79f8d RW |
845 | struct pci_dev *pdev = to_pci_dev(dev); |
846 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
847 | ||
848 | return i915_resume(drm_dev); | |
cbda12d7 ZW |
849 | } |
850 | ||
84b79f8d | 851 | static int i915_pm_freeze(struct device *dev) |
cbda12d7 | 852 | { |
84b79f8d RW |
853 | struct pci_dev *pdev = to_pci_dev(dev); |
854 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
855 | ||
856 | if (!drm_dev || !drm_dev->dev_private) { | |
857 | dev_err(dev, "DRM not initialized, aborting suspend.\n"); | |
858 | return -ENODEV; | |
859 | } | |
860 | ||
861 | return i915_drm_freeze(drm_dev); | |
cbda12d7 ZW |
862 | } |
863 | ||
84b79f8d | 864 | static int i915_pm_thaw(struct device *dev) |
cbda12d7 | 865 | { |
84b79f8d RW |
866 | struct pci_dev *pdev = to_pci_dev(dev); |
867 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
868 | ||
869 | return i915_drm_thaw(drm_dev); | |
cbda12d7 ZW |
870 | } |
871 | ||
84b79f8d | 872 | static int i915_pm_poweroff(struct device *dev) |
cbda12d7 | 873 | { |
84b79f8d RW |
874 | struct pci_dev *pdev = to_pci_dev(dev); |
875 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
84b79f8d | 876 | |
61caf87c | 877 | return i915_drm_freeze(drm_dev); |
cbda12d7 ZW |
878 | } |
879 | ||
b4b78d12 | 880 | static const struct dev_pm_ops i915_pm_ops = { |
0206e353 AJ |
881 | .suspend = i915_pm_suspend, |
882 | .resume = i915_pm_resume, | |
883 | .freeze = i915_pm_freeze, | |
884 | .thaw = i915_pm_thaw, | |
885 | .poweroff = i915_pm_poweroff, | |
886 | .restore = i915_pm_resume, | |
cbda12d7 ZW |
887 | }; |
888 | ||
78b68556 | 889 | static const struct vm_operations_struct i915_gem_vm_ops = { |
de151cf6 | 890 | .fault = i915_gem_fault, |
ab00b3e5 JB |
891 | .open = drm_gem_vm_open, |
892 | .close = drm_gem_vm_close, | |
de151cf6 JB |
893 | }; |
894 | ||
e08e96de AV |
895 | static const struct file_operations i915_driver_fops = { |
896 | .owner = THIS_MODULE, | |
897 | .open = drm_open, | |
898 | .release = drm_release, | |
899 | .unlocked_ioctl = drm_ioctl, | |
900 | .mmap = drm_gem_mmap, | |
901 | .poll = drm_poll, | |
e08e96de AV |
902 | .read = drm_read, |
903 | #ifdef CONFIG_COMPAT | |
904 | .compat_ioctl = i915_compat_ioctl, | |
905 | #endif | |
906 | .llseek = noop_llseek, | |
907 | }; | |
908 | ||
1da177e4 | 909 | static struct drm_driver driver = { |
0c54781b MW |
910 | /* Don't use MTRRs here; the Xserver or userspace app should |
911 | * deal with them for Intel hardware. | |
792d2b9a | 912 | */ |
673a394b | 913 | .driver_features = |
28185647 | 914 | DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | |
10ba5012 KH |
915 | DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME | |
916 | DRIVER_RENDER, | |
22eae947 | 917 | .load = i915_driver_load, |
ba8bbcf6 | 918 | .unload = i915_driver_unload, |
673a394b | 919 | .open = i915_driver_open, |
22eae947 DA |
920 | .lastclose = i915_driver_lastclose, |
921 | .preclose = i915_driver_preclose, | |
673a394b | 922 | .postclose = i915_driver_postclose, |
d8e29209 RW |
923 | |
924 | /* Used in place of i915_pm_ops for non-DRIVER_MODESET */ | |
925 | .suspend = i915_suspend, | |
926 | .resume = i915_resume, | |
927 | ||
cda17380 | 928 | .device_is_agp = i915_driver_device_is_agp, |
7c1c2871 DA |
929 | .master_create = i915_master_create, |
930 | .master_destroy = i915_master_destroy, | |
955b12de | 931 | #if defined(CONFIG_DEBUG_FS) |
27c202ad BG |
932 | .debugfs_init = i915_debugfs_init, |
933 | .debugfs_cleanup = i915_debugfs_cleanup, | |
955b12de | 934 | #endif |
673a394b | 935 | .gem_free_object = i915_gem_free_object, |
de151cf6 | 936 | .gem_vm_ops = &i915_gem_vm_ops, |
1286ff73 DV |
937 | |
938 | .prime_handle_to_fd = drm_gem_prime_handle_to_fd, | |
939 | .prime_fd_to_handle = drm_gem_prime_fd_to_handle, | |
940 | .gem_prime_export = i915_gem_prime_export, | |
941 | .gem_prime_import = i915_gem_prime_import, | |
942 | ||
ff72145b DA |
943 | .dumb_create = i915_gem_dumb_create, |
944 | .dumb_map_offset = i915_gem_mmap_gtt, | |
43387b37 | 945 | .dumb_destroy = drm_gem_dumb_destroy, |
1da177e4 | 946 | .ioctls = i915_ioctls, |
e08e96de | 947 | .fops = &i915_driver_fops, |
22eae947 DA |
948 | .name = DRIVER_NAME, |
949 | .desc = DRIVER_DESC, | |
950 | .date = DRIVER_DATE, | |
951 | .major = DRIVER_MAJOR, | |
952 | .minor = DRIVER_MINOR, | |
953 | .patchlevel = DRIVER_PATCHLEVEL, | |
1da177e4 LT |
954 | }; |
955 | ||
8410ea3b DA |
956 | static struct pci_driver i915_pci_driver = { |
957 | .name = DRIVER_NAME, | |
958 | .id_table = pciidlist, | |
959 | .probe = i915_pci_probe, | |
960 | .remove = i915_pci_remove, | |
961 | .driver.pm = &i915_pm_ops, | |
962 | }; | |
963 | ||
1da177e4 LT |
964 | static int __init i915_init(void) |
965 | { | |
966 | driver.num_ioctls = i915_max_ioctl; | |
79e53945 JB |
967 | |
968 | /* | |
969 | * If CONFIG_DRM_I915_KMS is set, default to KMS unless | |
970 | * explicitly disabled with the module pararmeter. | |
971 | * | |
972 | * Otherwise, just follow the parameter (defaulting to off). | |
973 | * | |
974 | * Allow optional vga_text_mode_force boot option to override | |
975 | * the default behavior. | |
976 | */ | |
977 | #if defined(CONFIG_DRM_I915_KMS) | |
978 | if (i915_modeset != 0) | |
979 | driver.driver_features |= DRIVER_MODESET; | |
980 | #endif | |
981 | if (i915_modeset == 1) | |
982 | driver.driver_features |= DRIVER_MODESET; | |
983 | ||
984 | #ifdef CONFIG_VGA_CONSOLE | |
985 | if (vgacon_text_force() && i915_modeset == -1) | |
986 | driver.driver_features &= ~DRIVER_MODESET; | |
987 | #endif | |
988 | ||
3885c6bb CW |
989 | if (!(driver.driver_features & DRIVER_MODESET)) |
990 | driver.get_vblank_timestamp = NULL; | |
991 | ||
8410ea3b | 992 | return drm_pci_init(&driver, &i915_pci_driver); |
1da177e4 LT |
993 | } |
994 | ||
995 | static void __exit i915_exit(void) | |
996 | { | |
8410ea3b | 997 | drm_pci_exit(&driver, &i915_pci_driver); |
1da177e4 LT |
998 | } |
999 | ||
1000 | module_init(i915_init); | |
1001 | module_exit(i915_exit); | |
1002 | ||
b5e89ed5 DA |
1003 | MODULE_AUTHOR(DRIVER_AUTHOR); |
1004 | MODULE_DESCRIPTION(DRIVER_DESC); | |
1da177e4 | 1005 | MODULE_LICENSE("GPL and additional rights"); |