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Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_drv.c
CommitLineData
1da177e4
LT		 1/* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
2 */
0d6aa60b 3/*
bc54fd1a 4 *
1da177e4
LT		 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
bc54fd1a
DA		 7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
0d6aa60b 28 */
1da177e4 29
5669fcac 30#include <linux/device.h>
760285e7
DH		 31#include <drm/drmP.h>
32#include <drm/i915_drm.h>
1da177e4 33#include "i915_drv.h"
990bbdad 34#include "i915_trace.h"
f49f0586 35#include "intel_drv.h"
1da177e4 36
79e53945 37#include <linux/console.h>
e0cd3608 38#include <linux/module.h>
760285e7 39#include <drm/drm_crtc_helper.h>
79e53945 40
a35d9d3c 41static int i915_modeset __read_mostly = -1;
79e53945 42module_param_named(modeset, i915_modeset, int, 0400);
6e96e775
BW		 43MODULE_PARM_DESC(modeset,
44 "Use kernel modesetting [KMS] (0=DRM_I915_KMS from .config, "
45 "1=on, -1=force vga console preference [default])");
79e53945 46
a35d9d3c 47unsigned int i915_fbpercrtc __always_unused = 0;
79e53945 48module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400);
1da177e4 49
a726915c 50int i915_panel_ignore_lid __read_mostly = 1;
fca87409 51module_param_named(panel_ignore_lid, i915_panel_ignore_lid, int, 0600);
6e96e775 52MODULE_PARM_DESC(panel_ignore_lid,
a726915c
DV		 53 "Override lid status (0=autodetect, 1=autodetect disabled [default], "
54 "-1=force lid closed, -2=force lid open)");
fca87409 55
a35d9d3c 56unsigned int i915_powersave __read_mostly = 1;
0aa99277 57module_param_named(powersave, i915_powersave, int, 0600);
6e96e775
BW		 58MODULE_PARM_DESC(powersave,
59 "Enable powersavings, fbc, downclocking, etc. (default: true)");
652c393a 60
f45b5557 61int i915_semaphores __read_mostly = -1;
a1656b90 62module_param_named(semaphores, i915_semaphores, int, 0600);
6e96e775 63MODULE_PARM_DESC(semaphores,
f45b5557 64 "Use semaphores for inter-ring sync (default: -1 (use per-chip defaults))");
a1656b90 65
c0f372b3 66int i915_enable_rc6 __read_mostly = -1;
f57f9c16 67module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0400);
6e96e775 68MODULE_PARM_DESC(i915_enable_rc6,
83b7f9ac
ED		 69 "Enable power-saving render C-state 6. "
70 "Different stages can be selected via bitmask values "
71 "(0 = disable; 1 = enable rc6; 2 = enable deep rc6; 4 = enable deepest rc6). "
72 "For example, 3 would enable rc6 and deep rc6, and 7 would enable everything. "
73 "default: -1 (use per-chip default)");
ac668088 74
4415e63b 75int i915_enable_fbc __read_mostly = -1;
c1a9f047 76module_param_named(i915_enable_fbc, i915_enable_fbc, int, 0600);
6e96e775
BW		 77MODULE_PARM_DESC(i915_enable_fbc,
78 "Enable frame buffer compression for power savings "
cd0de039 79 "(default: -1 (use per-chip default))");
c1a9f047 80
a35d9d3c 81unsigned int i915_lvds_downclock __read_mostly = 0;
33814341 82module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400);
6e96e775
BW		 83MODULE_PARM_DESC(lvds_downclock,
84 "Use panel (LVDS/eDP) downclocking for power savings "
85 "(default: false)");
33814341 86
121d527a
TI		 87int i915_lvds_channel_mode __read_mostly;
88module_param_named(lvds_channel_mode, i915_lvds_channel_mode, int, 0600);
89MODULE_PARM_DESC(lvds_channel_mode,
90 "Specify LVDS channel mode "
91 "(0=probe BIOS [default], 1=single-channel, 2=dual-channel)");
92
4415e63b 93int i915_panel_use_ssc __read_mostly = -1;
a7615030 94module_param_named(lvds_use_ssc, i915_panel_use_ssc, int, 0600);
6e96e775
BW		 95MODULE_PARM_DESC(lvds_use_ssc,
96 "Use Spread Spectrum Clock with panels [LVDS/eDP] "
72bbe58c 97 "(default: auto from VBT)");
a7615030 98
a35d9d3c 99int i915_vbt_sdvo_panel_type __read_mostly = -1;
5a1e5b6c 100module_param_named(vbt_sdvo_panel_type, i915_vbt_sdvo_panel_type, int, 0600);
6e96e775 101MODULE_PARM_DESC(vbt_sdvo_panel_type,
c10e408a
MF		 102 "Override/Ignore selection of SDVO panel mode in the VBT "
103 "(-2=ignore, -1=auto [default], index in VBT BIOS table)");
5a1e5b6c 104
a35d9d3c 105static bool i915_try_reset __read_mostly = true;
d78cb50b 106module_param_named(reset, i915_try_reset, bool, 0600);
6e96e775 107MODULE_PARM_DESC(reset, "Attempt GPU resets (default: true)");
d78cb50b 108
a35d9d3c 109bool i915_enable_hangcheck __read_mostly = true;
3e0dc6b0 110module_param_named(enable_hangcheck, i915_enable_hangcheck, bool, 0644);
6e96e775
BW		 111MODULE_PARM_DESC(enable_hangcheck,
112 "Periodically check GPU activity for detecting hangs. "
113 "WARNING: Disabling this can cause system wide hangs. "
114 "(default: true)");
3e0dc6b0 115
650dc07e
DV		 116int i915_enable_ppgtt __read_mostly = -1;
117module_param_named(i915_enable_ppgtt, i915_enable_ppgtt, int, 0600);
e21af88d
DV		 118MODULE_PARM_DESC(i915_enable_ppgtt,
119 "Enable PPGTT (default: true)");
120
0a3af268
RV		 121unsigned int i915_preliminary_hw_support __read_mostly = 0;
122module_param_named(preliminary_hw_support, i915_preliminary_hw_support, int, 0600);
123MODULE_PARM_DESC(preliminary_hw_support,
124 "Enable preliminary hardware support. "
125 "Enable Haswell and ValleyView Support. "
126 "(default: false)");
127
2124b72e
PZ		 128int i915_disable_power_well __read_mostly = 0;
129module_param_named(disable_power_well, i915_disable_power_well, int, 0600);
130MODULE_PARM_DESC(disable_power_well,
131 "Disable the power well when possible (default: false)");
132
112b715e 133static struct drm_driver driver;
1f7a6e37 134extern int intel_agp_enabled;
112b715e 135
cfdf1fa2 136#define INTEL_VGA_DEVICE(id, info) { \
80a2901d 137 .class = PCI_BASE_CLASS_DISPLAY << 16, \
934f992c 138 .class_mask = 0xff0000, \
49ae35f2
KH		 139 .vendor = 0x8086, \
140 .device = id, \
141 .subvendor = PCI_ANY_ID, \
142 .subdevice = PCI_ANY_ID, \
cfdf1fa2
KH		 143 .driver_data = (unsigned long) info }
144
9a7e8492 145static const struct intel_device_info intel_i830_info = {
a6c45cf0 146 .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1,
31578148 147 .has_overlay = 1, .overlay_needs_physical = 1,
cfdf1fa2
KH		 148};
149
9a7e8492 150static const struct intel_device_info intel_845g_info = {
a6c45cf0 151 .gen = 2,
31578148 152 .has_overlay = 1, .overlay_needs_physical = 1,
cfdf1fa2
KH		 153};
154
9a7e8492 155static const struct intel_device_info intel_i85x_info = {
a6c45cf0 156 .gen = 2, .is_i85x = 1, .is_mobile = 1,
5ce8ba7c 157 .cursor_needs_physical = 1,
31578148 158 .has_overlay = 1, .overlay_needs_physical = 1,
cfdf1fa2
KH		 159};
160
9a7e8492 161static const struct intel_device_info intel_i865g_info = {
a6c45cf0 162 .gen = 2,
31578148 163 .has_overlay = 1, .overlay_needs_physical = 1,
cfdf1fa2
KH		 164};
165
9a7e8492 166static const struct intel_device_info intel_i915g_info = {
a6c45cf0 167 .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1,
31578148 168 .has_overlay = 1, .overlay_needs_physical = 1,
cfdf1fa2 169};
9a7e8492 170static const struct intel_device_info intel_i915gm_info = {
a6c45cf0 171 .gen = 3, .is_mobile = 1,
b295d1b6 172 .cursor_needs_physical = 1,
31578148 173 .has_overlay = 1, .overlay_needs_physical = 1,
a6c45cf0 174 .supports_tv = 1,
cfdf1fa2 175};
9a7e8492 176static const struct intel_device_info intel_i945g_info = {
a6c45cf0 177 .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1,
31578148 178 .has_overlay = 1, .overlay_needs_physical = 1,
cfdf1fa2 179};
9a7e8492 180static const struct intel_device_info intel_i945gm_info = {
a6c45cf0 181 .gen = 3, .is_i945gm = 1, .is_mobile = 1,
b295d1b6 182 .has_hotplug = 1, .cursor_needs_physical = 1,
31578148 183 .has_overlay = 1, .overlay_needs_physical = 1,
a6c45cf0 184 .supports_tv = 1,
cfdf1fa2
KH		 185};
186
9a7e8492 187static const struct intel_device_info intel_i965g_info = {
a6c45cf0 188 .gen = 4, .is_broadwater = 1,
c96c3a8c 189 .has_hotplug = 1,
31578148 190 .has_overlay = 1,
cfdf1fa2
KH		 191};
192
9a7e8492 193static const struct intel_device_info intel_i965gm_info = {
a6c45cf0 194 .gen = 4, .is_crestline = 1,
e3c4e5dd 195 .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
31578148 196 .has_overlay = 1,
a6c45cf0 197 .supports_tv = 1,
cfdf1fa2
KH		 198};
199
9a7e8492 200static const struct intel_device_info intel_g33_info = {
a6c45cf0 201 .gen = 3, .is_g33 = 1,
c96c3a8c 202 .need_gfx_hws = 1, .has_hotplug = 1,
31578148 203 .has_overlay = 1,
cfdf1fa2
KH		 204};
205
9a7e8492 206static const struct intel_device_info intel_g45_info = {
a6c45cf0 207 .gen = 4, .is_g4x = 1, .need_gfx_hws = 1,
c96c3a8c 208 .has_pipe_cxsr = 1, .has_hotplug = 1,
92f49d9c 209 .has_bsd_ring = 1,
cfdf1fa2
KH		 210};
211
9a7e8492 212static const struct intel_device_info intel_gm45_info = {
a6c45cf0 213 .gen = 4, .is_g4x = 1,
e3c4e5dd 214 .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
c96c3a8c 215 .has_pipe_cxsr = 1, .has_hotplug = 1,
a6c45cf0 216 .supports_tv = 1,
92f49d9c 217 .has_bsd_ring = 1,
cfdf1fa2
KH		 218};
219
9a7e8492 220static const struct intel_device_info intel_pineview_info = {
a6c45cf0 221 .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1,
c96c3a8c 222 .need_gfx_hws = 1, .has_hotplug = 1,
31578148 223 .has_overlay = 1,
cfdf1fa2
KH		 224};
225
9a7e8492 226static const struct intel_device_info intel_ironlake_d_info = {
f00a3ddf 227 .gen = 5,
5a117db7 228 .need_gfx_hws = 1, .has_hotplug = 1,
92f49d9c 229 .has_bsd_ring = 1,
cfdf1fa2
KH		 230};
231
9a7e8492 232static const struct intel_device_info intel_ironlake_m_info = {
f00a3ddf 233 .gen = 5, .is_mobile = 1,
e3c4e5dd 234 .need_gfx_hws = 1, .has_hotplug = 1,
c1a9f047 235 .has_fbc = 1,
92f49d9c 236 .has_bsd_ring = 1,
cfdf1fa2
KH		 237};
238
9a7e8492 239static const struct intel_device_info intel_sandybridge_d_info = {
a6c45cf0 240 .gen = 6,
c96c3a8c 241 .need_gfx_hws = 1, .has_hotplug = 1,
881f47b6 242 .has_bsd_ring = 1,
549f7365 243 .has_blt_ring = 1,
3d29b842 244 .has_llc = 1,
b7884eb4 245 .has_force_wake = 1,
f6e450a6
EA		 246};
247
9a7e8492 248static const struct intel_device_info intel_sandybridge_m_info = {
a6c45cf0 249 .gen = 6, .is_mobile = 1,
c96c3a8c 250 .need_gfx_hws = 1, .has_hotplug = 1,
9c04f015 251 .has_fbc = 1,
881f47b6 252 .has_bsd_ring = 1,
549f7365 253 .has_blt_ring = 1,
3d29b842 254 .has_llc = 1,
b7884eb4 255 .has_force_wake = 1,
a13e4093
EA		 256};
257
c76b615c
JB		 258static const struct intel_device_info intel_ivybridge_d_info = {
259 .is_ivybridge = 1, .gen = 7,
260 .need_gfx_hws = 1, .has_hotplug = 1,
261 .has_bsd_ring = 1,
262 .has_blt_ring = 1,
3d29b842 263 .has_llc = 1,
b7884eb4 264 .has_force_wake = 1,
c76b615c
JB		 265};
266
267static const struct intel_device_info intel_ivybridge_m_info = {
268 .is_ivybridge = 1, .gen = 7, .is_mobile = 1,
269 .need_gfx_hws = 1, .has_hotplug = 1,
270 .has_fbc = 0, /* FBC is not enabled on Ivybridge mobile yet */
271 .has_bsd_ring = 1,
272 .has_blt_ring = 1,
3d29b842 273 .has_llc = 1,
b7884eb4 274 .has_force_wake = 1,
c76b615c
JB		 275};
276
70a3eb7a
JB		 277static const struct intel_device_info intel_valleyview_m_info = {
278 .gen = 7, .is_mobile = 1,
279 .need_gfx_hws = 1, .has_hotplug = 1,
280 .has_fbc = 0,
281 .has_bsd_ring = 1,
282 .has_blt_ring = 1,
283 .is_valleyview = 1,
fba5d532 284 .display_mmio_offset = VLV_DISPLAY_BASE,
70a3eb7a
JB		 285};
286
287static const struct intel_device_info intel_valleyview_d_info = {
288 .gen = 7,
289 .need_gfx_hws = 1, .has_hotplug = 1,
290 .has_fbc = 0,
291 .has_bsd_ring = 1,
292 .has_blt_ring = 1,
293 .is_valleyview = 1,
fba5d532 294 .display_mmio_offset = VLV_DISPLAY_BASE,
70a3eb7a
JB		 295};
296
4cae9ae0
ED		 297static const struct intel_device_info intel_haswell_d_info = {
298 .is_haswell = 1, .gen = 7,
299 .need_gfx_hws = 1, .has_hotplug = 1,
300 .has_bsd_ring = 1,
301 .has_blt_ring = 1,
302 .has_llc = 1,
b7884eb4 303 .has_force_wake = 1,
4cae9ae0
ED		 304};
305
306static const struct intel_device_info intel_haswell_m_info = {
307 .is_haswell = 1, .gen = 7, .is_mobile = 1,
308 .need_gfx_hws = 1, .has_hotplug = 1,
309 .has_bsd_ring = 1,
310 .has_blt_ring = 1,
311 .has_llc = 1,
b7884eb4 312 .has_force_wake = 1,
c76b615c
JB		 313};
314
6103da0d
CW		 315static const struct pci_device_id pciidlist[] = { /* aka */
316 INTEL_VGA_DEVICE(0x3577, &intel_i830_info), /* I830_M */
317 INTEL_VGA_DEVICE(0x2562, &intel_845g_info), /* 845_G */
318 INTEL_VGA_DEVICE(0x3582, &intel_i85x_info), /* I855_GM */
5ce8ba7c 319 INTEL_VGA_DEVICE(0x358e, &intel_i85x_info),
6103da0d
CW		 320 INTEL_VGA_DEVICE(0x2572, &intel_i865g_info), /* I865_G */
321 INTEL_VGA_DEVICE(0x2582, &intel_i915g_info), /* I915_G */
322 INTEL_VGA_DEVICE(0x258a, &intel_i915g_info), /* E7221_G */
323 INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info), /* I915_GM */
324 INTEL_VGA_DEVICE(0x2772, &intel_i945g_info), /* I945_G */
325 INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info), /* I945_GM */
326 INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info), /* I945_GME */
327 INTEL_VGA_DEVICE(0x2972, &intel_i965g_info), /* I946_GZ */
328 INTEL_VGA_DEVICE(0x2982, &intel_i965g_info), /* G35_G */
329 INTEL_VGA_DEVICE(0x2992, &intel_i965g_info), /* I965_Q */
330 INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info), /* I965_G */
331 INTEL_VGA_DEVICE(0x29b2, &intel_g33_info), /* Q35_G */
332 INTEL_VGA_DEVICE(0x29c2, &intel_g33_info), /* G33_G */
333 INTEL_VGA_DEVICE(0x29d2, &intel_g33_info), /* Q33_G */
334 INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info), /* I965_GM */
335 INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info), /* I965_GME */
336 INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info), /* GM45_G */
337 INTEL_VGA_DEVICE(0x2e02, &intel_g45_info), /* IGD_E_G */
338 INTEL_VGA_DEVICE(0x2e12, &intel_g45_info), /* Q45_G */
339 INTEL_VGA_DEVICE(0x2e22, &intel_g45_info), /* G45_G */
340 INTEL_VGA_DEVICE(0x2e32, &intel_g45_info), /* G41_G */
341 INTEL_VGA_DEVICE(0x2e42, &intel_g45_info), /* B43_G */
41a51428 342 INTEL_VGA_DEVICE(0x2e92, &intel_g45_info), /* B43_G.1 */
cfdf1fa2
KH		 343 INTEL_VGA_DEVICE(0xa001, &intel_pineview_info),
344 INTEL_VGA_DEVICE(0xa011, &intel_pineview_info),
345 INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info),
346 INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info),
f6e450a6 347 INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info),
85540480
ZW		 348 INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info),
349 INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info),
a13e4093 350 INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info),
85540480 351 INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info),
4fefe435 352 INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info),
85540480 353 INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info),
c76b615c
JB		 354 INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info), /* GT1 mobile */
355 INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info), /* GT2 mobile */
356 INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */
357 INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */
358 INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */
cc22a938 359 INTEL_VGA_DEVICE(0x016a, &intel_ivybridge_d_info), /* GT2 server */
c14f5286
ED		 360 INTEL_VGA_DEVICE(0x0402, &intel_haswell_d_info), /* GT1 desktop */
361 INTEL_VGA_DEVICE(0x0412, &intel_haswell_d_info), /* GT2 desktop */
da612d88 362 INTEL_VGA_DEVICE(0x0422, &intel_haswell_d_info), /* GT2 desktop */
c14f5286
ED		 363 INTEL_VGA_DEVICE(0x040a, &intel_haswell_d_info), /* GT1 server */
364 INTEL_VGA_DEVICE(0x041a, &intel_haswell_d_info), /* GT2 server */
da612d88 365 INTEL_VGA_DEVICE(0x042a, &intel_haswell_d_info), /* GT2 server */
c14f5286
ED		 366 INTEL_VGA_DEVICE(0x0406, &intel_haswell_m_info), /* GT1 mobile */
367 INTEL_VGA_DEVICE(0x0416, &intel_haswell_m_info), /* GT2 mobile */
da612d88
PZ		 368 INTEL_VGA_DEVICE(0x0426, &intel_haswell_m_info), /* GT2 mobile */
369 INTEL_VGA_DEVICE(0x0C02, &intel_haswell_d_info), /* SDV GT1 desktop */
370 INTEL_VGA_DEVICE(0x0C12, &intel_haswell_d_info), /* SDV GT2 desktop */
371 INTEL_VGA_DEVICE(0x0C22, &intel_haswell_d_info), /* SDV GT2 desktop */
372 INTEL_VGA_DEVICE(0x0C0A, &intel_haswell_d_info), /* SDV GT1 server */
373 INTEL_VGA_DEVICE(0x0C1A, &intel_haswell_d_info), /* SDV GT2 server */
374 INTEL_VGA_DEVICE(0x0C2A, &intel_haswell_d_info), /* SDV GT2 server */
375 INTEL_VGA_DEVICE(0x0C06, &intel_haswell_m_info), /* SDV GT1 mobile */
376 INTEL_VGA_DEVICE(0x0C16, &intel_haswell_m_info), /* SDV GT2 mobile */
377 INTEL_VGA_DEVICE(0x0C26, &intel_haswell_m_info), /* SDV GT2 mobile */
378 INTEL_VGA_DEVICE(0x0A02, &intel_haswell_d_info), /* ULT GT1 desktop */
379 INTEL_VGA_DEVICE(0x0A12, &intel_haswell_d_info), /* ULT GT2 desktop */
380 INTEL_VGA_DEVICE(0x0A22, &intel_haswell_d_info), /* ULT GT2 desktop */
381 INTEL_VGA_DEVICE(0x0A0A, &intel_haswell_d_info), /* ULT GT1 server */
382 INTEL_VGA_DEVICE(0x0A1A, &intel_haswell_d_info), /* ULT GT2 server */
383 INTEL_VGA_DEVICE(0x0A2A, &intel_haswell_d_info), /* ULT GT2 server */
384 INTEL_VGA_DEVICE(0x0A06, &intel_haswell_m_info), /* ULT GT1 mobile */
385 INTEL_VGA_DEVICE(0x0A16, &intel_haswell_m_info), /* ULT GT2 mobile */
386 INTEL_VGA_DEVICE(0x0A26, &intel_haswell_m_info), /* ULT GT2 mobile */
86c268ed
KG		 387 INTEL_VGA_DEVICE(0x0D02, &intel_haswell_d_info), /* CRW GT1 desktop */
388 INTEL_VGA_DEVICE(0x0D12, &intel_haswell_d_info), /* CRW GT2 desktop */
da612d88 389 INTEL_VGA_DEVICE(0x0D22, &intel_haswell_d_info), /* CRW GT2 desktop */
86c268ed
KG		 390 INTEL_VGA_DEVICE(0x0D0A, &intel_haswell_d_info), /* CRW GT1 server */
391 INTEL_VGA_DEVICE(0x0D1A, &intel_haswell_d_info), /* CRW GT2 server */
da612d88 392 INTEL_VGA_DEVICE(0x0D2A, &intel_haswell_d_info), /* CRW GT2 server */
86c268ed
KG		 393 INTEL_VGA_DEVICE(0x0D06, &intel_haswell_m_info), /* CRW GT1 mobile */
394 INTEL_VGA_DEVICE(0x0D16, &intel_haswell_m_info), /* CRW GT2 mobile */
da612d88 395 INTEL_VGA_DEVICE(0x0D26, &intel_haswell_m_info), /* CRW GT2 mobile */
ff049b6c
JB		 396 INTEL_VGA_DEVICE(0x0f30, &intel_valleyview_m_info),
397 INTEL_VGA_DEVICE(0x0157, &intel_valleyview_m_info),
398 INTEL_VGA_DEVICE(0x0155, &intel_valleyview_d_info),
49ae35f2 399 {0, 0, 0}
1da177e4
LT		 400};
401
79e53945
JB		 402#if defined(CONFIG_DRM_I915_KMS)
403MODULE_DEVICE_TABLE(pci, pciidlist);
404#endif
405
0206e353 406void intel_detect_pch(struct drm_device *dev)
3bad0781
ZW		 407{
408 struct drm_i915_private *dev_priv = dev->dev_private;
409 struct pci_dev *pch;
410
411 /*
412 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
413 * make graphics device passthrough work easy for VMM, that only
414 * need to expose ISA bridge to let driver know the real hardware
415 * underneath. This is a requirement from virtualization team.
416 */
417 pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
418 if (pch) {
419 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
17a303ec 420 unsigned short id;
3bad0781 421 id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
17a303ec 422 dev_priv->pch_id = id;
3bad0781 423
90711d50
JB		 424 if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
425 dev_priv->pch_type = PCH_IBX;
ee7b9f93 426 dev_priv->num_pch_pll = 2;
90711d50 427 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
7fcb83cd 428 WARN_ON(!IS_GEN5(dev));
90711d50 429 } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
3bad0781 430 dev_priv->pch_type = PCH_CPT;
ee7b9f93 431 dev_priv->num_pch_pll = 2;
3bad0781 432 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
7fcb83cd 433 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
c792513b
JB		 434 } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
435 /* PantherPoint is CPT compatible */
436 dev_priv->pch_type = PCH_CPT;
ee7b9f93 437 dev_priv->num_pch_pll = 2;
c792513b 438 DRM_DEBUG_KMS("Found PatherPoint PCH\n");
7fcb83cd 439 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
eb877ebf
ED		 440 } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
441 dev_priv->pch_type = PCH_LPT;
ee7b9f93 442 dev_priv->num_pch_pll = 0;
eb877ebf 443 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
7fcb83cd 444 WARN_ON(!IS_HASWELL(dev));
ae6935dd
WSC		 445 } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
446 dev_priv->pch_type = PCH_LPT;
447 dev_priv->num_pch_pll = 0;
448 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
449 WARN_ON(!IS_HASWELL(dev));
3bad0781 450 }
ee7b9f93 451 BUG_ON(dev_priv->num_pch_pll > I915_NUM_PLLS);
3bad0781
ZW		 452 }
453 pci_dev_put(pch);
454 }
455}
456
2911a35b
BW		 457bool i915_semaphore_is_enabled(struct drm_device *dev)
458{
459 if (INTEL_INFO(dev)->gen < 6)
460 return 0;
461
462 if (i915_semaphores >= 0)
463 return i915_semaphores;
464
59de3295 465#ifdef CONFIG_INTEL_IOMMU
2911a35b 466 /* Enable semaphores on SNB when IO remapping is off */
59de3295
DV		 467 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
468 return false;
469#endif
2911a35b
BW		 470
471 return 1;
472}
473
84b79f8d 474static int i915_drm_freeze(struct drm_device *dev)
ba8bbcf6 475{
61caf87c
RW		 476 struct drm_i915_private *dev_priv = dev->dev_private;
477
b8efb17b
ZR		 478 /* ignore lid events during suspend */
479 mutex_lock(&dev_priv->modeset_restore_lock);
480 dev_priv->modeset_restore = MODESET_SUSPENDED;
481 mutex_unlock(&dev_priv->modeset_restore_lock);
482
cb10799c
PZ		 483 intel_set_power_well(dev, true);
484
5bcf719b
DA		 485 drm_kms_helper_poll_disable(dev);
486
ba8bbcf6 487 pci_save_state(dev->pdev);
ba8bbcf6 488
5669fcac 489 /* If KMS is active, we do the leavevt stuff here */
226485e9 490 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
84b79f8d
RW		 491 int error = i915_gem_idle(dev);
492 if (error) {
226485e9 493 dev_err(&dev->pdev->dev,
84b79f8d
RW		 494 "GEM idle failed, resume might fail\n");
495 return error;
496 }
a261b246 497
1a01ab3b
JB		 498 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
499
a261b246
DV		 500 intel_modeset_disable(dev);
501
226485e9 502 drm_irq_uninstall(dev);
15239099 503 dev_priv->enable_hotplug_processing = false;
5669fcac
JB		 504 }
505
9e06dd39
JB		 506 i915_save_state(dev);
507
44834a67 508 intel_opregion_fini(dev);
8ee1c3db 509
3fa016a0
DA		 510 console_lock();
511 intel_fbdev_set_suspend(dev, 1);
512 console_unlock();
513
61caf87c 514 return 0;
84b79f8d
RW		 515}
516
6a9ee8af 517int i915_suspend(struct drm_device *dev, pm_message_t state)
84b79f8d
RW		 518{
519 int error;
520
521 if (!dev || !dev->dev_private) {
522 DRM_ERROR("dev: %p\n", dev);
523 DRM_ERROR("DRM not initialized, aborting suspend.\n");
524 return -ENODEV;
525 }
526
527 if (state.event == PM_EVENT_PRETHAW)
528 return 0;
529
5bcf719b
DA		 530
531 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
532 return 0;
6eecba33 533
84b79f8d
RW		 534 error = i915_drm_freeze(dev);
535 if (error)
536 return error;
537
b932ccb5
DA		 538 if (state.event == PM_EVENT_SUSPEND) {
539 /* Shut down the device */
540 pci_disable_device(dev->pdev);
541 pci_set_power_state(dev->pdev, PCI_D3hot);
542 }
ba8bbcf6
JB		 543
544 return 0;
545}
546
073f34d9
JB		 547void intel_console_resume(struct work_struct *work)
548{
549 struct drm_i915_private *dev_priv =
550 container_of(work, struct drm_i915_private,
551 console_resume_work);
552 struct drm_device *dev = dev_priv->dev;
553
554 console_lock();
555 intel_fbdev_set_suspend(dev, 0);
556 console_unlock();
557}
558
1abd02e2 559static int __i915_drm_thaw(struct drm_device *dev)
ba8bbcf6 560{
5669fcac 561 struct drm_i915_private *dev_priv = dev->dev_private;
84b79f8d 562 int error = 0;
8ee1c3db 563
61caf87c 564 i915_restore_state(dev);
44834a67 565 intel_opregion_setup(dev);
61caf87c 566
5669fcac
JB		 567 /* KMS EnterVT equivalent */
568 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
dde86e2d 569 intel_init_pch_refclk(dev);
1833b134 570
5669fcac
JB		 571 mutex_lock(&dev->struct_mutex);
572 dev_priv->mm.suspended = 0;
573
f691e2f4 574 error = i915_gem_init_hw(dev);
5669fcac 575 mutex_unlock(&dev->struct_mutex);
226485e9 576
15239099
DV		 577 /* We need working interrupts for modeset enabling ... */
578 drm_irq_install(dev);
579
1833b134 580 intel_modeset_init_hw(dev);
45e2b5f6 581 intel_modeset_setup_hw_state(dev, false);
15239099
DV		 582
583 /*
584 * ... but also need to make sure that hotplug processing
585 * doesn't cause havoc. Like in the driver load code we don't
586 * bother with the tiny race here where we might loose hotplug
587 * notifications.
588 * */
20afbda2 589 intel_hpd_init(dev);
15239099 590 dev_priv->enable_hotplug_processing = true;
d5bb081b 591 }
1daed3fb 592
44834a67
CW		 593 intel_opregion_init(dev);
594
073f34d9
JB		 595 /*
596 * The console lock can be pretty contented on resume due
597 * to all the printk activity. Try to keep it out of the hot
598 * path of resume if possible.
599 */
600 if (console_trylock()) {
601 intel_fbdev_set_suspend(dev, 0);
602 console_unlock();
603 } else {
604 schedule_work(&dev_priv->console_resume_work);
605 }
606
b8efb17b
ZR		 607 mutex_lock(&dev_priv->modeset_restore_lock);
608 dev_priv->modeset_restore = MODESET_DONE;
609 mutex_unlock(&dev_priv->modeset_restore_lock);
84b79f8d
RW		 610 return error;
611}
612
1abd02e2
JB		 613static int i915_drm_thaw(struct drm_device *dev)
614{
615 int error = 0;
616
617 intel_gt_reset(dev);
618
619 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
620 mutex_lock(&dev->struct_mutex);
621 i915_gem_restore_gtt_mappings(dev);
622 mutex_unlock(&dev->struct_mutex);
623 }
624
625 __i915_drm_thaw(dev);
626
84b79f8d
RW		 627 return error;
628}
629
6a9ee8af 630int i915_resume(struct drm_device *dev)
84b79f8d 631{
1abd02e2 632 struct drm_i915_private *dev_priv = dev->dev_private;
6eecba33
CW		 633 int ret;
634
5bcf719b
DA		 635 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
636 return 0;
637
84b79f8d
RW		 638 if (pci_enable_device(dev->pdev))
639 return -EIO;
640
641 pci_set_master(dev->pdev);
642
1abd02e2
JB		 643 intel_gt_reset(dev);
644
645 /*
646 * Platforms with opregion should have sane BIOS, older ones (gen3 and
647 * earlier) need this since the BIOS might clear all our scratch PTEs.
648 */
649 if (drm_core_check_feature(dev, DRIVER_MODESET) &&
650 !dev_priv->opregion.header) {
651 mutex_lock(&dev->struct_mutex);
652 i915_gem_restore_gtt_mappings(dev);
653 mutex_unlock(&dev->struct_mutex);
654 }
655
656 ret = __i915_drm_thaw(dev);
6eecba33
CW		 657 if (ret)
658 return ret;
659
660 drm_kms_helper_poll_enable(dev);
661 return 0;
ba8bbcf6
JB		 662}
663
d4b8bb2a 664static int i8xx_do_reset(struct drm_device *dev)
dc96e9b8
CW		 665{
666 struct drm_i915_private *dev_priv = dev->dev_private;
667
668 if (IS_I85X(dev))
669 return -ENODEV;
670
671 I915_WRITE(D_STATE, I915_READ(D_STATE) | DSTATE_GFX_RESET_I830);
672 POSTING_READ(D_STATE);
673
674 if (IS_I830(dev) || IS_845G(dev)) {
675 I915_WRITE(DEBUG_RESET_I830,
676 DEBUG_RESET_DISPLAY |
677 DEBUG_RESET_RENDER |
678 DEBUG_RESET_FULL);
679 POSTING_READ(DEBUG_RESET_I830);
680 msleep(1);
681
682 I915_WRITE(DEBUG_RESET_I830, 0);
683 POSTING_READ(DEBUG_RESET_I830);
684 }
685
686 msleep(1);
687
688 I915_WRITE(D_STATE, I915_READ(D_STATE) & ~DSTATE_GFX_RESET_I830);
689 POSTING_READ(D_STATE);
690
691 return 0;
692}
693
f49f0586
KG		 694static int i965_reset_complete(struct drm_device *dev)
695{
696 u8 gdrst;
eeccdcac 697 pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
5fe9fe8c 698 return (gdrst & GRDOM_RESET_ENABLE) == 0;
f49f0586
KG		 699}
700
d4b8bb2a 701static int i965_do_reset(struct drm_device *dev)
0573ed4a 702{
5ccce180 703 int ret;
0573ed4a
KG		 704 u8 gdrst;
705
ae681d96
CW		 706 /*
707 * Set the domains we want to reset (GRDOM/bits 2 and 3) as
708 * well as the reset bit (GR/bit 0). Setting the GR bit
709 * triggers the reset; when done, the hardware will clear it.
710 */
0573ed4a 711 pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
d4b8bb2a 712 pci_write_config_byte(dev->pdev, I965_GDRST,
5ccce180
DV		 713 gdrst | GRDOM_RENDER |
714 GRDOM_RESET_ENABLE);
715 ret = wait_for(i965_reset_complete(dev), 500);
716 if (ret)
717 return ret;
718
719 /* We can't reset render&media without also resetting display ... */
720 pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
721 pci_write_config_byte(dev->pdev, I965_GDRST,
722 gdrst | GRDOM_MEDIA |
723 GRDOM_RESET_ENABLE);
0573ed4a
KG		 724
725 return wait_for(i965_reset_complete(dev), 500);
726}
727
d4b8bb2a 728static int ironlake_do_reset(struct drm_device *dev)
0573ed4a
KG		 729{
730 struct drm_i915_private *dev_priv = dev->dev_private;
5ccce180
DV		 731 u32 gdrst;
732 int ret;
733
734 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
735 I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
736 gdrst | GRDOM_RENDER | GRDOM_RESET_ENABLE);
737 ret = wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
738 if (ret)
739 return ret;
740
741 /* We can't reset render&media without also resetting display ... */
742 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
d4b8bb2a 743 I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
5ccce180 744 gdrst | GRDOM_MEDIA | GRDOM_RESET_ENABLE);
0573ed4a 745 return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
ba8bbcf6
JB		 746}
747
d4b8bb2a 748static int gen6_do_reset(struct drm_device *dev)
cff458c2
EA		 749{
750 struct drm_i915_private *dev_priv = dev->dev_private;
b6e45f86
KP		 751 int ret;
752 unsigned long irqflags;
cff458c2 753
286fed41
KP		 754 /* Hold gt_lock across reset to prevent any register access
755 * with forcewake not set correctly
756 */
b6e45f86 757 spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
286fed41
KP		 758
759 /* Reset the chip */
760
761 /* GEN6_GDRST is not in the gt power well, no need to check
762 * for fifo space for the write or forcewake the chip for
763 * the read
764 */
765 I915_WRITE_NOTRACE(GEN6_GDRST, GEN6_GRDOM_FULL);
766
767 /* Spin waiting for the device to ack the reset request */
768 ret = wait_for((I915_READ_NOTRACE(GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500);
769
770 /* If reset with a user forcewake, try to restore, otherwise turn it off */
b6e45f86 771 if (dev_priv->forcewake_count)
990bbdad 772 dev_priv->gt.force_wake_get(dev_priv);
286fed41 773 else
990bbdad 774 dev_priv->gt.force_wake_put(dev_priv);
286fed41
KP		 775
776 /* Restore fifo count */
777 dev_priv->gt_fifo_count = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
778
b6e45f86
KP		 779 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
780 return ret;
cff458c2
EA		 781}
782
8e96d9c4 783int intel_gpu_reset(struct drm_device *dev)
350d2706 784{
2b9dc9a2 785 struct drm_i915_private *dev_priv = dev->dev_private;
350d2706
DV		 786 int ret = -ENODEV;
787
788 switch (INTEL_INFO(dev)->gen) {
789 case 7:
790 case 6:
d4b8bb2a 791 ret = gen6_do_reset(dev);
350d2706
DV		 792 break;
793 case 5:
d4b8bb2a 794 ret = ironlake_do_reset(dev);
350d2706
DV		 795 break;
796 case 4:
d4b8bb2a 797 ret = i965_do_reset(dev);
350d2706
DV		 798 break;
799 case 2:
d4b8bb2a 800 ret = i8xx_do_reset(dev);
350d2706
DV		 801 break;
802 }
803
2b9dc9a2 804 /* Also reset the gpu hangman. */
99584db3 805 if (dev_priv->gpu_error.stop_rings) {
2b9dc9a2 806 DRM_DEBUG("Simulated gpu hang, resetting stop_rings\n");
99584db3 807 dev_priv->gpu_error.stop_rings = 0;
2b9dc9a2
DV		 808 if (ret == -ENODEV) {
809 DRM_ERROR("Reset not implemented, but ignoring "
810 "error for simulated gpu hangs\n");
811 ret = 0;
812 }
813 }
814
350d2706
DV		 815 return ret;
816}
817
11ed50ec 818/**
f3953dcb 819 * i915_reset - reset chip after a hang
11ed50ec 820 * @dev: drm device to reset
11ed50ec
BG		 821 *
822 * Reset the chip. Useful if a hang is detected. Returns zero on successful
823 * reset or otherwise an error code.
824 *
825 * Procedure is fairly simple:
826 * - reset the chip using the reset reg
827 * - re-init context state
828 * - re-init hardware status page
829 * - re-init ring buffer
830 * - re-init interrupt state
831 * - re-init display
832 */
d4b8bb2a 833int i915_reset(struct drm_device *dev)
11ed50ec
BG		 834{
835 drm_i915_private_t *dev_priv = dev->dev_private;
0573ed4a 836 int ret;
11ed50ec 837
d78cb50b
CW		 838 if (!i915_try_reset)
839 return 0;
840
d54a02c0 841 mutex_lock(&dev->struct_mutex);
11ed50ec 842
069efc1d 843 i915_gem_reset(dev);
77f01230 844
f803aa55 845 ret = -ENODEV;
99584db3 846 if (get_seconds() - dev_priv->gpu_error.last_reset < 5)
ae681d96 847 DRM_ERROR("GPU hanging too fast, declaring wedged!\n");
350d2706 848 else
d4b8bb2a 849 ret = intel_gpu_reset(dev);
350d2706 850
99584db3 851 dev_priv->gpu_error.last_reset = get_seconds();
0573ed4a 852 if (ret) {
f803aa55 853 DRM_ERROR("Failed to reset chip.\n");
f953c935 854 mutex_unlock(&dev->struct_mutex);
f803aa55 855 return ret;
11ed50ec
BG		 856 }
857
858 /* Ok, now get things going again... */
859
860 /*
861 * Everything depends on having the GTT running, so we need to start
862 * there. Fortunately we don't need to do this unless we reset the
863 * chip at a PCI level.
864 *
865 * Next we need to restore the context, but we don't use those
866 * yet either...
867 *
868 * Ring buffer needs to be re-initialized in the KMS case, or if X
869 * was running at the time of the reset (i.e. we weren't VT
870 * switched away).
871 */
872 if (drm_core_check_feature(dev, DRIVER_MODESET) ||
8187a2b7 873 !dev_priv->mm.suspended) {
b4519513
CW		 874 struct intel_ring_buffer *ring;
875 int i;
876
11ed50ec 877 dev_priv->mm.suspended = 0;
75a6898f 878
f691e2f4
DV		 879 i915_gem_init_swizzling(dev);
880
b4519513
CW		 881 for_each_ring(ring, dev_priv, i)
882 ring->init(ring);
75a6898f 883
254f965c 884 i915_gem_context_init(dev);
e21af88d
DV		 885 i915_gem_init_ppgtt(dev);
886
8e88a2bd
DV		 887 /*
888 * It would make sense to re-init all the other hw state, at
889 * least the rps/rc6/emon init done within modeset_init_hw. For
890 * some unknown reason, this blows up my ilk, so don't.
891 */
f817586c 892
8e88a2bd 893 mutex_unlock(&dev->struct_mutex);
f817586c 894
11ed50ec
BG		 895 drm_irq_uninstall(dev);
896 drm_irq_install(dev);
20afbda2 897 intel_hpd_init(dev);
bcbc324a
DV		 898 } else {
899 mutex_unlock(&dev->struct_mutex);
11ed50ec
BG		 900 }
901
11ed50ec
BG		 902 return 0;
903}
904
56550d94 905static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
112b715e 906{
01a06850
DV		 907 struct intel_device_info *intel_info =
908 (struct intel_device_info *) ent->driver_data;
909
70b12bb4 910 if (intel_info->is_valleyview)
0a3af268
RV		 911 if(!i915_preliminary_hw_support) {
912 DRM_ERROR("Preliminary hardware support disabled\n");
913 return -ENODEV;
914 }
915
5fe49d86
CW		 916 /* Only bind to function 0 of the device. Early generations
917 * used function 1 as a placeholder for multi-head. This causes
918 * us confusion instead, especially on the systems where both
919 * functions have the same PCI-ID!
920 */
921 if (PCI_FUNC(pdev->devfn))
922 return -ENODEV;
923
01a06850
DV		 924 /* We've managed to ship a kms-enabled ddx that shipped with an XvMC
925 * implementation for gen3 (and only gen3) that used legacy drm maps
926 * (gasp!) to share buffers between X and the client. Hence we need to
927 * keep around the fake agp stuff for gen3, even when kms is enabled. */
928 if (intel_info->gen != 3) {
929 driver.driver_features &=
930 ~(DRIVER_USE_AGP | DRIVER_REQUIRE_AGP);
931 } else if (!intel_agp_enabled) {
932 DRM_ERROR("drm/i915 can't work without intel_agp module!\n");
933 return -ENODEV;
934 }
935
dcdb1674 936 return drm_get_pci_dev(pdev, ent, &driver);
112b715e
KH		 937}
938
939static void
940i915_pci_remove(struct pci_dev *pdev)
941{
942 struct drm_device *dev = pci_get_drvdata(pdev);
943
944 drm_put_dev(dev);
945}
946
84b79f8d 947static int i915_pm_suspend(struct device *dev)
112b715e 948{
84b79f8d
RW		 949 struct pci_dev *pdev = to_pci_dev(dev);
950 struct drm_device *drm_dev = pci_get_drvdata(pdev);
951 int error;
112b715e 952
84b79f8d
RW		 953 if (!drm_dev || !drm_dev->dev_private) {
954 dev_err(dev, "DRM not initialized, aborting suspend.\n");
955 return -ENODEV;
956 }
112b715e 957
5bcf719b
DA		 958 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
959 return 0;
960
84b79f8d
RW		 961 error = i915_drm_freeze(drm_dev);
962 if (error)
963 return error;
112b715e 964
84b79f8d
RW		 965 pci_disable_device(pdev);
966 pci_set_power_state(pdev, PCI_D3hot);
cbda12d7 967
84b79f8d 968 return 0;
cbda12d7
ZW		 969}
970
84b79f8d 971static int i915_pm_resume(struct device *dev)
cbda12d7 972{
84b79f8d
RW		 973 struct pci_dev *pdev = to_pci_dev(dev);
974 struct drm_device *drm_dev = pci_get_drvdata(pdev);
975
976 return i915_resume(drm_dev);
cbda12d7
ZW		 977}
978
84b79f8d 979static int i915_pm_freeze(struct device *dev)
cbda12d7 980{
84b79f8d
RW		 981 struct pci_dev *pdev = to_pci_dev(dev);
982 struct drm_device *drm_dev = pci_get_drvdata(pdev);
983
984 if (!drm_dev || !drm_dev->dev_private) {
985 dev_err(dev, "DRM not initialized, aborting suspend.\n");
986 return -ENODEV;
987 }
988
989 return i915_drm_freeze(drm_dev);
cbda12d7
ZW		 990}
991
84b79f8d 992static int i915_pm_thaw(struct device *dev)
cbda12d7 993{
84b79f8d
RW		 994 struct pci_dev *pdev = to_pci_dev(dev);
995 struct drm_device *drm_dev = pci_get_drvdata(pdev);
996
997 return i915_drm_thaw(drm_dev);
cbda12d7
ZW		 998}
999
84b79f8d 1000static int i915_pm_poweroff(struct device *dev)
cbda12d7 1001{
84b79f8d
RW		 1002 struct pci_dev *pdev = to_pci_dev(dev);
1003 struct drm_device *drm_dev = pci_get_drvdata(pdev);
84b79f8d 1004
61caf87c 1005 return i915_drm_freeze(drm_dev);
cbda12d7
ZW		 1006}
1007
b4b78d12 1008static const struct dev_pm_ops i915_pm_ops = {
0206e353
AJ		 1009 .suspend = i915_pm_suspend,
1010 .resume = i915_pm_resume,
1011 .freeze = i915_pm_freeze,
1012 .thaw = i915_pm_thaw,
1013 .poweroff = i915_pm_poweroff,
1014 .restore = i915_pm_resume,
cbda12d7
ZW		 1015};
1016
78b68556 1017static const struct vm_operations_struct i915_gem_vm_ops = {
de151cf6 1018 .fault = i915_gem_fault,
ab00b3e5
JB		 1019 .open = drm_gem_vm_open,
1020 .close = drm_gem_vm_close,
de151cf6
JB		 1021};
1022
e08e96de
AV		 1023static const struct file_operations i915_driver_fops = {
1024 .owner = THIS_MODULE,
1025 .open = drm_open,
1026 .release = drm_release,
1027 .unlocked_ioctl = drm_ioctl,
1028 .mmap = drm_gem_mmap,
1029 .poll = drm_poll,
1030 .fasync = drm_fasync,
1031 .read = drm_read,
1032#ifdef CONFIG_COMPAT
1033 .compat_ioctl = i915_compat_ioctl,
1034#endif
1035 .llseek = noop_llseek,
1036};
1037
1da177e4 1038static struct drm_driver driver = {
0c54781b
MW		 1039 /* Don't use MTRRs here; the Xserver or userspace app should
1040 * deal with them for Intel hardware.
792d2b9a 1041 */
673a394b
EA		 1042 .driver_features =
1043 DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR |*/
1286ff73 1044 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME,
22eae947 1045 .load = i915_driver_load,
ba8bbcf6 1046 .unload = i915_driver_unload,
673a394b 1047 .open = i915_driver_open,
22eae947
DA		 1048 .lastclose = i915_driver_lastclose,
1049 .preclose = i915_driver_preclose,
673a394b 1050 .postclose = i915_driver_postclose,
d8e29209
RW		 1051
1052 /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
1053 .suspend = i915_suspend,
1054 .resume = i915_resume,
1055
cda17380 1056 .device_is_agp = i915_driver_device_is_agp,
7c1c2871
DA		 1057 .master_create = i915_master_create,
1058 .master_destroy = i915_master_destroy,
955b12de 1059#if defined(CONFIG_DEBUG_FS)
27c202ad
BG		 1060 .debugfs_init = i915_debugfs_init,
1061 .debugfs_cleanup = i915_debugfs_cleanup,
955b12de 1062#endif
673a394b
EA		 1063 .gem_init_object = i915_gem_init_object,
1064 .gem_free_object = i915_gem_free_object,
de151cf6 1065 .gem_vm_ops = &i915_gem_vm_ops,
1286ff73
DV		 1066
1067 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1068 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1069 .gem_prime_export = i915_gem_prime_export,
1070 .gem_prime_import = i915_gem_prime_import,
1071
ff72145b
DA		 1072 .dumb_create = i915_gem_dumb_create,
1073 .dumb_map_offset = i915_gem_mmap_gtt,
1074 .dumb_destroy = i915_gem_dumb_destroy,
1da177e4 1075 .ioctls = i915_ioctls,
e08e96de 1076 .fops = &i915_driver_fops,
22eae947
DA		 1077 .name = DRIVER_NAME,
1078 .desc = DRIVER_DESC,
1079 .date = DRIVER_DATE,
1080 .major = DRIVER_MAJOR,
1081 .minor = DRIVER_MINOR,
1082 .patchlevel = DRIVER_PATCHLEVEL,
1da177e4
LT		 1083};
1084
8410ea3b
DA		 1085static struct pci_driver i915_pci_driver = {
1086 .name = DRIVER_NAME,
1087 .id_table = pciidlist,
1088 .probe = i915_pci_probe,
1089 .remove = i915_pci_remove,
1090 .driver.pm = &i915_pm_ops,
1091};
1092
1da177e4
LT		 1093static int __init i915_init(void)
1094{
1095 driver.num_ioctls = i915_max_ioctl;
79e53945
JB		 1096
1097 /*
1098 * If CONFIG_DRM_I915_KMS is set, default to KMS unless
1099 * explicitly disabled with the module pararmeter.
1100 *
1101 * Otherwise, just follow the parameter (defaulting to off).
1102 *
1103 * Allow optional vga_text_mode_force boot option to override
1104 * the default behavior.
1105 */
1106#if defined(CONFIG_DRM_I915_KMS)
1107 if (i915_modeset != 0)
1108 driver.driver_features |= DRIVER_MODESET;
1109#endif
1110 if (i915_modeset == 1)
1111 driver.driver_features |= DRIVER_MODESET;
1112
1113#ifdef CONFIG_VGA_CONSOLE
1114 if (vgacon_text_force() && i915_modeset == -1)
1115 driver.driver_features &= ~DRIVER_MODESET;
1116#endif
1117
3885c6bb
CW		 1118 if (!(driver.driver_features & DRIVER_MODESET))
1119 driver.get_vblank_timestamp = NULL;
1120
8410ea3b 1121 return drm_pci_init(&driver, &i915_pci_driver);
1da177e4
LT		 1122}
1123
1124static void __exit i915_exit(void)
1125{
8410ea3b 1126 drm_pci_exit(&driver, &i915_pci_driver);
1da177e4
LT		 1127}
1128
1129module_init(i915_init);
1130module_exit(i915_exit);
1131
b5e89ed5
DA		 1132MODULE_AUTHOR(DRIVER_AUTHOR);
1133MODULE_DESCRIPTION(DRIVER_DESC);
1da177e4 1134MODULE_LICENSE("GPL and additional rights");
f7000883 1135
b7d84096
JB		 1136/* We give fast paths for the really cool registers */
1137#define NEEDS_FORCE_WAKE(dev_priv, reg) \
b7884eb4
DV		 1138 ((HAS_FORCE_WAKE((dev_priv)->dev)) && \
1139 ((reg) < 0x40000) && \
1140 ((reg) != FORCEWAKE))
a8b1397d
DV		 1141static void
1142ilk_dummy_write(struct drm_i915_private *dev_priv)
1143{
1144 /* WaIssueDummyWriteToWakeupFromRC6: Issue a dummy write to wake up the
1145 * chip from rc6 before touching it for real. MI_MODE is masked, hence
1146 * harmless to write 0 into. */
1147 I915_WRITE_NOTRACE(MI_MODE, 0);
1148}
1149
f7000883
AK		 1150#define __i915_read(x, y) \
1151u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
1152 u##x val = 0; \
a8b1397d
DV		 1153 if (IS_GEN5(dev_priv->dev)) \
1154 ilk_dummy_write(dev_priv); \
f7000883 1155 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
c937504e
KP		 1156 unsigned long irqflags; \
1157 spin_lock_irqsave(&dev_priv->gt_lock, irqflags); \
1158 if (dev_priv->forcewake_count == 0) \
990bbdad 1159 dev_priv->gt.force_wake_get(dev_priv); \
f7000883 1160 val = read##y(dev_priv->regs + reg); \
c937504e 1161 if (dev_priv->forcewake_count == 0) \
990bbdad 1162 dev_priv->gt.force_wake_put(dev_priv); \
c937504e 1163 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); \
f7000883
AK		 1164 } else { \
1165 val = read##y(dev_priv->regs + reg); \
1166 } \
1167 trace_i915_reg_rw(false, reg, val, sizeof(val)); \
1168 return val; \
1169}
1170
1171__i915_read(8, b)
1172__i915_read(16, w)
1173__i915_read(32, l)
1174__i915_read(64, q)
1175#undef __i915_read
1176
1177#define __i915_write(x, y) \
1178void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
67a3744f 1179 u32 __fifo_ret = 0; \
f7000883
AK		 1180 trace_i915_reg_rw(true, reg, val, sizeof(val)); \
1181 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
67a3744f 1182 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
f7000883 1183 } \
a8b1397d
DV		 1184 if (IS_GEN5(dev_priv->dev)) \
1185 ilk_dummy_write(dev_priv); \
c54e5904
PZ		 1186 if (IS_HASWELL(dev_priv->dev) && (I915_READ_NOTRACE(GEN7_ERR_INT) & ERR_INT_MMIO_UNCLAIMED)) { \
1187 DRM_ERROR("Unknown unclaimed register before writing to %x\n", reg); \
1188 I915_WRITE_NOTRACE(GEN7_ERR_INT, ERR_INT_MMIO_UNCLAIMED); \
1189 } \
fe31b574 1190 write##y(val, dev_priv->regs + reg); \
67a3744f
BW		 1191 if (unlikely(__fifo_ret)) { \
1192 gen6_gt_check_fifodbg(dev_priv); \
1193 } \
b4c145c1
BW		 1194 if (IS_HASWELL(dev_priv->dev) && (I915_READ_NOTRACE(GEN7_ERR_INT) & ERR_INT_MMIO_UNCLAIMED)) { \
1195 DRM_ERROR("Unclaimed write to %x\n", reg); \
1196 writel(ERR_INT_MMIO_UNCLAIMED, dev_priv->regs + GEN7_ERR_INT); \
1197 } \
f7000883
AK		 1198}
1199__i915_write(8, b)
1200__i915_write(16, w)
1201__i915_write(32, l)
1202__i915_write(64, q)
1203#undef __i915_write
c0c7babc
BW		 1204
1205static const struct register_whitelist {
1206 uint64_t offset;
1207 uint32_t size;
1208 uint32_t gen_bitmask; /* support gens, 0x10 for 4, 0x30 for 4 and 5, etc. */
1209} whitelist[] = {
1210 { RING_TIMESTAMP(RENDER_RING_BASE), 8, 0xF0 },
1211};
1212
1213int i915_reg_read_ioctl(struct drm_device *dev,
1214 void *data, struct drm_file *file)
1215{
1216 struct drm_i915_private *dev_priv = dev->dev_private;
1217 struct drm_i915_reg_read *reg = data;
1218 struct register_whitelist const *entry = whitelist;
1219 int i;
1220
1221 for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) {
1222 if (entry->offset == reg->offset &&
1223 (1 << INTEL_INFO(dev)->gen & entry->gen_bitmask))
1224 break;
1225 }
1226
1227 if (i == ARRAY_SIZE(whitelist))
1228 return -EINVAL;
1229
1230 switch (entry->size) {
1231 case 8:
1232 reg->val = I915_READ64(reg->offset);
1233 break;
1234 case 4:
1235 reg->val = I915_READ(reg->offset);
1236 break;
1237 case 2:
1238 reg->val = I915_READ16(reg->offset);
1239 break;
1240 case 1:
1241 reg->val = I915_READ8(reg->offset);
1242 break;
1243 default:
1244 WARN_ON(1);
1245 return -EINVAL;
1246 }
1247
1248 return 0;
1249}
Linux kernel - Deliverables
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