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1da177e4 LT |
1 | /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*- |
2 | */ | |
0d6aa60b | 3 | /* |
bc54fd1a | 4 | * |
1da177e4 LT |
5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
6 | * All Rights Reserved. | |
bc54fd1a DA |
7 | * |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the | |
10 | * "Software"), to deal in the Software without restriction, including | |
11 | * without limitation the rights to use, copy, modify, merge, publish, | |
12 | * distribute, sub license, and/or sell copies of the Software, and to | |
13 | * permit persons to whom the Software is furnished to do so, subject to | |
14 | * the following conditions: | |
15 | * | |
16 | * The above copyright notice and this permission notice (including the | |
17 | * next paragraph) shall be included in all copies or substantial portions | |
18 | * of the Software. | |
19 | * | |
20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
27 | * | |
0d6aa60b | 28 | */ |
1da177e4 | 29 | |
5669fcac | 30 | #include <linux/device.h> |
e5747e3a | 31 | #include <linux/acpi.h> |
760285e7 DH |
32 | #include <drm/drmP.h> |
33 | #include <drm/i915_drm.h> | |
1da177e4 | 34 | #include "i915_drv.h" |
990bbdad | 35 | #include "i915_trace.h" |
f49f0586 | 36 | #include "intel_drv.h" |
1da177e4 | 37 | |
79e53945 | 38 | #include <linux/console.h> |
e0cd3608 | 39 | #include <linux/module.h> |
d6102977 | 40 | #include <linux/pm_runtime.h> |
760285e7 | 41 | #include <drm/drm_crtc_helper.h> |
79e53945 | 42 | |
112b715e KH |
43 | static struct drm_driver driver; |
44 | ||
a57c774a AK |
45 | #define GEN_DEFAULT_PIPEOFFSETS \ |
46 | .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \ | |
47 | PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \ | |
48 | .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \ | |
49 | TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \ | |
a57c774a AK |
50 | .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET } |
51 | ||
84fd4f4e RB |
52 | #define GEN_CHV_PIPEOFFSETS \ |
53 | .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \ | |
54 | CHV_PIPE_C_OFFSET }, \ | |
55 | .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \ | |
56 | CHV_TRANSCODER_C_OFFSET, }, \ | |
84fd4f4e RB |
57 | .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \ |
58 | CHV_PALETTE_C_OFFSET } | |
a57c774a | 59 | |
5efb3e28 VS |
60 | #define CURSOR_OFFSETS \ |
61 | .cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET } | |
62 | ||
63 | #define IVB_CURSOR_OFFSETS \ | |
64 | .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET } | |
65 | ||
9a7e8492 | 66 | static const struct intel_device_info intel_i830_info = { |
7eb552ae | 67 | .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2, |
31578148 | 68 | .has_overlay = 1, .overlay_needs_physical = 1, |
73ae478c | 69 | .ring_mask = RENDER_RING, |
a57c774a | 70 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 71 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
72 | }; |
73 | ||
9a7e8492 | 74 | static const struct intel_device_info intel_845g_info = { |
7eb552ae | 75 | .gen = 2, .num_pipes = 1, |
31578148 | 76 | .has_overlay = 1, .overlay_needs_physical = 1, |
73ae478c | 77 | .ring_mask = RENDER_RING, |
a57c774a | 78 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 79 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
80 | }; |
81 | ||
9a7e8492 | 82 | static const struct intel_device_info intel_i85x_info = { |
7eb552ae | 83 | .gen = 2, .is_i85x = 1, .is_mobile = 1, .num_pipes = 2, |
5ce8ba7c | 84 | .cursor_needs_physical = 1, |
31578148 | 85 | .has_overlay = 1, .overlay_needs_physical = 1, |
fd70d52a | 86 | .has_fbc = 1, |
73ae478c | 87 | .ring_mask = RENDER_RING, |
a57c774a | 88 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 89 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
90 | }; |
91 | ||
9a7e8492 | 92 | static const struct intel_device_info intel_i865g_info = { |
7eb552ae | 93 | .gen = 2, .num_pipes = 1, |
31578148 | 94 | .has_overlay = 1, .overlay_needs_physical = 1, |
73ae478c | 95 | .ring_mask = RENDER_RING, |
a57c774a | 96 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 97 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
98 | }; |
99 | ||
9a7e8492 | 100 | static const struct intel_device_info intel_i915g_info = { |
7eb552ae | 101 | .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2, |
31578148 | 102 | .has_overlay = 1, .overlay_needs_physical = 1, |
73ae478c | 103 | .ring_mask = RENDER_RING, |
a57c774a | 104 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 105 | CURSOR_OFFSETS, |
cfdf1fa2 | 106 | }; |
9a7e8492 | 107 | static const struct intel_device_info intel_i915gm_info = { |
7eb552ae | 108 | .gen = 3, .is_mobile = 1, .num_pipes = 2, |
b295d1b6 | 109 | .cursor_needs_physical = 1, |
31578148 | 110 | .has_overlay = 1, .overlay_needs_physical = 1, |
a6c45cf0 | 111 | .supports_tv = 1, |
fd70d52a | 112 | .has_fbc = 1, |
73ae478c | 113 | .ring_mask = RENDER_RING, |
a57c774a | 114 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 115 | CURSOR_OFFSETS, |
cfdf1fa2 | 116 | }; |
9a7e8492 | 117 | static const struct intel_device_info intel_i945g_info = { |
7eb552ae | 118 | .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2, |
31578148 | 119 | .has_overlay = 1, .overlay_needs_physical = 1, |
73ae478c | 120 | .ring_mask = RENDER_RING, |
a57c774a | 121 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 122 | CURSOR_OFFSETS, |
cfdf1fa2 | 123 | }; |
9a7e8492 | 124 | static const struct intel_device_info intel_i945gm_info = { |
7eb552ae | 125 | .gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2, |
b295d1b6 | 126 | .has_hotplug = 1, .cursor_needs_physical = 1, |
31578148 | 127 | .has_overlay = 1, .overlay_needs_physical = 1, |
a6c45cf0 | 128 | .supports_tv = 1, |
fd70d52a | 129 | .has_fbc = 1, |
73ae478c | 130 | .ring_mask = RENDER_RING, |
a57c774a | 131 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 132 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
133 | }; |
134 | ||
9a7e8492 | 135 | static const struct intel_device_info intel_i965g_info = { |
7eb552ae | 136 | .gen = 4, .is_broadwater = 1, .num_pipes = 2, |
c96c3a8c | 137 | .has_hotplug = 1, |
31578148 | 138 | .has_overlay = 1, |
73ae478c | 139 | .ring_mask = RENDER_RING, |
a57c774a | 140 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 141 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
142 | }; |
143 | ||
9a7e8492 | 144 | static const struct intel_device_info intel_i965gm_info = { |
7eb552ae | 145 | .gen = 4, .is_crestline = 1, .num_pipes = 2, |
e3c4e5dd | 146 | .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1, |
31578148 | 147 | .has_overlay = 1, |
a6c45cf0 | 148 | .supports_tv = 1, |
73ae478c | 149 | .ring_mask = RENDER_RING, |
a57c774a | 150 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 151 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
152 | }; |
153 | ||
9a7e8492 | 154 | static const struct intel_device_info intel_g33_info = { |
7eb552ae | 155 | .gen = 3, .is_g33 = 1, .num_pipes = 2, |
c96c3a8c | 156 | .need_gfx_hws = 1, .has_hotplug = 1, |
31578148 | 157 | .has_overlay = 1, |
73ae478c | 158 | .ring_mask = RENDER_RING, |
a57c774a | 159 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 160 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
161 | }; |
162 | ||
9a7e8492 | 163 | static const struct intel_device_info intel_g45_info = { |
7eb552ae | 164 | .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2, |
c96c3a8c | 165 | .has_pipe_cxsr = 1, .has_hotplug = 1, |
73ae478c | 166 | .ring_mask = RENDER_RING | BSD_RING, |
a57c774a | 167 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 168 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
169 | }; |
170 | ||
9a7e8492 | 171 | static const struct intel_device_info intel_gm45_info = { |
7eb552ae | 172 | .gen = 4, .is_g4x = 1, .num_pipes = 2, |
e3c4e5dd | 173 | .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1, |
c96c3a8c | 174 | .has_pipe_cxsr = 1, .has_hotplug = 1, |
a6c45cf0 | 175 | .supports_tv = 1, |
73ae478c | 176 | .ring_mask = RENDER_RING | BSD_RING, |
a57c774a | 177 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 178 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
179 | }; |
180 | ||
9a7e8492 | 181 | static const struct intel_device_info intel_pineview_info = { |
7eb552ae | 182 | .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2, |
c96c3a8c | 183 | .need_gfx_hws = 1, .has_hotplug = 1, |
31578148 | 184 | .has_overlay = 1, |
a57c774a | 185 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 186 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
187 | }; |
188 | ||
9a7e8492 | 189 | static const struct intel_device_info intel_ironlake_d_info = { |
7eb552ae | 190 | .gen = 5, .num_pipes = 2, |
5a117db7 | 191 | .need_gfx_hws = 1, .has_hotplug = 1, |
73ae478c | 192 | .ring_mask = RENDER_RING | BSD_RING, |
a57c774a | 193 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 194 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
195 | }; |
196 | ||
9a7e8492 | 197 | static const struct intel_device_info intel_ironlake_m_info = { |
7eb552ae | 198 | .gen = 5, .is_mobile = 1, .num_pipes = 2, |
e3c4e5dd | 199 | .need_gfx_hws = 1, .has_hotplug = 1, |
c1a9f047 | 200 | .has_fbc = 1, |
73ae478c | 201 | .ring_mask = RENDER_RING | BSD_RING, |
a57c774a | 202 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 203 | CURSOR_OFFSETS, |
cfdf1fa2 KH |
204 | }; |
205 | ||
9a7e8492 | 206 | static const struct intel_device_info intel_sandybridge_d_info = { |
7eb552ae | 207 | .gen = 6, .num_pipes = 2, |
c96c3a8c | 208 | .need_gfx_hws = 1, .has_hotplug = 1, |
cbaef0f1 | 209 | .has_fbc = 1, |
73ae478c | 210 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING, |
3d29b842 | 211 | .has_llc = 1, |
a57c774a | 212 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 213 | CURSOR_OFFSETS, |
f6e450a6 EA |
214 | }; |
215 | ||
9a7e8492 | 216 | static const struct intel_device_info intel_sandybridge_m_info = { |
7eb552ae | 217 | .gen = 6, .is_mobile = 1, .num_pipes = 2, |
c96c3a8c | 218 | .need_gfx_hws = 1, .has_hotplug = 1, |
9c04f015 | 219 | .has_fbc = 1, |
73ae478c | 220 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING, |
3d29b842 | 221 | .has_llc = 1, |
a57c774a | 222 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 223 | CURSOR_OFFSETS, |
a13e4093 EA |
224 | }; |
225 | ||
219f4fdb BW |
226 | #define GEN7_FEATURES \ |
227 | .gen = 7, .num_pipes = 3, \ | |
228 | .need_gfx_hws = 1, .has_hotplug = 1, \ | |
cbaef0f1 | 229 | .has_fbc = 1, \ |
73ae478c | 230 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \ |
ab484f8f | 231 | .has_llc = 1 |
219f4fdb | 232 | |
c76b615c | 233 | static const struct intel_device_info intel_ivybridge_d_info = { |
219f4fdb BW |
234 | GEN7_FEATURES, |
235 | .is_ivybridge = 1, | |
a57c774a | 236 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 237 | IVB_CURSOR_OFFSETS, |
c76b615c JB |
238 | }; |
239 | ||
240 | static const struct intel_device_info intel_ivybridge_m_info = { | |
219f4fdb BW |
241 | GEN7_FEATURES, |
242 | .is_ivybridge = 1, | |
243 | .is_mobile = 1, | |
a57c774a | 244 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 245 | IVB_CURSOR_OFFSETS, |
c76b615c JB |
246 | }; |
247 | ||
999bcdea BW |
248 | static const struct intel_device_info intel_ivybridge_q_info = { |
249 | GEN7_FEATURES, | |
250 | .is_ivybridge = 1, | |
251 | .num_pipes = 0, /* legal, last one wins */ | |
a57c774a | 252 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 253 | IVB_CURSOR_OFFSETS, |
999bcdea BW |
254 | }; |
255 | ||
70a3eb7a | 256 | static const struct intel_device_info intel_valleyview_m_info = { |
219f4fdb BW |
257 | GEN7_FEATURES, |
258 | .is_mobile = 1, | |
259 | .num_pipes = 2, | |
70a3eb7a | 260 | .is_valleyview = 1, |
fba5d532 | 261 | .display_mmio_offset = VLV_DISPLAY_BASE, |
cbaef0f1 | 262 | .has_fbc = 0, /* legal, last one wins */ |
30ccd964 | 263 | .has_llc = 0, /* legal, last one wins */ |
a57c774a | 264 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 265 | CURSOR_OFFSETS, |
70a3eb7a JB |
266 | }; |
267 | ||
268 | static const struct intel_device_info intel_valleyview_d_info = { | |
219f4fdb BW |
269 | GEN7_FEATURES, |
270 | .num_pipes = 2, | |
70a3eb7a | 271 | .is_valleyview = 1, |
fba5d532 | 272 | .display_mmio_offset = VLV_DISPLAY_BASE, |
cbaef0f1 | 273 | .has_fbc = 0, /* legal, last one wins */ |
30ccd964 | 274 | .has_llc = 0, /* legal, last one wins */ |
a57c774a | 275 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 276 | CURSOR_OFFSETS, |
70a3eb7a JB |
277 | }; |
278 | ||
4cae9ae0 | 279 | static const struct intel_device_info intel_haswell_d_info = { |
219f4fdb BW |
280 | GEN7_FEATURES, |
281 | .is_haswell = 1, | |
dd93be58 | 282 | .has_ddi = 1, |
30568c45 | 283 | .has_fpga_dbg = 1, |
73ae478c | 284 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, |
a57c774a | 285 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 286 | IVB_CURSOR_OFFSETS, |
4cae9ae0 ED |
287 | }; |
288 | ||
289 | static const struct intel_device_info intel_haswell_m_info = { | |
219f4fdb BW |
290 | GEN7_FEATURES, |
291 | .is_haswell = 1, | |
292 | .is_mobile = 1, | |
dd93be58 | 293 | .has_ddi = 1, |
30568c45 | 294 | .has_fpga_dbg = 1, |
73ae478c | 295 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, |
a57c774a | 296 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 297 | IVB_CURSOR_OFFSETS, |
c76b615c JB |
298 | }; |
299 | ||
4d4dead6 | 300 | static const struct intel_device_info intel_broadwell_d_info = { |
4b30553d | 301 | .gen = 8, .num_pipes = 3, |
4d4dead6 BW |
302 | .need_gfx_hws = 1, .has_hotplug = 1, |
303 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, | |
304 | .has_llc = 1, | |
305 | .has_ddi = 1, | |
8f94d24b | 306 | .has_fbc = 1, |
a57c774a | 307 | GEN_DEFAULT_PIPEOFFSETS, |
5efb3e28 | 308 | IVB_CURSOR_OFFSETS, |
4d4dead6 BW |
309 | }; |
310 | ||
311 | static const struct intel_device_info intel_broadwell_m_info = { | |
4b30553d | 312 | .gen = 8, .is_mobile = 1, .num_pipes = 3, |
4d4dead6 BW |
313 | .need_gfx_hws = 1, .has_hotplug = 1, |
314 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, | |
315 | .has_llc = 1, | |
316 | .has_ddi = 1, | |
8f94d24b | 317 | .has_fbc = 1, |
a57c774a | 318 | GEN_DEFAULT_PIPEOFFSETS, |
15d24aa5 | 319 | IVB_CURSOR_OFFSETS, |
4d4dead6 BW |
320 | }; |
321 | ||
fd3c269f ZY |
322 | static const struct intel_device_info intel_broadwell_gt3d_info = { |
323 | .gen = 8, .num_pipes = 3, | |
324 | .need_gfx_hws = 1, .has_hotplug = 1, | |
845f74a7 | 325 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, |
fd3c269f ZY |
326 | .has_llc = 1, |
327 | .has_ddi = 1, | |
328 | .has_fbc = 1, | |
329 | GEN_DEFAULT_PIPEOFFSETS, | |
15d24aa5 | 330 | IVB_CURSOR_OFFSETS, |
fd3c269f ZY |
331 | }; |
332 | ||
333 | static const struct intel_device_info intel_broadwell_gt3m_info = { | |
334 | .gen = 8, .is_mobile = 1, .num_pipes = 3, | |
335 | .need_gfx_hws = 1, .has_hotplug = 1, | |
845f74a7 | 336 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, |
fd3c269f ZY |
337 | .has_llc = 1, |
338 | .has_ddi = 1, | |
339 | .has_fbc = 1, | |
340 | GEN_DEFAULT_PIPEOFFSETS, | |
5efb3e28 | 341 | IVB_CURSOR_OFFSETS, |
fd3c269f ZY |
342 | }; |
343 | ||
7d87a7f7 VS |
344 | static const struct intel_device_info intel_cherryview_info = { |
345 | .is_preliminary = 1, | |
07fddb14 | 346 | .gen = 8, .num_pipes = 3, |
7d87a7f7 VS |
347 | .need_gfx_hws = 1, .has_hotplug = 1, |
348 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, | |
349 | .is_valleyview = 1, | |
350 | .display_mmio_offset = VLV_DISPLAY_BASE, | |
84fd4f4e | 351 | GEN_CHV_PIPEOFFSETS, |
5efb3e28 | 352 | CURSOR_OFFSETS, |
7d87a7f7 VS |
353 | }; |
354 | ||
a0a18075 JB |
355 | /* |
356 | * Make sure any device matches here are from most specific to most | |
357 | * general. For example, since the Quanta match is based on the subsystem | |
358 | * and subvendor IDs, we need it to come before the more general IVB | |
359 | * PCI ID matches, otherwise we'll use the wrong info struct above. | |
360 | */ | |
361 | #define INTEL_PCI_IDS \ | |
362 | INTEL_I830_IDS(&intel_i830_info), \ | |
363 | INTEL_I845G_IDS(&intel_845g_info), \ | |
364 | INTEL_I85X_IDS(&intel_i85x_info), \ | |
365 | INTEL_I865G_IDS(&intel_i865g_info), \ | |
366 | INTEL_I915G_IDS(&intel_i915g_info), \ | |
367 | INTEL_I915GM_IDS(&intel_i915gm_info), \ | |
368 | INTEL_I945G_IDS(&intel_i945g_info), \ | |
369 | INTEL_I945GM_IDS(&intel_i945gm_info), \ | |
370 | INTEL_I965G_IDS(&intel_i965g_info), \ | |
371 | INTEL_G33_IDS(&intel_g33_info), \ | |
372 | INTEL_I965GM_IDS(&intel_i965gm_info), \ | |
373 | INTEL_GM45_IDS(&intel_gm45_info), \ | |
374 | INTEL_G45_IDS(&intel_g45_info), \ | |
375 | INTEL_PINEVIEW_IDS(&intel_pineview_info), \ | |
376 | INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info), \ | |
377 | INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info), \ | |
378 | INTEL_SNB_D_IDS(&intel_sandybridge_d_info), \ | |
379 | INTEL_SNB_M_IDS(&intel_sandybridge_m_info), \ | |
380 | INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */ \ | |
381 | INTEL_IVB_M_IDS(&intel_ivybridge_m_info), \ | |
382 | INTEL_IVB_D_IDS(&intel_ivybridge_d_info), \ | |
383 | INTEL_HSW_D_IDS(&intel_haswell_d_info), \ | |
384 | INTEL_HSW_M_IDS(&intel_haswell_m_info), \ | |
385 | INTEL_VLV_M_IDS(&intel_valleyview_m_info), \ | |
4d4dead6 | 386 | INTEL_VLV_D_IDS(&intel_valleyview_d_info), \ |
fd3c269f ZY |
387 | INTEL_BDW_GT12M_IDS(&intel_broadwell_m_info), \ |
388 | INTEL_BDW_GT12D_IDS(&intel_broadwell_d_info), \ | |
389 | INTEL_BDW_GT3M_IDS(&intel_broadwell_gt3m_info), \ | |
7d87a7f7 VS |
390 | INTEL_BDW_GT3D_IDS(&intel_broadwell_gt3d_info), \ |
391 | INTEL_CHV_IDS(&intel_cherryview_info) | |
a0a18075 | 392 | |
6103da0d | 393 | static const struct pci_device_id pciidlist[] = { /* aka */ |
a0a18075 | 394 | INTEL_PCI_IDS, |
49ae35f2 | 395 | {0, 0, 0} |
1da177e4 LT |
396 | }; |
397 | ||
79e53945 JB |
398 | #if defined(CONFIG_DRM_I915_KMS) |
399 | MODULE_DEVICE_TABLE(pci, pciidlist); | |
400 | #endif | |
401 | ||
0206e353 | 402 | void intel_detect_pch(struct drm_device *dev) |
3bad0781 ZW |
403 | { |
404 | struct drm_i915_private *dev_priv = dev->dev_private; | |
bcdb72ac | 405 | struct pci_dev *pch = NULL; |
3bad0781 | 406 | |
ce1bb329 BW |
407 | /* In all current cases, num_pipes is equivalent to the PCH_NOP setting |
408 | * (which really amounts to a PCH but no South Display). | |
409 | */ | |
410 | if (INTEL_INFO(dev)->num_pipes == 0) { | |
411 | dev_priv->pch_type = PCH_NOP; | |
ce1bb329 BW |
412 | return; |
413 | } | |
414 | ||
3bad0781 ZW |
415 | /* |
416 | * The reason to probe ISA bridge instead of Dev31:Fun0 is to | |
417 | * make graphics device passthrough work easy for VMM, that only | |
418 | * need to expose ISA bridge to let driver know the real hardware | |
419 | * underneath. This is a requirement from virtualization team. | |
6a9c4b35 RG |
420 | * |
421 | * In some virtualized environments (e.g. XEN), there is irrelevant | |
422 | * ISA bridge in the system. To work reliably, we should scan trhough | |
423 | * all the ISA bridge devices and check for the first match, instead | |
424 | * of only checking the first one. | |
3bad0781 | 425 | */ |
bcdb72ac | 426 | while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) { |
3bad0781 | 427 | if (pch->vendor == PCI_VENDOR_ID_INTEL) { |
bcdb72ac | 428 | unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK; |
17a303ec | 429 | dev_priv->pch_id = id; |
3bad0781 | 430 | |
90711d50 JB |
431 | if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) { |
432 | dev_priv->pch_type = PCH_IBX; | |
433 | DRM_DEBUG_KMS("Found Ibex Peak PCH\n"); | |
7fcb83cd | 434 | WARN_ON(!IS_GEN5(dev)); |
90711d50 | 435 | } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) { |
3bad0781 ZW |
436 | dev_priv->pch_type = PCH_CPT; |
437 | DRM_DEBUG_KMS("Found CougarPoint PCH\n"); | |
7fcb83cd | 438 | WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev))); |
c792513b JB |
439 | } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) { |
440 | /* PantherPoint is CPT compatible */ | |
441 | dev_priv->pch_type = PCH_CPT; | |
492ab669 | 442 | DRM_DEBUG_KMS("Found PantherPoint PCH\n"); |
7fcb83cd | 443 | WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev))); |
eb877ebf ED |
444 | } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) { |
445 | dev_priv->pch_type = PCH_LPT; | |
446 | DRM_DEBUG_KMS("Found LynxPoint PCH\n"); | |
7fcb83cd | 447 | WARN_ON(!IS_HASWELL(dev)); |
08e1413d | 448 | WARN_ON(IS_ULT(dev)); |
018f52c9 PZ |
449 | } else if (IS_BROADWELL(dev)) { |
450 | dev_priv->pch_type = PCH_LPT; | |
451 | dev_priv->pch_id = | |
452 | INTEL_PCH_LPT_LP_DEVICE_ID_TYPE; | |
453 | DRM_DEBUG_KMS("This is Broadwell, assuming " | |
454 | "LynxPoint LP PCH\n"); | |
e76e0634 BW |
455 | } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { |
456 | dev_priv->pch_type = PCH_LPT; | |
457 | DRM_DEBUG_KMS("Found LynxPoint LP PCH\n"); | |
458 | WARN_ON(!IS_HASWELL(dev)); | |
459 | WARN_ON(!IS_ULT(dev)); | |
bcdb72ac ID |
460 | } else |
461 | continue; | |
462 | ||
6a9c4b35 | 463 | break; |
3bad0781 | 464 | } |
3bad0781 | 465 | } |
6a9c4b35 | 466 | if (!pch) |
bcdb72ac ID |
467 | DRM_DEBUG_KMS("No PCH found.\n"); |
468 | ||
469 | pci_dev_put(pch); | |
3bad0781 ZW |
470 | } |
471 | ||
2911a35b BW |
472 | bool i915_semaphore_is_enabled(struct drm_device *dev) |
473 | { | |
474 | if (INTEL_INFO(dev)->gen < 6) | |
a08acaf2 | 475 | return false; |
2911a35b | 476 | |
d330a953 JN |
477 | if (i915.semaphores >= 0) |
478 | return i915.semaphores; | |
2911a35b | 479 | |
c923facd JN |
480 | /* Until we get further testing... */ |
481 | if (IS_GEN8(dev)) | |
482 | return false; | |
483 | ||
59de3295 | 484 | #ifdef CONFIG_INTEL_IOMMU |
2911a35b | 485 | /* Enable semaphores on SNB when IO remapping is off */ |
59de3295 DV |
486 | if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) |
487 | return false; | |
488 | #endif | |
2911a35b | 489 | |
a08acaf2 | 490 | return true; |
2911a35b BW |
491 | } |
492 | ||
84b79f8d | 493 | static int i915_drm_freeze(struct drm_device *dev) |
ba8bbcf6 | 494 | { |
61caf87c | 495 | struct drm_i915_private *dev_priv = dev->dev_private; |
24576d23 | 496 | struct drm_crtc *crtc; |
e5747e3a | 497 | pci_power_t opregion_target_state; |
61caf87c | 498 | |
8a187455 PZ |
499 | intel_runtime_pm_get(dev_priv); |
500 | ||
b8efb17b ZR |
501 | /* ignore lid events during suspend */ |
502 | mutex_lock(&dev_priv->modeset_restore_lock); | |
503 | dev_priv->modeset_restore = MODESET_SUSPENDED; | |
504 | mutex_unlock(&dev_priv->modeset_restore_lock); | |
505 | ||
c67a470b PZ |
506 | /* We do a lot of poking in a lot of registers, make sure they work |
507 | * properly. */ | |
da7e29bd | 508 | intel_display_set_init_power(dev_priv, true); |
cb10799c | 509 | |
5bcf719b DA |
510 | drm_kms_helper_poll_disable(dev); |
511 | ||
ba8bbcf6 | 512 | pci_save_state(dev->pdev); |
ba8bbcf6 | 513 | |
5669fcac | 514 | /* If KMS is active, we do the leavevt stuff here */ |
226485e9 | 515 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
db1b76ca DV |
516 | int error; |
517 | ||
45c5f202 | 518 | error = i915_gem_suspend(dev); |
84b79f8d | 519 | if (error) { |
226485e9 | 520 | dev_err(&dev->pdev->dev, |
84b79f8d RW |
521 | "GEM idle failed, resume might fail\n"); |
522 | return error; | |
523 | } | |
a261b246 | 524 | |
226485e9 | 525 | drm_irq_uninstall(dev); |
15239099 | 526 | dev_priv->enable_hotplug_processing = false; |
fe5b1886 | 527 | |
156c7ca0 | 528 | intel_suspend_gt_powersave(dev); |
fe5b1886 | 529 | |
24576d23 JB |
530 | /* |
531 | * Disable CRTCs directly since we want to preserve sw state | |
532 | * for _thaw. | |
533 | */ | |
6e9f798d | 534 | drm_modeset_lock_all(dev); |
f7ef3fa7 | 535 | for_each_crtc(dev, crtc) { |
24576d23 | 536 | dev_priv->display.crtc_disable(crtc); |
f7ef3fa7 | 537 | } |
6e9f798d | 538 | drm_modeset_unlock_all(dev); |
7d708ee4 ID |
539 | |
540 | intel_modeset_suspend_hw(dev); | |
5669fcac JB |
541 | } |
542 | ||
828c7908 BW |
543 | i915_gem_suspend_gtt_mappings(dev); |
544 | ||
9e06dd39 JB |
545 | i915_save_state(dev); |
546 | ||
e5747e3a JB |
547 | if (acpi_target_system_state() >= ACPI_STATE_S3) |
548 | opregion_target_state = PCI_D3cold; | |
549 | else | |
550 | opregion_target_state = PCI_D1; | |
551 | intel_opregion_notify_adapter(dev, opregion_target_state); | |
552 | ||
156c7ca0 | 553 | intel_uncore_forcewake_reset(dev, false); |
44834a67 | 554 | intel_opregion_fini(dev); |
8ee1c3db | 555 | |
3fa016a0 | 556 | console_lock(); |
b6f3eff7 | 557 | intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED); |
3fa016a0 DA |
558 | console_unlock(); |
559 | ||
62d5d69b MK |
560 | dev_priv->suspend_count++; |
561 | ||
85e90679 KCA |
562 | intel_display_set_init_power(dev_priv, false); |
563 | ||
61caf87c | 564 | return 0; |
84b79f8d RW |
565 | } |
566 | ||
6a9ee8af | 567 | int i915_suspend(struct drm_device *dev, pm_message_t state) |
84b79f8d RW |
568 | { |
569 | int error; | |
570 | ||
571 | if (!dev || !dev->dev_private) { | |
572 | DRM_ERROR("dev: %p\n", dev); | |
573 | DRM_ERROR("DRM not initialized, aborting suspend.\n"); | |
574 | return -ENODEV; | |
575 | } | |
576 | ||
577 | if (state.event == PM_EVENT_PRETHAW) | |
578 | return 0; | |
579 | ||
5bcf719b DA |
580 | |
581 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) | |
582 | return 0; | |
6eecba33 | 583 | |
84b79f8d RW |
584 | error = i915_drm_freeze(dev); |
585 | if (error) | |
586 | return error; | |
587 | ||
b932ccb5 DA |
588 | if (state.event == PM_EVENT_SUSPEND) { |
589 | /* Shut down the device */ | |
590 | pci_disable_device(dev->pdev); | |
591 | pci_set_power_state(dev->pdev, PCI_D3hot); | |
592 | } | |
ba8bbcf6 JB |
593 | |
594 | return 0; | |
595 | } | |
596 | ||
073f34d9 JB |
597 | void intel_console_resume(struct work_struct *work) |
598 | { | |
599 | struct drm_i915_private *dev_priv = | |
600 | container_of(work, struct drm_i915_private, | |
601 | console_resume_work); | |
602 | struct drm_device *dev = dev_priv->dev; | |
603 | ||
604 | console_lock(); | |
b6f3eff7 | 605 | intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING); |
073f34d9 JB |
606 | console_unlock(); |
607 | } | |
608 | ||
76c4b250 | 609 | static int i915_drm_thaw_early(struct drm_device *dev) |
ba8bbcf6 | 610 | { |
5669fcac | 611 | struct drm_i915_private *dev_priv = dev->dev_private; |
8ee1c3db | 612 | |
8abdc179 KCA |
613 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
614 | hsw_disable_pc8(dev_priv); | |
615 | ||
10018603 | 616 | intel_uncore_early_sanitize(dev, true); |
9d49c0ef | 617 | intel_uncore_sanitize(dev); |
76c4b250 ID |
618 | intel_power_domains_init_hw(dev_priv); |
619 | ||
620 | return 0; | |
621 | } | |
622 | ||
623 | static int __i915_drm_thaw(struct drm_device *dev, bool restore_gtt_mappings) | |
624 | { | |
625 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9d49c0ef PZ |
626 | |
627 | if (drm_core_check_feature(dev, DRIVER_MODESET) && | |
628 | restore_gtt_mappings) { | |
629 | mutex_lock(&dev->struct_mutex); | |
630 | i915_gem_restore_gtt_mappings(dev); | |
631 | mutex_unlock(&dev->struct_mutex); | |
632 | } | |
633 | ||
61caf87c | 634 | i915_restore_state(dev); |
44834a67 | 635 | intel_opregion_setup(dev); |
61caf87c | 636 | |
5669fcac JB |
637 | /* KMS EnterVT equivalent */ |
638 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { | |
dde86e2d | 639 | intel_init_pch_refclk(dev); |
754970ee | 640 | drm_mode_config_reset(dev); |
1833b134 | 641 | |
5669fcac | 642 | mutex_lock(&dev->struct_mutex); |
074c6ada CW |
643 | if (i915_gem_init_hw(dev)) { |
644 | DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n"); | |
645 | atomic_set_mask(I915_WEDGED, &dev_priv->gpu_error.reset_counter); | |
646 | } | |
5669fcac | 647 | mutex_unlock(&dev->struct_mutex); |
226485e9 | 648 | |
15239099 | 649 | /* We need working interrupts for modeset enabling ... */ |
bb0f1b5c | 650 | drm_irq_install(dev, dev->pdev->irq); |
15239099 | 651 | |
1833b134 | 652 | intel_modeset_init_hw(dev); |
24576d23 JB |
653 | |
654 | drm_modeset_lock_all(dev); | |
655 | intel_modeset_setup_hw_state(dev, true); | |
656 | drm_modeset_unlock_all(dev); | |
15239099 DV |
657 | |
658 | /* | |
659 | * ... but also need to make sure that hotplug processing | |
660 | * doesn't cause havoc. Like in the driver load code we don't | |
661 | * bother with the tiny race here where we might loose hotplug | |
662 | * notifications. | |
663 | * */ | |
20afbda2 | 664 | intel_hpd_init(dev); |
15239099 | 665 | dev_priv->enable_hotplug_processing = true; |
bb60b969 | 666 | /* Config may have changed between suspend and resume */ |
1ff74cf1 | 667 | drm_helper_hpd_irq_event(dev); |
d5bb081b | 668 | } |
1daed3fb | 669 | |
44834a67 CW |
670 | intel_opregion_init(dev); |
671 | ||
073f34d9 JB |
672 | /* |
673 | * The console lock can be pretty contented on resume due | |
674 | * to all the printk activity. Try to keep it out of the hot | |
675 | * path of resume if possible. | |
676 | */ | |
677 | if (console_trylock()) { | |
b6f3eff7 | 678 | intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING); |
073f34d9 JB |
679 | console_unlock(); |
680 | } else { | |
681 | schedule_work(&dev_priv->console_resume_work); | |
682 | } | |
683 | ||
b8efb17b ZR |
684 | mutex_lock(&dev_priv->modeset_restore_lock); |
685 | dev_priv->modeset_restore = MODESET_DONE; | |
686 | mutex_unlock(&dev_priv->modeset_restore_lock); | |
8a187455 | 687 | |
e5747e3a JB |
688 | intel_opregion_notify_adapter(dev, PCI_D0); |
689 | ||
8a187455 | 690 | intel_runtime_pm_put(dev_priv); |
074c6ada | 691 | return 0; |
84b79f8d RW |
692 | } |
693 | ||
1abd02e2 JB |
694 | static int i915_drm_thaw(struct drm_device *dev) |
695 | { | |
7f16e5c1 | 696 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
828c7908 | 697 | i915_check_and_clear_faults(dev); |
1abd02e2 | 698 | |
9d49c0ef | 699 | return __i915_drm_thaw(dev, true); |
84b79f8d RW |
700 | } |
701 | ||
76c4b250 | 702 | static int i915_resume_early(struct drm_device *dev) |
84b79f8d | 703 | { |
5bcf719b DA |
704 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
705 | return 0; | |
706 | ||
76c4b250 ID |
707 | /* |
708 | * We have a resume ordering issue with the snd-hda driver also | |
709 | * requiring our device to be power up. Due to the lack of a | |
710 | * parent/child relationship we currently solve this with an early | |
711 | * resume hook. | |
712 | * | |
713 | * FIXME: This should be solved with a special hdmi sink device or | |
714 | * similar so that power domains can be employed. | |
715 | */ | |
84b79f8d RW |
716 | if (pci_enable_device(dev->pdev)) |
717 | return -EIO; | |
718 | ||
719 | pci_set_master(dev->pdev); | |
720 | ||
76c4b250 ID |
721 | return i915_drm_thaw_early(dev); |
722 | } | |
723 | ||
724 | int i915_resume(struct drm_device *dev) | |
725 | { | |
726 | struct drm_i915_private *dev_priv = dev->dev_private; | |
727 | int ret; | |
728 | ||
1abd02e2 JB |
729 | /* |
730 | * Platforms with opregion should have sane BIOS, older ones (gen3 and | |
9d49c0ef PZ |
731 | * earlier) need to restore the GTT mappings since the BIOS might clear |
732 | * all our scratch PTEs. | |
1abd02e2 | 733 | */ |
9d49c0ef | 734 | ret = __i915_drm_thaw(dev, !dev_priv->opregion.header); |
6eecba33 CW |
735 | if (ret) |
736 | return ret; | |
737 | ||
738 | drm_kms_helper_poll_enable(dev); | |
739 | return 0; | |
ba8bbcf6 JB |
740 | } |
741 | ||
76c4b250 ID |
742 | static int i915_resume_legacy(struct drm_device *dev) |
743 | { | |
744 | i915_resume_early(dev); | |
745 | i915_resume(dev); | |
746 | ||
747 | return 0; | |
748 | } | |
749 | ||
11ed50ec | 750 | /** |
f3953dcb | 751 | * i915_reset - reset chip after a hang |
11ed50ec | 752 | * @dev: drm device to reset |
11ed50ec BG |
753 | * |
754 | * Reset the chip. Useful if a hang is detected. Returns zero on successful | |
755 | * reset or otherwise an error code. | |
756 | * | |
757 | * Procedure is fairly simple: | |
758 | * - reset the chip using the reset reg | |
759 | * - re-init context state | |
760 | * - re-init hardware status page | |
761 | * - re-init ring buffer | |
762 | * - re-init interrupt state | |
763 | * - re-init display | |
764 | */ | |
d4b8bb2a | 765 | int i915_reset(struct drm_device *dev) |
11ed50ec | 766 | { |
50227e1c | 767 | struct drm_i915_private *dev_priv = dev->dev_private; |
2e7c8ee7 | 768 | bool simulated; |
0573ed4a | 769 | int ret; |
11ed50ec | 770 | |
d330a953 | 771 | if (!i915.reset) |
d78cb50b CW |
772 | return 0; |
773 | ||
d54a02c0 | 774 | mutex_lock(&dev->struct_mutex); |
11ed50ec | 775 | |
069efc1d | 776 | i915_gem_reset(dev); |
77f01230 | 777 | |
2e7c8ee7 CW |
778 | simulated = dev_priv->gpu_error.stop_rings != 0; |
779 | ||
be62acb4 MK |
780 | ret = intel_gpu_reset(dev); |
781 | ||
782 | /* Also reset the gpu hangman. */ | |
783 | if (simulated) { | |
784 | DRM_INFO("Simulated gpu hang, resetting stop_rings\n"); | |
785 | dev_priv->gpu_error.stop_rings = 0; | |
786 | if (ret == -ENODEV) { | |
f2d91a2c DV |
787 | DRM_INFO("Reset not implemented, but ignoring " |
788 | "error for simulated gpu hangs\n"); | |
be62acb4 MK |
789 | ret = 0; |
790 | } | |
2e7c8ee7 | 791 | } |
be62acb4 | 792 | |
0573ed4a | 793 | if (ret) { |
f2d91a2c | 794 | DRM_ERROR("Failed to reset chip: %i\n", ret); |
f953c935 | 795 | mutex_unlock(&dev->struct_mutex); |
f803aa55 | 796 | return ret; |
11ed50ec BG |
797 | } |
798 | ||
799 | /* Ok, now get things going again... */ | |
800 | ||
801 | /* | |
802 | * Everything depends on having the GTT running, so we need to start | |
803 | * there. Fortunately we don't need to do this unless we reset the | |
804 | * chip at a PCI level. | |
805 | * | |
806 | * Next we need to restore the context, but we don't use those | |
807 | * yet either... | |
808 | * | |
809 | * Ring buffer needs to be re-initialized in the KMS case, or if X | |
810 | * was running at the time of the reset (i.e. we weren't VT | |
811 | * switched away). | |
812 | */ | |
813 | if (drm_core_check_feature(dev, DRIVER_MODESET) || | |
db1b76ca | 814 | !dev_priv->ums.mm_suspended) { |
db1b76ca | 815 | dev_priv->ums.mm_suspended = 0; |
75a6898f | 816 | |
3d57e5bd | 817 | ret = i915_gem_init_hw(dev); |
8e88a2bd | 818 | mutex_unlock(&dev->struct_mutex); |
3d57e5bd BW |
819 | if (ret) { |
820 | DRM_ERROR("Failed hw init on reset %d\n", ret); | |
821 | return ret; | |
822 | } | |
f817586c | 823 | |
e090c53b | 824 | /* |
78ad455f DV |
825 | * FIXME: This races pretty badly against concurrent holders of |
826 | * ring interrupts. This is possible since we've started to drop | |
827 | * dev->struct_mutex in select places when waiting for the gpu. | |
e090c53b | 828 | */ |
dd0a1aa1 | 829 | |
78ad455f DV |
830 | /* |
831 | * rps/rc6 re-init is necessary to restore state lost after the | |
832 | * reset and the re-install of gt irqs. Skip for ironlake per | |
dd0a1aa1 | 833 | * previous concerns that it doesn't respond well to some forms |
78ad455f DV |
834 | * of re-init after reset. |
835 | */ | |
dc1d0136 | 836 | if (INTEL_INFO(dev)->gen > 5) |
c6df39b5 | 837 | intel_reset_gt_powersave(dev); |
dd0a1aa1 | 838 | |
20afbda2 | 839 | intel_hpd_init(dev); |
bcbc324a DV |
840 | } else { |
841 | mutex_unlock(&dev->struct_mutex); | |
11ed50ec BG |
842 | } |
843 | ||
11ed50ec BG |
844 | return 0; |
845 | } | |
846 | ||
56550d94 | 847 | static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) |
112b715e | 848 | { |
01a06850 DV |
849 | struct intel_device_info *intel_info = |
850 | (struct intel_device_info *) ent->driver_data; | |
851 | ||
d330a953 | 852 | if (IS_PRELIMINARY_HW(intel_info) && !i915.preliminary_hw_support) { |
b833d685 BW |
853 | DRM_INFO("This hardware requires preliminary hardware support.\n" |
854 | "See CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT, and/or modparam preliminary_hw_support\n"); | |
855 | return -ENODEV; | |
856 | } | |
857 | ||
5fe49d86 CW |
858 | /* Only bind to function 0 of the device. Early generations |
859 | * used function 1 as a placeholder for multi-head. This causes | |
860 | * us confusion instead, especially on the systems where both | |
861 | * functions have the same PCI-ID! | |
862 | */ | |
863 | if (PCI_FUNC(pdev->devfn)) | |
864 | return -ENODEV; | |
865 | ||
24986ee0 | 866 | driver.driver_features &= ~(DRIVER_USE_AGP); |
01a06850 | 867 | |
dcdb1674 | 868 | return drm_get_pci_dev(pdev, ent, &driver); |
112b715e KH |
869 | } |
870 | ||
871 | static void | |
872 | i915_pci_remove(struct pci_dev *pdev) | |
873 | { | |
874 | struct drm_device *dev = pci_get_drvdata(pdev); | |
875 | ||
876 | drm_put_dev(dev); | |
877 | } | |
878 | ||
84b79f8d | 879 | static int i915_pm_suspend(struct device *dev) |
112b715e | 880 | { |
84b79f8d RW |
881 | struct pci_dev *pdev = to_pci_dev(dev); |
882 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
112b715e | 883 | |
84b79f8d RW |
884 | if (!drm_dev || !drm_dev->dev_private) { |
885 | dev_err(dev, "DRM not initialized, aborting suspend.\n"); | |
886 | return -ENODEV; | |
887 | } | |
112b715e | 888 | |
5bcf719b DA |
889 | if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
890 | return 0; | |
891 | ||
76c4b250 ID |
892 | return i915_drm_freeze(drm_dev); |
893 | } | |
894 | ||
895 | static int i915_pm_suspend_late(struct device *dev) | |
896 | { | |
897 | struct pci_dev *pdev = to_pci_dev(dev); | |
898 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
8abdc179 | 899 | struct drm_i915_private *dev_priv = drm_dev->dev_private; |
76c4b250 ID |
900 | |
901 | /* | |
902 | * We have a suspedn ordering issue with the snd-hda driver also | |
903 | * requiring our device to be power up. Due to the lack of a | |
904 | * parent/child relationship we currently solve this with an late | |
905 | * suspend hook. | |
906 | * | |
907 | * FIXME: This should be solved with a special hdmi sink device or | |
908 | * similar so that power domains can be employed. | |
909 | */ | |
910 | if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF) | |
911 | return 0; | |
112b715e | 912 | |
8abdc179 KCA |
913 | if (IS_HASWELL(drm_dev) || IS_BROADWELL(drm_dev)) |
914 | hsw_enable_pc8(dev_priv); | |
915 | ||
84b79f8d RW |
916 | pci_disable_device(pdev); |
917 | pci_set_power_state(pdev, PCI_D3hot); | |
cbda12d7 | 918 | |
84b79f8d | 919 | return 0; |
cbda12d7 ZW |
920 | } |
921 | ||
76c4b250 ID |
922 | static int i915_pm_resume_early(struct device *dev) |
923 | { | |
924 | struct pci_dev *pdev = to_pci_dev(dev); | |
925 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
926 | ||
927 | return i915_resume_early(drm_dev); | |
928 | } | |
929 | ||
84b79f8d | 930 | static int i915_pm_resume(struct device *dev) |
cbda12d7 | 931 | { |
84b79f8d RW |
932 | struct pci_dev *pdev = to_pci_dev(dev); |
933 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
934 | ||
935 | return i915_resume(drm_dev); | |
cbda12d7 ZW |
936 | } |
937 | ||
84b79f8d | 938 | static int i915_pm_freeze(struct device *dev) |
cbda12d7 | 939 | { |
84b79f8d RW |
940 | struct pci_dev *pdev = to_pci_dev(dev); |
941 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
942 | ||
943 | if (!drm_dev || !drm_dev->dev_private) { | |
944 | dev_err(dev, "DRM not initialized, aborting suspend.\n"); | |
945 | return -ENODEV; | |
946 | } | |
947 | ||
948 | return i915_drm_freeze(drm_dev); | |
cbda12d7 ZW |
949 | } |
950 | ||
76c4b250 ID |
951 | static int i915_pm_thaw_early(struct device *dev) |
952 | { | |
953 | struct pci_dev *pdev = to_pci_dev(dev); | |
954 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
955 | ||
956 | return i915_drm_thaw_early(drm_dev); | |
957 | } | |
958 | ||
84b79f8d | 959 | static int i915_pm_thaw(struct device *dev) |
cbda12d7 | 960 | { |
84b79f8d RW |
961 | struct pci_dev *pdev = to_pci_dev(dev); |
962 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
963 | ||
964 | return i915_drm_thaw(drm_dev); | |
cbda12d7 ZW |
965 | } |
966 | ||
84b79f8d | 967 | static int i915_pm_poweroff(struct device *dev) |
cbda12d7 | 968 | { |
84b79f8d RW |
969 | struct pci_dev *pdev = to_pci_dev(dev); |
970 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
84b79f8d | 971 | |
61caf87c | 972 | return i915_drm_freeze(drm_dev); |
cbda12d7 ZW |
973 | } |
974 | ||
0ab9cfeb | 975 | static int hsw_runtime_suspend(struct drm_i915_private *dev_priv) |
97bea207 | 976 | { |
414de7a0 | 977 | hsw_enable_pc8(dev_priv); |
0ab9cfeb ID |
978 | |
979 | return 0; | |
97bea207 PZ |
980 | } |
981 | ||
0ab9cfeb | 982 | static int snb_runtime_resume(struct drm_i915_private *dev_priv) |
9a952a0d PZ |
983 | { |
984 | struct drm_device *dev = dev_priv->dev; | |
985 | ||
9a952a0d | 986 | intel_init_pch_refclk(dev); |
0ab9cfeb ID |
987 | |
988 | return 0; | |
9a952a0d PZ |
989 | } |
990 | ||
0ab9cfeb | 991 | static int hsw_runtime_resume(struct drm_i915_private *dev_priv) |
97bea207 | 992 | { |
414de7a0 | 993 | hsw_disable_pc8(dev_priv); |
0ab9cfeb ID |
994 | |
995 | return 0; | |
97bea207 PZ |
996 | } |
997 | ||
ddeea5b0 ID |
998 | /* |
999 | * Save all Gunit registers that may be lost after a D3 and a subsequent | |
1000 | * S0i[R123] transition. The list of registers needing a save/restore is | |
1001 | * defined in the VLV2_S0IXRegs document. This documents marks all Gunit | |
1002 | * registers in the following way: | |
1003 | * - Driver: saved/restored by the driver | |
1004 | * - Punit : saved/restored by the Punit firmware | |
1005 | * - No, w/o marking: no need to save/restore, since the register is R/O or | |
1006 | * used internally by the HW in a way that doesn't depend | |
1007 | * keeping the content across a suspend/resume. | |
1008 | * - Debug : used for debugging | |
1009 | * | |
1010 | * We save/restore all registers marked with 'Driver', with the following | |
1011 | * exceptions: | |
1012 | * - Registers out of use, including also registers marked with 'Debug'. | |
1013 | * These have no effect on the driver's operation, so we don't save/restore | |
1014 | * them to reduce the overhead. | |
1015 | * - Registers that are fully setup by an initialization function called from | |
1016 | * the resume path. For example many clock gating and RPS/RC6 registers. | |
1017 | * - Registers that provide the right functionality with their reset defaults. | |
1018 | * | |
1019 | * TODO: Except for registers that based on the above 3 criteria can be safely | |
1020 | * ignored, we save/restore all others, practically treating the HW context as | |
1021 | * a black-box for the driver. Further investigation is needed to reduce the | |
1022 | * saved/restored registers even further, by following the same 3 criteria. | |
1023 | */ | |
1024 | static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv) | |
1025 | { | |
1026 | struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state; | |
1027 | int i; | |
1028 | ||
1029 | /* GAM 0x4000-0x4770 */ | |
1030 | s->wr_watermark = I915_READ(GEN7_WR_WATERMARK); | |
1031 | s->gfx_prio_ctrl = I915_READ(GEN7_GFX_PRIO_CTRL); | |
1032 | s->arb_mode = I915_READ(ARB_MODE); | |
1033 | s->gfx_pend_tlb0 = I915_READ(GEN7_GFX_PEND_TLB0); | |
1034 | s->gfx_pend_tlb1 = I915_READ(GEN7_GFX_PEND_TLB1); | |
1035 | ||
1036 | for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++) | |
1037 | s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS_BASE + i * 4); | |
1038 | ||
1039 | s->media_max_req_count = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT); | |
1040 | s->gfx_max_req_count = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT); | |
1041 | ||
1042 | s->render_hwsp = I915_READ(RENDER_HWS_PGA_GEN7); | |
1043 | s->ecochk = I915_READ(GAM_ECOCHK); | |
1044 | s->bsd_hwsp = I915_READ(BSD_HWS_PGA_GEN7); | |
1045 | s->blt_hwsp = I915_READ(BLT_HWS_PGA_GEN7); | |
1046 | ||
1047 | s->tlb_rd_addr = I915_READ(GEN7_TLB_RD_ADDR); | |
1048 | ||
1049 | /* MBC 0x9024-0x91D0, 0x8500 */ | |
1050 | s->g3dctl = I915_READ(VLV_G3DCTL); | |
1051 | s->gsckgctl = I915_READ(VLV_GSCKGCTL); | |
1052 | s->mbctl = I915_READ(GEN6_MBCTL); | |
1053 | ||
1054 | /* GCP 0x9400-0x9424, 0x8100-0x810C */ | |
1055 | s->ucgctl1 = I915_READ(GEN6_UCGCTL1); | |
1056 | s->ucgctl3 = I915_READ(GEN6_UCGCTL3); | |
1057 | s->rcgctl1 = I915_READ(GEN6_RCGCTL1); | |
1058 | s->rcgctl2 = I915_READ(GEN6_RCGCTL2); | |
1059 | s->rstctl = I915_READ(GEN6_RSTCTL); | |
1060 | s->misccpctl = I915_READ(GEN7_MISCCPCTL); | |
1061 | ||
1062 | /* GPM 0xA000-0xAA84, 0x8000-0x80FC */ | |
1063 | s->gfxpause = I915_READ(GEN6_GFXPAUSE); | |
1064 | s->rpdeuhwtc = I915_READ(GEN6_RPDEUHWTC); | |
1065 | s->rpdeuc = I915_READ(GEN6_RPDEUC); | |
1066 | s->ecobus = I915_READ(ECOBUS); | |
1067 | s->pwrdwnupctl = I915_READ(VLV_PWRDWNUPCTL); | |
1068 | s->rp_down_timeout = I915_READ(GEN6_RP_DOWN_TIMEOUT); | |
1069 | s->rp_deucsw = I915_READ(GEN6_RPDEUCSW); | |
1070 | s->rcubmabdtmr = I915_READ(GEN6_RCUBMABDTMR); | |
1071 | s->rcedata = I915_READ(VLV_RCEDATA); | |
1072 | s->spare2gh = I915_READ(VLV_SPAREG2H); | |
1073 | ||
1074 | /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */ | |
1075 | s->gt_imr = I915_READ(GTIMR); | |
1076 | s->gt_ier = I915_READ(GTIER); | |
1077 | s->pm_imr = I915_READ(GEN6_PMIMR); | |
1078 | s->pm_ier = I915_READ(GEN6_PMIER); | |
1079 | ||
1080 | for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++) | |
1081 | s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH_BASE + i * 4); | |
1082 | ||
1083 | /* GT SA CZ domain, 0x100000-0x138124 */ | |
1084 | s->tilectl = I915_READ(TILECTL); | |
1085 | s->gt_fifoctl = I915_READ(GTFIFOCTL); | |
1086 | s->gtlc_wake_ctrl = I915_READ(VLV_GTLC_WAKE_CTRL); | |
1087 | s->gtlc_survive = I915_READ(VLV_GTLC_SURVIVABILITY_REG); | |
1088 | s->pmwgicz = I915_READ(VLV_PMWGICZ); | |
1089 | ||
1090 | /* Gunit-Display CZ domain, 0x182028-0x1821CF */ | |
1091 | s->gu_ctl0 = I915_READ(VLV_GU_CTL0); | |
1092 | s->gu_ctl1 = I915_READ(VLV_GU_CTL1); | |
1093 | s->clock_gate_dis2 = I915_READ(VLV_GUNIT_CLOCK_GATE2); | |
1094 | ||
1095 | /* | |
1096 | * Not saving any of: | |
1097 | * DFT, 0x9800-0x9EC0 | |
1098 | * SARB, 0xB000-0xB1FC | |
1099 | * GAC, 0x5208-0x524C, 0x14000-0x14C000 | |
1100 | * PCI CFG | |
1101 | */ | |
1102 | } | |
1103 | ||
1104 | static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv) | |
1105 | { | |
1106 | struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state; | |
1107 | u32 val; | |
1108 | int i; | |
1109 | ||
1110 | /* GAM 0x4000-0x4770 */ | |
1111 | I915_WRITE(GEN7_WR_WATERMARK, s->wr_watermark); | |
1112 | I915_WRITE(GEN7_GFX_PRIO_CTRL, s->gfx_prio_ctrl); | |
1113 | I915_WRITE(ARB_MODE, s->arb_mode | (0xffff << 16)); | |
1114 | I915_WRITE(GEN7_GFX_PEND_TLB0, s->gfx_pend_tlb0); | |
1115 | I915_WRITE(GEN7_GFX_PEND_TLB1, s->gfx_pend_tlb1); | |
1116 | ||
1117 | for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++) | |
1118 | I915_WRITE(GEN7_LRA_LIMITS_BASE + i * 4, s->lra_limits[i]); | |
1119 | ||
1120 | I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count); | |
1121 | I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->gfx_max_req_count); | |
1122 | ||
1123 | I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp); | |
1124 | I915_WRITE(GAM_ECOCHK, s->ecochk); | |
1125 | I915_WRITE(BSD_HWS_PGA_GEN7, s->bsd_hwsp); | |
1126 | I915_WRITE(BLT_HWS_PGA_GEN7, s->blt_hwsp); | |
1127 | ||
1128 | I915_WRITE(GEN7_TLB_RD_ADDR, s->tlb_rd_addr); | |
1129 | ||
1130 | /* MBC 0x9024-0x91D0, 0x8500 */ | |
1131 | I915_WRITE(VLV_G3DCTL, s->g3dctl); | |
1132 | I915_WRITE(VLV_GSCKGCTL, s->gsckgctl); | |
1133 | I915_WRITE(GEN6_MBCTL, s->mbctl); | |
1134 | ||
1135 | /* GCP 0x9400-0x9424, 0x8100-0x810C */ | |
1136 | I915_WRITE(GEN6_UCGCTL1, s->ucgctl1); | |
1137 | I915_WRITE(GEN6_UCGCTL3, s->ucgctl3); | |
1138 | I915_WRITE(GEN6_RCGCTL1, s->rcgctl1); | |
1139 | I915_WRITE(GEN6_RCGCTL2, s->rcgctl2); | |
1140 | I915_WRITE(GEN6_RSTCTL, s->rstctl); | |
1141 | I915_WRITE(GEN7_MISCCPCTL, s->misccpctl); | |
1142 | ||
1143 | /* GPM 0xA000-0xAA84, 0x8000-0x80FC */ | |
1144 | I915_WRITE(GEN6_GFXPAUSE, s->gfxpause); | |
1145 | I915_WRITE(GEN6_RPDEUHWTC, s->rpdeuhwtc); | |
1146 | I915_WRITE(GEN6_RPDEUC, s->rpdeuc); | |
1147 | I915_WRITE(ECOBUS, s->ecobus); | |
1148 | I915_WRITE(VLV_PWRDWNUPCTL, s->pwrdwnupctl); | |
1149 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout); | |
1150 | I915_WRITE(GEN6_RPDEUCSW, s->rp_deucsw); | |
1151 | I915_WRITE(GEN6_RCUBMABDTMR, s->rcubmabdtmr); | |
1152 | I915_WRITE(VLV_RCEDATA, s->rcedata); | |
1153 | I915_WRITE(VLV_SPAREG2H, s->spare2gh); | |
1154 | ||
1155 | /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */ | |
1156 | I915_WRITE(GTIMR, s->gt_imr); | |
1157 | I915_WRITE(GTIER, s->gt_ier); | |
1158 | I915_WRITE(GEN6_PMIMR, s->pm_imr); | |
1159 | I915_WRITE(GEN6_PMIER, s->pm_ier); | |
1160 | ||
1161 | for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++) | |
1162 | I915_WRITE(GEN7_GT_SCRATCH_BASE + i * 4, s->gt_scratch[i]); | |
1163 | ||
1164 | /* GT SA CZ domain, 0x100000-0x138124 */ | |
1165 | I915_WRITE(TILECTL, s->tilectl); | |
1166 | I915_WRITE(GTFIFOCTL, s->gt_fifoctl); | |
1167 | /* | |
1168 | * Preserve the GT allow wake and GFX force clock bit, they are not | |
1169 | * be restored, as they are used to control the s0ix suspend/resume | |
1170 | * sequence by the caller. | |
1171 | */ | |
1172 | val = I915_READ(VLV_GTLC_WAKE_CTRL); | |
1173 | val &= VLV_GTLC_ALLOWWAKEREQ; | |
1174 | val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ; | |
1175 | I915_WRITE(VLV_GTLC_WAKE_CTRL, val); | |
1176 | ||
1177 | val = I915_READ(VLV_GTLC_SURVIVABILITY_REG); | |
1178 | val &= VLV_GFX_CLK_FORCE_ON_BIT; | |
1179 | val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT; | |
1180 | I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val); | |
1181 | ||
1182 | I915_WRITE(VLV_PMWGICZ, s->pmwgicz); | |
1183 | ||
1184 | /* Gunit-Display CZ domain, 0x182028-0x1821CF */ | |
1185 | I915_WRITE(VLV_GU_CTL0, s->gu_ctl0); | |
1186 | I915_WRITE(VLV_GU_CTL1, s->gu_ctl1); | |
1187 | I915_WRITE(VLV_GUNIT_CLOCK_GATE2, s->clock_gate_dis2); | |
1188 | } | |
1189 | ||
650ad970 ID |
1190 | int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on) |
1191 | { | |
1192 | u32 val; | |
1193 | int err; | |
1194 | ||
1195 | val = I915_READ(VLV_GTLC_SURVIVABILITY_REG); | |
1196 | WARN_ON(!!(val & VLV_GFX_CLK_FORCE_ON_BIT) == force_on); | |
1197 | ||
1198 | #define COND (I915_READ(VLV_GTLC_SURVIVABILITY_REG) & VLV_GFX_CLK_STATUS_BIT) | |
1199 | /* Wait for a previous force-off to settle */ | |
1200 | if (force_on) { | |
8d4eee9c | 1201 | err = wait_for(!COND, 20); |
650ad970 ID |
1202 | if (err) { |
1203 | DRM_ERROR("timeout waiting for GFX clock force-off (%08x)\n", | |
1204 | I915_READ(VLV_GTLC_SURVIVABILITY_REG)); | |
1205 | return err; | |
1206 | } | |
1207 | } | |
1208 | ||
1209 | val = I915_READ(VLV_GTLC_SURVIVABILITY_REG); | |
1210 | val &= ~VLV_GFX_CLK_FORCE_ON_BIT; | |
1211 | if (force_on) | |
1212 | val |= VLV_GFX_CLK_FORCE_ON_BIT; | |
1213 | I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val); | |
1214 | ||
1215 | if (!force_on) | |
1216 | return 0; | |
1217 | ||
8d4eee9c | 1218 | err = wait_for(COND, 20); |
650ad970 ID |
1219 | if (err) |
1220 | DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n", | |
1221 | I915_READ(VLV_GTLC_SURVIVABILITY_REG)); | |
1222 | ||
1223 | return err; | |
1224 | #undef COND | |
1225 | } | |
1226 | ||
ddeea5b0 ID |
1227 | static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow) |
1228 | { | |
1229 | u32 val; | |
1230 | int err = 0; | |
1231 | ||
1232 | val = I915_READ(VLV_GTLC_WAKE_CTRL); | |
1233 | val &= ~VLV_GTLC_ALLOWWAKEREQ; | |
1234 | if (allow) | |
1235 | val |= VLV_GTLC_ALLOWWAKEREQ; | |
1236 | I915_WRITE(VLV_GTLC_WAKE_CTRL, val); | |
1237 | POSTING_READ(VLV_GTLC_WAKE_CTRL); | |
1238 | ||
1239 | #define COND (!!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEACK) == \ | |
1240 | allow) | |
1241 | err = wait_for(COND, 1); | |
1242 | if (err) | |
1243 | DRM_ERROR("timeout disabling GT waking\n"); | |
1244 | return err; | |
1245 | #undef COND | |
1246 | } | |
1247 | ||
1248 | static int vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv, | |
1249 | bool wait_for_on) | |
1250 | { | |
1251 | u32 mask; | |
1252 | u32 val; | |
1253 | int err; | |
1254 | ||
1255 | mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK; | |
1256 | val = wait_for_on ? mask : 0; | |
1257 | #define COND ((I915_READ(VLV_GTLC_PW_STATUS) & mask) == val) | |
1258 | if (COND) | |
1259 | return 0; | |
1260 | ||
1261 | DRM_DEBUG_KMS("waiting for GT wells to go %s (%08x)\n", | |
1262 | wait_for_on ? "on" : "off", | |
1263 | I915_READ(VLV_GTLC_PW_STATUS)); | |
1264 | ||
1265 | /* | |
1266 | * RC6 transitioning can be delayed up to 2 msec (see | |
1267 | * valleyview_enable_rps), use 3 msec for safety. | |
1268 | */ | |
1269 | err = wait_for(COND, 3); | |
1270 | if (err) | |
1271 | DRM_ERROR("timeout waiting for GT wells to go %s\n", | |
1272 | wait_for_on ? "on" : "off"); | |
1273 | ||
1274 | return err; | |
1275 | #undef COND | |
1276 | } | |
1277 | ||
1278 | static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv) | |
1279 | { | |
1280 | if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR)) | |
1281 | return; | |
1282 | ||
1283 | DRM_ERROR("GT register access while GT waking disabled\n"); | |
1284 | I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR); | |
1285 | } | |
1286 | ||
1287 | static int vlv_runtime_suspend(struct drm_i915_private *dev_priv) | |
1288 | { | |
1289 | u32 mask; | |
1290 | int err; | |
1291 | ||
1292 | /* | |
1293 | * Bspec defines the following GT well on flags as debug only, so | |
1294 | * don't treat them as hard failures. | |
1295 | */ | |
1296 | (void)vlv_wait_for_gt_wells(dev_priv, false); | |
1297 | ||
1298 | mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS; | |
1299 | WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask); | |
1300 | ||
1301 | vlv_check_no_gt_access(dev_priv); | |
1302 | ||
1303 | err = vlv_force_gfx_clock(dev_priv, true); | |
1304 | if (err) | |
1305 | goto err1; | |
1306 | ||
1307 | err = vlv_allow_gt_wake(dev_priv, false); | |
1308 | if (err) | |
1309 | goto err2; | |
1310 | vlv_save_gunit_s0ix_state(dev_priv); | |
1311 | ||
1312 | err = vlv_force_gfx_clock(dev_priv, false); | |
1313 | if (err) | |
1314 | goto err2; | |
1315 | ||
1316 | return 0; | |
1317 | ||
1318 | err2: | |
1319 | /* For safety always re-enable waking and disable gfx clock forcing */ | |
1320 | vlv_allow_gt_wake(dev_priv, true); | |
1321 | err1: | |
1322 | vlv_force_gfx_clock(dev_priv, false); | |
1323 | ||
1324 | return err; | |
1325 | } | |
1326 | ||
1327 | static int vlv_runtime_resume(struct drm_i915_private *dev_priv) | |
1328 | { | |
1329 | struct drm_device *dev = dev_priv->dev; | |
1330 | int err; | |
1331 | int ret; | |
1332 | ||
1333 | /* | |
1334 | * If any of the steps fail just try to continue, that's the best we | |
1335 | * can do at this point. Return the first error code (which will also | |
1336 | * leave RPM permanently disabled). | |
1337 | */ | |
1338 | ret = vlv_force_gfx_clock(dev_priv, true); | |
1339 | ||
1340 | vlv_restore_gunit_s0ix_state(dev_priv); | |
1341 | ||
1342 | err = vlv_allow_gt_wake(dev_priv, true); | |
1343 | if (!ret) | |
1344 | ret = err; | |
1345 | ||
1346 | err = vlv_force_gfx_clock(dev_priv, false); | |
1347 | if (!ret) | |
1348 | ret = err; | |
1349 | ||
1350 | vlv_check_no_gt_access(dev_priv); | |
1351 | ||
1352 | intel_init_clock_gating(dev); | |
1353 | i915_gem_restore_fences(dev); | |
1354 | ||
1355 | return ret; | |
1356 | } | |
1357 | ||
97bea207 | 1358 | static int intel_runtime_suspend(struct device *device) |
8a187455 PZ |
1359 | { |
1360 | struct pci_dev *pdev = to_pci_dev(device); | |
1361 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1362 | struct drm_i915_private *dev_priv = dev->dev_private; | |
0ab9cfeb | 1363 | int ret; |
8a187455 | 1364 | |
aeab0b5a | 1365 | if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6(dev)))) |
c6df39b5 ID |
1366 | return -ENODEV; |
1367 | ||
8a187455 | 1368 | WARN_ON(!HAS_RUNTIME_PM(dev)); |
e998c40f | 1369 | assert_force_wake_inactive(dev_priv); |
8a187455 PZ |
1370 | |
1371 | DRM_DEBUG_KMS("Suspending device\n"); | |
1372 | ||
d6102977 ID |
1373 | /* |
1374 | * We could deadlock here in case another thread holding struct_mutex | |
1375 | * calls RPM suspend concurrently, since the RPM suspend will wait | |
1376 | * first for this RPM suspend to finish. In this case the concurrent | |
1377 | * RPM resume will be followed by its RPM suspend counterpart. Still | |
1378 | * for consistency return -EAGAIN, which will reschedule this suspend. | |
1379 | */ | |
1380 | if (!mutex_trylock(&dev->struct_mutex)) { | |
1381 | DRM_DEBUG_KMS("device lock contention, deffering suspend\n"); | |
1382 | /* | |
1383 | * Bump the expiration timestamp, otherwise the suspend won't | |
1384 | * be rescheduled. | |
1385 | */ | |
1386 | pm_runtime_mark_last_busy(device); | |
1387 | ||
1388 | return -EAGAIN; | |
1389 | } | |
1390 | /* | |
1391 | * We are safe here against re-faults, since the fault handler takes | |
1392 | * an RPM reference. | |
1393 | */ | |
1394 | i915_gem_release_all_mmaps(dev_priv); | |
1395 | mutex_unlock(&dev->struct_mutex); | |
1396 | ||
9486db61 ID |
1397 | /* |
1398 | * rps.work can't be rearmed here, since we get here only after making | |
1399 | * sure the GPU is idle and the RPS freq is set to the minimum. See | |
1400 | * intel_mark_idle(). | |
1401 | */ | |
1402 | cancel_work_sync(&dev_priv->rps.work); | |
b5478bcd ID |
1403 | intel_runtime_pm_disable_interrupts(dev); |
1404 | ||
0ab9cfeb ID |
1405 | if (IS_GEN6(dev)) { |
1406 | ret = 0; | |
1407 | } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { | |
1408 | ret = hsw_runtime_suspend(dev_priv); | |
ddeea5b0 ID |
1409 | } else if (IS_VALLEYVIEW(dev)) { |
1410 | ret = vlv_runtime_suspend(dev_priv); | |
0ab9cfeb ID |
1411 | } else { |
1412 | ret = -ENODEV; | |
6157d3c8 | 1413 | WARN_ON(1); |
0ab9cfeb ID |
1414 | } |
1415 | ||
1416 | if (ret) { | |
1417 | DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret); | |
1418 | intel_runtime_pm_restore_interrupts(dev); | |
1419 | ||
1420 | return ret; | |
1421 | } | |
a8a8bd54 | 1422 | |
16a3d6ef | 1423 | del_timer_sync(&dev_priv->gpu_error.hangcheck_timer); |
8a187455 | 1424 | dev_priv->pm.suspended = true; |
1fb2362b KCA |
1425 | |
1426 | /* | |
1427 | * current versions of firmware which depend on this opregion | |
1428 | * notification have repurposed the D1 definition to mean | |
1429 | * "runtime suspended" vs. what you would normally expect (D3) | |
1430 | * to distinguish it from notifications that might be sent | |
1431 | * via the suspend path. | |
1432 | */ | |
1433 | intel_opregion_notify_adapter(dev, PCI_D1); | |
8a187455 | 1434 | |
a8a8bd54 | 1435 | DRM_DEBUG_KMS("Device suspended\n"); |
8a187455 PZ |
1436 | return 0; |
1437 | } | |
1438 | ||
97bea207 | 1439 | static int intel_runtime_resume(struct device *device) |
8a187455 PZ |
1440 | { |
1441 | struct pci_dev *pdev = to_pci_dev(device); | |
1442 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1443 | struct drm_i915_private *dev_priv = dev->dev_private; | |
0ab9cfeb | 1444 | int ret; |
8a187455 PZ |
1445 | |
1446 | WARN_ON(!HAS_RUNTIME_PM(dev)); | |
1447 | ||
1448 | DRM_DEBUG_KMS("Resuming device\n"); | |
1449 | ||
cd2e9e90 | 1450 | intel_opregion_notify_adapter(dev, PCI_D0); |
8a187455 PZ |
1451 | dev_priv->pm.suspended = false; |
1452 | ||
0ab9cfeb ID |
1453 | if (IS_GEN6(dev)) { |
1454 | ret = snb_runtime_resume(dev_priv); | |
1455 | } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { | |
1456 | ret = hsw_runtime_resume(dev_priv); | |
ddeea5b0 ID |
1457 | } else if (IS_VALLEYVIEW(dev)) { |
1458 | ret = vlv_runtime_resume(dev_priv); | |
0ab9cfeb | 1459 | } else { |
6157d3c8 | 1460 | WARN_ON(1); |
0ab9cfeb ID |
1461 | ret = -ENODEV; |
1462 | } | |
a8a8bd54 | 1463 | |
0ab9cfeb ID |
1464 | /* |
1465 | * No point of rolling back things in case of an error, as the best | |
1466 | * we can do is to hope that things will still work (and disable RPM). | |
1467 | */ | |
92b806d3 ID |
1468 | i915_gem_init_swizzling(dev); |
1469 | gen6_update_ring_freq(dev); | |
1470 | ||
b5478bcd | 1471 | intel_runtime_pm_restore_interrupts(dev); |
9486db61 | 1472 | intel_reset_gt_powersave(dev); |
b5478bcd | 1473 | |
0ab9cfeb ID |
1474 | if (ret) |
1475 | DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret); | |
1476 | else | |
1477 | DRM_DEBUG_KMS("Device resumed\n"); | |
1478 | ||
1479 | return ret; | |
8a187455 PZ |
1480 | } |
1481 | ||
b4b78d12 | 1482 | static const struct dev_pm_ops i915_pm_ops = { |
0206e353 | 1483 | .suspend = i915_pm_suspend, |
76c4b250 ID |
1484 | .suspend_late = i915_pm_suspend_late, |
1485 | .resume_early = i915_pm_resume_early, | |
0206e353 AJ |
1486 | .resume = i915_pm_resume, |
1487 | .freeze = i915_pm_freeze, | |
76c4b250 | 1488 | .thaw_early = i915_pm_thaw_early, |
0206e353 AJ |
1489 | .thaw = i915_pm_thaw, |
1490 | .poweroff = i915_pm_poweroff, | |
76c4b250 | 1491 | .restore_early = i915_pm_resume_early, |
0206e353 | 1492 | .restore = i915_pm_resume, |
97bea207 PZ |
1493 | .runtime_suspend = intel_runtime_suspend, |
1494 | .runtime_resume = intel_runtime_resume, | |
cbda12d7 ZW |
1495 | }; |
1496 | ||
78b68556 | 1497 | static const struct vm_operations_struct i915_gem_vm_ops = { |
de151cf6 | 1498 | .fault = i915_gem_fault, |
ab00b3e5 JB |
1499 | .open = drm_gem_vm_open, |
1500 | .close = drm_gem_vm_close, | |
de151cf6 JB |
1501 | }; |
1502 | ||
e08e96de AV |
1503 | static const struct file_operations i915_driver_fops = { |
1504 | .owner = THIS_MODULE, | |
1505 | .open = drm_open, | |
1506 | .release = drm_release, | |
1507 | .unlocked_ioctl = drm_ioctl, | |
1508 | .mmap = drm_gem_mmap, | |
1509 | .poll = drm_poll, | |
e08e96de AV |
1510 | .read = drm_read, |
1511 | #ifdef CONFIG_COMPAT | |
1512 | .compat_ioctl = i915_compat_ioctl, | |
1513 | #endif | |
1514 | .llseek = noop_llseek, | |
1515 | }; | |
1516 | ||
1da177e4 | 1517 | static struct drm_driver driver = { |
0c54781b MW |
1518 | /* Don't use MTRRs here; the Xserver or userspace app should |
1519 | * deal with them for Intel hardware. | |
792d2b9a | 1520 | */ |
673a394b | 1521 | .driver_features = |
24986ee0 | 1522 | DRIVER_USE_AGP | |
10ba5012 KH |
1523 | DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME | |
1524 | DRIVER_RENDER, | |
22eae947 | 1525 | .load = i915_driver_load, |
ba8bbcf6 | 1526 | .unload = i915_driver_unload, |
673a394b | 1527 | .open = i915_driver_open, |
22eae947 DA |
1528 | .lastclose = i915_driver_lastclose, |
1529 | .preclose = i915_driver_preclose, | |
673a394b | 1530 | .postclose = i915_driver_postclose, |
d8e29209 RW |
1531 | |
1532 | /* Used in place of i915_pm_ops for non-DRIVER_MODESET */ | |
1533 | .suspend = i915_suspend, | |
76c4b250 | 1534 | .resume = i915_resume_legacy, |
d8e29209 | 1535 | |
cda17380 | 1536 | .device_is_agp = i915_driver_device_is_agp, |
7c1c2871 DA |
1537 | .master_create = i915_master_create, |
1538 | .master_destroy = i915_master_destroy, | |
955b12de | 1539 | #if defined(CONFIG_DEBUG_FS) |
27c202ad BG |
1540 | .debugfs_init = i915_debugfs_init, |
1541 | .debugfs_cleanup = i915_debugfs_cleanup, | |
955b12de | 1542 | #endif |
673a394b | 1543 | .gem_free_object = i915_gem_free_object, |
de151cf6 | 1544 | .gem_vm_ops = &i915_gem_vm_ops, |
1286ff73 DV |
1545 | |
1546 | .prime_handle_to_fd = drm_gem_prime_handle_to_fd, | |
1547 | .prime_fd_to_handle = drm_gem_prime_fd_to_handle, | |
1548 | .gem_prime_export = i915_gem_prime_export, | |
1549 | .gem_prime_import = i915_gem_prime_import, | |
1550 | ||
ff72145b DA |
1551 | .dumb_create = i915_gem_dumb_create, |
1552 | .dumb_map_offset = i915_gem_mmap_gtt, | |
43387b37 | 1553 | .dumb_destroy = drm_gem_dumb_destroy, |
1da177e4 | 1554 | .ioctls = i915_ioctls, |
e08e96de | 1555 | .fops = &i915_driver_fops, |
22eae947 DA |
1556 | .name = DRIVER_NAME, |
1557 | .desc = DRIVER_DESC, | |
1558 | .date = DRIVER_DATE, | |
1559 | .major = DRIVER_MAJOR, | |
1560 | .minor = DRIVER_MINOR, | |
1561 | .patchlevel = DRIVER_PATCHLEVEL, | |
1da177e4 LT |
1562 | }; |
1563 | ||
8410ea3b DA |
1564 | static struct pci_driver i915_pci_driver = { |
1565 | .name = DRIVER_NAME, | |
1566 | .id_table = pciidlist, | |
1567 | .probe = i915_pci_probe, | |
1568 | .remove = i915_pci_remove, | |
1569 | .driver.pm = &i915_pm_ops, | |
1570 | }; | |
1571 | ||
1da177e4 LT |
1572 | static int __init i915_init(void) |
1573 | { | |
1574 | driver.num_ioctls = i915_max_ioctl; | |
79e53945 JB |
1575 | |
1576 | /* | |
1577 | * If CONFIG_DRM_I915_KMS is set, default to KMS unless | |
1578 | * explicitly disabled with the module pararmeter. | |
1579 | * | |
1580 | * Otherwise, just follow the parameter (defaulting to off). | |
1581 | * | |
1582 | * Allow optional vga_text_mode_force boot option to override | |
1583 | * the default behavior. | |
1584 | */ | |
1585 | #if defined(CONFIG_DRM_I915_KMS) | |
d330a953 | 1586 | if (i915.modeset != 0) |
79e53945 JB |
1587 | driver.driver_features |= DRIVER_MODESET; |
1588 | #endif | |
d330a953 | 1589 | if (i915.modeset == 1) |
79e53945 JB |
1590 | driver.driver_features |= DRIVER_MODESET; |
1591 | ||
1592 | #ifdef CONFIG_VGA_CONSOLE | |
d330a953 | 1593 | if (vgacon_text_force() && i915.modeset == -1) |
79e53945 JB |
1594 | driver.driver_features &= ~DRIVER_MODESET; |
1595 | #endif | |
1596 | ||
b30324ad | 1597 | if (!(driver.driver_features & DRIVER_MODESET)) { |
3885c6bb | 1598 | driver.get_vblank_timestamp = NULL; |
b30324ad DV |
1599 | #ifndef CONFIG_DRM_I915_UMS |
1600 | /* Silently fail loading to not upset userspace. */ | |
c9cd7b65 | 1601 | DRM_DEBUG_DRIVER("KMS and UMS disabled.\n"); |
b30324ad DV |
1602 | return 0; |
1603 | #endif | |
1604 | } | |
3885c6bb | 1605 | |
8410ea3b | 1606 | return drm_pci_init(&driver, &i915_pci_driver); |
1da177e4 LT |
1607 | } |
1608 | ||
1609 | static void __exit i915_exit(void) | |
1610 | { | |
b33ecdd1 DV |
1611 | #ifndef CONFIG_DRM_I915_UMS |
1612 | if (!(driver.driver_features & DRIVER_MODESET)) | |
1613 | return; /* Never loaded a driver. */ | |
1614 | #endif | |
1615 | ||
8410ea3b | 1616 | drm_pci_exit(&driver, &i915_pci_driver); |
1da177e4 LT |
1617 | } |
1618 | ||
1619 | module_init(i915_init); | |
1620 | module_exit(i915_exit); | |
1621 | ||
b5e89ed5 DA |
1622 | MODULE_AUTHOR(DRIVER_AUTHOR); |
1623 | MODULE_DESCRIPTION(DRIVER_DESC); | |
1da177e4 | 1624 | MODULE_LICENSE("GPL and additional rights"); |