Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*- |
2 | */ | |
0d6aa60b | 3 | /* |
bc54fd1a | 4 | * |
1da177e4 LT |
5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
6 | * All Rights Reserved. | |
bc54fd1a DA |
7 | * |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the | |
10 | * "Software"), to deal in the Software without restriction, including | |
11 | * without limitation the rights to use, copy, modify, merge, publish, | |
12 | * distribute, sub license, and/or sell copies of the Software, and to | |
13 | * permit persons to whom the Software is furnished to do so, subject to | |
14 | * the following conditions: | |
15 | * | |
16 | * The above copyright notice and this permission notice (including the | |
17 | * next paragraph) shall be included in all copies or substantial portions | |
18 | * of the Software. | |
19 | * | |
20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
27 | * | |
0d6aa60b | 28 | */ |
1da177e4 | 29 | |
5669fcac | 30 | #include <linux/device.h> |
760285e7 DH |
31 | #include <drm/drmP.h> |
32 | #include <drm/i915_drm.h> | |
1da177e4 | 33 | #include "i915_drv.h" |
990bbdad | 34 | #include "i915_trace.h" |
f49f0586 | 35 | #include "intel_drv.h" |
1da177e4 | 36 | |
79e53945 | 37 | #include <linux/console.h> |
e0cd3608 | 38 | #include <linux/module.h> |
760285e7 | 39 | #include <drm/drm_crtc_helper.h> |
79e53945 | 40 | |
a35d9d3c | 41 | static int i915_modeset __read_mostly = -1; |
79e53945 | 42 | module_param_named(modeset, i915_modeset, int, 0400); |
6e96e775 BW |
43 | MODULE_PARM_DESC(modeset, |
44 | "Use kernel modesetting [KMS] (0=DRM_I915_KMS from .config, " | |
45 | "1=on, -1=force vga console preference [default])"); | |
79e53945 | 46 | |
a35d9d3c | 47 | unsigned int i915_fbpercrtc __always_unused = 0; |
79e53945 | 48 | module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400); |
1da177e4 | 49 | |
a726915c | 50 | int i915_panel_ignore_lid __read_mostly = 1; |
fca87409 | 51 | module_param_named(panel_ignore_lid, i915_panel_ignore_lid, int, 0600); |
6e96e775 | 52 | MODULE_PARM_DESC(panel_ignore_lid, |
a726915c DV |
53 | "Override lid status (0=autodetect, 1=autodetect disabled [default], " |
54 | "-1=force lid closed, -2=force lid open)"); | |
fca87409 | 55 | |
a35d9d3c | 56 | unsigned int i915_powersave __read_mostly = 1; |
0aa99277 | 57 | module_param_named(powersave, i915_powersave, int, 0600); |
6e96e775 BW |
58 | MODULE_PARM_DESC(powersave, |
59 | "Enable powersavings, fbc, downclocking, etc. (default: true)"); | |
652c393a | 60 | |
f45b5557 | 61 | int i915_semaphores __read_mostly = -1; |
a1656b90 | 62 | module_param_named(semaphores, i915_semaphores, int, 0600); |
6e96e775 | 63 | MODULE_PARM_DESC(semaphores, |
f45b5557 | 64 | "Use semaphores for inter-ring sync (default: -1 (use per-chip defaults))"); |
a1656b90 | 65 | |
c0f372b3 | 66 | int i915_enable_rc6 __read_mostly = -1; |
f57f9c16 | 67 | module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0400); |
6e96e775 | 68 | MODULE_PARM_DESC(i915_enable_rc6, |
83b7f9ac ED |
69 | "Enable power-saving render C-state 6. " |
70 | "Different stages can be selected via bitmask values " | |
71 | "(0 = disable; 1 = enable rc6; 2 = enable deep rc6; 4 = enable deepest rc6). " | |
72 | "For example, 3 would enable rc6 and deep rc6, and 7 would enable everything. " | |
73 | "default: -1 (use per-chip default)"); | |
ac668088 | 74 | |
4415e63b | 75 | int i915_enable_fbc __read_mostly = -1; |
c1a9f047 | 76 | module_param_named(i915_enable_fbc, i915_enable_fbc, int, 0600); |
6e96e775 BW |
77 | MODULE_PARM_DESC(i915_enable_fbc, |
78 | "Enable frame buffer compression for power savings " | |
cd0de039 | 79 | "(default: -1 (use per-chip default))"); |
c1a9f047 | 80 | |
a35d9d3c | 81 | unsigned int i915_lvds_downclock __read_mostly = 0; |
33814341 | 82 | module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400); |
6e96e775 BW |
83 | MODULE_PARM_DESC(lvds_downclock, |
84 | "Use panel (LVDS/eDP) downclocking for power savings " | |
85 | "(default: false)"); | |
33814341 | 86 | |
121d527a TI |
87 | int i915_lvds_channel_mode __read_mostly; |
88 | module_param_named(lvds_channel_mode, i915_lvds_channel_mode, int, 0600); | |
89 | MODULE_PARM_DESC(lvds_channel_mode, | |
90 | "Specify LVDS channel mode " | |
91 | "(0=probe BIOS [default], 1=single-channel, 2=dual-channel)"); | |
92 | ||
4415e63b | 93 | int i915_panel_use_ssc __read_mostly = -1; |
a7615030 | 94 | module_param_named(lvds_use_ssc, i915_panel_use_ssc, int, 0600); |
6e96e775 BW |
95 | MODULE_PARM_DESC(lvds_use_ssc, |
96 | "Use Spread Spectrum Clock with panels [LVDS/eDP] " | |
72bbe58c | 97 | "(default: auto from VBT)"); |
a7615030 | 98 | |
a35d9d3c | 99 | int i915_vbt_sdvo_panel_type __read_mostly = -1; |
5a1e5b6c | 100 | module_param_named(vbt_sdvo_panel_type, i915_vbt_sdvo_panel_type, int, 0600); |
6e96e775 | 101 | MODULE_PARM_DESC(vbt_sdvo_panel_type, |
c10e408a MF |
102 | "Override/Ignore selection of SDVO panel mode in the VBT " |
103 | "(-2=ignore, -1=auto [default], index in VBT BIOS table)"); | |
5a1e5b6c | 104 | |
a35d9d3c | 105 | static bool i915_try_reset __read_mostly = true; |
d78cb50b | 106 | module_param_named(reset, i915_try_reset, bool, 0600); |
6e96e775 | 107 | MODULE_PARM_DESC(reset, "Attempt GPU resets (default: true)"); |
d78cb50b | 108 | |
a35d9d3c | 109 | bool i915_enable_hangcheck __read_mostly = true; |
3e0dc6b0 | 110 | module_param_named(enable_hangcheck, i915_enable_hangcheck, bool, 0644); |
6e96e775 BW |
111 | MODULE_PARM_DESC(enable_hangcheck, |
112 | "Periodically check GPU activity for detecting hangs. " | |
113 | "WARNING: Disabling this can cause system wide hangs. " | |
114 | "(default: true)"); | |
3e0dc6b0 | 115 | |
650dc07e DV |
116 | int i915_enable_ppgtt __read_mostly = -1; |
117 | module_param_named(i915_enable_ppgtt, i915_enable_ppgtt, int, 0600); | |
e21af88d DV |
118 | MODULE_PARM_DESC(i915_enable_ppgtt, |
119 | "Enable PPGTT (default: true)"); | |
120 | ||
105b7c11 RV |
121 | int i915_enable_psr __read_mostly = 0; |
122 | module_param_named(enable_psr, i915_enable_psr, int, 0600); | |
123 | MODULE_PARM_DESC(enable_psr, "Enable PSR (default: false)"); | |
124 | ||
99486b8e | 125 | unsigned int i915_preliminary_hw_support __read_mostly = IS_ENABLED(CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT); |
0a3af268 RV |
126 | module_param_named(preliminary_hw_support, i915_preliminary_hw_support, int, 0600); |
127 | MODULE_PARM_DESC(preliminary_hw_support, | |
99486b8e | 128 | "Enable preliminary hardware support."); |
0a3af268 | 129 | |
bf51d5e2 | 130 | int i915_disable_power_well __read_mostly = 1; |
2124b72e PZ |
131 | module_param_named(disable_power_well, i915_disable_power_well, int, 0600); |
132 | MODULE_PARM_DESC(disable_power_well, | |
bf51d5e2 | 133 | "Disable the power well when possible (default: true)"); |
2124b72e | 134 | |
3c4ca58c PZ |
135 | int i915_enable_ips __read_mostly = 1; |
136 | module_param_named(enable_ips, i915_enable_ips, int, 0600); | |
137 | MODULE_PARM_DESC(enable_ips, "Enable IPS (default: true)"); | |
138 | ||
2385bdf0 JB |
139 | bool i915_fastboot __read_mostly = 0; |
140 | module_param_named(fastboot, i915_fastboot, bool, 0600); | |
141 | MODULE_PARM_DESC(fastboot, "Try to skip unnecessary mode sets at boot time " | |
142 | "(default: false)"); | |
143 | ||
e27e9708 | 144 | int i915_enable_pc8 __read_mostly = 1; |
c67a470b | 145 | module_param_named(enable_pc8, i915_enable_pc8, int, 0600); |
e27e9708 | 146 | MODULE_PARM_DESC(enable_pc8, "Enable support for low power package C states (PC8+) (default: true)"); |
c67a470b | 147 | |
90058745 PZ |
148 | int i915_pc8_timeout __read_mostly = 5000; |
149 | module_param_named(pc8_timeout, i915_pc8_timeout, int, 0600); | |
150 | MODULE_PARM_DESC(pc8_timeout, "Number of msecs of idleness required to enter PC8+ (default: 5000)"); | |
151 | ||
0b74b508 XZ |
152 | bool i915_prefault_disable __read_mostly; |
153 | module_param_named(prefault_disable, i915_prefault_disable, bool, 0600); | |
154 | MODULE_PARM_DESC(prefault_disable, | |
155 | "Disable page prefaulting for pread/pwrite/reloc (default:false). For developers only."); | |
156 | ||
112b715e | 157 | static struct drm_driver driver; |
1f7a6e37 | 158 | extern int intel_agp_enabled; |
112b715e | 159 | |
cfdf1fa2 | 160 | #define INTEL_VGA_DEVICE(id, info) { \ |
80a2901d | 161 | .class = PCI_BASE_CLASS_DISPLAY << 16, \ |
934f992c | 162 | .class_mask = 0xff0000, \ |
49ae35f2 KH |
163 | .vendor = 0x8086, \ |
164 | .device = id, \ | |
165 | .subvendor = PCI_ANY_ID, \ | |
166 | .subdevice = PCI_ANY_ID, \ | |
cfdf1fa2 KH |
167 | .driver_data = (unsigned long) info } |
168 | ||
999bcdea BW |
169 | #define INTEL_QUANTA_VGA_DEVICE(info) { \ |
170 | .class = PCI_BASE_CLASS_DISPLAY << 16, \ | |
171 | .class_mask = 0xff0000, \ | |
172 | .vendor = 0x8086, \ | |
173 | .device = 0x16a, \ | |
174 | .subvendor = 0x152d, \ | |
175 | .subdevice = 0x8990, \ | |
176 | .driver_data = (unsigned long) info } | |
177 | ||
178 | ||
9a7e8492 | 179 | static const struct intel_device_info intel_i830_info = { |
7eb552ae | 180 | .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2, |
31578148 | 181 | .has_overlay = 1, .overlay_needs_physical = 1, |
cfdf1fa2 KH |
182 | }; |
183 | ||
9a7e8492 | 184 | static const struct intel_device_info intel_845g_info = { |
7eb552ae | 185 | .gen = 2, .num_pipes = 1, |
31578148 | 186 | .has_overlay = 1, .overlay_needs_physical = 1, |
cfdf1fa2 KH |
187 | }; |
188 | ||
9a7e8492 | 189 | static const struct intel_device_info intel_i85x_info = { |
7eb552ae | 190 | .gen = 2, .is_i85x = 1, .is_mobile = 1, .num_pipes = 2, |
5ce8ba7c | 191 | .cursor_needs_physical = 1, |
31578148 | 192 | .has_overlay = 1, .overlay_needs_physical = 1, |
cfdf1fa2 KH |
193 | }; |
194 | ||
9a7e8492 | 195 | static const struct intel_device_info intel_i865g_info = { |
7eb552ae | 196 | .gen = 2, .num_pipes = 1, |
31578148 | 197 | .has_overlay = 1, .overlay_needs_physical = 1, |
cfdf1fa2 KH |
198 | }; |
199 | ||
9a7e8492 | 200 | static const struct intel_device_info intel_i915g_info = { |
7eb552ae | 201 | .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2, |
31578148 | 202 | .has_overlay = 1, .overlay_needs_physical = 1, |
cfdf1fa2 | 203 | }; |
9a7e8492 | 204 | static const struct intel_device_info intel_i915gm_info = { |
7eb552ae | 205 | .gen = 3, .is_mobile = 1, .num_pipes = 2, |
b295d1b6 | 206 | .cursor_needs_physical = 1, |
31578148 | 207 | .has_overlay = 1, .overlay_needs_physical = 1, |
a6c45cf0 | 208 | .supports_tv = 1, |
cfdf1fa2 | 209 | }; |
9a7e8492 | 210 | static const struct intel_device_info intel_i945g_info = { |
7eb552ae | 211 | .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2, |
31578148 | 212 | .has_overlay = 1, .overlay_needs_physical = 1, |
cfdf1fa2 | 213 | }; |
9a7e8492 | 214 | static const struct intel_device_info intel_i945gm_info = { |
7eb552ae | 215 | .gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2, |
b295d1b6 | 216 | .has_hotplug = 1, .cursor_needs_physical = 1, |
31578148 | 217 | .has_overlay = 1, .overlay_needs_physical = 1, |
a6c45cf0 | 218 | .supports_tv = 1, |
cfdf1fa2 KH |
219 | }; |
220 | ||
9a7e8492 | 221 | static const struct intel_device_info intel_i965g_info = { |
7eb552ae | 222 | .gen = 4, .is_broadwater = 1, .num_pipes = 2, |
c96c3a8c | 223 | .has_hotplug = 1, |
31578148 | 224 | .has_overlay = 1, |
cfdf1fa2 KH |
225 | }; |
226 | ||
9a7e8492 | 227 | static const struct intel_device_info intel_i965gm_info = { |
7eb552ae | 228 | .gen = 4, .is_crestline = 1, .num_pipes = 2, |
e3c4e5dd | 229 | .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1, |
31578148 | 230 | .has_overlay = 1, |
a6c45cf0 | 231 | .supports_tv = 1, |
cfdf1fa2 KH |
232 | }; |
233 | ||
9a7e8492 | 234 | static const struct intel_device_info intel_g33_info = { |
7eb552ae | 235 | .gen = 3, .is_g33 = 1, .num_pipes = 2, |
c96c3a8c | 236 | .need_gfx_hws = 1, .has_hotplug = 1, |
31578148 | 237 | .has_overlay = 1, |
cfdf1fa2 KH |
238 | }; |
239 | ||
9a7e8492 | 240 | static const struct intel_device_info intel_g45_info = { |
7eb552ae | 241 | .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2, |
c96c3a8c | 242 | .has_pipe_cxsr = 1, .has_hotplug = 1, |
92f49d9c | 243 | .has_bsd_ring = 1, |
cfdf1fa2 KH |
244 | }; |
245 | ||
9a7e8492 | 246 | static const struct intel_device_info intel_gm45_info = { |
7eb552ae | 247 | .gen = 4, .is_g4x = 1, .num_pipes = 2, |
e3c4e5dd | 248 | .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1, |
c96c3a8c | 249 | .has_pipe_cxsr = 1, .has_hotplug = 1, |
a6c45cf0 | 250 | .supports_tv = 1, |
92f49d9c | 251 | .has_bsd_ring = 1, |
cfdf1fa2 KH |
252 | }; |
253 | ||
9a7e8492 | 254 | static const struct intel_device_info intel_pineview_info = { |
7eb552ae | 255 | .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2, |
c96c3a8c | 256 | .need_gfx_hws = 1, .has_hotplug = 1, |
31578148 | 257 | .has_overlay = 1, |
cfdf1fa2 KH |
258 | }; |
259 | ||
9a7e8492 | 260 | static const struct intel_device_info intel_ironlake_d_info = { |
7eb552ae | 261 | .gen = 5, .num_pipes = 2, |
5a117db7 | 262 | .need_gfx_hws = 1, .has_hotplug = 1, |
92f49d9c | 263 | .has_bsd_ring = 1, |
cfdf1fa2 KH |
264 | }; |
265 | ||
9a7e8492 | 266 | static const struct intel_device_info intel_ironlake_m_info = { |
7eb552ae | 267 | .gen = 5, .is_mobile = 1, .num_pipes = 2, |
e3c4e5dd | 268 | .need_gfx_hws = 1, .has_hotplug = 1, |
c1a9f047 | 269 | .has_fbc = 1, |
92f49d9c | 270 | .has_bsd_ring = 1, |
cfdf1fa2 KH |
271 | }; |
272 | ||
9a7e8492 | 273 | static const struct intel_device_info intel_sandybridge_d_info = { |
7eb552ae | 274 | .gen = 6, .num_pipes = 2, |
c96c3a8c | 275 | .need_gfx_hws = 1, .has_hotplug = 1, |
881f47b6 | 276 | .has_bsd_ring = 1, |
549f7365 | 277 | .has_blt_ring = 1, |
3d29b842 | 278 | .has_llc = 1, |
b7884eb4 | 279 | .has_force_wake = 1, |
f6e450a6 EA |
280 | }; |
281 | ||
9a7e8492 | 282 | static const struct intel_device_info intel_sandybridge_m_info = { |
7eb552ae | 283 | .gen = 6, .is_mobile = 1, .num_pipes = 2, |
c96c3a8c | 284 | .need_gfx_hws = 1, .has_hotplug = 1, |
9c04f015 | 285 | .has_fbc = 1, |
881f47b6 | 286 | .has_bsd_ring = 1, |
549f7365 | 287 | .has_blt_ring = 1, |
3d29b842 | 288 | .has_llc = 1, |
b7884eb4 | 289 | .has_force_wake = 1, |
a13e4093 EA |
290 | }; |
291 | ||
219f4fdb BW |
292 | #define GEN7_FEATURES \ |
293 | .gen = 7, .num_pipes = 3, \ | |
294 | .need_gfx_hws = 1, .has_hotplug = 1, \ | |
295 | .has_bsd_ring = 1, \ | |
296 | .has_blt_ring = 1, \ | |
297 | .has_llc = 1, \ | |
298 | .has_force_wake = 1 | |
299 | ||
c76b615c | 300 | static const struct intel_device_info intel_ivybridge_d_info = { |
219f4fdb BW |
301 | GEN7_FEATURES, |
302 | .is_ivybridge = 1, | |
c76b615c JB |
303 | }; |
304 | ||
305 | static const struct intel_device_info intel_ivybridge_m_info = { | |
219f4fdb BW |
306 | GEN7_FEATURES, |
307 | .is_ivybridge = 1, | |
308 | .is_mobile = 1, | |
abe959c7 | 309 | .has_fbc = 1, |
c76b615c JB |
310 | }; |
311 | ||
999bcdea BW |
312 | static const struct intel_device_info intel_ivybridge_q_info = { |
313 | GEN7_FEATURES, | |
314 | .is_ivybridge = 1, | |
315 | .num_pipes = 0, /* legal, last one wins */ | |
316 | }; | |
317 | ||
70a3eb7a | 318 | static const struct intel_device_info intel_valleyview_m_info = { |
219f4fdb BW |
319 | GEN7_FEATURES, |
320 | .is_mobile = 1, | |
321 | .num_pipes = 2, | |
70a3eb7a | 322 | .is_valleyview = 1, |
fba5d532 | 323 | .display_mmio_offset = VLV_DISPLAY_BASE, |
30ccd964 | 324 | .has_llc = 0, /* legal, last one wins */ |
70a3eb7a JB |
325 | }; |
326 | ||
327 | static const struct intel_device_info intel_valleyview_d_info = { | |
219f4fdb BW |
328 | GEN7_FEATURES, |
329 | .num_pipes = 2, | |
70a3eb7a | 330 | .is_valleyview = 1, |
fba5d532 | 331 | .display_mmio_offset = VLV_DISPLAY_BASE, |
30ccd964 | 332 | .has_llc = 0, /* legal, last one wins */ |
70a3eb7a JB |
333 | }; |
334 | ||
4cae9ae0 | 335 | static const struct intel_device_info intel_haswell_d_info = { |
219f4fdb BW |
336 | GEN7_FEATURES, |
337 | .is_haswell = 1, | |
dd93be58 | 338 | .has_ddi = 1, |
30568c45 | 339 | .has_fpga_dbg = 1, |
f72a1183 | 340 | .has_vebox_ring = 1, |
4cae9ae0 ED |
341 | }; |
342 | ||
343 | static const struct intel_device_info intel_haswell_m_info = { | |
219f4fdb BW |
344 | GEN7_FEATURES, |
345 | .is_haswell = 1, | |
346 | .is_mobile = 1, | |
dd93be58 | 347 | .has_ddi = 1, |
30568c45 | 348 | .has_fpga_dbg = 1, |
891348b2 | 349 | .has_fbc = 1, |
f72a1183 | 350 | .has_vebox_ring = 1, |
c76b615c JB |
351 | }; |
352 | ||
6103da0d CW |
353 | static const struct pci_device_id pciidlist[] = { /* aka */ |
354 | INTEL_VGA_DEVICE(0x3577, &intel_i830_info), /* I830_M */ | |
355 | INTEL_VGA_DEVICE(0x2562, &intel_845g_info), /* 845_G */ | |
356 | INTEL_VGA_DEVICE(0x3582, &intel_i85x_info), /* I855_GM */ | |
5ce8ba7c | 357 | INTEL_VGA_DEVICE(0x358e, &intel_i85x_info), |
6103da0d CW |
358 | INTEL_VGA_DEVICE(0x2572, &intel_i865g_info), /* I865_G */ |
359 | INTEL_VGA_DEVICE(0x2582, &intel_i915g_info), /* I915_G */ | |
360 | INTEL_VGA_DEVICE(0x258a, &intel_i915g_info), /* E7221_G */ | |
361 | INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info), /* I915_GM */ | |
362 | INTEL_VGA_DEVICE(0x2772, &intel_i945g_info), /* I945_G */ | |
363 | INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info), /* I945_GM */ | |
364 | INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info), /* I945_GME */ | |
365 | INTEL_VGA_DEVICE(0x2972, &intel_i965g_info), /* I946_GZ */ | |
366 | INTEL_VGA_DEVICE(0x2982, &intel_i965g_info), /* G35_G */ | |
367 | INTEL_VGA_DEVICE(0x2992, &intel_i965g_info), /* I965_Q */ | |
368 | INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info), /* I965_G */ | |
369 | INTEL_VGA_DEVICE(0x29b2, &intel_g33_info), /* Q35_G */ | |
370 | INTEL_VGA_DEVICE(0x29c2, &intel_g33_info), /* G33_G */ | |
371 | INTEL_VGA_DEVICE(0x29d2, &intel_g33_info), /* Q33_G */ | |
372 | INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info), /* I965_GM */ | |
373 | INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info), /* I965_GME */ | |
374 | INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info), /* GM45_G */ | |
375 | INTEL_VGA_DEVICE(0x2e02, &intel_g45_info), /* IGD_E_G */ | |
376 | INTEL_VGA_DEVICE(0x2e12, &intel_g45_info), /* Q45_G */ | |
377 | INTEL_VGA_DEVICE(0x2e22, &intel_g45_info), /* G45_G */ | |
378 | INTEL_VGA_DEVICE(0x2e32, &intel_g45_info), /* G41_G */ | |
379 | INTEL_VGA_DEVICE(0x2e42, &intel_g45_info), /* B43_G */ | |
41a51428 | 380 | INTEL_VGA_DEVICE(0x2e92, &intel_g45_info), /* B43_G.1 */ |
cfdf1fa2 KH |
381 | INTEL_VGA_DEVICE(0xa001, &intel_pineview_info), |
382 | INTEL_VGA_DEVICE(0xa011, &intel_pineview_info), | |
383 | INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info), | |
384 | INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info), | |
f6e450a6 | 385 | INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info), |
85540480 ZW |
386 | INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info), |
387 | INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info), | |
a13e4093 | 388 | INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info), |
85540480 | 389 | INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info), |
4fefe435 | 390 | INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info), |
85540480 | 391 | INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info), |
c76b615c JB |
392 | INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info), /* GT1 mobile */ |
393 | INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info), /* GT2 mobile */ | |
394 | INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */ | |
395 | INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */ | |
396 | INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */ | |
999bcdea | 397 | INTEL_QUANTA_VGA_DEVICE(&intel_ivybridge_q_info), /* Quanta transcode */ |
cc22a938 | 398 | INTEL_VGA_DEVICE(0x016a, &intel_ivybridge_d_info), /* GT2 server */ |
c14f5286 ED |
399 | INTEL_VGA_DEVICE(0x0402, &intel_haswell_d_info), /* GT1 desktop */ |
400 | INTEL_VGA_DEVICE(0x0412, &intel_haswell_d_info), /* GT2 desktop */ | |
1c98b487 | 401 | INTEL_VGA_DEVICE(0x0422, &intel_haswell_d_info), /* GT3 desktop */ |
c14f5286 ED |
402 | INTEL_VGA_DEVICE(0x040a, &intel_haswell_d_info), /* GT1 server */ |
403 | INTEL_VGA_DEVICE(0x041a, &intel_haswell_d_info), /* GT2 server */ | |
1c98b487 | 404 | INTEL_VGA_DEVICE(0x042a, &intel_haswell_d_info), /* GT3 server */ |
c14f5286 ED |
405 | INTEL_VGA_DEVICE(0x0406, &intel_haswell_m_info), /* GT1 mobile */ |
406 | INTEL_VGA_DEVICE(0x0416, &intel_haswell_m_info), /* GT2 mobile */ | |
da612d88 | 407 | INTEL_VGA_DEVICE(0x0426, &intel_haswell_m_info), /* GT2 mobile */ |
1c98b487 RV |
408 | INTEL_VGA_DEVICE(0x040B, &intel_haswell_d_info), /* GT1 reserved */ |
409 | INTEL_VGA_DEVICE(0x041B, &intel_haswell_d_info), /* GT2 reserved */ | |
410 | INTEL_VGA_DEVICE(0x042B, &intel_haswell_d_info), /* GT3 reserved */ | |
411 | INTEL_VGA_DEVICE(0x040E, &intel_haswell_d_info), /* GT1 reserved */ | |
412 | INTEL_VGA_DEVICE(0x041E, &intel_haswell_d_info), /* GT2 reserved */ | |
413 | INTEL_VGA_DEVICE(0x042E, &intel_haswell_d_info), /* GT3 reserved */ | |
da612d88 PZ |
414 | INTEL_VGA_DEVICE(0x0C02, &intel_haswell_d_info), /* SDV GT1 desktop */ |
415 | INTEL_VGA_DEVICE(0x0C12, &intel_haswell_d_info), /* SDV GT2 desktop */ | |
1c98b487 | 416 | INTEL_VGA_DEVICE(0x0C22, &intel_haswell_d_info), /* SDV GT3 desktop */ |
da612d88 PZ |
417 | INTEL_VGA_DEVICE(0x0C0A, &intel_haswell_d_info), /* SDV GT1 server */ |
418 | INTEL_VGA_DEVICE(0x0C1A, &intel_haswell_d_info), /* SDV GT2 server */ | |
1c98b487 | 419 | INTEL_VGA_DEVICE(0x0C2A, &intel_haswell_d_info), /* SDV GT3 server */ |
da612d88 PZ |
420 | INTEL_VGA_DEVICE(0x0C06, &intel_haswell_m_info), /* SDV GT1 mobile */ |
421 | INTEL_VGA_DEVICE(0x0C16, &intel_haswell_m_info), /* SDV GT2 mobile */ | |
1c98b487 RV |
422 | INTEL_VGA_DEVICE(0x0C26, &intel_haswell_m_info), /* SDV GT3 mobile */ |
423 | INTEL_VGA_DEVICE(0x0C0B, &intel_haswell_d_info), /* SDV GT1 reserved */ | |
424 | INTEL_VGA_DEVICE(0x0C1B, &intel_haswell_d_info), /* SDV GT2 reserved */ | |
425 | INTEL_VGA_DEVICE(0x0C2B, &intel_haswell_d_info), /* SDV GT3 reserved */ | |
426 | INTEL_VGA_DEVICE(0x0C0E, &intel_haswell_d_info), /* SDV GT1 reserved */ | |
427 | INTEL_VGA_DEVICE(0x0C1E, &intel_haswell_d_info), /* SDV GT2 reserved */ | |
428 | INTEL_VGA_DEVICE(0x0C2E, &intel_haswell_d_info), /* SDV GT3 reserved */ | |
da612d88 PZ |
429 | INTEL_VGA_DEVICE(0x0A02, &intel_haswell_d_info), /* ULT GT1 desktop */ |
430 | INTEL_VGA_DEVICE(0x0A12, &intel_haswell_d_info), /* ULT GT2 desktop */ | |
1c98b487 | 431 | INTEL_VGA_DEVICE(0x0A22, &intel_haswell_d_info), /* ULT GT3 desktop */ |
da612d88 PZ |
432 | INTEL_VGA_DEVICE(0x0A0A, &intel_haswell_d_info), /* ULT GT1 server */ |
433 | INTEL_VGA_DEVICE(0x0A1A, &intel_haswell_d_info), /* ULT GT2 server */ | |
1c98b487 | 434 | INTEL_VGA_DEVICE(0x0A2A, &intel_haswell_d_info), /* ULT GT3 server */ |
da612d88 PZ |
435 | INTEL_VGA_DEVICE(0x0A06, &intel_haswell_m_info), /* ULT GT1 mobile */ |
436 | INTEL_VGA_DEVICE(0x0A16, &intel_haswell_m_info), /* ULT GT2 mobile */ | |
1c98b487 RV |
437 | INTEL_VGA_DEVICE(0x0A26, &intel_haswell_m_info), /* ULT GT3 mobile */ |
438 | INTEL_VGA_DEVICE(0x0A0B, &intel_haswell_d_info), /* ULT GT1 reserved */ | |
439 | INTEL_VGA_DEVICE(0x0A1B, &intel_haswell_d_info), /* ULT GT2 reserved */ | |
440 | INTEL_VGA_DEVICE(0x0A2B, &intel_haswell_d_info), /* ULT GT3 reserved */ | |
441 | INTEL_VGA_DEVICE(0x0A0E, &intel_haswell_m_info), /* ULT GT1 reserved */ | |
442 | INTEL_VGA_DEVICE(0x0A1E, &intel_haswell_m_info), /* ULT GT2 reserved */ | |
443 | INTEL_VGA_DEVICE(0x0A2E, &intel_haswell_m_info), /* ULT GT3 reserved */ | |
86c268ed KG |
444 | INTEL_VGA_DEVICE(0x0D02, &intel_haswell_d_info), /* CRW GT1 desktop */ |
445 | INTEL_VGA_DEVICE(0x0D12, &intel_haswell_d_info), /* CRW GT2 desktop */ | |
1c98b487 | 446 | INTEL_VGA_DEVICE(0x0D22, &intel_haswell_d_info), /* CRW GT3 desktop */ |
86c268ed KG |
447 | INTEL_VGA_DEVICE(0x0D0A, &intel_haswell_d_info), /* CRW GT1 server */ |
448 | INTEL_VGA_DEVICE(0x0D1A, &intel_haswell_d_info), /* CRW GT2 server */ | |
1c98b487 | 449 | INTEL_VGA_DEVICE(0x0D2A, &intel_haswell_d_info), /* CRW GT3 server */ |
86c268ed KG |
450 | INTEL_VGA_DEVICE(0x0D06, &intel_haswell_m_info), /* CRW GT1 mobile */ |
451 | INTEL_VGA_DEVICE(0x0D16, &intel_haswell_m_info), /* CRW GT2 mobile */ | |
1c98b487 RV |
452 | INTEL_VGA_DEVICE(0x0D26, &intel_haswell_m_info), /* CRW GT3 mobile */ |
453 | INTEL_VGA_DEVICE(0x0D0B, &intel_haswell_d_info), /* CRW GT1 reserved */ | |
454 | INTEL_VGA_DEVICE(0x0D1B, &intel_haswell_d_info), /* CRW GT2 reserved */ | |
455 | INTEL_VGA_DEVICE(0x0D2B, &intel_haswell_d_info), /* CRW GT3 reserved */ | |
456 | INTEL_VGA_DEVICE(0x0D0E, &intel_haswell_d_info), /* CRW GT1 reserved */ | |
457 | INTEL_VGA_DEVICE(0x0D1E, &intel_haswell_d_info), /* CRW GT2 reserved */ | |
458 | INTEL_VGA_DEVICE(0x0D2E, &intel_haswell_d_info), /* CRW GT3 reserved */ | |
ff049b6c | 459 | INTEL_VGA_DEVICE(0x0f30, &intel_valleyview_m_info), |
d7fee5f6 JB |
460 | INTEL_VGA_DEVICE(0x0f31, &intel_valleyview_m_info), |
461 | INTEL_VGA_DEVICE(0x0f32, &intel_valleyview_m_info), | |
462 | INTEL_VGA_DEVICE(0x0f33, &intel_valleyview_m_info), | |
ff049b6c JB |
463 | INTEL_VGA_DEVICE(0x0157, &intel_valleyview_m_info), |
464 | INTEL_VGA_DEVICE(0x0155, &intel_valleyview_d_info), | |
49ae35f2 | 465 | {0, 0, 0} |
1da177e4 LT |
466 | }; |
467 | ||
79e53945 JB |
468 | #if defined(CONFIG_DRM_I915_KMS) |
469 | MODULE_DEVICE_TABLE(pci, pciidlist); | |
470 | #endif | |
471 | ||
0206e353 | 472 | void intel_detect_pch(struct drm_device *dev) |
3bad0781 ZW |
473 | { |
474 | struct drm_i915_private *dev_priv = dev->dev_private; | |
475 | struct pci_dev *pch; | |
476 | ||
ce1bb329 BW |
477 | /* In all current cases, num_pipes is equivalent to the PCH_NOP setting |
478 | * (which really amounts to a PCH but no South Display). | |
479 | */ | |
480 | if (INTEL_INFO(dev)->num_pipes == 0) { | |
481 | dev_priv->pch_type = PCH_NOP; | |
ce1bb329 BW |
482 | return; |
483 | } | |
484 | ||
3bad0781 ZW |
485 | /* |
486 | * The reason to probe ISA bridge instead of Dev31:Fun0 is to | |
487 | * make graphics device passthrough work easy for VMM, that only | |
488 | * need to expose ISA bridge to let driver know the real hardware | |
489 | * underneath. This is a requirement from virtualization team. | |
6a9c4b35 RG |
490 | * |
491 | * In some virtualized environments (e.g. XEN), there is irrelevant | |
492 | * ISA bridge in the system. To work reliably, we should scan trhough | |
493 | * all the ISA bridge devices and check for the first match, instead | |
494 | * of only checking the first one. | |
3bad0781 ZW |
495 | */ |
496 | pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL); | |
6a9c4b35 RG |
497 | while (pch) { |
498 | struct pci_dev *curr = pch; | |
3bad0781 | 499 | if (pch->vendor == PCI_VENDOR_ID_INTEL) { |
17a303ec | 500 | unsigned short id; |
3bad0781 | 501 | id = pch->device & INTEL_PCH_DEVICE_ID_MASK; |
17a303ec | 502 | dev_priv->pch_id = id; |
3bad0781 | 503 | |
90711d50 JB |
504 | if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) { |
505 | dev_priv->pch_type = PCH_IBX; | |
506 | DRM_DEBUG_KMS("Found Ibex Peak PCH\n"); | |
7fcb83cd | 507 | WARN_ON(!IS_GEN5(dev)); |
90711d50 | 508 | } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) { |
3bad0781 ZW |
509 | dev_priv->pch_type = PCH_CPT; |
510 | DRM_DEBUG_KMS("Found CougarPoint PCH\n"); | |
7fcb83cd | 511 | WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev))); |
c792513b JB |
512 | } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) { |
513 | /* PantherPoint is CPT compatible */ | |
514 | dev_priv->pch_type = PCH_CPT; | |
515 | DRM_DEBUG_KMS("Found PatherPoint PCH\n"); | |
7fcb83cd | 516 | WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev))); |
eb877ebf ED |
517 | } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) { |
518 | dev_priv->pch_type = PCH_LPT; | |
519 | DRM_DEBUG_KMS("Found LynxPoint PCH\n"); | |
7fcb83cd | 520 | WARN_ON(!IS_HASWELL(dev)); |
08e1413d | 521 | WARN_ON(IS_ULT(dev)); |
ae6935dd WSC |
522 | } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { |
523 | dev_priv->pch_type = PCH_LPT; | |
ae6935dd WSC |
524 | DRM_DEBUG_KMS("Found LynxPoint LP PCH\n"); |
525 | WARN_ON(!IS_HASWELL(dev)); | |
08e1413d | 526 | WARN_ON(!IS_ULT(dev)); |
6a9c4b35 RG |
527 | } else { |
528 | goto check_next; | |
3bad0781 | 529 | } |
6a9c4b35 RG |
530 | pci_dev_put(pch); |
531 | break; | |
3bad0781 | 532 | } |
6a9c4b35 RG |
533 | check_next: |
534 | pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, curr); | |
535 | pci_dev_put(curr); | |
3bad0781 | 536 | } |
6a9c4b35 RG |
537 | if (!pch) |
538 | DRM_DEBUG_KMS("No PCH found?\n"); | |
3bad0781 ZW |
539 | } |
540 | ||
2911a35b BW |
541 | bool i915_semaphore_is_enabled(struct drm_device *dev) |
542 | { | |
543 | if (INTEL_INFO(dev)->gen < 6) | |
544 | return 0; | |
545 | ||
546 | if (i915_semaphores >= 0) | |
547 | return i915_semaphores; | |
548 | ||
59de3295 | 549 | #ifdef CONFIG_INTEL_IOMMU |
2911a35b | 550 | /* Enable semaphores on SNB when IO remapping is off */ |
59de3295 DV |
551 | if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) |
552 | return false; | |
553 | #endif | |
2911a35b BW |
554 | |
555 | return 1; | |
556 | } | |
557 | ||
84b79f8d | 558 | static int i915_drm_freeze(struct drm_device *dev) |
ba8bbcf6 | 559 | { |
61caf87c | 560 | struct drm_i915_private *dev_priv = dev->dev_private; |
24576d23 | 561 | struct drm_crtc *crtc; |
61caf87c | 562 | |
b8efb17b ZR |
563 | /* ignore lid events during suspend */ |
564 | mutex_lock(&dev_priv->modeset_restore_lock); | |
565 | dev_priv->modeset_restore = MODESET_SUSPENDED; | |
566 | mutex_unlock(&dev_priv->modeset_restore_lock); | |
567 | ||
c67a470b PZ |
568 | /* We do a lot of poking in a lot of registers, make sure they work |
569 | * properly. */ | |
570 | hsw_disable_package_c8(dev_priv); | |
cb10799c PZ |
571 | intel_set_power_well(dev, true); |
572 | ||
5bcf719b DA |
573 | drm_kms_helper_poll_disable(dev); |
574 | ||
ba8bbcf6 | 575 | pci_save_state(dev->pdev); |
ba8bbcf6 | 576 | |
5669fcac | 577 | /* If KMS is active, we do the leavevt stuff here */ |
226485e9 | 578 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
db1b76ca DV |
579 | int error; |
580 | ||
581 | mutex_lock(&dev->struct_mutex); | |
582 | error = i915_gem_idle(dev); | |
583 | mutex_unlock(&dev->struct_mutex); | |
84b79f8d | 584 | if (error) { |
226485e9 | 585 | dev_err(&dev->pdev->dev, |
84b79f8d RW |
586 | "GEM idle failed, resume might fail\n"); |
587 | return error; | |
588 | } | |
a261b246 | 589 | |
1a01ab3b JB |
590 | cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work); |
591 | ||
226485e9 | 592 | drm_irq_uninstall(dev); |
15239099 | 593 | dev_priv->enable_hotplug_processing = false; |
24576d23 JB |
594 | /* |
595 | * Disable CRTCs directly since we want to preserve sw state | |
596 | * for _thaw. | |
597 | */ | |
598 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) | |
599 | dev_priv->display.crtc_disable(crtc); | |
7d708ee4 ID |
600 | |
601 | intel_modeset_suspend_hw(dev); | |
5669fcac JB |
602 | } |
603 | ||
9e06dd39 JB |
604 | i915_save_state(dev); |
605 | ||
44834a67 | 606 | intel_opregion_fini(dev); |
8ee1c3db | 607 | |
3fa016a0 | 608 | console_lock(); |
b6f3eff7 | 609 | intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED); |
3fa016a0 DA |
610 | console_unlock(); |
611 | ||
61caf87c | 612 | return 0; |
84b79f8d RW |
613 | } |
614 | ||
6a9ee8af | 615 | int i915_suspend(struct drm_device *dev, pm_message_t state) |
84b79f8d RW |
616 | { |
617 | int error; | |
618 | ||
619 | if (!dev || !dev->dev_private) { | |
620 | DRM_ERROR("dev: %p\n", dev); | |
621 | DRM_ERROR("DRM not initialized, aborting suspend.\n"); | |
622 | return -ENODEV; | |
623 | } | |
624 | ||
625 | if (state.event == PM_EVENT_PRETHAW) | |
626 | return 0; | |
627 | ||
5bcf719b DA |
628 | |
629 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) | |
630 | return 0; | |
6eecba33 | 631 | |
84b79f8d RW |
632 | error = i915_drm_freeze(dev); |
633 | if (error) | |
634 | return error; | |
635 | ||
b932ccb5 DA |
636 | if (state.event == PM_EVENT_SUSPEND) { |
637 | /* Shut down the device */ | |
638 | pci_disable_device(dev->pdev); | |
639 | pci_set_power_state(dev->pdev, PCI_D3hot); | |
640 | } | |
ba8bbcf6 JB |
641 | |
642 | return 0; | |
643 | } | |
644 | ||
073f34d9 JB |
645 | void intel_console_resume(struct work_struct *work) |
646 | { | |
647 | struct drm_i915_private *dev_priv = | |
648 | container_of(work, struct drm_i915_private, | |
649 | console_resume_work); | |
650 | struct drm_device *dev = dev_priv->dev; | |
651 | ||
652 | console_lock(); | |
b6f3eff7 | 653 | intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING); |
073f34d9 JB |
654 | console_unlock(); |
655 | } | |
656 | ||
bb60b969 JB |
657 | static void intel_resume_hotplug(struct drm_device *dev) |
658 | { | |
659 | struct drm_mode_config *mode_config = &dev->mode_config; | |
660 | struct intel_encoder *encoder; | |
661 | ||
662 | mutex_lock(&mode_config->mutex); | |
663 | DRM_DEBUG_KMS("running encoder hotplug functions\n"); | |
664 | ||
665 | list_for_each_entry(encoder, &mode_config->encoder_list, base.head) | |
666 | if (encoder->hot_plug) | |
667 | encoder->hot_plug(encoder); | |
668 | ||
669 | mutex_unlock(&mode_config->mutex); | |
670 | ||
671 | /* Just fire off a uevent and let userspace tell us what to do */ | |
672 | drm_helper_hpd_irq_event(dev); | |
673 | } | |
674 | ||
1abd02e2 | 675 | static int __i915_drm_thaw(struct drm_device *dev) |
ba8bbcf6 | 676 | { |
5669fcac | 677 | struct drm_i915_private *dev_priv = dev->dev_private; |
84b79f8d | 678 | int error = 0; |
8ee1c3db | 679 | |
61caf87c | 680 | i915_restore_state(dev); |
44834a67 | 681 | intel_opregion_setup(dev); |
61caf87c | 682 | |
5669fcac JB |
683 | /* KMS EnterVT equivalent */ |
684 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { | |
dde86e2d | 685 | intel_init_pch_refclk(dev); |
1833b134 | 686 | |
5669fcac | 687 | mutex_lock(&dev->struct_mutex); |
5669fcac | 688 | |
f691e2f4 | 689 | error = i915_gem_init_hw(dev); |
5669fcac | 690 | mutex_unlock(&dev->struct_mutex); |
226485e9 | 691 | |
15239099 DV |
692 | /* We need working interrupts for modeset enabling ... */ |
693 | drm_irq_install(dev); | |
694 | ||
1833b134 | 695 | intel_modeset_init_hw(dev); |
24576d23 JB |
696 | |
697 | drm_modeset_lock_all(dev); | |
698 | intel_modeset_setup_hw_state(dev, true); | |
699 | drm_modeset_unlock_all(dev); | |
15239099 DV |
700 | |
701 | /* | |
702 | * ... but also need to make sure that hotplug processing | |
703 | * doesn't cause havoc. Like in the driver load code we don't | |
704 | * bother with the tiny race here where we might loose hotplug | |
705 | * notifications. | |
706 | * */ | |
20afbda2 | 707 | intel_hpd_init(dev); |
15239099 | 708 | dev_priv->enable_hotplug_processing = true; |
bb60b969 JB |
709 | /* Config may have changed between suspend and resume */ |
710 | intel_resume_hotplug(dev); | |
d5bb081b | 711 | } |
1daed3fb | 712 | |
44834a67 CW |
713 | intel_opregion_init(dev); |
714 | ||
073f34d9 JB |
715 | /* |
716 | * The console lock can be pretty contented on resume due | |
717 | * to all the printk activity. Try to keep it out of the hot | |
718 | * path of resume if possible. | |
719 | */ | |
720 | if (console_trylock()) { | |
b6f3eff7 | 721 | intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING); |
073f34d9 JB |
722 | console_unlock(); |
723 | } else { | |
724 | schedule_work(&dev_priv->console_resume_work); | |
725 | } | |
726 | ||
c67a470b PZ |
727 | /* Undo what we did at i915_drm_freeze so the refcount goes back to the |
728 | * expected level. */ | |
729 | hsw_enable_package_c8(dev_priv); | |
730 | ||
b8efb17b ZR |
731 | mutex_lock(&dev_priv->modeset_restore_lock); |
732 | dev_priv->modeset_restore = MODESET_DONE; | |
733 | mutex_unlock(&dev_priv->modeset_restore_lock); | |
84b79f8d RW |
734 | return error; |
735 | } | |
736 | ||
1abd02e2 JB |
737 | static int i915_drm_thaw(struct drm_device *dev) |
738 | { | |
739 | int error = 0; | |
740 | ||
907b28c5 | 741 | intel_uncore_sanitize(dev); |
1abd02e2 JB |
742 | |
743 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { | |
744 | mutex_lock(&dev->struct_mutex); | |
745 | i915_gem_restore_gtt_mappings(dev); | |
746 | mutex_unlock(&dev->struct_mutex); | |
747 | } | |
748 | ||
749 | __i915_drm_thaw(dev); | |
750 | ||
84b79f8d RW |
751 | return error; |
752 | } | |
753 | ||
6a9ee8af | 754 | int i915_resume(struct drm_device *dev) |
84b79f8d | 755 | { |
1abd02e2 | 756 | struct drm_i915_private *dev_priv = dev->dev_private; |
6eecba33 CW |
757 | int ret; |
758 | ||
5bcf719b DA |
759 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
760 | return 0; | |
761 | ||
84b79f8d RW |
762 | if (pci_enable_device(dev->pdev)) |
763 | return -EIO; | |
764 | ||
765 | pci_set_master(dev->pdev); | |
766 | ||
907b28c5 | 767 | intel_uncore_sanitize(dev); |
1abd02e2 JB |
768 | |
769 | /* | |
770 | * Platforms with opregion should have sane BIOS, older ones (gen3 and | |
771 | * earlier) need this since the BIOS might clear all our scratch PTEs. | |
772 | */ | |
773 | if (drm_core_check_feature(dev, DRIVER_MODESET) && | |
774 | !dev_priv->opregion.header) { | |
775 | mutex_lock(&dev->struct_mutex); | |
776 | i915_gem_restore_gtt_mappings(dev); | |
777 | mutex_unlock(&dev->struct_mutex); | |
778 | } | |
779 | ||
780 | ret = __i915_drm_thaw(dev); | |
6eecba33 CW |
781 | if (ret) |
782 | return ret; | |
783 | ||
784 | drm_kms_helper_poll_enable(dev); | |
785 | return 0; | |
ba8bbcf6 JB |
786 | } |
787 | ||
11ed50ec | 788 | /** |
f3953dcb | 789 | * i915_reset - reset chip after a hang |
11ed50ec | 790 | * @dev: drm device to reset |
11ed50ec BG |
791 | * |
792 | * Reset the chip. Useful if a hang is detected. Returns zero on successful | |
793 | * reset or otherwise an error code. | |
794 | * | |
795 | * Procedure is fairly simple: | |
796 | * - reset the chip using the reset reg | |
797 | * - re-init context state | |
798 | * - re-init hardware status page | |
799 | * - re-init ring buffer | |
800 | * - re-init interrupt state | |
801 | * - re-init display | |
802 | */ | |
d4b8bb2a | 803 | int i915_reset(struct drm_device *dev) |
11ed50ec BG |
804 | { |
805 | drm_i915_private_t *dev_priv = dev->dev_private; | |
2e7c8ee7 | 806 | bool simulated; |
0573ed4a | 807 | int ret; |
11ed50ec | 808 | |
d78cb50b CW |
809 | if (!i915_try_reset) |
810 | return 0; | |
811 | ||
d54a02c0 | 812 | mutex_lock(&dev->struct_mutex); |
11ed50ec | 813 | |
069efc1d | 814 | i915_gem_reset(dev); |
77f01230 | 815 | |
2e7c8ee7 CW |
816 | simulated = dev_priv->gpu_error.stop_rings != 0; |
817 | ||
818 | if (!simulated && get_seconds() - dev_priv->gpu_error.last_reset < 5) { | |
ae681d96 | 819 | DRM_ERROR("GPU hanging too fast, declaring wedged!\n"); |
2e7c8ee7 CW |
820 | ret = -ENODEV; |
821 | } else { | |
d4b8bb2a | 822 | ret = intel_gpu_reset(dev); |
350d2706 | 823 | |
2e7c8ee7 CW |
824 | /* Also reset the gpu hangman. */ |
825 | if (simulated) { | |
826 | DRM_INFO("Simulated gpu hang, resetting stop_rings\n"); | |
827 | dev_priv->gpu_error.stop_rings = 0; | |
828 | if (ret == -ENODEV) { | |
829 | DRM_ERROR("Reset not implemented, but ignoring " | |
830 | "error for simulated gpu hangs\n"); | |
831 | ret = 0; | |
832 | } | |
833 | } else | |
834 | dev_priv->gpu_error.last_reset = get_seconds(); | |
835 | } | |
0573ed4a | 836 | if (ret) { |
f803aa55 | 837 | DRM_ERROR("Failed to reset chip.\n"); |
f953c935 | 838 | mutex_unlock(&dev->struct_mutex); |
f803aa55 | 839 | return ret; |
11ed50ec BG |
840 | } |
841 | ||
842 | /* Ok, now get things going again... */ | |
843 | ||
844 | /* | |
845 | * Everything depends on having the GTT running, so we need to start | |
846 | * there. Fortunately we don't need to do this unless we reset the | |
847 | * chip at a PCI level. | |
848 | * | |
849 | * Next we need to restore the context, but we don't use those | |
850 | * yet either... | |
851 | * | |
852 | * Ring buffer needs to be re-initialized in the KMS case, or if X | |
853 | * was running at the time of the reset (i.e. we weren't VT | |
854 | * switched away). | |
855 | */ | |
856 | if (drm_core_check_feature(dev, DRIVER_MODESET) || | |
db1b76ca | 857 | !dev_priv->ums.mm_suspended) { |
b4519513 CW |
858 | struct intel_ring_buffer *ring; |
859 | int i; | |
860 | ||
db1b76ca | 861 | dev_priv->ums.mm_suspended = 0; |
75a6898f | 862 | |
f691e2f4 DV |
863 | i915_gem_init_swizzling(dev); |
864 | ||
b4519513 CW |
865 | for_each_ring(ring, dev_priv, i) |
866 | ring->init(ring); | |
75a6898f | 867 | |
254f965c | 868 | i915_gem_context_init(dev); |
b7c36d25 BW |
869 | if (dev_priv->mm.aliasing_ppgtt) { |
870 | ret = dev_priv->mm.aliasing_ppgtt->enable(dev); | |
871 | if (ret) | |
872 | i915_gem_cleanup_aliasing_ppgtt(dev); | |
873 | } | |
e21af88d | 874 | |
8e88a2bd DV |
875 | /* |
876 | * It would make sense to re-init all the other hw state, at | |
877 | * least the rps/rc6/emon init done within modeset_init_hw. For | |
878 | * some unknown reason, this blows up my ilk, so don't. | |
879 | */ | |
f817586c | 880 | |
8e88a2bd | 881 | mutex_unlock(&dev->struct_mutex); |
f817586c | 882 | |
11ed50ec BG |
883 | drm_irq_uninstall(dev); |
884 | drm_irq_install(dev); | |
20afbda2 | 885 | intel_hpd_init(dev); |
bcbc324a DV |
886 | } else { |
887 | mutex_unlock(&dev->struct_mutex); | |
11ed50ec BG |
888 | } |
889 | ||
11ed50ec BG |
890 | return 0; |
891 | } | |
892 | ||
56550d94 | 893 | static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) |
112b715e | 894 | { |
01a06850 DV |
895 | struct intel_device_info *intel_info = |
896 | (struct intel_device_info *) ent->driver_data; | |
897 | ||
5fe49d86 CW |
898 | /* Only bind to function 0 of the device. Early generations |
899 | * used function 1 as a placeholder for multi-head. This causes | |
900 | * us confusion instead, especially on the systems where both | |
901 | * functions have the same PCI-ID! | |
902 | */ | |
903 | if (PCI_FUNC(pdev->devfn)) | |
904 | return -ENODEV; | |
905 | ||
01a06850 DV |
906 | /* We've managed to ship a kms-enabled ddx that shipped with an XvMC |
907 | * implementation for gen3 (and only gen3) that used legacy drm maps | |
908 | * (gasp!) to share buffers between X and the client. Hence we need to | |
909 | * keep around the fake agp stuff for gen3, even when kms is enabled. */ | |
910 | if (intel_info->gen != 3) { | |
911 | driver.driver_features &= | |
912 | ~(DRIVER_USE_AGP | DRIVER_REQUIRE_AGP); | |
913 | } else if (!intel_agp_enabled) { | |
914 | DRM_ERROR("drm/i915 can't work without intel_agp module!\n"); | |
915 | return -ENODEV; | |
916 | } | |
917 | ||
dcdb1674 | 918 | return drm_get_pci_dev(pdev, ent, &driver); |
112b715e KH |
919 | } |
920 | ||
921 | static void | |
922 | i915_pci_remove(struct pci_dev *pdev) | |
923 | { | |
924 | struct drm_device *dev = pci_get_drvdata(pdev); | |
925 | ||
926 | drm_put_dev(dev); | |
927 | } | |
928 | ||
84b79f8d | 929 | static int i915_pm_suspend(struct device *dev) |
112b715e | 930 | { |
84b79f8d RW |
931 | struct pci_dev *pdev = to_pci_dev(dev); |
932 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
933 | int error; | |
112b715e | 934 | |
84b79f8d RW |
935 | if (!drm_dev || !drm_dev->dev_private) { |
936 | dev_err(dev, "DRM not initialized, aborting suspend.\n"); | |
937 | return -ENODEV; | |
938 | } | |
112b715e | 939 | |
5bcf719b DA |
940 | if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
941 | return 0; | |
942 | ||
84b79f8d RW |
943 | error = i915_drm_freeze(drm_dev); |
944 | if (error) | |
945 | return error; | |
112b715e | 946 | |
84b79f8d RW |
947 | pci_disable_device(pdev); |
948 | pci_set_power_state(pdev, PCI_D3hot); | |
cbda12d7 | 949 | |
84b79f8d | 950 | return 0; |
cbda12d7 ZW |
951 | } |
952 | ||
84b79f8d | 953 | static int i915_pm_resume(struct device *dev) |
cbda12d7 | 954 | { |
84b79f8d RW |
955 | struct pci_dev *pdev = to_pci_dev(dev); |
956 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
957 | ||
958 | return i915_resume(drm_dev); | |
cbda12d7 ZW |
959 | } |
960 | ||
84b79f8d | 961 | static int i915_pm_freeze(struct device *dev) |
cbda12d7 | 962 | { |
84b79f8d RW |
963 | struct pci_dev *pdev = to_pci_dev(dev); |
964 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
965 | ||
966 | if (!drm_dev || !drm_dev->dev_private) { | |
967 | dev_err(dev, "DRM not initialized, aborting suspend.\n"); | |
968 | return -ENODEV; | |
969 | } | |
970 | ||
971 | return i915_drm_freeze(drm_dev); | |
cbda12d7 ZW |
972 | } |
973 | ||
84b79f8d | 974 | static int i915_pm_thaw(struct device *dev) |
cbda12d7 | 975 | { |
84b79f8d RW |
976 | struct pci_dev *pdev = to_pci_dev(dev); |
977 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
978 | ||
979 | return i915_drm_thaw(drm_dev); | |
cbda12d7 ZW |
980 | } |
981 | ||
84b79f8d | 982 | static int i915_pm_poweroff(struct device *dev) |
cbda12d7 | 983 | { |
84b79f8d RW |
984 | struct pci_dev *pdev = to_pci_dev(dev); |
985 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
84b79f8d | 986 | |
61caf87c | 987 | return i915_drm_freeze(drm_dev); |
cbda12d7 ZW |
988 | } |
989 | ||
b4b78d12 | 990 | static const struct dev_pm_ops i915_pm_ops = { |
0206e353 AJ |
991 | .suspend = i915_pm_suspend, |
992 | .resume = i915_pm_resume, | |
993 | .freeze = i915_pm_freeze, | |
994 | .thaw = i915_pm_thaw, | |
995 | .poweroff = i915_pm_poweroff, | |
996 | .restore = i915_pm_resume, | |
cbda12d7 ZW |
997 | }; |
998 | ||
78b68556 | 999 | static const struct vm_operations_struct i915_gem_vm_ops = { |
de151cf6 | 1000 | .fault = i915_gem_fault, |
ab00b3e5 JB |
1001 | .open = drm_gem_vm_open, |
1002 | .close = drm_gem_vm_close, | |
de151cf6 JB |
1003 | }; |
1004 | ||
e08e96de AV |
1005 | static const struct file_operations i915_driver_fops = { |
1006 | .owner = THIS_MODULE, | |
1007 | .open = drm_open, | |
1008 | .release = drm_release, | |
1009 | .unlocked_ioctl = drm_ioctl, | |
1010 | .mmap = drm_gem_mmap, | |
1011 | .poll = drm_poll, | |
e08e96de AV |
1012 | .read = drm_read, |
1013 | #ifdef CONFIG_COMPAT | |
1014 | .compat_ioctl = i915_compat_ioctl, | |
1015 | #endif | |
1016 | .llseek = noop_llseek, | |
1017 | }; | |
1018 | ||
1da177e4 | 1019 | static struct drm_driver driver = { |
0c54781b MW |
1020 | /* Don't use MTRRs here; the Xserver or userspace app should |
1021 | * deal with them for Intel hardware. | |
792d2b9a | 1022 | */ |
673a394b | 1023 | .driver_features = |
28185647 | 1024 | DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | |
10ba5012 KH |
1025 | DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME | |
1026 | DRIVER_RENDER, | |
22eae947 | 1027 | .load = i915_driver_load, |
ba8bbcf6 | 1028 | .unload = i915_driver_unload, |
673a394b | 1029 | .open = i915_driver_open, |
22eae947 DA |
1030 | .lastclose = i915_driver_lastclose, |
1031 | .preclose = i915_driver_preclose, | |
673a394b | 1032 | .postclose = i915_driver_postclose, |
d8e29209 RW |
1033 | |
1034 | /* Used in place of i915_pm_ops for non-DRIVER_MODESET */ | |
1035 | .suspend = i915_suspend, | |
1036 | .resume = i915_resume, | |
1037 | ||
cda17380 | 1038 | .device_is_agp = i915_driver_device_is_agp, |
7c1c2871 DA |
1039 | .master_create = i915_master_create, |
1040 | .master_destroy = i915_master_destroy, | |
955b12de | 1041 | #if defined(CONFIG_DEBUG_FS) |
27c202ad BG |
1042 | .debugfs_init = i915_debugfs_init, |
1043 | .debugfs_cleanup = i915_debugfs_cleanup, | |
955b12de | 1044 | #endif |
673a394b EA |
1045 | .gem_init_object = i915_gem_init_object, |
1046 | .gem_free_object = i915_gem_free_object, | |
de151cf6 | 1047 | .gem_vm_ops = &i915_gem_vm_ops, |
1286ff73 DV |
1048 | |
1049 | .prime_handle_to_fd = drm_gem_prime_handle_to_fd, | |
1050 | .prime_fd_to_handle = drm_gem_prime_fd_to_handle, | |
1051 | .gem_prime_export = i915_gem_prime_export, | |
1052 | .gem_prime_import = i915_gem_prime_import, | |
1053 | ||
ff72145b DA |
1054 | .dumb_create = i915_gem_dumb_create, |
1055 | .dumb_map_offset = i915_gem_mmap_gtt, | |
43387b37 | 1056 | .dumb_destroy = drm_gem_dumb_destroy, |
1da177e4 | 1057 | .ioctls = i915_ioctls, |
e08e96de | 1058 | .fops = &i915_driver_fops, |
22eae947 DA |
1059 | .name = DRIVER_NAME, |
1060 | .desc = DRIVER_DESC, | |
1061 | .date = DRIVER_DATE, | |
1062 | .major = DRIVER_MAJOR, | |
1063 | .minor = DRIVER_MINOR, | |
1064 | .patchlevel = DRIVER_PATCHLEVEL, | |
1da177e4 LT |
1065 | }; |
1066 | ||
8410ea3b DA |
1067 | static struct pci_driver i915_pci_driver = { |
1068 | .name = DRIVER_NAME, | |
1069 | .id_table = pciidlist, | |
1070 | .probe = i915_pci_probe, | |
1071 | .remove = i915_pci_remove, | |
1072 | .driver.pm = &i915_pm_ops, | |
1073 | }; | |
1074 | ||
1da177e4 LT |
1075 | static int __init i915_init(void) |
1076 | { | |
1077 | driver.num_ioctls = i915_max_ioctl; | |
79e53945 JB |
1078 | |
1079 | /* | |
1080 | * If CONFIG_DRM_I915_KMS is set, default to KMS unless | |
1081 | * explicitly disabled with the module pararmeter. | |
1082 | * | |
1083 | * Otherwise, just follow the parameter (defaulting to off). | |
1084 | * | |
1085 | * Allow optional vga_text_mode_force boot option to override | |
1086 | * the default behavior. | |
1087 | */ | |
1088 | #if defined(CONFIG_DRM_I915_KMS) | |
1089 | if (i915_modeset != 0) | |
1090 | driver.driver_features |= DRIVER_MODESET; | |
1091 | #endif | |
1092 | if (i915_modeset == 1) | |
1093 | driver.driver_features |= DRIVER_MODESET; | |
1094 | ||
1095 | #ifdef CONFIG_VGA_CONSOLE | |
1096 | if (vgacon_text_force() && i915_modeset == -1) | |
1097 | driver.driver_features &= ~DRIVER_MODESET; | |
1098 | #endif | |
1099 | ||
3885c6bb CW |
1100 | if (!(driver.driver_features & DRIVER_MODESET)) |
1101 | driver.get_vblank_timestamp = NULL; | |
1102 | ||
8410ea3b | 1103 | return drm_pci_init(&driver, &i915_pci_driver); |
1da177e4 LT |
1104 | } |
1105 | ||
1106 | static void __exit i915_exit(void) | |
1107 | { | |
8410ea3b | 1108 | drm_pci_exit(&driver, &i915_pci_driver); |
1da177e4 LT |
1109 | } |
1110 | ||
1111 | module_init(i915_init); | |
1112 | module_exit(i915_exit); | |
1113 | ||
b5e89ed5 DA |
1114 | MODULE_AUTHOR(DRIVER_AUTHOR); |
1115 | MODULE_DESCRIPTION(DRIVER_DESC); | |
1da177e4 | 1116 | MODULE_LICENSE("GPL and additional rights"); |