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1da177e4 LT |
1 | /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- |
2 | */ | |
0d6aa60b | 3 | /* |
bc54fd1a | 4 | * |
1da177e4 LT |
5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
6 | * All Rights Reserved. | |
bc54fd1a DA |
7 | * |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the | |
10 | * "Software"), to deal in the Software without restriction, including | |
11 | * without limitation the rights to use, copy, modify, merge, publish, | |
12 | * distribute, sub license, and/or sell copies of the Software, and to | |
13 | * permit persons to whom the Software is furnished to do so, subject to | |
14 | * the following conditions: | |
15 | * | |
16 | * The above copyright notice and this permission notice (including the | |
17 | * next paragraph) shall be included in all copies or substantial portions | |
18 | * of the Software. | |
19 | * | |
20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
27 | * | |
0d6aa60b | 28 | */ |
1da177e4 LT |
29 | |
30 | #ifndef _I915_DRV_H_ | |
31 | #define _I915_DRV_H_ | |
32 | ||
585fb111 | 33 | #include "i915_reg.h" |
79e53945 | 34 | #include "intel_bios.h" |
0839ccb8 | 35 | #include <linux/io-mapping.h> |
585fb111 | 36 | |
1da177e4 LT |
37 | /* General customization: |
38 | */ | |
39 | ||
40 | #define DRIVER_AUTHOR "Tungsten Graphics, Inc." | |
41 | ||
42 | #define DRIVER_NAME "i915" | |
43 | #define DRIVER_DESC "Intel Graphics" | |
673a394b | 44 | #define DRIVER_DATE "20080730" |
1da177e4 | 45 | |
317c35d1 JB |
46 | enum pipe { |
47 | PIPE_A = 0, | |
48 | PIPE_B, | |
49 | }; | |
50 | ||
52440211 KP |
51 | #define I915_NUM_PIPE 2 |
52 | ||
1da177e4 LT |
53 | /* Interface history: |
54 | * | |
55 | * 1.1: Original. | |
0d6aa60b DA |
56 | * 1.2: Add Power Management |
57 | * 1.3: Add vblank support | |
de227f5f | 58 | * 1.4: Fix cmdbuffer path, add heap destroy |
702880f2 | 59 | * 1.5: Add vblank pipe configuration |
2228ed67 MCA |
60 | * 1.6: - New ioctl for scheduling buffer swaps on vertical blank |
61 | * - Support vertical blank on secondary display pipe | |
1da177e4 LT |
62 | */ |
63 | #define DRIVER_MAJOR 1 | |
2228ed67 | 64 | #define DRIVER_MINOR 6 |
1da177e4 LT |
65 | #define DRIVER_PATCHLEVEL 0 |
66 | ||
673a394b EA |
67 | #define WATCH_COHERENCY 0 |
68 | #define WATCH_BUF 0 | |
69 | #define WATCH_EXEC 0 | |
70 | #define WATCH_LRU 0 | |
71 | #define WATCH_RELOC 0 | |
72 | #define WATCH_INACTIVE 0 | |
73 | #define WATCH_PWRITE 0 | |
74 | ||
71acb5eb DA |
75 | #define I915_GEM_PHYS_CURSOR_0 1 |
76 | #define I915_GEM_PHYS_CURSOR_1 2 | |
77 | #define I915_GEM_PHYS_OVERLAY_REGS 3 | |
78 | #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS) | |
79 | ||
80 | struct drm_i915_gem_phys_object { | |
81 | int id; | |
82 | struct page **page_list; | |
83 | drm_dma_handle_t *handle; | |
84 | struct drm_gem_object *cur_obj; | |
85 | }; | |
86 | ||
1da177e4 | 87 | typedef struct _drm_i915_ring_buffer { |
1da177e4 LT |
88 | unsigned long Size; |
89 | u8 *virtual_start; | |
90 | int head; | |
91 | int tail; | |
92 | int space; | |
93 | drm_local_map_t map; | |
673a394b | 94 | struct drm_gem_object *ring_obj; |
1da177e4 LT |
95 | } drm_i915_ring_buffer_t; |
96 | ||
97 | struct mem_block { | |
98 | struct mem_block *next; | |
99 | struct mem_block *prev; | |
100 | int start; | |
101 | int size; | |
6c340eac | 102 | struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */ |
1da177e4 LT |
103 | }; |
104 | ||
0a3e67a4 JB |
105 | struct opregion_header; |
106 | struct opregion_acpi; | |
107 | struct opregion_swsci; | |
108 | struct opregion_asle; | |
109 | ||
8ee1c3db MG |
110 | struct intel_opregion { |
111 | struct opregion_header *header; | |
112 | struct opregion_acpi *acpi; | |
113 | struct opregion_swsci *swsci; | |
114 | struct opregion_asle *asle; | |
115 | int enabled; | |
116 | }; | |
117 | ||
7c1c2871 DA |
118 | struct drm_i915_master_private { |
119 | drm_local_map_t *sarea; | |
120 | struct _drm_i915_sarea *sarea_priv; | |
121 | }; | |
de151cf6 JB |
122 | #define I915_FENCE_REG_NONE -1 |
123 | ||
124 | struct drm_i915_fence_reg { | |
125 | struct drm_gem_object *obj; | |
126 | }; | |
7c1c2871 | 127 | |
9b9d172d | 128 | struct sdvo_device_mapping { |
129 | u8 dvo_port; | |
130 | u8 slave_addr; | |
131 | u8 dvo_wiring; | |
132 | u8 initialized; | |
133 | }; | |
134 | ||
63eeaf38 JB |
135 | struct drm_i915_error_state { |
136 | u32 eir; | |
137 | u32 pgtbl_er; | |
138 | u32 pipeastat; | |
139 | u32 pipebstat; | |
140 | u32 ipeir; | |
141 | u32 ipehr; | |
142 | u32 instdone; | |
143 | u32 acthd; | |
144 | u32 instpm; | |
145 | u32 instps; | |
146 | u32 instdone1; | |
147 | u32 seqno; | |
148 | struct timeval time; | |
149 | }; | |
150 | ||
1da177e4 | 151 | typedef struct drm_i915_private { |
673a394b EA |
152 | struct drm_device *dev; |
153 | ||
ac5c4e76 DA |
154 | int has_gem; |
155 | ||
3043c60c | 156 | void __iomem *regs; |
1da177e4 | 157 | |
ec2a4c3f | 158 | struct pci_dev *bridge_dev; |
1da177e4 LT |
159 | drm_i915_ring_buffer_t ring; |
160 | ||
9c8da5eb | 161 | drm_dma_handle_t *status_page_dmah; |
1da177e4 | 162 | void *hw_status_page; |
1da177e4 | 163 | dma_addr_t dma_status_page; |
0a3e67a4 | 164 | uint32_t counter; |
dc7a9319 WZ |
165 | unsigned int status_gfx_addr; |
166 | drm_local_map_t hws_map; | |
673a394b | 167 | struct drm_gem_object *hws_obj; |
1da177e4 | 168 | |
d7658989 JB |
169 | struct resource mch_res; |
170 | ||
a6b54f3f | 171 | unsigned int cpp; |
1da177e4 LT |
172 | int back_offset; |
173 | int front_offset; | |
174 | int current_page; | |
175 | int page_flipping; | |
1da177e4 LT |
176 | |
177 | wait_queue_head_t irq_queue; | |
178 | atomic_t irq_received; | |
ed4cb414 EA |
179 | /** Protects user_irq_refcount and irq_mask_reg */ |
180 | spinlock_t user_irq_lock; | |
181 | /** Refcount for i915_user_irq_get() versus i915_user_irq_put(). */ | |
182 | int user_irq_refcount; | |
183 | /** Cached value of IMR to avoid reads in updating the bitfield */ | |
184 | u32 irq_mask_reg; | |
7c463586 | 185 | u32 pipestat[2]; |
036a4a7d ZW |
186 | /** splitted irq regs for graphics and display engine on IGDNG, |
187 | irq_mask_reg is still used for display irq. */ | |
188 | u32 gt_irq_mask_reg; | |
189 | u32 gt_irq_enable_reg; | |
190 | u32 de_irq_enable_reg; | |
1da177e4 | 191 | |
5ca58282 JB |
192 | u32 hotplug_supported_mask; |
193 | struct work_struct hotplug_work; | |
194 | ||
1da177e4 LT |
195 | int tex_lru_log_granularity; |
196 | int allow_batchbuffer; | |
197 | struct mem_block *agp_heap; | |
0d6aa60b | 198 | unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds; |
702880f2 | 199 | int vblank_pipe; |
a6b54f3f | 200 | |
79e53945 JB |
201 | bool cursor_needs_physical; |
202 | ||
203 | struct drm_mm vram; | |
204 | ||
205 | int irq_enabled; | |
206 | ||
8ee1c3db MG |
207 | struct intel_opregion opregion; |
208 | ||
79e53945 JB |
209 | /* LVDS info */ |
210 | int backlight_duty_cycle; /* restore backlight to this value */ | |
211 | bool panel_wants_dither; | |
212 | struct drm_display_mode *panel_fixed_mode; | |
88631706 ML |
213 | struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ |
214 | struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ | |
79e53945 JB |
215 | |
216 | /* Feature bits from the VBIOS */ | |
95281e35 HE |
217 | unsigned int int_tv_support:1; |
218 | unsigned int lvds_dither:1; | |
219 | unsigned int lvds_vbt:1; | |
220 | unsigned int int_crt_support:1; | |
43565a06 | 221 | unsigned int lvds_use_ssc:1; |
32f9d658 | 222 | unsigned int edp_support:1; |
43565a06 | 223 | int lvds_ssc_freq; |
79e53945 | 224 | |
c1c7af60 JB |
225 | struct notifier_block lid_notifier; |
226 | ||
db545019 | 227 | int crt_ddc_bus; /* -1 = unknown, else GPIO to use for CRT DDC */ |
de151cf6 JB |
228 | struct drm_i915_fence_reg fence_regs[16]; /* assume 965 */ |
229 | int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */ | |
230 | int num_fence_regs; /* 8 on pre-965, 16 otherwise */ | |
231 | ||
7662c8bd SL |
232 | unsigned int fsb_freq, mem_freq; |
233 | ||
63eeaf38 JB |
234 | spinlock_t error_lock; |
235 | struct drm_i915_error_state *first_error; | |
8a905236 | 236 | struct work_struct error_work; |
9c9fe1f8 | 237 | struct workqueue_struct *wq; |
63eeaf38 | 238 | |
ba8bbcf6 JB |
239 | /* Register state */ |
240 | u8 saveLBB; | |
241 | u32 saveDSPACNTR; | |
242 | u32 saveDSPBCNTR; | |
e948e994 | 243 | u32 saveDSPARB; |
881ee988 | 244 | u32 saveRENDERSTANDBY; |
461cba2d | 245 | u32 saveHWS; |
ba8bbcf6 JB |
246 | u32 savePIPEACONF; |
247 | u32 savePIPEBCONF; | |
248 | u32 savePIPEASRC; | |
249 | u32 savePIPEBSRC; | |
250 | u32 saveFPA0; | |
251 | u32 saveFPA1; | |
252 | u32 saveDPLL_A; | |
253 | u32 saveDPLL_A_MD; | |
254 | u32 saveHTOTAL_A; | |
255 | u32 saveHBLANK_A; | |
256 | u32 saveHSYNC_A; | |
257 | u32 saveVTOTAL_A; | |
258 | u32 saveVBLANK_A; | |
259 | u32 saveVSYNC_A; | |
260 | u32 saveBCLRPAT_A; | |
0da3ea12 | 261 | u32 savePIPEASTAT; |
ba8bbcf6 JB |
262 | u32 saveDSPASTRIDE; |
263 | u32 saveDSPASIZE; | |
264 | u32 saveDSPAPOS; | |
585fb111 | 265 | u32 saveDSPAADDR; |
ba8bbcf6 JB |
266 | u32 saveDSPASURF; |
267 | u32 saveDSPATILEOFF; | |
268 | u32 savePFIT_PGM_RATIOS; | |
269 | u32 saveBLC_PWM_CTL; | |
270 | u32 saveBLC_PWM_CTL2; | |
271 | u32 saveFPB0; | |
272 | u32 saveFPB1; | |
273 | u32 saveDPLL_B; | |
274 | u32 saveDPLL_B_MD; | |
275 | u32 saveHTOTAL_B; | |
276 | u32 saveHBLANK_B; | |
277 | u32 saveHSYNC_B; | |
278 | u32 saveVTOTAL_B; | |
279 | u32 saveVBLANK_B; | |
280 | u32 saveVSYNC_B; | |
281 | u32 saveBCLRPAT_B; | |
0da3ea12 | 282 | u32 savePIPEBSTAT; |
ba8bbcf6 JB |
283 | u32 saveDSPBSTRIDE; |
284 | u32 saveDSPBSIZE; | |
285 | u32 saveDSPBPOS; | |
585fb111 | 286 | u32 saveDSPBADDR; |
ba8bbcf6 JB |
287 | u32 saveDSPBSURF; |
288 | u32 saveDSPBTILEOFF; | |
585fb111 JB |
289 | u32 saveVGA0; |
290 | u32 saveVGA1; | |
291 | u32 saveVGA_PD; | |
ba8bbcf6 JB |
292 | u32 saveVGACNTRL; |
293 | u32 saveADPA; | |
294 | u32 saveLVDS; | |
585fb111 JB |
295 | u32 savePP_ON_DELAYS; |
296 | u32 savePP_OFF_DELAYS; | |
ba8bbcf6 JB |
297 | u32 saveDVOA; |
298 | u32 saveDVOB; | |
299 | u32 saveDVOC; | |
300 | u32 savePP_ON; | |
301 | u32 savePP_OFF; | |
302 | u32 savePP_CONTROL; | |
585fb111 | 303 | u32 savePP_DIVISOR; |
ba8bbcf6 JB |
304 | u32 savePFIT_CONTROL; |
305 | u32 save_palette_a[256]; | |
306 | u32 save_palette_b[256]; | |
307 | u32 saveFBC_CFB_BASE; | |
308 | u32 saveFBC_LL_BASE; | |
309 | u32 saveFBC_CONTROL; | |
310 | u32 saveFBC_CONTROL2; | |
0da3ea12 JB |
311 | u32 saveIER; |
312 | u32 saveIIR; | |
313 | u32 saveIMR; | |
1f84e550 | 314 | u32 saveCACHE_MODE_0; |
e948e994 | 315 | u32 saveD_STATE; |
652c393a | 316 | u32 saveDSPCLK_GATE_D; |
1f84e550 | 317 | u32 saveMI_ARB_STATE; |
ba8bbcf6 JB |
318 | u32 saveSWF0[16]; |
319 | u32 saveSWF1[16]; | |
320 | u32 saveSWF2[3]; | |
321 | u8 saveMSR; | |
322 | u8 saveSR[8]; | |
123f794f | 323 | u8 saveGR[25]; |
ba8bbcf6 | 324 | u8 saveAR_INDEX; |
a59e122a | 325 | u8 saveAR[21]; |
ba8bbcf6 | 326 | u8 saveDACMASK; |
a59e122a | 327 | u8 saveCR[37]; |
79f11c19 | 328 | uint64_t saveFENCE[16]; |
1fd1c624 EA |
329 | u32 saveCURACNTR; |
330 | u32 saveCURAPOS; | |
331 | u32 saveCURABASE; | |
332 | u32 saveCURBCNTR; | |
333 | u32 saveCURBPOS; | |
334 | u32 saveCURBBASE; | |
335 | u32 saveCURSIZE; | |
a4fc5ed6 KP |
336 | u32 saveDP_B; |
337 | u32 saveDP_C; | |
338 | u32 saveDP_D; | |
339 | u32 savePIPEA_GMCH_DATA_M; | |
340 | u32 savePIPEB_GMCH_DATA_M; | |
341 | u32 savePIPEA_GMCH_DATA_N; | |
342 | u32 savePIPEB_GMCH_DATA_N; | |
343 | u32 savePIPEA_DP_LINK_M; | |
344 | u32 savePIPEB_DP_LINK_M; | |
345 | u32 savePIPEA_DP_LINK_N; | |
346 | u32 savePIPEB_DP_LINK_N; | |
673a394b EA |
347 | |
348 | struct { | |
349 | struct drm_mm gtt_space; | |
350 | ||
0839ccb8 | 351 | struct io_mapping *gtt_mapping; |
ab657db1 | 352 | int gtt_mtrr; |
0839ccb8 | 353 | |
673a394b EA |
354 | /** |
355 | * List of objects currently involved in rendering from the | |
356 | * ringbuffer. | |
357 | * | |
ce44b0ea EA |
358 | * Includes buffers having the contents of their GPU caches |
359 | * flushed, not necessarily primitives. last_rendering_seqno | |
360 | * represents when the rendering involved will be completed. | |
361 | * | |
673a394b EA |
362 | * A reference is held on the buffer while on this list. |
363 | */ | |
5e118f41 | 364 | spinlock_t active_list_lock; |
673a394b EA |
365 | struct list_head active_list; |
366 | ||
367 | /** | |
368 | * List of objects which are not in the ringbuffer but which | |
369 | * still have a write_domain which needs to be flushed before | |
370 | * unbinding. | |
371 | * | |
ce44b0ea EA |
372 | * last_rendering_seqno is 0 while an object is in this list. |
373 | * | |
673a394b EA |
374 | * A reference is held on the buffer while on this list. |
375 | */ | |
376 | struct list_head flushing_list; | |
377 | ||
378 | /** | |
379 | * LRU list of objects which are not in the ringbuffer and | |
380 | * are ready to unbind, but are still in the GTT. | |
381 | * | |
ce44b0ea EA |
382 | * last_rendering_seqno is 0 while an object is in this list. |
383 | * | |
673a394b EA |
384 | * A reference is not held on the buffer while on this list, |
385 | * as merely being GTT-bound shouldn't prevent its being | |
386 | * freed, and we'll pull it off the list in the free path. | |
387 | */ | |
388 | struct list_head inactive_list; | |
389 | ||
a09ba7fa EA |
390 | /** LRU list of objects with fence regs on them. */ |
391 | struct list_head fence_list; | |
392 | ||
673a394b EA |
393 | /** |
394 | * List of breadcrumbs associated with GPU requests currently | |
395 | * outstanding. | |
396 | */ | |
397 | struct list_head request_list; | |
398 | ||
399 | /** | |
400 | * We leave the user IRQ off as much as possible, | |
401 | * but this means that requests will finish and never | |
402 | * be retired once the system goes idle. Set a timer to | |
403 | * fire periodically while the ring is running. When it | |
404 | * fires, go retire requests. | |
405 | */ | |
406 | struct delayed_work retire_work; | |
407 | ||
408 | uint32_t next_gem_seqno; | |
409 | ||
410 | /** | |
411 | * Waiting sequence number, if any | |
412 | */ | |
413 | uint32_t waiting_gem_seqno; | |
414 | ||
415 | /** | |
416 | * Last seq seen at irq time | |
417 | */ | |
418 | uint32_t irq_gem_seqno; | |
419 | ||
420 | /** | |
421 | * Flag if the X Server, and thus DRM, is not currently in | |
422 | * control of the device. | |
423 | * | |
424 | * This is set between LeaveVT and EnterVT. It needs to be | |
425 | * replaced with a semaphore. It also needs to be | |
426 | * transitioned away from for kernel modesetting. | |
427 | */ | |
428 | int suspended; | |
429 | ||
430 | /** | |
431 | * Flag if the hardware appears to be wedged. | |
432 | * | |
433 | * This is set when attempts to idle the device timeout. | |
434 | * It prevents command submission from occuring and makes | |
435 | * every pending request fail | |
436 | */ | |
437 | int wedged; | |
438 | ||
439 | /** Bit 6 swizzling required for X tiling */ | |
440 | uint32_t bit_6_swizzle_x; | |
441 | /** Bit 6 swizzling required for Y tiling */ | |
442 | uint32_t bit_6_swizzle_y; | |
71acb5eb DA |
443 | |
444 | /* storage for physical objects */ | |
445 | struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT]; | |
673a394b | 446 | } mm; |
9b9d172d | 447 | struct sdvo_device_mapping sdvo_mappings[2]; |
652c393a JB |
448 | |
449 | /* Reclocking support */ | |
450 | bool render_reclock_avail; | |
451 | bool lvds_downclock_avail; | |
452 | struct work_struct idle_work; | |
453 | struct timer_list idle_timer; | |
454 | bool busy; | |
455 | u16 orig_clock; | |
1da177e4 LT |
456 | } drm_i915_private_t; |
457 | ||
673a394b EA |
458 | /** driver private structure attached to each drm_gem_object */ |
459 | struct drm_i915_gem_object { | |
460 | struct drm_gem_object *obj; | |
461 | ||
462 | /** Current space allocated to this object in the GTT, if any. */ | |
463 | struct drm_mm_node *gtt_space; | |
464 | ||
465 | /** This object's place on the active/flushing/inactive lists */ | |
466 | struct list_head list; | |
467 | ||
a09ba7fa EA |
468 | /** This object's place on the fenced object LRU */ |
469 | struct list_head fence_list; | |
470 | ||
673a394b EA |
471 | /** |
472 | * This is set if the object is on the active or flushing lists | |
473 | * (has pending rendering), and is not set if it's on inactive (ready | |
474 | * to be unbound). | |
475 | */ | |
476 | int active; | |
477 | ||
478 | /** | |
479 | * This is set if the object has been written to since last bound | |
480 | * to the GTT | |
481 | */ | |
482 | int dirty; | |
483 | ||
484 | /** AGP memory structure for our GTT binding. */ | |
485 | DRM_AGP_MEM *agp_mem; | |
486 | ||
856fa198 EA |
487 | struct page **pages; |
488 | int pages_refcount; | |
673a394b EA |
489 | |
490 | /** | |
491 | * Current offset of the object in GTT space. | |
492 | * | |
493 | * This is the same as gtt_space->start | |
494 | */ | |
495 | uint32_t gtt_offset; | |
de151cf6 JB |
496 | /** |
497 | * Required alignment for the object | |
498 | */ | |
499 | uint32_t gtt_alignment; | |
500 | /** | |
501 | * Fake offset for use by mmap(2) | |
502 | */ | |
503 | uint64_t mmap_offset; | |
504 | ||
505 | /** | |
506 | * Fence register bits (if any) for this object. Will be set | |
507 | * as needed when mapped into the GTT. | |
508 | * Protected by dev->struct_mutex. | |
509 | */ | |
510 | int fence_reg; | |
673a394b | 511 | |
673a394b EA |
512 | /** How many users have pinned this object in GTT space */ |
513 | int pin_count; | |
514 | ||
515 | /** Breadcrumb of last rendering to the buffer. */ | |
516 | uint32_t last_rendering_seqno; | |
517 | ||
518 | /** Current tiling mode for the object. */ | |
519 | uint32_t tiling_mode; | |
de151cf6 | 520 | uint32_t stride; |
673a394b | 521 | |
280b713b EA |
522 | /** Record of address bit 17 of each page at last unbind. */ |
523 | long *bit_17; | |
524 | ||
ba1eb1d8 KP |
525 | /** AGP mapping type (AGP_USER_MEMORY or AGP_USER_CACHED_MEMORY */ |
526 | uint32_t agp_type; | |
527 | ||
673a394b | 528 | /** |
e47c68e9 EA |
529 | * If present, while GEM_DOMAIN_CPU is in the read domain this array |
530 | * flags which individual pages are valid. | |
673a394b EA |
531 | */ |
532 | uint8_t *page_cpu_valid; | |
79e53945 JB |
533 | |
534 | /** User space pin count and filp owning the pin */ | |
535 | uint32_t user_pin_count; | |
536 | struct drm_file *pin_filp; | |
71acb5eb DA |
537 | |
538 | /** for phy allocated objects */ | |
539 | struct drm_i915_gem_phys_object *phys_obj; | |
b70d11da KH |
540 | |
541 | /** | |
542 | * Used for checking the object doesn't appear more than once | |
543 | * in an execbuffer object list. | |
544 | */ | |
545 | int in_execbuffer; | |
673a394b EA |
546 | }; |
547 | ||
548 | /** | |
549 | * Request queue structure. | |
550 | * | |
551 | * The request queue allows us to note sequence numbers that have been emitted | |
552 | * and may be associated with active buffers to be retired. | |
553 | * | |
554 | * By keeping this list, we can avoid having to do questionable | |
555 | * sequence-number comparisons on buffer last_rendering_seqnos, and associate | |
556 | * an emission time with seqnos for tracking how far ahead of the GPU we are. | |
557 | */ | |
558 | struct drm_i915_gem_request { | |
559 | /** GEM sequence number associated with this request. */ | |
560 | uint32_t seqno; | |
561 | ||
562 | /** Time at which this request was emitted, in jiffies. */ | |
563 | unsigned long emitted_jiffies; | |
564 | ||
b962442e | 565 | /** global list entry for this request */ |
673a394b | 566 | struct list_head list; |
b962442e EA |
567 | |
568 | /** file_priv list entry for this request */ | |
569 | struct list_head client_list; | |
673a394b EA |
570 | }; |
571 | ||
572 | struct drm_i915_file_private { | |
573 | struct { | |
b962442e | 574 | struct list_head request_list; |
673a394b EA |
575 | } mm; |
576 | }; | |
577 | ||
79e53945 JB |
578 | enum intel_chip_family { |
579 | CHIP_I8XX = 0x01, | |
580 | CHIP_I9XX = 0x02, | |
581 | CHIP_I915 = 0x04, | |
582 | CHIP_I965 = 0x08, | |
583 | }; | |
584 | ||
c153f45f | 585 | extern struct drm_ioctl_desc i915_ioctls[]; |
b3a83639 | 586 | extern int i915_max_ioctl; |
79e53945 | 587 | extern unsigned int i915_fbpercrtc; |
652c393a | 588 | extern unsigned int i915_powersave; |
b3a83639 | 589 | |
7c1c2871 DA |
590 | extern int i915_master_create(struct drm_device *dev, struct drm_master *master); |
591 | extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master); | |
592 | ||
1da177e4 | 593 | /* i915_dma.c */ |
84b1fd10 | 594 | extern void i915_kernel_lost_context(struct drm_device * dev); |
22eae947 | 595 | extern int i915_driver_load(struct drm_device *, unsigned long flags); |
ba8bbcf6 | 596 | extern int i915_driver_unload(struct drm_device *); |
673a394b | 597 | extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv); |
84b1fd10 | 598 | extern void i915_driver_lastclose(struct drm_device * dev); |
6c340eac EA |
599 | extern void i915_driver_preclose(struct drm_device *dev, |
600 | struct drm_file *file_priv); | |
673a394b EA |
601 | extern void i915_driver_postclose(struct drm_device *dev, |
602 | struct drm_file *file_priv); | |
84b1fd10 | 603 | extern int i915_driver_device_is_agp(struct drm_device * dev); |
0d6aa60b DA |
604 | extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, |
605 | unsigned long arg); | |
673a394b | 606 | extern int i915_emit_box(struct drm_device *dev, |
201361a5 | 607 | struct drm_clip_rect *boxes, |
673a394b | 608 | int i, int DR1, int DR4); |
af6061af | 609 | |
1da177e4 | 610 | /* i915_irq.c */ |
c153f45f EA |
611 | extern int i915_irq_emit(struct drm_device *dev, void *data, |
612 | struct drm_file *file_priv); | |
613 | extern int i915_irq_wait(struct drm_device *dev, void *data, | |
614 | struct drm_file *file_priv); | |
673a394b EA |
615 | void i915_user_irq_get(struct drm_device *dev); |
616 | void i915_user_irq_put(struct drm_device *dev); | |
79e53945 | 617 | extern void i915_enable_interrupt (struct drm_device *dev); |
1da177e4 LT |
618 | |
619 | extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS); | |
84b1fd10 | 620 | extern void i915_driver_irq_preinstall(struct drm_device * dev); |
0a3e67a4 | 621 | extern int i915_driver_irq_postinstall(struct drm_device *dev); |
84b1fd10 | 622 | extern void i915_driver_irq_uninstall(struct drm_device * dev); |
c153f45f EA |
623 | extern int i915_vblank_pipe_set(struct drm_device *dev, void *data, |
624 | struct drm_file *file_priv); | |
625 | extern int i915_vblank_pipe_get(struct drm_device *dev, void *data, | |
626 | struct drm_file *file_priv); | |
0a3e67a4 JB |
627 | extern int i915_enable_vblank(struct drm_device *dev, int crtc); |
628 | extern void i915_disable_vblank(struct drm_device *dev, int crtc); | |
629 | extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc); | |
9880b7a5 | 630 | extern u32 gm45_get_vblank_counter(struct drm_device *dev, int crtc); |
c153f45f EA |
631 | extern int i915_vblank_swap(struct drm_device *dev, void *data, |
632 | struct drm_file *file_priv); | |
8ee1c3db | 633 | extern void i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask); |
1da177e4 | 634 | |
7c463586 KP |
635 | void |
636 | i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); | |
637 | ||
638 | void | |
639 | i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); | |
640 | ||
641 | ||
1da177e4 | 642 | /* i915_mem.c */ |
c153f45f EA |
643 | extern int i915_mem_alloc(struct drm_device *dev, void *data, |
644 | struct drm_file *file_priv); | |
645 | extern int i915_mem_free(struct drm_device *dev, void *data, | |
646 | struct drm_file *file_priv); | |
647 | extern int i915_mem_init_heap(struct drm_device *dev, void *data, | |
648 | struct drm_file *file_priv); | |
649 | extern int i915_mem_destroy_heap(struct drm_device *dev, void *data, | |
650 | struct drm_file *file_priv); | |
1da177e4 | 651 | extern void i915_mem_takedown(struct mem_block **heap); |
84b1fd10 | 652 | extern void i915_mem_release(struct drm_device * dev, |
6c340eac | 653 | struct drm_file *file_priv, struct mem_block *heap); |
673a394b EA |
654 | /* i915_gem.c */ |
655 | int i915_gem_init_ioctl(struct drm_device *dev, void *data, | |
656 | struct drm_file *file_priv); | |
657 | int i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
658 | struct drm_file *file_priv); | |
659 | int i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
660 | struct drm_file *file_priv); | |
661 | int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
662 | struct drm_file *file_priv); | |
663 | int i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
664 | struct drm_file *file_priv); | |
de151cf6 JB |
665 | int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, |
666 | struct drm_file *file_priv); | |
673a394b EA |
667 | int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, |
668 | struct drm_file *file_priv); | |
669 | int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
670 | struct drm_file *file_priv); | |
671 | int i915_gem_execbuffer(struct drm_device *dev, void *data, | |
672 | struct drm_file *file_priv); | |
673 | int i915_gem_pin_ioctl(struct drm_device *dev, void *data, | |
674 | struct drm_file *file_priv); | |
675 | int i915_gem_unpin_ioctl(struct drm_device *dev, void *data, | |
676 | struct drm_file *file_priv); | |
677 | int i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
678 | struct drm_file *file_priv); | |
679 | int i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
680 | struct drm_file *file_priv); | |
681 | int i915_gem_entervt_ioctl(struct drm_device *dev, void *data, | |
682 | struct drm_file *file_priv); | |
683 | int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, | |
684 | struct drm_file *file_priv); | |
685 | int i915_gem_set_tiling(struct drm_device *dev, void *data, | |
686 | struct drm_file *file_priv); | |
687 | int i915_gem_get_tiling(struct drm_device *dev, void *data, | |
688 | struct drm_file *file_priv); | |
5a125c3c EA |
689 | int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, |
690 | struct drm_file *file_priv); | |
673a394b | 691 | void i915_gem_load(struct drm_device *dev); |
673a394b EA |
692 | int i915_gem_init_object(struct drm_gem_object *obj); |
693 | void i915_gem_free_object(struct drm_gem_object *obj); | |
694 | int i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment); | |
695 | void i915_gem_object_unpin(struct drm_gem_object *obj); | |
0f973f27 | 696 | int i915_gem_object_unbind(struct drm_gem_object *obj); |
d05ca301 | 697 | void i915_gem_release_mmap(struct drm_gem_object *obj); |
673a394b EA |
698 | void i915_gem_lastclose(struct drm_device *dev); |
699 | uint32_t i915_get_gem_seqno(struct drm_device *dev); | |
8c4b8c3f | 700 | int i915_gem_object_get_fence_reg(struct drm_gem_object *obj); |
52dc7d32 | 701 | int i915_gem_object_put_fence_reg(struct drm_gem_object *obj); |
673a394b EA |
702 | void i915_gem_retire_requests(struct drm_device *dev); |
703 | void i915_gem_retire_work_handler(struct work_struct *work); | |
704 | void i915_gem_clflush_object(struct drm_gem_object *obj); | |
79e53945 JB |
705 | int i915_gem_object_set_domain(struct drm_gem_object *obj, |
706 | uint32_t read_domains, | |
707 | uint32_t write_domain); | |
708 | int i915_gem_init_ringbuffer(struct drm_device *dev); | |
709 | void i915_gem_cleanup_ringbuffer(struct drm_device *dev); | |
710 | int i915_gem_do_init(struct drm_device *dev, unsigned long start, | |
711 | unsigned long end); | |
5669fcac | 712 | int i915_gem_idle(struct drm_device *dev); |
de151cf6 | 713 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf); |
79e53945 JB |
714 | int i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, |
715 | int write); | |
71acb5eb DA |
716 | int i915_gem_attach_phys_object(struct drm_device *dev, |
717 | struct drm_gem_object *obj, int id); | |
718 | void i915_gem_detach_phys_object(struct drm_device *dev, | |
719 | struct drm_gem_object *obj); | |
720 | void i915_gem_free_all_phys_object(struct drm_device *dev); | |
6911a9b8 BG |
721 | int i915_gem_object_get_pages(struct drm_gem_object *obj); |
722 | void i915_gem_object_put_pages(struct drm_gem_object *obj); | |
1fd1c624 | 723 | void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv); |
673a394b EA |
724 | |
725 | /* i915_gem_tiling.c */ | |
726 | void i915_gem_detect_bit_6_swizzle(struct drm_device *dev); | |
280b713b EA |
727 | void i915_gem_object_do_bit_17_swizzle(struct drm_gem_object *obj); |
728 | void i915_gem_object_save_bit_17_swizzle(struct drm_gem_object *obj); | |
673a394b EA |
729 | |
730 | /* i915_gem_debug.c */ | |
731 | void i915_gem_dump_object(struct drm_gem_object *obj, int len, | |
732 | const char *where, uint32_t mark); | |
733 | #if WATCH_INACTIVE | |
734 | void i915_verify_inactive(struct drm_device *dev, char *file, int line); | |
735 | #else | |
736 | #define i915_verify_inactive(dev, file, line) | |
737 | #endif | |
738 | void i915_gem_object_check_coherency(struct drm_gem_object *obj, int handle); | |
739 | void i915_gem_dump_object(struct drm_gem_object *obj, int len, | |
740 | const char *where, uint32_t mark); | |
741 | void i915_dump_lru(struct drm_device *dev, const char *where); | |
1da177e4 | 742 | |
2017263e | 743 | /* i915_debugfs.c */ |
27c202ad BG |
744 | int i915_debugfs_init(struct drm_minor *minor); |
745 | void i915_debugfs_cleanup(struct drm_minor *minor); | |
2017263e | 746 | |
317c35d1 JB |
747 | /* i915_suspend.c */ |
748 | extern int i915_save_state(struct drm_device *dev); | |
749 | extern int i915_restore_state(struct drm_device *dev); | |
0a3e67a4 JB |
750 | |
751 | /* i915_suspend.c */ | |
752 | extern int i915_save_state(struct drm_device *dev); | |
753 | extern int i915_restore_state(struct drm_device *dev); | |
317c35d1 | 754 | |
65e082c9 | 755 | #ifdef CONFIG_ACPI |
8ee1c3db | 756 | /* i915_opregion.c */ |
74a365b3 | 757 | extern int intel_opregion_init(struct drm_device *dev, int resume); |
3b1c1c11 | 758 | extern void intel_opregion_free(struct drm_device *dev, int suspend); |
8ee1c3db MG |
759 | extern void opregion_asle_intr(struct drm_device *dev); |
760 | extern void opregion_enable_asle(struct drm_device *dev); | |
65e082c9 | 761 | #else |
03ae61dd | 762 | static inline int intel_opregion_init(struct drm_device *dev, int resume) { return 0; } |
3b1c1c11 | 763 | static inline void intel_opregion_free(struct drm_device *dev, int suspend) { return; } |
65e082c9 LB |
764 | static inline void opregion_asle_intr(struct drm_device *dev) { return; } |
765 | static inline void opregion_enable_asle(struct drm_device *dev) { return; } | |
766 | #endif | |
8ee1c3db | 767 | |
79e53945 JB |
768 | /* modesetting */ |
769 | extern void intel_modeset_init(struct drm_device *dev); | |
770 | extern void intel_modeset_cleanup(struct drm_device *dev); | |
771 | ||
546b0974 EA |
772 | /** |
773 | * Lock test for when it's just for synchronization of ring access. | |
774 | * | |
775 | * In that case, we don't need to do it when GEM is initialized as nobody else | |
776 | * has access to the ring. | |
777 | */ | |
778 | #define RING_LOCK_TEST_WITH_RETURN(dev, file_priv) do { \ | |
779 | if (((drm_i915_private_t *)dev->dev_private)->ring.ring_obj == NULL) \ | |
780 | LOCK_TEST_WITH_RETURN(dev, file_priv); \ | |
781 | } while (0) | |
782 | ||
3043c60c EA |
783 | #define I915_READ(reg) readl(dev_priv->regs + (reg)) |
784 | #define I915_WRITE(reg, val) writel(val, dev_priv->regs + (reg)) | |
785 | #define I915_READ16(reg) readw(dev_priv->regs + (reg)) | |
786 | #define I915_WRITE16(reg, val) writel(val, dev_priv->regs + (reg)) | |
787 | #define I915_READ8(reg) readb(dev_priv->regs + (reg)) | |
788 | #define I915_WRITE8(reg, val) writeb(val, dev_priv->regs + (reg)) | |
de151cf6 | 789 | #define I915_WRITE64(reg, val) writeq(val, dev_priv->regs + (reg)) |
049ef7e4 | 790 | #define I915_READ64(reg) readq(dev_priv->regs + (reg)) |
7d57382e | 791 | #define POSTING_READ(reg) (void)I915_READ(reg) |
1da177e4 LT |
792 | |
793 | #define I915_VERBOSE 0 | |
794 | ||
0ef82af7 CW |
795 | #define RING_LOCALS volatile unsigned int *ring_virt__; |
796 | ||
797 | #define BEGIN_LP_RING(n) do { \ | |
798 | int bytes__ = 4*(n); \ | |
799 | if (I915_VERBOSE) DRM_DEBUG("BEGIN_LP_RING(%d)\n", (n)); \ | |
800 | /* a wrap must occur between instructions so pad beforehand */ \ | |
801 | if (unlikely (dev_priv->ring.tail + bytes__ > dev_priv->ring.Size)) \ | |
802 | i915_wrap_ring(dev); \ | |
803 | if (unlikely (dev_priv->ring.space < bytes__)) \ | |
804 | i915_wait_ring(dev, bytes__, __func__); \ | |
805 | ring_virt__ = (unsigned int *) \ | |
806 | (dev_priv->ring.virtual_start + dev_priv->ring.tail); \ | |
807 | dev_priv->ring.tail += bytes__; \ | |
808 | dev_priv->ring.tail &= dev_priv->ring.Size - 1; \ | |
809 | dev_priv->ring.space -= bytes__; \ | |
1da177e4 LT |
810 | } while (0) |
811 | ||
0ef82af7 | 812 | #define OUT_RING(n) do { \ |
1da177e4 | 813 | if (I915_VERBOSE) DRM_DEBUG(" OUT_RING %x\n", (int)(n)); \ |
0ef82af7 | 814 | *ring_virt__++ = (n); \ |
1da177e4 LT |
815 | } while (0) |
816 | ||
817 | #define ADVANCE_LP_RING() do { \ | |
0ef82af7 CW |
818 | if (I915_VERBOSE) \ |
819 | DRM_DEBUG("ADVANCE_LP_RING %x\n", dev_priv->ring.tail); \ | |
820 | I915_WRITE(PRB0_TAIL, dev_priv->ring.tail); \ | |
1da177e4 LT |
821 | } while(0) |
822 | ||
ba8bbcf6 | 823 | /** |
585fb111 JB |
824 | * Reads a dword out of the status page, which is written to from the command |
825 | * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or | |
826 | * MI_STORE_DATA_IMM. | |
ba8bbcf6 | 827 | * |
585fb111 | 828 | * The following dwords have a reserved meaning: |
0cdad7e8 KP |
829 | * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes. |
830 | * 0x04: ring 0 head pointer | |
831 | * 0x05: ring 1 head pointer (915-class) | |
832 | * 0x06: ring 2 head pointer (915-class) | |
833 | * 0x10-0x1b: Context status DWords (GM45) | |
834 | * 0x1f: Last written status offset. (GM45) | |
ba8bbcf6 | 835 | * |
0cdad7e8 | 836 | * The area from dword 0x20 to 0x3ff is available for driver usage. |
ba8bbcf6 | 837 | */ |
585fb111 | 838 | #define READ_HWSP(dev_priv, reg) (((volatile u32*)(dev_priv->hw_status_page))[reg]) |
0baf823a | 839 | #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX) |
0cdad7e8 | 840 | #define I915_GEM_HWS_INDEX 0x20 |
0baf823a | 841 | #define I915_BREADCRUMB_INDEX 0x21 |
ba8bbcf6 | 842 | |
0ef82af7 | 843 | extern int i915_wrap_ring(struct drm_device * dev); |
585fb111 | 844 | extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller); |
ba8bbcf6 JB |
845 | |
846 | #define IS_I830(dev) ((dev)->pci_device == 0x3577) | |
847 | #define IS_845G(dev) ((dev)->pci_device == 0x2562) | |
848 | #define IS_I85X(dev) ((dev)->pci_device == 0x3582) | |
849 | #define IS_I855(dev) ((dev)->pci_device == 0x3582) | |
850 | #define IS_I865G(dev) ((dev)->pci_device == 0x2572) | |
851 | ||
4d1f7888 | 852 | #define IS_I915G(dev) ((dev)->pci_device == 0x2582 || (dev)->pci_device == 0x258a) |
ba8bbcf6 JB |
853 | #define IS_I915GM(dev) ((dev)->pci_device == 0x2592) |
854 | #define IS_I945G(dev) ((dev)->pci_device == 0x2772) | |
3bf48468 JB |
855 | #define IS_I945GM(dev) ((dev)->pci_device == 0x27A2 ||\ |
856 | (dev)->pci_device == 0x27AE) | |
ba8bbcf6 JB |
857 | #define IS_I965G(dev) ((dev)->pci_device == 0x2972 || \ |
858 | (dev)->pci_device == 0x2982 || \ | |
859 | (dev)->pci_device == 0x2992 || \ | |
860 | (dev)->pci_device == 0x29A2 || \ | |
861 | (dev)->pci_device == 0x2A02 || \ | |
5f5f9d4c | 862 | (dev)->pci_device == 0x2A12 || \ |
d3adbc0c ZW |
863 | (dev)->pci_device == 0x2A42 || \ |
864 | (dev)->pci_device == 0x2E02 || \ | |
865 | (dev)->pci_device == 0x2E12 || \ | |
72021788 | 866 | (dev)->pci_device == 0x2E22 || \ |
280da227 | 867 | (dev)->pci_device == 0x2E32 || \ |
7839c5d5 | 868 | (dev)->pci_device == 0x2E42 || \ |
280da227 ZW |
869 | (dev)->pci_device == 0x0042 || \ |
870 | (dev)->pci_device == 0x0046) | |
ba8bbcf6 | 871 | |
c9ed4486 ML |
872 | #define IS_I965GM(dev) ((dev)->pci_device == 0x2A02 || \ |
873 | (dev)->pci_device == 0x2A12) | |
ba8bbcf6 | 874 | |
b9bfdfe6 | 875 | #define IS_GM45(dev) ((dev)->pci_device == 0x2A42) |
5f5f9d4c | 876 | |
d3adbc0c ZW |
877 | #define IS_G4X(dev) ((dev)->pci_device == 0x2E02 || \ |
878 | (dev)->pci_device == 0x2E12 || \ | |
60fd99e3 | 879 | (dev)->pci_device == 0x2E22 || \ |
72021788 | 880 | (dev)->pci_device == 0x2E32 || \ |
7839c5d5 | 881 | (dev)->pci_device == 0x2E42 || \ |
60fd99e3 | 882 | IS_GM45(dev)) |
d3adbc0c | 883 | |
2177832f SL |
884 | #define IS_IGDG(dev) ((dev)->pci_device == 0xa001) |
885 | #define IS_IGDGM(dev) ((dev)->pci_device == 0xa011) | |
886 | #define IS_IGD(dev) (IS_IGDG(dev) || IS_IGDGM(dev)) | |
887 | ||
ba8bbcf6 JB |
888 | #define IS_G33(dev) ((dev)->pci_device == 0x29C2 || \ |
889 | (dev)->pci_device == 0x29B2 || \ | |
2177832f SL |
890 | (dev)->pci_device == 0x29D2 || \ |
891 | (IS_IGD(dev))) | |
ba8bbcf6 | 892 | |
280da227 ZW |
893 | #define IS_IGDNG_D(dev) ((dev)->pci_device == 0x0042) |
894 | #define IS_IGDNG_M(dev) ((dev)->pci_device == 0x0046) | |
895 | #define IS_IGDNG(dev) (IS_IGDNG_D(dev) || IS_IGDNG_M(dev)) | |
896 | ||
ba8bbcf6 | 897 | #define IS_I9XX(dev) (IS_I915G(dev) || IS_I915GM(dev) || IS_I945G(dev) || \ |
280da227 ZW |
898 | IS_I945GM(dev) || IS_I965G(dev) || IS_G33(dev) || \ |
899 | IS_IGDNG(dev)) | |
ba8bbcf6 JB |
900 | |
901 | #define IS_MOBILE(dev) (IS_I830(dev) || IS_I85X(dev) || IS_I915GM(dev) || \ | |
2177832f | 902 | IS_I945GM(dev) || IS_I965GM(dev) || IS_GM45(dev) || \ |
280da227 | 903 | IS_IGD(dev) || IS_IGDNG_M(dev)) |
ba8bbcf6 | 904 | |
280da227 ZW |
905 | #define I915_NEED_GFX_HWS(dev) (IS_G33(dev) || IS_GM45(dev) || IS_G4X(dev) || \ |
906 | IS_IGDNG(dev)) | |
0f973f27 JB |
907 | /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte |
908 | * rows, which changed the alignment requirements and fence programming. | |
909 | */ | |
910 | #define HAS_128_BYTE_Y_TILING(dev) (IS_I9XX(dev) && !(IS_I915G(dev) || \ | |
911 | IS_I915GM(dev))) | |
280da227 | 912 | #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_IGDNG(dev)) |
a4fc5ed6 | 913 | #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_IGDNG(dev)) |
32f9d658 | 914 | #define SUPPORTS_EDP(dev) (IS_IGDNG_M(dev)) |
af729a26 | 915 | #define I915_HAS_HOTPLUG(dev) (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev) || IS_I965G(dev)) |
7662c8bd | 916 | /* dsparb controlled by hw only */ |
22bd50c5 | 917 | #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IGDNG(dev)) |
b39d50e5 | 918 | |
652c393a JB |
919 | #define HAS_FW_BLC(dev) (IS_I9XX(dev) || IS_G4X(dev) || IS_IGDNG(dev)) |
920 | #define HAS_PIPE_CXSR(dev) (IS_G4X(dev) || IS_IGDNG(dev)) | |
921 | ||
ba8bbcf6 | 922 | #define PRIMARY_RINGBUFFER_SIZE (128*1024) |
0d6aa60b | 923 | |
1da177e4 | 924 | #endif |