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drm/i915/ddi: use struct for ddi buf translation tables
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_drv.h
CommitLineData
1da177e4
LT		 1/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
2 */
0d6aa60b 3/*
bc54fd1a 4 *
1da177e4
LT		 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
bc54fd1a
DA		 7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
0d6aa60b 28 */
1da177e4
LT		 29
30#ifndef _I915_DRV_H_
31#define _I915_DRV_H_
32
e9b73c67
CW		 33#include <uapi/drm/i915_drm.h>
34
585fb111 35#include "i915_reg.h"
79e53945 36#include "intel_bios.h"
8187a2b7 37#include "intel_ringbuffer.h"
b20385f1 38#include "intel_lrc.h"
0260c420 39#include "i915_gem_gtt.h"
0839ccb8 40#include <linux/io-mapping.h>
f899fc64 41#include <linux/i2c.h>
c167a6fc 42#include <linux/i2c-algo-bit.h>
0ade6386 43#include <drm/intel-gtt.h>
aaa6fd2a 44#include <linux/backlight.h>
5cc9ed4b 45#include <linux/hashtable.h>
2911a35b 46#include <linux/intel-iommu.h>
742cbee8 47#include <linux/kref.h>
9ee32fea 48#include <linux/pm_qos.h>
585fb111 49
1da177e4
LT		 50/* General customization:
51 */
52
1da177e4
LT		 53#define DRIVER_NAME "i915"
54#define DRIVER_DESC "Intel Graphics"
c2813548 55#define DRIVER_DATE "20140822"
1da177e4 56
317c35d1 57enum pipe {
752aa88a 58 INVALID_PIPE = -1,
317c35d1
JB		 59 PIPE_A = 0,
60 PIPE_B,
9db4a9c7 61 PIPE_C,
a57c774a
AK		 62 _PIPE_EDP,
63 I915_MAX_PIPES = _PIPE_EDP
317c35d1 64};
9db4a9c7 65#define pipe_name(p) ((p) + 'A')
317c35d1 66
a5c961d1
PZ		 67enum transcoder {
68 TRANSCODER_A = 0,
69 TRANSCODER_B,
70 TRANSCODER_C,
a57c774a
AK		 71 TRANSCODER_EDP,
72 I915_MAX_TRANSCODERS
a5c961d1
PZ		 73};
74#define transcoder_name(t) ((t) + 'A')
75
80824003
JB		 76enum plane {
77 PLANE_A = 0,
78 PLANE_B,
9db4a9c7 79 PLANE_C,
80824003 80};
9db4a9c7 81#define plane_name(p) ((p) + 'A')
52440211 82
d615a166 83#define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
06da8da2 84
2b139522
ED		 85enum port {
86 PORT_A = 0,
87 PORT_B,
88 PORT_C,
89 PORT_D,
90 PORT_E,
91 I915_MAX_PORTS
92};
93#define port_name(p) ((p) + 'A')
94
a09caddd 95#define I915_NUM_PHYS_VLV 2
e4607fcf
CML		 96
97enum dpio_channel {
98 DPIO_CH0,
99 DPIO_CH1
100};
101
102enum dpio_phy {
103 DPIO_PHY0,
104 DPIO_PHY1
105};
106
b97186f0
PZ		 107enum intel_display_power_domain {
108 POWER_DOMAIN_PIPE_A,
109 POWER_DOMAIN_PIPE_B,
110 POWER_DOMAIN_PIPE_C,
111 POWER_DOMAIN_PIPE_A_PANEL_FITTER,
112 POWER_DOMAIN_PIPE_B_PANEL_FITTER,
113 POWER_DOMAIN_PIPE_C_PANEL_FITTER,
114 POWER_DOMAIN_TRANSCODER_A,
115 POWER_DOMAIN_TRANSCODER_B,
116 POWER_DOMAIN_TRANSCODER_C,
f52e353e 117 POWER_DOMAIN_TRANSCODER_EDP,
319be8ae
ID		 118 POWER_DOMAIN_PORT_DDI_A_2_LANES,
119 POWER_DOMAIN_PORT_DDI_A_4_LANES,
120 POWER_DOMAIN_PORT_DDI_B_2_LANES,
121 POWER_DOMAIN_PORT_DDI_B_4_LANES,
122 POWER_DOMAIN_PORT_DDI_C_2_LANES,
123 POWER_DOMAIN_PORT_DDI_C_4_LANES,
124 POWER_DOMAIN_PORT_DDI_D_2_LANES,
125 POWER_DOMAIN_PORT_DDI_D_4_LANES,
126 POWER_DOMAIN_PORT_DSI,
127 POWER_DOMAIN_PORT_CRT,
128 POWER_DOMAIN_PORT_OTHER,
cdf8dd7f 129 POWER_DOMAIN_VGA,
fbeeaa23 130 POWER_DOMAIN_AUDIO,
bd2bb1b9 131 POWER_DOMAIN_PLLS,
baa70707 132 POWER_DOMAIN_INIT,
bddc7645
ID		 133
134 POWER_DOMAIN_NUM,
b97186f0
PZ		 135};
136
137#define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
138#define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
139 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
f52e353e
ID		 140#define POWER_DOMAIN_TRANSCODER(tran) \
141 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
142 (tran) + POWER_DOMAIN_TRANSCODER_A)
b97186f0 143
1d843f9d
EE		 144enum hpd_pin {
145 HPD_NONE = 0,
146 HPD_PORT_A = HPD_NONE, /* PORT_A is internal */
147 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
148 HPD_CRT,
149 HPD_SDVO_B,
150 HPD_SDVO_C,
151 HPD_PORT_B,
152 HPD_PORT_C,
153 HPD_PORT_D,
154 HPD_NUM_PINS
155};
156
2a2d5482
CW		 157#define I915_GEM_GPU_DOMAINS \
158 (I915_GEM_DOMAIN_RENDER | \
159 I915_GEM_DOMAIN_SAMPLER | \
160 I915_GEM_DOMAIN_COMMAND | \
161 I915_GEM_DOMAIN_INSTRUCTION | \
162 I915_GEM_DOMAIN_VERTEX)
62fdfeaf 163
055e393f
DL		 164#define for_each_pipe(__dev_priv, __p) \
165 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
d615a166 166#define for_each_sprite(p, s) for ((s) = 0; (s) < INTEL_INFO(dev)->num_sprites[(p)]; (s)++)
9db4a9c7 167
d79b814d
DL		 168#define for_each_crtc(dev, crtc) \
169 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
170
d063ae48
DL		 171#define for_each_intel_crtc(dev, intel_crtc) \
172 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head)
173
b2784e15
DL		 174#define for_each_intel_encoder(dev, intel_encoder) \
175 list_for_each_entry(intel_encoder, \
176 &(dev)->mode_config.encoder_list, \
177 base.head)
178
6c2b7c12
DV		 179#define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
180 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
181 if ((intel_encoder)->base.crtc == (__crtc))
182
53f5e3ca
JB		 183#define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
184 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
185 if ((intel_connector)->base.encoder == (__encoder))
186
b04c5bd6
BF		 187#define for_each_power_domain(domain, mask) \
188 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
189 if ((1 << (domain)) & (mask))
190
e7b903d2 191struct drm_i915_private;
5cc9ed4b 192struct i915_mmu_object;
e7b903d2 193
46edb027
DV		 194enum intel_dpll_id {
195 DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */
196 /* real shared dpll ids must be >= 0 */
9cd86933
DV		 197 DPLL_ID_PCH_PLL_A = 0,
198 DPLL_ID_PCH_PLL_B = 1,
199 DPLL_ID_WRPLL1 = 0,
200 DPLL_ID_WRPLL2 = 1,
46edb027
DV		 201};
202#define I915_NUM_PLLS 2
203
5358901f 204struct intel_dpll_hw_state {
dcfc3552 205 /* i9xx, pch plls */
66e985c0 206 uint32_t dpll;
8bcc2795 207 uint32_t dpll_md;
66e985c0
DV		 208 uint32_t fp0;
209 uint32_t fp1;
dcfc3552
DL		 210
211 /* hsw, bdw */
d452c5b6 212 uint32_t wrpll;
5358901f
DV		 213};
214
e72f9fbf 215struct intel_shared_dpll {
ee7b9f93
JB		 216 int refcount; /* count of number of CRTCs sharing this PLL */
217 int active; /* count of number of active CRTCs (i.e. DPMS on) */
218 bool on; /* is the PLL actually active? Disabled during modeset */
46edb027
DV		 219 const char *name;
220 /* should match the index in the dev_priv->shared_dplls array */
221 enum intel_dpll_id id;
5358901f 222 struct intel_dpll_hw_state hw_state;
96f6128c
DV		 223 /* The mode_set hook is optional and should be used together with the
224 * intel_prepare_shared_dpll function. */
15bdd4cf
DV		 225 void (*mode_set)(struct drm_i915_private *dev_priv,
226 struct intel_shared_dpll *pll);
e7b903d2
DV		 227 void (*enable)(struct drm_i915_private *dev_priv,
228 struct intel_shared_dpll *pll);
229 void (*disable)(struct drm_i915_private *dev_priv,
230 struct intel_shared_dpll *pll);
5358901f
DV		 231 bool (*get_hw_state)(struct drm_i915_private *dev_priv,
232 struct intel_shared_dpll *pll,
233 struct intel_dpll_hw_state *hw_state);
ee7b9f93 234};
ee7b9f93 235
e69d0bc1
DV		 236/* Used by dp and fdi links */
237struct intel_link_m_n {
238 uint32_t tu;
239 uint32_t gmch_m;
240 uint32_t gmch_n;
241 uint32_t link_m;
242 uint32_t link_n;
243};
244
245void intel_link_compute_m_n(int bpp, int nlanes,
246 int pixel_clock, int link_clock,
247 struct intel_link_m_n *m_n);
248
1da177e4
LT		 249/* Interface history:
250 *
251 * 1.1: Original.
0d6aa60b
DA		 252 * 1.2: Add Power Management
253 * 1.3: Add vblank support
de227f5f 254 * 1.4: Fix cmdbuffer path, add heap destroy
702880f2 255 * 1.5: Add vblank pipe configuration
2228ed67
MCA		 256 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
257 * - Support vertical blank on secondary display pipe
1da177e4
LT		 258 */
259#define DRIVER_MAJOR 1
2228ed67 260#define DRIVER_MINOR 6
1da177e4
LT		 261#define DRIVER_PATCHLEVEL 0
262
23bc5982 263#define WATCH_LISTS 0
42d6ab48 264#define WATCH_GTT 0
673a394b 265
0a3e67a4
JB		 266struct opregion_header;
267struct opregion_acpi;
268struct opregion_swsci;
269struct opregion_asle;
270
8ee1c3db 271struct intel_opregion {
5bc4418b
BW		 272 struct opregion_header __iomem *header;
273 struct opregion_acpi __iomem *acpi;
274 struct opregion_swsci __iomem *swsci;
ebde53c7
JN		 275 u32 swsci_gbda_sub_functions;
276 u32 swsci_sbcb_sub_functions;
5bc4418b
BW		 277 struct opregion_asle __iomem *asle;
278 void __iomem *vbt;
01fe9dbd 279 u32 __iomem *lid_state;
91a60f20 280 struct work_struct asle_work;
8ee1c3db 281};
44834a67 282#define OPREGION_SIZE (8*1024)
8ee1c3db 283
6ef3d427
CW		 284struct intel_overlay;
285struct intel_overlay_error_state;
286
7c1c2871
DA		 287struct drm_i915_master_private {
288 drm_local_map_t *sarea;
289 struct _drm_i915_sarea *sarea_priv;
290};
de151cf6 291#define I915_FENCE_REG_NONE -1
42b5aeab
VS		 292#define I915_MAX_NUM_FENCES 32
293/* 32 fences + sign bit for FENCE_REG_NONE */
294#define I915_MAX_NUM_FENCE_BITS 6
de151cf6
JB		 295
296struct drm_i915_fence_reg {
007cc8ac 297 struct list_head lru_list;
caea7476 298 struct drm_i915_gem_object *obj;
1690e1eb 299 int pin_count;
de151cf6 300};
7c1c2871 301
9b9d172d 302struct sdvo_device_mapping {
e957d772 303 u8 initialized;
9b9d172d 304 u8 dvo_port;
305 u8 slave_addr;
306 u8 dvo_wiring;
e957d772 307 u8 i2c_pin;
b1083333 308 u8 ddc_pin;
9b9d172d 309};
310
c4a1d9e4
CW		 311struct intel_display_error_state;
312
63eeaf38 313struct drm_i915_error_state {
742cbee8 314 struct kref ref;
585b0288
BW		 315 struct timeval time;
316
cb383002 317 char error_msg[128];
48b031e3 318 u32 reset_count;
62d5d69b 319 u32 suspend_count;
cb383002 320
585b0288 321 /* Generic register state */
63eeaf38
JB		 322 u32 eir;
323 u32 pgtbl_er;
be998e2e 324 u32 ier;
885ea5a8 325 u32 gtier[4];
b9a3906b 326 u32 ccid;
0f3b6849
CW		 327 u32 derrmr;
328 u32 forcewake;
585b0288
BW		 329 u32 error; /* gen6+ */
330 u32 err_int; /* gen7 */
331 u32 done_reg;
91ec5d11
BW		 332 u32 gac_eco;
333 u32 gam_ecochk;
334 u32 gab_ctl;
335 u32 gfx_mode;
585b0288 336 u32 extra_instdone[I915_NUM_INSTDONE_REG];
585b0288
BW		 337 u64 fence[I915_MAX_NUM_FENCES];
338 struct intel_overlay_error_state *overlay;
339 struct intel_display_error_state *display;
0ca36d78 340 struct drm_i915_error_object *semaphore_obj;
585b0288 341
52d39a21 342 struct drm_i915_error_ring {
372fbb8e 343 bool valid;
362b8af7
BW		 344 /* Software tracked state */
345 bool waiting;
346 int hangcheck_score;
347 enum intel_ring_hangcheck_action hangcheck_action;
348 int num_requests;
349
350 /* our own tracking of ring head and tail */
351 u32 cpu_ring_head;
352 u32 cpu_ring_tail;
353
354 u32 semaphore_seqno[I915_NUM_RINGS - 1];
355
356 /* Register state */
357 u32 tail;
358 u32 head;
359 u32 ctl;
360 u32 hws;
361 u32 ipeir;
362 u32 ipehr;
363 u32 instdone;
362b8af7
BW		 364 u32 bbstate;
365 u32 instpm;
366 u32 instps;
367 u32 seqno;
368 u64 bbaddr;
50877445 369 u64 acthd;
362b8af7 370 u32 fault_reg;
13ffadd1 371 u64 faddr;
362b8af7
BW		 372 u32 rc_psmi; /* sleep state */
373 u32 semaphore_mboxes[I915_NUM_RINGS - 1];
374
52d39a21
CW		 375 struct drm_i915_error_object {
376 int page_count;
377 u32 gtt_offset;
378 u32 *pages[0];
ab0e7ff9 379 } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;
362b8af7 380
52d39a21
CW		 381 struct drm_i915_error_request {
382 long jiffies;
383 u32 seqno;
ee4f42b1 384 u32 tail;
52d39a21 385 } *requests;
6c7a01ec
BW		 386
387 struct {
388 u32 gfx_mode;
389 union {
390 u64 pdp[4];
391 u32 pp_dir_base;
392 };
393 } vm_info;
ab0e7ff9
CW		 394
395 pid_t pid;
396 char comm[TASK_COMM_LEN];
52d39a21 397 } ring[I915_NUM_RINGS];
3a448734 398
9df30794 399 struct drm_i915_error_buffer {
a779e5ab 400 u32 size;
9df30794 401 u32 name;
0201f1ec 402 u32 rseqno, wseqno;
9df30794
CW		 403 u32 gtt_offset;
404 u32 read_domains;
405 u32 write_domain;
4b9de737 406 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
9df30794
CW		 407 s32 pinned:2;
408 u32 tiling:2;
409 u32 dirty:1;
410 u32 purgeable:1;
5cc9ed4b 411 u32 userptr:1;
5d1333fc 412 s32 ring:4;
f56383cb 413 u32 cache_level:3;
95f5301d 414 } **active_bo, **pinned_bo;
6c7a01ec 415
95f5301d 416 u32 *active_bo_count, *pinned_bo_count;
3a448734 417 u32 vm_count;
63eeaf38
JB		 418};
419
7bd688cd 420struct intel_connector;
b8cecdf5 421struct intel_crtc_config;
46f297fb 422struct intel_plane_config;
0e8ffe1b 423struct intel_crtc;
ee9300bb
DV		 424struct intel_limit;
425struct dpll;
b8cecdf5 426
e70236a8 427struct drm_i915_display_funcs {
ee5382ae 428 bool (*fbc_enabled)(struct drm_device *dev);
993495ae 429 void (*enable_fbc)(struct drm_crtc *crtc);
e70236a8
JB		 430 void (*disable_fbc)(struct drm_device *dev);
431 int (*get_display_clock_speed)(struct drm_device *dev);
432 int (*get_fifo_size)(struct drm_device *dev, int plane);
ee9300bb
DV		 433 /**
434 * find_dpll() - Find the best values for the PLL
435 * @limit: limits for the PLL
436 * @crtc: current CRTC
437 * @target: target frequency in kHz
438 * @refclk: reference clock frequency in kHz
439 * @match_clock: if provided, @best_clock P divider must
440 * match the P divider from @match_clock
441 * used for LVDS downclocking
442 * @best_clock: best PLL values found
443 *
444 * Returns true on success, false on failure.
445 */
446 bool (*find_dpll)(const struct intel_limit *limit,
447 struct drm_crtc *crtc,
448 int target, int refclk,
449 struct dpll *match_clock,
450 struct dpll *best_clock);
46ba614c 451 void (*update_wm)(struct drm_crtc *crtc);
adf3d35e
VS		 452 void (*update_sprite_wm)(struct drm_plane *plane,
453 struct drm_crtc *crtc,
ed57cb8a
DL		 454 uint32_t sprite_width, uint32_t sprite_height,
455 int pixel_size, bool enable, bool scaled);
47fab737 456 void (*modeset_global_resources)(struct drm_device *dev);
0e8ffe1b
DV		 457 /* Returns the active state of the crtc, and if the crtc is active,
458 * fills out the pipe-config with the hw state. */
459 bool (*get_pipe_config)(struct intel_crtc *,
460 struct intel_crtc_config *);
46f297fb
JB		 461 void (*get_plane_config)(struct intel_crtc *,
462 struct intel_plane_config *);
f564048e 463 int (*crtc_mode_set)(struct drm_crtc *crtc,
f564048e
EA		 464 int x, int y,
465 struct drm_framebuffer *old_fb);
76e5a89c
DV		 466 void (*crtc_enable)(struct drm_crtc *crtc);
467 void (*crtc_disable)(struct drm_crtc *crtc);
ee7b9f93 468 void (*off)(struct drm_crtc *crtc);
e0dac65e 469 void (*write_eld)(struct drm_connector *connector,
34427052
JN		 470 struct drm_crtc *crtc,
471 struct drm_display_mode *mode);
674cf967 472 void (*fdi_link_train)(struct drm_crtc *crtc);
6067aaea 473 void (*init_clock_gating)(struct drm_device *dev);
8c9f3aaf
JB		 474 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
475 struct drm_framebuffer *fb,
ed8d1975 476 struct drm_i915_gem_object *obj,
a4872ba6 477 struct intel_engine_cs *ring,
ed8d1975 478 uint32_t flags);
29b9bde6
DV		 479 void (*update_primary_plane)(struct drm_crtc *crtc,
480 struct drm_framebuffer *fb,
481 int x, int y);
20afbda2 482 void (*hpd_irq_setup)(struct drm_device *dev);
e70236a8
JB		 483 /* clock updates for mode set */
484 /* cursor updates */
485 /* render clock increase/decrease */
486 /* display clock increase/decrease */
487 /* pll clock increase/decrease */
7bd688cd
JN		 488
489 int (*setup_backlight)(struct intel_connector *connector);
7bd688cd
JN		 490 uint32_t (*get_backlight)(struct intel_connector *connector);
491 void (*set_backlight)(struct intel_connector *connector,
492 uint32_t level);
493 void (*disable_backlight)(struct intel_connector *connector);
494 void (*enable_backlight)(struct intel_connector *connector);
e70236a8
JB		 495};
496
907b28c5 497struct intel_uncore_funcs {
c8d9a590
D		 498 void (*force_wake_get)(struct drm_i915_private *dev_priv,
499 int fw_engine);
500 void (*force_wake_put)(struct drm_i915_private *dev_priv,
501 int fw_engine);
0b274481
BW		 502
503 uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
504 uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
505 uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
506 uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
507
508 void (*mmio_writeb)(struct drm_i915_private *dev_priv, off_t offset,
509 uint8_t val, bool trace);
510 void (*mmio_writew)(struct drm_i915_private *dev_priv, off_t offset,
511 uint16_t val, bool trace);
512 void (*mmio_writel)(struct drm_i915_private *dev_priv, off_t offset,
513 uint32_t val, bool trace);
514 void (*mmio_writeq)(struct drm_i915_private *dev_priv, off_t offset,
515 uint64_t val, bool trace);
990bbdad
CW		 516};
517
907b28c5
CW		 518struct intel_uncore {
519 spinlock_t lock; /** lock is also taken in irq contexts. */
520
521 struct intel_uncore_funcs funcs;
522
523 unsigned fifo_count;
524 unsigned forcewake_count;
aec347ab 525
940aece4
D		 526 unsigned fw_rendercount;
527 unsigned fw_mediacount;
528
8232644c 529 struct timer_list force_wake_timer;
907b28c5
CW		 530};
531
79fc46df
DL		 532#define DEV_INFO_FOR_EACH_FLAG(func, sep) \
533 func(is_mobile) sep \
534 func(is_i85x) sep \
535 func(is_i915g) sep \
536 func(is_i945gm) sep \
537 func(is_g33) sep \
538 func(need_gfx_hws) sep \
539 func(is_g4x) sep \
540 func(is_pineview) sep \
541 func(is_broadwater) sep \
542 func(is_crestline) sep \
543 func(is_ivybridge) sep \
544 func(is_valleyview) sep \
545 func(is_haswell) sep \
b833d685 546 func(is_preliminary) sep \
79fc46df
DL		 547 func(has_fbc) sep \
548 func(has_pipe_cxsr) sep \
549 func(has_hotplug) sep \
550 func(cursor_needs_physical) sep \
551 func(has_overlay) sep \
552 func(overlay_needs_physical) sep \
553 func(supports_tv) sep \
dd93be58 554 func(has_llc) sep \
30568c45
DL		 555 func(has_ddi) sep \
556 func(has_fpga_dbg)
c96ea64e 557
a587f779
DL		 558#define DEFINE_FLAG(name) u8 name:1
559#define SEP_SEMICOLON ;
c96ea64e 560
cfdf1fa2 561struct intel_device_info {
10fce67a 562 u32 display_mmio_offset;
87f1f465 563 u16 device_id;
7eb552ae 564 u8 num_pipes:3;
d615a166 565 u8 num_sprites[I915_MAX_PIPES];
c96c3a8c 566 u8 gen;
73ae478c 567 u8 ring_mask; /* Rings supported by the HW */
a587f779 568 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
a57c774a
AK		 569 /* Register offsets for the various display pipes and transcoders */
570 int pipe_offsets[I915_MAX_TRANSCODERS];
571 int trans_offsets[I915_MAX_TRANSCODERS];
a57c774a 572 int palette_offsets[I915_MAX_PIPES];
5efb3e28 573 int cursor_offsets[I915_MAX_PIPES];
cfdf1fa2
KH		 574};
575
a587f779
DL		 576#undef DEFINE_FLAG
577#undef SEP_SEMICOLON
578
7faf1ab2
DV		 579enum i915_cache_level {
580 I915_CACHE_NONE = 0,
350ec881
CW		 581 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
582 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
583 caches, eg sampler/render caches, and the
584 large Last-Level-Cache. LLC is coherent with
585 the CPU, but L3 is only visible to the GPU. */
651d794f 586 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
7faf1ab2
DV		 587};
588
e59ec13d
MK		 589struct i915_ctx_hang_stats {
590 /* This context had batch pending when hang was declared */
591 unsigned batch_pending;
592
593 /* This context had batch active when hang was declared */
594 unsigned batch_active;
be62acb4
MK		 595
596 /* Time when this context was last blamed for a GPU reset */
597 unsigned long guilty_ts;
598
599 /* This context is banned to submit more work */
600 bool banned;
e59ec13d 601};
40521054
BW		 602
603/* This must match up with the value previously used for execbuf2.rsvd1. */
821d66dd 604#define DEFAULT_CONTEXT_HANDLE 0
31b7a88d
OM		 605/**
606 * struct intel_context - as the name implies, represents a context.
607 * @ref: reference count.
608 * @user_handle: userspace tracking identity for this context.
609 * @remap_slice: l3 row remapping information.
610 * @file_priv: filp associated with this context (NULL for global default
611 * context).
612 * @hang_stats: information about the role of this context in possible GPU
613 * hangs.
614 * @vm: virtual memory space used by this context.
615 * @legacy_hw_ctx: render context backing object and whether it is correctly
616 * initialized (legacy ring submission mechanism only).
617 * @link: link in the global list of contexts.
618 *
619 * Contexts are memory images used by the hardware to store copies of their
620 * internal state.
621 */
273497e5 622struct intel_context {
dce3271b 623 struct kref ref;
821d66dd 624 int user_handle;
3ccfd19d 625 uint8_t remap_slice;
40521054 626 struct drm_i915_file_private *file_priv;
e59ec13d 627 struct i915_ctx_hang_stats hang_stats;
ae6c4806 628 struct i915_hw_ppgtt *ppgtt;
a33afea5 629
c9e003af 630 /* Legacy ring buffer submission */
ea0c76f8
OM		 631 struct {
632 struct drm_i915_gem_object *rcs_state;
633 bool initialized;
634 } legacy_hw_ctx;
635
c9e003af
OM		 636 /* Execlists */
637 struct {
638 struct drm_i915_gem_object *state;
84c2377f 639 struct intel_ringbuffer *ringbuf;
c9e003af
OM		 640 } engine[I915_NUM_RINGS];
641
a33afea5 642 struct list_head link;
40521054
BW		 643};
644
5c3fe8b0
BW		 645struct i915_fbc {
646 unsigned long size;
5e59f717 647 unsigned threshold;
5c3fe8b0
BW		 648 unsigned int fb_id;
649 enum plane plane;
650 int y;
651
c4213885 652 struct drm_mm_node compressed_fb;
5c3fe8b0
BW		 653 struct drm_mm_node *compressed_llb;
654
da46f936
RV		 655 bool false_color;
656
5c3fe8b0
BW		 657 struct intel_fbc_work {
658 struct delayed_work work;
659 struct drm_crtc *crtc;
660 struct drm_framebuffer *fb;
5c3fe8b0
BW		 661 } *fbc_work;
662
29ebf90f
CW		 663 enum no_fbc_reason {
664 FBC_OK, /* FBC is enabled */
665 FBC_UNSUPPORTED, /* FBC is not supported by this chipset */
5c3fe8b0
BW		 666 FBC_NO_OUTPUT, /* no outputs enabled to compress */
667 FBC_STOLEN_TOO_SMALL, /* not enough space for buffers */
668 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
669 FBC_MODE_TOO_LARGE, /* mode too large for compression */
670 FBC_BAD_PLANE, /* fbc not supported on plane */
671 FBC_NOT_TILED, /* buffer not tiled */
672 FBC_MULTIPLE_PIPES, /* more than one pipe active */
673 FBC_MODULE_PARAM,
674 FBC_CHIP_DEFAULT, /* disabled by default on this chip */
675 } no_fbc_reason;
b5e50c3f
JB		 676};
677
439d7ac0
PB		 678struct i915_drrs {
679 struct intel_connector *connector;
680};
681
2807cf69 682struct intel_dp;
a031d709 683struct i915_psr {
f0355c4a 684 struct mutex lock;
a031d709
RV		 685 bool sink_support;
686 bool source_ok;
2807cf69 687 struct intel_dp *enabled;
7c8f8a70
RV		 688 bool active;
689 struct delayed_work work;
9ca15301 690 unsigned busy_frontbuffer_bits;
3f51e471 691};
5c3fe8b0 692
3bad0781 693enum intel_pch {
f0350830 694 PCH_NONE = 0, /* No PCH present */
3bad0781
ZW		 695 PCH_IBX, /* Ibexpeak PCH */
696 PCH_CPT, /* Cougarpoint PCH */
eb877ebf 697 PCH_LPT, /* Lynxpoint PCH */
40c7ead9 698 PCH_NOP,
3bad0781
ZW		 699};
700
988d6ee8
PZ		 701enum intel_sbi_destination {
702 SBI_ICLK,
703 SBI_MPHY,
704};
705
b690e96c 706#define QUIRK_PIPEA_FORCE (1<<0)
435793df 707#define QUIRK_LVDS_SSC_DISABLE (1<<1)
4dca20ef 708#define QUIRK_INVERT_BRIGHTNESS (1<<2)
9c72cc6f 709#define QUIRK_BACKLIGHT_PRESENT (1<<3)
b690e96c 710
8be48d92 711struct intel_fbdev;
1630fe75 712struct intel_fbc_work;
38651674 713
c2b9152f
DV		 714struct intel_gmbus {
715 struct i2c_adapter adapter;
f2ce9faf 716 u32 force_bit;
c2b9152f 717 u32 reg0;
36c785f0 718 u32 gpio_reg;
c167a6fc 719 struct i2c_algo_bit_data bit_algo;
c2b9152f
DV		 720 struct drm_i915_private *dev_priv;
721};
722
f4c956ad 723struct i915_suspend_saved_registers {
ba8bbcf6
JB		 724 u8 saveLBB;
725 u32 saveDSPACNTR;
726 u32 saveDSPBCNTR;
e948e994 727 u32 saveDSPARB;
ba8bbcf6
JB		 728 u32 savePIPEACONF;
729 u32 savePIPEBCONF;
730 u32 savePIPEASRC;
731 u32 savePIPEBSRC;
732 u32 saveFPA0;
733 u32 saveFPA1;
734 u32 saveDPLL_A;
735 u32 saveDPLL_A_MD;
736 u32 saveHTOTAL_A;
737 u32 saveHBLANK_A;
738 u32 saveHSYNC_A;
739 u32 saveVTOTAL_A;
740 u32 saveVBLANK_A;
741 u32 saveVSYNC_A;
742 u32 saveBCLRPAT_A;
5586c8bc 743 u32 saveTRANSACONF;
42048781
ZW		 744 u32 saveTRANS_HTOTAL_A;
745 u32 saveTRANS_HBLANK_A;
746 u32 saveTRANS_HSYNC_A;
747 u32 saveTRANS_VTOTAL_A;
748 u32 saveTRANS_VBLANK_A;
749 u32 saveTRANS_VSYNC_A;
0da3ea12 750 u32 savePIPEASTAT;
ba8bbcf6
JB		 751 u32 saveDSPASTRIDE;
752 u32 saveDSPASIZE;
753 u32 saveDSPAPOS;
585fb111 754 u32 saveDSPAADDR;
ba8bbcf6
JB		 755 u32 saveDSPASURF;
756 u32 saveDSPATILEOFF;
757 u32 savePFIT_PGM_RATIOS;
0eb96d6e 758 u32 saveBLC_HIST_CTL;
ba8bbcf6
JB		 759 u32 saveBLC_PWM_CTL;
760 u32 saveBLC_PWM_CTL2;
07bf139b 761 u32 saveBLC_HIST_CTL_B;
42048781
ZW		 762 u32 saveBLC_CPU_PWM_CTL;
763 u32 saveBLC_CPU_PWM_CTL2;
ba8bbcf6
JB		 764 u32 saveFPB0;
765 u32 saveFPB1;
766 u32 saveDPLL_B;
767 u32 saveDPLL_B_MD;
768 u32 saveHTOTAL_B;
769 u32 saveHBLANK_B;
770 u32 saveHSYNC_B;
771 u32 saveVTOTAL_B;
772 u32 saveVBLANK_B;
773 u32 saveVSYNC_B;
774 u32 saveBCLRPAT_B;
5586c8bc 775 u32 saveTRANSBCONF;
42048781
ZW		 776 u32 saveTRANS_HTOTAL_B;
777 u32 saveTRANS_HBLANK_B;
778 u32 saveTRANS_HSYNC_B;
779 u32 saveTRANS_VTOTAL_B;
780 u32 saveTRANS_VBLANK_B;
781 u32 saveTRANS_VSYNC_B;
0da3ea12 782 u32 savePIPEBSTAT;
ba8bbcf6
JB		 783 u32 saveDSPBSTRIDE;
784 u32 saveDSPBSIZE;
785 u32 saveDSPBPOS;
585fb111 786 u32 saveDSPBADDR;
ba8bbcf6
JB		 787 u32 saveDSPBSURF;
788 u32 saveDSPBTILEOFF;
585fb111
JB		 789 u32 saveVGA0;
790 u32 saveVGA1;
791 u32 saveVGA_PD;
ba8bbcf6
JB		 792 u32 saveVGACNTRL;
793 u32 saveADPA;
794 u32 saveLVDS;
585fb111
JB		 795 u32 savePP_ON_DELAYS;
796 u32 savePP_OFF_DELAYS;
ba8bbcf6
JB		 797 u32 saveDVOA;
798 u32 saveDVOB;
799 u32 saveDVOC;
800 u32 savePP_ON;
801 u32 savePP_OFF;
802 u32 savePP_CONTROL;
585fb111 803 u32 savePP_DIVISOR;
ba8bbcf6
JB		 804 u32 savePFIT_CONTROL;
805 u32 save_palette_a[256];
806 u32 save_palette_b[256];
ba8bbcf6 807 u32 saveFBC_CONTROL;
0da3ea12
JB		 808 u32 saveIER;
809 u32 saveIIR;
810 u32 saveIMR;
42048781
ZW		 811 u32 saveDEIER;
812 u32 saveDEIMR;
813 u32 saveGTIER;
814 u32 saveGTIMR;
815 u32 saveFDI_RXA_IMR;
816 u32 saveFDI_RXB_IMR;
1f84e550 817 u32 saveCACHE_MODE_0;
1f84e550 818 u32 saveMI_ARB_STATE;
ba8bbcf6
JB		 819 u32 saveSWF0[16];
820 u32 saveSWF1[16];
821 u32 saveSWF2[3];
822 u8 saveMSR;
823 u8 saveSR[8];
123f794f 824 u8 saveGR[25];
ba8bbcf6 825 u8 saveAR_INDEX;
a59e122a 826 u8 saveAR[21];
ba8bbcf6 827 u8 saveDACMASK;
a59e122a 828 u8 saveCR[37];
4b9de737 829 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
1fd1c624
EA		 830 u32 saveCURACNTR;
831 u32 saveCURAPOS;
832 u32 saveCURABASE;
833 u32 saveCURBCNTR;
834 u32 saveCURBPOS;
835 u32 saveCURBBASE;
836 u32 saveCURSIZE;
a4fc5ed6
KP		 837 u32 saveDP_B;
838 u32 saveDP_C;
839 u32 saveDP_D;
840 u32 savePIPEA_GMCH_DATA_M;
841 u32 savePIPEB_GMCH_DATA_M;
842 u32 savePIPEA_GMCH_DATA_N;
843 u32 savePIPEB_GMCH_DATA_N;
844 u32 savePIPEA_DP_LINK_M;
845 u32 savePIPEB_DP_LINK_M;
846 u32 savePIPEA_DP_LINK_N;
847 u32 savePIPEB_DP_LINK_N;
42048781
ZW		 848 u32 saveFDI_RXA_CTL;
849 u32 saveFDI_TXA_CTL;
850 u32 saveFDI_RXB_CTL;
851 u32 saveFDI_TXB_CTL;
852 u32 savePFA_CTL_1;
853 u32 savePFB_CTL_1;
854 u32 savePFA_WIN_SZ;
855 u32 savePFB_WIN_SZ;
856 u32 savePFA_WIN_POS;
857 u32 savePFB_WIN_POS;
5586c8bc
ZW		 858 u32 savePCH_DREF_CONTROL;
859 u32 saveDISP_ARB_CTL;
860 u32 savePIPEA_DATA_M1;
861 u32 savePIPEA_DATA_N1;
862 u32 savePIPEA_LINK_M1;
863 u32 savePIPEA_LINK_N1;
864 u32 savePIPEB_DATA_M1;
865 u32 savePIPEB_DATA_N1;
866 u32 savePIPEB_LINK_M1;
867 u32 savePIPEB_LINK_N1;
b5b72e89 868 u32 saveMCHBAR_RENDER_STANDBY;
cda2bb78 869 u32 savePCH_PORT_HOTPLUG;
f4c956ad 870};
c85aa885 871
ddeea5b0
ID		 872struct vlv_s0ix_state {
873 /* GAM */
874 u32 wr_watermark;
875 u32 gfx_prio_ctrl;
876 u32 arb_mode;
877 u32 gfx_pend_tlb0;
878 u32 gfx_pend_tlb1;
879 u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
880 u32 media_max_req_count;
881 u32 gfx_max_req_count;
882 u32 render_hwsp;
883 u32 ecochk;
884 u32 bsd_hwsp;
885 u32 blt_hwsp;
886 u32 tlb_rd_addr;
887
888 /* MBC */
889 u32 g3dctl;
890 u32 gsckgctl;
891 u32 mbctl;
892
893 /* GCP */
894 u32 ucgctl1;
895 u32 ucgctl3;
896 u32 rcgctl1;
897 u32 rcgctl2;
898 u32 rstctl;
899 u32 misccpctl;
900
901 /* GPM */
902 u32 gfxpause;
903 u32 rpdeuhwtc;
904 u32 rpdeuc;
905 u32 ecobus;
906 u32 pwrdwnupctl;
907 u32 rp_down_timeout;
908 u32 rp_deucsw;
909 u32 rcubmabdtmr;
910 u32 rcedata;
911 u32 spare2gh;
912
913 /* Display 1 CZ domain */
914 u32 gt_imr;
915 u32 gt_ier;
916 u32 pm_imr;
917 u32 pm_ier;
918 u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
919
920 /* GT SA CZ domain */
921 u32 tilectl;
922 u32 gt_fifoctl;
923 u32 gtlc_wake_ctrl;
924 u32 gtlc_survive;
925 u32 pmwgicz;
926
927 /* Display 2 CZ domain */
928 u32 gu_ctl0;
929 u32 gu_ctl1;
930 u32 clock_gate_dis2;
931};
932
bf225f20
CW		 933struct intel_rps_ei {
934 u32 cz_clock;
935 u32 render_c0;
936 u32 media_c0;
31685c25
D		 937};
938
c85aa885 939struct intel_gen6_power_mgmt {
59cdb63d 940 /* work and pm_iir are protected by dev_priv->irq_lock */
c85aa885
DV		 941 struct work_struct work;
942 u32 pm_iir;
59cdb63d 943
b39fb297
BW		 944 /* Frequencies are stored in potentially platform dependent multiples.
945 * In other words, *_freq needs to be multiplied by X to be interesting.
946 * Soft limits are those which are used for the dynamic reclocking done
947 * by the driver (raise frequencies under heavy loads, and lower for
948 * lighter loads). Hard limits are those imposed by the hardware.
949 *
950 * A distinction is made for overclocking, which is never enabled by
951 * default, and is considered to be above the hard limit if it's
952 * possible at all.
953 */
954 u8 cur_freq; /* Current frequency (cached, may not == HW) */
955 u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */
956 u8 max_freq_softlimit; /* Max frequency permitted by the driver */
957 u8 max_freq; /* Maximum frequency, RP0 if not overclocking */
958 u8 min_freq; /* AKA RPn. Minimum frequency */
959 u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */
960 u8 rp1_freq; /* "less than" RP0 power/freqency */
961 u8 rp0_freq; /* Non-overclocked max frequency. */
67c3bf6f 962 u32 cz_freq;
1a01ab3b 963
31685c25 964 u32 ei_interrupt_count;
1a01ab3b 965
dd75fdc8
CW		 966 int last_adj;
967 enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
968
c0951f0c 969 bool enabled;
1a01ab3b 970 struct delayed_work delayed_resume_work;
4fc688ce 971
bf225f20
CW		 972 /* manual wa residency calculations */
973 struct intel_rps_ei up_ei, down_ei;
974
4fc688ce
JB		 975 /*
976 * Protects RPS/RC6 register access and PCU communication.
977 * Must be taken after struct_mutex if nested.
978 */
979 struct mutex hw_lock;
c85aa885
DV		 980};
981
1a240d4d
DV		 982/* defined intel_pm.c */
983extern spinlock_t mchdev_lock;
984
c85aa885
DV		 985struct intel_ilk_power_mgmt {
986 u8 cur_delay;
987 u8 min_delay;
988 u8 max_delay;
989 u8 fmax;
990 u8 fstart;
991
992 u64 last_count1;
993 unsigned long last_time1;
994 unsigned long chipset_power;
995 u64 last_count2;
5ed0bdf2 996 u64 last_time2;
c85aa885
DV		 997 unsigned long gfx_power;
998 u8 corr;
999
1000 int c_m;
1001 int r_t;
3e373948
DV		 1002
1003 struct drm_i915_gem_object *pwrctx;
1004 struct drm_i915_gem_object *renderctx;
c85aa885
DV		 1005};
1006
c6cb582e
ID		 1007struct drm_i915_private;
1008struct i915_power_well;
1009
1010struct i915_power_well_ops {
1011 /*
1012 * Synchronize the well's hw state to match the current sw state, for
1013 * example enable/disable it based on the current refcount. Called
1014 * during driver init and resume time, possibly after first calling
1015 * the enable/disable handlers.
1016 */
1017 void (*sync_hw)(struct drm_i915_private *dev_priv,
1018 struct i915_power_well *power_well);
1019 /*
1020 * Enable the well and resources that depend on it (for example
1021 * interrupts located on the well). Called after the 0->1 refcount
1022 * transition.
1023 */
1024 void (*enable)(struct drm_i915_private *dev_priv,
1025 struct i915_power_well *power_well);
1026 /*
1027 * Disable the well and resources that depend on it. Called after
1028 * the 1->0 refcount transition.
1029 */
1030 void (*disable)(struct drm_i915_private *dev_priv,
1031 struct i915_power_well *power_well);
1032 /* Returns the hw enabled state. */
1033 bool (*is_enabled)(struct drm_i915_private *dev_priv,
1034 struct i915_power_well *power_well);
1035};
1036
a38911a3
WX		 1037/* Power well structure for haswell */
1038struct i915_power_well {
c1ca727f 1039 const char *name;
6f3ef5dd 1040 bool always_on;
a38911a3
WX		 1041 /* power well enable/disable usage count */
1042 int count;
bfafe93a
ID		 1043 /* cached hw enabled state */
1044 bool hw_enabled;
c1ca727f 1045 unsigned long domains;
77961eb9 1046 unsigned long data;
c6cb582e 1047 const struct i915_power_well_ops *ops;
a38911a3
WX		 1048};
1049
83c00f55 1050struct i915_power_domains {
baa70707
ID		 1051 /*
1052 * Power wells needed for initialization at driver init and suspend
1053 * time are on. They are kept on until after the first modeset.
1054 */
1055 bool init_power_on;
0d116a29 1056 bool initializing;
c1ca727f 1057 int power_well_count;
baa70707 1058
83c00f55 1059 struct mutex lock;
1da51581 1060 int domain_use_count[POWER_DOMAIN_NUM];
c1ca727f 1061 struct i915_power_well *power_wells;
83c00f55
ID		 1062};
1063
231f42a4
DV		 1064struct i915_dri1_state {
1065 unsigned allow_batchbuffer : 1;
1066 u32 __iomem *gfx_hws_cpu_addr;
1067
1068 unsigned int cpp;
1069 int back_offset;
1070 int front_offset;
1071 int current_page;
1072 int page_flipping;
1073
1074 uint32_t counter;
1075};
1076
db1b76ca
DV		 1077struct i915_ums_state {
1078 /**
1079 * Flag if the X Server, and thus DRM, is not currently in
1080 * control of the device.
1081 *
1082 * This is set between LeaveVT and EnterVT. It needs to be
1083 * replaced with a semaphore. It also needs to be
1084 * transitioned away from for kernel modesetting.
1085 */
1086 int mm_suspended;
1087};
1088
35a85ac6 1089#define MAX_L3_SLICES 2
a4da4fa4 1090struct intel_l3_parity {
35a85ac6 1091 u32 *remap_info[MAX_L3_SLICES];
a4da4fa4 1092 struct work_struct error_work;
35a85ac6 1093 int which_slice;
a4da4fa4
DV		 1094};
1095
4b5aed62 1096struct i915_gem_mm {
4b5aed62
DV		 1097 /** Memory allocator for GTT stolen memory */
1098 struct drm_mm stolen;
4b5aed62
DV		 1099 /** List of all objects in gtt_space. Used to restore gtt
1100 * mappings on resume */
1101 struct list_head bound_list;
1102 /**
1103 * List of objects which are not bound to the GTT (thus
1104 * are idle and not used by the GPU) but still have
1105 * (presumably uncached) pages still attached.
1106 */
1107 struct list_head unbound_list;
1108
1109 /** Usable portion of the GTT for GEM */
1110 unsigned long stolen_base; /* limited to low memory (32-bit) */
1111
4b5aed62
DV		 1112 /** PPGTT used for aliasing the PPGTT with the GTT */
1113 struct i915_hw_ppgtt *aliasing_ppgtt;
1114
2cfcd32a 1115 struct notifier_block oom_notifier;
ceabbba5 1116 struct shrinker shrinker;
4b5aed62
DV		 1117 bool shrinker_no_lock_stealing;
1118
4b5aed62
DV		 1119 /** LRU list of objects with fence regs on them. */
1120 struct list_head fence_list;
1121
1122 /**
1123 * We leave the user IRQ off as much as possible,
1124 * but this means that requests will finish and never
1125 * be retired once the system goes idle. Set a timer to
1126 * fire periodically while the ring is running. When it
1127 * fires, go retire requests.
1128 */
1129 struct delayed_work retire_work;
1130
b29c19b6
CW		 1131 /**
1132 * When we detect an idle GPU, we want to turn on
1133 * powersaving features. So once we see that there
1134 * are no more requests outstanding and no more
1135 * arrive within a small period of time, we fire
1136 * off the idle_work.
1137 */
1138 struct delayed_work idle_work;
1139
4b5aed62
DV		 1140 /**
1141 * Are we in a non-interruptible section of code like
1142 * modesetting?
1143 */
1144 bool interruptible;
1145
f62a0076
CW		 1146 /**
1147 * Is the GPU currently considered idle, or busy executing userspace
1148 * requests? Whilst idle, we attempt to power down the hardware and
1149 * display clocks. In order to reduce the effect on performance, there
1150 * is a slight delay before we do so.
1151 */
1152 bool busy;
1153
bdf1e7e3
DV		 1154 /* the indicator for dispatch video commands on two BSD rings */
1155 int bsd_ring_dispatch_index;
1156
4b5aed62
DV		 1157 /** Bit 6 swizzling required for X tiling */
1158 uint32_t bit_6_swizzle_x;
1159 /** Bit 6 swizzling required for Y tiling */
1160 uint32_t bit_6_swizzle_y;
1161
4b5aed62 1162 /* accounting, useful for userland debugging */
c20e8355 1163 spinlock_t object_stat_lock;
4b5aed62
DV		 1164 size_t object_memory;
1165 u32 object_count;
1166};
1167
edc3d884 1168struct drm_i915_error_state_buf {
0a4cd7c8 1169 struct drm_i915_private *i915;
edc3d884
MK		 1170 unsigned bytes;
1171 unsigned size;
1172 int err;
1173 u8 *buf;
1174 loff_t start;
1175 loff_t pos;
1176};
1177
fc16b48b
MK		 1178struct i915_error_state_file_priv {
1179 struct drm_device *dev;
1180 struct drm_i915_error_state *error;
1181};
1182
99584db3
DV		 1183struct i915_gpu_error {
1184 /* For hangcheck timer */
1185#define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1186#define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
be62acb4
MK		 1187 /* Hang gpu twice in this window and your context gets banned */
1188#define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1189
99584db3 1190 struct timer_list hangcheck_timer;
99584db3
DV		 1191
1192 /* For reset and error_state handling. */
1193 spinlock_t lock;
1194 /* Protected by the above dev->gpu_error.lock. */
1195 struct drm_i915_error_state *first_error;
1196 struct work_struct work;
99584db3 1197
094f9a54
CW		 1198
1199 unsigned long missed_irq_rings;
1200
1f83fee0 1201 /**
2ac0f450 1202 * State variable controlling the reset flow and count
1f83fee0 1203 *
2ac0f450
MK		 1204 * This is a counter which gets incremented when reset is triggered,
1205 * and again when reset has been handled. So odd values (lowest bit set)
1206 * means that reset is in progress and even values that
1207 * (reset_counter >> 1):th reset was successfully completed.
1208 *
1209 * If reset is not completed succesfully, the I915_WEDGE bit is
1210 * set meaning that hardware is terminally sour and there is no
1211 * recovery. All waiters on the reset_queue will be woken when
1212 * that happens.
1213 *
1214 * This counter is used by the wait_seqno code to notice that reset
1215 * event happened and it needs to restart the entire ioctl (since most
1216 * likely the seqno it waited for won't ever signal anytime soon).
f69061be
DV		 1217 *
1218 * This is important for lock-free wait paths, where no contended lock
1219 * naturally enforces the correct ordering between the bail-out of the
1220 * waiter and the gpu reset work code.
1f83fee0
DV		 1221 */
1222 atomic_t reset_counter;
1223
1f83fee0 1224#define I915_RESET_IN_PROGRESS_FLAG 1
2ac0f450 1225#define I915_WEDGED (1 << 31)
1f83fee0
DV		 1226
1227 /**
1228 * Waitqueue to signal when the reset has completed. Used by clients
1229 * that wait for dev_priv->mm.wedged to settle.
1230 */
1231 wait_queue_head_t reset_queue;
33196ded 1232
88b4aa87
MK		 1233 /* Userspace knobs for gpu hang simulation;
1234 * combines both a ring mask, and extra flags
1235 */
1236 u32 stop_rings;
1237#define I915_STOP_RING_ALLOW_BAN (1 << 31)
1238#define I915_STOP_RING_ALLOW_WARN (1 << 30)
094f9a54
CW		 1239
1240 /* For missed irq/seqno simulation. */
1241 unsigned int test_irq_rings;
6689c167
MA		 1242
1243 /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */
1244 bool reload_in_reset;
99584db3
DV		 1245};
1246
b8efb17b
ZR		 1247enum modeset_restore {
1248 MODESET_ON_LID_OPEN,
1249 MODESET_DONE,
1250 MODESET_SUSPENDED,
1251};
1252
6acab15a 1253struct ddi_vbt_port_info {
ce4dd49e
DL		 1254 /*
1255 * This is an index in the HDMI/DVI DDI buffer translation table.
1256 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1257 * populate this field.
1258 */
1259#define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
6acab15a 1260 uint8_t hdmi_level_shift;
311a2094
PZ		 1261
1262 uint8_t supports_dvi:1;
1263 uint8_t supports_hdmi:1;
1264 uint8_t supports_dp:1;
6acab15a
PZ		 1265};
1266
83a7280e
PB		 1267enum drrs_support_type {
1268 DRRS_NOT_SUPPORTED = 0,
1269 STATIC_DRRS_SUPPORT = 1,
1270 SEAMLESS_DRRS_SUPPORT = 2
1271};
1272
41aa3448
RV		 1273struct intel_vbt_data {
1274 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
1275 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
1276
1277 /* Feature bits */
1278 unsigned int int_tv_support:1;
1279 unsigned int lvds_dither:1;
1280 unsigned int lvds_vbt:1;
1281 unsigned int int_crt_support:1;
1282 unsigned int lvds_use_ssc:1;
1283 unsigned int display_clock_mode:1;
1284 unsigned int fdi_rx_polarity_inverted:1;
3e6bd011 1285 unsigned int has_mipi:1;
41aa3448
RV		 1286 int lvds_ssc_freq;
1287 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
1288
83a7280e
PB		 1289 enum drrs_support_type drrs_type;
1290
41aa3448
RV		 1291 /* eDP */
1292 int edp_rate;
1293 int edp_lanes;
1294 int edp_preemphasis;
1295 int edp_vswing;
1296 bool edp_initialized;
1297 bool edp_support;
1298 int edp_bpp;
1299 struct edp_power_seq edp_pps;
1300
f00076d2
JN		 1301 struct {
1302 u16 pwm_freq_hz;
39fbc9c8 1303 bool present;
f00076d2 1304 bool active_low_pwm;
1de6068e 1305 u8 min_brightness; /* min_brightness/255 of max */
f00076d2
JN		 1306 } backlight;
1307
d17c5443
SK		 1308 /* MIPI DSI */
1309 struct {
3e6bd011 1310 u16 port;
d17c5443 1311 u16 panel_id;
d3b542fc
SK		 1312 struct mipi_config *config;
1313 struct mipi_pps_data *pps;
1314 u8 seq_version;
1315 u32 size;
1316 u8 *data;
1317 u8 *sequence[MIPI_SEQ_MAX];
d17c5443
SK		 1318 } dsi;
1319
41aa3448
RV		 1320 int crt_ddc_pin;
1321
1322 int child_dev_num;
768f69c9 1323 union child_device_config *child_dev;
6acab15a
PZ		 1324
1325 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
41aa3448
RV		 1326};
1327
77c122bc
VS		 1328enum intel_ddb_partitioning {
1329 INTEL_DDB_PART_1_2,
1330 INTEL_DDB_PART_5_6, /* IVB+ */
1331};
1332
1fd527cc
VS		 1333struct intel_wm_level {
1334 bool enable;
1335 uint32_t pri_val;
1336 uint32_t spr_val;
1337 uint32_t cur_val;
1338 uint32_t fbc_val;
1339};
1340
820c1980 1341struct ilk_wm_values {
609cedef
VS		 1342 uint32_t wm_pipe[3];
1343 uint32_t wm_lp[3];
1344 uint32_t wm_lp_spr[3];
1345 uint32_t wm_linetime[3];
1346 bool enable_fbc_wm;
1347 enum intel_ddb_partitioning partitioning;
1348};
1349
c67a470b 1350/*
765dab67
PZ		 1351 * This struct helps tracking the state needed for runtime PM, which puts the
1352 * device in PCI D3 state. Notice that when this happens, nothing on the
1353 * graphics device works, even register access, so we don't get interrupts nor
1354 * anything else.
c67a470b 1355 *
765dab67
PZ		 1356 * Every piece of our code that needs to actually touch the hardware needs to
1357 * either call intel_runtime_pm_get or call intel_display_power_get with the
1358 * appropriate power domain.
a8a8bd54 1359 *
765dab67
PZ		 1360 * Our driver uses the autosuspend delay feature, which means we'll only really
1361 * suspend if we stay with zero refcount for a certain amount of time. The
1362 * default value is currently very conservative (see intel_init_runtime_pm), but
1363 * it can be changed with the standard runtime PM files from sysfs.
c67a470b
PZ		 1364 *
1365 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1366 * goes back to false exactly before we reenable the IRQs. We use this variable
1367 * to check if someone is trying to enable/disable IRQs while they're supposed
1368 * to be disabled. This shouldn't happen and we'll print some error messages in
730488b2 1369 * case it happens.
c67a470b 1370 *
765dab67 1371 * For more, read the Documentation/power/runtime_pm.txt.
c67a470b 1372 */
5d584b2e
PZ		 1373struct i915_runtime_pm {
1374 bool suspended;
9df7575f 1375 bool _irqs_disabled;
c67a470b
PZ		 1376};
1377
926321d5
DV		 1378enum intel_pipe_crc_source {
1379 INTEL_PIPE_CRC_SOURCE_NONE,
1380 INTEL_PIPE_CRC_SOURCE_PLANE1,
1381 INTEL_PIPE_CRC_SOURCE_PLANE2,
1382 INTEL_PIPE_CRC_SOURCE_PF,
5b3a856b 1383 INTEL_PIPE_CRC_SOURCE_PIPE,
3d099a05
DV		 1384 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1385 INTEL_PIPE_CRC_SOURCE_TV,
1386 INTEL_PIPE_CRC_SOURCE_DP_B,
1387 INTEL_PIPE_CRC_SOURCE_DP_C,
1388 INTEL_PIPE_CRC_SOURCE_DP_D,
46a19188 1389 INTEL_PIPE_CRC_SOURCE_AUTO,
926321d5
DV		 1390 INTEL_PIPE_CRC_SOURCE_MAX,
1391};
1392
8bf1e9f1 1393struct intel_pipe_crc_entry {
ac2300d4 1394 uint32_t frame;
8bf1e9f1
SH		 1395 uint32_t crc[5];
1396};
1397
b2c88f5b 1398#define INTEL_PIPE_CRC_ENTRIES_NR 128
8bf1e9f1 1399struct intel_pipe_crc {
d538bbdf
DL		 1400 spinlock_t lock;
1401 bool opened; /* exclusive access to the result file */
e5f75aca 1402 struct intel_pipe_crc_entry *entries;
926321d5 1403 enum intel_pipe_crc_source source;
d538bbdf 1404 int head, tail;
07144428 1405 wait_queue_head_t wq;
8bf1e9f1
SH		 1406};
1407
f99d7069
DV		 1408struct i915_frontbuffer_tracking {
1409 struct mutex lock;
1410
1411 /*
1412 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1413 * scheduled flips.
1414 */
1415 unsigned busy_bits;
1416 unsigned flip_bits;
1417};
1418
77fec556 1419struct drm_i915_private {
f4c956ad 1420 struct drm_device *dev;
42dcedd4 1421 struct kmem_cache *slab;
f4c956ad 1422
5c969aa7 1423 const struct intel_device_info info;
f4c956ad
DV		 1424
1425 int relative_constants_mode;
1426
1427 void __iomem *regs;
1428
907b28c5 1429 struct intel_uncore uncore;
f4c956ad
DV		 1430
1431 struct intel_gmbus gmbus[GMBUS_NUM_PORTS];
1432
28c70f16 1433
f4c956ad
DV		 1434 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1435 * controller on different i2c buses. */
1436 struct mutex gmbus_mutex;
1437
1438 /**
1439 * Base address of the gmbus and gpio block.
1440 */
1441 uint32_t gpio_mmio_base;
1442
b6fdd0f2
SS		 1443 /* MMIO base address for MIPI regs */
1444 uint32_t mipi_mmio_base;
1445
28c70f16
DV		 1446 wait_queue_head_t gmbus_wait_queue;
1447
f4c956ad 1448 struct pci_dev *bridge_dev;
a4872ba6 1449 struct intel_engine_cs ring[I915_NUM_RINGS];
3e78998a 1450 struct drm_i915_gem_object *semaphore_obj;
f72b3435 1451 uint32_t last_seqno, next_seqno;
f4c956ad
DV		 1452
1453 drm_dma_handle_t *status_page_dmah;
f4c956ad
DV		 1454 struct resource mch_res;
1455
f4c956ad
DV		 1456 /* protects the irq masks */
1457 spinlock_t irq_lock;
1458
84c33a64
SG		 1459 /* protects the mmio flip data */
1460 spinlock_t mmio_flip_lock;
1461
f8b79e58
ID		 1462 bool display_irqs_enabled;
1463
9ee32fea
DV		 1464 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1465 struct pm_qos_request pm_qos;
1466
f4c956ad 1467 /* DPIO indirect register protection */
09153000 1468 struct mutex dpio_lock;
f4c956ad
DV		 1469
1470 /** Cached value of IMR to avoid reads in updating the bitfield */
abd58f01
BW		 1471 union {
1472 u32 irq_mask;
1473 u32 de_irq_mask[I915_MAX_PIPES];
1474 };
f4c956ad 1475 u32 gt_irq_mask;
605cd25b 1476 u32 pm_irq_mask;
a6706b45 1477 u32 pm_rps_events;
91d181dd 1478 u32 pipestat_irq_mask[I915_MAX_PIPES];
f4c956ad 1479
f4c956ad 1480 struct work_struct hotplug_work;
b543fb04
EE		 1481 struct {
1482 unsigned long hpd_last_jiffies;
1483 int hpd_cnt;
1484 enum {
1485 HPD_ENABLED = 0,
1486 HPD_DISABLED = 1,
1487 HPD_MARK_DISABLED = 2
1488 } hpd_mark;
1489 } hpd_stats[HPD_NUM_PINS];
142e2398 1490 u32 hpd_event_bits;
6323751d 1491 struct delayed_work hotplug_reenable_work;
f4c956ad 1492
5c3fe8b0 1493 struct i915_fbc fbc;
439d7ac0 1494 struct i915_drrs drrs;
f4c956ad 1495 struct intel_opregion opregion;
41aa3448 1496 struct intel_vbt_data vbt;
f4c956ad
DV		 1497
1498 /* overlay */
1499 struct intel_overlay *overlay;
f4c956ad 1500
58c68779
JN		 1501 /* backlight registers and fields in struct intel_panel */
1502 spinlock_t backlight_lock;
31ad8ec6 1503
f4c956ad 1504 /* LVDS info */
f4c956ad
DV		 1505 bool no_aux_handshake;
1506
f4c956ad
DV		 1507 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
1508 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
1509 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
1510
1511 unsigned int fsb_freq, mem_freq, is_ddr3;
d60c4473 1512 unsigned int vlv_cdclk_freq;
f4c956ad 1513
645416f5
DV		 1514 /**
1515 * wq - Driver workqueue for GEM.
1516 *
1517 * NOTE: Work items scheduled here are not allowed to grab any modeset
1518 * locks, for otherwise the flushing done in the pageflip code will
1519 * result in deadlocks.
1520 */
f4c956ad
DV		 1521 struct workqueue_struct *wq;
1522
1523 /* Display functions */
1524 struct drm_i915_display_funcs display;
1525
1526 /* PCH chipset type */
1527 enum intel_pch pch_type;
17a303ec 1528 unsigned short pch_id;
f4c956ad
DV		 1529
1530 unsigned long quirks;
1531
b8efb17b
ZR		 1532 enum modeset_restore modeset_restore;
1533 struct mutex modeset_restore_lock;
673a394b 1534
a7bbbd63 1535 struct list_head vm_list; /* Global list of all address spaces */
0260c420 1536 struct i915_gtt gtt; /* VM representing the global address space */
5d4545ae 1537
4b5aed62 1538 struct i915_gem_mm mm;
5cc9ed4b
CW		 1539#if defined(CONFIG_MMU_NOTIFIER)
1540 DECLARE_HASHTABLE(mmu_notifiers, 7);
1541#endif
8781342d 1542
8781342d
DV		 1543 /* Kernel Modesetting */
1544
9b9d172d 1545 struct sdvo_device_mapping sdvo_mappings[2];
652c393a 1546
76c4ac04
DL		 1547 struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
1548 struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
6b95a207
KH		 1549 wait_queue_head_t pending_flip_queue;
1550
c4597872
DV		 1551#ifdef CONFIG_DEBUG_FS
1552 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
1553#endif
1554
e72f9fbf
DV		 1555 int num_shared_dpll;
1556 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
e4607fcf 1557 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
ee7b9f93 1558
652c393a
JB		 1559 /* Reclocking support */
1560 bool render_reclock_avail;
1561 bool lvds_downclock_avail;
18f9ed12
ZY		 1562 /* indicates the reduced downclock for LVDS*/
1563 int lvds_downclock;
f99d7069
DV		 1564
1565 struct i915_frontbuffer_tracking fb_tracking;
1566
652c393a 1567 u16 orig_clock;
f97108d1 1568
c4804411 1569 bool mchbar_need_disable;
f97108d1 1570
a4da4fa4
DV		 1571 struct intel_l3_parity l3_parity;
1572
59124506
BW		 1573 /* Cannot be determined by PCIID. You must always read a register. */
1574 size_t ellc_size;
1575
c6a828d3 1576 /* gen6+ rps state */
c85aa885 1577 struct intel_gen6_power_mgmt rps;
c6a828d3 1578
20e4d407
DV		 1579 /* ilk-only ips/rps state. Everything in here is protected by the global
1580 * mchdev_lock in intel_pm.c */
c85aa885 1581 struct intel_ilk_power_mgmt ips;
b5e50c3f 1582
83c00f55 1583 struct i915_power_domains power_domains;
a38911a3 1584
a031d709 1585 struct i915_psr psr;
3f51e471 1586
99584db3 1587 struct i915_gpu_error gpu_error;
ae681d96 1588
c9cddffc
JB		 1589 struct drm_i915_gem_object *vlv_pctx;
1590
4520f53a 1591#ifdef CONFIG_DRM_I915_FBDEV
8be48d92
DA		 1592 /* list of fbdev register on this device */
1593 struct intel_fbdev *fbdev;
82e3b8c1 1594 struct work_struct fbdev_suspend_work;
4520f53a 1595#endif
e953fd7b
CW		 1596
1597 struct drm_property *broadcast_rgb_property;
3f43c48d 1598 struct drm_property *force_audio_property;
e3689190 1599
254f965c 1600 uint32_t hw_context_size;
a33afea5 1601 struct list_head context_list;
f4c956ad 1602
3e68320e 1603 u32 fdi_rx_config;
68d18ad7 1604
842f1c8b 1605 u32 suspend_count;
f4c956ad 1606 struct i915_suspend_saved_registers regfile;
ddeea5b0 1607 struct vlv_s0ix_state vlv_s0ix_state;
231f42a4 1608
53615a5e
VS		 1609 struct {
1610 /*
1611 * Raw watermark latency values:
1612 * in 0.1us units for WM0,
1613 * in 0.5us units for WM1+.
1614 */
1615 /* primary */
1616 uint16_t pri_latency[5];
1617 /* sprite */
1618 uint16_t spr_latency[5];
1619 /* cursor */
1620 uint16_t cur_latency[5];
609cedef
VS		 1621
1622 /* current hardware state */
820c1980 1623 struct ilk_wm_values hw;
53615a5e
VS		 1624 } wm;
1625
8a187455
PZ		 1626 struct i915_runtime_pm pm;
1627
13cf5504
DA		 1628 struct intel_digital_port *hpd_irq_port[I915_MAX_PORTS];
1629 u32 long_hpd_port_mask;
1630 u32 short_hpd_port_mask;
1631 struct work_struct dig_port_work;
1632
0e32b39c
DA		 1633 /*
1634 * if we get a HPD irq from DP and a HPD irq from non-DP
1635 * the non-DP HPD could block the workqueue on a mode config
1636 * mutex getting, that userspace may have taken. However
1637 * userspace is waiting on the DP workqueue to run which is
1638 * blocked behind the non-DP one.
1639 */
1640 struct workqueue_struct *dp_wq;
1641
231f42a4
DV		 1642 /* Old dri1 support infrastructure, beware the dragons ya fools entering
1643 * here! */
1644 struct i915_dri1_state dri1;
db1b76ca
DV		 1645 /* Old ums support infrastructure, same warning applies. */
1646 struct i915_ums_state ums;
bdf1e7e3 1647
a83014d3
OM		 1648 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
1649 struct {
1650 int (*do_execbuf)(struct drm_device *dev, struct drm_file *file,
1651 struct intel_engine_cs *ring,
1652 struct intel_context *ctx,
1653 struct drm_i915_gem_execbuffer2 *args,
1654 struct list_head *vmas,
1655 struct drm_i915_gem_object *batch_obj,
1656 u64 exec_start, u32 flags);
1657 int (*init_rings)(struct drm_device *dev);
1658 void (*cleanup_ring)(struct intel_engine_cs *ring);
1659 void (*stop_ring)(struct intel_engine_cs *ring);
1660 } gt;
1661
bdf1e7e3
DV		 1662 /*
1663 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
1664 * will be rejected. Instead look for a better place.
1665 */
77fec556 1666};
1da177e4 1667
2c1792a1
CW		 1668static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
1669{
1670 return dev->dev_private;
1671}
1672
b4519513
CW		 1673/* Iterate over initialised rings */
1674#define for_each_ring(ring__, dev_priv__, i__) \
1675 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
1676 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
1677
b1d7e4b4
WF		 1678enum hdmi_force_audio {
1679 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
1680 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
1681 HDMI_AUDIO_AUTO, /* trust EDID */
1682 HDMI_AUDIO_ON, /* force turn on HDMI audio */
1683};
1684
190d6cd5 1685#define I915_GTT_OFFSET_NONE ((u32)-1)
ed2f3452 1686
37e680a1
CW		 1687struct drm_i915_gem_object_ops {
1688 /* Interface between the GEM object and its backing storage.
1689 * get_pages() is called once prior to the use of the associated set
1690 * of pages before to binding them into the GTT, and put_pages() is
1691 * called after we no longer need them. As we expect there to be
1692 * associated cost with migrating pages between the backing storage
1693 * and making them available for the GPU (e.g. clflush), we may hold
1694 * onto the pages after they are no longer referenced by the GPU
1695 * in case they may be used again shortly (for example migrating the
1696 * pages to a different memory domain within the GTT). put_pages()
1697 * will therefore most likely be called when the object itself is
1698 * being released or under memory pressure (where we attempt to
1699 * reap pages for the shrinker).
1700 */
1701 int (*get_pages)(struct drm_i915_gem_object *);
1702 void (*put_pages)(struct drm_i915_gem_object *);
5cc9ed4b
CW		 1703 int (*dmabuf_export)(struct drm_i915_gem_object *);
1704 void (*release)(struct drm_i915_gem_object *);
37e680a1
CW		 1705};
1706
a071fa00
DV		 1707/*
1708 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
1709 * considered to be the frontbuffer for the given plane interface-vise. This
1710 * doesn't mean that the hw necessarily already scans it out, but that any
1711 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
1712 *
1713 * We have one bit per pipe and per scanout plane type.
1714 */
1715#define INTEL_FRONTBUFFER_BITS_PER_PIPE 4
1716#define INTEL_FRONTBUFFER_BITS \
1717 (INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES)
1718#define INTEL_FRONTBUFFER_PRIMARY(pipe) \
1719 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
1720#define INTEL_FRONTBUFFER_CURSOR(pipe) \
1721 (1 << (1 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
1722#define INTEL_FRONTBUFFER_SPRITE(pipe) \
1723 (1 << (2 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
1724#define INTEL_FRONTBUFFER_OVERLAY(pipe) \
1725 (1 << (3 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
cc36513c
DV		 1726#define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
1727 (0xf << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
a071fa00 1728
673a394b 1729struct drm_i915_gem_object {
c397b908 1730 struct drm_gem_object base;
673a394b 1731
37e680a1
CW		 1732 const struct drm_i915_gem_object_ops *ops;
1733
2f633156
BW		 1734 /** List of VMAs backed by this object */
1735 struct list_head vma_list;
1736
c1ad11fc
CW		 1737 /** Stolen memory for this object, instead of being backed by shmem. */
1738 struct drm_mm_node *stolen;
35c20a60 1739 struct list_head global_list;
673a394b 1740
69dc4987 1741 struct list_head ring_list;
b25cb2f8
BW		 1742 /** Used in execbuf to temporarily hold a ref */
1743 struct list_head obj_exec_link;
673a394b
EA		 1744
1745 /**
65ce3027
CW		 1746 * This is set if the object is on the active lists (has pending
1747 * rendering and so a non-zero seqno), and is not set if it i s on
1748 * inactive (ready to be unbound) list.
673a394b 1749 */
0206e353 1750 unsigned int active:1;
673a394b
EA		 1751
1752 /**
1753 * This is set if the object has been written to since last bound
1754 * to the GTT
1755 */
0206e353 1756 unsigned int dirty:1;
778c3544
DV		 1757
1758 /**
1759 * Fence register bits (if any) for this object. Will be set
1760 * as needed when mapped into the GTT.
1761 * Protected by dev->struct_mutex.
778c3544 1762 */
4b9de737 1763 signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
778c3544 1764
778c3544
DV		 1765 /**
1766 * Advice: are the backing pages purgeable?
1767 */
0206e353 1768 unsigned int madv:2;
778c3544 1769
778c3544
DV		 1770 /**
1771 * Current tiling mode for the object.
1772 */
0206e353 1773 unsigned int tiling_mode:2;
5d82e3e6
CW		 1774 /**
1775 * Whether the tiling parameters for the currently associated fence
1776 * register have changed. Note that for the purposes of tracking
1777 * tiling changes we also treat the unfenced register, the register
1778 * slot that the object occupies whilst it executes a fenced
1779 * command (such as BLT on gen2/3), as a "fence".
1780 */
1781 unsigned int fence_dirty:1;
778c3544 1782
75e9e915
DV		 1783 /**
1784 * Is the object at the current location in the gtt mappable and
1785 * fenceable? Used to avoid costly recalculations.
1786 */
0206e353 1787 unsigned int map_and_fenceable:1;
75e9e915 1788
fb7d516a
DV		 1789 /**
1790 * Whether the current gtt mapping needs to be mappable (and isn't just
1791 * mappable by accident). Track pin and fault separate for a more
1792 * accurate mappable working set.
1793 */
0206e353
AJ		 1794 unsigned int fault_mappable:1;
1795 unsigned int pin_mappable:1;
cc98b413 1796 unsigned int pin_display:1;
fb7d516a 1797
24f3a8cf
AG		 1798 /*
1799 * Is the object to be mapped as read-only to the GPU
1800 * Only honoured if hardware has relevant pte bit
1801 */
1802 unsigned long gt_ro:1;
651d794f 1803 unsigned int cache_level:3;
93dfb40c 1804
7bddb01f 1805 unsigned int has_aliasing_ppgtt_mapping:1;
74898d7e 1806 unsigned int has_global_gtt_mapping:1;
9da3da66 1807 unsigned int has_dma_mapping:1;
7bddb01f 1808
a071fa00
DV		 1809 unsigned int frontbuffer_bits:INTEL_FRONTBUFFER_BITS;
1810
9da3da66 1811 struct sg_table *pages;
a5570178 1812 int pages_pin_count;
673a394b 1813
1286ff73 1814 /* prime dma-buf support */
9a70cc2a
DA		 1815 void *dma_buf_vmapping;
1816 int vmapping_count;
1817
a4872ba6 1818 struct intel_engine_cs *ring;
caea7476 1819
1c293ea3 1820 /** Breadcrumb of last rendering to the buffer. */
0201f1ec
CW		 1821 uint32_t last_read_seqno;
1822 uint32_t last_write_seqno;
caea7476
CW		 1823 /** Breadcrumb of last fenced GPU access to the buffer. */
1824 uint32_t last_fenced_seqno;
673a394b 1825
778c3544 1826 /** Current tiling stride for the object, if it's tiled. */
de151cf6 1827 uint32_t stride;
673a394b 1828
80075d49
DV		 1829 /** References from framebuffers, locks out tiling changes. */
1830 unsigned long framebuffer_references;
1831
280b713b 1832 /** Record of address bit 17 of each page at last unbind. */
d312ec25 1833 unsigned long *bit_17;
280b713b 1834
79e53945 1835 /** User space pin count and filp owning the pin */
aa5f8021 1836 unsigned long user_pin_count;
79e53945 1837 struct drm_file *pin_filp;
71acb5eb
DA		 1838
1839 /** for phy allocated objects */
00731155 1840 drm_dma_handle_t *phys_handle;
673a394b 1841
5cc9ed4b
CW		 1842 union {
1843 struct i915_gem_userptr {
1844 uintptr_t ptr;
1845 unsigned read_only :1;
1846 unsigned workers :4;
1847#define I915_GEM_USERPTR_MAX_WORKERS 15
1848
1849 struct mm_struct *mm;
1850 struct i915_mmu_object *mn;
1851 struct work_struct *work;
1852 } userptr;
1853 };
1854};
62b8b215 1855#define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
23010e43 1856
a071fa00
DV		 1857void i915_gem_track_fb(struct drm_i915_gem_object *old,
1858 struct drm_i915_gem_object *new,
1859 unsigned frontbuffer_bits);
1860
673a394b
EA		 1861/**
1862 * Request queue structure.
1863 *
1864 * The request queue allows us to note sequence numbers that have been emitted
1865 * and may be associated with active buffers to be retired.
1866 *
1867 * By keeping this list, we can avoid having to do questionable
1868 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
1869 * an emission time with seqnos for tracking how far ahead of the GPU we are.
1870 */
1871struct drm_i915_gem_request {
852835f3 1872 /** On Which ring this request was generated */
a4872ba6 1873 struct intel_engine_cs *ring;
852835f3 1874
673a394b
EA		 1875 /** GEM sequence number associated with this request. */
1876 uint32_t seqno;
1877
7d736f4f
MK		 1878 /** Position in the ringbuffer of the start of the request */
1879 u32 head;
1880
1881 /** Position in the ringbuffer of the end of the request */
a71d8d94
CW		 1882 u32 tail;
1883
0e50e96b 1884 /** Context related to this request */
273497e5 1885 struct intel_context *ctx;
0e50e96b 1886
7d736f4f
MK		 1887 /** Batch buffer related to this request if any */
1888 struct drm_i915_gem_object *batch_obj;
1889
673a394b
EA		 1890 /** Time at which this request was emitted, in jiffies. */
1891 unsigned long emitted_jiffies;
1892
b962442e 1893 /** global list entry for this request */
673a394b 1894 struct list_head list;
b962442e 1895
f787a5f5 1896 struct drm_i915_file_private *file_priv;
b962442e
EA		 1897 /** file_priv list entry for this request */
1898 struct list_head client_list;
673a394b
EA		 1899};
1900
1901struct drm_i915_file_private {
b29c19b6 1902 struct drm_i915_private *dev_priv;
ab0e7ff9 1903 struct drm_file *file;
b29c19b6 1904
673a394b 1905 struct {
99057c81 1906 spinlock_t lock;
b962442e 1907 struct list_head request_list;
b29c19b6 1908 struct delayed_work idle_work;
673a394b 1909 } mm;
40521054 1910 struct idr context_idr;
e59ec13d 1911
b29c19b6 1912 atomic_t rps_wait_boost;
a4872ba6 1913 struct intel_engine_cs *bsd_ring;
673a394b
EA		 1914};
1915
351e3db2
BV		 1916/*
1917 * A command that requires special handling by the command parser.
1918 */
1919struct drm_i915_cmd_descriptor {
1920 /*
1921 * Flags describing how the command parser processes the command.
1922 *
1923 * CMD_DESC_FIXED: The command has a fixed length if this is set,
1924 * a length mask if not set
1925 * CMD_DESC_SKIP: The command is allowed but does not follow the
1926 * standard length encoding for the opcode range in
1927 * which it falls
1928 * CMD_DESC_REJECT: The command is never allowed
1929 * CMD_DESC_REGISTER: The command should be checked against the
1930 * register whitelist for the appropriate ring
1931 * CMD_DESC_MASTER: The command is allowed if the submitting process
1932 * is the DRM master
1933 */
1934 u32 flags;
1935#define CMD_DESC_FIXED (1<<0)
1936#define CMD_DESC_SKIP (1<<1)
1937#define CMD_DESC_REJECT (1<<2)
1938#define CMD_DESC_REGISTER (1<<3)
1939#define CMD_DESC_BITMASK (1<<4)
1940#define CMD_DESC_MASTER (1<<5)
1941
1942 /*
1943 * The command's unique identification bits and the bitmask to get them.
1944 * This isn't strictly the opcode field as defined in the spec and may
1945 * also include type, subtype, and/or subop fields.
1946 */
1947 struct {
1948 u32 value;
1949 u32 mask;
1950 } cmd;
1951
1952 /*
1953 * The command's length. The command is either fixed length (i.e. does
1954 * not include a length field) or has a length field mask. The flag
1955 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
1956 * a length mask. All command entries in a command table must include
1957 * length information.
1958 */
1959 union {
1960 u32 fixed;
1961 u32 mask;
1962 } length;
1963
1964 /*
1965 * Describes where to find a register address in the command to check
1966 * against the ring's register whitelist. Only valid if flags has the
1967 * CMD_DESC_REGISTER bit set.
1968 */
1969 struct {
1970 u32 offset;
1971 u32 mask;
1972 } reg;
1973
1974#define MAX_CMD_DESC_BITMASKS 3
1975 /*
1976 * Describes command checks where a particular dword is masked and
1977 * compared against an expected value. If the command does not match
1978 * the expected value, the parser rejects it. Only valid if flags has
1979 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
1980 * are valid.
d4d48035
BV		 1981 *
1982 * If the check specifies a non-zero condition_mask then the parser
1983 * only performs the check when the bits specified by condition_mask
1984 * are non-zero.
351e3db2
BV		 1985 */
1986 struct {
1987 u32 offset;
1988 u32 mask;
1989 u32 expected;
d4d48035
BV		 1990 u32 condition_offset;
1991 u32 condition_mask;
351e3db2
BV		 1992 } bits[MAX_CMD_DESC_BITMASKS];
1993};
1994
1995/*
1996 * A table of commands requiring special handling by the command parser.
1997 *
1998 * Each ring has an array of tables. Each table consists of an array of command
1999 * descriptors, which must be sorted with command opcodes in ascending order.
2000 */
2001struct drm_i915_cmd_table {
2002 const struct drm_i915_cmd_descriptor *table;
2003 int count;
2004};
2005
dbbe9127 2006/* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */
7312e2dd
CW		 2007#define __I915__(p) ({ \
2008 struct drm_i915_private *__p; \
2009 if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \
2010 __p = (struct drm_i915_private *)p; \
2011 else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \
2012 __p = to_i915((struct drm_device *)p); \
2013 else \
2014 BUILD_BUG(); \
2015 __p; \
2016})
dbbe9127 2017#define INTEL_INFO(p) (&__I915__(p)->info)
87f1f465 2018#define INTEL_DEVID(p) (INTEL_INFO(p)->device_id)
cae5852d 2019
87f1f465
CW		 2020#define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577)
2021#define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562)
cae5852d 2022#define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
87f1f465 2023#define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572)
cae5852d 2024#define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
87f1f465
CW		 2025#define IS_I915GM(dev) (INTEL_DEVID(dev) == 0x2592)
2026#define IS_I945G(dev) (INTEL_DEVID(dev) == 0x2772)
cae5852d
ZN		 2027#define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
2028#define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
2029#define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
87f1f465 2030#define IS_GM45(dev) (INTEL_DEVID(dev) == 0x2A42)
cae5852d 2031#define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
87f1f465
CW		 2032#define IS_PINEVIEW_G(dev) (INTEL_DEVID(dev) == 0xa001)
2033#define IS_PINEVIEW_M(dev) (INTEL_DEVID(dev) == 0xa011)
cae5852d
ZN		 2034#define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
2035#define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
87f1f465 2036#define IS_IRONLAKE_M(dev) (INTEL_DEVID(dev) == 0x0046)
4b65177b 2037#define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
87f1f465
CW		 2038#define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 || \
2039 INTEL_DEVID(dev) == 0x0152 || \
2040 INTEL_DEVID(dev) == 0x015a)
2041#define IS_SNB_GT1(dev) (INTEL_DEVID(dev) == 0x0102 || \
2042 INTEL_DEVID(dev) == 0x0106 || \
2043 INTEL_DEVID(dev) == 0x010A)
70a3eb7a 2044#define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
6df4027b 2045#define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
4cae9ae0 2046#define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
8179f1f0 2047#define IS_BROADWELL(dev) (!INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
cae5852d 2048#define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
ed1c9e2c 2049#define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
87f1f465 2050 (INTEL_DEVID(dev) & 0xFF00) == 0x0C00)
5dd8c4c3 2051#define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \
87f1f465
CW		 2052 ((INTEL_DEVID(dev) & 0xf) == 0x2 || \
2053 (INTEL_DEVID(dev) & 0xf) == 0x6 || \
2054 (INTEL_DEVID(dev) & 0xf) == 0xe))
5dd8c4c3 2055#define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \
87f1f465 2056 (INTEL_DEVID(dev) & 0xFF00) == 0x0A00)
5dd8c4c3 2057#define IS_ULT(dev) (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
9435373e 2058#define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
87f1f465 2059 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
9bbfd20a 2060/* ULX machines are also considered ULT. */
87f1f465
CW		 2061#define IS_HSW_ULX(dev) (INTEL_DEVID(dev) == 0x0A0E || \
2062 INTEL_DEVID(dev) == 0x0A1E)
b833d685 2063#define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
cae5852d 2064
85436696
JB		 2065/*
2066 * The genX designation typically refers to the render engine, so render
2067 * capability related checks should use IS_GEN, while display and other checks
2068 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2069 * chips, etc.).
2070 */
cae5852d
ZN		 2071#define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
2072#define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
2073#define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
2074#define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
2075#define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
85436696 2076#define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
d2980845 2077#define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8)
cae5852d 2078
73ae478c
BW		 2079#define RENDER_RING (1<<RCS)
2080#define BSD_RING (1<<VCS)
2081#define BLT_RING (1<<BCS)
2082#define VEBOX_RING (1<<VECS)
845f74a7 2083#define BSD2_RING (1<<VCS2)
63c42e56 2084#define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING)
845f74a7 2085#define HAS_BSD2(dev) (INTEL_INFO(dev)->ring_mask & BSD2_RING)
63c42e56
BW		 2086#define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING)
2087#define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING)
2088#define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
2089#define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
2090 to_i915(dev)->ellc_size)
cae5852d
ZN		 2091#define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
2092
254f965c 2093#define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
d7f621e5 2094#define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 8)
7365fb78
JB		 2095#define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >= 6)
2096#define HAS_PPGTT(dev) (INTEL_INFO(dev)->gen >= 7 && !IS_GEN8(dev))
692ef70c
JB		 2097#define USES_PPGTT(dev) (i915.enable_ppgtt)
2098#define USES_FULL_PPGTT(dev) (i915.enable_ppgtt == 2)
1d2a314c 2099
05394f39 2100#define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
cae5852d
ZN		 2101#define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
2102
b45305fc
DV		 2103/* Early gen2 have a totally busted CS tlb and require pinned batches. */
2104#define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
4e6b788c
DV		 2105/*
2106 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2107 * even when in MSI mode. This results in spurious interrupt warnings if the
2108 * legacy irq no. is shared with another device. The kernel then disables that
2109 * interrupt source and so prevents the other device from working properly.
2110 */
2111#define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2112#define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
b45305fc 2113
cae5852d
ZN		 2114/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2115 * rows, which changed the alignment requirements and fence programming.
2116 */
2117#define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
2118 IS_I915GM(dev)))
2119#define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
2120#define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
2121#define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
cae5852d
ZN		 2122#define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
2123#define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
cae5852d
ZN		 2124
2125#define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
2126#define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
3a77c4c4 2127#define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
cae5852d 2128
2a114cc1 2129#define HAS_IPS(dev) (IS_ULT(dev) || IS_BROADWELL(dev))
f5adf94e 2130
dd93be58 2131#define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
30568c45 2132#define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
ed8546ac 2133#define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev))
6157d3c8 2134#define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \
fd7f8cce 2135 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev))
affa9354 2136
17a303ec
PZ		 2137#define INTEL_PCH_DEVICE_ID_MASK 0xff00
2138#define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2139#define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2140#define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2141#define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2142#define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
2143
2c1792a1 2144#define INTEL_PCH_TYPE(dev) (to_i915(dev)->pch_type)
eb877ebf 2145#define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
cae5852d
ZN		 2146#define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
2147#define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
40c7ead9 2148#define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
45e6e3a1 2149#define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
cae5852d 2150
5fafe292
SJ		 2151#define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev))
2152
040d2baa
BW		 2153/* DPF == dynamic parity feature */
2154#define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
2155#define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
e1ef7cc2 2156
c8735b0c
BW		 2157#define GT_FREQUENCY_MULTIPLIER 50
2158
05394f39
CW		 2159#include "i915_trace.h"
2160
baa70943 2161extern const struct drm_ioctl_desc i915_ioctls[];
b3a83639
DA		 2162extern int i915_max_ioctl;
2163
6a9ee8af
DA		 2164extern int i915_suspend(struct drm_device *dev, pm_message_t state);
2165extern int i915_resume(struct drm_device *dev);
7c1c2871
DA		 2166extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
2167extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
2168
d330a953
JN		 2169/* i915_params.c */
2170struct i915_params {
2171 int modeset;
2172 int panel_ignore_lid;
2173 unsigned int powersave;
2174 int semaphores;
2175 unsigned int lvds_downclock;
2176 int lvds_channel_mode;
2177 int panel_use_ssc;
2178 int vbt_sdvo_panel_type;
2179 int enable_rc6;
2180 int enable_fbc;
d330a953 2181 int enable_ppgtt;
127f1003 2182 int enable_execlists;
d330a953
JN		 2183 int enable_psr;
2184 unsigned int preliminary_hw_support;
2185 int disable_power_well;
2186 int enable_ips;
e5aa6541 2187 int invert_brightness;
351e3db2 2188 int enable_cmd_parser;
e5aa6541
DL		 2189 /* leave bools at the end to not create holes */
2190 bool enable_hangcheck;
2191 bool fastboot;
d330a953
JN		 2192 bool prefault_disable;
2193 bool reset;
a0bae57f 2194 bool disable_display;
7a10dfa6 2195 bool disable_vtd_wa;
84c33a64 2196 int use_mmio_flip;
5978118c 2197 bool mmio_debug;
d330a953
JN		 2198};
2199extern struct i915_params i915 __read_mostly;
2200
1da177e4 2201 /* i915_dma.c */
d05c617e 2202void i915_update_dri1_breadcrumb(struct drm_device *dev);
84b1fd10 2203extern void i915_kernel_lost_context(struct drm_device * dev);
22eae947 2204extern int i915_driver_load(struct drm_device *, unsigned long flags);
ba8bbcf6 2205extern int i915_driver_unload(struct drm_device *);
2885f6ac 2206extern int i915_driver_open(struct drm_device *dev, struct drm_file *file);
84b1fd10 2207extern void i915_driver_lastclose(struct drm_device * dev);
6c340eac 2208extern void i915_driver_preclose(struct drm_device *dev,
2885f6ac 2209 struct drm_file *file);
673a394b 2210extern void i915_driver_postclose(struct drm_device *dev,
2885f6ac 2211 struct drm_file *file);
84b1fd10 2212extern int i915_driver_device_is_agp(struct drm_device * dev);
c43b5634 2213#ifdef CONFIG_COMPAT
0d6aa60b
DA		 2214extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
2215 unsigned long arg);
c43b5634 2216#endif
673a394b 2217extern int i915_emit_box(struct drm_device *dev,
c4e7a414
CW		 2218 struct drm_clip_rect *box,
2219 int DR1, int DR4);
8e96d9c4 2220extern int intel_gpu_reset(struct drm_device *dev);
d4b8bb2a 2221extern int i915_reset(struct drm_device *dev);
7648fa99
JB		 2222extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
2223extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
2224extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
2225extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
650ad970 2226int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
1d0d343a 2227void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
7648fa99 2228
1da177e4 2229/* i915_irq.c */
10cd45b6 2230void i915_queue_hangcheck(struct drm_device *dev);
58174462
MK		 2231__printf(3, 4)
2232void i915_handle_error(struct drm_device *dev, bool wedged,
2233 const char *fmt, ...);
1da177e4 2234
76c3552f
D		 2235void gen6_set_pm_mask(struct drm_i915_private *dev_priv, u32 pm_iir,
2236 int new_delay);
f71d4af4 2237extern void intel_irq_init(struct drm_device *dev);
20afbda2 2238extern void intel_hpd_init(struct drm_device *dev);
907b28c5
CW		 2239
2240extern void intel_uncore_sanitize(struct drm_device *dev);
10018603
ID		 2241extern void intel_uncore_early_sanitize(struct drm_device *dev,
2242 bool restore_forcewake);
907b28c5 2243extern void intel_uncore_init(struct drm_device *dev);
907b28c5 2244extern void intel_uncore_check_errors(struct drm_device *dev);
aec347ab 2245extern void intel_uncore_fini(struct drm_device *dev);
156c7ca0 2246extern void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore);
b1f14ad0 2247
7c463586 2248void
50227e1c 2249i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
755e9019 2250 u32 status_mask);
7c463586
KP		 2251
2252void
50227e1c 2253i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
755e9019 2254 u32 status_mask);
7c463586 2255
f8b79e58
ID		 2256void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
2257void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
2258
673a394b
EA		 2259/* i915_gem.c */
2260int i915_gem_init_ioctl(struct drm_device *dev, void *data,
2261 struct drm_file *file_priv);
2262int i915_gem_create_ioctl(struct drm_device *dev, void *data,
2263 struct drm_file *file_priv);
2264int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
2265 struct drm_file *file_priv);
2266int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2267 struct drm_file *file_priv);
2268int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
2269 struct drm_file *file_priv);
de151cf6
JB		 2270int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
2271 struct drm_file *file_priv);
673a394b
EA		 2272int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2273 struct drm_file *file_priv);
2274int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
2275 struct drm_file *file_priv);
ba8b7ccb
OM		 2276void i915_gem_execbuffer_move_to_active(struct list_head *vmas,
2277 struct intel_engine_cs *ring);
2278void i915_gem_execbuffer_retire_commands(struct drm_device *dev,
2279 struct drm_file *file,
2280 struct intel_engine_cs *ring,
2281 struct drm_i915_gem_object *obj);
a83014d3
OM		 2282int i915_gem_ringbuffer_submission(struct drm_device *dev,
2283 struct drm_file *file,
2284 struct intel_engine_cs *ring,
2285 struct intel_context *ctx,
2286 struct drm_i915_gem_execbuffer2 *args,
2287 struct list_head *vmas,
2288 struct drm_i915_gem_object *batch_obj,
2289 u64 exec_start, u32 flags);
673a394b
EA		 2290int i915_gem_execbuffer(struct drm_device *dev, void *data,
2291 struct drm_file *file_priv);
76446cac
JB		 2292int i915_gem_execbuffer2(struct drm_device *dev, void *data,
2293 struct drm_file *file_priv);
673a394b
EA		 2294int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
2295 struct drm_file *file_priv);
2296int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
2297 struct drm_file *file_priv);
2298int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
2299 struct drm_file *file_priv);
199adf40
BW		 2300int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
2301 struct drm_file *file);
2302int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
2303 struct drm_file *file);
673a394b
EA		 2304int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
2305 struct drm_file *file_priv);
3ef94daa
CW		 2306int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
2307 struct drm_file *file_priv);
673a394b
EA		 2308int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
2309 struct drm_file *file_priv);
2310int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
2311 struct drm_file *file_priv);
2312int i915_gem_set_tiling(struct drm_device *dev, void *data,
2313 struct drm_file *file_priv);
2314int i915_gem_get_tiling(struct drm_device *dev, void *data,
2315 struct drm_file *file_priv);
5cc9ed4b
CW		 2316int i915_gem_init_userptr(struct drm_device *dev);
2317int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
2318 struct drm_file *file);
5a125c3c
EA		 2319int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
2320 struct drm_file *file_priv);
23ba4fd0
BW		 2321int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
2322 struct drm_file *file_priv);
673a394b 2323void i915_gem_load(struct drm_device *dev);
42dcedd4
CW		 2324void *i915_gem_object_alloc(struct drm_device *dev);
2325void i915_gem_object_free(struct drm_i915_gem_object *obj);
37e680a1
CW		 2326void i915_gem_object_init(struct drm_i915_gem_object *obj,
2327 const struct drm_i915_gem_object_ops *ops);
05394f39
CW		 2328struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
2329 size_t size);
7e0d96bc
BW		 2330void i915_init_vm(struct drm_i915_private *dev_priv,
2331 struct i915_address_space *vm);
673a394b 2332void i915_gem_free_object(struct drm_gem_object *obj);
2f633156 2333void i915_gem_vma_destroy(struct i915_vma *vma);
42dcedd4 2334
1ec9e26d
DV		 2335#define PIN_MAPPABLE 0x1
2336#define PIN_NONBLOCK 0x2
bf3d149b 2337#define PIN_GLOBAL 0x4
d23db88c
CW		 2338#define PIN_OFFSET_BIAS 0x8
2339#define PIN_OFFSET_MASK (~4095)
2021746e 2340int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj,
c37e2204 2341 struct i915_address_space *vm,
2021746e 2342 uint32_t alignment,
d23db88c 2343 uint64_t flags);
07fe0b12 2344int __must_check i915_vma_unbind(struct i915_vma *vma);
dd624afd 2345int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
48018a57 2346void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv);
05394f39 2347void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
673a394b 2348void i915_gem_lastclose(struct drm_device *dev);
f787a5f5 2349
4c914c0c
BV		 2350int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
2351 int *needs_clflush);
2352
37e680a1 2353int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
9da3da66
CW		 2354static inline struct page *i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
2355{
67d5a50c
ID		 2356 struct sg_page_iter sg_iter;
2357
2358 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, n)
2db76d7c 2359 return sg_page_iter_page(&sg_iter);
67d5a50c
ID		 2360
2361 return NULL;
9da3da66 2362}
a5570178
CW		 2363static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
2364{
2365 BUG_ON(obj->pages == NULL);
2366 obj->pages_pin_count++;
2367}
2368static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
2369{
2370 BUG_ON(obj->pages_pin_count == 0);
2371 obj->pages_pin_count--;
2372}
2373
54cf91dc 2374int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
2911a35b 2375int i915_gem_object_sync(struct drm_i915_gem_object *obj,
a4872ba6 2376 struct intel_engine_cs *to);
e2d05a8b 2377void i915_vma_move_to_active(struct i915_vma *vma,
a4872ba6 2378 struct intel_engine_cs *ring);
ff72145b
DA		 2379int i915_gem_dumb_create(struct drm_file *file_priv,
2380 struct drm_device *dev,
2381 struct drm_mode_create_dumb *args);
2382int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
2383 uint32_t handle, uint64_t *offset);
f787a5f5
CW		 2384/**
2385 * Returns true if seq1 is later than seq2.
2386 */
2387static inline bool
2388i915_seqno_passed(uint32_t seq1, uint32_t seq2)
2389{
2390 return (int32_t)(seq1 - seq2) >= 0;
2391}
2392
fca26bb4
MK		 2393int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno);
2394int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
06d98131 2395int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
d9e86c0e 2396int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
2021746e 2397
d8ffa60b
DV		 2398bool i915_gem_object_pin_fence(struct drm_i915_gem_object *obj);
2399void i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj);
1690e1eb 2400
8d9fc7fd 2401struct drm_i915_gem_request *
a4872ba6 2402i915_gem_find_active_request(struct intel_engine_cs *ring);
8d9fc7fd 2403
b29c19b6 2404bool i915_gem_retire_requests(struct drm_device *dev);
a4872ba6 2405void i915_gem_retire_requests_ring(struct intel_engine_cs *ring);
33196ded 2406int __must_check i915_gem_check_wedge(struct i915_gpu_error *error,
d6b2c790 2407 bool interruptible);
84c33a64
SG		 2408int __must_check i915_gem_check_olr(struct intel_engine_cs *ring, u32 seqno);
2409
1f83fee0
DV		 2410static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
2411{
2412 return unlikely(atomic_read(&error->reset_counter)
2ac0f450 2413 & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED));
1f83fee0
DV		 2414}
2415
2416static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
2417{
2ac0f450
MK		 2418 return atomic_read(&error->reset_counter) & I915_WEDGED;
2419}
2420
2421static inline u32 i915_reset_count(struct i915_gpu_error *error)
2422{
2423 return ((atomic_read(&error->reset_counter) & ~I915_WEDGED) + 1) / 2;
1f83fee0 2424}
a71d8d94 2425
88b4aa87
MK		 2426static inline bool i915_stop_ring_allow_ban(struct drm_i915_private *dev_priv)
2427{
2428 return dev_priv->gpu_error.stop_rings == 0 ||
2429 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_BAN;
2430}
2431
2432static inline bool i915_stop_ring_allow_warn(struct drm_i915_private *dev_priv)
2433{
2434 return dev_priv->gpu_error.stop_rings == 0 ||
2435 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_WARN;
2436}
2437
069efc1d 2438void i915_gem_reset(struct drm_device *dev);
000433b6 2439bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
a8198eea 2440int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj);
1070a42b 2441int __must_check i915_gem_init(struct drm_device *dev);
a83014d3 2442int i915_gem_init_rings(struct drm_device *dev);
f691e2f4 2443int __must_check i915_gem_init_hw(struct drm_device *dev);
a4872ba6 2444int i915_gem_l3_remap(struct intel_engine_cs *ring, int slice);
f691e2f4 2445void i915_gem_init_swizzling(struct drm_device *dev);
79e53945 2446void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
b2da9fe5 2447int __must_check i915_gpu_idle(struct drm_device *dev);
45c5f202 2448int __must_check i915_gem_suspend(struct drm_device *dev);
a4872ba6 2449int __i915_add_request(struct intel_engine_cs *ring,
0025c077 2450 struct drm_file *file,
7d736f4f 2451 struct drm_i915_gem_object *batch_obj,
0025c077
MK		 2452 u32 *seqno);
2453#define i915_add_request(ring, seqno) \
854c94a7 2454 __i915_add_request(ring, NULL, NULL, seqno)
a4872ba6 2455int __must_check i915_wait_seqno(struct intel_engine_cs *ring,
199b2bc2 2456 uint32_t seqno);
de151cf6 2457int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
2021746e
CW		 2458int __must_check
2459i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
2460 bool write);
2461int __must_check
dabdfe02
CW		 2462i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
2463int __must_check
2da3b9b9
CW		 2464i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
2465 u32 alignment,
a4872ba6 2466 struct intel_engine_cs *pipelined);
cc98b413 2467void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj);
00731155 2468int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
6eeefaf3 2469 int align);
b29c19b6 2470int i915_gem_open(struct drm_device *dev, struct drm_file *file);
05394f39 2471void i915_gem_release(struct drm_device *dev, struct drm_file *file);
673a394b 2472
0fa87796
ID		 2473uint32_t
2474i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode);
467cffba 2475uint32_t
d865110c
ID		 2476i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
2477 int tiling_mode, bool fenced);
467cffba 2478
e4ffd173
CW		 2479int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
2480 enum i915_cache_level cache_level);
2481
1286ff73
DV		 2482struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
2483 struct dma_buf *dma_buf);
2484
2485struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
2486 struct drm_gem_object *gem_obj, int flags);
2487
19b2dbde
CW		 2488void i915_gem_restore_fences(struct drm_device *dev);
2489
a70a3148
BW		 2490unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o,
2491 struct i915_address_space *vm);
2492bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o);
2493bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
2494 struct i915_address_space *vm);
2495unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
2496 struct i915_address_space *vm);
2497struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
2498 struct i915_address_space *vm);
accfef2e
BW		 2499struct i915_vma *
2500i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
2501 struct i915_address_space *vm);
5c2abbea
BW		 2502
2503struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj);
d7f46fc4
BW		 2504static inline bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj) {
2505 struct i915_vma *vma;
2506 list_for_each_entry(vma, &obj->vma_list, vma_link)
2507 if (vma->pin_count > 0)
2508 return true;
2509 return false;
2510}
5c2abbea 2511
a70a3148 2512/* Some GGTT VM helpers */
5dc383b0 2513#define i915_obj_to_ggtt(obj) \
a70a3148
BW		 2514 (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base)
2515static inline bool i915_is_ggtt(struct i915_address_space *vm)
2516{
2517 struct i915_address_space *ggtt =
2518 &((struct drm_i915_private *)(vm)->dev->dev_private)->gtt.base;
2519 return vm == ggtt;
2520}
2521
841cd773
DV		 2522static inline struct i915_hw_ppgtt *
2523i915_vm_to_ppgtt(struct i915_address_space *vm)
2524{
2525 WARN_ON(i915_is_ggtt(vm));
2526
2527 return container_of(vm, struct i915_hw_ppgtt, base);
2528}
2529
2530
a70a3148
BW		 2531static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj)
2532{
5dc383b0 2533 return i915_gem_obj_bound(obj, i915_obj_to_ggtt(obj));
a70a3148
BW		 2534}
2535
2536static inline unsigned long
2537i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *obj)
2538{
5dc383b0 2539 return i915_gem_obj_offset(obj, i915_obj_to_ggtt(obj));
a70a3148
BW		 2540}
2541
2542static inline unsigned long
2543i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj)
2544{
5dc383b0 2545 return i915_gem_obj_size(obj, i915_obj_to_ggtt(obj));
a70a3148 2546}
c37e2204
BW		 2547
2548static inline int __must_check
2549i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj,
2550 uint32_t alignment,
1ec9e26d 2551 unsigned flags)
c37e2204 2552{
5dc383b0
DV		 2553 return i915_gem_object_pin(obj, i915_obj_to_ggtt(obj),
2554 alignment, flags | PIN_GLOBAL);
c37e2204 2555}
a70a3148 2556
b287110e
DV		 2557static inline int
2558i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj)
2559{
2560 return i915_vma_unbind(i915_gem_obj_to_ggtt(obj));
2561}
2562
2563void i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj);
2564
254f965c 2565/* i915_gem_context.c */
8245be31 2566int __must_check i915_gem_context_init(struct drm_device *dev);
254f965c 2567void i915_gem_context_fini(struct drm_device *dev);
acce9ffa 2568void i915_gem_context_reset(struct drm_device *dev);
e422b888 2569int i915_gem_context_open(struct drm_device *dev, struct drm_file *file);
2fa48d8d 2570int i915_gem_context_enable(struct drm_i915_private *dev_priv);
254f965c 2571void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
a4872ba6 2572int i915_switch_context(struct intel_engine_cs *ring,
273497e5
OM		 2573 struct intel_context *to);
2574struct intel_context *
41bde553 2575i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id);
dce3271b 2576void i915_gem_context_free(struct kref *ctx_ref);
8c857917
OM		 2577struct drm_i915_gem_object *
2578i915_gem_alloc_context_obj(struct drm_device *dev, size_t size);
273497e5 2579static inline void i915_gem_context_reference(struct intel_context *ctx)
dce3271b 2580{
691e6415 2581 kref_get(&ctx->ref);
dce3271b
MK		 2582}
2583
273497e5 2584static inline void i915_gem_context_unreference(struct intel_context *ctx)
dce3271b 2585{
691e6415 2586 kref_put(&ctx->ref, i915_gem_context_free);
dce3271b
MK		 2587}
2588
273497e5 2589static inline bool i915_gem_context_is_default(const struct intel_context *c)
3fac8978 2590{
821d66dd 2591 return c->user_handle == DEFAULT_CONTEXT_HANDLE;
3fac8978
MK		 2592}
2593
84624813
BW		 2594int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
2595 struct drm_file *file);
2596int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
2597 struct drm_file *file);
1286ff73 2598
9d0a6fa6 2599/* i915_gem_render_state.c */
a4872ba6 2600int i915_gem_render_state_init(struct intel_engine_cs *ring);
679845ed
BW		 2601/* i915_gem_evict.c */
2602int __must_check i915_gem_evict_something(struct drm_device *dev,
2603 struct i915_address_space *vm,
2604 int min_size,
2605 unsigned alignment,
2606 unsigned cache_level,
d23db88c
CW		 2607 unsigned long start,
2608 unsigned long end,
1ec9e26d 2609 unsigned flags);
679845ed
BW		 2610int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
2611int i915_gem_evict_everything(struct drm_device *dev);
1d2a314c 2612
0260c420 2613/* belongs in i915_gem_gtt.h */
d09105c6 2614static inline void i915_gem_chipset_flush(struct drm_device *dev)
e76e9aeb
BW		 2615{
2616 if (INTEL_INFO(dev)->gen < 6)
2617 intel_gtt_chipset_flush();
2618}
246cbfb5 2619
9797fbfb
CW		 2620/* i915_gem_stolen.c */
2621int i915_gem_init_stolen(struct drm_device *dev);
5e59f717 2622int i915_gem_stolen_setup_compression(struct drm_device *dev, int size, int fb_cpp);
11be49eb 2623void i915_gem_stolen_cleanup_compression(struct drm_device *dev);
9797fbfb 2624void i915_gem_cleanup_stolen(struct drm_device *dev);
0104fdbb
CW		 2625struct drm_i915_gem_object *
2626i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
866d12b4
CW		 2627struct drm_i915_gem_object *
2628i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
2629 u32 stolen_offset,
2630 u32 gtt_offset,
2631 u32 size);
9797fbfb 2632
673a394b 2633/* i915_gem_tiling.c */
2c1792a1 2634static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
e9b73c67 2635{
50227e1c 2636 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
e9b73c67
CW		 2637
2638 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
2639 obj->tiling_mode != I915_TILING_NONE;
2640}
2641
673a394b 2642void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
05394f39
CW		 2643void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
2644void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
673a394b
EA		 2645
2646/* i915_gem_debug.c */
23bc5982
CW		 2647#if WATCH_LISTS
2648int i915_verify_lists(struct drm_device *dev);
673a394b 2649#else
23bc5982 2650#define i915_verify_lists(dev) 0
673a394b 2651#endif
1da177e4 2652
2017263e 2653/* i915_debugfs.c */
27c202ad
BG		 2654int i915_debugfs_init(struct drm_minor *minor);
2655void i915_debugfs_cleanup(struct drm_minor *minor);
f8c168fa 2656#ifdef CONFIG_DEBUG_FS
07144428
DL		 2657void intel_display_crc_init(struct drm_device *dev);
2658#else
f8c168fa 2659static inline void intel_display_crc_init(struct drm_device *dev) {}
07144428 2660#endif
84734a04
MK		 2661
2662/* i915_gpu_error.c */
edc3d884
MK		 2663__printf(2, 3)
2664void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
fc16b48b
MK		 2665int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
2666 const struct i915_error_state_file_priv *error);
4dc955f7 2667int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
0a4cd7c8 2668 struct drm_i915_private *i915,
4dc955f7
MK		 2669 size_t count, loff_t pos);
2670static inline void i915_error_state_buf_release(
2671 struct drm_i915_error_state_buf *eb)
2672{
2673 kfree(eb->buf);
2674}
58174462
MK		 2675void i915_capture_error_state(struct drm_device *dev, bool wedge,
2676 const char *error_msg);
84734a04
MK		 2677void i915_error_state_get(struct drm_device *dev,
2678 struct i915_error_state_file_priv *error_priv);
2679void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
2680void i915_destroy_error_state(struct drm_device *dev);
2681
2682void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone);
0a4cd7c8 2683const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
2017263e 2684
351e3db2 2685/* i915_cmd_parser.c */
d728c8ef 2686int i915_cmd_parser_get_version(void);
a4872ba6
OM		 2687int i915_cmd_parser_init_ring(struct intel_engine_cs *ring);
2688void i915_cmd_parser_fini_ring(struct intel_engine_cs *ring);
2689bool i915_needs_cmd_parser(struct intel_engine_cs *ring);
2690int i915_parse_cmds(struct intel_engine_cs *ring,
351e3db2
BV		 2691 struct drm_i915_gem_object *batch_obj,
2692 u32 batch_start_offset,
2693 bool is_master);
2694
317c35d1
JB		 2695/* i915_suspend.c */
2696extern int i915_save_state(struct drm_device *dev);
2697extern int i915_restore_state(struct drm_device *dev);
0a3e67a4 2698
d8157a36
DV		 2699/* i915_ums.c */
2700void i915_save_display_reg(struct drm_device *dev);
2701void i915_restore_display_reg(struct drm_device *dev);
317c35d1 2702
0136db58
BW		 2703/* i915_sysfs.c */
2704void i915_setup_sysfs(struct drm_device *dev_priv);
2705void i915_teardown_sysfs(struct drm_device *dev_priv);
2706
f899fc64
CW		 2707/* intel_i2c.c */
2708extern int intel_setup_gmbus(struct drm_device *dev);
2709extern void intel_teardown_gmbus(struct drm_device *dev);
8f375e10 2710static inline bool intel_gmbus_is_port_valid(unsigned port)
3bd7d909 2711{
2ed06c93 2712 return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD);
3bd7d909
DK		 2713}
2714
2715extern struct i2c_adapter *intel_gmbus_get_adapter(
2716 struct drm_i915_private *dev_priv, unsigned port);
e957d772
CW		 2717extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
2718extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
8f375e10 2719static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
b8232e90
CW		 2720{
2721 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
2722}
f899fc64
CW		 2723extern void intel_i2c_reset(struct drm_device *dev);
2724
3b617967 2725/* intel_opregion.c */
9c4b0a68 2726struct intel_encoder;
44834a67 2727#ifdef CONFIG_ACPI
27d50c82 2728extern int intel_opregion_setup(struct drm_device *dev);
44834a67
CW		 2729extern void intel_opregion_init(struct drm_device *dev);
2730extern void intel_opregion_fini(struct drm_device *dev);
3b617967 2731extern void intel_opregion_asle_intr(struct drm_device *dev);
9c4b0a68
JN		 2732extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
2733 bool enable);
ecbc5cf3
JN		 2734extern int intel_opregion_notify_adapter(struct drm_device *dev,
2735 pci_power_t state);
65e082c9 2736#else
27d50c82 2737static inline int intel_opregion_setup(struct drm_device *dev) { return 0; }
44834a67
CW		 2738static inline void intel_opregion_init(struct drm_device *dev) { return; }
2739static inline void intel_opregion_fini(struct drm_device *dev) { return; }
3b617967 2740static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
9c4b0a68
JN		 2741static inline int
2742intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
2743{
2744 return 0;
2745}
ecbc5cf3
JN		 2746static inline int
2747intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state)
2748{
2749 return 0;
2750}
65e082c9 2751#endif
8ee1c3db 2752
723bfd70
JB		 2753/* intel_acpi.c */
2754#ifdef CONFIG_ACPI
2755extern void intel_register_dsm_handler(void);
2756extern void intel_unregister_dsm_handler(void);
2757#else
2758static inline void intel_register_dsm_handler(void) { return; }
2759static inline void intel_unregister_dsm_handler(void) { return; }
2760#endif /* CONFIG_ACPI */
2761
79e53945 2762/* modesetting */
f817586c 2763extern void intel_modeset_init_hw(struct drm_device *dev);
7d708ee4 2764extern void intel_modeset_suspend_hw(struct drm_device *dev);
79e53945 2765extern void intel_modeset_init(struct drm_device *dev);
2c7111db 2766extern void intel_modeset_gem_init(struct drm_device *dev);
79e53945 2767extern void intel_modeset_cleanup(struct drm_device *dev);
4932e2c3 2768extern void intel_connector_unregister(struct intel_connector *);
28d52043 2769extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
45e2b5f6
DV		 2770extern void intel_modeset_setup_hw_state(struct drm_device *dev,
2771 bool force_restore);
44cec740 2772extern void i915_redisable_vga(struct drm_device *dev);
04098753 2773extern void i915_redisable_vga_power_on(struct drm_device *dev);
ee5382ae 2774extern bool intel_fbc_enabled(struct drm_device *dev);
43a9539f 2775extern void intel_disable_fbc(struct drm_device *dev);
7648fa99 2776extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
dde86e2d 2777extern void intel_init_pch_refclk(struct drm_device *dev);
3b8d8d91 2778extern void gen6_set_rps(struct drm_device *dev, u8 val);
0a073b84 2779extern void valleyview_set_rps(struct drm_device *dev, u8 val);
5209b1f4
ID		 2780extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
2781 bool enable);
0206e353
AJ		 2782extern void intel_detect_pch(struct drm_device *dev);
2783extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
0136db58 2784extern int intel_enable_rc6(const struct drm_device *dev);
3bad0781 2785
2911a35b 2786extern bool i915_semaphore_is_enabled(struct drm_device *dev);
c0c7babc
BW		 2787int i915_reg_read_ioctl(struct drm_device *dev, void *data,
2788 struct drm_file *file);
b6359918
MK		 2789int i915_get_reset_stats_ioctl(struct drm_device *dev, void *data,
2790 struct drm_file *file);
575155a9 2791
84c33a64
SG		 2792void intel_notify_mmio_flip(struct intel_engine_cs *ring);
2793
6ef3d427
CW		 2794/* overlay */
2795extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
edc3d884
MK		 2796extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
2797 struct intel_overlay_error_state *error);
c4a1d9e4
CW		 2798
2799extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
edc3d884 2800extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
c4a1d9e4
CW		 2801 struct drm_device *dev,
2802 struct intel_display_error_state *error);
6ef3d427 2803
b7287d80
BW		 2804/* On SNB platform, before reading ring registers forcewake bit
2805 * must be set to prevent GT core from power down and stale values being
2806 * returned.
2807 */
c8d9a590
D		 2808void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine);
2809void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine);
e998c40f 2810void assert_force_wake_inactive(struct drm_i915_private *dev_priv);
b7287d80 2811
42c0526c
BW		 2812int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val);
2813int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val);
59de0813
JN		 2814
2815/* intel_sideband.c */
64936258
JN		 2816u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr);
2817void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val);
2818u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
e9f882a3
JN		 2819u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg);
2820void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2821u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
2822void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2823u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
2824void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
f3419158
JB		 2825u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
2826void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
e9f882a3
JN		 2827u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg);
2828void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
5e69f97f
CML		 2829u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
2830void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
59de0813
JN		 2831u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
2832 enum intel_sbi_destination destination);
2833void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
2834 enum intel_sbi_destination destination);
e9fe51c6
SK		 2835u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
2836void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
0a073b84 2837
2ec3815f
VS		 2838int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val);
2839int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val);
42c0526c 2840
c8d9a590
D		 2841#define FORCEWAKE_RENDER (1 << 0)
2842#define FORCEWAKE_MEDIA (1 << 1)
2843#define FORCEWAKE_ALL (FORCEWAKE_RENDER | FORCEWAKE_MEDIA)
2844
2845
0b274481
BW		 2846#define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
2847#define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
2848
2849#define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
2850#define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
2851#define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
2852#define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
2853
2854#define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
2855#define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
2856#define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
2857#define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
2858
698b3135
CW		 2859/* Be very careful with read/write 64-bit values. On 32-bit machines, they
2860 * will be implemented using 2 32-bit writes in an arbitrary order with
2861 * an arbitrary delay between them. This can cause the hardware to
2862 * act upon the intermediate value, possibly leading to corruption and
2863 * machine death. You have been warned.
2864 */
0b274481
BW		 2865#define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
2866#define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
cae5852d 2867
50877445
CW		 2868#define I915_READ64_2x32(lower_reg, upper_reg) ({ \
2869 u32 upper = I915_READ(upper_reg); \
2870 u32 lower = I915_READ(lower_reg); \
2871 u32 tmp = I915_READ(upper_reg); \
2872 if (upper != tmp) { \
2873 upper = tmp; \
2874 lower = I915_READ(lower_reg); \
2875 WARN_ON(I915_READ(upper_reg) != upper); \
2876 } \
2877 (u64)upper << 32 | lower; })
2878
cae5852d
ZN		 2879#define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
2880#define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
2881
55bc60db
VS		 2882/* "Broadcast RGB" property */
2883#define INTEL_BROADCAST_RGB_AUTO 0
2884#define INTEL_BROADCAST_RGB_FULL 1
2885#define INTEL_BROADCAST_RGB_LIMITED 2
ba4f01a3 2886
766aa1c4
VS		 2887static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev)
2888{
92e23b99 2889 if (IS_VALLEYVIEW(dev))
766aa1c4 2890 return VLV_VGACNTRL;
92e23b99
SJ		 2891 else if (INTEL_INFO(dev)->gen >= 5)
2892 return CPU_VGACNTRL;
766aa1c4
VS		 2893 else
2894 return VGACNTRL;
2895}
2896
2bb4629a
VS		 2897static inline void __user *to_user_ptr(u64 address)
2898{
2899 return (void __user *)(uintptr_t)address;
2900}
2901
df97729f
ID		 2902static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
2903{
2904 unsigned long j = msecs_to_jiffies(m);
2905
2906 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
2907}
2908
2909static inline unsigned long
2910timespec_to_jiffies_timeout(const struct timespec *value)
2911{
2912 unsigned long j = timespec_to_jiffies(value);
2913
2914 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
2915}
2916
dce56b3c
PZ		 2917/*
2918 * If you need to wait X milliseconds between events A and B, but event B
2919 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
2920 * when event A happened, then just before event B you call this function and
2921 * pass the timestamp as the first argument, and X as the second argument.
2922 */
2923static inline void
2924wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
2925{
ec5e0cfb 2926 unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
dce56b3c
PZ		 2927
2928 /*
2929 * Don't re-read the value of "jiffies" every time since it may change
2930 * behind our back and break the math.
2931 */
2932 tmp_jiffies = jiffies;
2933 target_jiffies = timestamp_jiffies +
2934 msecs_to_jiffies_timeout(to_wait_ms);
2935
2936 if (time_after(target_jiffies, tmp_jiffies)) {
ec5e0cfb
ID		 2937 remaining_jiffies = target_jiffies - tmp_jiffies;
2938 while (remaining_jiffies)
2939 remaining_jiffies =
2940 schedule_timeout_uninterruptible(remaining_jiffies);
dce56b3c
PZ		 2941 }
2942}
2943
1da177e4 2944#endif
Linux kernel - Deliverables
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