Commit | Line | Data |
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1da177e4 LT |
1 | /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- |
2 | */ | |
0d6aa60b | 3 | /* |
bc54fd1a | 4 | * |
1da177e4 LT |
5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
6 | * All Rights Reserved. | |
bc54fd1a DA |
7 | * |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the | |
10 | * "Software"), to deal in the Software without restriction, including | |
11 | * without limitation the rights to use, copy, modify, merge, publish, | |
12 | * distribute, sub license, and/or sell copies of the Software, and to | |
13 | * permit persons to whom the Software is furnished to do so, subject to | |
14 | * the following conditions: | |
15 | * | |
16 | * The above copyright notice and this permission notice (including the | |
17 | * next paragraph) shall be included in all copies or substantial portions | |
18 | * of the Software. | |
19 | * | |
20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
27 | * | |
0d6aa60b | 28 | */ |
1da177e4 LT |
29 | |
30 | #ifndef _I915_DRV_H_ | |
31 | #define _I915_DRV_H_ | |
32 | ||
e9b73c67 CW |
33 | #include <uapi/drm/i915_drm.h> |
34 | ||
585fb111 | 35 | #include "i915_reg.h" |
79e53945 | 36 | #include "intel_bios.h" |
8187a2b7 | 37 | #include "intel_ringbuffer.h" |
0260c420 | 38 | #include "i915_gem_gtt.h" |
0839ccb8 | 39 | #include <linux/io-mapping.h> |
f899fc64 | 40 | #include <linux/i2c.h> |
c167a6fc | 41 | #include <linux/i2c-algo-bit.h> |
0ade6386 | 42 | #include <drm/intel-gtt.h> |
aaa6fd2a | 43 | #include <linux/backlight.h> |
5cc9ed4b | 44 | #include <linux/hashtable.h> |
2911a35b | 45 | #include <linux/intel-iommu.h> |
742cbee8 | 46 | #include <linux/kref.h> |
9ee32fea | 47 | #include <linux/pm_qos.h> |
585fb111 | 48 | |
1da177e4 LT |
49 | /* General customization: |
50 | */ | |
51 | ||
52 | #define DRIVER_AUTHOR "Tungsten Graphics, Inc." | |
53 | ||
54 | #define DRIVER_NAME "i915" | |
55 | #define DRIVER_DESC "Intel Graphics" | |
72b79c9b | 56 | #define DRIVER_DATE "20140725" |
1da177e4 | 57 | |
317c35d1 | 58 | enum pipe { |
752aa88a | 59 | INVALID_PIPE = -1, |
317c35d1 JB |
60 | PIPE_A = 0, |
61 | PIPE_B, | |
9db4a9c7 | 62 | PIPE_C, |
a57c774a AK |
63 | _PIPE_EDP, |
64 | I915_MAX_PIPES = _PIPE_EDP | |
317c35d1 | 65 | }; |
9db4a9c7 | 66 | #define pipe_name(p) ((p) + 'A') |
317c35d1 | 67 | |
a5c961d1 PZ |
68 | enum transcoder { |
69 | TRANSCODER_A = 0, | |
70 | TRANSCODER_B, | |
71 | TRANSCODER_C, | |
a57c774a AK |
72 | TRANSCODER_EDP, |
73 | I915_MAX_TRANSCODERS | |
a5c961d1 PZ |
74 | }; |
75 | #define transcoder_name(t) ((t) + 'A') | |
76 | ||
80824003 JB |
77 | enum plane { |
78 | PLANE_A = 0, | |
79 | PLANE_B, | |
9db4a9c7 | 80 | PLANE_C, |
80824003 | 81 | }; |
9db4a9c7 | 82 | #define plane_name(p) ((p) + 'A') |
52440211 | 83 | |
d615a166 | 84 | #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A') |
06da8da2 | 85 | |
2b139522 ED |
86 | enum port { |
87 | PORT_A = 0, | |
88 | PORT_B, | |
89 | PORT_C, | |
90 | PORT_D, | |
91 | PORT_E, | |
92 | I915_MAX_PORTS | |
93 | }; | |
94 | #define port_name(p) ((p) + 'A') | |
95 | ||
a09caddd | 96 | #define I915_NUM_PHYS_VLV 2 |
e4607fcf CML |
97 | |
98 | enum dpio_channel { | |
99 | DPIO_CH0, | |
100 | DPIO_CH1 | |
101 | }; | |
102 | ||
103 | enum dpio_phy { | |
104 | DPIO_PHY0, | |
105 | DPIO_PHY1 | |
106 | }; | |
107 | ||
b97186f0 PZ |
108 | enum intel_display_power_domain { |
109 | POWER_DOMAIN_PIPE_A, | |
110 | POWER_DOMAIN_PIPE_B, | |
111 | POWER_DOMAIN_PIPE_C, | |
112 | POWER_DOMAIN_PIPE_A_PANEL_FITTER, | |
113 | POWER_DOMAIN_PIPE_B_PANEL_FITTER, | |
114 | POWER_DOMAIN_PIPE_C_PANEL_FITTER, | |
115 | POWER_DOMAIN_TRANSCODER_A, | |
116 | POWER_DOMAIN_TRANSCODER_B, | |
117 | POWER_DOMAIN_TRANSCODER_C, | |
f52e353e | 118 | POWER_DOMAIN_TRANSCODER_EDP, |
319be8ae ID |
119 | POWER_DOMAIN_PORT_DDI_A_2_LANES, |
120 | POWER_DOMAIN_PORT_DDI_A_4_LANES, | |
121 | POWER_DOMAIN_PORT_DDI_B_2_LANES, | |
122 | POWER_DOMAIN_PORT_DDI_B_4_LANES, | |
123 | POWER_DOMAIN_PORT_DDI_C_2_LANES, | |
124 | POWER_DOMAIN_PORT_DDI_C_4_LANES, | |
125 | POWER_DOMAIN_PORT_DDI_D_2_LANES, | |
126 | POWER_DOMAIN_PORT_DDI_D_4_LANES, | |
127 | POWER_DOMAIN_PORT_DSI, | |
128 | POWER_DOMAIN_PORT_CRT, | |
129 | POWER_DOMAIN_PORT_OTHER, | |
cdf8dd7f | 130 | POWER_DOMAIN_VGA, |
fbeeaa23 | 131 | POWER_DOMAIN_AUDIO, |
bd2bb1b9 | 132 | POWER_DOMAIN_PLLS, |
baa70707 | 133 | POWER_DOMAIN_INIT, |
bddc7645 ID |
134 | |
135 | POWER_DOMAIN_NUM, | |
b97186f0 PZ |
136 | }; |
137 | ||
138 | #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A) | |
139 | #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \ | |
140 | ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER) | |
f52e353e ID |
141 | #define POWER_DOMAIN_TRANSCODER(tran) \ |
142 | ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \ | |
143 | (tran) + POWER_DOMAIN_TRANSCODER_A) | |
b97186f0 | 144 | |
1d843f9d EE |
145 | enum hpd_pin { |
146 | HPD_NONE = 0, | |
147 | HPD_PORT_A = HPD_NONE, /* PORT_A is internal */ | |
148 | HPD_TV = HPD_NONE, /* TV is known to be unreliable */ | |
149 | HPD_CRT, | |
150 | HPD_SDVO_B, | |
151 | HPD_SDVO_C, | |
152 | HPD_PORT_B, | |
153 | HPD_PORT_C, | |
154 | HPD_PORT_D, | |
155 | HPD_NUM_PINS | |
156 | }; | |
157 | ||
2a2d5482 CW |
158 | #define I915_GEM_GPU_DOMAINS \ |
159 | (I915_GEM_DOMAIN_RENDER | \ | |
160 | I915_GEM_DOMAIN_SAMPLER | \ | |
161 | I915_GEM_DOMAIN_COMMAND | \ | |
162 | I915_GEM_DOMAIN_INSTRUCTION | \ | |
163 | I915_GEM_DOMAIN_VERTEX) | |
62fdfeaf | 164 | |
7eb552ae | 165 | #define for_each_pipe(p) for ((p) = 0; (p) < INTEL_INFO(dev)->num_pipes; (p)++) |
d615a166 | 166 | #define for_each_sprite(p, s) for ((s) = 0; (s) < INTEL_INFO(dev)->num_sprites[(p)]; (s)++) |
9db4a9c7 | 167 | |
d79b814d DL |
168 | #define for_each_crtc(dev, crtc) \ |
169 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) | |
170 | ||
d063ae48 DL |
171 | #define for_each_intel_crtc(dev, intel_crtc) \ |
172 | list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head) | |
173 | ||
6c2b7c12 DV |
174 | #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \ |
175 | list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \ | |
176 | if ((intel_encoder)->base.crtc == (__crtc)) | |
177 | ||
53f5e3ca JB |
178 | #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \ |
179 | list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \ | |
180 | if ((intel_connector)->base.encoder == (__encoder)) | |
181 | ||
b04c5bd6 BF |
182 | #define for_each_power_domain(domain, mask) \ |
183 | for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \ | |
184 | if ((1 << (domain)) & (mask)) | |
185 | ||
e7b903d2 | 186 | struct drm_i915_private; |
ad46cb53 | 187 | struct i915_mm_struct; |
5cc9ed4b | 188 | struct i915_mmu_object; |
e7b903d2 | 189 | |
46edb027 DV |
190 | enum intel_dpll_id { |
191 | DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */ | |
192 | /* real shared dpll ids must be >= 0 */ | |
9cd86933 DV |
193 | DPLL_ID_PCH_PLL_A = 0, |
194 | DPLL_ID_PCH_PLL_B = 1, | |
195 | DPLL_ID_WRPLL1 = 0, | |
196 | DPLL_ID_WRPLL2 = 1, | |
46edb027 DV |
197 | }; |
198 | #define I915_NUM_PLLS 2 | |
199 | ||
5358901f | 200 | struct intel_dpll_hw_state { |
66e985c0 | 201 | uint32_t dpll; |
8bcc2795 | 202 | uint32_t dpll_md; |
66e985c0 DV |
203 | uint32_t fp0; |
204 | uint32_t fp1; | |
d452c5b6 | 205 | uint32_t wrpll; |
5358901f DV |
206 | }; |
207 | ||
e72f9fbf | 208 | struct intel_shared_dpll { |
ee7b9f93 JB |
209 | int refcount; /* count of number of CRTCs sharing this PLL */ |
210 | int active; /* count of number of active CRTCs (i.e. DPMS on) */ | |
211 | bool on; /* is the PLL actually active? Disabled during modeset */ | |
46edb027 DV |
212 | const char *name; |
213 | /* should match the index in the dev_priv->shared_dplls array */ | |
214 | enum intel_dpll_id id; | |
5358901f | 215 | struct intel_dpll_hw_state hw_state; |
96f6128c DV |
216 | /* The mode_set hook is optional and should be used together with the |
217 | * intel_prepare_shared_dpll function. */ | |
15bdd4cf DV |
218 | void (*mode_set)(struct drm_i915_private *dev_priv, |
219 | struct intel_shared_dpll *pll); | |
e7b903d2 DV |
220 | void (*enable)(struct drm_i915_private *dev_priv, |
221 | struct intel_shared_dpll *pll); | |
222 | void (*disable)(struct drm_i915_private *dev_priv, | |
223 | struct intel_shared_dpll *pll); | |
5358901f DV |
224 | bool (*get_hw_state)(struct drm_i915_private *dev_priv, |
225 | struct intel_shared_dpll *pll, | |
226 | struct intel_dpll_hw_state *hw_state); | |
ee7b9f93 | 227 | }; |
ee7b9f93 | 228 | |
e69d0bc1 DV |
229 | /* Used by dp and fdi links */ |
230 | struct intel_link_m_n { | |
231 | uint32_t tu; | |
232 | uint32_t gmch_m; | |
233 | uint32_t gmch_n; | |
234 | uint32_t link_m; | |
235 | uint32_t link_n; | |
236 | }; | |
237 | ||
238 | void intel_link_compute_m_n(int bpp, int nlanes, | |
239 | int pixel_clock, int link_clock, | |
240 | struct intel_link_m_n *m_n); | |
241 | ||
1da177e4 LT |
242 | /* Interface history: |
243 | * | |
244 | * 1.1: Original. | |
0d6aa60b DA |
245 | * 1.2: Add Power Management |
246 | * 1.3: Add vblank support | |
de227f5f | 247 | * 1.4: Fix cmdbuffer path, add heap destroy |
702880f2 | 248 | * 1.5: Add vblank pipe configuration |
2228ed67 MCA |
249 | * 1.6: - New ioctl for scheduling buffer swaps on vertical blank |
250 | * - Support vertical blank on secondary display pipe | |
1da177e4 LT |
251 | */ |
252 | #define DRIVER_MAJOR 1 | |
2228ed67 | 253 | #define DRIVER_MINOR 6 |
1da177e4 LT |
254 | #define DRIVER_PATCHLEVEL 0 |
255 | ||
23bc5982 | 256 | #define WATCH_LISTS 0 |
42d6ab48 | 257 | #define WATCH_GTT 0 |
673a394b | 258 | |
0a3e67a4 JB |
259 | struct opregion_header; |
260 | struct opregion_acpi; | |
261 | struct opregion_swsci; | |
262 | struct opregion_asle; | |
263 | ||
8ee1c3db | 264 | struct intel_opregion { |
5bc4418b BW |
265 | struct opregion_header __iomem *header; |
266 | struct opregion_acpi __iomem *acpi; | |
267 | struct opregion_swsci __iomem *swsci; | |
ebde53c7 JN |
268 | u32 swsci_gbda_sub_functions; |
269 | u32 swsci_sbcb_sub_functions; | |
5bc4418b BW |
270 | struct opregion_asle __iomem *asle; |
271 | void __iomem *vbt; | |
01fe9dbd | 272 | u32 __iomem *lid_state; |
91a60f20 | 273 | struct work_struct asle_work; |
8ee1c3db | 274 | }; |
44834a67 | 275 | #define OPREGION_SIZE (8*1024) |
8ee1c3db | 276 | |
6ef3d427 CW |
277 | struct intel_overlay; |
278 | struct intel_overlay_error_state; | |
279 | ||
7c1c2871 DA |
280 | struct drm_i915_master_private { |
281 | drm_local_map_t *sarea; | |
282 | struct _drm_i915_sarea *sarea_priv; | |
283 | }; | |
de151cf6 | 284 | #define I915_FENCE_REG_NONE -1 |
42b5aeab VS |
285 | #define I915_MAX_NUM_FENCES 32 |
286 | /* 32 fences + sign bit for FENCE_REG_NONE */ | |
287 | #define I915_MAX_NUM_FENCE_BITS 6 | |
de151cf6 JB |
288 | |
289 | struct drm_i915_fence_reg { | |
007cc8ac | 290 | struct list_head lru_list; |
caea7476 | 291 | struct drm_i915_gem_object *obj; |
1690e1eb | 292 | int pin_count; |
de151cf6 | 293 | }; |
7c1c2871 | 294 | |
9b9d172d | 295 | struct sdvo_device_mapping { |
e957d772 | 296 | u8 initialized; |
9b9d172d | 297 | u8 dvo_port; |
298 | u8 slave_addr; | |
299 | u8 dvo_wiring; | |
e957d772 | 300 | u8 i2c_pin; |
b1083333 | 301 | u8 ddc_pin; |
9b9d172d | 302 | }; |
303 | ||
c4a1d9e4 CW |
304 | struct intel_display_error_state; |
305 | ||
63eeaf38 | 306 | struct drm_i915_error_state { |
742cbee8 | 307 | struct kref ref; |
585b0288 BW |
308 | struct timeval time; |
309 | ||
cb383002 | 310 | char error_msg[128]; |
48b031e3 | 311 | u32 reset_count; |
62d5d69b | 312 | u32 suspend_count; |
cb383002 | 313 | |
585b0288 | 314 | /* Generic register state */ |
63eeaf38 JB |
315 | u32 eir; |
316 | u32 pgtbl_er; | |
be998e2e | 317 | u32 ier; |
885ea5a8 | 318 | u32 gtier[4]; |
b9a3906b | 319 | u32 ccid; |
0f3b6849 CW |
320 | u32 derrmr; |
321 | u32 forcewake; | |
585b0288 BW |
322 | u32 error; /* gen6+ */ |
323 | u32 err_int; /* gen7 */ | |
324 | u32 done_reg; | |
91ec5d11 BW |
325 | u32 gac_eco; |
326 | u32 gam_ecochk; | |
327 | u32 gab_ctl; | |
328 | u32 gfx_mode; | |
585b0288 | 329 | u32 extra_instdone[I915_NUM_INSTDONE_REG]; |
585b0288 BW |
330 | u64 fence[I915_MAX_NUM_FENCES]; |
331 | struct intel_overlay_error_state *overlay; | |
332 | struct intel_display_error_state *display; | |
0ca36d78 | 333 | struct drm_i915_error_object *semaphore_obj; |
585b0288 | 334 | |
52d39a21 | 335 | struct drm_i915_error_ring { |
372fbb8e | 336 | bool valid; |
362b8af7 BW |
337 | /* Software tracked state */ |
338 | bool waiting; | |
339 | int hangcheck_score; | |
340 | enum intel_ring_hangcheck_action hangcheck_action; | |
341 | int num_requests; | |
342 | ||
343 | /* our own tracking of ring head and tail */ | |
344 | u32 cpu_ring_head; | |
345 | u32 cpu_ring_tail; | |
346 | ||
347 | u32 semaphore_seqno[I915_NUM_RINGS - 1]; | |
348 | ||
349 | /* Register state */ | |
350 | u32 tail; | |
351 | u32 head; | |
352 | u32 ctl; | |
353 | u32 hws; | |
354 | u32 ipeir; | |
355 | u32 ipehr; | |
356 | u32 instdone; | |
362b8af7 BW |
357 | u32 bbstate; |
358 | u32 instpm; | |
359 | u32 instps; | |
360 | u32 seqno; | |
361 | u64 bbaddr; | |
50877445 | 362 | u64 acthd; |
362b8af7 | 363 | u32 fault_reg; |
13ffadd1 | 364 | u64 faddr; |
362b8af7 BW |
365 | u32 rc_psmi; /* sleep state */ |
366 | u32 semaphore_mboxes[I915_NUM_RINGS - 1]; | |
367 | ||
52d39a21 CW |
368 | struct drm_i915_error_object { |
369 | int page_count; | |
370 | u32 gtt_offset; | |
371 | u32 *pages[0]; | |
ab0e7ff9 | 372 | } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page; |
362b8af7 | 373 | |
52d39a21 CW |
374 | struct drm_i915_error_request { |
375 | long jiffies; | |
376 | u32 seqno; | |
ee4f42b1 | 377 | u32 tail; |
52d39a21 | 378 | } *requests; |
6c7a01ec BW |
379 | |
380 | struct { | |
381 | u32 gfx_mode; | |
382 | union { | |
383 | u64 pdp[4]; | |
384 | u32 pp_dir_base; | |
385 | }; | |
386 | } vm_info; | |
ab0e7ff9 CW |
387 | |
388 | pid_t pid; | |
389 | char comm[TASK_COMM_LEN]; | |
52d39a21 | 390 | } ring[I915_NUM_RINGS]; |
9df30794 | 391 | struct drm_i915_error_buffer { |
a779e5ab | 392 | u32 size; |
9df30794 | 393 | u32 name; |
0201f1ec | 394 | u32 rseqno, wseqno; |
9df30794 CW |
395 | u32 gtt_offset; |
396 | u32 read_domains; | |
397 | u32 write_domain; | |
4b9de737 | 398 | s32 fence_reg:I915_MAX_NUM_FENCE_BITS; |
9df30794 CW |
399 | s32 pinned:2; |
400 | u32 tiling:2; | |
401 | u32 dirty:1; | |
402 | u32 purgeable:1; | |
5cc9ed4b | 403 | u32 userptr:1; |
5d1333fc | 404 | s32 ring:4; |
f56383cb | 405 | u32 cache_level:3; |
95f5301d | 406 | } **active_bo, **pinned_bo; |
6c7a01ec | 407 | |
95f5301d | 408 | u32 *active_bo_count, *pinned_bo_count; |
63eeaf38 JB |
409 | }; |
410 | ||
7bd688cd | 411 | struct intel_connector; |
b8cecdf5 | 412 | struct intel_crtc_config; |
46f297fb | 413 | struct intel_plane_config; |
0e8ffe1b | 414 | struct intel_crtc; |
ee9300bb DV |
415 | struct intel_limit; |
416 | struct dpll; | |
b8cecdf5 | 417 | |
e70236a8 | 418 | struct drm_i915_display_funcs { |
ee5382ae | 419 | bool (*fbc_enabled)(struct drm_device *dev); |
993495ae | 420 | void (*enable_fbc)(struct drm_crtc *crtc); |
e70236a8 JB |
421 | void (*disable_fbc)(struct drm_device *dev); |
422 | int (*get_display_clock_speed)(struct drm_device *dev); | |
423 | int (*get_fifo_size)(struct drm_device *dev, int plane); | |
ee9300bb DV |
424 | /** |
425 | * find_dpll() - Find the best values for the PLL | |
426 | * @limit: limits for the PLL | |
427 | * @crtc: current CRTC | |
428 | * @target: target frequency in kHz | |
429 | * @refclk: reference clock frequency in kHz | |
430 | * @match_clock: if provided, @best_clock P divider must | |
431 | * match the P divider from @match_clock | |
432 | * used for LVDS downclocking | |
433 | * @best_clock: best PLL values found | |
434 | * | |
435 | * Returns true on success, false on failure. | |
436 | */ | |
437 | bool (*find_dpll)(const struct intel_limit *limit, | |
438 | struct drm_crtc *crtc, | |
439 | int target, int refclk, | |
440 | struct dpll *match_clock, | |
441 | struct dpll *best_clock); | |
46ba614c | 442 | void (*update_wm)(struct drm_crtc *crtc); |
adf3d35e VS |
443 | void (*update_sprite_wm)(struct drm_plane *plane, |
444 | struct drm_crtc *crtc, | |
ed57cb8a DL |
445 | uint32_t sprite_width, uint32_t sprite_height, |
446 | int pixel_size, bool enable, bool scaled); | |
47fab737 | 447 | void (*modeset_global_resources)(struct drm_device *dev); |
0e8ffe1b DV |
448 | /* Returns the active state of the crtc, and if the crtc is active, |
449 | * fills out the pipe-config with the hw state. */ | |
450 | bool (*get_pipe_config)(struct intel_crtc *, | |
451 | struct intel_crtc_config *); | |
46f297fb JB |
452 | void (*get_plane_config)(struct intel_crtc *, |
453 | struct intel_plane_config *); | |
f564048e | 454 | int (*crtc_mode_set)(struct drm_crtc *crtc, |
f564048e EA |
455 | int x, int y, |
456 | struct drm_framebuffer *old_fb); | |
76e5a89c DV |
457 | void (*crtc_enable)(struct drm_crtc *crtc); |
458 | void (*crtc_disable)(struct drm_crtc *crtc); | |
ee7b9f93 | 459 | void (*off)(struct drm_crtc *crtc); |
e0dac65e | 460 | void (*write_eld)(struct drm_connector *connector, |
34427052 JN |
461 | struct drm_crtc *crtc, |
462 | struct drm_display_mode *mode); | |
674cf967 | 463 | void (*fdi_link_train)(struct drm_crtc *crtc); |
6067aaea | 464 | void (*init_clock_gating)(struct drm_device *dev); |
8c9f3aaf JB |
465 | int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc, |
466 | struct drm_framebuffer *fb, | |
ed8d1975 | 467 | struct drm_i915_gem_object *obj, |
a4872ba6 | 468 | struct intel_engine_cs *ring, |
ed8d1975 | 469 | uint32_t flags); |
29b9bde6 DV |
470 | void (*update_primary_plane)(struct drm_crtc *crtc, |
471 | struct drm_framebuffer *fb, | |
472 | int x, int y); | |
20afbda2 | 473 | void (*hpd_irq_setup)(struct drm_device *dev); |
e70236a8 JB |
474 | /* clock updates for mode set */ |
475 | /* cursor updates */ | |
476 | /* render clock increase/decrease */ | |
477 | /* display clock increase/decrease */ | |
478 | /* pll clock increase/decrease */ | |
7bd688cd JN |
479 | |
480 | int (*setup_backlight)(struct intel_connector *connector); | |
7bd688cd JN |
481 | uint32_t (*get_backlight)(struct intel_connector *connector); |
482 | void (*set_backlight)(struct intel_connector *connector, | |
483 | uint32_t level); | |
484 | void (*disable_backlight)(struct intel_connector *connector); | |
485 | void (*enable_backlight)(struct intel_connector *connector); | |
e70236a8 JB |
486 | }; |
487 | ||
907b28c5 | 488 | struct intel_uncore_funcs { |
c8d9a590 D |
489 | void (*force_wake_get)(struct drm_i915_private *dev_priv, |
490 | int fw_engine); | |
491 | void (*force_wake_put)(struct drm_i915_private *dev_priv, | |
492 | int fw_engine); | |
0b274481 BW |
493 | |
494 | uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, off_t offset, bool trace); | |
495 | uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, off_t offset, bool trace); | |
496 | uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, off_t offset, bool trace); | |
497 | uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, off_t offset, bool trace); | |
498 | ||
499 | void (*mmio_writeb)(struct drm_i915_private *dev_priv, off_t offset, | |
500 | uint8_t val, bool trace); | |
501 | void (*mmio_writew)(struct drm_i915_private *dev_priv, off_t offset, | |
502 | uint16_t val, bool trace); | |
503 | void (*mmio_writel)(struct drm_i915_private *dev_priv, off_t offset, | |
504 | uint32_t val, bool trace); | |
505 | void (*mmio_writeq)(struct drm_i915_private *dev_priv, off_t offset, | |
506 | uint64_t val, bool trace); | |
990bbdad CW |
507 | }; |
508 | ||
907b28c5 CW |
509 | struct intel_uncore { |
510 | spinlock_t lock; /** lock is also taken in irq contexts. */ | |
511 | ||
512 | struct intel_uncore_funcs funcs; | |
513 | ||
514 | unsigned fifo_count; | |
515 | unsigned forcewake_count; | |
aec347ab | 516 | |
940aece4 D |
517 | unsigned fw_rendercount; |
518 | unsigned fw_mediacount; | |
519 | ||
8232644c | 520 | struct timer_list force_wake_timer; |
907b28c5 CW |
521 | }; |
522 | ||
79fc46df DL |
523 | #define DEV_INFO_FOR_EACH_FLAG(func, sep) \ |
524 | func(is_mobile) sep \ | |
525 | func(is_i85x) sep \ | |
526 | func(is_i915g) sep \ | |
527 | func(is_i945gm) sep \ | |
528 | func(is_g33) sep \ | |
529 | func(need_gfx_hws) sep \ | |
530 | func(is_g4x) sep \ | |
531 | func(is_pineview) sep \ | |
532 | func(is_broadwater) sep \ | |
533 | func(is_crestline) sep \ | |
534 | func(is_ivybridge) sep \ | |
535 | func(is_valleyview) sep \ | |
536 | func(is_haswell) sep \ | |
b833d685 | 537 | func(is_preliminary) sep \ |
79fc46df DL |
538 | func(has_fbc) sep \ |
539 | func(has_pipe_cxsr) sep \ | |
540 | func(has_hotplug) sep \ | |
541 | func(cursor_needs_physical) sep \ | |
542 | func(has_overlay) sep \ | |
543 | func(overlay_needs_physical) sep \ | |
544 | func(supports_tv) sep \ | |
dd93be58 | 545 | func(has_llc) sep \ |
30568c45 DL |
546 | func(has_ddi) sep \ |
547 | func(has_fpga_dbg) | |
c96ea64e | 548 | |
a587f779 DL |
549 | #define DEFINE_FLAG(name) u8 name:1 |
550 | #define SEP_SEMICOLON ; | |
c96ea64e | 551 | |
cfdf1fa2 | 552 | struct intel_device_info { |
10fce67a | 553 | u32 display_mmio_offset; |
7eb552ae | 554 | u8 num_pipes:3; |
d615a166 | 555 | u8 num_sprites[I915_MAX_PIPES]; |
c96c3a8c | 556 | u8 gen; |
73ae478c | 557 | u8 ring_mask; /* Rings supported by the HW */ |
a587f779 | 558 | DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON); |
a57c774a AK |
559 | /* Register offsets for the various display pipes and transcoders */ |
560 | int pipe_offsets[I915_MAX_TRANSCODERS]; | |
561 | int trans_offsets[I915_MAX_TRANSCODERS]; | |
a57c774a | 562 | int palette_offsets[I915_MAX_PIPES]; |
5efb3e28 | 563 | int cursor_offsets[I915_MAX_PIPES]; |
cfdf1fa2 KH |
564 | }; |
565 | ||
a587f779 DL |
566 | #undef DEFINE_FLAG |
567 | #undef SEP_SEMICOLON | |
568 | ||
7faf1ab2 DV |
569 | enum i915_cache_level { |
570 | I915_CACHE_NONE = 0, | |
350ec881 CW |
571 | I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */ |
572 | I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc | |
573 | caches, eg sampler/render caches, and the | |
574 | large Last-Level-Cache. LLC is coherent with | |
575 | the CPU, but L3 is only visible to the GPU. */ | |
651d794f | 576 | I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */ |
7faf1ab2 DV |
577 | }; |
578 | ||
e59ec13d MK |
579 | struct i915_ctx_hang_stats { |
580 | /* This context had batch pending when hang was declared */ | |
581 | unsigned batch_pending; | |
582 | ||
583 | /* This context had batch active when hang was declared */ | |
584 | unsigned batch_active; | |
be62acb4 MK |
585 | |
586 | /* Time when this context was last blamed for a GPU reset */ | |
587 | unsigned long guilty_ts; | |
588 | ||
589 | /* This context is banned to submit more work */ | |
590 | bool banned; | |
e59ec13d | 591 | }; |
40521054 BW |
592 | |
593 | /* This must match up with the value previously used for execbuf2.rsvd1. */ | |
821d66dd | 594 | #define DEFAULT_CONTEXT_HANDLE 0 |
31b7a88d OM |
595 | /** |
596 | * struct intel_context - as the name implies, represents a context. | |
597 | * @ref: reference count. | |
598 | * @user_handle: userspace tracking identity for this context. | |
599 | * @remap_slice: l3 row remapping information. | |
600 | * @file_priv: filp associated with this context (NULL for global default | |
601 | * context). | |
602 | * @hang_stats: information about the role of this context in possible GPU | |
603 | * hangs. | |
604 | * @vm: virtual memory space used by this context. | |
605 | * @legacy_hw_ctx: render context backing object and whether it is correctly | |
606 | * initialized (legacy ring submission mechanism only). | |
607 | * @link: link in the global list of contexts. | |
608 | * | |
609 | * Contexts are memory images used by the hardware to store copies of their | |
610 | * internal state. | |
611 | */ | |
273497e5 | 612 | struct intel_context { |
dce3271b | 613 | struct kref ref; |
821d66dd | 614 | int user_handle; |
3ccfd19d | 615 | uint8_t remap_slice; |
40521054 | 616 | struct drm_i915_file_private *file_priv; |
e59ec13d | 617 | struct i915_ctx_hang_stats hang_stats; |
c7c48dfd | 618 | struct i915_address_space *vm; |
a33afea5 | 619 | |
ea0c76f8 OM |
620 | struct { |
621 | struct drm_i915_gem_object *rcs_state; | |
622 | bool initialized; | |
623 | } legacy_hw_ctx; | |
624 | ||
a33afea5 | 625 | struct list_head link; |
40521054 BW |
626 | }; |
627 | ||
5c3fe8b0 BW |
628 | struct i915_fbc { |
629 | unsigned long size; | |
5e59f717 | 630 | unsigned threshold; |
5c3fe8b0 BW |
631 | unsigned int fb_id; |
632 | enum plane plane; | |
633 | int y; | |
634 | ||
c4213885 | 635 | struct drm_mm_node compressed_fb; |
5c3fe8b0 BW |
636 | struct drm_mm_node *compressed_llb; |
637 | ||
638 | struct intel_fbc_work { | |
639 | struct delayed_work work; | |
640 | struct drm_crtc *crtc; | |
641 | struct drm_framebuffer *fb; | |
5c3fe8b0 BW |
642 | } *fbc_work; |
643 | ||
29ebf90f CW |
644 | enum no_fbc_reason { |
645 | FBC_OK, /* FBC is enabled */ | |
646 | FBC_UNSUPPORTED, /* FBC is not supported by this chipset */ | |
5c3fe8b0 BW |
647 | FBC_NO_OUTPUT, /* no outputs enabled to compress */ |
648 | FBC_STOLEN_TOO_SMALL, /* not enough space for buffers */ | |
649 | FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */ | |
650 | FBC_MODE_TOO_LARGE, /* mode too large for compression */ | |
651 | FBC_BAD_PLANE, /* fbc not supported on plane */ | |
652 | FBC_NOT_TILED, /* buffer not tiled */ | |
653 | FBC_MULTIPLE_PIPES, /* more than one pipe active */ | |
654 | FBC_MODULE_PARAM, | |
655 | FBC_CHIP_DEFAULT, /* disabled by default on this chip */ | |
656 | } no_fbc_reason; | |
b5e50c3f JB |
657 | }; |
658 | ||
439d7ac0 PB |
659 | struct i915_drrs { |
660 | struct intel_connector *connector; | |
661 | }; | |
662 | ||
2807cf69 | 663 | struct intel_dp; |
a031d709 | 664 | struct i915_psr { |
f0355c4a | 665 | struct mutex lock; |
a031d709 RV |
666 | bool sink_support; |
667 | bool source_ok; | |
2807cf69 | 668 | struct intel_dp *enabled; |
7c8f8a70 RV |
669 | bool active; |
670 | struct delayed_work work; | |
9ca15301 | 671 | unsigned busy_frontbuffer_bits; |
3f51e471 | 672 | }; |
5c3fe8b0 | 673 | |
3bad0781 | 674 | enum intel_pch { |
f0350830 | 675 | PCH_NONE = 0, /* No PCH present */ |
3bad0781 ZW |
676 | PCH_IBX, /* Ibexpeak PCH */ |
677 | PCH_CPT, /* Cougarpoint PCH */ | |
eb877ebf | 678 | PCH_LPT, /* Lynxpoint PCH */ |
40c7ead9 | 679 | PCH_NOP, |
3bad0781 ZW |
680 | }; |
681 | ||
988d6ee8 PZ |
682 | enum intel_sbi_destination { |
683 | SBI_ICLK, | |
684 | SBI_MPHY, | |
685 | }; | |
686 | ||
b690e96c | 687 | #define QUIRK_PIPEA_FORCE (1<<0) |
435793df | 688 | #define QUIRK_LVDS_SSC_DISABLE (1<<1) |
4dca20ef | 689 | #define QUIRK_INVERT_BRIGHTNESS (1<<2) |
9c72cc6f | 690 | #define QUIRK_BACKLIGHT_PRESENT (1<<3) |
b690e96c | 691 | |
8be48d92 | 692 | struct intel_fbdev; |
1630fe75 | 693 | struct intel_fbc_work; |
38651674 | 694 | |
c2b9152f DV |
695 | struct intel_gmbus { |
696 | struct i2c_adapter adapter; | |
f2ce9faf | 697 | u32 force_bit; |
c2b9152f | 698 | u32 reg0; |
36c785f0 | 699 | u32 gpio_reg; |
c167a6fc | 700 | struct i2c_algo_bit_data bit_algo; |
c2b9152f DV |
701 | struct drm_i915_private *dev_priv; |
702 | }; | |
703 | ||
f4c956ad | 704 | struct i915_suspend_saved_registers { |
ba8bbcf6 JB |
705 | u8 saveLBB; |
706 | u32 saveDSPACNTR; | |
707 | u32 saveDSPBCNTR; | |
e948e994 | 708 | u32 saveDSPARB; |
ba8bbcf6 JB |
709 | u32 savePIPEACONF; |
710 | u32 savePIPEBCONF; | |
711 | u32 savePIPEASRC; | |
712 | u32 savePIPEBSRC; | |
713 | u32 saveFPA0; | |
714 | u32 saveFPA1; | |
715 | u32 saveDPLL_A; | |
716 | u32 saveDPLL_A_MD; | |
717 | u32 saveHTOTAL_A; | |
718 | u32 saveHBLANK_A; | |
719 | u32 saveHSYNC_A; | |
720 | u32 saveVTOTAL_A; | |
721 | u32 saveVBLANK_A; | |
722 | u32 saveVSYNC_A; | |
723 | u32 saveBCLRPAT_A; | |
5586c8bc | 724 | u32 saveTRANSACONF; |
42048781 ZW |
725 | u32 saveTRANS_HTOTAL_A; |
726 | u32 saveTRANS_HBLANK_A; | |
727 | u32 saveTRANS_HSYNC_A; | |
728 | u32 saveTRANS_VTOTAL_A; | |
729 | u32 saveTRANS_VBLANK_A; | |
730 | u32 saveTRANS_VSYNC_A; | |
0da3ea12 | 731 | u32 savePIPEASTAT; |
ba8bbcf6 JB |
732 | u32 saveDSPASTRIDE; |
733 | u32 saveDSPASIZE; | |
734 | u32 saveDSPAPOS; | |
585fb111 | 735 | u32 saveDSPAADDR; |
ba8bbcf6 JB |
736 | u32 saveDSPASURF; |
737 | u32 saveDSPATILEOFF; | |
738 | u32 savePFIT_PGM_RATIOS; | |
0eb96d6e | 739 | u32 saveBLC_HIST_CTL; |
ba8bbcf6 JB |
740 | u32 saveBLC_PWM_CTL; |
741 | u32 saveBLC_PWM_CTL2; | |
07bf139b | 742 | u32 saveBLC_HIST_CTL_B; |
42048781 ZW |
743 | u32 saveBLC_CPU_PWM_CTL; |
744 | u32 saveBLC_CPU_PWM_CTL2; | |
ba8bbcf6 JB |
745 | u32 saveFPB0; |
746 | u32 saveFPB1; | |
747 | u32 saveDPLL_B; | |
748 | u32 saveDPLL_B_MD; | |
749 | u32 saveHTOTAL_B; | |
750 | u32 saveHBLANK_B; | |
751 | u32 saveHSYNC_B; | |
752 | u32 saveVTOTAL_B; | |
753 | u32 saveVBLANK_B; | |
754 | u32 saveVSYNC_B; | |
755 | u32 saveBCLRPAT_B; | |
5586c8bc | 756 | u32 saveTRANSBCONF; |
42048781 ZW |
757 | u32 saveTRANS_HTOTAL_B; |
758 | u32 saveTRANS_HBLANK_B; | |
759 | u32 saveTRANS_HSYNC_B; | |
760 | u32 saveTRANS_VTOTAL_B; | |
761 | u32 saveTRANS_VBLANK_B; | |
762 | u32 saveTRANS_VSYNC_B; | |
0da3ea12 | 763 | u32 savePIPEBSTAT; |
ba8bbcf6 JB |
764 | u32 saveDSPBSTRIDE; |
765 | u32 saveDSPBSIZE; | |
766 | u32 saveDSPBPOS; | |
585fb111 | 767 | u32 saveDSPBADDR; |
ba8bbcf6 JB |
768 | u32 saveDSPBSURF; |
769 | u32 saveDSPBTILEOFF; | |
585fb111 JB |
770 | u32 saveVGA0; |
771 | u32 saveVGA1; | |
772 | u32 saveVGA_PD; | |
ba8bbcf6 JB |
773 | u32 saveVGACNTRL; |
774 | u32 saveADPA; | |
775 | u32 saveLVDS; | |
585fb111 JB |
776 | u32 savePP_ON_DELAYS; |
777 | u32 savePP_OFF_DELAYS; | |
ba8bbcf6 JB |
778 | u32 saveDVOA; |
779 | u32 saveDVOB; | |
780 | u32 saveDVOC; | |
781 | u32 savePP_ON; | |
782 | u32 savePP_OFF; | |
783 | u32 savePP_CONTROL; | |
585fb111 | 784 | u32 savePP_DIVISOR; |
ba8bbcf6 JB |
785 | u32 savePFIT_CONTROL; |
786 | u32 save_palette_a[256]; | |
787 | u32 save_palette_b[256]; | |
ba8bbcf6 | 788 | u32 saveFBC_CONTROL; |
0da3ea12 JB |
789 | u32 saveIER; |
790 | u32 saveIIR; | |
791 | u32 saveIMR; | |
42048781 ZW |
792 | u32 saveDEIER; |
793 | u32 saveDEIMR; | |
794 | u32 saveGTIER; | |
795 | u32 saveGTIMR; | |
796 | u32 saveFDI_RXA_IMR; | |
797 | u32 saveFDI_RXB_IMR; | |
1f84e550 | 798 | u32 saveCACHE_MODE_0; |
1f84e550 | 799 | u32 saveMI_ARB_STATE; |
ba8bbcf6 JB |
800 | u32 saveSWF0[16]; |
801 | u32 saveSWF1[16]; | |
802 | u32 saveSWF2[3]; | |
803 | u8 saveMSR; | |
804 | u8 saveSR[8]; | |
123f794f | 805 | u8 saveGR[25]; |
ba8bbcf6 | 806 | u8 saveAR_INDEX; |
a59e122a | 807 | u8 saveAR[21]; |
ba8bbcf6 | 808 | u8 saveDACMASK; |
a59e122a | 809 | u8 saveCR[37]; |
4b9de737 | 810 | uint64_t saveFENCE[I915_MAX_NUM_FENCES]; |
1fd1c624 EA |
811 | u32 saveCURACNTR; |
812 | u32 saveCURAPOS; | |
813 | u32 saveCURABASE; | |
814 | u32 saveCURBCNTR; | |
815 | u32 saveCURBPOS; | |
816 | u32 saveCURBBASE; | |
817 | u32 saveCURSIZE; | |
a4fc5ed6 KP |
818 | u32 saveDP_B; |
819 | u32 saveDP_C; | |
820 | u32 saveDP_D; | |
821 | u32 savePIPEA_GMCH_DATA_M; | |
822 | u32 savePIPEB_GMCH_DATA_M; | |
823 | u32 savePIPEA_GMCH_DATA_N; | |
824 | u32 savePIPEB_GMCH_DATA_N; | |
825 | u32 savePIPEA_DP_LINK_M; | |
826 | u32 savePIPEB_DP_LINK_M; | |
827 | u32 savePIPEA_DP_LINK_N; | |
828 | u32 savePIPEB_DP_LINK_N; | |
42048781 ZW |
829 | u32 saveFDI_RXA_CTL; |
830 | u32 saveFDI_TXA_CTL; | |
831 | u32 saveFDI_RXB_CTL; | |
832 | u32 saveFDI_TXB_CTL; | |
833 | u32 savePFA_CTL_1; | |
834 | u32 savePFB_CTL_1; | |
835 | u32 savePFA_WIN_SZ; | |
836 | u32 savePFB_WIN_SZ; | |
837 | u32 savePFA_WIN_POS; | |
838 | u32 savePFB_WIN_POS; | |
5586c8bc ZW |
839 | u32 savePCH_DREF_CONTROL; |
840 | u32 saveDISP_ARB_CTL; | |
841 | u32 savePIPEA_DATA_M1; | |
842 | u32 savePIPEA_DATA_N1; | |
843 | u32 savePIPEA_LINK_M1; | |
844 | u32 savePIPEA_LINK_N1; | |
845 | u32 savePIPEB_DATA_M1; | |
846 | u32 savePIPEB_DATA_N1; | |
847 | u32 savePIPEB_LINK_M1; | |
848 | u32 savePIPEB_LINK_N1; | |
b5b72e89 | 849 | u32 saveMCHBAR_RENDER_STANDBY; |
cda2bb78 | 850 | u32 savePCH_PORT_HOTPLUG; |
f4c956ad | 851 | }; |
c85aa885 | 852 | |
ddeea5b0 ID |
853 | struct vlv_s0ix_state { |
854 | /* GAM */ | |
855 | u32 wr_watermark; | |
856 | u32 gfx_prio_ctrl; | |
857 | u32 arb_mode; | |
858 | u32 gfx_pend_tlb0; | |
859 | u32 gfx_pend_tlb1; | |
860 | u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM]; | |
861 | u32 media_max_req_count; | |
862 | u32 gfx_max_req_count; | |
863 | u32 render_hwsp; | |
864 | u32 ecochk; | |
865 | u32 bsd_hwsp; | |
866 | u32 blt_hwsp; | |
867 | u32 tlb_rd_addr; | |
868 | ||
869 | /* MBC */ | |
870 | u32 g3dctl; | |
871 | u32 gsckgctl; | |
872 | u32 mbctl; | |
873 | ||
874 | /* GCP */ | |
875 | u32 ucgctl1; | |
876 | u32 ucgctl3; | |
877 | u32 rcgctl1; | |
878 | u32 rcgctl2; | |
879 | u32 rstctl; | |
880 | u32 misccpctl; | |
881 | ||
882 | /* GPM */ | |
883 | u32 gfxpause; | |
884 | u32 rpdeuhwtc; | |
885 | u32 rpdeuc; | |
886 | u32 ecobus; | |
887 | u32 pwrdwnupctl; | |
888 | u32 rp_down_timeout; | |
889 | u32 rp_deucsw; | |
890 | u32 rcubmabdtmr; | |
891 | u32 rcedata; | |
892 | u32 spare2gh; | |
893 | ||
894 | /* Display 1 CZ domain */ | |
895 | u32 gt_imr; | |
896 | u32 gt_ier; | |
897 | u32 pm_imr; | |
898 | u32 pm_ier; | |
899 | u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM]; | |
900 | ||
901 | /* GT SA CZ domain */ | |
902 | u32 tilectl; | |
903 | u32 gt_fifoctl; | |
904 | u32 gtlc_wake_ctrl; | |
905 | u32 gtlc_survive; | |
906 | u32 pmwgicz; | |
907 | ||
908 | /* Display 2 CZ domain */ | |
909 | u32 gu_ctl0; | |
910 | u32 gu_ctl1; | |
911 | u32 clock_gate_dis2; | |
912 | }; | |
913 | ||
bf225f20 CW |
914 | struct intel_rps_ei { |
915 | u32 cz_clock; | |
916 | u32 render_c0; | |
917 | u32 media_c0; | |
31685c25 D |
918 | }; |
919 | ||
c85aa885 | 920 | struct intel_gen6_power_mgmt { |
59cdb63d | 921 | /* work and pm_iir are protected by dev_priv->irq_lock */ |
c85aa885 DV |
922 | struct work_struct work; |
923 | u32 pm_iir; | |
59cdb63d | 924 | |
b39fb297 BW |
925 | /* Frequencies are stored in potentially platform dependent multiples. |
926 | * In other words, *_freq needs to be multiplied by X to be interesting. | |
927 | * Soft limits are those which are used for the dynamic reclocking done | |
928 | * by the driver (raise frequencies under heavy loads, and lower for | |
929 | * lighter loads). Hard limits are those imposed by the hardware. | |
930 | * | |
931 | * A distinction is made for overclocking, which is never enabled by | |
932 | * default, and is considered to be above the hard limit if it's | |
933 | * possible at all. | |
934 | */ | |
935 | u8 cur_freq; /* Current frequency (cached, may not == HW) */ | |
936 | u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */ | |
937 | u8 max_freq_softlimit; /* Max frequency permitted by the driver */ | |
938 | u8 max_freq; /* Maximum frequency, RP0 if not overclocking */ | |
939 | u8 min_freq; /* AKA RPn. Minimum frequency */ | |
940 | u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */ | |
941 | u8 rp1_freq; /* "less than" RP0 power/freqency */ | |
942 | u8 rp0_freq; /* Non-overclocked max frequency. */ | |
67c3bf6f | 943 | u32 cz_freq; |
1a01ab3b | 944 | |
31685c25 | 945 | u32 ei_interrupt_count; |
1a01ab3b | 946 | |
dd75fdc8 CW |
947 | int last_adj; |
948 | enum { LOW_POWER, BETWEEN, HIGH_POWER } power; | |
949 | ||
c0951f0c | 950 | bool enabled; |
1a01ab3b | 951 | struct delayed_work delayed_resume_work; |
4fc688ce | 952 | |
bf225f20 CW |
953 | /* manual wa residency calculations */ |
954 | struct intel_rps_ei up_ei, down_ei; | |
955 | ||
4fc688ce JB |
956 | /* |
957 | * Protects RPS/RC6 register access and PCU communication. | |
958 | * Must be taken after struct_mutex if nested. | |
959 | */ | |
960 | struct mutex hw_lock; | |
c85aa885 DV |
961 | }; |
962 | ||
1a240d4d DV |
963 | /* defined intel_pm.c */ |
964 | extern spinlock_t mchdev_lock; | |
965 | ||
c85aa885 DV |
966 | struct intel_ilk_power_mgmt { |
967 | u8 cur_delay; | |
968 | u8 min_delay; | |
969 | u8 max_delay; | |
970 | u8 fmax; | |
971 | u8 fstart; | |
972 | ||
973 | u64 last_count1; | |
974 | unsigned long last_time1; | |
975 | unsigned long chipset_power; | |
976 | u64 last_count2; | |
5ed0bdf2 | 977 | u64 last_time2; |
c85aa885 DV |
978 | unsigned long gfx_power; |
979 | u8 corr; | |
980 | ||
981 | int c_m; | |
982 | int r_t; | |
3e373948 DV |
983 | |
984 | struct drm_i915_gem_object *pwrctx; | |
985 | struct drm_i915_gem_object *renderctx; | |
c85aa885 DV |
986 | }; |
987 | ||
c6cb582e ID |
988 | struct drm_i915_private; |
989 | struct i915_power_well; | |
990 | ||
991 | struct i915_power_well_ops { | |
992 | /* | |
993 | * Synchronize the well's hw state to match the current sw state, for | |
994 | * example enable/disable it based on the current refcount. Called | |
995 | * during driver init and resume time, possibly after first calling | |
996 | * the enable/disable handlers. | |
997 | */ | |
998 | void (*sync_hw)(struct drm_i915_private *dev_priv, | |
999 | struct i915_power_well *power_well); | |
1000 | /* | |
1001 | * Enable the well and resources that depend on it (for example | |
1002 | * interrupts located on the well). Called after the 0->1 refcount | |
1003 | * transition. | |
1004 | */ | |
1005 | void (*enable)(struct drm_i915_private *dev_priv, | |
1006 | struct i915_power_well *power_well); | |
1007 | /* | |
1008 | * Disable the well and resources that depend on it. Called after | |
1009 | * the 1->0 refcount transition. | |
1010 | */ | |
1011 | void (*disable)(struct drm_i915_private *dev_priv, | |
1012 | struct i915_power_well *power_well); | |
1013 | /* Returns the hw enabled state. */ | |
1014 | bool (*is_enabled)(struct drm_i915_private *dev_priv, | |
1015 | struct i915_power_well *power_well); | |
1016 | }; | |
1017 | ||
a38911a3 WX |
1018 | /* Power well structure for haswell */ |
1019 | struct i915_power_well { | |
c1ca727f | 1020 | const char *name; |
6f3ef5dd | 1021 | bool always_on; |
a38911a3 WX |
1022 | /* power well enable/disable usage count */ |
1023 | int count; | |
bfafe93a ID |
1024 | /* cached hw enabled state */ |
1025 | bool hw_enabled; | |
c1ca727f | 1026 | unsigned long domains; |
77961eb9 | 1027 | unsigned long data; |
c6cb582e | 1028 | const struct i915_power_well_ops *ops; |
a38911a3 WX |
1029 | }; |
1030 | ||
83c00f55 | 1031 | struct i915_power_domains { |
baa70707 ID |
1032 | /* |
1033 | * Power wells needed for initialization at driver init and suspend | |
1034 | * time are on. They are kept on until after the first modeset. | |
1035 | */ | |
1036 | bool init_power_on; | |
0d116a29 | 1037 | bool initializing; |
c1ca727f | 1038 | int power_well_count; |
baa70707 | 1039 | |
83c00f55 | 1040 | struct mutex lock; |
1da51581 | 1041 | int domain_use_count[POWER_DOMAIN_NUM]; |
c1ca727f | 1042 | struct i915_power_well *power_wells; |
83c00f55 ID |
1043 | }; |
1044 | ||
231f42a4 DV |
1045 | struct i915_dri1_state { |
1046 | unsigned allow_batchbuffer : 1; | |
1047 | u32 __iomem *gfx_hws_cpu_addr; | |
1048 | ||
1049 | unsigned int cpp; | |
1050 | int back_offset; | |
1051 | int front_offset; | |
1052 | int current_page; | |
1053 | int page_flipping; | |
1054 | ||
1055 | uint32_t counter; | |
1056 | }; | |
1057 | ||
db1b76ca DV |
1058 | struct i915_ums_state { |
1059 | /** | |
1060 | * Flag if the X Server, and thus DRM, is not currently in | |
1061 | * control of the device. | |
1062 | * | |
1063 | * This is set between LeaveVT and EnterVT. It needs to be | |
1064 | * replaced with a semaphore. It also needs to be | |
1065 | * transitioned away from for kernel modesetting. | |
1066 | */ | |
1067 | int mm_suspended; | |
1068 | }; | |
1069 | ||
35a85ac6 | 1070 | #define MAX_L3_SLICES 2 |
a4da4fa4 | 1071 | struct intel_l3_parity { |
35a85ac6 | 1072 | u32 *remap_info[MAX_L3_SLICES]; |
a4da4fa4 | 1073 | struct work_struct error_work; |
35a85ac6 | 1074 | int which_slice; |
a4da4fa4 DV |
1075 | }; |
1076 | ||
4b5aed62 | 1077 | struct i915_gem_mm { |
4b5aed62 DV |
1078 | /** Memory allocator for GTT stolen memory */ |
1079 | struct drm_mm stolen; | |
4b5aed62 DV |
1080 | /** List of all objects in gtt_space. Used to restore gtt |
1081 | * mappings on resume */ | |
1082 | struct list_head bound_list; | |
1083 | /** | |
1084 | * List of objects which are not bound to the GTT (thus | |
1085 | * are idle and not used by the GPU) but still have | |
1086 | * (presumably uncached) pages still attached. | |
1087 | */ | |
1088 | struct list_head unbound_list; | |
1089 | ||
1090 | /** Usable portion of the GTT for GEM */ | |
1091 | unsigned long stolen_base; /* limited to low memory (32-bit) */ | |
1092 | ||
4b5aed62 DV |
1093 | /** PPGTT used for aliasing the PPGTT with the GTT */ |
1094 | struct i915_hw_ppgtt *aliasing_ppgtt; | |
1095 | ||
2cfcd32a | 1096 | struct notifier_block oom_notifier; |
ceabbba5 | 1097 | struct shrinker shrinker; |
4b5aed62 DV |
1098 | bool shrinker_no_lock_stealing; |
1099 | ||
4b5aed62 DV |
1100 | /** LRU list of objects with fence regs on them. */ |
1101 | struct list_head fence_list; | |
1102 | ||
1103 | /** | |
1104 | * We leave the user IRQ off as much as possible, | |
1105 | * but this means that requests will finish and never | |
1106 | * be retired once the system goes idle. Set a timer to | |
1107 | * fire periodically while the ring is running. When it | |
1108 | * fires, go retire requests. | |
1109 | */ | |
1110 | struct delayed_work retire_work; | |
1111 | ||
b29c19b6 CW |
1112 | /** |
1113 | * When we detect an idle GPU, we want to turn on | |
1114 | * powersaving features. So once we see that there | |
1115 | * are no more requests outstanding and no more | |
1116 | * arrive within a small period of time, we fire | |
1117 | * off the idle_work. | |
1118 | */ | |
1119 | struct delayed_work idle_work; | |
1120 | ||
4b5aed62 DV |
1121 | /** |
1122 | * Are we in a non-interruptible section of code like | |
1123 | * modesetting? | |
1124 | */ | |
1125 | bool interruptible; | |
1126 | ||
f62a0076 CW |
1127 | /** |
1128 | * Is the GPU currently considered idle, or busy executing userspace | |
1129 | * requests? Whilst idle, we attempt to power down the hardware and | |
1130 | * display clocks. In order to reduce the effect on performance, there | |
1131 | * is a slight delay before we do so. | |
1132 | */ | |
1133 | bool busy; | |
1134 | ||
bdf1e7e3 DV |
1135 | /* the indicator for dispatch video commands on two BSD rings */ |
1136 | int bsd_ring_dispatch_index; | |
1137 | ||
4b5aed62 DV |
1138 | /** Bit 6 swizzling required for X tiling */ |
1139 | uint32_t bit_6_swizzle_x; | |
1140 | /** Bit 6 swizzling required for Y tiling */ | |
1141 | uint32_t bit_6_swizzle_y; | |
1142 | ||
4b5aed62 | 1143 | /* accounting, useful for userland debugging */ |
c20e8355 | 1144 | spinlock_t object_stat_lock; |
4b5aed62 DV |
1145 | size_t object_memory; |
1146 | u32 object_count; | |
1147 | }; | |
1148 | ||
edc3d884 MK |
1149 | struct drm_i915_error_state_buf { |
1150 | unsigned bytes; | |
1151 | unsigned size; | |
1152 | int err; | |
1153 | u8 *buf; | |
1154 | loff_t start; | |
1155 | loff_t pos; | |
1156 | }; | |
1157 | ||
fc16b48b MK |
1158 | struct i915_error_state_file_priv { |
1159 | struct drm_device *dev; | |
1160 | struct drm_i915_error_state *error; | |
1161 | }; | |
1162 | ||
99584db3 DV |
1163 | struct i915_gpu_error { |
1164 | /* For hangcheck timer */ | |
1165 | #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */ | |
1166 | #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD) | |
be62acb4 MK |
1167 | /* Hang gpu twice in this window and your context gets banned */ |
1168 | #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000) | |
1169 | ||
99584db3 | 1170 | struct timer_list hangcheck_timer; |
99584db3 DV |
1171 | |
1172 | /* For reset and error_state handling. */ | |
1173 | spinlock_t lock; | |
1174 | /* Protected by the above dev->gpu_error.lock. */ | |
1175 | struct drm_i915_error_state *first_error; | |
1176 | struct work_struct work; | |
99584db3 | 1177 | |
094f9a54 CW |
1178 | |
1179 | unsigned long missed_irq_rings; | |
1180 | ||
1f83fee0 | 1181 | /** |
2ac0f450 | 1182 | * State variable controlling the reset flow and count |
1f83fee0 | 1183 | * |
2ac0f450 MK |
1184 | * This is a counter which gets incremented when reset is triggered, |
1185 | * and again when reset has been handled. So odd values (lowest bit set) | |
1186 | * means that reset is in progress and even values that | |
1187 | * (reset_counter >> 1):th reset was successfully completed. | |
1188 | * | |
1189 | * If reset is not completed succesfully, the I915_WEDGE bit is | |
1190 | * set meaning that hardware is terminally sour and there is no | |
1191 | * recovery. All waiters on the reset_queue will be woken when | |
1192 | * that happens. | |
1193 | * | |
1194 | * This counter is used by the wait_seqno code to notice that reset | |
1195 | * event happened and it needs to restart the entire ioctl (since most | |
1196 | * likely the seqno it waited for won't ever signal anytime soon). | |
f69061be DV |
1197 | * |
1198 | * This is important for lock-free wait paths, where no contended lock | |
1199 | * naturally enforces the correct ordering between the bail-out of the | |
1200 | * waiter and the gpu reset work code. | |
1f83fee0 DV |
1201 | */ |
1202 | atomic_t reset_counter; | |
1203 | ||
1f83fee0 | 1204 | #define I915_RESET_IN_PROGRESS_FLAG 1 |
2ac0f450 | 1205 | #define I915_WEDGED (1 << 31) |
1f83fee0 DV |
1206 | |
1207 | /** | |
1208 | * Waitqueue to signal when the reset has completed. Used by clients | |
1209 | * that wait for dev_priv->mm.wedged to settle. | |
1210 | */ | |
1211 | wait_queue_head_t reset_queue; | |
33196ded | 1212 | |
88b4aa87 MK |
1213 | /* Userspace knobs for gpu hang simulation; |
1214 | * combines both a ring mask, and extra flags | |
1215 | */ | |
1216 | u32 stop_rings; | |
1217 | #define I915_STOP_RING_ALLOW_BAN (1 << 31) | |
1218 | #define I915_STOP_RING_ALLOW_WARN (1 << 30) | |
094f9a54 CW |
1219 | |
1220 | /* For missed irq/seqno simulation. */ | |
1221 | unsigned int test_irq_rings; | |
99584db3 DV |
1222 | }; |
1223 | ||
b8efb17b ZR |
1224 | enum modeset_restore { |
1225 | MODESET_ON_LID_OPEN, | |
1226 | MODESET_DONE, | |
1227 | MODESET_SUSPENDED, | |
1228 | }; | |
1229 | ||
6acab15a PZ |
1230 | struct ddi_vbt_port_info { |
1231 | uint8_t hdmi_level_shift; | |
311a2094 PZ |
1232 | |
1233 | uint8_t supports_dvi:1; | |
1234 | uint8_t supports_hdmi:1; | |
1235 | uint8_t supports_dp:1; | |
6acab15a PZ |
1236 | }; |
1237 | ||
83a7280e PB |
1238 | enum drrs_support_type { |
1239 | DRRS_NOT_SUPPORTED = 0, | |
1240 | STATIC_DRRS_SUPPORT = 1, | |
1241 | SEAMLESS_DRRS_SUPPORT = 2 | |
1242 | }; | |
1243 | ||
41aa3448 RV |
1244 | struct intel_vbt_data { |
1245 | struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ | |
1246 | struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ | |
1247 | ||
1248 | /* Feature bits */ | |
1249 | unsigned int int_tv_support:1; | |
1250 | unsigned int lvds_dither:1; | |
1251 | unsigned int lvds_vbt:1; | |
1252 | unsigned int int_crt_support:1; | |
1253 | unsigned int lvds_use_ssc:1; | |
1254 | unsigned int display_clock_mode:1; | |
1255 | unsigned int fdi_rx_polarity_inverted:1; | |
3e6bd011 | 1256 | unsigned int has_mipi:1; |
41aa3448 RV |
1257 | int lvds_ssc_freq; |
1258 | unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */ | |
1259 | ||
83a7280e PB |
1260 | enum drrs_support_type drrs_type; |
1261 | ||
41aa3448 RV |
1262 | /* eDP */ |
1263 | int edp_rate; | |
1264 | int edp_lanes; | |
1265 | int edp_preemphasis; | |
1266 | int edp_vswing; | |
1267 | bool edp_initialized; | |
1268 | bool edp_support; | |
1269 | int edp_bpp; | |
1270 | struct edp_power_seq edp_pps; | |
1271 | ||
f00076d2 JN |
1272 | struct { |
1273 | u16 pwm_freq_hz; | |
39fbc9c8 | 1274 | bool present; |
f00076d2 | 1275 | bool active_low_pwm; |
1de6068e | 1276 | u8 min_brightness; /* min_brightness/255 of max */ |
f00076d2 JN |
1277 | } backlight; |
1278 | ||
d17c5443 SK |
1279 | /* MIPI DSI */ |
1280 | struct { | |
3e6bd011 | 1281 | u16 port; |
d17c5443 | 1282 | u16 panel_id; |
d3b542fc SK |
1283 | struct mipi_config *config; |
1284 | struct mipi_pps_data *pps; | |
1285 | u8 seq_version; | |
1286 | u32 size; | |
1287 | u8 *data; | |
1288 | u8 *sequence[MIPI_SEQ_MAX]; | |
d17c5443 SK |
1289 | } dsi; |
1290 | ||
41aa3448 RV |
1291 | int crt_ddc_pin; |
1292 | ||
1293 | int child_dev_num; | |
768f69c9 | 1294 | union child_device_config *child_dev; |
6acab15a PZ |
1295 | |
1296 | struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS]; | |
41aa3448 RV |
1297 | }; |
1298 | ||
77c122bc VS |
1299 | enum intel_ddb_partitioning { |
1300 | INTEL_DDB_PART_1_2, | |
1301 | INTEL_DDB_PART_5_6, /* IVB+ */ | |
1302 | }; | |
1303 | ||
1fd527cc VS |
1304 | struct intel_wm_level { |
1305 | bool enable; | |
1306 | uint32_t pri_val; | |
1307 | uint32_t spr_val; | |
1308 | uint32_t cur_val; | |
1309 | uint32_t fbc_val; | |
1310 | }; | |
1311 | ||
820c1980 | 1312 | struct ilk_wm_values { |
609cedef VS |
1313 | uint32_t wm_pipe[3]; |
1314 | uint32_t wm_lp[3]; | |
1315 | uint32_t wm_lp_spr[3]; | |
1316 | uint32_t wm_linetime[3]; | |
1317 | bool enable_fbc_wm; | |
1318 | enum intel_ddb_partitioning partitioning; | |
1319 | }; | |
1320 | ||
c67a470b | 1321 | /* |
765dab67 PZ |
1322 | * This struct helps tracking the state needed for runtime PM, which puts the |
1323 | * device in PCI D3 state. Notice that when this happens, nothing on the | |
1324 | * graphics device works, even register access, so we don't get interrupts nor | |
1325 | * anything else. | |
c67a470b | 1326 | * |
765dab67 PZ |
1327 | * Every piece of our code that needs to actually touch the hardware needs to |
1328 | * either call intel_runtime_pm_get or call intel_display_power_get with the | |
1329 | * appropriate power domain. | |
a8a8bd54 | 1330 | * |
765dab67 PZ |
1331 | * Our driver uses the autosuspend delay feature, which means we'll only really |
1332 | * suspend if we stay with zero refcount for a certain amount of time. The | |
1333 | * default value is currently very conservative (see intel_init_runtime_pm), but | |
1334 | * it can be changed with the standard runtime PM files from sysfs. | |
c67a470b PZ |
1335 | * |
1336 | * The irqs_disabled variable becomes true exactly after we disable the IRQs and | |
1337 | * goes back to false exactly before we reenable the IRQs. We use this variable | |
1338 | * to check if someone is trying to enable/disable IRQs while they're supposed | |
1339 | * to be disabled. This shouldn't happen and we'll print some error messages in | |
730488b2 | 1340 | * case it happens. |
c67a470b | 1341 | * |
765dab67 | 1342 | * For more, read the Documentation/power/runtime_pm.txt. |
c67a470b | 1343 | */ |
5d584b2e PZ |
1344 | struct i915_runtime_pm { |
1345 | bool suspended; | |
9df7575f | 1346 | bool _irqs_disabled; |
c67a470b PZ |
1347 | }; |
1348 | ||
926321d5 DV |
1349 | enum intel_pipe_crc_source { |
1350 | INTEL_PIPE_CRC_SOURCE_NONE, | |
1351 | INTEL_PIPE_CRC_SOURCE_PLANE1, | |
1352 | INTEL_PIPE_CRC_SOURCE_PLANE2, | |
1353 | INTEL_PIPE_CRC_SOURCE_PF, | |
5b3a856b | 1354 | INTEL_PIPE_CRC_SOURCE_PIPE, |
3d099a05 DV |
1355 | /* TV/DP on pre-gen5/vlv can't use the pipe source. */ |
1356 | INTEL_PIPE_CRC_SOURCE_TV, | |
1357 | INTEL_PIPE_CRC_SOURCE_DP_B, | |
1358 | INTEL_PIPE_CRC_SOURCE_DP_C, | |
1359 | INTEL_PIPE_CRC_SOURCE_DP_D, | |
46a19188 | 1360 | INTEL_PIPE_CRC_SOURCE_AUTO, |
926321d5 DV |
1361 | INTEL_PIPE_CRC_SOURCE_MAX, |
1362 | }; | |
1363 | ||
8bf1e9f1 | 1364 | struct intel_pipe_crc_entry { |
ac2300d4 | 1365 | uint32_t frame; |
8bf1e9f1 SH |
1366 | uint32_t crc[5]; |
1367 | }; | |
1368 | ||
b2c88f5b | 1369 | #define INTEL_PIPE_CRC_ENTRIES_NR 128 |
8bf1e9f1 | 1370 | struct intel_pipe_crc { |
d538bbdf DL |
1371 | spinlock_t lock; |
1372 | bool opened; /* exclusive access to the result file */ | |
e5f75aca | 1373 | struct intel_pipe_crc_entry *entries; |
926321d5 | 1374 | enum intel_pipe_crc_source source; |
d538bbdf | 1375 | int head, tail; |
07144428 | 1376 | wait_queue_head_t wq; |
8bf1e9f1 SH |
1377 | }; |
1378 | ||
f99d7069 DV |
1379 | struct i915_frontbuffer_tracking { |
1380 | struct mutex lock; | |
1381 | ||
1382 | /* | |
1383 | * Tracking bits for delayed frontbuffer flushing du to gpu activity or | |
1384 | * scheduled flips. | |
1385 | */ | |
1386 | unsigned busy_bits; | |
1387 | unsigned flip_bits; | |
1388 | }; | |
1389 | ||
77fec556 | 1390 | struct drm_i915_private { |
f4c956ad | 1391 | struct drm_device *dev; |
42dcedd4 | 1392 | struct kmem_cache *slab; |
f4c956ad | 1393 | |
5c969aa7 | 1394 | const struct intel_device_info info; |
f4c956ad DV |
1395 | |
1396 | int relative_constants_mode; | |
1397 | ||
1398 | void __iomem *regs; | |
1399 | ||
907b28c5 | 1400 | struct intel_uncore uncore; |
f4c956ad DV |
1401 | |
1402 | struct intel_gmbus gmbus[GMBUS_NUM_PORTS]; | |
1403 | ||
28c70f16 | 1404 | |
f4c956ad DV |
1405 | /** gmbus_mutex protects against concurrent usage of the single hw gmbus |
1406 | * controller on different i2c buses. */ | |
1407 | struct mutex gmbus_mutex; | |
1408 | ||
1409 | /** | |
1410 | * Base address of the gmbus and gpio block. | |
1411 | */ | |
1412 | uint32_t gpio_mmio_base; | |
1413 | ||
b6fdd0f2 SS |
1414 | /* MMIO base address for MIPI regs */ |
1415 | uint32_t mipi_mmio_base; | |
1416 | ||
28c70f16 DV |
1417 | wait_queue_head_t gmbus_wait_queue; |
1418 | ||
f4c956ad | 1419 | struct pci_dev *bridge_dev; |
a4872ba6 | 1420 | struct intel_engine_cs ring[I915_NUM_RINGS]; |
3e78998a | 1421 | struct drm_i915_gem_object *semaphore_obj; |
f72b3435 | 1422 | uint32_t last_seqno, next_seqno; |
f4c956ad DV |
1423 | |
1424 | drm_dma_handle_t *status_page_dmah; | |
f4c956ad DV |
1425 | struct resource mch_res; |
1426 | ||
f4c956ad DV |
1427 | /* protects the irq masks */ |
1428 | spinlock_t irq_lock; | |
1429 | ||
84c33a64 SG |
1430 | /* protects the mmio flip data */ |
1431 | spinlock_t mmio_flip_lock; | |
1432 | ||
f8b79e58 ID |
1433 | bool display_irqs_enabled; |
1434 | ||
9ee32fea DV |
1435 | /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */ |
1436 | struct pm_qos_request pm_qos; | |
1437 | ||
f4c956ad | 1438 | /* DPIO indirect register protection */ |
09153000 | 1439 | struct mutex dpio_lock; |
f4c956ad DV |
1440 | |
1441 | /** Cached value of IMR to avoid reads in updating the bitfield */ | |
abd58f01 BW |
1442 | union { |
1443 | u32 irq_mask; | |
1444 | u32 de_irq_mask[I915_MAX_PIPES]; | |
1445 | }; | |
f4c956ad | 1446 | u32 gt_irq_mask; |
605cd25b | 1447 | u32 pm_irq_mask; |
a6706b45 | 1448 | u32 pm_rps_events; |
91d181dd | 1449 | u32 pipestat_irq_mask[I915_MAX_PIPES]; |
f4c956ad | 1450 | |
f4c956ad | 1451 | struct work_struct hotplug_work; |
b543fb04 EE |
1452 | struct { |
1453 | unsigned long hpd_last_jiffies; | |
1454 | int hpd_cnt; | |
1455 | enum { | |
1456 | HPD_ENABLED = 0, | |
1457 | HPD_DISABLED = 1, | |
1458 | HPD_MARK_DISABLED = 2 | |
1459 | } hpd_mark; | |
1460 | } hpd_stats[HPD_NUM_PINS]; | |
142e2398 | 1461 | u32 hpd_event_bits; |
6323751d | 1462 | struct delayed_work hotplug_reenable_work; |
f4c956ad | 1463 | |
5c3fe8b0 | 1464 | struct i915_fbc fbc; |
439d7ac0 | 1465 | struct i915_drrs drrs; |
f4c956ad | 1466 | struct intel_opregion opregion; |
41aa3448 | 1467 | struct intel_vbt_data vbt; |
f4c956ad DV |
1468 | |
1469 | /* overlay */ | |
1470 | struct intel_overlay *overlay; | |
f4c956ad | 1471 | |
58c68779 JN |
1472 | /* backlight registers and fields in struct intel_panel */ |
1473 | spinlock_t backlight_lock; | |
31ad8ec6 | 1474 | |
f4c956ad | 1475 | /* LVDS info */ |
f4c956ad DV |
1476 | bool no_aux_handshake; |
1477 | ||
f4c956ad DV |
1478 | struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */ |
1479 | int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */ | |
1480 | int num_fence_regs; /* 8 on pre-965, 16 otherwise */ | |
1481 | ||
1482 | unsigned int fsb_freq, mem_freq, is_ddr3; | |
d60c4473 | 1483 | unsigned int vlv_cdclk_freq; |
f4c956ad | 1484 | |
645416f5 DV |
1485 | /** |
1486 | * wq - Driver workqueue for GEM. | |
1487 | * | |
1488 | * NOTE: Work items scheduled here are not allowed to grab any modeset | |
1489 | * locks, for otherwise the flushing done in the pageflip code will | |
1490 | * result in deadlocks. | |
1491 | */ | |
f4c956ad DV |
1492 | struct workqueue_struct *wq; |
1493 | ||
1494 | /* Display functions */ | |
1495 | struct drm_i915_display_funcs display; | |
1496 | ||
1497 | /* PCH chipset type */ | |
1498 | enum intel_pch pch_type; | |
17a303ec | 1499 | unsigned short pch_id; |
f4c956ad DV |
1500 | |
1501 | unsigned long quirks; | |
1502 | ||
b8efb17b ZR |
1503 | enum modeset_restore modeset_restore; |
1504 | struct mutex modeset_restore_lock; | |
673a394b | 1505 | |
a7bbbd63 | 1506 | struct list_head vm_list; /* Global list of all address spaces */ |
0260c420 | 1507 | struct i915_gtt gtt; /* VM representing the global address space */ |
5d4545ae | 1508 | |
4b5aed62 | 1509 | struct i915_gem_mm mm; |
ad46cb53 CW |
1510 | DECLARE_HASHTABLE(mm_structs, 7); |
1511 | struct mutex mm_lock; | |
8781342d | 1512 | |
8781342d DV |
1513 | /* Kernel Modesetting */ |
1514 | ||
9b9d172d | 1515 | struct sdvo_device_mapping sdvo_mappings[2]; |
652c393a | 1516 | |
76c4ac04 DL |
1517 | struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES]; |
1518 | struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES]; | |
6b95a207 KH |
1519 | wait_queue_head_t pending_flip_queue; |
1520 | ||
c4597872 DV |
1521 | #ifdef CONFIG_DEBUG_FS |
1522 | struct intel_pipe_crc pipe_crc[I915_MAX_PIPES]; | |
1523 | #endif | |
1524 | ||
e72f9fbf DV |
1525 | int num_shared_dpll; |
1526 | struct intel_shared_dpll shared_dplls[I915_NUM_PLLS]; | |
e4607fcf | 1527 | int dpio_phy_iosf_port[I915_NUM_PHYS_VLV]; |
ee7b9f93 | 1528 | |
652c393a JB |
1529 | /* Reclocking support */ |
1530 | bool render_reclock_avail; | |
1531 | bool lvds_downclock_avail; | |
18f9ed12 ZY |
1532 | /* indicates the reduced downclock for LVDS*/ |
1533 | int lvds_downclock; | |
f99d7069 DV |
1534 | |
1535 | struct i915_frontbuffer_tracking fb_tracking; | |
1536 | ||
652c393a | 1537 | u16 orig_clock; |
f97108d1 | 1538 | |
c4804411 | 1539 | bool mchbar_need_disable; |
f97108d1 | 1540 | |
a4da4fa4 DV |
1541 | struct intel_l3_parity l3_parity; |
1542 | ||
59124506 BW |
1543 | /* Cannot be determined by PCIID. You must always read a register. */ |
1544 | size_t ellc_size; | |
1545 | ||
c6a828d3 | 1546 | /* gen6+ rps state */ |
c85aa885 | 1547 | struct intel_gen6_power_mgmt rps; |
c6a828d3 | 1548 | |
20e4d407 DV |
1549 | /* ilk-only ips/rps state. Everything in here is protected by the global |
1550 | * mchdev_lock in intel_pm.c */ | |
c85aa885 | 1551 | struct intel_ilk_power_mgmt ips; |
b5e50c3f | 1552 | |
83c00f55 | 1553 | struct i915_power_domains power_domains; |
a38911a3 | 1554 | |
a031d709 | 1555 | struct i915_psr psr; |
3f51e471 | 1556 | |
99584db3 | 1557 | struct i915_gpu_error gpu_error; |
ae681d96 | 1558 | |
c9cddffc JB |
1559 | struct drm_i915_gem_object *vlv_pctx; |
1560 | ||
4520f53a | 1561 | #ifdef CONFIG_DRM_I915_FBDEV |
8be48d92 DA |
1562 | /* list of fbdev register on this device */ |
1563 | struct intel_fbdev *fbdev; | |
4520f53a | 1564 | #endif |
e953fd7b | 1565 | |
073f34d9 JB |
1566 | /* |
1567 | * The console may be contended at resume, but we don't | |
1568 | * want it to block on it. | |
1569 | */ | |
1570 | struct work_struct console_resume_work; | |
1571 | ||
e953fd7b | 1572 | struct drm_property *broadcast_rgb_property; |
3f43c48d | 1573 | struct drm_property *force_audio_property; |
e3689190 | 1574 | |
254f965c | 1575 | uint32_t hw_context_size; |
a33afea5 | 1576 | struct list_head context_list; |
f4c956ad | 1577 | |
3e68320e | 1578 | u32 fdi_rx_config; |
68d18ad7 | 1579 | |
842f1c8b | 1580 | u32 suspend_count; |
f4c956ad | 1581 | struct i915_suspend_saved_registers regfile; |
ddeea5b0 | 1582 | struct vlv_s0ix_state vlv_s0ix_state; |
231f42a4 | 1583 | |
53615a5e VS |
1584 | struct { |
1585 | /* | |
1586 | * Raw watermark latency values: | |
1587 | * in 0.1us units for WM0, | |
1588 | * in 0.5us units for WM1+. | |
1589 | */ | |
1590 | /* primary */ | |
1591 | uint16_t pri_latency[5]; | |
1592 | /* sprite */ | |
1593 | uint16_t spr_latency[5]; | |
1594 | /* cursor */ | |
1595 | uint16_t cur_latency[5]; | |
609cedef VS |
1596 | |
1597 | /* current hardware state */ | |
820c1980 | 1598 | struct ilk_wm_values hw; |
53615a5e VS |
1599 | } wm; |
1600 | ||
8a187455 PZ |
1601 | struct i915_runtime_pm pm; |
1602 | ||
13cf5504 DA |
1603 | struct intel_digital_port *hpd_irq_port[I915_MAX_PORTS]; |
1604 | u32 long_hpd_port_mask; | |
1605 | u32 short_hpd_port_mask; | |
1606 | struct work_struct dig_port_work; | |
1607 | ||
0e32b39c DA |
1608 | /* |
1609 | * if we get a HPD irq from DP and a HPD irq from non-DP | |
1610 | * the non-DP HPD could block the workqueue on a mode config | |
1611 | * mutex getting, that userspace may have taken. However | |
1612 | * userspace is waiting on the DP workqueue to run which is | |
1613 | * blocked behind the non-DP one. | |
1614 | */ | |
1615 | struct workqueue_struct *dp_wq; | |
1616 | ||
231f42a4 DV |
1617 | /* Old dri1 support infrastructure, beware the dragons ya fools entering |
1618 | * here! */ | |
1619 | struct i915_dri1_state dri1; | |
db1b76ca DV |
1620 | /* Old ums support infrastructure, same warning applies. */ |
1621 | struct i915_ums_state ums; | |
bdf1e7e3 DV |
1622 | |
1623 | /* | |
1624 | * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch | |
1625 | * will be rejected. Instead look for a better place. | |
1626 | */ | |
77fec556 | 1627 | }; |
1da177e4 | 1628 | |
2c1792a1 CW |
1629 | static inline struct drm_i915_private *to_i915(const struct drm_device *dev) |
1630 | { | |
1631 | return dev->dev_private; | |
1632 | } | |
1633 | ||
b4519513 CW |
1634 | /* Iterate over initialised rings */ |
1635 | #define for_each_ring(ring__, dev_priv__, i__) \ | |
1636 | for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \ | |
1637 | if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__))) | |
1638 | ||
b1d7e4b4 WF |
1639 | enum hdmi_force_audio { |
1640 | HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */ | |
1641 | HDMI_AUDIO_OFF, /* force turn off HDMI audio */ | |
1642 | HDMI_AUDIO_AUTO, /* trust EDID */ | |
1643 | HDMI_AUDIO_ON, /* force turn on HDMI audio */ | |
1644 | }; | |
1645 | ||
190d6cd5 | 1646 | #define I915_GTT_OFFSET_NONE ((u32)-1) |
ed2f3452 | 1647 | |
37e680a1 CW |
1648 | struct drm_i915_gem_object_ops { |
1649 | /* Interface between the GEM object and its backing storage. | |
1650 | * get_pages() is called once prior to the use of the associated set | |
1651 | * of pages before to binding them into the GTT, and put_pages() is | |
1652 | * called after we no longer need them. As we expect there to be | |
1653 | * associated cost with migrating pages between the backing storage | |
1654 | * and making them available for the GPU (e.g. clflush), we may hold | |
1655 | * onto the pages after they are no longer referenced by the GPU | |
1656 | * in case they may be used again shortly (for example migrating the | |
1657 | * pages to a different memory domain within the GTT). put_pages() | |
1658 | * will therefore most likely be called when the object itself is | |
1659 | * being released or under memory pressure (where we attempt to | |
1660 | * reap pages for the shrinker). | |
1661 | */ | |
1662 | int (*get_pages)(struct drm_i915_gem_object *); | |
1663 | void (*put_pages)(struct drm_i915_gem_object *); | |
5cc9ed4b CW |
1664 | int (*dmabuf_export)(struct drm_i915_gem_object *); |
1665 | void (*release)(struct drm_i915_gem_object *); | |
37e680a1 CW |
1666 | }; |
1667 | ||
a071fa00 DV |
1668 | /* |
1669 | * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is | |
1670 | * considered to be the frontbuffer for the given plane interface-vise. This | |
1671 | * doesn't mean that the hw necessarily already scans it out, but that any | |
1672 | * rendering (by the cpu or gpu) will land in the frontbuffer eventually. | |
1673 | * | |
1674 | * We have one bit per pipe and per scanout plane type. | |
1675 | */ | |
1676 | #define INTEL_FRONTBUFFER_BITS_PER_PIPE 4 | |
1677 | #define INTEL_FRONTBUFFER_BITS \ | |
1678 | (INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES) | |
1679 | #define INTEL_FRONTBUFFER_PRIMARY(pipe) \ | |
1680 | (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))) | |
1681 | #define INTEL_FRONTBUFFER_CURSOR(pipe) \ | |
1682 | (1 << (1 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))) | |
1683 | #define INTEL_FRONTBUFFER_SPRITE(pipe) \ | |
1684 | (1 << (2 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))) | |
1685 | #define INTEL_FRONTBUFFER_OVERLAY(pipe) \ | |
1686 | (1 << (3 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))) | |
cc36513c DV |
1687 | #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \ |
1688 | (0xf << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))) | |
a071fa00 | 1689 | |
673a394b | 1690 | struct drm_i915_gem_object { |
c397b908 | 1691 | struct drm_gem_object base; |
673a394b | 1692 | |
37e680a1 CW |
1693 | const struct drm_i915_gem_object_ops *ops; |
1694 | ||
2f633156 BW |
1695 | /** List of VMAs backed by this object */ |
1696 | struct list_head vma_list; | |
1697 | ||
c1ad11fc CW |
1698 | /** Stolen memory for this object, instead of being backed by shmem. */ |
1699 | struct drm_mm_node *stolen; | |
35c20a60 | 1700 | struct list_head global_list; |
673a394b | 1701 | |
69dc4987 | 1702 | struct list_head ring_list; |
b25cb2f8 BW |
1703 | /** Used in execbuf to temporarily hold a ref */ |
1704 | struct list_head obj_exec_link; | |
673a394b EA |
1705 | |
1706 | /** | |
65ce3027 CW |
1707 | * This is set if the object is on the active lists (has pending |
1708 | * rendering and so a non-zero seqno), and is not set if it i s on | |
1709 | * inactive (ready to be unbound) list. | |
673a394b | 1710 | */ |
0206e353 | 1711 | unsigned int active:1; |
673a394b EA |
1712 | |
1713 | /** | |
1714 | * This is set if the object has been written to since last bound | |
1715 | * to the GTT | |
1716 | */ | |
0206e353 | 1717 | unsigned int dirty:1; |
778c3544 DV |
1718 | |
1719 | /** | |
1720 | * Fence register bits (if any) for this object. Will be set | |
1721 | * as needed when mapped into the GTT. | |
1722 | * Protected by dev->struct_mutex. | |
778c3544 | 1723 | */ |
4b9de737 | 1724 | signed int fence_reg:I915_MAX_NUM_FENCE_BITS; |
778c3544 | 1725 | |
778c3544 DV |
1726 | /** |
1727 | * Advice: are the backing pages purgeable? | |
1728 | */ | |
0206e353 | 1729 | unsigned int madv:2; |
778c3544 | 1730 | |
778c3544 DV |
1731 | /** |
1732 | * Current tiling mode for the object. | |
1733 | */ | |
0206e353 | 1734 | unsigned int tiling_mode:2; |
5d82e3e6 CW |
1735 | /** |
1736 | * Whether the tiling parameters for the currently associated fence | |
1737 | * register have changed. Note that for the purposes of tracking | |
1738 | * tiling changes we also treat the unfenced register, the register | |
1739 | * slot that the object occupies whilst it executes a fenced | |
1740 | * command (such as BLT on gen2/3), as a "fence". | |
1741 | */ | |
1742 | unsigned int fence_dirty:1; | |
778c3544 | 1743 | |
75e9e915 DV |
1744 | /** |
1745 | * Is the object at the current location in the gtt mappable and | |
1746 | * fenceable? Used to avoid costly recalculations. | |
1747 | */ | |
0206e353 | 1748 | unsigned int map_and_fenceable:1; |
75e9e915 | 1749 | |
fb7d516a DV |
1750 | /** |
1751 | * Whether the current gtt mapping needs to be mappable (and isn't just | |
1752 | * mappable by accident). Track pin and fault separate for a more | |
1753 | * accurate mappable working set. | |
1754 | */ | |
0206e353 AJ |
1755 | unsigned int fault_mappable:1; |
1756 | unsigned int pin_mappable:1; | |
cc98b413 | 1757 | unsigned int pin_display:1; |
fb7d516a | 1758 | |
24f3a8cf AG |
1759 | /* |
1760 | * Is the object to be mapped as read-only to the GPU | |
1761 | * Only honoured if hardware has relevant pte bit | |
1762 | */ | |
1763 | unsigned long gt_ro:1; | |
1764 | ||
caea7476 CW |
1765 | /* |
1766 | * Is the GPU currently using a fence to access this buffer, | |
1767 | */ | |
1768 | unsigned int pending_fenced_gpu_access:1; | |
1769 | unsigned int fenced_gpu_access:1; | |
1770 | ||
651d794f | 1771 | unsigned int cache_level:3; |
93dfb40c | 1772 | |
7bddb01f | 1773 | unsigned int has_aliasing_ppgtt_mapping:1; |
74898d7e | 1774 | unsigned int has_global_gtt_mapping:1; |
9da3da66 | 1775 | unsigned int has_dma_mapping:1; |
7bddb01f | 1776 | |
a071fa00 DV |
1777 | unsigned int frontbuffer_bits:INTEL_FRONTBUFFER_BITS; |
1778 | ||
9da3da66 | 1779 | struct sg_table *pages; |
a5570178 | 1780 | int pages_pin_count; |
673a394b | 1781 | |
1286ff73 | 1782 | /* prime dma-buf support */ |
9a70cc2a DA |
1783 | void *dma_buf_vmapping; |
1784 | int vmapping_count; | |
1785 | ||
a4872ba6 | 1786 | struct intel_engine_cs *ring; |
caea7476 | 1787 | |
1c293ea3 | 1788 | /** Breadcrumb of last rendering to the buffer. */ |
0201f1ec CW |
1789 | uint32_t last_read_seqno; |
1790 | uint32_t last_write_seqno; | |
caea7476 CW |
1791 | /** Breadcrumb of last fenced GPU access to the buffer. */ |
1792 | uint32_t last_fenced_seqno; | |
673a394b | 1793 | |
778c3544 | 1794 | /** Current tiling stride for the object, if it's tiled. */ |
de151cf6 | 1795 | uint32_t stride; |
673a394b | 1796 | |
80075d49 DV |
1797 | /** References from framebuffers, locks out tiling changes. */ |
1798 | unsigned long framebuffer_references; | |
1799 | ||
280b713b | 1800 | /** Record of address bit 17 of each page at last unbind. */ |
d312ec25 | 1801 | unsigned long *bit_17; |
280b713b | 1802 | |
79e53945 | 1803 | /** User space pin count and filp owning the pin */ |
aa5f8021 | 1804 | unsigned long user_pin_count; |
79e53945 | 1805 | struct drm_file *pin_filp; |
71acb5eb DA |
1806 | |
1807 | /** for phy allocated objects */ | |
00731155 | 1808 | drm_dma_handle_t *phys_handle; |
673a394b | 1809 | |
5cc9ed4b CW |
1810 | union { |
1811 | struct i915_gem_userptr { | |
1812 | uintptr_t ptr; | |
1813 | unsigned read_only :1; | |
1814 | unsigned workers :4; | |
1815 | #define I915_GEM_USERPTR_MAX_WORKERS 15 | |
1816 | ||
ad46cb53 CW |
1817 | struct i915_mm_struct *mm; |
1818 | struct i915_mmu_object *mmu_object; | |
5cc9ed4b CW |
1819 | struct work_struct *work; |
1820 | } userptr; | |
1821 | }; | |
1822 | }; | |
62b8b215 | 1823 | #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base) |
23010e43 | 1824 | |
a071fa00 DV |
1825 | void i915_gem_track_fb(struct drm_i915_gem_object *old, |
1826 | struct drm_i915_gem_object *new, | |
1827 | unsigned frontbuffer_bits); | |
1828 | ||
673a394b EA |
1829 | /** |
1830 | * Request queue structure. | |
1831 | * | |
1832 | * The request queue allows us to note sequence numbers that have been emitted | |
1833 | * and may be associated with active buffers to be retired. | |
1834 | * | |
1835 | * By keeping this list, we can avoid having to do questionable | |
1836 | * sequence-number comparisons on buffer last_rendering_seqnos, and associate | |
1837 | * an emission time with seqnos for tracking how far ahead of the GPU we are. | |
1838 | */ | |
1839 | struct drm_i915_gem_request { | |
852835f3 | 1840 | /** On Which ring this request was generated */ |
a4872ba6 | 1841 | struct intel_engine_cs *ring; |
852835f3 | 1842 | |
673a394b EA |
1843 | /** GEM sequence number associated with this request. */ |
1844 | uint32_t seqno; | |
1845 | ||
7d736f4f MK |
1846 | /** Position in the ringbuffer of the start of the request */ |
1847 | u32 head; | |
1848 | ||
1849 | /** Position in the ringbuffer of the end of the request */ | |
a71d8d94 CW |
1850 | u32 tail; |
1851 | ||
0e50e96b | 1852 | /** Context related to this request */ |
273497e5 | 1853 | struct intel_context *ctx; |
0e50e96b | 1854 | |
7d736f4f MK |
1855 | /** Batch buffer related to this request if any */ |
1856 | struct drm_i915_gem_object *batch_obj; | |
1857 | ||
673a394b EA |
1858 | /** Time at which this request was emitted, in jiffies. */ |
1859 | unsigned long emitted_jiffies; | |
1860 | ||
b962442e | 1861 | /** global list entry for this request */ |
673a394b | 1862 | struct list_head list; |
b962442e | 1863 | |
f787a5f5 | 1864 | struct drm_i915_file_private *file_priv; |
b962442e EA |
1865 | /** file_priv list entry for this request */ |
1866 | struct list_head client_list; | |
673a394b EA |
1867 | }; |
1868 | ||
1869 | struct drm_i915_file_private { | |
b29c19b6 | 1870 | struct drm_i915_private *dev_priv; |
ab0e7ff9 | 1871 | struct drm_file *file; |
b29c19b6 | 1872 | |
673a394b | 1873 | struct { |
99057c81 | 1874 | spinlock_t lock; |
b962442e | 1875 | struct list_head request_list; |
b29c19b6 | 1876 | struct delayed_work idle_work; |
673a394b | 1877 | } mm; |
40521054 | 1878 | struct idr context_idr; |
e59ec13d | 1879 | |
b29c19b6 | 1880 | atomic_t rps_wait_boost; |
a4872ba6 | 1881 | struct intel_engine_cs *bsd_ring; |
673a394b EA |
1882 | }; |
1883 | ||
351e3db2 BV |
1884 | /* |
1885 | * A command that requires special handling by the command parser. | |
1886 | */ | |
1887 | struct drm_i915_cmd_descriptor { | |
1888 | /* | |
1889 | * Flags describing how the command parser processes the command. | |
1890 | * | |
1891 | * CMD_DESC_FIXED: The command has a fixed length if this is set, | |
1892 | * a length mask if not set | |
1893 | * CMD_DESC_SKIP: The command is allowed but does not follow the | |
1894 | * standard length encoding for the opcode range in | |
1895 | * which it falls | |
1896 | * CMD_DESC_REJECT: The command is never allowed | |
1897 | * CMD_DESC_REGISTER: The command should be checked against the | |
1898 | * register whitelist for the appropriate ring | |
1899 | * CMD_DESC_MASTER: The command is allowed if the submitting process | |
1900 | * is the DRM master | |
1901 | */ | |
1902 | u32 flags; | |
1903 | #define CMD_DESC_FIXED (1<<0) | |
1904 | #define CMD_DESC_SKIP (1<<1) | |
1905 | #define CMD_DESC_REJECT (1<<2) | |
1906 | #define CMD_DESC_REGISTER (1<<3) | |
1907 | #define CMD_DESC_BITMASK (1<<4) | |
1908 | #define CMD_DESC_MASTER (1<<5) | |
1909 | ||
1910 | /* | |
1911 | * The command's unique identification bits and the bitmask to get them. | |
1912 | * This isn't strictly the opcode field as defined in the spec and may | |
1913 | * also include type, subtype, and/or subop fields. | |
1914 | */ | |
1915 | struct { | |
1916 | u32 value; | |
1917 | u32 mask; | |
1918 | } cmd; | |
1919 | ||
1920 | /* | |
1921 | * The command's length. The command is either fixed length (i.e. does | |
1922 | * not include a length field) or has a length field mask. The flag | |
1923 | * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has | |
1924 | * a length mask. All command entries in a command table must include | |
1925 | * length information. | |
1926 | */ | |
1927 | union { | |
1928 | u32 fixed; | |
1929 | u32 mask; | |
1930 | } length; | |
1931 | ||
1932 | /* | |
1933 | * Describes where to find a register address in the command to check | |
1934 | * against the ring's register whitelist. Only valid if flags has the | |
1935 | * CMD_DESC_REGISTER bit set. | |
1936 | */ | |
1937 | struct { | |
1938 | u32 offset; | |
1939 | u32 mask; | |
1940 | } reg; | |
1941 | ||
1942 | #define MAX_CMD_DESC_BITMASKS 3 | |
1943 | /* | |
1944 | * Describes command checks where a particular dword is masked and | |
1945 | * compared against an expected value. If the command does not match | |
1946 | * the expected value, the parser rejects it. Only valid if flags has | |
1947 | * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero | |
1948 | * are valid. | |
d4d48035 BV |
1949 | * |
1950 | * If the check specifies a non-zero condition_mask then the parser | |
1951 | * only performs the check when the bits specified by condition_mask | |
1952 | * are non-zero. | |
351e3db2 BV |
1953 | */ |
1954 | struct { | |
1955 | u32 offset; | |
1956 | u32 mask; | |
1957 | u32 expected; | |
d4d48035 BV |
1958 | u32 condition_offset; |
1959 | u32 condition_mask; | |
351e3db2 BV |
1960 | } bits[MAX_CMD_DESC_BITMASKS]; |
1961 | }; | |
1962 | ||
1963 | /* | |
1964 | * A table of commands requiring special handling by the command parser. | |
1965 | * | |
1966 | * Each ring has an array of tables. Each table consists of an array of command | |
1967 | * descriptors, which must be sorted with command opcodes in ascending order. | |
1968 | */ | |
1969 | struct drm_i915_cmd_table { | |
1970 | const struct drm_i915_cmd_descriptor *table; | |
1971 | int count; | |
1972 | }; | |
1973 | ||
5c969aa7 | 1974 | #define INTEL_INFO(dev) (&to_i915(dev)->info) |
cae5852d | 1975 | |
ffbab09b VS |
1976 | #define IS_I830(dev) ((dev)->pdev->device == 0x3577) |
1977 | #define IS_845G(dev) ((dev)->pdev->device == 0x2562) | |
cae5852d | 1978 | #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x) |
ffbab09b | 1979 | #define IS_I865G(dev) ((dev)->pdev->device == 0x2572) |
cae5852d | 1980 | #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g) |
ffbab09b VS |
1981 | #define IS_I915GM(dev) ((dev)->pdev->device == 0x2592) |
1982 | #define IS_I945G(dev) ((dev)->pdev->device == 0x2772) | |
cae5852d ZN |
1983 | #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm) |
1984 | #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater) | |
1985 | #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline) | |
ffbab09b | 1986 | #define IS_GM45(dev) ((dev)->pdev->device == 0x2A42) |
cae5852d | 1987 | #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x) |
ffbab09b VS |
1988 | #define IS_PINEVIEW_G(dev) ((dev)->pdev->device == 0xa001) |
1989 | #define IS_PINEVIEW_M(dev) ((dev)->pdev->device == 0xa011) | |
cae5852d ZN |
1990 | #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview) |
1991 | #define IS_G33(dev) (INTEL_INFO(dev)->is_g33) | |
ffbab09b | 1992 | #define IS_IRONLAKE_M(dev) ((dev)->pdev->device == 0x0046) |
4b65177b | 1993 | #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge) |
ffbab09b VS |
1994 | #define IS_IVB_GT1(dev) ((dev)->pdev->device == 0x0156 || \ |
1995 | (dev)->pdev->device == 0x0152 || \ | |
1996 | (dev)->pdev->device == 0x015a) | |
1997 | #define IS_SNB_GT1(dev) ((dev)->pdev->device == 0x0102 || \ | |
1998 | (dev)->pdev->device == 0x0106 || \ | |
1999 | (dev)->pdev->device == 0x010A) | |
70a3eb7a | 2000 | #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview) |
6df4027b | 2001 | #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev)) |
4cae9ae0 | 2002 | #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell) |
8179f1f0 | 2003 | #define IS_BROADWELL(dev) (!INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev)) |
cae5852d | 2004 | #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) |
ed1c9e2c | 2005 | #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \ |
ffbab09b | 2006 | ((dev)->pdev->device & 0xFF00) == 0x0C00) |
5dd8c4c3 BW |
2007 | #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \ |
2008 | (((dev)->pdev->device & 0xf) == 0x2 || \ | |
2009 | ((dev)->pdev->device & 0xf) == 0x6 || \ | |
2010 | ((dev)->pdev->device & 0xf) == 0xe)) | |
2011 | #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \ | |
ffbab09b | 2012 | ((dev)->pdev->device & 0xFF00) == 0x0A00) |
5dd8c4c3 | 2013 | #define IS_ULT(dev) (IS_HSW_ULT(dev) || IS_BDW_ULT(dev)) |
9435373e | 2014 | #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \ |
ffbab09b | 2015 | ((dev)->pdev->device & 0x00F0) == 0x0020) |
9bbfd20a PZ |
2016 | /* ULX machines are also considered ULT. */ |
2017 | #define IS_HSW_ULX(dev) ((dev)->pdev->device == 0x0A0E || \ | |
2018 | (dev)->pdev->device == 0x0A1E) | |
b833d685 | 2019 | #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary) |
cae5852d | 2020 | |
85436696 JB |
2021 | /* |
2022 | * The genX designation typically refers to the render engine, so render | |
2023 | * capability related checks should use IS_GEN, while display and other checks | |
2024 | * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular | |
2025 | * chips, etc.). | |
2026 | */ | |
cae5852d ZN |
2027 | #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2) |
2028 | #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3) | |
2029 | #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4) | |
2030 | #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5) | |
2031 | #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6) | |
85436696 | 2032 | #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7) |
d2980845 | 2033 | #define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8) |
cae5852d | 2034 | |
73ae478c BW |
2035 | #define RENDER_RING (1<<RCS) |
2036 | #define BSD_RING (1<<VCS) | |
2037 | #define BLT_RING (1<<BCS) | |
2038 | #define VEBOX_RING (1<<VECS) | |
845f74a7 | 2039 | #define BSD2_RING (1<<VCS2) |
63c42e56 | 2040 | #define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING) |
845f74a7 | 2041 | #define HAS_BSD2(dev) (INTEL_INFO(dev)->ring_mask & BSD2_RING) |
63c42e56 BW |
2042 | #define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING) |
2043 | #define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING) | |
2044 | #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc) | |
2045 | #define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \ | |
2046 | to_i915(dev)->ellc_size) | |
cae5852d ZN |
2047 | #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws) |
2048 | ||
254f965c | 2049 | #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6) |
7365fb78 JB |
2050 | #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >= 6) |
2051 | #define HAS_PPGTT(dev) (INTEL_INFO(dev)->gen >= 7 && !IS_GEN8(dev)) | |
c5dc5cec | 2052 | #define USES_PPGTT(dev) intel_enable_ppgtt(dev, false) |
7e0d96bc | 2053 | #define USES_FULL_PPGTT(dev) intel_enable_ppgtt(dev, true) |
1d2a314c | 2054 | |
05394f39 | 2055 | #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay) |
cae5852d ZN |
2056 | #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical) |
2057 | ||
b45305fc DV |
2058 | /* Early gen2 have a totally busted CS tlb and require pinned batches. */ |
2059 | #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev)) | |
4e6b788c DV |
2060 | /* |
2061 | * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts | |
2062 | * even when in MSI mode. This results in spurious interrupt warnings if the | |
2063 | * legacy irq no. is shared with another device. The kernel then disables that | |
2064 | * interrupt source and so prevents the other device from working properly. | |
2065 | */ | |
2066 | #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5) | |
2067 | #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5) | |
b45305fc | 2068 | |
cae5852d ZN |
2069 | /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte |
2070 | * rows, which changed the alignment requirements and fence programming. | |
2071 | */ | |
2072 | #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \ | |
2073 | IS_I915GM(dev))) | |
2074 | #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) | |
2075 | #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev)) | |
2076 | #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev)) | |
cae5852d ZN |
2077 | #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv) |
2078 | #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug) | |
cae5852d ZN |
2079 | |
2080 | #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2) | |
2081 | #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr) | |
3a77c4c4 | 2082 | #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc) |
cae5852d | 2083 | |
2a114cc1 | 2084 | #define HAS_IPS(dev) (IS_ULT(dev) || IS_BROADWELL(dev)) |
f5adf94e | 2085 | |
dd93be58 | 2086 | #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi) |
30568c45 | 2087 | #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg) |
ed8546ac | 2088 | #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
6157d3c8 | 2089 | #define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \ |
fd7f8cce | 2090 | IS_BROADWELL(dev) || IS_VALLEYVIEW(dev)) |
affa9354 | 2091 | |
17a303ec PZ |
2092 | #define INTEL_PCH_DEVICE_ID_MASK 0xff00 |
2093 | #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00 | |
2094 | #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00 | |
2095 | #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00 | |
2096 | #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00 | |
2097 | #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00 | |
2098 | ||
2c1792a1 | 2099 | #define INTEL_PCH_TYPE(dev) (to_i915(dev)->pch_type) |
eb877ebf | 2100 | #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT) |
cae5852d ZN |
2101 | #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT) |
2102 | #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX) | |
40c7ead9 | 2103 | #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP) |
45e6e3a1 | 2104 | #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE) |
cae5852d | 2105 | |
5fafe292 SJ |
2106 | #define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev)) |
2107 | ||
040d2baa BW |
2108 | /* DPF == dynamic parity feature */ |
2109 | #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) | |
2110 | #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev)) | |
e1ef7cc2 | 2111 | |
c8735b0c BW |
2112 | #define GT_FREQUENCY_MULTIPLIER 50 |
2113 | ||
05394f39 CW |
2114 | #include "i915_trace.h" |
2115 | ||
baa70943 | 2116 | extern const struct drm_ioctl_desc i915_ioctls[]; |
b3a83639 DA |
2117 | extern int i915_max_ioctl; |
2118 | ||
6a9ee8af DA |
2119 | extern int i915_suspend(struct drm_device *dev, pm_message_t state); |
2120 | extern int i915_resume(struct drm_device *dev); | |
7c1c2871 DA |
2121 | extern int i915_master_create(struct drm_device *dev, struct drm_master *master); |
2122 | extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master); | |
2123 | ||
d330a953 JN |
2124 | /* i915_params.c */ |
2125 | struct i915_params { | |
2126 | int modeset; | |
2127 | int panel_ignore_lid; | |
2128 | unsigned int powersave; | |
2129 | int semaphores; | |
2130 | unsigned int lvds_downclock; | |
2131 | int lvds_channel_mode; | |
2132 | int panel_use_ssc; | |
2133 | int vbt_sdvo_panel_type; | |
2134 | int enable_rc6; | |
2135 | int enable_fbc; | |
d330a953 JN |
2136 | int enable_ppgtt; |
2137 | int enable_psr; | |
2138 | unsigned int preliminary_hw_support; | |
2139 | int disable_power_well; | |
2140 | int enable_ips; | |
e5aa6541 | 2141 | int invert_brightness; |
351e3db2 | 2142 | int enable_cmd_parser; |
e5aa6541 DL |
2143 | /* leave bools at the end to not create holes */ |
2144 | bool enable_hangcheck; | |
2145 | bool fastboot; | |
d330a953 JN |
2146 | bool prefault_disable; |
2147 | bool reset; | |
a0bae57f | 2148 | bool disable_display; |
7a10dfa6 | 2149 | bool disable_vtd_wa; |
84c33a64 | 2150 | int use_mmio_flip; |
5978118c | 2151 | bool mmio_debug; |
d330a953 JN |
2152 | }; |
2153 | extern struct i915_params i915 __read_mostly; | |
2154 | ||
1da177e4 | 2155 | /* i915_dma.c */ |
d05c617e | 2156 | void i915_update_dri1_breadcrumb(struct drm_device *dev); |
84b1fd10 | 2157 | extern void i915_kernel_lost_context(struct drm_device * dev); |
22eae947 | 2158 | extern int i915_driver_load(struct drm_device *, unsigned long flags); |
ba8bbcf6 | 2159 | extern int i915_driver_unload(struct drm_device *); |
2885f6ac | 2160 | extern int i915_driver_open(struct drm_device *dev, struct drm_file *file); |
84b1fd10 | 2161 | extern void i915_driver_lastclose(struct drm_device * dev); |
6c340eac | 2162 | extern void i915_driver_preclose(struct drm_device *dev, |
2885f6ac | 2163 | struct drm_file *file); |
673a394b | 2164 | extern void i915_driver_postclose(struct drm_device *dev, |
2885f6ac | 2165 | struct drm_file *file); |
84b1fd10 | 2166 | extern int i915_driver_device_is_agp(struct drm_device * dev); |
c43b5634 | 2167 | #ifdef CONFIG_COMPAT |
0d6aa60b DA |
2168 | extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, |
2169 | unsigned long arg); | |
c43b5634 | 2170 | #endif |
673a394b | 2171 | extern int i915_emit_box(struct drm_device *dev, |
c4e7a414 CW |
2172 | struct drm_clip_rect *box, |
2173 | int DR1, int DR4); | |
8e96d9c4 | 2174 | extern int intel_gpu_reset(struct drm_device *dev); |
d4b8bb2a | 2175 | extern int i915_reset(struct drm_device *dev); |
7648fa99 JB |
2176 | extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv); |
2177 | extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv); | |
2178 | extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv); | |
2179 | extern void i915_update_gfx_val(struct drm_i915_private *dev_priv); | |
650ad970 | 2180 | int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on); |
1d0d343a | 2181 | void intel_hpd_cancel_work(struct drm_i915_private *dev_priv); |
7648fa99 | 2182 | |
073f34d9 | 2183 | extern void intel_console_resume(struct work_struct *work); |
af6061af | 2184 | |
1da177e4 | 2185 | /* i915_irq.c */ |
10cd45b6 | 2186 | void i915_queue_hangcheck(struct drm_device *dev); |
58174462 MK |
2187 | __printf(3, 4) |
2188 | void i915_handle_error(struct drm_device *dev, bool wedged, | |
2189 | const char *fmt, ...); | |
1da177e4 | 2190 | |
76c3552f D |
2191 | void gen6_set_pm_mask(struct drm_i915_private *dev_priv, u32 pm_iir, |
2192 | int new_delay); | |
f71d4af4 | 2193 | extern void intel_irq_init(struct drm_device *dev); |
20afbda2 | 2194 | extern void intel_hpd_init(struct drm_device *dev); |
907b28c5 CW |
2195 | |
2196 | extern void intel_uncore_sanitize(struct drm_device *dev); | |
10018603 ID |
2197 | extern void intel_uncore_early_sanitize(struct drm_device *dev, |
2198 | bool restore_forcewake); | |
907b28c5 | 2199 | extern void intel_uncore_init(struct drm_device *dev); |
907b28c5 | 2200 | extern void intel_uncore_check_errors(struct drm_device *dev); |
aec347ab | 2201 | extern void intel_uncore_fini(struct drm_device *dev); |
156c7ca0 | 2202 | extern void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore); |
b1f14ad0 | 2203 | |
7c463586 | 2204 | void |
50227e1c | 2205 | i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, |
755e9019 | 2206 | u32 status_mask); |
7c463586 KP |
2207 | |
2208 | void | |
50227e1c | 2209 | i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, |
755e9019 | 2210 | u32 status_mask); |
7c463586 | 2211 | |
f8b79e58 ID |
2212 | void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv); |
2213 | void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv); | |
2214 | ||
673a394b EA |
2215 | /* i915_gem.c */ |
2216 | int i915_gem_init_ioctl(struct drm_device *dev, void *data, | |
2217 | struct drm_file *file_priv); | |
2218 | int i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
2219 | struct drm_file *file_priv); | |
2220 | int i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
2221 | struct drm_file *file_priv); | |
2222 | int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
2223 | struct drm_file *file_priv); | |
2224 | int i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
2225 | struct drm_file *file_priv); | |
de151cf6 JB |
2226 | int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, |
2227 | struct drm_file *file_priv); | |
673a394b EA |
2228 | int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, |
2229 | struct drm_file *file_priv); | |
2230 | int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
2231 | struct drm_file *file_priv); | |
2232 | int i915_gem_execbuffer(struct drm_device *dev, void *data, | |
2233 | struct drm_file *file_priv); | |
76446cac JB |
2234 | int i915_gem_execbuffer2(struct drm_device *dev, void *data, |
2235 | struct drm_file *file_priv); | |
673a394b EA |
2236 | int i915_gem_pin_ioctl(struct drm_device *dev, void *data, |
2237 | struct drm_file *file_priv); | |
2238 | int i915_gem_unpin_ioctl(struct drm_device *dev, void *data, | |
2239 | struct drm_file *file_priv); | |
2240 | int i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
2241 | struct drm_file *file_priv); | |
199adf40 BW |
2242 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, |
2243 | struct drm_file *file); | |
2244 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, | |
2245 | struct drm_file *file); | |
673a394b EA |
2246 | int i915_gem_throttle_ioctl(struct drm_device *dev, void *data, |
2247 | struct drm_file *file_priv); | |
3ef94daa CW |
2248 | int i915_gem_madvise_ioctl(struct drm_device *dev, void *data, |
2249 | struct drm_file *file_priv); | |
673a394b EA |
2250 | int i915_gem_entervt_ioctl(struct drm_device *dev, void *data, |
2251 | struct drm_file *file_priv); | |
2252 | int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, | |
2253 | struct drm_file *file_priv); | |
2254 | int i915_gem_set_tiling(struct drm_device *dev, void *data, | |
2255 | struct drm_file *file_priv); | |
2256 | int i915_gem_get_tiling(struct drm_device *dev, void *data, | |
2257 | struct drm_file *file_priv); | |
5cc9ed4b CW |
2258 | int i915_gem_init_userptr(struct drm_device *dev); |
2259 | int i915_gem_userptr_ioctl(struct drm_device *dev, void *data, | |
2260 | struct drm_file *file); | |
5a125c3c EA |
2261 | int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, |
2262 | struct drm_file *file_priv); | |
23ba4fd0 BW |
2263 | int i915_gem_wait_ioctl(struct drm_device *dev, void *data, |
2264 | struct drm_file *file_priv); | |
673a394b | 2265 | void i915_gem_load(struct drm_device *dev); |
42dcedd4 CW |
2266 | void *i915_gem_object_alloc(struct drm_device *dev); |
2267 | void i915_gem_object_free(struct drm_i915_gem_object *obj); | |
37e680a1 CW |
2268 | void i915_gem_object_init(struct drm_i915_gem_object *obj, |
2269 | const struct drm_i915_gem_object_ops *ops); | |
05394f39 CW |
2270 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
2271 | size_t size); | |
7e0d96bc BW |
2272 | void i915_init_vm(struct drm_i915_private *dev_priv, |
2273 | struct i915_address_space *vm); | |
673a394b | 2274 | void i915_gem_free_object(struct drm_gem_object *obj); |
2f633156 | 2275 | void i915_gem_vma_destroy(struct i915_vma *vma); |
42dcedd4 | 2276 | |
1ec9e26d DV |
2277 | #define PIN_MAPPABLE 0x1 |
2278 | #define PIN_NONBLOCK 0x2 | |
bf3d149b | 2279 | #define PIN_GLOBAL 0x4 |
d23db88c CW |
2280 | #define PIN_OFFSET_BIAS 0x8 |
2281 | #define PIN_OFFSET_MASK (~4095) | |
2021746e | 2282 | int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj, |
c37e2204 | 2283 | struct i915_address_space *vm, |
2021746e | 2284 | uint32_t alignment, |
d23db88c | 2285 | uint64_t flags); |
07fe0b12 | 2286 | int __must_check i915_vma_unbind(struct i915_vma *vma); |
dd624afd | 2287 | int i915_gem_object_put_pages(struct drm_i915_gem_object *obj); |
48018a57 | 2288 | void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv); |
05394f39 | 2289 | void i915_gem_release_mmap(struct drm_i915_gem_object *obj); |
673a394b | 2290 | void i915_gem_lastclose(struct drm_device *dev); |
f787a5f5 | 2291 | |
4c914c0c BV |
2292 | int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj, |
2293 | int *needs_clflush); | |
2294 | ||
37e680a1 | 2295 | int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj); |
9da3da66 CW |
2296 | static inline struct page *i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n) |
2297 | { | |
67d5a50c ID |
2298 | struct sg_page_iter sg_iter; |
2299 | ||
2300 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, n) | |
2db76d7c | 2301 | return sg_page_iter_page(&sg_iter); |
67d5a50c ID |
2302 | |
2303 | return NULL; | |
9da3da66 | 2304 | } |
a5570178 CW |
2305 | static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj) |
2306 | { | |
2307 | BUG_ON(obj->pages == NULL); | |
2308 | obj->pages_pin_count++; | |
2309 | } | |
2310 | static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj) | |
2311 | { | |
2312 | BUG_ON(obj->pages_pin_count == 0); | |
2313 | obj->pages_pin_count--; | |
2314 | } | |
2315 | ||
54cf91dc | 2316 | int __must_check i915_mutex_lock_interruptible(struct drm_device *dev); |
2911a35b | 2317 | int i915_gem_object_sync(struct drm_i915_gem_object *obj, |
a4872ba6 | 2318 | struct intel_engine_cs *to); |
e2d05a8b | 2319 | void i915_vma_move_to_active(struct i915_vma *vma, |
a4872ba6 | 2320 | struct intel_engine_cs *ring); |
ff72145b DA |
2321 | int i915_gem_dumb_create(struct drm_file *file_priv, |
2322 | struct drm_device *dev, | |
2323 | struct drm_mode_create_dumb *args); | |
2324 | int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev, | |
2325 | uint32_t handle, uint64_t *offset); | |
f787a5f5 CW |
2326 | /** |
2327 | * Returns true if seq1 is later than seq2. | |
2328 | */ | |
2329 | static inline bool | |
2330 | i915_seqno_passed(uint32_t seq1, uint32_t seq2) | |
2331 | { | |
2332 | return (int32_t)(seq1 - seq2) >= 0; | |
2333 | } | |
2334 | ||
fca26bb4 MK |
2335 | int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno); |
2336 | int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno); | |
06d98131 | 2337 | int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj); |
d9e86c0e | 2338 | int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj); |
2021746e | 2339 | |
d8ffa60b DV |
2340 | bool i915_gem_object_pin_fence(struct drm_i915_gem_object *obj); |
2341 | void i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj); | |
1690e1eb | 2342 | |
8d9fc7fd | 2343 | struct drm_i915_gem_request * |
a4872ba6 | 2344 | i915_gem_find_active_request(struct intel_engine_cs *ring); |
8d9fc7fd | 2345 | |
b29c19b6 | 2346 | bool i915_gem_retire_requests(struct drm_device *dev); |
a4872ba6 | 2347 | void i915_gem_retire_requests_ring(struct intel_engine_cs *ring); |
33196ded | 2348 | int __must_check i915_gem_check_wedge(struct i915_gpu_error *error, |
d6b2c790 | 2349 | bool interruptible); |
84c33a64 SG |
2350 | int __must_check i915_gem_check_olr(struct intel_engine_cs *ring, u32 seqno); |
2351 | ||
1f83fee0 DV |
2352 | static inline bool i915_reset_in_progress(struct i915_gpu_error *error) |
2353 | { | |
2354 | return unlikely(atomic_read(&error->reset_counter) | |
2ac0f450 | 2355 | & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED)); |
1f83fee0 DV |
2356 | } |
2357 | ||
2358 | static inline bool i915_terminally_wedged(struct i915_gpu_error *error) | |
2359 | { | |
2ac0f450 MK |
2360 | return atomic_read(&error->reset_counter) & I915_WEDGED; |
2361 | } | |
2362 | ||
2363 | static inline u32 i915_reset_count(struct i915_gpu_error *error) | |
2364 | { | |
2365 | return ((atomic_read(&error->reset_counter) & ~I915_WEDGED) + 1) / 2; | |
1f83fee0 | 2366 | } |
a71d8d94 | 2367 | |
88b4aa87 MK |
2368 | static inline bool i915_stop_ring_allow_ban(struct drm_i915_private *dev_priv) |
2369 | { | |
2370 | return dev_priv->gpu_error.stop_rings == 0 || | |
2371 | dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_BAN; | |
2372 | } | |
2373 | ||
2374 | static inline bool i915_stop_ring_allow_warn(struct drm_i915_private *dev_priv) | |
2375 | { | |
2376 | return dev_priv->gpu_error.stop_rings == 0 || | |
2377 | dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_WARN; | |
2378 | } | |
2379 | ||
069efc1d | 2380 | void i915_gem_reset(struct drm_device *dev); |
000433b6 | 2381 | bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force); |
a8198eea | 2382 | int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj); |
1070a42b | 2383 | int __must_check i915_gem_init(struct drm_device *dev); |
f691e2f4 | 2384 | int __must_check i915_gem_init_hw(struct drm_device *dev); |
a4872ba6 | 2385 | int i915_gem_l3_remap(struct intel_engine_cs *ring, int slice); |
f691e2f4 | 2386 | void i915_gem_init_swizzling(struct drm_device *dev); |
79e53945 | 2387 | void i915_gem_cleanup_ringbuffer(struct drm_device *dev); |
b2da9fe5 | 2388 | int __must_check i915_gpu_idle(struct drm_device *dev); |
45c5f202 | 2389 | int __must_check i915_gem_suspend(struct drm_device *dev); |
a4872ba6 | 2390 | int __i915_add_request(struct intel_engine_cs *ring, |
0025c077 | 2391 | struct drm_file *file, |
7d736f4f | 2392 | struct drm_i915_gem_object *batch_obj, |
0025c077 MK |
2393 | u32 *seqno); |
2394 | #define i915_add_request(ring, seqno) \ | |
854c94a7 | 2395 | __i915_add_request(ring, NULL, NULL, seqno) |
a4872ba6 | 2396 | int __must_check i915_wait_seqno(struct intel_engine_cs *ring, |
199b2bc2 | 2397 | uint32_t seqno); |
de151cf6 | 2398 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf); |
2021746e CW |
2399 | int __must_check |
2400 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, | |
2401 | bool write); | |
2402 | int __must_check | |
dabdfe02 CW |
2403 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write); |
2404 | int __must_check | |
2da3b9b9 CW |
2405 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
2406 | u32 alignment, | |
a4872ba6 | 2407 | struct intel_engine_cs *pipelined); |
cc98b413 | 2408 | void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj); |
00731155 | 2409 | int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj, |
6eeefaf3 | 2410 | int align); |
b29c19b6 | 2411 | int i915_gem_open(struct drm_device *dev, struct drm_file *file); |
05394f39 | 2412 | void i915_gem_release(struct drm_device *dev, struct drm_file *file); |
673a394b | 2413 | |
0fa87796 ID |
2414 | uint32_t |
2415 | i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode); | |
467cffba | 2416 | uint32_t |
d865110c ID |
2417 | i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size, |
2418 | int tiling_mode, bool fenced); | |
467cffba | 2419 | |
e4ffd173 CW |
2420 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
2421 | enum i915_cache_level cache_level); | |
2422 | ||
1286ff73 DV |
2423 | struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev, |
2424 | struct dma_buf *dma_buf); | |
2425 | ||
2426 | struct dma_buf *i915_gem_prime_export(struct drm_device *dev, | |
2427 | struct drm_gem_object *gem_obj, int flags); | |
2428 | ||
19b2dbde CW |
2429 | void i915_gem_restore_fences(struct drm_device *dev); |
2430 | ||
a70a3148 BW |
2431 | unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o, |
2432 | struct i915_address_space *vm); | |
2433 | bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o); | |
2434 | bool i915_gem_obj_bound(struct drm_i915_gem_object *o, | |
2435 | struct i915_address_space *vm); | |
2436 | unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o, | |
2437 | struct i915_address_space *vm); | |
2438 | struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj, | |
2439 | struct i915_address_space *vm); | |
accfef2e BW |
2440 | struct i915_vma * |
2441 | i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj, | |
2442 | struct i915_address_space *vm); | |
5c2abbea BW |
2443 | |
2444 | struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj); | |
d7f46fc4 BW |
2445 | static inline bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj) { |
2446 | struct i915_vma *vma; | |
2447 | list_for_each_entry(vma, &obj->vma_list, vma_link) | |
2448 | if (vma->pin_count > 0) | |
2449 | return true; | |
2450 | return false; | |
2451 | } | |
5c2abbea | 2452 | |
a70a3148 BW |
2453 | /* Some GGTT VM helpers */ |
2454 | #define obj_to_ggtt(obj) \ | |
2455 | (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base) | |
2456 | static inline bool i915_is_ggtt(struct i915_address_space *vm) | |
2457 | { | |
2458 | struct i915_address_space *ggtt = | |
2459 | &((struct drm_i915_private *)(vm)->dev->dev_private)->gtt.base; | |
2460 | return vm == ggtt; | |
2461 | } | |
2462 | ||
2463 | static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj) | |
2464 | { | |
2465 | return i915_gem_obj_bound(obj, obj_to_ggtt(obj)); | |
2466 | } | |
2467 | ||
2468 | static inline unsigned long | |
2469 | i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *obj) | |
2470 | { | |
2471 | return i915_gem_obj_offset(obj, obj_to_ggtt(obj)); | |
2472 | } | |
2473 | ||
2474 | static inline unsigned long | |
2475 | i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj) | |
2476 | { | |
2477 | return i915_gem_obj_size(obj, obj_to_ggtt(obj)); | |
2478 | } | |
c37e2204 BW |
2479 | |
2480 | static inline int __must_check | |
2481 | i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj, | |
2482 | uint32_t alignment, | |
1ec9e26d | 2483 | unsigned flags) |
c37e2204 | 2484 | { |
bf3d149b | 2485 | return i915_gem_object_pin(obj, obj_to_ggtt(obj), alignment, flags | PIN_GLOBAL); |
c37e2204 | 2486 | } |
a70a3148 | 2487 | |
b287110e DV |
2488 | static inline int |
2489 | i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj) | |
2490 | { | |
2491 | return i915_vma_unbind(i915_gem_obj_to_ggtt(obj)); | |
2492 | } | |
2493 | ||
2494 | void i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj); | |
2495 | ||
254f965c | 2496 | /* i915_gem_context.c */ |
0eea67eb | 2497 | #define ctx_to_ppgtt(ctx) container_of((ctx)->vm, struct i915_hw_ppgtt, base) |
8245be31 | 2498 | int __must_check i915_gem_context_init(struct drm_device *dev); |
254f965c | 2499 | void i915_gem_context_fini(struct drm_device *dev); |
acce9ffa | 2500 | void i915_gem_context_reset(struct drm_device *dev); |
e422b888 | 2501 | int i915_gem_context_open(struct drm_device *dev, struct drm_file *file); |
2fa48d8d | 2502 | int i915_gem_context_enable(struct drm_i915_private *dev_priv); |
254f965c | 2503 | void i915_gem_context_close(struct drm_device *dev, struct drm_file *file); |
a4872ba6 | 2504 | int i915_switch_context(struct intel_engine_cs *ring, |
273497e5 OM |
2505 | struct intel_context *to); |
2506 | struct intel_context * | |
41bde553 | 2507 | i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id); |
dce3271b | 2508 | void i915_gem_context_free(struct kref *ctx_ref); |
273497e5 | 2509 | static inline void i915_gem_context_reference(struct intel_context *ctx) |
dce3271b | 2510 | { |
691e6415 | 2511 | kref_get(&ctx->ref); |
dce3271b MK |
2512 | } |
2513 | ||
273497e5 | 2514 | static inline void i915_gem_context_unreference(struct intel_context *ctx) |
dce3271b | 2515 | { |
691e6415 | 2516 | kref_put(&ctx->ref, i915_gem_context_free); |
dce3271b MK |
2517 | } |
2518 | ||
273497e5 | 2519 | static inline bool i915_gem_context_is_default(const struct intel_context *c) |
3fac8978 | 2520 | { |
821d66dd | 2521 | return c->user_handle == DEFAULT_CONTEXT_HANDLE; |
3fac8978 MK |
2522 | } |
2523 | ||
84624813 BW |
2524 | int i915_gem_context_create_ioctl(struct drm_device *dev, void *data, |
2525 | struct drm_file *file); | |
2526 | int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data, | |
2527 | struct drm_file *file); | |
1286ff73 | 2528 | |
9d0a6fa6 | 2529 | /* i915_gem_render_state.c */ |
a4872ba6 | 2530 | int i915_gem_render_state_init(struct intel_engine_cs *ring); |
679845ed BW |
2531 | /* i915_gem_evict.c */ |
2532 | int __must_check i915_gem_evict_something(struct drm_device *dev, | |
2533 | struct i915_address_space *vm, | |
2534 | int min_size, | |
2535 | unsigned alignment, | |
2536 | unsigned cache_level, | |
d23db88c CW |
2537 | unsigned long start, |
2538 | unsigned long end, | |
1ec9e26d | 2539 | unsigned flags); |
679845ed BW |
2540 | int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle); |
2541 | int i915_gem_evict_everything(struct drm_device *dev); | |
1d2a314c | 2542 | |
0260c420 | 2543 | /* belongs in i915_gem_gtt.h */ |
d09105c6 | 2544 | static inline void i915_gem_chipset_flush(struct drm_device *dev) |
e76e9aeb BW |
2545 | { |
2546 | if (INTEL_INFO(dev)->gen < 6) | |
2547 | intel_gtt_chipset_flush(); | |
2548 | } | |
246cbfb5 | 2549 | |
9797fbfb CW |
2550 | /* i915_gem_stolen.c */ |
2551 | int i915_gem_init_stolen(struct drm_device *dev); | |
5e59f717 | 2552 | int i915_gem_stolen_setup_compression(struct drm_device *dev, int size, int fb_cpp); |
11be49eb | 2553 | void i915_gem_stolen_cleanup_compression(struct drm_device *dev); |
9797fbfb | 2554 | void i915_gem_cleanup_stolen(struct drm_device *dev); |
0104fdbb CW |
2555 | struct drm_i915_gem_object * |
2556 | i915_gem_object_create_stolen(struct drm_device *dev, u32 size); | |
866d12b4 CW |
2557 | struct drm_i915_gem_object * |
2558 | i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev, | |
2559 | u32 stolen_offset, | |
2560 | u32 gtt_offset, | |
2561 | u32 size); | |
9797fbfb | 2562 | |
673a394b | 2563 | /* i915_gem_tiling.c */ |
2c1792a1 | 2564 | static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj) |
e9b73c67 | 2565 | { |
50227e1c | 2566 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
e9b73c67 CW |
2567 | |
2568 | return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && | |
2569 | obj->tiling_mode != I915_TILING_NONE; | |
2570 | } | |
2571 | ||
673a394b | 2572 | void i915_gem_detect_bit_6_swizzle(struct drm_device *dev); |
05394f39 CW |
2573 | void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj); |
2574 | void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj); | |
673a394b EA |
2575 | |
2576 | /* i915_gem_debug.c */ | |
23bc5982 CW |
2577 | #if WATCH_LISTS |
2578 | int i915_verify_lists(struct drm_device *dev); | |
673a394b | 2579 | #else |
23bc5982 | 2580 | #define i915_verify_lists(dev) 0 |
673a394b | 2581 | #endif |
1da177e4 | 2582 | |
2017263e | 2583 | /* i915_debugfs.c */ |
27c202ad BG |
2584 | int i915_debugfs_init(struct drm_minor *minor); |
2585 | void i915_debugfs_cleanup(struct drm_minor *minor); | |
f8c168fa | 2586 | #ifdef CONFIG_DEBUG_FS |
07144428 DL |
2587 | void intel_display_crc_init(struct drm_device *dev); |
2588 | #else | |
f8c168fa | 2589 | static inline void intel_display_crc_init(struct drm_device *dev) {} |
07144428 | 2590 | #endif |
84734a04 MK |
2591 | |
2592 | /* i915_gpu_error.c */ | |
edc3d884 MK |
2593 | __printf(2, 3) |
2594 | void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...); | |
fc16b48b MK |
2595 | int i915_error_state_to_str(struct drm_i915_error_state_buf *estr, |
2596 | const struct i915_error_state_file_priv *error); | |
4dc955f7 MK |
2597 | int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb, |
2598 | size_t count, loff_t pos); | |
2599 | static inline void i915_error_state_buf_release( | |
2600 | struct drm_i915_error_state_buf *eb) | |
2601 | { | |
2602 | kfree(eb->buf); | |
2603 | } | |
58174462 MK |
2604 | void i915_capture_error_state(struct drm_device *dev, bool wedge, |
2605 | const char *error_msg); | |
84734a04 MK |
2606 | void i915_error_state_get(struct drm_device *dev, |
2607 | struct i915_error_state_file_priv *error_priv); | |
2608 | void i915_error_state_put(struct i915_error_state_file_priv *error_priv); | |
2609 | void i915_destroy_error_state(struct drm_device *dev); | |
2610 | ||
2611 | void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone); | |
2612 | const char *i915_cache_level_str(int type); | |
2017263e | 2613 | |
351e3db2 | 2614 | /* i915_cmd_parser.c */ |
d728c8ef | 2615 | int i915_cmd_parser_get_version(void); |
a4872ba6 OM |
2616 | int i915_cmd_parser_init_ring(struct intel_engine_cs *ring); |
2617 | void i915_cmd_parser_fini_ring(struct intel_engine_cs *ring); | |
2618 | bool i915_needs_cmd_parser(struct intel_engine_cs *ring); | |
2619 | int i915_parse_cmds(struct intel_engine_cs *ring, | |
351e3db2 BV |
2620 | struct drm_i915_gem_object *batch_obj, |
2621 | u32 batch_start_offset, | |
2622 | bool is_master); | |
2623 | ||
317c35d1 JB |
2624 | /* i915_suspend.c */ |
2625 | extern int i915_save_state(struct drm_device *dev); | |
2626 | extern int i915_restore_state(struct drm_device *dev); | |
0a3e67a4 | 2627 | |
d8157a36 DV |
2628 | /* i915_ums.c */ |
2629 | void i915_save_display_reg(struct drm_device *dev); | |
2630 | void i915_restore_display_reg(struct drm_device *dev); | |
317c35d1 | 2631 | |
0136db58 BW |
2632 | /* i915_sysfs.c */ |
2633 | void i915_setup_sysfs(struct drm_device *dev_priv); | |
2634 | void i915_teardown_sysfs(struct drm_device *dev_priv); | |
2635 | ||
f899fc64 CW |
2636 | /* intel_i2c.c */ |
2637 | extern int intel_setup_gmbus(struct drm_device *dev); | |
2638 | extern void intel_teardown_gmbus(struct drm_device *dev); | |
8f375e10 | 2639 | static inline bool intel_gmbus_is_port_valid(unsigned port) |
3bd7d909 | 2640 | { |
2ed06c93 | 2641 | return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD); |
3bd7d909 DK |
2642 | } |
2643 | ||
2644 | extern struct i2c_adapter *intel_gmbus_get_adapter( | |
2645 | struct drm_i915_private *dev_priv, unsigned port); | |
e957d772 CW |
2646 | extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed); |
2647 | extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit); | |
8f375e10 | 2648 | static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter) |
b8232e90 CW |
2649 | { |
2650 | return container_of(adapter, struct intel_gmbus, adapter)->force_bit; | |
2651 | } | |
f899fc64 CW |
2652 | extern void intel_i2c_reset(struct drm_device *dev); |
2653 | ||
3b617967 | 2654 | /* intel_opregion.c */ |
9c4b0a68 | 2655 | struct intel_encoder; |
44834a67 | 2656 | #ifdef CONFIG_ACPI |
27d50c82 | 2657 | extern int intel_opregion_setup(struct drm_device *dev); |
44834a67 CW |
2658 | extern void intel_opregion_init(struct drm_device *dev); |
2659 | extern void intel_opregion_fini(struct drm_device *dev); | |
3b617967 | 2660 | extern void intel_opregion_asle_intr(struct drm_device *dev); |
9c4b0a68 JN |
2661 | extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, |
2662 | bool enable); | |
ecbc5cf3 JN |
2663 | extern int intel_opregion_notify_adapter(struct drm_device *dev, |
2664 | pci_power_t state); | |
65e082c9 | 2665 | #else |
27d50c82 | 2666 | static inline int intel_opregion_setup(struct drm_device *dev) { return 0; } |
44834a67 CW |
2667 | static inline void intel_opregion_init(struct drm_device *dev) { return; } |
2668 | static inline void intel_opregion_fini(struct drm_device *dev) { return; } | |
3b617967 | 2669 | static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; } |
9c4b0a68 JN |
2670 | static inline int |
2671 | intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable) | |
2672 | { | |
2673 | return 0; | |
2674 | } | |
ecbc5cf3 JN |
2675 | static inline int |
2676 | intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state) | |
2677 | { | |
2678 | return 0; | |
2679 | } | |
65e082c9 | 2680 | #endif |
8ee1c3db | 2681 | |
723bfd70 JB |
2682 | /* intel_acpi.c */ |
2683 | #ifdef CONFIG_ACPI | |
2684 | extern void intel_register_dsm_handler(void); | |
2685 | extern void intel_unregister_dsm_handler(void); | |
2686 | #else | |
2687 | static inline void intel_register_dsm_handler(void) { return; } | |
2688 | static inline void intel_unregister_dsm_handler(void) { return; } | |
2689 | #endif /* CONFIG_ACPI */ | |
2690 | ||
79e53945 | 2691 | /* modesetting */ |
f817586c | 2692 | extern void intel_modeset_init_hw(struct drm_device *dev); |
7d708ee4 | 2693 | extern void intel_modeset_suspend_hw(struct drm_device *dev); |
79e53945 | 2694 | extern void intel_modeset_init(struct drm_device *dev); |
2c7111db | 2695 | extern void intel_modeset_gem_init(struct drm_device *dev); |
79e53945 | 2696 | extern void intel_modeset_cleanup(struct drm_device *dev); |
4932e2c3 | 2697 | extern void intel_connector_unregister(struct intel_connector *); |
28d52043 | 2698 | extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state); |
45e2b5f6 DV |
2699 | extern void intel_modeset_setup_hw_state(struct drm_device *dev, |
2700 | bool force_restore); | |
44cec740 | 2701 | extern void i915_redisable_vga(struct drm_device *dev); |
04098753 | 2702 | extern void i915_redisable_vga_power_on(struct drm_device *dev); |
ee5382ae | 2703 | extern bool intel_fbc_enabled(struct drm_device *dev); |
43a9539f | 2704 | extern void intel_disable_fbc(struct drm_device *dev); |
7648fa99 | 2705 | extern bool ironlake_set_drps(struct drm_device *dev, u8 val); |
dde86e2d | 2706 | extern void intel_init_pch_refclk(struct drm_device *dev); |
3b8d8d91 | 2707 | extern void gen6_set_rps(struct drm_device *dev, u8 val); |
0a073b84 | 2708 | extern void valleyview_set_rps(struct drm_device *dev, u8 val); |
5209b1f4 ID |
2709 | extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, |
2710 | bool enable); | |
0206e353 AJ |
2711 | extern void intel_detect_pch(struct drm_device *dev); |
2712 | extern int intel_trans_dp_port_sel(struct drm_crtc *crtc); | |
0136db58 | 2713 | extern int intel_enable_rc6(const struct drm_device *dev); |
3bad0781 | 2714 | |
2911a35b | 2715 | extern bool i915_semaphore_is_enabled(struct drm_device *dev); |
c0c7babc BW |
2716 | int i915_reg_read_ioctl(struct drm_device *dev, void *data, |
2717 | struct drm_file *file); | |
b6359918 MK |
2718 | int i915_get_reset_stats_ioctl(struct drm_device *dev, void *data, |
2719 | struct drm_file *file); | |
575155a9 | 2720 | |
84c33a64 SG |
2721 | void intel_notify_mmio_flip(struct intel_engine_cs *ring); |
2722 | ||
6ef3d427 CW |
2723 | /* overlay */ |
2724 | extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev); | |
edc3d884 MK |
2725 | extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e, |
2726 | struct intel_overlay_error_state *error); | |
c4a1d9e4 CW |
2727 | |
2728 | extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev); | |
edc3d884 | 2729 | extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e, |
c4a1d9e4 CW |
2730 | struct drm_device *dev, |
2731 | struct intel_display_error_state *error); | |
6ef3d427 | 2732 | |
b7287d80 BW |
2733 | /* On SNB platform, before reading ring registers forcewake bit |
2734 | * must be set to prevent GT core from power down and stale values being | |
2735 | * returned. | |
2736 | */ | |
c8d9a590 D |
2737 | void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine); |
2738 | void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine); | |
e998c40f | 2739 | void assert_force_wake_inactive(struct drm_i915_private *dev_priv); |
b7287d80 | 2740 | |
42c0526c BW |
2741 | int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val); |
2742 | int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val); | |
59de0813 JN |
2743 | |
2744 | /* intel_sideband.c */ | |
64936258 JN |
2745 | u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr); |
2746 | void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val); | |
2747 | u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr); | |
e9f882a3 JN |
2748 | u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg); |
2749 | void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
2750 | u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg); | |
2751 | void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
2752 | u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg); | |
2753 | void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
f3419158 JB |
2754 | u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg); |
2755 | void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
e9f882a3 JN |
2756 | u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg); |
2757 | void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
5e69f97f CML |
2758 | u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg); |
2759 | void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val); | |
59de0813 JN |
2760 | u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg, |
2761 | enum intel_sbi_destination destination); | |
2762 | void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value, | |
2763 | enum intel_sbi_destination destination); | |
e9fe51c6 SK |
2764 | u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg); |
2765 | void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
0a073b84 | 2766 | |
2ec3815f VS |
2767 | int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val); |
2768 | int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val); | |
42c0526c | 2769 | |
c8d9a590 D |
2770 | #define FORCEWAKE_RENDER (1 << 0) |
2771 | #define FORCEWAKE_MEDIA (1 << 1) | |
2772 | #define FORCEWAKE_ALL (FORCEWAKE_RENDER | FORCEWAKE_MEDIA) | |
2773 | ||
2774 | ||
0b274481 BW |
2775 | #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true) |
2776 | #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true) | |
2777 | ||
2778 | #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true) | |
2779 | #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true) | |
2780 | #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false) | |
2781 | #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false) | |
2782 | ||
2783 | #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true) | |
2784 | #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true) | |
2785 | #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false) | |
2786 | #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false) | |
2787 | ||
698b3135 CW |
2788 | /* Be very careful with read/write 64-bit values. On 32-bit machines, they |
2789 | * will be implemented using 2 32-bit writes in an arbitrary order with | |
2790 | * an arbitrary delay between them. This can cause the hardware to | |
2791 | * act upon the intermediate value, possibly leading to corruption and | |
2792 | * machine death. You have been warned. | |
2793 | */ | |
0b274481 BW |
2794 | #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true) |
2795 | #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true) | |
cae5852d | 2796 | |
50877445 CW |
2797 | #define I915_READ64_2x32(lower_reg, upper_reg) ({ \ |
2798 | u32 upper = I915_READ(upper_reg); \ | |
2799 | u32 lower = I915_READ(lower_reg); \ | |
2800 | u32 tmp = I915_READ(upper_reg); \ | |
2801 | if (upper != tmp) { \ | |
2802 | upper = tmp; \ | |
2803 | lower = I915_READ(lower_reg); \ | |
2804 | WARN_ON(I915_READ(upper_reg) != upper); \ | |
2805 | } \ | |
2806 | (u64)upper << 32 | lower; }) | |
2807 | ||
cae5852d ZN |
2808 | #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg) |
2809 | #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg) | |
2810 | ||
55bc60db VS |
2811 | /* "Broadcast RGB" property */ |
2812 | #define INTEL_BROADCAST_RGB_AUTO 0 | |
2813 | #define INTEL_BROADCAST_RGB_FULL 1 | |
2814 | #define INTEL_BROADCAST_RGB_LIMITED 2 | |
ba4f01a3 | 2815 | |
766aa1c4 VS |
2816 | static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev) |
2817 | { | |
92e23b99 | 2818 | if (IS_VALLEYVIEW(dev)) |
766aa1c4 | 2819 | return VLV_VGACNTRL; |
92e23b99 SJ |
2820 | else if (INTEL_INFO(dev)->gen >= 5) |
2821 | return CPU_VGACNTRL; | |
766aa1c4 VS |
2822 | else |
2823 | return VGACNTRL; | |
2824 | } | |
2825 | ||
2bb4629a VS |
2826 | static inline void __user *to_user_ptr(u64 address) |
2827 | { | |
2828 | return (void __user *)(uintptr_t)address; | |
2829 | } | |
2830 | ||
df97729f ID |
2831 | static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m) |
2832 | { | |
2833 | unsigned long j = msecs_to_jiffies(m); | |
2834 | ||
2835 | return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1); | |
2836 | } | |
2837 | ||
2838 | static inline unsigned long | |
2839 | timespec_to_jiffies_timeout(const struct timespec *value) | |
2840 | { | |
2841 | unsigned long j = timespec_to_jiffies(value); | |
2842 | ||
2843 | return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1); | |
2844 | } | |
2845 | ||
dce56b3c PZ |
2846 | /* |
2847 | * If you need to wait X milliseconds between events A and B, but event B | |
2848 | * doesn't happen exactly after event A, you record the timestamp (jiffies) of | |
2849 | * when event A happened, then just before event B you call this function and | |
2850 | * pass the timestamp as the first argument, and X as the second argument. | |
2851 | */ | |
2852 | static inline void | |
2853 | wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms) | |
2854 | { | |
ec5e0cfb | 2855 | unsigned long target_jiffies, tmp_jiffies, remaining_jiffies; |
dce56b3c PZ |
2856 | |
2857 | /* | |
2858 | * Don't re-read the value of "jiffies" every time since it may change | |
2859 | * behind our back and break the math. | |
2860 | */ | |
2861 | tmp_jiffies = jiffies; | |
2862 | target_jiffies = timestamp_jiffies + | |
2863 | msecs_to_jiffies_timeout(to_wait_ms); | |
2864 | ||
2865 | if (time_after(target_jiffies, tmp_jiffies)) { | |
ec5e0cfb ID |
2866 | remaining_jiffies = target_jiffies - tmp_jiffies; |
2867 | while (remaining_jiffies) | |
2868 | remaining_jiffies = | |
2869 | schedule_timeout_uninterruptible(remaining_jiffies); | |
dce56b3c PZ |
2870 | } |
2871 | } | |
2872 | ||
1da177e4 | 2873 | #endif |