Commit | Line | Data |
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1da177e4 LT |
1 | /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- |
2 | */ | |
0d6aa60b | 3 | /* |
bc54fd1a | 4 | * |
1da177e4 LT |
5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
6 | * All Rights Reserved. | |
bc54fd1a DA |
7 | * |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the | |
10 | * "Software"), to deal in the Software without restriction, including | |
11 | * without limitation the rights to use, copy, modify, merge, publish, | |
12 | * distribute, sub license, and/or sell copies of the Software, and to | |
13 | * permit persons to whom the Software is furnished to do so, subject to | |
14 | * the following conditions: | |
15 | * | |
16 | * The above copyright notice and this permission notice (including the | |
17 | * next paragraph) shall be included in all copies or substantial portions | |
18 | * of the Software. | |
19 | * | |
20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
27 | * | |
0d6aa60b | 28 | */ |
1da177e4 LT |
29 | |
30 | #ifndef _I915_DRV_H_ | |
31 | #define _I915_DRV_H_ | |
32 | ||
585fb111 | 33 | #include "i915_reg.h" |
79e53945 | 34 | #include "intel_bios.h" |
8187a2b7 | 35 | #include "intel_ringbuffer.h" |
0839ccb8 | 36 | #include <linux/io-mapping.h> |
f899fc64 | 37 | #include <linux/i2c.h> |
c167a6fc | 38 | #include <linux/i2c-algo-bit.h> |
0ade6386 | 39 | #include <drm/intel-gtt.h> |
aaa6fd2a | 40 | #include <linux/backlight.h> |
2911a35b | 41 | #include <linux/intel-iommu.h> |
742cbee8 | 42 | #include <linux/kref.h> |
585fb111 | 43 | |
1da177e4 LT |
44 | /* General customization: |
45 | */ | |
46 | ||
47 | #define DRIVER_AUTHOR "Tungsten Graphics, Inc." | |
48 | ||
49 | #define DRIVER_NAME "i915" | |
50 | #define DRIVER_DESC "Intel Graphics" | |
673a394b | 51 | #define DRIVER_DATE "20080730" |
1da177e4 | 52 | |
317c35d1 JB |
53 | enum pipe { |
54 | PIPE_A = 0, | |
55 | PIPE_B, | |
9db4a9c7 JB |
56 | PIPE_C, |
57 | I915_MAX_PIPES | |
317c35d1 | 58 | }; |
9db4a9c7 | 59 | #define pipe_name(p) ((p) + 'A') |
317c35d1 | 60 | |
a5c961d1 PZ |
61 | enum transcoder { |
62 | TRANSCODER_A = 0, | |
63 | TRANSCODER_B, | |
64 | TRANSCODER_C, | |
65 | TRANSCODER_EDP = 0xF, | |
66 | }; | |
67 | #define transcoder_name(t) ((t) + 'A') | |
68 | ||
80824003 JB |
69 | enum plane { |
70 | PLANE_A = 0, | |
71 | PLANE_B, | |
9db4a9c7 | 72 | PLANE_C, |
80824003 | 73 | }; |
9db4a9c7 | 74 | #define plane_name(p) ((p) + 'A') |
52440211 | 75 | |
2b139522 ED |
76 | enum port { |
77 | PORT_A = 0, | |
78 | PORT_B, | |
79 | PORT_C, | |
80 | PORT_D, | |
81 | PORT_E, | |
82 | I915_MAX_PORTS | |
83 | }; | |
84 | #define port_name(p) ((p) + 'A') | |
85 | ||
62fdfeaf EA |
86 | #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT)) |
87 | ||
9db4a9c7 JB |
88 | #define for_each_pipe(p) for ((p) = 0; (p) < dev_priv->num_pipe; (p)++) |
89 | ||
6c2b7c12 DV |
90 | #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \ |
91 | list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \ | |
92 | if ((intel_encoder)->base.crtc == (__crtc)) | |
93 | ||
ee7b9f93 JB |
94 | struct intel_pch_pll { |
95 | int refcount; /* count of number of CRTCs sharing this PLL */ | |
96 | int active; /* count of number of active CRTCs (i.e. DPMS on) */ | |
97 | bool on; /* is the PLL actually active? Disabled during modeset */ | |
98 | int pll_reg; | |
99 | int fp0_reg; | |
100 | int fp1_reg; | |
101 | }; | |
102 | #define I915_NUM_PLLS 2 | |
103 | ||
6441ab5f PZ |
104 | struct intel_ddi_plls { |
105 | int spll_refcount; | |
106 | int wrpll1_refcount; | |
107 | int wrpll2_refcount; | |
108 | }; | |
109 | ||
1da177e4 LT |
110 | /* Interface history: |
111 | * | |
112 | * 1.1: Original. | |
0d6aa60b DA |
113 | * 1.2: Add Power Management |
114 | * 1.3: Add vblank support | |
de227f5f | 115 | * 1.4: Fix cmdbuffer path, add heap destroy |
702880f2 | 116 | * 1.5: Add vblank pipe configuration |
2228ed67 MCA |
117 | * 1.6: - New ioctl for scheduling buffer swaps on vertical blank |
118 | * - Support vertical blank on secondary display pipe | |
1da177e4 LT |
119 | */ |
120 | #define DRIVER_MAJOR 1 | |
2228ed67 | 121 | #define DRIVER_MINOR 6 |
1da177e4 LT |
122 | #define DRIVER_PATCHLEVEL 0 |
123 | ||
673a394b | 124 | #define WATCH_COHERENCY 0 |
23bc5982 | 125 | #define WATCH_LISTS 0 |
42d6ab48 | 126 | #define WATCH_GTT 0 |
673a394b | 127 | |
71acb5eb DA |
128 | #define I915_GEM_PHYS_CURSOR_0 1 |
129 | #define I915_GEM_PHYS_CURSOR_1 2 | |
130 | #define I915_GEM_PHYS_OVERLAY_REGS 3 | |
131 | #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS) | |
132 | ||
133 | struct drm_i915_gem_phys_object { | |
134 | int id; | |
135 | struct page **page_list; | |
136 | drm_dma_handle_t *handle; | |
05394f39 | 137 | struct drm_i915_gem_object *cur_obj; |
71acb5eb DA |
138 | }; |
139 | ||
0a3e67a4 JB |
140 | struct opregion_header; |
141 | struct opregion_acpi; | |
142 | struct opregion_swsci; | |
143 | struct opregion_asle; | |
8d715f00 | 144 | struct drm_i915_private; |
0a3e67a4 | 145 | |
8ee1c3db | 146 | struct intel_opregion { |
5bc4418b BW |
147 | struct opregion_header __iomem *header; |
148 | struct opregion_acpi __iomem *acpi; | |
149 | struct opregion_swsci __iomem *swsci; | |
150 | struct opregion_asle __iomem *asle; | |
151 | void __iomem *vbt; | |
01fe9dbd | 152 | u32 __iomem *lid_state; |
8ee1c3db | 153 | }; |
44834a67 | 154 | #define OPREGION_SIZE (8*1024) |
8ee1c3db | 155 | |
6ef3d427 CW |
156 | struct intel_overlay; |
157 | struct intel_overlay_error_state; | |
158 | ||
7c1c2871 DA |
159 | struct drm_i915_master_private { |
160 | drm_local_map_t *sarea; | |
161 | struct _drm_i915_sarea *sarea_priv; | |
162 | }; | |
de151cf6 | 163 | #define I915_FENCE_REG_NONE -1 |
4b9de737 DV |
164 | #define I915_MAX_NUM_FENCES 16 |
165 | /* 16 fences + sign bit for FENCE_REG_NONE */ | |
166 | #define I915_MAX_NUM_FENCE_BITS 5 | |
de151cf6 JB |
167 | |
168 | struct drm_i915_fence_reg { | |
007cc8ac | 169 | struct list_head lru_list; |
caea7476 | 170 | struct drm_i915_gem_object *obj; |
1690e1eb | 171 | int pin_count; |
de151cf6 | 172 | }; |
7c1c2871 | 173 | |
9b9d172d | 174 | struct sdvo_device_mapping { |
e957d772 | 175 | u8 initialized; |
9b9d172d | 176 | u8 dvo_port; |
177 | u8 slave_addr; | |
178 | u8 dvo_wiring; | |
e957d772 | 179 | u8 i2c_pin; |
b1083333 | 180 | u8 ddc_pin; |
9b9d172d | 181 | }; |
182 | ||
c4a1d9e4 CW |
183 | struct intel_display_error_state; |
184 | ||
63eeaf38 | 185 | struct drm_i915_error_state { |
742cbee8 | 186 | struct kref ref; |
63eeaf38 JB |
187 | u32 eir; |
188 | u32 pgtbl_er; | |
be998e2e | 189 | u32 ier; |
b9a3906b | 190 | u32 ccid; |
9574b3fe | 191 | bool waiting[I915_NUM_RINGS]; |
9db4a9c7 | 192 | u32 pipestat[I915_MAX_PIPES]; |
c1cd90ed DV |
193 | u32 tail[I915_NUM_RINGS]; |
194 | u32 head[I915_NUM_RINGS]; | |
d27b1e0e DV |
195 | u32 ipeir[I915_NUM_RINGS]; |
196 | u32 ipehr[I915_NUM_RINGS]; | |
197 | u32 instdone[I915_NUM_RINGS]; | |
198 | u32 acthd[I915_NUM_RINGS]; | |
7e3b8737 | 199 | u32 semaphore_mboxes[I915_NUM_RINGS][I915_NUM_RINGS - 1]; |
12f55818 | 200 | u32 rc_psmi[I915_NUM_RINGS]; /* sleep state */ |
7e3b8737 DV |
201 | /* our own tracking of ring head and tail */ |
202 | u32 cpu_ring_head[I915_NUM_RINGS]; | |
203 | u32 cpu_ring_tail[I915_NUM_RINGS]; | |
1d8f38f4 | 204 | u32 error; /* gen6+ */ |
71e172e8 | 205 | u32 err_int; /* gen7 */ |
c1cd90ed DV |
206 | u32 instpm[I915_NUM_RINGS]; |
207 | u32 instps[I915_NUM_RINGS]; | |
050ee91f | 208 | u32 extra_instdone[I915_NUM_INSTDONE_REG]; |
d27b1e0e | 209 | u32 seqno[I915_NUM_RINGS]; |
9df30794 | 210 | u64 bbaddr; |
33f3f518 DV |
211 | u32 fault_reg[I915_NUM_RINGS]; |
212 | u32 done_reg; | |
c1cd90ed | 213 | u32 faddr[I915_NUM_RINGS]; |
4b9de737 | 214 | u64 fence[I915_MAX_NUM_FENCES]; |
63eeaf38 | 215 | struct timeval time; |
52d39a21 CW |
216 | struct drm_i915_error_ring { |
217 | struct drm_i915_error_object { | |
218 | int page_count; | |
219 | u32 gtt_offset; | |
220 | u32 *pages[0]; | |
221 | } *ringbuffer, *batchbuffer; | |
222 | struct drm_i915_error_request { | |
223 | long jiffies; | |
224 | u32 seqno; | |
ee4f42b1 | 225 | u32 tail; |
52d39a21 CW |
226 | } *requests; |
227 | int num_requests; | |
228 | } ring[I915_NUM_RINGS]; | |
9df30794 | 229 | struct drm_i915_error_buffer { |
a779e5ab | 230 | u32 size; |
9df30794 | 231 | u32 name; |
0201f1ec | 232 | u32 rseqno, wseqno; |
9df30794 CW |
233 | u32 gtt_offset; |
234 | u32 read_domains; | |
235 | u32 write_domain; | |
4b9de737 | 236 | s32 fence_reg:I915_MAX_NUM_FENCE_BITS; |
9df30794 CW |
237 | s32 pinned:2; |
238 | u32 tiling:2; | |
239 | u32 dirty:1; | |
240 | u32 purgeable:1; | |
5d1333fc | 241 | s32 ring:4; |
93dfb40c | 242 | u32 cache_level:2; |
c724e8a9 CW |
243 | } *active_bo, *pinned_bo; |
244 | u32 active_bo_count, pinned_bo_count; | |
6ef3d427 | 245 | struct intel_overlay_error_state *overlay; |
c4a1d9e4 | 246 | struct intel_display_error_state *display; |
63eeaf38 JB |
247 | }; |
248 | ||
e70236a8 | 249 | struct drm_i915_display_funcs { |
ee5382ae | 250 | bool (*fbc_enabled)(struct drm_device *dev); |
e70236a8 JB |
251 | void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval); |
252 | void (*disable_fbc)(struct drm_device *dev); | |
253 | int (*get_display_clock_speed)(struct drm_device *dev); | |
254 | int (*get_fifo_size)(struct drm_device *dev, int plane); | |
d210246a | 255 | void (*update_wm)(struct drm_device *dev); |
b840d907 JB |
256 | void (*update_sprite_wm)(struct drm_device *dev, int pipe, |
257 | uint32_t sprite_width, int pixel_size); | |
1f8eeabf ED |
258 | void (*update_linetime_wm)(struct drm_device *dev, int pipe, |
259 | struct drm_display_mode *mode); | |
47fab737 | 260 | void (*modeset_global_resources)(struct drm_device *dev); |
f564048e EA |
261 | int (*crtc_mode_set)(struct drm_crtc *crtc, |
262 | struct drm_display_mode *mode, | |
263 | struct drm_display_mode *adjusted_mode, | |
264 | int x, int y, | |
265 | struct drm_framebuffer *old_fb); | |
76e5a89c DV |
266 | void (*crtc_enable)(struct drm_crtc *crtc); |
267 | void (*crtc_disable)(struct drm_crtc *crtc); | |
ee7b9f93 | 268 | void (*off)(struct drm_crtc *crtc); |
e0dac65e WF |
269 | void (*write_eld)(struct drm_connector *connector, |
270 | struct drm_crtc *crtc); | |
674cf967 | 271 | void (*fdi_link_train)(struct drm_crtc *crtc); |
6067aaea | 272 | void (*init_clock_gating)(struct drm_device *dev); |
8c9f3aaf JB |
273 | int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc, |
274 | struct drm_framebuffer *fb, | |
275 | struct drm_i915_gem_object *obj); | |
17638cd6 JB |
276 | int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb, |
277 | int x, int y); | |
e70236a8 JB |
278 | /* clock updates for mode set */ |
279 | /* cursor updates */ | |
280 | /* render clock increase/decrease */ | |
281 | /* display clock increase/decrease */ | |
282 | /* pll clock increase/decrease */ | |
e70236a8 JB |
283 | }; |
284 | ||
990bbdad CW |
285 | struct drm_i915_gt_funcs { |
286 | void (*force_wake_get)(struct drm_i915_private *dev_priv); | |
287 | void (*force_wake_put)(struct drm_i915_private *dev_priv); | |
288 | }; | |
289 | ||
c96ea64e DV |
290 | #define DEV_INFO_FLAGS \ |
291 | DEV_INFO_FLAG(is_mobile) DEV_INFO_SEP \ | |
292 | DEV_INFO_FLAG(is_i85x) DEV_INFO_SEP \ | |
293 | DEV_INFO_FLAG(is_i915g) DEV_INFO_SEP \ | |
294 | DEV_INFO_FLAG(is_i945gm) DEV_INFO_SEP \ | |
295 | DEV_INFO_FLAG(is_g33) DEV_INFO_SEP \ | |
296 | DEV_INFO_FLAG(need_gfx_hws) DEV_INFO_SEP \ | |
297 | DEV_INFO_FLAG(is_g4x) DEV_INFO_SEP \ | |
298 | DEV_INFO_FLAG(is_pineview) DEV_INFO_SEP \ | |
299 | DEV_INFO_FLAG(is_broadwater) DEV_INFO_SEP \ | |
300 | DEV_INFO_FLAG(is_crestline) DEV_INFO_SEP \ | |
301 | DEV_INFO_FLAG(is_ivybridge) DEV_INFO_SEP \ | |
302 | DEV_INFO_FLAG(is_valleyview) DEV_INFO_SEP \ | |
303 | DEV_INFO_FLAG(is_haswell) DEV_INFO_SEP \ | |
304 | DEV_INFO_FLAG(has_force_wake) DEV_INFO_SEP \ | |
305 | DEV_INFO_FLAG(has_fbc) DEV_INFO_SEP \ | |
306 | DEV_INFO_FLAG(has_pipe_cxsr) DEV_INFO_SEP \ | |
307 | DEV_INFO_FLAG(has_hotplug) DEV_INFO_SEP \ | |
308 | DEV_INFO_FLAG(cursor_needs_physical) DEV_INFO_SEP \ | |
309 | DEV_INFO_FLAG(has_overlay) DEV_INFO_SEP \ | |
310 | DEV_INFO_FLAG(overlay_needs_physical) DEV_INFO_SEP \ | |
311 | DEV_INFO_FLAG(supports_tv) DEV_INFO_SEP \ | |
312 | DEV_INFO_FLAG(has_bsd_ring) DEV_INFO_SEP \ | |
313 | DEV_INFO_FLAG(has_blt_ring) DEV_INFO_SEP \ | |
314 | DEV_INFO_FLAG(has_llc) | |
315 | ||
cfdf1fa2 | 316 | struct intel_device_info { |
c96c3a8c | 317 | u8 gen; |
0206e353 AJ |
318 | u8 is_mobile:1; |
319 | u8 is_i85x:1; | |
320 | u8 is_i915g:1; | |
321 | u8 is_i945gm:1; | |
322 | u8 is_g33:1; | |
323 | u8 need_gfx_hws:1; | |
324 | u8 is_g4x:1; | |
325 | u8 is_pineview:1; | |
326 | u8 is_broadwater:1; | |
327 | u8 is_crestline:1; | |
328 | u8 is_ivybridge:1; | |
70a3eb7a | 329 | u8 is_valleyview:1; |
b7884eb4 | 330 | u8 has_force_wake:1; |
4cae9ae0 | 331 | u8 is_haswell:1; |
0206e353 AJ |
332 | u8 has_fbc:1; |
333 | u8 has_pipe_cxsr:1; | |
334 | u8 has_hotplug:1; | |
335 | u8 cursor_needs_physical:1; | |
336 | u8 has_overlay:1; | |
337 | u8 overlay_needs_physical:1; | |
338 | u8 supports_tv:1; | |
339 | u8 has_bsd_ring:1; | |
340 | u8 has_blt_ring:1; | |
3d29b842 | 341 | u8 has_llc:1; |
cfdf1fa2 KH |
342 | }; |
343 | ||
1d2a314c DV |
344 | #define I915_PPGTT_PD_ENTRIES 512 |
345 | #define I915_PPGTT_PT_ENTRIES 1024 | |
346 | struct i915_hw_ppgtt { | |
8f2c59f0 | 347 | struct drm_device *dev; |
1d2a314c DV |
348 | unsigned num_pd_entries; |
349 | struct page **pt_pages; | |
350 | uint32_t pd_offset; | |
351 | dma_addr_t *pt_dma_addr; | |
352 | dma_addr_t scratch_page_dma_addr; | |
353 | }; | |
354 | ||
40521054 BW |
355 | |
356 | /* This must match up with the value previously used for execbuf2.rsvd1. */ | |
357 | #define DEFAULT_CONTEXT_ID 0 | |
358 | struct i915_hw_context { | |
359 | int id; | |
e0556841 | 360 | bool is_initialized; |
40521054 BW |
361 | struct drm_i915_file_private *file_priv; |
362 | struct intel_ring_buffer *ring; | |
363 | struct drm_i915_gem_object *obj; | |
364 | }; | |
365 | ||
b5e50c3f | 366 | enum no_fbc_reason { |
bed4a673 | 367 | FBC_NO_OUTPUT, /* no outputs enabled to compress */ |
b5e50c3f JB |
368 | FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */ |
369 | FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */ | |
370 | FBC_MODE_TOO_LARGE, /* mode too large for compression */ | |
371 | FBC_BAD_PLANE, /* fbc not supported on plane */ | |
372 | FBC_NOT_TILED, /* buffer not tiled */ | |
9c928d16 | 373 | FBC_MULTIPLE_PIPES, /* more than one pipe active */ |
c1a9f047 | 374 | FBC_MODULE_PARAM, |
b5e50c3f JB |
375 | }; |
376 | ||
3bad0781 | 377 | enum intel_pch { |
f0350830 | 378 | PCH_NONE = 0, /* No PCH present */ |
3bad0781 ZW |
379 | PCH_IBX, /* Ibexpeak PCH */ |
380 | PCH_CPT, /* Cougarpoint PCH */ | |
eb877ebf | 381 | PCH_LPT, /* Lynxpoint PCH */ |
3bad0781 ZW |
382 | }; |
383 | ||
b690e96c | 384 | #define QUIRK_PIPEA_FORCE (1<<0) |
435793df | 385 | #define QUIRK_LVDS_SSC_DISABLE (1<<1) |
4dca20ef | 386 | #define QUIRK_INVERT_BRIGHTNESS (1<<2) |
b690e96c | 387 | |
8be48d92 | 388 | struct intel_fbdev; |
1630fe75 | 389 | struct intel_fbc_work; |
38651674 | 390 | |
c2b9152f DV |
391 | struct intel_gmbus { |
392 | struct i2c_adapter adapter; | |
f6f808c8 | 393 | bool force_bit; |
c2b9152f | 394 | u32 reg0; |
36c785f0 | 395 | u32 gpio_reg; |
c167a6fc | 396 | struct i2c_algo_bit_data bit_algo; |
c2b9152f DV |
397 | struct drm_i915_private *dev_priv; |
398 | }; | |
399 | ||
1da177e4 | 400 | typedef struct drm_i915_private { |
673a394b EA |
401 | struct drm_device *dev; |
402 | ||
cfdf1fa2 KH |
403 | const struct intel_device_info *info; |
404 | ||
72bfa19c | 405 | int relative_constants_mode; |
ac5c4e76 | 406 | |
3043c60c | 407 | void __iomem *regs; |
990bbdad CW |
408 | |
409 | struct drm_i915_gt_funcs gt; | |
9f1f46a4 DV |
410 | /** gt_fifo_count and the subsequent register write are synchronized |
411 | * with dev->struct_mutex. */ | |
412 | unsigned gt_fifo_count; | |
413 | /** forcewake_count is protected by gt_lock */ | |
414 | unsigned forcewake_count; | |
415 | /** gt_lock is also taken in irq contexts. */ | |
416 | struct spinlock gt_lock; | |
1da177e4 | 417 | |
f2c9677b | 418 | struct intel_gmbus gmbus[GMBUS_NUM_PORTS]; |
f899fc64 | 419 | |
8a8ed1f5 YS |
420 | /** gmbus_mutex protects against concurrent usage of the single hw gmbus |
421 | * controller on different i2c buses. */ | |
422 | struct mutex gmbus_mutex; | |
423 | ||
110447fc DV |
424 | /** |
425 | * Base address of the gmbus and gpio block. | |
426 | */ | |
427 | uint32_t gpio_mmio_base; | |
428 | ||
ec2a4c3f | 429 | struct pci_dev *bridge_dev; |
1ec14ad3 | 430 | struct intel_ring_buffer ring[I915_NUM_RINGS]; |
6f392d54 | 431 | uint32_t next_seqno; |
1da177e4 | 432 | |
9c8da5eb | 433 | drm_dma_handle_t *status_page_dmah; |
0a3e67a4 | 434 | uint32_t counter; |
05394f39 CW |
435 | struct drm_i915_gem_object *pwrctx; |
436 | struct drm_i915_gem_object *renderctx; | |
1da177e4 | 437 | |
d7658989 JB |
438 | struct resource mch_res; |
439 | ||
1da177e4 | 440 | atomic_t irq_received; |
1ec14ad3 CW |
441 | |
442 | /* protects the irq masks */ | |
443 | spinlock_t irq_lock; | |
57f350b6 JB |
444 | |
445 | /* DPIO indirect register protection */ | |
446 | spinlock_t dpio_lock; | |
447 | ||
ed4cb414 | 448 | /** Cached value of IMR to avoid reads in updating the bitfield */ |
7c463586 | 449 | u32 pipestat[2]; |
1ec14ad3 CW |
450 | u32 irq_mask; |
451 | u32 gt_irq_mask; | |
452 | u32 pch_irq_mask; | |
1da177e4 | 453 | |
5ca58282 JB |
454 | u32 hotplug_supported_mask; |
455 | struct work_struct hotplug_work; | |
456 | ||
a3524f1b | 457 | int num_pipe; |
ee7b9f93 | 458 | int num_pch_pll; |
a6b54f3f | 459 | |
f65d9421 | 460 | /* For hangcheck timer */ |
576ae4b8 | 461 | #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */ |
cecc21fe | 462 | #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD) |
f65d9421 BG |
463 | struct timer_list hangcheck_timer; |
464 | int hangcheck_count; | |
b4519513 | 465 | uint32_t last_acthd[I915_NUM_RINGS]; |
050ee91f | 466 | uint32_t prev_instdone[I915_NUM_INSTDONE_REG]; |
f65d9421 | 467 | |
e5eb3d63 DV |
468 | unsigned int stop_rings; |
469 | ||
80824003 | 470 | unsigned long cfb_size; |
016b9b61 CW |
471 | unsigned int cfb_fb; |
472 | enum plane cfb_plane; | |
bed4a673 | 473 | int cfb_y; |
1630fe75 | 474 | struct intel_fbc_work *fbc_work; |
80824003 | 475 | |
8ee1c3db MG |
476 | struct intel_opregion opregion; |
477 | ||
02e792fb DV |
478 | /* overlay */ |
479 | struct intel_overlay *overlay; | |
b840d907 | 480 | bool sprite_scaling_enabled; |
02e792fb | 481 | |
79e53945 | 482 | /* LVDS info */ |
a9573556 | 483 | int backlight_level; /* restore backlight to this value */ |
47356eb6 | 484 | bool backlight_enabled; |
88631706 ML |
485 | struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ |
486 | struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ | |
79e53945 JB |
487 | |
488 | /* Feature bits from the VBIOS */ | |
95281e35 HE |
489 | unsigned int int_tv_support:1; |
490 | unsigned int lvds_dither:1; | |
491 | unsigned int lvds_vbt:1; | |
492 | unsigned int int_crt_support:1; | |
43565a06 | 493 | unsigned int lvds_use_ssc:1; |
abd06860 | 494 | unsigned int display_clock_mode:1; |
43565a06 | 495 | int lvds_ssc_freq; |
b0354385 TI |
496 | unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */ |
497 | unsigned int lvds_val; /* used for checking LVDS channel mode */ | |
5ceb0f9b | 498 | struct { |
9f0e7ff4 JB |
499 | int rate; |
500 | int lanes; | |
501 | int preemphasis; | |
502 | int vswing; | |
503 | ||
504 | bool initialized; | |
505 | bool support; | |
506 | int bpp; | |
507 | struct edp_power_seq pps; | |
5ceb0f9b | 508 | } edp; |
89667383 | 509 | bool no_aux_handshake; |
79e53945 | 510 | |
f899fc64 | 511 | int crt_ddc_pin; |
4b9de737 | 512 | struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */ |
de151cf6 JB |
513 | int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */ |
514 | int num_fence_regs; /* 8 on pre-965, 16 otherwise */ | |
515 | ||
95534263 | 516 | unsigned int fsb_freq, mem_freq, is_ddr3; |
7662c8bd | 517 | |
63eeaf38 | 518 | spinlock_t error_lock; |
742cbee8 | 519 | /* Protected by dev->error_lock. */ |
63eeaf38 | 520 | struct drm_i915_error_state *first_error; |
8a905236 | 521 | struct work_struct error_work; |
30dbf0c0 | 522 | struct completion error_completion; |
9c9fe1f8 | 523 | struct workqueue_struct *wq; |
63eeaf38 | 524 | |
e70236a8 JB |
525 | /* Display functions */ |
526 | struct drm_i915_display_funcs display; | |
527 | ||
3bad0781 ZW |
528 | /* PCH chipset type */ |
529 | enum intel_pch pch_type; | |
530 | ||
b690e96c JB |
531 | unsigned long quirks; |
532 | ||
ba8bbcf6 | 533 | /* Register state */ |
c9354c85 | 534 | bool modeset_on_lid; |
ba8bbcf6 JB |
535 | u8 saveLBB; |
536 | u32 saveDSPACNTR; | |
537 | u32 saveDSPBCNTR; | |
e948e994 | 538 | u32 saveDSPARB; |
968b503e | 539 | u32 saveHWS; |
ba8bbcf6 JB |
540 | u32 savePIPEACONF; |
541 | u32 savePIPEBCONF; | |
542 | u32 savePIPEASRC; | |
543 | u32 savePIPEBSRC; | |
544 | u32 saveFPA0; | |
545 | u32 saveFPA1; | |
546 | u32 saveDPLL_A; | |
547 | u32 saveDPLL_A_MD; | |
548 | u32 saveHTOTAL_A; | |
549 | u32 saveHBLANK_A; | |
550 | u32 saveHSYNC_A; | |
551 | u32 saveVTOTAL_A; | |
552 | u32 saveVBLANK_A; | |
553 | u32 saveVSYNC_A; | |
554 | u32 saveBCLRPAT_A; | |
5586c8bc | 555 | u32 saveTRANSACONF; |
42048781 ZW |
556 | u32 saveTRANS_HTOTAL_A; |
557 | u32 saveTRANS_HBLANK_A; | |
558 | u32 saveTRANS_HSYNC_A; | |
559 | u32 saveTRANS_VTOTAL_A; | |
560 | u32 saveTRANS_VBLANK_A; | |
561 | u32 saveTRANS_VSYNC_A; | |
0da3ea12 | 562 | u32 savePIPEASTAT; |
ba8bbcf6 JB |
563 | u32 saveDSPASTRIDE; |
564 | u32 saveDSPASIZE; | |
565 | u32 saveDSPAPOS; | |
585fb111 | 566 | u32 saveDSPAADDR; |
ba8bbcf6 JB |
567 | u32 saveDSPASURF; |
568 | u32 saveDSPATILEOFF; | |
569 | u32 savePFIT_PGM_RATIOS; | |
0eb96d6e | 570 | u32 saveBLC_HIST_CTL; |
ba8bbcf6 JB |
571 | u32 saveBLC_PWM_CTL; |
572 | u32 saveBLC_PWM_CTL2; | |
42048781 ZW |
573 | u32 saveBLC_CPU_PWM_CTL; |
574 | u32 saveBLC_CPU_PWM_CTL2; | |
ba8bbcf6 JB |
575 | u32 saveFPB0; |
576 | u32 saveFPB1; | |
577 | u32 saveDPLL_B; | |
578 | u32 saveDPLL_B_MD; | |
579 | u32 saveHTOTAL_B; | |
580 | u32 saveHBLANK_B; | |
581 | u32 saveHSYNC_B; | |
582 | u32 saveVTOTAL_B; | |
583 | u32 saveVBLANK_B; | |
584 | u32 saveVSYNC_B; | |
585 | u32 saveBCLRPAT_B; | |
5586c8bc | 586 | u32 saveTRANSBCONF; |
42048781 ZW |
587 | u32 saveTRANS_HTOTAL_B; |
588 | u32 saveTRANS_HBLANK_B; | |
589 | u32 saveTRANS_HSYNC_B; | |
590 | u32 saveTRANS_VTOTAL_B; | |
591 | u32 saveTRANS_VBLANK_B; | |
592 | u32 saveTRANS_VSYNC_B; | |
0da3ea12 | 593 | u32 savePIPEBSTAT; |
ba8bbcf6 JB |
594 | u32 saveDSPBSTRIDE; |
595 | u32 saveDSPBSIZE; | |
596 | u32 saveDSPBPOS; | |
585fb111 | 597 | u32 saveDSPBADDR; |
ba8bbcf6 JB |
598 | u32 saveDSPBSURF; |
599 | u32 saveDSPBTILEOFF; | |
585fb111 JB |
600 | u32 saveVGA0; |
601 | u32 saveVGA1; | |
602 | u32 saveVGA_PD; | |
ba8bbcf6 JB |
603 | u32 saveVGACNTRL; |
604 | u32 saveADPA; | |
605 | u32 saveLVDS; | |
585fb111 JB |
606 | u32 savePP_ON_DELAYS; |
607 | u32 savePP_OFF_DELAYS; | |
ba8bbcf6 JB |
608 | u32 saveDVOA; |
609 | u32 saveDVOB; | |
610 | u32 saveDVOC; | |
611 | u32 savePP_ON; | |
612 | u32 savePP_OFF; | |
613 | u32 savePP_CONTROL; | |
585fb111 | 614 | u32 savePP_DIVISOR; |
ba8bbcf6 JB |
615 | u32 savePFIT_CONTROL; |
616 | u32 save_palette_a[256]; | |
617 | u32 save_palette_b[256]; | |
06027f91 | 618 | u32 saveDPFC_CB_BASE; |
ba8bbcf6 JB |
619 | u32 saveFBC_CFB_BASE; |
620 | u32 saveFBC_LL_BASE; | |
621 | u32 saveFBC_CONTROL; | |
622 | u32 saveFBC_CONTROL2; | |
0da3ea12 JB |
623 | u32 saveIER; |
624 | u32 saveIIR; | |
625 | u32 saveIMR; | |
42048781 ZW |
626 | u32 saveDEIER; |
627 | u32 saveDEIMR; | |
628 | u32 saveGTIER; | |
629 | u32 saveGTIMR; | |
630 | u32 saveFDI_RXA_IMR; | |
631 | u32 saveFDI_RXB_IMR; | |
1f84e550 | 632 | u32 saveCACHE_MODE_0; |
1f84e550 | 633 | u32 saveMI_ARB_STATE; |
ba8bbcf6 JB |
634 | u32 saveSWF0[16]; |
635 | u32 saveSWF1[16]; | |
636 | u32 saveSWF2[3]; | |
637 | u8 saveMSR; | |
638 | u8 saveSR[8]; | |
123f794f | 639 | u8 saveGR[25]; |
ba8bbcf6 | 640 | u8 saveAR_INDEX; |
a59e122a | 641 | u8 saveAR[21]; |
ba8bbcf6 | 642 | u8 saveDACMASK; |
a59e122a | 643 | u8 saveCR[37]; |
4b9de737 | 644 | uint64_t saveFENCE[I915_MAX_NUM_FENCES]; |
1fd1c624 EA |
645 | u32 saveCURACNTR; |
646 | u32 saveCURAPOS; | |
647 | u32 saveCURABASE; | |
648 | u32 saveCURBCNTR; | |
649 | u32 saveCURBPOS; | |
650 | u32 saveCURBBASE; | |
651 | u32 saveCURSIZE; | |
a4fc5ed6 KP |
652 | u32 saveDP_B; |
653 | u32 saveDP_C; | |
654 | u32 saveDP_D; | |
655 | u32 savePIPEA_GMCH_DATA_M; | |
656 | u32 savePIPEB_GMCH_DATA_M; | |
657 | u32 savePIPEA_GMCH_DATA_N; | |
658 | u32 savePIPEB_GMCH_DATA_N; | |
659 | u32 savePIPEA_DP_LINK_M; | |
660 | u32 savePIPEB_DP_LINK_M; | |
661 | u32 savePIPEA_DP_LINK_N; | |
662 | u32 savePIPEB_DP_LINK_N; | |
42048781 ZW |
663 | u32 saveFDI_RXA_CTL; |
664 | u32 saveFDI_TXA_CTL; | |
665 | u32 saveFDI_RXB_CTL; | |
666 | u32 saveFDI_TXB_CTL; | |
667 | u32 savePFA_CTL_1; | |
668 | u32 savePFB_CTL_1; | |
669 | u32 savePFA_WIN_SZ; | |
670 | u32 savePFB_WIN_SZ; | |
671 | u32 savePFA_WIN_POS; | |
672 | u32 savePFB_WIN_POS; | |
5586c8bc ZW |
673 | u32 savePCH_DREF_CONTROL; |
674 | u32 saveDISP_ARB_CTL; | |
675 | u32 savePIPEA_DATA_M1; | |
676 | u32 savePIPEA_DATA_N1; | |
677 | u32 savePIPEA_LINK_M1; | |
678 | u32 savePIPEA_LINK_N1; | |
679 | u32 savePIPEB_DATA_M1; | |
680 | u32 savePIPEB_DATA_N1; | |
681 | u32 savePIPEB_LINK_M1; | |
682 | u32 savePIPEB_LINK_N1; | |
b5b72e89 | 683 | u32 saveMCHBAR_RENDER_STANDBY; |
cda2bb78 | 684 | u32 savePCH_PORT_HOTPLUG; |
673a394b EA |
685 | |
686 | struct { | |
19966754 | 687 | /** Bridge to intel-gtt-ko */ |
c64f7ba5 | 688 | const struct intel_gtt *gtt; |
19966754 | 689 | /** Memory allocator for GTT stolen memory */ |
fe669bf8 | 690 | struct drm_mm stolen; |
19966754 | 691 | /** Memory allocator for GTT */ |
673a394b | 692 | struct drm_mm gtt_space; |
93a37f20 DV |
693 | /** List of all objects in gtt_space. Used to restore gtt |
694 | * mappings on resume */ | |
6c085a72 CW |
695 | struct list_head bound_list; |
696 | /** | |
697 | * List of objects which are not bound to the GTT (thus | |
698 | * are idle and not used by the GPU) but still have | |
699 | * (presumably uncached) pages still attached. | |
700 | */ | |
701 | struct list_head unbound_list; | |
bee4a186 CW |
702 | |
703 | /** Usable portion of the GTT for GEM */ | |
704 | unsigned long gtt_start; | |
a6e0aa42 | 705 | unsigned long gtt_mappable_end; |
bee4a186 | 706 | unsigned long gtt_end; |
673a394b | 707 | |
0839ccb8 | 708 | struct io_mapping *gtt_mapping; |
dd2757f8 | 709 | phys_addr_t gtt_base_addr; |
ab657db1 | 710 | int gtt_mtrr; |
0839ccb8 | 711 | |
1d2a314c DV |
712 | /** PPGTT used for aliasing the PPGTT with the GTT */ |
713 | struct i915_hw_ppgtt *aliasing_ppgtt; | |
714 | ||
b9524a1e BW |
715 | u32 *l3_remap_info; |
716 | ||
17250b71 | 717 | struct shrinker inactive_shrinker; |
31169714 | 718 | |
69dc4987 CW |
719 | /** |
720 | * List of objects currently involved in rendering. | |
721 | * | |
722 | * Includes buffers having the contents of their GPU caches | |
723 | * flushed, not necessarily primitives. last_rendering_seqno | |
724 | * represents when the rendering involved will be completed. | |
725 | * | |
726 | * A reference is held on the buffer while on this list. | |
727 | */ | |
728 | struct list_head active_list; | |
729 | ||
673a394b EA |
730 | /** |
731 | * LRU list of objects which are not in the ringbuffer and | |
732 | * are ready to unbind, but are still in the GTT. | |
733 | * | |
ce44b0ea EA |
734 | * last_rendering_seqno is 0 while an object is in this list. |
735 | * | |
673a394b EA |
736 | * A reference is not held on the buffer while on this list, |
737 | * as merely being GTT-bound shouldn't prevent its being | |
738 | * freed, and we'll pull it off the list in the free path. | |
739 | */ | |
740 | struct list_head inactive_list; | |
741 | ||
a09ba7fa EA |
742 | /** LRU list of objects with fence regs on them. */ |
743 | struct list_head fence_list; | |
744 | ||
673a394b EA |
745 | /** |
746 | * We leave the user IRQ off as much as possible, | |
747 | * but this means that requests will finish and never | |
748 | * be retired once the system goes idle. Set a timer to | |
749 | * fire periodically while the ring is running. When it | |
750 | * fires, go retire requests. | |
751 | */ | |
752 | struct delayed_work retire_work; | |
753 | ||
ce453d81 CW |
754 | /** |
755 | * Are we in a non-interruptible section of code like | |
756 | * modesetting? | |
757 | */ | |
758 | bool interruptible; | |
759 | ||
673a394b EA |
760 | /** |
761 | * Flag if the X Server, and thus DRM, is not currently in | |
762 | * control of the device. | |
763 | * | |
764 | * This is set between LeaveVT and EnterVT. It needs to be | |
765 | * replaced with a semaphore. It also needs to be | |
766 | * transitioned away from for kernel modesetting. | |
767 | */ | |
768 | int suspended; | |
769 | ||
770 | /** | |
771 | * Flag if the hardware appears to be wedged. | |
772 | * | |
773 | * This is set when attempts to idle the device timeout. | |
25985edc | 774 | * It prevents command submission from occurring and makes |
673a394b EA |
775 | * every pending request fail |
776 | */ | |
ba1234d1 | 777 | atomic_t wedged; |
673a394b EA |
778 | |
779 | /** Bit 6 swizzling required for X tiling */ | |
780 | uint32_t bit_6_swizzle_x; | |
781 | /** Bit 6 swizzling required for Y tiling */ | |
782 | uint32_t bit_6_swizzle_y; | |
71acb5eb DA |
783 | |
784 | /* storage for physical objects */ | |
785 | struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT]; | |
9220434a | 786 | |
73aa808f | 787 | /* accounting, useful for userland debugging */ |
73aa808f | 788 | size_t gtt_total; |
6299f992 CW |
789 | size_t mappable_gtt_total; |
790 | size_t object_memory; | |
73aa808f | 791 | u32 object_count; |
673a394b | 792 | } mm; |
8781342d DV |
793 | |
794 | /* Old dri1 support infrastructure, beware the dragons ya fools entering | |
795 | * here! */ | |
796 | struct { | |
797 | unsigned allow_batchbuffer : 1; | |
316d3884 | 798 | u32 __iomem *gfx_hws_cpu_addr; |
5d985ac8 DV |
799 | |
800 | unsigned int cpp; | |
801 | int back_offset; | |
802 | int front_offset; | |
803 | int current_page; | |
804 | int page_flipping; | |
8781342d DV |
805 | } dri1; |
806 | ||
807 | /* Kernel Modesetting */ | |
808 | ||
9b9d172d | 809 | struct sdvo_device_mapping sdvo_mappings[2]; |
a3e17eb8 ZY |
810 | /* indicate whether the LVDS_BORDER should be enabled or not */ |
811 | unsigned int lvds_border_bits; | |
1d8e1c75 CW |
812 | /* Panel fitter placement and size for Ironlake+ */ |
813 | u32 pch_pf_pos, pch_pf_size; | |
652c393a | 814 | |
27f8227b JB |
815 | struct drm_crtc *plane_to_crtc_mapping[3]; |
816 | struct drm_crtc *pipe_to_crtc_mapping[3]; | |
6b95a207 KH |
817 | wait_queue_head_t pending_flip_queue; |
818 | ||
ee7b9f93 | 819 | struct intel_pch_pll pch_plls[I915_NUM_PLLS]; |
6441ab5f | 820 | struct intel_ddi_plls ddi_plls; |
ee7b9f93 | 821 | |
652c393a JB |
822 | /* Reclocking support */ |
823 | bool render_reclock_avail; | |
824 | bool lvds_downclock_avail; | |
18f9ed12 ZY |
825 | /* indicates the reduced downclock for LVDS*/ |
826 | int lvds_downclock; | |
652c393a | 827 | u16 orig_clock; |
6363ee6f ZY |
828 | int child_dev_num; |
829 | struct child_device_config *child_dev; | |
f97108d1 | 830 | |
c4804411 | 831 | bool mchbar_need_disable; |
f97108d1 | 832 | |
c6a828d3 DV |
833 | /* gen6+ rps state */ |
834 | struct { | |
835 | struct work_struct work; | |
836 | u32 pm_iir; | |
837 | /* lock - irqsave spinlock that protectects the work_struct and | |
838 | * pm_iir. */ | |
839 | spinlock_t lock; | |
840 | ||
841 | /* The below variables an all the rps hw state are protected by | |
842 | * dev->struct mutext. */ | |
843 | u8 cur_delay; | |
844 | u8 min_delay; | |
845 | u8 max_delay; | |
846 | } rps; | |
847 | ||
20e4d407 DV |
848 | /* ilk-only ips/rps state. Everything in here is protected by the global |
849 | * mchdev_lock in intel_pm.c */ | |
850 | struct { | |
851 | u8 cur_delay; | |
852 | u8 min_delay; | |
853 | u8 max_delay; | |
854 | u8 fmax; | |
855 | u8 fstart; | |
856 | ||
857 | u64 last_count1; | |
858 | unsigned long last_time1; | |
859 | unsigned long chipset_power; | |
860 | u64 last_count2; | |
861 | struct timespec last_time2; | |
862 | unsigned long gfx_power; | |
863 | u8 corr; | |
864 | ||
865 | int c_m; | |
866 | int r_t; | |
867 | } ips; | |
b5e50c3f JB |
868 | |
869 | enum no_fbc_reason no_fbc_reason; | |
38651674 | 870 | |
20bf377e JB |
871 | struct drm_mm_node *compressed_fb; |
872 | struct drm_mm_node *compressed_llb; | |
34dc4d44 | 873 | |
ae681d96 CW |
874 | unsigned long last_gpu_reset; |
875 | ||
8be48d92 DA |
876 | /* list of fbdev register on this device */ |
877 | struct intel_fbdev *fbdev; | |
e953fd7b | 878 | |
aaa6fd2a MG |
879 | struct backlight_device *backlight; |
880 | ||
e953fd7b | 881 | struct drm_property *broadcast_rgb_property; |
3f43c48d | 882 | struct drm_property *force_audio_property; |
e3689190 BW |
883 | |
884 | struct work_struct parity_error_work; | |
254f965c BW |
885 | bool hw_contexts_disabled; |
886 | uint32_t hw_context_size; | |
1da177e4 LT |
887 | } drm_i915_private_t; |
888 | ||
b4519513 CW |
889 | /* Iterate over initialised rings */ |
890 | #define for_each_ring(ring__, dev_priv__, i__) \ | |
891 | for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \ | |
892 | if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__))) | |
893 | ||
b1d7e4b4 WF |
894 | enum hdmi_force_audio { |
895 | HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */ | |
896 | HDMI_AUDIO_OFF, /* force turn off HDMI audio */ | |
897 | HDMI_AUDIO_AUTO, /* trust EDID */ | |
898 | HDMI_AUDIO_ON, /* force turn on HDMI audio */ | |
899 | }; | |
900 | ||
93dfb40c | 901 | enum i915_cache_level { |
e6994aee | 902 | I915_CACHE_NONE = 0, |
93dfb40c | 903 | I915_CACHE_LLC, |
e6994aee | 904 | I915_CACHE_LLC_MLC, /* gen6+, in docs at least! */ |
93dfb40c CW |
905 | }; |
906 | ||
37e680a1 CW |
907 | struct drm_i915_gem_object_ops { |
908 | /* Interface between the GEM object and its backing storage. | |
909 | * get_pages() is called once prior to the use of the associated set | |
910 | * of pages before to binding them into the GTT, and put_pages() is | |
911 | * called after we no longer need them. As we expect there to be | |
912 | * associated cost with migrating pages between the backing storage | |
913 | * and making them available for the GPU (e.g. clflush), we may hold | |
914 | * onto the pages after they are no longer referenced by the GPU | |
915 | * in case they may be used again shortly (for example migrating the | |
916 | * pages to a different memory domain within the GTT). put_pages() | |
917 | * will therefore most likely be called when the object itself is | |
918 | * being released or under memory pressure (where we attempt to | |
919 | * reap pages for the shrinker). | |
920 | */ | |
921 | int (*get_pages)(struct drm_i915_gem_object *); | |
922 | void (*put_pages)(struct drm_i915_gem_object *); | |
923 | }; | |
924 | ||
673a394b | 925 | struct drm_i915_gem_object { |
c397b908 | 926 | struct drm_gem_object base; |
673a394b | 927 | |
37e680a1 CW |
928 | const struct drm_i915_gem_object_ops *ops; |
929 | ||
673a394b EA |
930 | /** Current space allocated to this object in the GTT, if any. */ |
931 | struct drm_mm_node *gtt_space; | |
93a37f20 | 932 | struct list_head gtt_list; |
673a394b | 933 | |
65ce3027 | 934 | /** This object's place on the active/inactive lists */ |
69dc4987 CW |
935 | struct list_head ring_list; |
936 | struct list_head mm_list; | |
432e58ed CW |
937 | /** This object's place in the batchbuffer or on the eviction list */ |
938 | struct list_head exec_list; | |
673a394b EA |
939 | |
940 | /** | |
65ce3027 CW |
941 | * This is set if the object is on the active lists (has pending |
942 | * rendering and so a non-zero seqno), and is not set if it i s on | |
943 | * inactive (ready to be unbound) list. | |
673a394b | 944 | */ |
0206e353 | 945 | unsigned int active:1; |
673a394b EA |
946 | |
947 | /** | |
948 | * This is set if the object has been written to since last bound | |
949 | * to the GTT | |
950 | */ | |
0206e353 | 951 | unsigned int dirty:1; |
778c3544 DV |
952 | |
953 | /** | |
954 | * Fence register bits (if any) for this object. Will be set | |
955 | * as needed when mapped into the GTT. | |
956 | * Protected by dev->struct_mutex. | |
778c3544 | 957 | */ |
4b9de737 | 958 | signed int fence_reg:I915_MAX_NUM_FENCE_BITS; |
778c3544 | 959 | |
778c3544 DV |
960 | /** |
961 | * Advice: are the backing pages purgeable? | |
962 | */ | |
0206e353 | 963 | unsigned int madv:2; |
778c3544 | 964 | |
778c3544 DV |
965 | /** |
966 | * Current tiling mode for the object. | |
967 | */ | |
0206e353 | 968 | unsigned int tiling_mode:2; |
5d82e3e6 CW |
969 | /** |
970 | * Whether the tiling parameters for the currently associated fence | |
971 | * register have changed. Note that for the purposes of tracking | |
972 | * tiling changes we also treat the unfenced register, the register | |
973 | * slot that the object occupies whilst it executes a fenced | |
974 | * command (such as BLT on gen2/3), as a "fence". | |
975 | */ | |
976 | unsigned int fence_dirty:1; | |
778c3544 DV |
977 | |
978 | /** How many users have pinned this object in GTT space. The following | |
979 | * users can each hold at most one reference: pwrite/pread, pin_ioctl | |
980 | * (via user_pin_count), execbuffer (objects are not allowed multiple | |
981 | * times for the same batchbuffer), and the framebuffer code. When | |
982 | * switching/pageflipping, the framebuffer code has at most two buffers | |
983 | * pinned per crtc. | |
984 | * | |
985 | * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3 | |
986 | * bits with absolutely no headroom. So use 4 bits. */ | |
0206e353 | 987 | unsigned int pin_count:4; |
778c3544 | 988 | #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf |
673a394b | 989 | |
75e9e915 DV |
990 | /** |
991 | * Is the object at the current location in the gtt mappable and | |
992 | * fenceable? Used to avoid costly recalculations. | |
993 | */ | |
0206e353 | 994 | unsigned int map_and_fenceable:1; |
75e9e915 | 995 | |
fb7d516a DV |
996 | /** |
997 | * Whether the current gtt mapping needs to be mappable (and isn't just | |
998 | * mappable by accident). Track pin and fault separate for a more | |
999 | * accurate mappable working set. | |
1000 | */ | |
0206e353 AJ |
1001 | unsigned int fault_mappable:1; |
1002 | unsigned int pin_mappable:1; | |
fb7d516a | 1003 | |
caea7476 CW |
1004 | /* |
1005 | * Is the GPU currently using a fence to access this buffer, | |
1006 | */ | |
1007 | unsigned int pending_fenced_gpu_access:1; | |
1008 | unsigned int fenced_gpu_access:1; | |
1009 | ||
93dfb40c CW |
1010 | unsigned int cache_level:2; |
1011 | ||
7bddb01f | 1012 | unsigned int has_aliasing_ppgtt_mapping:1; |
74898d7e | 1013 | unsigned int has_global_gtt_mapping:1; |
9da3da66 | 1014 | unsigned int has_dma_mapping:1; |
7bddb01f | 1015 | |
9da3da66 | 1016 | struct sg_table *pages; |
a5570178 | 1017 | int pages_pin_count; |
673a394b | 1018 | |
1286ff73 | 1019 | /* prime dma-buf support */ |
9a70cc2a DA |
1020 | void *dma_buf_vmapping; |
1021 | int vmapping_count; | |
1022 | ||
67731b87 CW |
1023 | /** |
1024 | * Used for performing relocations during execbuffer insertion. | |
1025 | */ | |
1026 | struct hlist_node exec_node; | |
1027 | unsigned long exec_handle; | |
6fe4f140 | 1028 | struct drm_i915_gem_exec_object2 *exec_entry; |
67731b87 | 1029 | |
673a394b EA |
1030 | /** |
1031 | * Current offset of the object in GTT space. | |
1032 | * | |
1033 | * This is the same as gtt_space->start | |
1034 | */ | |
1035 | uint32_t gtt_offset; | |
e67b8ce1 | 1036 | |
caea7476 CW |
1037 | struct intel_ring_buffer *ring; |
1038 | ||
1c293ea3 | 1039 | /** Breadcrumb of last rendering to the buffer. */ |
0201f1ec CW |
1040 | uint32_t last_read_seqno; |
1041 | uint32_t last_write_seqno; | |
caea7476 CW |
1042 | /** Breadcrumb of last fenced GPU access to the buffer. */ |
1043 | uint32_t last_fenced_seqno; | |
673a394b | 1044 | |
778c3544 | 1045 | /** Current tiling stride for the object, if it's tiled. */ |
de151cf6 | 1046 | uint32_t stride; |
673a394b | 1047 | |
280b713b | 1048 | /** Record of address bit 17 of each page at last unbind. */ |
d312ec25 | 1049 | unsigned long *bit_17; |
280b713b | 1050 | |
79e53945 JB |
1051 | /** User space pin count and filp owning the pin */ |
1052 | uint32_t user_pin_count; | |
1053 | struct drm_file *pin_filp; | |
71acb5eb DA |
1054 | |
1055 | /** for phy allocated objects */ | |
1056 | struct drm_i915_gem_phys_object *phys_obj; | |
b70d11da | 1057 | |
6b95a207 KH |
1058 | /** |
1059 | * Number of crtcs where this object is currently the fb, but | |
1060 | * will be page flipped away on the next vblank. When it | |
1061 | * reaches 0, dev_priv->pending_flip_queue will be woken up. | |
1062 | */ | |
1063 | atomic_t pending_flip; | |
673a394b EA |
1064 | }; |
1065 | ||
62b8b215 | 1066 | #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base) |
23010e43 | 1067 | |
673a394b EA |
1068 | /** |
1069 | * Request queue structure. | |
1070 | * | |
1071 | * The request queue allows us to note sequence numbers that have been emitted | |
1072 | * and may be associated with active buffers to be retired. | |
1073 | * | |
1074 | * By keeping this list, we can avoid having to do questionable | |
1075 | * sequence-number comparisons on buffer last_rendering_seqnos, and associate | |
1076 | * an emission time with seqnos for tracking how far ahead of the GPU we are. | |
1077 | */ | |
1078 | struct drm_i915_gem_request { | |
852835f3 ZN |
1079 | /** On Which ring this request was generated */ |
1080 | struct intel_ring_buffer *ring; | |
1081 | ||
673a394b EA |
1082 | /** GEM sequence number associated with this request. */ |
1083 | uint32_t seqno; | |
1084 | ||
a71d8d94 CW |
1085 | /** Postion in the ringbuffer of the end of the request */ |
1086 | u32 tail; | |
1087 | ||
673a394b EA |
1088 | /** Time at which this request was emitted, in jiffies. */ |
1089 | unsigned long emitted_jiffies; | |
1090 | ||
b962442e | 1091 | /** global list entry for this request */ |
673a394b | 1092 | struct list_head list; |
b962442e | 1093 | |
f787a5f5 | 1094 | struct drm_i915_file_private *file_priv; |
b962442e EA |
1095 | /** file_priv list entry for this request */ |
1096 | struct list_head client_list; | |
673a394b EA |
1097 | }; |
1098 | ||
1099 | struct drm_i915_file_private { | |
1100 | struct { | |
1c25595f | 1101 | struct spinlock lock; |
b962442e | 1102 | struct list_head request_list; |
673a394b | 1103 | } mm; |
40521054 | 1104 | struct idr context_idr; |
673a394b EA |
1105 | }; |
1106 | ||
cae5852d ZN |
1107 | #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info) |
1108 | ||
1109 | #define IS_I830(dev) ((dev)->pci_device == 0x3577) | |
1110 | #define IS_845G(dev) ((dev)->pci_device == 0x2562) | |
1111 | #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x) | |
1112 | #define IS_I865G(dev) ((dev)->pci_device == 0x2572) | |
1113 | #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g) | |
1114 | #define IS_I915GM(dev) ((dev)->pci_device == 0x2592) | |
1115 | #define IS_I945G(dev) ((dev)->pci_device == 0x2772) | |
1116 | #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm) | |
1117 | #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater) | |
1118 | #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline) | |
1119 | #define IS_GM45(dev) ((dev)->pci_device == 0x2A42) | |
1120 | #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x) | |
1121 | #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001) | |
1122 | #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011) | |
1123 | #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview) | |
1124 | #define IS_G33(dev) (INTEL_INFO(dev)->is_g33) | |
1125 | #define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042) | |
1126 | #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046) | |
4b65177b | 1127 | #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge) |
70a3eb7a | 1128 | #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview) |
4cae9ae0 | 1129 | #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell) |
cae5852d ZN |
1130 | #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) |
1131 | ||
85436696 JB |
1132 | /* |
1133 | * The genX designation typically refers to the render engine, so render | |
1134 | * capability related checks should use IS_GEN, while display and other checks | |
1135 | * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular | |
1136 | * chips, etc.). | |
1137 | */ | |
cae5852d ZN |
1138 | #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2) |
1139 | #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3) | |
1140 | #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4) | |
1141 | #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5) | |
1142 | #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6) | |
85436696 | 1143 | #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7) |
cae5852d ZN |
1144 | |
1145 | #define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring) | |
1146 | #define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring) | |
3d29b842 | 1147 | #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc) |
cae5852d ZN |
1148 | #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws) |
1149 | ||
254f965c | 1150 | #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6) |
93553609 | 1151 | #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >=6 && !IS_VALLEYVIEW(dev)) |
1d2a314c | 1152 | |
05394f39 | 1153 | #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay) |
cae5852d ZN |
1154 | #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical) |
1155 | ||
1156 | /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte | |
1157 | * rows, which changed the alignment requirements and fence programming. | |
1158 | */ | |
1159 | #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \ | |
1160 | IS_I915GM(dev))) | |
1161 | #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) | |
1162 | #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev)) | |
1163 | #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev)) | |
1164 | #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev)) | |
1165 | #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv) | |
1166 | #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug) | |
1167 | /* dsparb controlled by hw only */ | |
1168 | #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev)) | |
1169 | ||
1170 | #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2) | |
1171 | #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr) | |
1172 | #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc) | |
cae5852d | 1173 | |
eceae481 | 1174 | #define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5) |
cae5852d ZN |
1175 | |
1176 | #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type) | |
eb877ebf | 1177 | #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT) |
cae5852d ZN |
1178 | #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT) |
1179 | #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX) | |
45e6e3a1 | 1180 | #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE) |
cae5852d | 1181 | |
b7884eb4 DV |
1182 | #define HAS_FORCE_WAKE(dev) (INTEL_INFO(dev)->has_force_wake) |
1183 | ||
f27b9265 | 1184 | #define HAS_L3_GPU_CACHE(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) |
e1ef7cc2 | 1185 | |
c8735b0c BW |
1186 | #define GT_FREQUENCY_MULTIPLIER 50 |
1187 | ||
05394f39 CW |
1188 | #include "i915_trace.h" |
1189 | ||
83b7f9ac ED |
1190 | /** |
1191 | * RC6 is a special power stage which allows the GPU to enter an very | |
1192 | * low-voltage mode when idle, using down to 0V while at this stage. This | |
1193 | * stage is entered automatically when the GPU is idle when RC6 support is | |
1194 | * enabled, and as soon as new workload arises GPU wakes up automatically as well. | |
1195 | * | |
1196 | * There are different RC6 modes available in Intel GPU, which differentiate | |
1197 | * among each other with the latency required to enter and leave RC6 and | |
1198 | * voltage consumed by the GPU in different states. | |
1199 | * | |
1200 | * The combination of the following flags define which states GPU is allowed | |
1201 | * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and | |
1202 | * RC6pp is deepest RC6. Their support by hardware varies according to the | |
1203 | * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one | |
1204 | * which brings the most power savings; deeper states save more power, but | |
1205 | * require higher latency to switch to and wake up. | |
1206 | */ | |
1207 | #define INTEL_RC6_ENABLE (1<<0) | |
1208 | #define INTEL_RC6p_ENABLE (1<<1) | |
1209 | #define INTEL_RC6pp_ENABLE (1<<2) | |
1210 | ||
c153f45f | 1211 | extern struct drm_ioctl_desc i915_ioctls[]; |
b3a83639 | 1212 | extern int i915_max_ioctl; |
a35d9d3c BW |
1213 | extern unsigned int i915_fbpercrtc __always_unused; |
1214 | extern int i915_panel_ignore_lid __read_mostly; | |
1215 | extern unsigned int i915_powersave __read_mostly; | |
f45b5557 | 1216 | extern int i915_semaphores __read_mostly; |
a35d9d3c | 1217 | extern unsigned int i915_lvds_downclock __read_mostly; |
121d527a | 1218 | extern int i915_lvds_channel_mode __read_mostly; |
4415e63b | 1219 | extern int i915_panel_use_ssc __read_mostly; |
a35d9d3c | 1220 | extern int i915_vbt_sdvo_panel_type __read_mostly; |
c0f372b3 | 1221 | extern int i915_enable_rc6 __read_mostly; |
4415e63b | 1222 | extern int i915_enable_fbc __read_mostly; |
a35d9d3c | 1223 | extern bool i915_enable_hangcheck __read_mostly; |
650dc07e | 1224 | extern int i915_enable_ppgtt __read_mostly; |
b3a83639 | 1225 | |
6a9ee8af DA |
1226 | extern int i915_suspend(struct drm_device *dev, pm_message_t state); |
1227 | extern int i915_resume(struct drm_device *dev); | |
7c1c2871 DA |
1228 | extern int i915_master_create(struct drm_device *dev, struct drm_master *master); |
1229 | extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master); | |
1230 | ||
1da177e4 | 1231 | /* i915_dma.c */ |
d05c617e | 1232 | void i915_update_dri1_breadcrumb(struct drm_device *dev); |
84b1fd10 | 1233 | extern void i915_kernel_lost_context(struct drm_device * dev); |
22eae947 | 1234 | extern int i915_driver_load(struct drm_device *, unsigned long flags); |
ba8bbcf6 | 1235 | extern int i915_driver_unload(struct drm_device *); |
673a394b | 1236 | extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv); |
84b1fd10 | 1237 | extern void i915_driver_lastclose(struct drm_device * dev); |
6c340eac EA |
1238 | extern void i915_driver_preclose(struct drm_device *dev, |
1239 | struct drm_file *file_priv); | |
673a394b EA |
1240 | extern void i915_driver_postclose(struct drm_device *dev, |
1241 | struct drm_file *file_priv); | |
84b1fd10 | 1242 | extern int i915_driver_device_is_agp(struct drm_device * dev); |
c43b5634 | 1243 | #ifdef CONFIG_COMPAT |
0d6aa60b DA |
1244 | extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, |
1245 | unsigned long arg); | |
c43b5634 | 1246 | #endif |
673a394b | 1247 | extern int i915_emit_box(struct drm_device *dev, |
c4e7a414 CW |
1248 | struct drm_clip_rect *box, |
1249 | int DR1, int DR4); | |
8e96d9c4 | 1250 | extern int intel_gpu_reset(struct drm_device *dev); |
d4b8bb2a | 1251 | extern int i915_reset(struct drm_device *dev); |
7648fa99 JB |
1252 | extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv); |
1253 | extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv); | |
1254 | extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv); | |
1255 | extern void i915_update_gfx_val(struct drm_i915_private *dev_priv); | |
1256 | ||
af6061af | 1257 | |
1da177e4 | 1258 | /* i915_irq.c */ |
f65d9421 | 1259 | void i915_hangcheck_elapsed(unsigned long data); |
527f9e90 | 1260 | void i915_handle_error(struct drm_device *dev, bool wedged); |
1da177e4 | 1261 | |
f71d4af4 | 1262 | extern void intel_irq_init(struct drm_device *dev); |
990bbdad | 1263 | extern void intel_gt_init(struct drm_device *dev); |
16995a9f | 1264 | extern void intel_gt_reset(struct drm_device *dev); |
b1f14ad0 | 1265 | |
742cbee8 DV |
1266 | void i915_error_state_free(struct kref *error_ref); |
1267 | ||
7c463586 KP |
1268 | void |
1269 | i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); | |
1270 | ||
1271 | void | |
1272 | i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); | |
1273 | ||
0206e353 | 1274 | void intel_enable_asle(struct drm_device *dev); |
01c66889 | 1275 | |
3bd3c932 CW |
1276 | #ifdef CONFIG_DEBUG_FS |
1277 | extern void i915_destroy_error_state(struct drm_device *dev); | |
1278 | #else | |
1279 | #define i915_destroy_error_state(x) | |
1280 | #endif | |
1281 | ||
7c463586 | 1282 | |
673a394b EA |
1283 | /* i915_gem.c */ |
1284 | int i915_gem_init_ioctl(struct drm_device *dev, void *data, | |
1285 | struct drm_file *file_priv); | |
1286 | int i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
1287 | struct drm_file *file_priv); | |
1288 | int i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
1289 | struct drm_file *file_priv); | |
1290 | int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
1291 | struct drm_file *file_priv); | |
1292 | int i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
1293 | struct drm_file *file_priv); | |
de151cf6 JB |
1294 | int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, |
1295 | struct drm_file *file_priv); | |
673a394b EA |
1296 | int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, |
1297 | struct drm_file *file_priv); | |
1298 | int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
1299 | struct drm_file *file_priv); | |
1300 | int i915_gem_execbuffer(struct drm_device *dev, void *data, | |
1301 | struct drm_file *file_priv); | |
76446cac JB |
1302 | int i915_gem_execbuffer2(struct drm_device *dev, void *data, |
1303 | struct drm_file *file_priv); | |
673a394b EA |
1304 | int i915_gem_pin_ioctl(struct drm_device *dev, void *data, |
1305 | struct drm_file *file_priv); | |
1306 | int i915_gem_unpin_ioctl(struct drm_device *dev, void *data, | |
1307 | struct drm_file *file_priv); | |
1308 | int i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
1309 | struct drm_file *file_priv); | |
199adf40 BW |
1310 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, |
1311 | struct drm_file *file); | |
1312 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, | |
1313 | struct drm_file *file); | |
673a394b EA |
1314 | int i915_gem_throttle_ioctl(struct drm_device *dev, void *data, |
1315 | struct drm_file *file_priv); | |
3ef94daa CW |
1316 | int i915_gem_madvise_ioctl(struct drm_device *dev, void *data, |
1317 | struct drm_file *file_priv); | |
673a394b EA |
1318 | int i915_gem_entervt_ioctl(struct drm_device *dev, void *data, |
1319 | struct drm_file *file_priv); | |
1320 | int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, | |
1321 | struct drm_file *file_priv); | |
1322 | int i915_gem_set_tiling(struct drm_device *dev, void *data, | |
1323 | struct drm_file *file_priv); | |
1324 | int i915_gem_get_tiling(struct drm_device *dev, void *data, | |
1325 | struct drm_file *file_priv); | |
5a125c3c EA |
1326 | int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, |
1327 | struct drm_file *file_priv); | |
23ba4fd0 BW |
1328 | int i915_gem_wait_ioctl(struct drm_device *dev, void *data, |
1329 | struct drm_file *file_priv); | |
673a394b | 1330 | void i915_gem_load(struct drm_device *dev); |
673a394b | 1331 | int i915_gem_init_object(struct drm_gem_object *obj); |
37e680a1 CW |
1332 | void i915_gem_object_init(struct drm_i915_gem_object *obj, |
1333 | const struct drm_i915_gem_object_ops *ops); | |
05394f39 CW |
1334 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
1335 | size_t size); | |
673a394b | 1336 | void i915_gem_free_object(struct drm_gem_object *obj); |
2021746e CW |
1337 | int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj, |
1338 | uint32_t alignment, | |
86a1ee26 CW |
1339 | bool map_and_fenceable, |
1340 | bool nonblocking); | |
05394f39 | 1341 | void i915_gem_object_unpin(struct drm_i915_gem_object *obj); |
2021746e | 1342 | int __must_check i915_gem_object_unbind(struct drm_i915_gem_object *obj); |
05394f39 | 1343 | void i915_gem_release_mmap(struct drm_i915_gem_object *obj); |
673a394b | 1344 | void i915_gem_lastclose(struct drm_device *dev); |
f787a5f5 | 1345 | |
37e680a1 | 1346 | int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj); |
9da3da66 CW |
1347 | static inline struct page *i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n) |
1348 | { | |
1349 | struct scatterlist *sg = obj->pages->sgl; | |
1cf83789 CW |
1350 | int nents = obj->pages->nents; |
1351 | while (nents > SG_MAX_SINGLE_ALLOC) { | |
1352 | if (n < SG_MAX_SINGLE_ALLOC - 1) | |
1353 | break; | |
1354 | ||
9da3da66 CW |
1355 | sg = sg_chain_ptr(sg + SG_MAX_SINGLE_ALLOC - 1); |
1356 | n -= SG_MAX_SINGLE_ALLOC - 1; | |
1cf83789 | 1357 | nents -= SG_MAX_SINGLE_ALLOC - 1; |
9da3da66 CW |
1358 | } |
1359 | return sg_page(sg+n); | |
1360 | } | |
a5570178 CW |
1361 | static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj) |
1362 | { | |
1363 | BUG_ON(obj->pages == NULL); | |
1364 | obj->pages_pin_count++; | |
1365 | } | |
1366 | static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj) | |
1367 | { | |
1368 | BUG_ON(obj->pages_pin_count == 0); | |
1369 | obj->pages_pin_count--; | |
1370 | } | |
1371 | ||
54cf91dc | 1372 | int __must_check i915_mutex_lock_interruptible(struct drm_device *dev); |
2911a35b BW |
1373 | int i915_gem_object_sync(struct drm_i915_gem_object *obj, |
1374 | struct intel_ring_buffer *to); | |
54cf91dc | 1375 | void i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, |
1ec14ad3 CW |
1376 | struct intel_ring_buffer *ring, |
1377 | u32 seqno); | |
54cf91dc | 1378 | |
ff72145b DA |
1379 | int i915_gem_dumb_create(struct drm_file *file_priv, |
1380 | struct drm_device *dev, | |
1381 | struct drm_mode_create_dumb *args); | |
1382 | int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev, | |
1383 | uint32_t handle, uint64_t *offset); | |
1384 | int i915_gem_dumb_destroy(struct drm_file *file_priv, struct drm_device *dev, | |
0206e353 | 1385 | uint32_t handle); |
f787a5f5 CW |
1386 | /** |
1387 | * Returns true if seq1 is later than seq2. | |
1388 | */ | |
1389 | static inline bool | |
1390 | i915_seqno_passed(uint32_t seq1, uint32_t seq2) | |
1391 | { | |
1392 | return (int32_t)(seq1 - seq2) >= 0; | |
1393 | } | |
1394 | ||
53d227f2 | 1395 | u32 i915_gem_next_request_seqno(struct intel_ring_buffer *ring); |
54cf91dc | 1396 | |
06d98131 | 1397 | int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj); |
d9e86c0e | 1398 | int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj); |
2021746e | 1399 | |
9a5a53b3 | 1400 | static inline bool |
1690e1eb CW |
1401 | i915_gem_object_pin_fence(struct drm_i915_gem_object *obj) |
1402 | { | |
1403 | if (obj->fence_reg != I915_FENCE_REG_NONE) { | |
1404 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
1405 | dev_priv->fence_regs[obj->fence_reg].pin_count++; | |
9a5a53b3 CW |
1406 | return true; |
1407 | } else | |
1408 | return false; | |
1690e1eb CW |
1409 | } |
1410 | ||
1411 | static inline void | |
1412 | i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj) | |
1413 | { | |
1414 | if (obj->fence_reg != I915_FENCE_REG_NONE) { | |
1415 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
1416 | dev_priv->fence_regs[obj->fence_reg].pin_count--; | |
1417 | } | |
1418 | } | |
1419 | ||
b09a1fec | 1420 | void i915_gem_retire_requests(struct drm_device *dev); |
a71d8d94 | 1421 | void i915_gem_retire_requests_ring(struct intel_ring_buffer *ring); |
d6b2c790 DV |
1422 | int __must_check i915_gem_check_wedge(struct drm_i915_private *dev_priv, |
1423 | bool interruptible); | |
a71d8d94 | 1424 | |
069efc1d | 1425 | void i915_gem_reset(struct drm_device *dev); |
05394f39 | 1426 | void i915_gem_clflush_object(struct drm_i915_gem_object *obj); |
2021746e CW |
1427 | int __must_check i915_gem_object_set_domain(struct drm_i915_gem_object *obj, |
1428 | uint32_t read_domains, | |
1429 | uint32_t write_domain); | |
a8198eea | 1430 | int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj); |
1070a42b | 1431 | int __must_check i915_gem_init(struct drm_device *dev); |
f691e2f4 | 1432 | int __must_check i915_gem_init_hw(struct drm_device *dev); |
b9524a1e | 1433 | void i915_gem_l3_remap(struct drm_device *dev); |
f691e2f4 | 1434 | void i915_gem_init_swizzling(struct drm_device *dev); |
e21af88d | 1435 | void i915_gem_init_ppgtt(struct drm_device *dev); |
79e53945 | 1436 | void i915_gem_cleanup_ringbuffer(struct drm_device *dev); |
b2da9fe5 | 1437 | int __must_check i915_gpu_idle(struct drm_device *dev); |
2021746e | 1438 | int __must_check i915_gem_idle(struct drm_device *dev); |
3bb73aba CW |
1439 | int i915_add_request(struct intel_ring_buffer *ring, |
1440 | struct drm_file *file, | |
acb868d3 | 1441 | u32 *seqno); |
199b2bc2 BW |
1442 | int __must_check i915_wait_seqno(struct intel_ring_buffer *ring, |
1443 | uint32_t seqno); | |
de151cf6 | 1444 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf); |
2021746e CW |
1445 | int __must_check |
1446 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, | |
1447 | bool write); | |
1448 | int __must_check | |
dabdfe02 CW |
1449 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write); |
1450 | int __must_check | |
2da3b9b9 CW |
1451 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
1452 | u32 alignment, | |
2021746e | 1453 | struct intel_ring_buffer *pipelined); |
71acb5eb | 1454 | int i915_gem_attach_phys_object(struct drm_device *dev, |
05394f39 | 1455 | struct drm_i915_gem_object *obj, |
6eeefaf3 CW |
1456 | int id, |
1457 | int align); | |
71acb5eb | 1458 | void i915_gem_detach_phys_object(struct drm_device *dev, |
05394f39 | 1459 | struct drm_i915_gem_object *obj); |
71acb5eb | 1460 | void i915_gem_free_all_phys_object(struct drm_device *dev); |
05394f39 | 1461 | void i915_gem_release(struct drm_device *dev, struct drm_file *file); |
673a394b | 1462 | |
467cffba | 1463 | uint32_t |
e28f8711 CW |
1464 | i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev, |
1465 | uint32_t size, | |
1466 | int tiling_mode); | |
467cffba | 1467 | |
e4ffd173 CW |
1468 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
1469 | enum i915_cache_level cache_level); | |
1470 | ||
1286ff73 DV |
1471 | struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev, |
1472 | struct dma_buf *dma_buf); | |
1473 | ||
1474 | struct dma_buf *i915_gem_prime_export(struct drm_device *dev, | |
1475 | struct drm_gem_object *gem_obj, int flags); | |
1476 | ||
254f965c BW |
1477 | /* i915_gem_context.c */ |
1478 | void i915_gem_context_init(struct drm_device *dev); | |
1479 | void i915_gem_context_fini(struct drm_device *dev); | |
254f965c | 1480 | void i915_gem_context_close(struct drm_device *dev, struct drm_file *file); |
e0556841 BW |
1481 | int i915_switch_context(struct intel_ring_buffer *ring, |
1482 | struct drm_file *file, int to_id); | |
84624813 BW |
1483 | int i915_gem_context_create_ioctl(struct drm_device *dev, void *data, |
1484 | struct drm_file *file); | |
1485 | int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data, | |
1486 | struct drm_file *file); | |
1286ff73 | 1487 | |
76aaf220 | 1488 | /* i915_gem_gtt.c */ |
1d2a314c DV |
1489 | int __must_check i915_gem_init_aliasing_ppgtt(struct drm_device *dev); |
1490 | void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev); | |
7bddb01f DV |
1491 | void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt, |
1492 | struct drm_i915_gem_object *obj, | |
1493 | enum i915_cache_level cache_level); | |
1494 | void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt, | |
1495 | struct drm_i915_gem_object *obj); | |
1d2a314c | 1496 | |
76aaf220 | 1497 | void i915_gem_restore_gtt_mappings(struct drm_device *dev); |
74163907 DV |
1498 | int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj); |
1499 | void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj, | |
e4ffd173 | 1500 | enum i915_cache_level cache_level); |
05394f39 | 1501 | void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj); |
74163907 | 1502 | void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj); |
644ec02b DV |
1503 | void i915_gem_init_global_gtt(struct drm_device *dev, |
1504 | unsigned long start, | |
1505 | unsigned long mappable_end, | |
1506 | unsigned long end); | |
76aaf220 | 1507 | |
b47eb4a2 | 1508 | /* i915_gem_evict.c */ |
2021746e | 1509 | int __must_check i915_gem_evict_something(struct drm_device *dev, int min_size, |
42d6ab48 CW |
1510 | unsigned alignment, |
1511 | unsigned cache_level, | |
86a1ee26 CW |
1512 | bool mappable, |
1513 | bool nonblock); | |
6c085a72 | 1514 | int i915_gem_evict_everything(struct drm_device *dev); |
b47eb4a2 | 1515 | |
9797fbfb CW |
1516 | /* i915_gem_stolen.c */ |
1517 | int i915_gem_init_stolen(struct drm_device *dev); | |
1518 | void i915_gem_cleanup_stolen(struct drm_device *dev); | |
1519 | ||
673a394b EA |
1520 | /* i915_gem_tiling.c */ |
1521 | void i915_gem_detect_bit_6_swizzle(struct drm_device *dev); | |
05394f39 CW |
1522 | void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj); |
1523 | void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj); | |
673a394b EA |
1524 | |
1525 | /* i915_gem_debug.c */ | |
05394f39 | 1526 | void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len, |
673a394b | 1527 | const char *where, uint32_t mark); |
23bc5982 CW |
1528 | #if WATCH_LISTS |
1529 | int i915_verify_lists(struct drm_device *dev); | |
673a394b | 1530 | #else |
23bc5982 | 1531 | #define i915_verify_lists(dev) 0 |
673a394b | 1532 | #endif |
05394f39 CW |
1533 | void i915_gem_object_check_coherency(struct drm_i915_gem_object *obj, |
1534 | int handle); | |
1535 | void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len, | |
673a394b | 1536 | const char *where, uint32_t mark); |
1da177e4 | 1537 | |
2017263e | 1538 | /* i915_debugfs.c */ |
27c202ad BG |
1539 | int i915_debugfs_init(struct drm_minor *minor); |
1540 | void i915_debugfs_cleanup(struct drm_minor *minor); | |
2017263e | 1541 | |
317c35d1 JB |
1542 | /* i915_suspend.c */ |
1543 | extern int i915_save_state(struct drm_device *dev); | |
1544 | extern int i915_restore_state(struct drm_device *dev); | |
0a3e67a4 JB |
1545 | |
1546 | /* i915_suspend.c */ | |
1547 | extern int i915_save_state(struct drm_device *dev); | |
1548 | extern int i915_restore_state(struct drm_device *dev); | |
317c35d1 | 1549 | |
0136db58 BW |
1550 | /* i915_sysfs.c */ |
1551 | void i915_setup_sysfs(struct drm_device *dev_priv); | |
1552 | void i915_teardown_sysfs(struct drm_device *dev_priv); | |
1553 | ||
f899fc64 CW |
1554 | /* intel_i2c.c */ |
1555 | extern int intel_setup_gmbus(struct drm_device *dev); | |
1556 | extern void intel_teardown_gmbus(struct drm_device *dev); | |
3bd7d909 DK |
1557 | extern inline bool intel_gmbus_is_port_valid(unsigned port) |
1558 | { | |
2ed06c93 | 1559 | return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD); |
3bd7d909 DK |
1560 | } |
1561 | ||
1562 | extern struct i2c_adapter *intel_gmbus_get_adapter( | |
1563 | struct drm_i915_private *dev_priv, unsigned port); | |
e957d772 CW |
1564 | extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed); |
1565 | extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit); | |
b8232e90 CW |
1566 | extern inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter) |
1567 | { | |
1568 | return container_of(adapter, struct intel_gmbus, adapter)->force_bit; | |
1569 | } | |
f899fc64 CW |
1570 | extern void intel_i2c_reset(struct drm_device *dev); |
1571 | ||
3b617967 | 1572 | /* intel_opregion.c */ |
44834a67 CW |
1573 | extern int intel_opregion_setup(struct drm_device *dev); |
1574 | #ifdef CONFIG_ACPI | |
1575 | extern void intel_opregion_init(struct drm_device *dev); | |
1576 | extern void intel_opregion_fini(struct drm_device *dev); | |
3b617967 CW |
1577 | extern void intel_opregion_asle_intr(struct drm_device *dev); |
1578 | extern void intel_opregion_gse_intr(struct drm_device *dev); | |
1579 | extern void intel_opregion_enable_asle(struct drm_device *dev); | |
65e082c9 | 1580 | #else |
44834a67 CW |
1581 | static inline void intel_opregion_init(struct drm_device *dev) { return; } |
1582 | static inline void intel_opregion_fini(struct drm_device *dev) { return; } | |
3b617967 CW |
1583 | static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; } |
1584 | static inline void intel_opregion_gse_intr(struct drm_device *dev) { return; } | |
1585 | static inline void intel_opregion_enable_asle(struct drm_device *dev) { return; } | |
65e082c9 | 1586 | #endif |
8ee1c3db | 1587 | |
723bfd70 JB |
1588 | /* intel_acpi.c */ |
1589 | #ifdef CONFIG_ACPI | |
1590 | extern void intel_register_dsm_handler(void); | |
1591 | extern void intel_unregister_dsm_handler(void); | |
1592 | #else | |
1593 | static inline void intel_register_dsm_handler(void) { return; } | |
1594 | static inline void intel_unregister_dsm_handler(void) { return; } | |
1595 | #endif /* CONFIG_ACPI */ | |
1596 | ||
79e53945 | 1597 | /* modesetting */ |
f817586c | 1598 | extern void intel_modeset_init_hw(struct drm_device *dev); |
79e53945 | 1599 | extern void intel_modeset_init(struct drm_device *dev); |
2c7111db | 1600 | extern void intel_modeset_gem_init(struct drm_device *dev); |
79e53945 | 1601 | extern void intel_modeset_cleanup(struct drm_device *dev); |
28d52043 | 1602 | extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state); |
24929352 | 1603 | extern void intel_modeset_setup_hw_state(struct drm_device *dev); |
ee5382ae | 1604 | extern bool intel_fbc_enabled(struct drm_device *dev); |
43a9539f | 1605 | extern void intel_disable_fbc(struct drm_device *dev); |
7648fa99 | 1606 | extern bool ironlake_set_drps(struct drm_device *dev, u8 val); |
9fb526db | 1607 | extern void ironlake_init_pch_refclk(struct drm_device *dev); |
3b8d8d91 | 1608 | extern void gen6_set_rps(struct drm_device *dev, u8 val); |
0206e353 AJ |
1609 | extern void intel_detect_pch(struct drm_device *dev); |
1610 | extern int intel_trans_dp_port_sel(struct drm_crtc *crtc); | |
0136db58 | 1611 | extern int intel_enable_rc6(const struct drm_device *dev); |
3bad0781 | 1612 | |
2911a35b | 1613 | extern bool i915_semaphore_is_enabled(struct drm_device *dev); |
c0c7babc BW |
1614 | int i915_reg_read_ioctl(struct drm_device *dev, void *data, |
1615 | struct drm_file *file); | |
575155a9 | 1616 | |
6ef3d427 | 1617 | /* overlay */ |
3bd3c932 | 1618 | #ifdef CONFIG_DEBUG_FS |
6ef3d427 CW |
1619 | extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev); |
1620 | extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error); | |
c4a1d9e4 CW |
1621 | |
1622 | extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev); | |
1623 | extern void intel_display_print_error_state(struct seq_file *m, | |
1624 | struct drm_device *dev, | |
1625 | struct intel_display_error_state *error); | |
3bd3c932 | 1626 | #endif |
6ef3d427 | 1627 | |
b7287d80 BW |
1628 | /* On SNB platform, before reading ring registers forcewake bit |
1629 | * must be set to prevent GT core from power down and stale values being | |
1630 | * returned. | |
1631 | */ | |
fcca7926 BW |
1632 | void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv); |
1633 | void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv); | |
67a3744f | 1634 | int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv); |
b7287d80 | 1635 | |
42c0526c BW |
1636 | int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val); |
1637 | int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val); | |
1638 | ||
5f75377d | 1639 | #define __i915_read(x, y) \ |
f7000883 | 1640 | u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg); |
fcca7926 | 1641 | |
5f75377d KP |
1642 | __i915_read(8, b) |
1643 | __i915_read(16, w) | |
1644 | __i915_read(32, l) | |
1645 | __i915_read(64, q) | |
1646 | #undef __i915_read | |
1647 | ||
1648 | #define __i915_write(x, y) \ | |
f7000883 AK |
1649 | void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val); |
1650 | ||
5f75377d KP |
1651 | __i915_write(8, b) |
1652 | __i915_write(16, w) | |
1653 | __i915_write(32, l) | |
1654 | __i915_write(64, q) | |
1655 | #undef __i915_write | |
1656 | ||
1657 | #define I915_READ8(reg) i915_read8(dev_priv, (reg)) | |
1658 | #define I915_WRITE8(reg, val) i915_write8(dev_priv, (reg), (val)) | |
1659 | ||
1660 | #define I915_READ16(reg) i915_read16(dev_priv, (reg)) | |
1661 | #define I915_WRITE16(reg, val) i915_write16(dev_priv, (reg), (val)) | |
1662 | #define I915_READ16_NOTRACE(reg) readw(dev_priv->regs + (reg)) | |
1663 | #define I915_WRITE16_NOTRACE(reg, val) writew(val, dev_priv->regs + (reg)) | |
1664 | ||
1665 | #define I915_READ(reg) i915_read32(dev_priv, (reg)) | |
1666 | #define I915_WRITE(reg, val) i915_write32(dev_priv, (reg), (val)) | |
cae5852d ZN |
1667 | #define I915_READ_NOTRACE(reg) readl(dev_priv->regs + (reg)) |
1668 | #define I915_WRITE_NOTRACE(reg, val) writel(val, dev_priv->regs + (reg)) | |
5f75377d KP |
1669 | |
1670 | #define I915_WRITE64(reg, val) i915_write64(dev_priv, (reg), (val)) | |
1671 | #define I915_READ64(reg) i915_read64(dev_priv, (reg)) | |
cae5852d ZN |
1672 | |
1673 | #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg) | |
1674 | #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg) | |
1675 | ||
ba4f01a3 | 1676 | |
1da177e4 | 1677 | #endif |