Commit | Line | Data |
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1da177e4 LT |
1 | /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- |
2 | */ | |
0d6aa60b | 3 | /* |
bc54fd1a | 4 | * |
1da177e4 LT |
5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
6 | * All Rights Reserved. | |
bc54fd1a DA |
7 | * |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the | |
10 | * "Software"), to deal in the Software without restriction, including | |
11 | * without limitation the rights to use, copy, modify, merge, publish, | |
12 | * distribute, sub license, and/or sell copies of the Software, and to | |
13 | * permit persons to whom the Software is furnished to do so, subject to | |
14 | * the following conditions: | |
15 | * | |
16 | * The above copyright notice and this permission notice (including the | |
17 | * next paragraph) shall be included in all copies or substantial portions | |
18 | * of the Software. | |
19 | * | |
20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
27 | * | |
0d6aa60b | 28 | */ |
1da177e4 LT |
29 | |
30 | #ifndef _I915_DRV_H_ | |
31 | #define _I915_DRV_H_ | |
32 | ||
e9b73c67 CW |
33 | #include <uapi/drm/i915_drm.h> |
34 | ||
585fb111 | 35 | #include "i915_reg.h" |
79e53945 | 36 | #include "intel_bios.h" |
8187a2b7 | 37 | #include "intel_ringbuffer.h" |
0839ccb8 | 38 | #include <linux/io-mapping.h> |
f899fc64 | 39 | #include <linux/i2c.h> |
c167a6fc | 40 | #include <linux/i2c-algo-bit.h> |
0ade6386 | 41 | #include <drm/intel-gtt.h> |
aaa6fd2a | 42 | #include <linux/backlight.h> |
2911a35b | 43 | #include <linux/intel-iommu.h> |
742cbee8 | 44 | #include <linux/kref.h> |
9ee32fea | 45 | #include <linux/pm_qos.h> |
585fb111 | 46 | |
1da177e4 LT |
47 | /* General customization: |
48 | */ | |
49 | ||
50 | #define DRIVER_AUTHOR "Tungsten Graphics, Inc." | |
51 | ||
52 | #define DRIVER_NAME "i915" | |
53 | #define DRIVER_DESC "Intel Graphics" | |
673a394b | 54 | #define DRIVER_DATE "20080730" |
1da177e4 | 55 | |
317c35d1 JB |
56 | enum pipe { |
57 | PIPE_A = 0, | |
58 | PIPE_B, | |
9db4a9c7 JB |
59 | PIPE_C, |
60 | I915_MAX_PIPES | |
317c35d1 | 61 | }; |
9db4a9c7 | 62 | #define pipe_name(p) ((p) + 'A') |
317c35d1 | 63 | |
a5c961d1 PZ |
64 | enum transcoder { |
65 | TRANSCODER_A = 0, | |
66 | TRANSCODER_B, | |
67 | TRANSCODER_C, | |
68 | TRANSCODER_EDP = 0xF, | |
69 | }; | |
70 | #define transcoder_name(t) ((t) + 'A') | |
71 | ||
80824003 JB |
72 | enum plane { |
73 | PLANE_A = 0, | |
74 | PLANE_B, | |
9db4a9c7 | 75 | PLANE_C, |
80824003 | 76 | }; |
9db4a9c7 | 77 | #define plane_name(p) ((p) + 'A') |
52440211 | 78 | |
06da8da2 VS |
79 | #define sprite_name(p, s) ((p) * dev_priv->num_plane + (s) + 'A') |
80 | ||
2b139522 ED |
81 | enum port { |
82 | PORT_A = 0, | |
83 | PORT_B, | |
84 | PORT_C, | |
85 | PORT_D, | |
86 | PORT_E, | |
87 | I915_MAX_PORTS | |
88 | }; | |
89 | #define port_name(p) ((p) + 'A') | |
90 | ||
b97186f0 PZ |
91 | enum intel_display_power_domain { |
92 | POWER_DOMAIN_PIPE_A, | |
93 | POWER_DOMAIN_PIPE_B, | |
94 | POWER_DOMAIN_PIPE_C, | |
95 | POWER_DOMAIN_PIPE_A_PANEL_FITTER, | |
96 | POWER_DOMAIN_PIPE_B_PANEL_FITTER, | |
97 | POWER_DOMAIN_PIPE_C_PANEL_FITTER, | |
98 | POWER_DOMAIN_TRANSCODER_A, | |
99 | POWER_DOMAIN_TRANSCODER_B, | |
100 | POWER_DOMAIN_TRANSCODER_C, | |
101 | POWER_DOMAIN_TRANSCODER_EDP = POWER_DOMAIN_TRANSCODER_A + 0xF, | |
102 | }; | |
103 | ||
104 | #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A) | |
105 | #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \ | |
106 | ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER) | |
107 | #define POWER_DOMAIN_TRANSCODER(tran) ((tran) + POWER_DOMAIN_TRANSCODER_A) | |
108 | ||
1d843f9d EE |
109 | enum hpd_pin { |
110 | HPD_NONE = 0, | |
111 | HPD_PORT_A = HPD_NONE, /* PORT_A is internal */ | |
112 | HPD_TV = HPD_NONE, /* TV is known to be unreliable */ | |
113 | HPD_CRT, | |
114 | HPD_SDVO_B, | |
115 | HPD_SDVO_C, | |
116 | HPD_PORT_B, | |
117 | HPD_PORT_C, | |
118 | HPD_PORT_D, | |
119 | HPD_NUM_PINS | |
120 | }; | |
121 | ||
2a2d5482 CW |
122 | #define I915_GEM_GPU_DOMAINS \ |
123 | (I915_GEM_DOMAIN_RENDER | \ | |
124 | I915_GEM_DOMAIN_SAMPLER | \ | |
125 | I915_GEM_DOMAIN_COMMAND | \ | |
126 | I915_GEM_DOMAIN_INSTRUCTION | \ | |
127 | I915_GEM_DOMAIN_VERTEX) | |
62fdfeaf | 128 | |
7eb552ae | 129 | #define for_each_pipe(p) for ((p) = 0; (p) < INTEL_INFO(dev)->num_pipes; (p)++) |
9db4a9c7 | 130 | |
6c2b7c12 DV |
131 | #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \ |
132 | list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \ | |
133 | if ((intel_encoder)->base.crtc == (__crtc)) | |
134 | ||
ee7b9f93 JB |
135 | struct intel_pch_pll { |
136 | int refcount; /* count of number of CRTCs sharing this PLL */ | |
137 | int active; /* count of number of active CRTCs (i.e. DPMS on) */ | |
138 | bool on; /* is the PLL actually active? Disabled during modeset */ | |
139 | int pll_reg; | |
140 | int fp0_reg; | |
141 | int fp1_reg; | |
142 | }; | |
143 | #define I915_NUM_PLLS 2 | |
144 | ||
e69d0bc1 DV |
145 | /* Used by dp and fdi links */ |
146 | struct intel_link_m_n { | |
147 | uint32_t tu; | |
148 | uint32_t gmch_m; | |
149 | uint32_t gmch_n; | |
150 | uint32_t link_m; | |
151 | uint32_t link_n; | |
152 | }; | |
153 | ||
154 | void intel_link_compute_m_n(int bpp, int nlanes, | |
155 | int pixel_clock, int link_clock, | |
156 | struct intel_link_m_n *m_n); | |
157 | ||
6441ab5f PZ |
158 | struct intel_ddi_plls { |
159 | int spll_refcount; | |
160 | int wrpll1_refcount; | |
161 | int wrpll2_refcount; | |
162 | }; | |
163 | ||
1da177e4 LT |
164 | /* Interface history: |
165 | * | |
166 | * 1.1: Original. | |
0d6aa60b DA |
167 | * 1.2: Add Power Management |
168 | * 1.3: Add vblank support | |
de227f5f | 169 | * 1.4: Fix cmdbuffer path, add heap destroy |
702880f2 | 170 | * 1.5: Add vblank pipe configuration |
2228ed67 MCA |
171 | * 1.6: - New ioctl for scheduling buffer swaps on vertical blank |
172 | * - Support vertical blank on secondary display pipe | |
1da177e4 LT |
173 | */ |
174 | #define DRIVER_MAJOR 1 | |
2228ed67 | 175 | #define DRIVER_MINOR 6 |
1da177e4 LT |
176 | #define DRIVER_PATCHLEVEL 0 |
177 | ||
673a394b | 178 | #define WATCH_COHERENCY 0 |
23bc5982 | 179 | #define WATCH_LISTS 0 |
42d6ab48 | 180 | #define WATCH_GTT 0 |
673a394b | 181 | |
71acb5eb DA |
182 | #define I915_GEM_PHYS_CURSOR_0 1 |
183 | #define I915_GEM_PHYS_CURSOR_1 2 | |
184 | #define I915_GEM_PHYS_OVERLAY_REGS 3 | |
185 | #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS) | |
186 | ||
187 | struct drm_i915_gem_phys_object { | |
188 | int id; | |
189 | struct page **page_list; | |
190 | drm_dma_handle_t *handle; | |
05394f39 | 191 | struct drm_i915_gem_object *cur_obj; |
71acb5eb DA |
192 | }; |
193 | ||
0a3e67a4 JB |
194 | struct opregion_header; |
195 | struct opregion_acpi; | |
196 | struct opregion_swsci; | |
197 | struct opregion_asle; | |
8d715f00 | 198 | struct drm_i915_private; |
0a3e67a4 | 199 | |
8ee1c3db | 200 | struct intel_opregion { |
5bc4418b BW |
201 | struct opregion_header __iomem *header; |
202 | struct opregion_acpi __iomem *acpi; | |
203 | struct opregion_swsci __iomem *swsci; | |
204 | struct opregion_asle __iomem *asle; | |
205 | void __iomem *vbt; | |
01fe9dbd | 206 | u32 __iomem *lid_state; |
8ee1c3db | 207 | }; |
44834a67 | 208 | #define OPREGION_SIZE (8*1024) |
8ee1c3db | 209 | |
6ef3d427 CW |
210 | struct intel_overlay; |
211 | struct intel_overlay_error_state; | |
212 | ||
7c1c2871 DA |
213 | struct drm_i915_master_private { |
214 | drm_local_map_t *sarea; | |
215 | struct _drm_i915_sarea *sarea_priv; | |
216 | }; | |
de151cf6 | 217 | #define I915_FENCE_REG_NONE -1 |
42b5aeab VS |
218 | #define I915_MAX_NUM_FENCES 32 |
219 | /* 32 fences + sign bit for FENCE_REG_NONE */ | |
220 | #define I915_MAX_NUM_FENCE_BITS 6 | |
de151cf6 JB |
221 | |
222 | struct drm_i915_fence_reg { | |
007cc8ac | 223 | struct list_head lru_list; |
caea7476 | 224 | struct drm_i915_gem_object *obj; |
1690e1eb | 225 | int pin_count; |
de151cf6 | 226 | }; |
7c1c2871 | 227 | |
9b9d172d | 228 | struct sdvo_device_mapping { |
e957d772 | 229 | u8 initialized; |
9b9d172d | 230 | u8 dvo_port; |
231 | u8 slave_addr; | |
232 | u8 dvo_wiring; | |
e957d772 | 233 | u8 i2c_pin; |
b1083333 | 234 | u8 ddc_pin; |
9b9d172d | 235 | }; |
236 | ||
c4a1d9e4 CW |
237 | struct intel_display_error_state; |
238 | ||
63eeaf38 | 239 | struct drm_i915_error_state { |
742cbee8 | 240 | struct kref ref; |
63eeaf38 JB |
241 | u32 eir; |
242 | u32 pgtbl_er; | |
be998e2e | 243 | u32 ier; |
b9a3906b | 244 | u32 ccid; |
0f3b6849 CW |
245 | u32 derrmr; |
246 | u32 forcewake; | |
9574b3fe | 247 | bool waiting[I915_NUM_RINGS]; |
9db4a9c7 | 248 | u32 pipestat[I915_MAX_PIPES]; |
c1cd90ed DV |
249 | u32 tail[I915_NUM_RINGS]; |
250 | u32 head[I915_NUM_RINGS]; | |
0f3b6849 | 251 | u32 ctl[I915_NUM_RINGS]; |
d27b1e0e DV |
252 | u32 ipeir[I915_NUM_RINGS]; |
253 | u32 ipehr[I915_NUM_RINGS]; | |
254 | u32 instdone[I915_NUM_RINGS]; | |
255 | u32 acthd[I915_NUM_RINGS]; | |
7e3b8737 | 256 | u32 semaphore_mboxes[I915_NUM_RINGS][I915_NUM_RINGS - 1]; |
df2b23d9 | 257 | u32 semaphore_seqno[I915_NUM_RINGS][I915_NUM_RINGS - 1]; |
12f55818 | 258 | u32 rc_psmi[I915_NUM_RINGS]; /* sleep state */ |
7e3b8737 DV |
259 | /* our own tracking of ring head and tail */ |
260 | u32 cpu_ring_head[I915_NUM_RINGS]; | |
261 | u32 cpu_ring_tail[I915_NUM_RINGS]; | |
1d8f38f4 | 262 | u32 error; /* gen6+ */ |
71e172e8 | 263 | u32 err_int; /* gen7 */ |
c1cd90ed DV |
264 | u32 instpm[I915_NUM_RINGS]; |
265 | u32 instps[I915_NUM_RINGS]; | |
050ee91f | 266 | u32 extra_instdone[I915_NUM_INSTDONE_REG]; |
d27b1e0e | 267 | u32 seqno[I915_NUM_RINGS]; |
9df30794 | 268 | u64 bbaddr; |
33f3f518 DV |
269 | u32 fault_reg[I915_NUM_RINGS]; |
270 | u32 done_reg; | |
c1cd90ed | 271 | u32 faddr[I915_NUM_RINGS]; |
4b9de737 | 272 | u64 fence[I915_MAX_NUM_FENCES]; |
63eeaf38 | 273 | struct timeval time; |
52d39a21 CW |
274 | struct drm_i915_error_ring { |
275 | struct drm_i915_error_object { | |
276 | int page_count; | |
277 | u32 gtt_offset; | |
278 | u32 *pages[0]; | |
8c123e54 | 279 | } *ringbuffer, *batchbuffer, *ctx; |
52d39a21 CW |
280 | struct drm_i915_error_request { |
281 | long jiffies; | |
282 | u32 seqno; | |
ee4f42b1 | 283 | u32 tail; |
52d39a21 CW |
284 | } *requests; |
285 | int num_requests; | |
286 | } ring[I915_NUM_RINGS]; | |
9df30794 | 287 | struct drm_i915_error_buffer { |
a779e5ab | 288 | u32 size; |
9df30794 | 289 | u32 name; |
0201f1ec | 290 | u32 rseqno, wseqno; |
9df30794 CW |
291 | u32 gtt_offset; |
292 | u32 read_domains; | |
293 | u32 write_domain; | |
4b9de737 | 294 | s32 fence_reg:I915_MAX_NUM_FENCE_BITS; |
9df30794 CW |
295 | s32 pinned:2; |
296 | u32 tiling:2; | |
297 | u32 dirty:1; | |
298 | u32 purgeable:1; | |
5d1333fc | 299 | s32 ring:4; |
93dfb40c | 300 | u32 cache_level:2; |
c724e8a9 CW |
301 | } *active_bo, *pinned_bo; |
302 | u32 active_bo_count, pinned_bo_count; | |
6ef3d427 | 303 | struct intel_overlay_error_state *overlay; |
c4a1d9e4 | 304 | struct intel_display_error_state *display; |
63eeaf38 JB |
305 | }; |
306 | ||
b8cecdf5 | 307 | struct intel_crtc_config; |
0e8ffe1b | 308 | struct intel_crtc; |
b8cecdf5 | 309 | |
e70236a8 | 310 | struct drm_i915_display_funcs { |
ee5382ae | 311 | bool (*fbc_enabled)(struct drm_device *dev); |
e70236a8 JB |
312 | void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval); |
313 | void (*disable_fbc)(struct drm_device *dev); | |
314 | int (*get_display_clock_speed)(struct drm_device *dev); | |
315 | int (*get_fifo_size)(struct drm_device *dev, int plane); | |
d210246a | 316 | void (*update_wm)(struct drm_device *dev); |
b840d907 | 317 | void (*update_sprite_wm)(struct drm_device *dev, int pipe, |
4c4ff43a PZ |
318 | uint32_t sprite_width, int pixel_size, |
319 | bool enable); | |
47fab737 | 320 | void (*modeset_global_resources)(struct drm_device *dev); |
0e8ffe1b DV |
321 | /* Returns the active state of the crtc, and if the crtc is active, |
322 | * fills out the pipe-config with the hw state. */ | |
323 | bool (*get_pipe_config)(struct intel_crtc *, | |
324 | struct intel_crtc_config *); | |
f564048e | 325 | int (*crtc_mode_set)(struct drm_crtc *crtc, |
f564048e EA |
326 | int x, int y, |
327 | struct drm_framebuffer *old_fb); | |
76e5a89c DV |
328 | void (*crtc_enable)(struct drm_crtc *crtc); |
329 | void (*crtc_disable)(struct drm_crtc *crtc); | |
ee7b9f93 | 330 | void (*off)(struct drm_crtc *crtc); |
e0dac65e WF |
331 | void (*write_eld)(struct drm_connector *connector, |
332 | struct drm_crtc *crtc); | |
674cf967 | 333 | void (*fdi_link_train)(struct drm_crtc *crtc); |
6067aaea | 334 | void (*init_clock_gating)(struct drm_device *dev); |
8c9f3aaf JB |
335 | int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc, |
336 | struct drm_framebuffer *fb, | |
337 | struct drm_i915_gem_object *obj); | |
17638cd6 JB |
338 | int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb, |
339 | int x, int y); | |
20afbda2 | 340 | void (*hpd_irq_setup)(struct drm_device *dev); |
e70236a8 JB |
341 | /* clock updates for mode set */ |
342 | /* cursor updates */ | |
343 | /* render clock increase/decrease */ | |
344 | /* display clock increase/decrease */ | |
345 | /* pll clock increase/decrease */ | |
e70236a8 JB |
346 | }; |
347 | ||
990bbdad CW |
348 | struct drm_i915_gt_funcs { |
349 | void (*force_wake_get)(struct drm_i915_private *dev_priv); | |
350 | void (*force_wake_put)(struct drm_i915_private *dev_priv); | |
351 | }; | |
352 | ||
79fc46df DL |
353 | #define DEV_INFO_FOR_EACH_FLAG(func, sep) \ |
354 | func(is_mobile) sep \ | |
355 | func(is_i85x) sep \ | |
356 | func(is_i915g) sep \ | |
357 | func(is_i945gm) sep \ | |
358 | func(is_g33) sep \ | |
359 | func(need_gfx_hws) sep \ | |
360 | func(is_g4x) sep \ | |
361 | func(is_pineview) sep \ | |
362 | func(is_broadwater) sep \ | |
363 | func(is_crestline) sep \ | |
364 | func(is_ivybridge) sep \ | |
365 | func(is_valleyview) sep \ | |
366 | func(is_haswell) sep \ | |
367 | func(has_force_wake) sep \ | |
368 | func(has_fbc) sep \ | |
369 | func(has_pipe_cxsr) sep \ | |
370 | func(has_hotplug) sep \ | |
371 | func(cursor_needs_physical) sep \ | |
372 | func(has_overlay) sep \ | |
373 | func(overlay_needs_physical) sep \ | |
374 | func(supports_tv) sep \ | |
375 | func(has_bsd_ring) sep \ | |
376 | func(has_blt_ring) sep \ | |
f72a1183 | 377 | func(has_vebox_ring) sep \ |
dd93be58 | 378 | func(has_llc) sep \ |
30568c45 DL |
379 | func(has_ddi) sep \ |
380 | func(has_fpga_dbg) | |
c96ea64e | 381 | |
a587f779 DL |
382 | #define DEFINE_FLAG(name) u8 name:1 |
383 | #define SEP_SEMICOLON ; | |
384 | ||
cfdf1fa2 | 385 | struct intel_device_info { |
10fce67a | 386 | u32 display_mmio_offset; |
7eb552ae | 387 | u8 num_pipes:3; |
c96c3a8c | 388 | u8 gen; |
a587f779 | 389 | DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON); |
cfdf1fa2 KH |
390 | }; |
391 | ||
a587f779 DL |
392 | #undef DEFINE_FLAG |
393 | #undef SEP_SEMICOLON | |
394 | ||
7faf1ab2 DV |
395 | enum i915_cache_level { |
396 | I915_CACHE_NONE = 0, | |
397 | I915_CACHE_LLC, | |
398 | I915_CACHE_LLC_MLC, /* gen6+, in docs at least! */ | |
399 | }; | |
400 | ||
2d04befb KG |
401 | typedef uint32_t gen6_gtt_pte_t; |
402 | ||
5d4545ae BW |
403 | /* The Graphics Translation Table is the way in which GEN hardware translates a |
404 | * Graphics Virtual Address into a Physical Address. In addition to the normal | |
405 | * collateral associated with any va->pa translations GEN hardware also has a | |
406 | * portion of the GTT which can be mapped by the CPU and remain both coherent | |
407 | * and correct (in cases like swizzling). That region is referred to as GMADR in | |
408 | * the spec. | |
409 | */ | |
410 | struct i915_gtt { | |
411 | unsigned long start; /* Start offset of used GTT */ | |
412 | size_t total; /* Total size GTT can map */ | |
baa09f5f | 413 | size_t stolen_size; /* Total size of stolen memory */ |
5d4545ae BW |
414 | |
415 | unsigned long mappable_end; /* End offset that we can CPU map */ | |
416 | struct io_mapping *mappable; /* Mapping to our CPU mappable region */ | |
417 | phys_addr_t mappable_base; /* PA of our GMADR */ | |
418 | ||
419 | /** "Graphics Stolen Memory" holds the global PTEs */ | |
420 | void __iomem *gsm; | |
a81cc00c BW |
421 | |
422 | bool do_idle_maps; | |
9c61a32d BW |
423 | dma_addr_t scratch_page_dma; |
424 | struct page *scratch_page; | |
7faf1ab2 DV |
425 | |
426 | /* global gtt ops */ | |
baa09f5f | 427 | int (*gtt_probe)(struct drm_device *dev, size_t *gtt_total, |
41907ddc BW |
428 | size_t *stolen, phys_addr_t *mappable_base, |
429 | unsigned long *mappable_end); | |
baa09f5f | 430 | void (*gtt_remove)(struct drm_device *dev); |
7faf1ab2 DV |
431 | void (*gtt_clear_range)(struct drm_device *dev, |
432 | unsigned int first_entry, | |
433 | unsigned int num_entries); | |
434 | void (*gtt_insert_entries)(struct drm_device *dev, | |
435 | struct sg_table *st, | |
436 | unsigned int pg_start, | |
437 | enum i915_cache_level cache_level); | |
2d04befb KG |
438 | gen6_gtt_pte_t (*pte_encode)(struct drm_device *dev, |
439 | dma_addr_t addr, | |
440 | enum i915_cache_level level); | |
5d4545ae | 441 | }; |
a54c0c27 | 442 | #define gtt_total_entries(gtt) ((gtt).total >> PAGE_SHIFT) |
5d4545ae | 443 | |
1d2a314c DV |
444 | #define I915_PPGTT_PD_ENTRIES 512 |
445 | #define I915_PPGTT_PT_ENTRIES 1024 | |
446 | struct i915_hw_ppgtt { | |
8f2c59f0 | 447 | struct drm_device *dev; |
1d2a314c DV |
448 | unsigned num_pd_entries; |
449 | struct page **pt_pages; | |
450 | uint32_t pd_offset; | |
451 | dma_addr_t *pt_dma_addr; | |
452 | dma_addr_t scratch_page_dma_addr; | |
def886c3 DV |
453 | |
454 | /* pte functions, mirroring the interface of the global gtt. */ | |
455 | void (*clear_range)(struct i915_hw_ppgtt *ppgtt, | |
456 | unsigned int first_entry, | |
457 | unsigned int num_entries); | |
458 | void (*insert_entries)(struct i915_hw_ppgtt *ppgtt, | |
459 | struct sg_table *st, | |
460 | unsigned int pg_start, | |
461 | enum i915_cache_level cache_level); | |
2d04befb KG |
462 | gen6_gtt_pte_t (*pte_encode)(struct drm_device *dev, |
463 | dma_addr_t addr, | |
464 | enum i915_cache_level level); | |
b7c36d25 | 465 | int (*enable)(struct drm_device *dev); |
3440d265 | 466 | void (*cleanup)(struct i915_hw_ppgtt *ppgtt); |
1d2a314c DV |
467 | }; |
468 | ||
40521054 BW |
469 | |
470 | /* This must match up with the value previously used for execbuf2.rsvd1. */ | |
471 | #define DEFAULT_CONTEXT_ID 0 | |
472 | struct i915_hw_context { | |
dce3271b | 473 | struct kref ref; |
40521054 | 474 | int id; |
e0556841 | 475 | bool is_initialized; |
40521054 BW |
476 | struct drm_i915_file_private *file_priv; |
477 | struct intel_ring_buffer *ring; | |
478 | struct drm_i915_gem_object *obj; | |
479 | }; | |
480 | ||
b5e50c3f | 481 | enum no_fbc_reason { |
bed4a673 | 482 | FBC_NO_OUTPUT, /* no outputs enabled to compress */ |
b5e50c3f JB |
483 | FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */ |
484 | FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */ | |
485 | FBC_MODE_TOO_LARGE, /* mode too large for compression */ | |
486 | FBC_BAD_PLANE, /* fbc not supported on plane */ | |
487 | FBC_NOT_TILED, /* buffer not tiled */ | |
9c928d16 | 488 | FBC_MULTIPLE_PIPES, /* more than one pipe active */ |
c1a9f047 | 489 | FBC_MODULE_PARAM, |
b5e50c3f JB |
490 | }; |
491 | ||
3bad0781 | 492 | enum intel_pch { |
f0350830 | 493 | PCH_NONE = 0, /* No PCH present */ |
3bad0781 ZW |
494 | PCH_IBX, /* Ibexpeak PCH */ |
495 | PCH_CPT, /* Cougarpoint PCH */ | |
eb877ebf | 496 | PCH_LPT, /* Lynxpoint PCH */ |
40c7ead9 | 497 | PCH_NOP, |
3bad0781 ZW |
498 | }; |
499 | ||
988d6ee8 PZ |
500 | enum intel_sbi_destination { |
501 | SBI_ICLK, | |
502 | SBI_MPHY, | |
503 | }; | |
504 | ||
b690e96c | 505 | #define QUIRK_PIPEA_FORCE (1<<0) |
435793df | 506 | #define QUIRK_LVDS_SSC_DISABLE (1<<1) |
4dca20ef | 507 | #define QUIRK_INVERT_BRIGHTNESS (1<<2) |
b690e96c | 508 | |
8be48d92 | 509 | struct intel_fbdev; |
1630fe75 | 510 | struct intel_fbc_work; |
38651674 | 511 | |
c2b9152f DV |
512 | struct intel_gmbus { |
513 | struct i2c_adapter adapter; | |
f2ce9faf | 514 | u32 force_bit; |
c2b9152f | 515 | u32 reg0; |
36c785f0 | 516 | u32 gpio_reg; |
c167a6fc | 517 | struct i2c_algo_bit_data bit_algo; |
c2b9152f DV |
518 | struct drm_i915_private *dev_priv; |
519 | }; | |
520 | ||
f4c956ad | 521 | struct i915_suspend_saved_registers { |
ba8bbcf6 JB |
522 | u8 saveLBB; |
523 | u32 saveDSPACNTR; | |
524 | u32 saveDSPBCNTR; | |
e948e994 | 525 | u32 saveDSPARB; |
ba8bbcf6 JB |
526 | u32 savePIPEACONF; |
527 | u32 savePIPEBCONF; | |
528 | u32 savePIPEASRC; | |
529 | u32 savePIPEBSRC; | |
530 | u32 saveFPA0; | |
531 | u32 saveFPA1; | |
532 | u32 saveDPLL_A; | |
533 | u32 saveDPLL_A_MD; | |
534 | u32 saveHTOTAL_A; | |
535 | u32 saveHBLANK_A; | |
536 | u32 saveHSYNC_A; | |
537 | u32 saveVTOTAL_A; | |
538 | u32 saveVBLANK_A; | |
539 | u32 saveVSYNC_A; | |
540 | u32 saveBCLRPAT_A; | |
5586c8bc | 541 | u32 saveTRANSACONF; |
42048781 ZW |
542 | u32 saveTRANS_HTOTAL_A; |
543 | u32 saveTRANS_HBLANK_A; | |
544 | u32 saveTRANS_HSYNC_A; | |
545 | u32 saveTRANS_VTOTAL_A; | |
546 | u32 saveTRANS_VBLANK_A; | |
547 | u32 saveTRANS_VSYNC_A; | |
0da3ea12 | 548 | u32 savePIPEASTAT; |
ba8bbcf6 JB |
549 | u32 saveDSPASTRIDE; |
550 | u32 saveDSPASIZE; | |
551 | u32 saveDSPAPOS; | |
585fb111 | 552 | u32 saveDSPAADDR; |
ba8bbcf6 JB |
553 | u32 saveDSPASURF; |
554 | u32 saveDSPATILEOFF; | |
555 | u32 savePFIT_PGM_RATIOS; | |
0eb96d6e | 556 | u32 saveBLC_HIST_CTL; |
ba8bbcf6 JB |
557 | u32 saveBLC_PWM_CTL; |
558 | u32 saveBLC_PWM_CTL2; | |
42048781 ZW |
559 | u32 saveBLC_CPU_PWM_CTL; |
560 | u32 saveBLC_CPU_PWM_CTL2; | |
ba8bbcf6 JB |
561 | u32 saveFPB0; |
562 | u32 saveFPB1; | |
563 | u32 saveDPLL_B; | |
564 | u32 saveDPLL_B_MD; | |
565 | u32 saveHTOTAL_B; | |
566 | u32 saveHBLANK_B; | |
567 | u32 saveHSYNC_B; | |
568 | u32 saveVTOTAL_B; | |
569 | u32 saveVBLANK_B; | |
570 | u32 saveVSYNC_B; | |
571 | u32 saveBCLRPAT_B; | |
5586c8bc | 572 | u32 saveTRANSBCONF; |
42048781 ZW |
573 | u32 saveTRANS_HTOTAL_B; |
574 | u32 saveTRANS_HBLANK_B; | |
575 | u32 saveTRANS_HSYNC_B; | |
576 | u32 saveTRANS_VTOTAL_B; | |
577 | u32 saveTRANS_VBLANK_B; | |
578 | u32 saveTRANS_VSYNC_B; | |
0da3ea12 | 579 | u32 savePIPEBSTAT; |
ba8bbcf6 JB |
580 | u32 saveDSPBSTRIDE; |
581 | u32 saveDSPBSIZE; | |
582 | u32 saveDSPBPOS; | |
585fb111 | 583 | u32 saveDSPBADDR; |
ba8bbcf6 JB |
584 | u32 saveDSPBSURF; |
585 | u32 saveDSPBTILEOFF; | |
585fb111 JB |
586 | u32 saveVGA0; |
587 | u32 saveVGA1; | |
588 | u32 saveVGA_PD; | |
ba8bbcf6 JB |
589 | u32 saveVGACNTRL; |
590 | u32 saveADPA; | |
591 | u32 saveLVDS; | |
585fb111 JB |
592 | u32 savePP_ON_DELAYS; |
593 | u32 savePP_OFF_DELAYS; | |
ba8bbcf6 JB |
594 | u32 saveDVOA; |
595 | u32 saveDVOB; | |
596 | u32 saveDVOC; | |
597 | u32 savePP_ON; | |
598 | u32 savePP_OFF; | |
599 | u32 savePP_CONTROL; | |
585fb111 | 600 | u32 savePP_DIVISOR; |
ba8bbcf6 JB |
601 | u32 savePFIT_CONTROL; |
602 | u32 save_palette_a[256]; | |
603 | u32 save_palette_b[256]; | |
06027f91 | 604 | u32 saveDPFC_CB_BASE; |
ba8bbcf6 JB |
605 | u32 saveFBC_CFB_BASE; |
606 | u32 saveFBC_LL_BASE; | |
607 | u32 saveFBC_CONTROL; | |
608 | u32 saveFBC_CONTROL2; | |
0da3ea12 JB |
609 | u32 saveIER; |
610 | u32 saveIIR; | |
611 | u32 saveIMR; | |
42048781 ZW |
612 | u32 saveDEIER; |
613 | u32 saveDEIMR; | |
614 | u32 saveGTIER; | |
615 | u32 saveGTIMR; | |
616 | u32 saveFDI_RXA_IMR; | |
617 | u32 saveFDI_RXB_IMR; | |
1f84e550 | 618 | u32 saveCACHE_MODE_0; |
1f84e550 | 619 | u32 saveMI_ARB_STATE; |
ba8bbcf6 JB |
620 | u32 saveSWF0[16]; |
621 | u32 saveSWF1[16]; | |
622 | u32 saveSWF2[3]; | |
623 | u8 saveMSR; | |
624 | u8 saveSR[8]; | |
123f794f | 625 | u8 saveGR[25]; |
ba8bbcf6 | 626 | u8 saveAR_INDEX; |
a59e122a | 627 | u8 saveAR[21]; |
ba8bbcf6 | 628 | u8 saveDACMASK; |
a59e122a | 629 | u8 saveCR[37]; |
4b9de737 | 630 | uint64_t saveFENCE[I915_MAX_NUM_FENCES]; |
1fd1c624 EA |
631 | u32 saveCURACNTR; |
632 | u32 saveCURAPOS; | |
633 | u32 saveCURABASE; | |
634 | u32 saveCURBCNTR; | |
635 | u32 saveCURBPOS; | |
636 | u32 saveCURBBASE; | |
637 | u32 saveCURSIZE; | |
a4fc5ed6 KP |
638 | u32 saveDP_B; |
639 | u32 saveDP_C; | |
640 | u32 saveDP_D; | |
641 | u32 savePIPEA_GMCH_DATA_M; | |
642 | u32 savePIPEB_GMCH_DATA_M; | |
643 | u32 savePIPEA_GMCH_DATA_N; | |
644 | u32 savePIPEB_GMCH_DATA_N; | |
645 | u32 savePIPEA_DP_LINK_M; | |
646 | u32 savePIPEB_DP_LINK_M; | |
647 | u32 savePIPEA_DP_LINK_N; | |
648 | u32 savePIPEB_DP_LINK_N; | |
42048781 ZW |
649 | u32 saveFDI_RXA_CTL; |
650 | u32 saveFDI_TXA_CTL; | |
651 | u32 saveFDI_RXB_CTL; | |
652 | u32 saveFDI_TXB_CTL; | |
653 | u32 savePFA_CTL_1; | |
654 | u32 savePFB_CTL_1; | |
655 | u32 savePFA_WIN_SZ; | |
656 | u32 savePFB_WIN_SZ; | |
657 | u32 savePFA_WIN_POS; | |
658 | u32 savePFB_WIN_POS; | |
5586c8bc ZW |
659 | u32 savePCH_DREF_CONTROL; |
660 | u32 saveDISP_ARB_CTL; | |
661 | u32 savePIPEA_DATA_M1; | |
662 | u32 savePIPEA_DATA_N1; | |
663 | u32 savePIPEA_LINK_M1; | |
664 | u32 savePIPEA_LINK_N1; | |
665 | u32 savePIPEB_DATA_M1; | |
666 | u32 savePIPEB_DATA_N1; | |
667 | u32 savePIPEB_LINK_M1; | |
668 | u32 savePIPEB_LINK_N1; | |
b5b72e89 | 669 | u32 saveMCHBAR_RENDER_STANDBY; |
cda2bb78 | 670 | u32 savePCH_PORT_HOTPLUG; |
f4c956ad | 671 | }; |
c85aa885 DV |
672 | |
673 | struct intel_gen6_power_mgmt { | |
674 | struct work_struct work; | |
52ceb908 | 675 | struct delayed_work vlv_work; |
c85aa885 DV |
676 | u32 pm_iir; |
677 | /* lock - irqsave spinlock that protectects the work_struct and | |
678 | * pm_iir. */ | |
679 | spinlock_t lock; | |
680 | ||
681 | /* The below variables an all the rps hw state are protected by | |
682 | * dev->struct mutext. */ | |
683 | u8 cur_delay; | |
684 | u8 min_delay; | |
685 | u8 max_delay; | |
52ceb908 | 686 | u8 rpe_delay; |
31c77388 | 687 | u8 hw_max; |
1a01ab3b JB |
688 | |
689 | struct delayed_work delayed_resume_work; | |
4fc688ce JB |
690 | |
691 | /* | |
692 | * Protects RPS/RC6 register access and PCU communication. | |
693 | * Must be taken after struct_mutex if nested. | |
694 | */ | |
695 | struct mutex hw_lock; | |
c85aa885 DV |
696 | }; |
697 | ||
1a240d4d DV |
698 | /* defined intel_pm.c */ |
699 | extern spinlock_t mchdev_lock; | |
700 | ||
c85aa885 DV |
701 | struct intel_ilk_power_mgmt { |
702 | u8 cur_delay; | |
703 | u8 min_delay; | |
704 | u8 max_delay; | |
705 | u8 fmax; | |
706 | u8 fstart; | |
707 | ||
708 | u64 last_count1; | |
709 | unsigned long last_time1; | |
710 | unsigned long chipset_power; | |
711 | u64 last_count2; | |
712 | struct timespec last_time2; | |
713 | unsigned long gfx_power; | |
714 | u8 corr; | |
715 | ||
716 | int c_m; | |
717 | int r_t; | |
3e373948 DV |
718 | |
719 | struct drm_i915_gem_object *pwrctx; | |
720 | struct drm_i915_gem_object *renderctx; | |
c85aa885 DV |
721 | }; |
722 | ||
231f42a4 DV |
723 | struct i915_dri1_state { |
724 | unsigned allow_batchbuffer : 1; | |
725 | u32 __iomem *gfx_hws_cpu_addr; | |
726 | ||
727 | unsigned int cpp; | |
728 | int back_offset; | |
729 | int front_offset; | |
730 | int current_page; | |
731 | int page_flipping; | |
732 | ||
733 | uint32_t counter; | |
734 | }; | |
735 | ||
a4da4fa4 DV |
736 | struct intel_l3_parity { |
737 | u32 *remap_info; | |
738 | struct work_struct error_work; | |
739 | }; | |
740 | ||
4b5aed62 | 741 | struct i915_gem_mm { |
4b5aed62 DV |
742 | /** Memory allocator for GTT stolen memory */ |
743 | struct drm_mm stolen; | |
744 | /** Memory allocator for GTT */ | |
745 | struct drm_mm gtt_space; | |
746 | /** List of all objects in gtt_space. Used to restore gtt | |
747 | * mappings on resume */ | |
748 | struct list_head bound_list; | |
749 | /** | |
750 | * List of objects which are not bound to the GTT (thus | |
751 | * are idle and not used by the GPU) but still have | |
752 | * (presumably uncached) pages still attached. | |
753 | */ | |
754 | struct list_head unbound_list; | |
755 | ||
756 | /** Usable portion of the GTT for GEM */ | |
757 | unsigned long stolen_base; /* limited to low memory (32-bit) */ | |
758 | ||
759 | int gtt_mtrr; | |
760 | ||
761 | /** PPGTT used for aliasing the PPGTT with the GTT */ | |
762 | struct i915_hw_ppgtt *aliasing_ppgtt; | |
763 | ||
764 | struct shrinker inactive_shrinker; | |
765 | bool shrinker_no_lock_stealing; | |
766 | ||
767 | /** | |
768 | * List of objects currently involved in rendering. | |
769 | * | |
770 | * Includes buffers having the contents of their GPU caches | |
771 | * flushed, not necessarily primitives. last_rendering_seqno | |
772 | * represents when the rendering involved will be completed. | |
773 | * | |
774 | * A reference is held on the buffer while on this list. | |
775 | */ | |
776 | struct list_head active_list; | |
777 | ||
778 | /** | |
779 | * LRU list of objects which are not in the ringbuffer and | |
780 | * are ready to unbind, but are still in the GTT. | |
781 | * | |
782 | * last_rendering_seqno is 0 while an object is in this list. | |
783 | * | |
784 | * A reference is not held on the buffer while on this list, | |
785 | * as merely being GTT-bound shouldn't prevent its being | |
786 | * freed, and we'll pull it off the list in the free path. | |
787 | */ | |
788 | struct list_head inactive_list; | |
789 | ||
790 | /** LRU list of objects with fence regs on them. */ | |
791 | struct list_head fence_list; | |
792 | ||
793 | /** | |
794 | * We leave the user IRQ off as much as possible, | |
795 | * but this means that requests will finish and never | |
796 | * be retired once the system goes idle. Set a timer to | |
797 | * fire periodically while the ring is running. When it | |
798 | * fires, go retire requests. | |
799 | */ | |
800 | struct delayed_work retire_work; | |
801 | ||
802 | /** | |
803 | * Are we in a non-interruptible section of code like | |
804 | * modesetting? | |
805 | */ | |
806 | bool interruptible; | |
807 | ||
808 | /** | |
809 | * Flag if the X Server, and thus DRM, is not currently in | |
810 | * control of the device. | |
811 | * | |
812 | * This is set between LeaveVT and EnterVT. It needs to be | |
813 | * replaced with a semaphore. It also needs to be | |
814 | * transitioned away from for kernel modesetting. | |
815 | */ | |
816 | int suspended; | |
817 | ||
4b5aed62 DV |
818 | /** Bit 6 swizzling required for X tiling */ |
819 | uint32_t bit_6_swizzle_x; | |
820 | /** Bit 6 swizzling required for Y tiling */ | |
821 | uint32_t bit_6_swizzle_y; | |
822 | ||
823 | /* storage for physical objects */ | |
824 | struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT]; | |
825 | ||
826 | /* accounting, useful for userland debugging */ | |
827 | size_t object_memory; | |
828 | u32 object_count; | |
829 | }; | |
830 | ||
edc3d884 MK |
831 | struct drm_i915_error_state_buf { |
832 | unsigned bytes; | |
833 | unsigned size; | |
834 | int err; | |
835 | u8 *buf; | |
836 | loff_t start; | |
837 | loff_t pos; | |
838 | }; | |
839 | ||
99584db3 DV |
840 | struct i915_gpu_error { |
841 | /* For hangcheck timer */ | |
842 | #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */ | |
843 | #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD) | |
844 | struct timer_list hangcheck_timer; | |
845 | int hangcheck_count; | |
99584db3 DV |
846 | |
847 | /* For reset and error_state handling. */ | |
848 | spinlock_t lock; | |
849 | /* Protected by the above dev->gpu_error.lock. */ | |
850 | struct drm_i915_error_state *first_error; | |
851 | struct work_struct work; | |
99584db3 DV |
852 | |
853 | unsigned long last_reset; | |
854 | ||
1f83fee0 | 855 | /** |
f69061be | 856 | * State variable and reset counter controlling the reset flow |
1f83fee0 | 857 | * |
f69061be DV |
858 | * Upper bits are for the reset counter. This counter is used by the |
859 | * wait_seqno code to race-free noticed that a reset event happened and | |
860 | * that it needs to restart the entire ioctl (since most likely the | |
861 | * seqno it waited for won't ever signal anytime soon). | |
862 | * | |
863 | * This is important for lock-free wait paths, where no contended lock | |
864 | * naturally enforces the correct ordering between the bail-out of the | |
865 | * waiter and the gpu reset work code. | |
1f83fee0 DV |
866 | * |
867 | * Lowest bit controls the reset state machine: Set means a reset is in | |
868 | * progress. This state will (presuming we don't have any bugs) decay | |
869 | * into either unset (successful reset) or the special WEDGED value (hw | |
870 | * terminally sour). All waiters on the reset_queue will be woken when | |
871 | * that happens. | |
872 | */ | |
873 | atomic_t reset_counter; | |
874 | ||
875 | /** | |
876 | * Special values/flags for reset_counter | |
877 | * | |
878 | * Note that the code relies on | |
879 | * I915_WEDGED & I915_RESET_IN_PROGRESS_FLAG | |
880 | * being true. | |
881 | */ | |
882 | #define I915_RESET_IN_PROGRESS_FLAG 1 | |
883 | #define I915_WEDGED 0xffffffff | |
884 | ||
885 | /** | |
886 | * Waitqueue to signal when the reset has completed. Used by clients | |
887 | * that wait for dev_priv->mm.wedged to settle. | |
888 | */ | |
889 | wait_queue_head_t reset_queue; | |
33196ded | 890 | |
99584db3 DV |
891 | /* For gpu hang simulation. */ |
892 | unsigned int stop_rings; | |
893 | }; | |
894 | ||
b8efb17b ZR |
895 | enum modeset_restore { |
896 | MODESET_ON_LID_OPEN, | |
897 | MODESET_DONE, | |
898 | MODESET_SUSPENDED, | |
899 | }; | |
900 | ||
41aa3448 RV |
901 | struct intel_vbt_data { |
902 | struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ | |
903 | struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ | |
904 | ||
905 | /* Feature bits */ | |
906 | unsigned int int_tv_support:1; | |
907 | unsigned int lvds_dither:1; | |
908 | unsigned int lvds_vbt:1; | |
909 | unsigned int int_crt_support:1; | |
910 | unsigned int lvds_use_ssc:1; | |
911 | unsigned int display_clock_mode:1; | |
912 | unsigned int fdi_rx_polarity_inverted:1; | |
913 | int lvds_ssc_freq; | |
914 | unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */ | |
915 | ||
916 | /* eDP */ | |
917 | int edp_rate; | |
918 | int edp_lanes; | |
919 | int edp_preemphasis; | |
920 | int edp_vswing; | |
921 | bool edp_initialized; | |
922 | bool edp_support; | |
923 | int edp_bpp; | |
924 | struct edp_power_seq edp_pps; | |
925 | ||
926 | int crt_ddc_pin; | |
927 | ||
928 | int child_dev_num; | |
929 | struct child_device_config *child_dev; | |
930 | }; | |
931 | ||
f4c956ad DV |
932 | typedef struct drm_i915_private { |
933 | struct drm_device *dev; | |
42dcedd4 | 934 | struct kmem_cache *slab; |
f4c956ad DV |
935 | |
936 | const struct intel_device_info *info; | |
937 | ||
938 | int relative_constants_mode; | |
939 | ||
940 | void __iomem *regs; | |
941 | ||
942 | struct drm_i915_gt_funcs gt; | |
943 | /** gt_fifo_count and the subsequent register write are synchronized | |
944 | * with dev->struct_mutex. */ | |
945 | unsigned gt_fifo_count; | |
946 | /** forcewake_count is protected by gt_lock */ | |
947 | unsigned forcewake_count; | |
948 | /** gt_lock is also taken in irq contexts. */ | |
99057c81 | 949 | spinlock_t gt_lock; |
f4c956ad DV |
950 | |
951 | struct intel_gmbus gmbus[GMBUS_NUM_PORTS]; | |
952 | ||
28c70f16 | 953 | |
f4c956ad DV |
954 | /** gmbus_mutex protects against concurrent usage of the single hw gmbus |
955 | * controller on different i2c buses. */ | |
956 | struct mutex gmbus_mutex; | |
957 | ||
958 | /** | |
959 | * Base address of the gmbus and gpio block. | |
960 | */ | |
961 | uint32_t gpio_mmio_base; | |
962 | ||
28c70f16 DV |
963 | wait_queue_head_t gmbus_wait_queue; |
964 | ||
f4c956ad DV |
965 | struct pci_dev *bridge_dev; |
966 | struct intel_ring_buffer ring[I915_NUM_RINGS]; | |
f72b3435 | 967 | uint32_t last_seqno, next_seqno; |
f4c956ad DV |
968 | |
969 | drm_dma_handle_t *status_page_dmah; | |
f4c956ad DV |
970 | struct resource mch_res; |
971 | ||
972 | atomic_t irq_received; | |
973 | ||
974 | /* protects the irq masks */ | |
975 | spinlock_t irq_lock; | |
976 | ||
9ee32fea DV |
977 | /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */ |
978 | struct pm_qos_request pm_qos; | |
979 | ||
f4c956ad | 980 | /* DPIO indirect register protection */ |
09153000 | 981 | struct mutex dpio_lock; |
f4c956ad DV |
982 | |
983 | /** Cached value of IMR to avoid reads in updating the bitfield */ | |
f4c956ad DV |
984 | u32 irq_mask; |
985 | u32 gt_irq_mask; | |
f4c956ad | 986 | |
f4c956ad | 987 | struct work_struct hotplug_work; |
52d7eced | 988 | bool enable_hotplug_processing; |
b543fb04 EE |
989 | struct { |
990 | unsigned long hpd_last_jiffies; | |
991 | int hpd_cnt; | |
992 | enum { | |
993 | HPD_ENABLED = 0, | |
994 | HPD_DISABLED = 1, | |
995 | HPD_MARK_DISABLED = 2 | |
996 | } hpd_mark; | |
997 | } hpd_stats[HPD_NUM_PINS]; | |
142e2398 | 998 | u32 hpd_event_bits; |
ac4c16c5 | 999 | struct timer_list hotplug_reenable_timer; |
f4c956ad | 1000 | |
f4c956ad | 1001 | int num_pch_pll; |
7f1f3851 | 1002 | int num_plane; |
f4c956ad | 1003 | |
f4c956ad DV |
1004 | unsigned long cfb_size; |
1005 | unsigned int cfb_fb; | |
1006 | enum plane cfb_plane; | |
1007 | int cfb_y; | |
1008 | struct intel_fbc_work *fbc_work; | |
1009 | ||
1010 | struct intel_opregion opregion; | |
41aa3448 | 1011 | struct intel_vbt_data vbt; |
f4c956ad DV |
1012 | |
1013 | /* overlay */ | |
1014 | struct intel_overlay *overlay; | |
2c6602df | 1015 | unsigned int sprite_scaling_enabled; |
f4c956ad | 1016 | |
31ad8ec6 JN |
1017 | /* backlight */ |
1018 | struct { | |
1019 | int level; | |
1020 | bool enabled; | |
8ba2d185 | 1021 | spinlock_t lock; /* bl registers and the above bl fields */ |
31ad8ec6 JN |
1022 | struct backlight_device *device; |
1023 | } backlight; | |
1024 | ||
f4c956ad | 1025 | /* LVDS info */ |
f4c956ad DV |
1026 | struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ |
1027 | struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ | |
f4c956ad DV |
1028 | bool no_aux_handshake; |
1029 | ||
f4c956ad DV |
1030 | struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */ |
1031 | int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */ | |
1032 | int num_fence_regs; /* 8 on pre-965, 16 otherwise */ | |
1033 | ||
1034 | unsigned int fsb_freq, mem_freq, is_ddr3; | |
1035 | ||
f4c956ad DV |
1036 | struct workqueue_struct *wq; |
1037 | ||
1038 | /* Display functions */ | |
1039 | struct drm_i915_display_funcs display; | |
1040 | ||
1041 | /* PCH chipset type */ | |
1042 | enum intel_pch pch_type; | |
17a303ec | 1043 | unsigned short pch_id; |
f4c956ad DV |
1044 | |
1045 | unsigned long quirks; | |
1046 | ||
b8efb17b ZR |
1047 | enum modeset_restore modeset_restore; |
1048 | struct mutex modeset_restore_lock; | |
673a394b | 1049 | |
5d4545ae BW |
1050 | struct i915_gtt gtt; |
1051 | ||
4b5aed62 | 1052 | struct i915_gem_mm mm; |
8781342d | 1053 | |
8781342d DV |
1054 | /* Kernel Modesetting */ |
1055 | ||
9b9d172d | 1056 | struct sdvo_device_mapping sdvo_mappings[2]; |
652c393a | 1057 | |
27f8227b JB |
1058 | struct drm_crtc *plane_to_crtc_mapping[3]; |
1059 | struct drm_crtc *pipe_to_crtc_mapping[3]; | |
6b95a207 KH |
1060 | wait_queue_head_t pending_flip_queue; |
1061 | ||
ee7b9f93 | 1062 | struct intel_pch_pll pch_plls[I915_NUM_PLLS]; |
6441ab5f | 1063 | struct intel_ddi_plls ddi_plls; |
ee7b9f93 | 1064 | |
652c393a JB |
1065 | /* Reclocking support */ |
1066 | bool render_reclock_avail; | |
1067 | bool lvds_downclock_avail; | |
18f9ed12 ZY |
1068 | /* indicates the reduced downclock for LVDS*/ |
1069 | int lvds_downclock; | |
652c393a | 1070 | u16 orig_clock; |
f97108d1 | 1071 | |
c4804411 | 1072 | bool mchbar_need_disable; |
f97108d1 | 1073 | |
a4da4fa4 DV |
1074 | struct intel_l3_parity l3_parity; |
1075 | ||
c6a828d3 | 1076 | /* gen6+ rps state */ |
c85aa885 | 1077 | struct intel_gen6_power_mgmt rps; |
c6a828d3 | 1078 | |
20e4d407 DV |
1079 | /* ilk-only ips/rps state. Everything in here is protected by the global |
1080 | * mchdev_lock in intel_pm.c */ | |
c85aa885 | 1081 | struct intel_ilk_power_mgmt ips; |
b5e50c3f JB |
1082 | |
1083 | enum no_fbc_reason no_fbc_reason; | |
38651674 | 1084 | |
20bf377e JB |
1085 | struct drm_mm_node *compressed_fb; |
1086 | struct drm_mm_node *compressed_llb; | |
34dc4d44 | 1087 | |
99584db3 | 1088 | struct i915_gpu_error gpu_error; |
ae681d96 | 1089 | |
c9cddffc JB |
1090 | struct drm_i915_gem_object *vlv_pctx; |
1091 | ||
8be48d92 DA |
1092 | /* list of fbdev register on this device */ |
1093 | struct intel_fbdev *fbdev; | |
e953fd7b | 1094 | |
073f34d9 JB |
1095 | /* |
1096 | * The console may be contended at resume, but we don't | |
1097 | * want it to block on it. | |
1098 | */ | |
1099 | struct work_struct console_resume_work; | |
1100 | ||
e953fd7b | 1101 | struct drm_property *broadcast_rgb_property; |
3f43c48d | 1102 | struct drm_property *force_audio_property; |
e3689190 | 1103 | |
254f965c BW |
1104 | bool hw_contexts_disabled; |
1105 | uint32_t hw_context_size; | |
f4c956ad | 1106 | |
3e68320e | 1107 | u32 fdi_rx_config; |
68d18ad7 | 1108 | |
f4c956ad | 1109 | struct i915_suspend_saved_registers regfile; |
231f42a4 DV |
1110 | |
1111 | /* Old dri1 support infrastructure, beware the dragons ya fools entering | |
1112 | * here! */ | |
1113 | struct i915_dri1_state dri1; | |
1da177e4 LT |
1114 | } drm_i915_private_t; |
1115 | ||
b4519513 CW |
1116 | /* Iterate over initialised rings */ |
1117 | #define for_each_ring(ring__, dev_priv__, i__) \ | |
1118 | for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \ | |
1119 | if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__))) | |
1120 | ||
b1d7e4b4 WF |
1121 | enum hdmi_force_audio { |
1122 | HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */ | |
1123 | HDMI_AUDIO_OFF, /* force turn off HDMI audio */ | |
1124 | HDMI_AUDIO_AUTO, /* trust EDID */ | |
1125 | HDMI_AUDIO_ON, /* force turn on HDMI audio */ | |
1126 | }; | |
1127 | ||
ed2f3452 CW |
1128 | #define I915_GTT_RESERVED ((struct drm_mm_node *)0x1) |
1129 | ||
37e680a1 CW |
1130 | struct drm_i915_gem_object_ops { |
1131 | /* Interface between the GEM object and its backing storage. | |
1132 | * get_pages() is called once prior to the use of the associated set | |
1133 | * of pages before to binding them into the GTT, and put_pages() is | |
1134 | * called after we no longer need them. As we expect there to be | |
1135 | * associated cost with migrating pages between the backing storage | |
1136 | * and making them available for the GPU (e.g. clflush), we may hold | |
1137 | * onto the pages after they are no longer referenced by the GPU | |
1138 | * in case they may be used again shortly (for example migrating the | |
1139 | * pages to a different memory domain within the GTT). put_pages() | |
1140 | * will therefore most likely be called when the object itself is | |
1141 | * being released or under memory pressure (where we attempt to | |
1142 | * reap pages for the shrinker). | |
1143 | */ | |
1144 | int (*get_pages)(struct drm_i915_gem_object *); | |
1145 | void (*put_pages)(struct drm_i915_gem_object *); | |
1146 | }; | |
1147 | ||
673a394b | 1148 | struct drm_i915_gem_object { |
c397b908 | 1149 | struct drm_gem_object base; |
673a394b | 1150 | |
37e680a1 CW |
1151 | const struct drm_i915_gem_object_ops *ops; |
1152 | ||
673a394b EA |
1153 | /** Current space allocated to this object in the GTT, if any. */ |
1154 | struct drm_mm_node *gtt_space; | |
c1ad11fc CW |
1155 | /** Stolen memory for this object, instead of being backed by shmem. */ |
1156 | struct drm_mm_node *stolen; | |
93a37f20 | 1157 | struct list_head gtt_list; |
673a394b | 1158 | |
65ce3027 | 1159 | /** This object's place on the active/inactive lists */ |
69dc4987 CW |
1160 | struct list_head ring_list; |
1161 | struct list_head mm_list; | |
432e58ed CW |
1162 | /** This object's place in the batchbuffer or on the eviction list */ |
1163 | struct list_head exec_list; | |
673a394b EA |
1164 | |
1165 | /** | |
65ce3027 CW |
1166 | * This is set if the object is on the active lists (has pending |
1167 | * rendering and so a non-zero seqno), and is not set if it i s on | |
1168 | * inactive (ready to be unbound) list. | |
673a394b | 1169 | */ |
0206e353 | 1170 | unsigned int active:1; |
673a394b EA |
1171 | |
1172 | /** | |
1173 | * This is set if the object has been written to since last bound | |
1174 | * to the GTT | |
1175 | */ | |
0206e353 | 1176 | unsigned int dirty:1; |
778c3544 DV |
1177 | |
1178 | /** | |
1179 | * Fence register bits (if any) for this object. Will be set | |
1180 | * as needed when mapped into the GTT. | |
1181 | * Protected by dev->struct_mutex. | |
778c3544 | 1182 | */ |
4b9de737 | 1183 | signed int fence_reg:I915_MAX_NUM_FENCE_BITS; |
778c3544 | 1184 | |
778c3544 DV |
1185 | /** |
1186 | * Advice: are the backing pages purgeable? | |
1187 | */ | |
0206e353 | 1188 | unsigned int madv:2; |
778c3544 | 1189 | |
778c3544 DV |
1190 | /** |
1191 | * Current tiling mode for the object. | |
1192 | */ | |
0206e353 | 1193 | unsigned int tiling_mode:2; |
5d82e3e6 CW |
1194 | /** |
1195 | * Whether the tiling parameters for the currently associated fence | |
1196 | * register have changed. Note that for the purposes of tracking | |
1197 | * tiling changes we also treat the unfenced register, the register | |
1198 | * slot that the object occupies whilst it executes a fenced | |
1199 | * command (such as BLT on gen2/3), as a "fence". | |
1200 | */ | |
1201 | unsigned int fence_dirty:1; | |
778c3544 DV |
1202 | |
1203 | /** How many users have pinned this object in GTT space. The following | |
1204 | * users can each hold at most one reference: pwrite/pread, pin_ioctl | |
1205 | * (via user_pin_count), execbuffer (objects are not allowed multiple | |
1206 | * times for the same batchbuffer), and the framebuffer code. When | |
1207 | * switching/pageflipping, the framebuffer code has at most two buffers | |
1208 | * pinned per crtc. | |
1209 | * | |
1210 | * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3 | |
1211 | * bits with absolutely no headroom. So use 4 bits. */ | |
0206e353 | 1212 | unsigned int pin_count:4; |
778c3544 | 1213 | #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf |
673a394b | 1214 | |
75e9e915 DV |
1215 | /** |
1216 | * Is the object at the current location in the gtt mappable and | |
1217 | * fenceable? Used to avoid costly recalculations. | |
1218 | */ | |
0206e353 | 1219 | unsigned int map_and_fenceable:1; |
75e9e915 | 1220 | |
fb7d516a DV |
1221 | /** |
1222 | * Whether the current gtt mapping needs to be mappable (and isn't just | |
1223 | * mappable by accident). Track pin and fault separate for a more | |
1224 | * accurate mappable working set. | |
1225 | */ | |
0206e353 AJ |
1226 | unsigned int fault_mappable:1; |
1227 | unsigned int pin_mappable:1; | |
fb7d516a | 1228 | |
caea7476 CW |
1229 | /* |
1230 | * Is the GPU currently using a fence to access this buffer, | |
1231 | */ | |
1232 | unsigned int pending_fenced_gpu_access:1; | |
1233 | unsigned int fenced_gpu_access:1; | |
1234 | ||
93dfb40c CW |
1235 | unsigned int cache_level:2; |
1236 | ||
7bddb01f | 1237 | unsigned int has_aliasing_ppgtt_mapping:1; |
74898d7e | 1238 | unsigned int has_global_gtt_mapping:1; |
9da3da66 | 1239 | unsigned int has_dma_mapping:1; |
7bddb01f | 1240 | |
9da3da66 | 1241 | struct sg_table *pages; |
a5570178 | 1242 | int pages_pin_count; |
673a394b | 1243 | |
1286ff73 | 1244 | /* prime dma-buf support */ |
9a70cc2a DA |
1245 | void *dma_buf_vmapping; |
1246 | int vmapping_count; | |
1247 | ||
67731b87 CW |
1248 | /** |
1249 | * Used for performing relocations during execbuffer insertion. | |
1250 | */ | |
1251 | struct hlist_node exec_node; | |
1252 | unsigned long exec_handle; | |
6fe4f140 | 1253 | struct drm_i915_gem_exec_object2 *exec_entry; |
67731b87 | 1254 | |
673a394b EA |
1255 | /** |
1256 | * Current offset of the object in GTT space. | |
1257 | * | |
1258 | * This is the same as gtt_space->start | |
1259 | */ | |
1260 | uint32_t gtt_offset; | |
e67b8ce1 | 1261 | |
caea7476 CW |
1262 | struct intel_ring_buffer *ring; |
1263 | ||
1c293ea3 | 1264 | /** Breadcrumb of last rendering to the buffer. */ |
0201f1ec CW |
1265 | uint32_t last_read_seqno; |
1266 | uint32_t last_write_seqno; | |
caea7476 CW |
1267 | /** Breadcrumb of last fenced GPU access to the buffer. */ |
1268 | uint32_t last_fenced_seqno; | |
673a394b | 1269 | |
778c3544 | 1270 | /** Current tiling stride for the object, if it's tiled. */ |
de151cf6 | 1271 | uint32_t stride; |
673a394b | 1272 | |
280b713b | 1273 | /** Record of address bit 17 of each page at last unbind. */ |
d312ec25 | 1274 | unsigned long *bit_17; |
280b713b | 1275 | |
79e53945 JB |
1276 | /** User space pin count and filp owning the pin */ |
1277 | uint32_t user_pin_count; | |
1278 | struct drm_file *pin_filp; | |
71acb5eb DA |
1279 | |
1280 | /** for phy allocated objects */ | |
1281 | struct drm_i915_gem_phys_object *phys_obj; | |
673a394b | 1282 | }; |
b45305fc | 1283 | #define to_gem_object(obj) (&((struct drm_i915_gem_object *)(obj))->base) |
673a394b | 1284 | |
62b8b215 | 1285 | #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base) |
23010e43 | 1286 | |
673a394b EA |
1287 | /** |
1288 | * Request queue structure. | |
1289 | * | |
1290 | * The request queue allows us to note sequence numbers that have been emitted | |
1291 | * and may be associated with active buffers to be retired. | |
1292 | * | |
1293 | * By keeping this list, we can avoid having to do questionable | |
1294 | * sequence-number comparisons on buffer last_rendering_seqnos, and associate | |
1295 | * an emission time with seqnos for tracking how far ahead of the GPU we are. | |
1296 | */ | |
1297 | struct drm_i915_gem_request { | |
852835f3 ZN |
1298 | /** On Which ring this request was generated */ |
1299 | struct intel_ring_buffer *ring; | |
1300 | ||
673a394b EA |
1301 | /** GEM sequence number associated with this request. */ |
1302 | uint32_t seqno; | |
1303 | ||
a71d8d94 CW |
1304 | /** Postion in the ringbuffer of the end of the request */ |
1305 | u32 tail; | |
1306 | ||
0e50e96b MK |
1307 | /** Context related to this request */ |
1308 | struct i915_hw_context *ctx; | |
1309 | ||
673a394b EA |
1310 | /** Time at which this request was emitted, in jiffies. */ |
1311 | unsigned long emitted_jiffies; | |
1312 | ||
b962442e | 1313 | /** global list entry for this request */ |
673a394b | 1314 | struct list_head list; |
b962442e | 1315 | |
f787a5f5 | 1316 | struct drm_i915_file_private *file_priv; |
b962442e EA |
1317 | /** file_priv list entry for this request */ |
1318 | struct list_head client_list; | |
673a394b EA |
1319 | }; |
1320 | ||
1321 | struct drm_i915_file_private { | |
1322 | struct { | |
99057c81 | 1323 | spinlock_t lock; |
b962442e | 1324 | struct list_head request_list; |
673a394b | 1325 | } mm; |
40521054 | 1326 | struct idr context_idr; |
673a394b EA |
1327 | }; |
1328 | ||
cae5852d ZN |
1329 | #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info) |
1330 | ||
1331 | #define IS_I830(dev) ((dev)->pci_device == 0x3577) | |
1332 | #define IS_845G(dev) ((dev)->pci_device == 0x2562) | |
1333 | #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x) | |
1334 | #define IS_I865G(dev) ((dev)->pci_device == 0x2572) | |
1335 | #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g) | |
1336 | #define IS_I915GM(dev) ((dev)->pci_device == 0x2592) | |
1337 | #define IS_I945G(dev) ((dev)->pci_device == 0x2772) | |
1338 | #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm) | |
1339 | #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater) | |
1340 | #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline) | |
1341 | #define IS_GM45(dev) ((dev)->pci_device == 0x2A42) | |
1342 | #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x) | |
1343 | #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001) | |
1344 | #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011) | |
1345 | #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview) | |
1346 | #define IS_G33(dev) (INTEL_INFO(dev)->is_g33) | |
1347 | #define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042) | |
1348 | #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046) | |
4b65177b | 1349 | #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge) |
8ab43976 JB |
1350 | #define IS_IVB_GT1(dev) ((dev)->pci_device == 0x0156 || \ |
1351 | (dev)->pci_device == 0x0152 || \ | |
1352 | (dev)->pci_device == 0x015a) | |
6547fbdb DV |
1353 | #define IS_SNB_GT1(dev) ((dev)->pci_device == 0x0102 || \ |
1354 | (dev)->pci_device == 0x0106 || \ | |
1355 | (dev)->pci_device == 0x010A) | |
70a3eb7a | 1356 | #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview) |
4cae9ae0 | 1357 | #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell) |
cae5852d | 1358 | #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) |
d567b07f PZ |
1359 | #define IS_ULT(dev) (IS_HASWELL(dev) && \ |
1360 | ((dev)->pci_device & 0xFF00) == 0x0A00) | |
cae5852d | 1361 | |
85436696 JB |
1362 | /* |
1363 | * The genX designation typically refers to the render engine, so render | |
1364 | * capability related checks should use IS_GEN, while display and other checks | |
1365 | * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular | |
1366 | * chips, etc.). | |
1367 | */ | |
cae5852d ZN |
1368 | #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2) |
1369 | #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3) | |
1370 | #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4) | |
1371 | #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5) | |
1372 | #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6) | |
85436696 | 1373 | #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7) |
cae5852d ZN |
1374 | |
1375 | #define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring) | |
1376 | #define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring) | |
f72a1183 | 1377 | #define HAS_VEBOX(dev) (INTEL_INFO(dev)->has_vebox_ring) |
3d29b842 | 1378 | #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc) |
cae5852d ZN |
1379 | #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws) |
1380 | ||
254f965c | 1381 | #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6) |
93553609 | 1382 | #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >=6 && !IS_VALLEYVIEW(dev)) |
1d2a314c | 1383 | |
05394f39 | 1384 | #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay) |
cae5852d ZN |
1385 | #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical) |
1386 | ||
b45305fc DV |
1387 | /* Early gen2 have a totally busted CS tlb and require pinned batches. */ |
1388 | #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev)) | |
1389 | ||
cae5852d ZN |
1390 | /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte |
1391 | * rows, which changed the alignment requirements and fence programming. | |
1392 | */ | |
1393 | #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \ | |
1394 | IS_I915GM(dev))) | |
1395 | #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) | |
1396 | #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev)) | |
1397 | #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev)) | |
1398 | #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev)) | |
1399 | #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv) | |
1400 | #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug) | |
1401 | /* dsparb controlled by hw only */ | |
1402 | #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev)) | |
1403 | ||
1404 | #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2) | |
1405 | #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr) | |
1406 | #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc) | |
cae5852d | 1407 | |
eceae481 | 1408 | #define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5) |
cae5852d | 1409 | |
dd93be58 | 1410 | #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi) |
86d52df6 | 1411 | #define HAS_POWER_WELL(dev) (IS_HASWELL(dev)) |
30568c45 | 1412 | #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg) |
affa9354 | 1413 | |
17a303ec PZ |
1414 | #define INTEL_PCH_DEVICE_ID_MASK 0xff00 |
1415 | #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00 | |
1416 | #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00 | |
1417 | #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00 | |
1418 | #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00 | |
1419 | #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00 | |
1420 | ||
cae5852d | 1421 | #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type) |
eb877ebf | 1422 | #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT) |
cae5852d ZN |
1423 | #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT) |
1424 | #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX) | |
40c7ead9 | 1425 | #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP) |
45e6e3a1 | 1426 | #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE) |
cae5852d | 1427 | |
b7884eb4 DV |
1428 | #define HAS_FORCE_WAKE(dev) (INTEL_INFO(dev)->has_force_wake) |
1429 | ||
f27b9265 | 1430 | #define HAS_L3_GPU_CACHE(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) |
e1ef7cc2 | 1431 | |
c8735b0c BW |
1432 | #define GT_FREQUENCY_MULTIPLIER 50 |
1433 | ||
05394f39 CW |
1434 | #include "i915_trace.h" |
1435 | ||
83b7f9ac ED |
1436 | /** |
1437 | * RC6 is a special power stage which allows the GPU to enter an very | |
1438 | * low-voltage mode when idle, using down to 0V while at this stage. This | |
1439 | * stage is entered automatically when the GPU is idle when RC6 support is | |
1440 | * enabled, and as soon as new workload arises GPU wakes up automatically as well. | |
1441 | * | |
1442 | * There are different RC6 modes available in Intel GPU, which differentiate | |
1443 | * among each other with the latency required to enter and leave RC6 and | |
1444 | * voltage consumed by the GPU in different states. | |
1445 | * | |
1446 | * The combination of the following flags define which states GPU is allowed | |
1447 | * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and | |
1448 | * RC6pp is deepest RC6. Their support by hardware varies according to the | |
1449 | * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one | |
1450 | * which brings the most power savings; deeper states save more power, but | |
1451 | * require higher latency to switch to and wake up. | |
1452 | */ | |
1453 | #define INTEL_RC6_ENABLE (1<<0) | |
1454 | #define INTEL_RC6p_ENABLE (1<<1) | |
1455 | #define INTEL_RC6pp_ENABLE (1<<2) | |
1456 | ||
c153f45f | 1457 | extern struct drm_ioctl_desc i915_ioctls[]; |
b3a83639 | 1458 | extern int i915_max_ioctl; |
a35d9d3c BW |
1459 | extern unsigned int i915_fbpercrtc __always_unused; |
1460 | extern int i915_panel_ignore_lid __read_mostly; | |
1461 | extern unsigned int i915_powersave __read_mostly; | |
f45b5557 | 1462 | extern int i915_semaphores __read_mostly; |
a35d9d3c | 1463 | extern unsigned int i915_lvds_downclock __read_mostly; |
121d527a | 1464 | extern int i915_lvds_channel_mode __read_mostly; |
4415e63b | 1465 | extern int i915_panel_use_ssc __read_mostly; |
a35d9d3c | 1466 | extern int i915_vbt_sdvo_panel_type __read_mostly; |
c0f372b3 | 1467 | extern int i915_enable_rc6 __read_mostly; |
4415e63b | 1468 | extern int i915_enable_fbc __read_mostly; |
a35d9d3c | 1469 | extern bool i915_enable_hangcheck __read_mostly; |
650dc07e | 1470 | extern int i915_enable_ppgtt __read_mostly; |
0a3af268 | 1471 | extern unsigned int i915_preliminary_hw_support __read_mostly; |
2124b72e | 1472 | extern int i915_disable_power_well __read_mostly; |
b3a83639 | 1473 | |
6a9ee8af DA |
1474 | extern int i915_suspend(struct drm_device *dev, pm_message_t state); |
1475 | extern int i915_resume(struct drm_device *dev); | |
7c1c2871 DA |
1476 | extern int i915_master_create(struct drm_device *dev, struct drm_master *master); |
1477 | extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master); | |
1478 | ||
1da177e4 | 1479 | /* i915_dma.c */ |
d05c617e | 1480 | void i915_update_dri1_breadcrumb(struct drm_device *dev); |
84b1fd10 | 1481 | extern void i915_kernel_lost_context(struct drm_device * dev); |
22eae947 | 1482 | extern int i915_driver_load(struct drm_device *, unsigned long flags); |
ba8bbcf6 | 1483 | extern int i915_driver_unload(struct drm_device *); |
673a394b | 1484 | extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv); |
84b1fd10 | 1485 | extern void i915_driver_lastclose(struct drm_device * dev); |
6c340eac EA |
1486 | extern void i915_driver_preclose(struct drm_device *dev, |
1487 | struct drm_file *file_priv); | |
673a394b EA |
1488 | extern void i915_driver_postclose(struct drm_device *dev, |
1489 | struct drm_file *file_priv); | |
84b1fd10 | 1490 | extern int i915_driver_device_is_agp(struct drm_device * dev); |
c43b5634 | 1491 | #ifdef CONFIG_COMPAT |
0d6aa60b DA |
1492 | extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, |
1493 | unsigned long arg); | |
c43b5634 | 1494 | #endif |
673a394b | 1495 | extern int i915_emit_box(struct drm_device *dev, |
c4e7a414 CW |
1496 | struct drm_clip_rect *box, |
1497 | int DR1, int DR4); | |
8e96d9c4 | 1498 | extern int intel_gpu_reset(struct drm_device *dev); |
d4b8bb2a | 1499 | extern int i915_reset(struct drm_device *dev); |
7648fa99 JB |
1500 | extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv); |
1501 | extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv); | |
1502 | extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv); | |
1503 | extern void i915_update_gfx_val(struct drm_i915_private *dev_priv); | |
1504 | ||
073f34d9 | 1505 | extern void intel_console_resume(struct work_struct *work); |
af6061af | 1506 | |
1da177e4 | 1507 | /* i915_irq.c */ |
f65d9421 | 1508 | void i915_hangcheck_elapsed(unsigned long data); |
527f9e90 | 1509 | void i915_handle_error(struct drm_device *dev, bool wedged); |
1da177e4 | 1510 | |
f71d4af4 | 1511 | extern void intel_irq_init(struct drm_device *dev); |
20afbda2 | 1512 | extern void intel_hpd_init(struct drm_device *dev); |
990bbdad | 1513 | extern void intel_gt_init(struct drm_device *dev); |
16995a9f | 1514 | extern void intel_gt_reset(struct drm_device *dev); |
b1f14ad0 | 1515 | |
742cbee8 DV |
1516 | void i915_error_state_free(struct kref *error_ref); |
1517 | ||
7c463586 KP |
1518 | void |
1519 | i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); | |
1520 | ||
1521 | void | |
1522 | i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); | |
1523 | ||
3bd3c932 CW |
1524 | #ifdef CONFIG_DEBUG_FS |
1525 | extern void i915_destroy_error_state(struct drm_device *dev); | |
1526 | #else | |
1527 | #define i915_destroy_error_state(x) | |
1528 | #endif | |
1529 | ||
7c463586 | 1530 | |
673a394b EA |
1531 | /* i915_gem.c */ |
1532 | int i915_gem_init_ioctl(struct drm_device *dev, void *data, | |
1533 | struct drm_file *file_priv); | |
1534 | int i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
1535 | struct drm_file *file_priv); | |
1536 | int i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
1537 | struct drm_file *file_priv); | |
1538 | int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
1539 | struct drm_file *file_priv); | |
1540 | int i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
1541 | struct drm_file *file_priv); | |
de151cf6 JB |
1542 | int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, |
1543 | struct drm_file *file_priv); | |
673a394b EA |
1544 | int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, |
1545 | struct drm_file *file_priv); | |
1546 | int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
1547 | struct drm_file *file_priv); | |
1548 | int i915_gem_execbuffer(struct drm_device *dev, void *data, | |
1549 | struct drm_file *file_priv); | |
76446cac JB |
1550 | int i915_gem_execbuffer2(struct drm_device *dev, void *data, |
1551 | struct drm_file *file_priv); | |
673a394b EA |
1552 | int i915_gem_pin_ioctl(struct drm_device *dev, void *data, |
1553 | struct drm_file *file_priv); | |
1554 | int i915_gem_unpin_ioctl(struct drm_device *dev, void *data, | |
1555 | struct drm_file *file_priv); | |
1556 | int i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
1557 | struct drm_file *file_priv); | |
199adf40 BW |
1558 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, |
1559 | struct drm_file *file); | |
1560 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, | |
1561 | struct drm_file *file); | |
673a394b EA |
1562 | int i915_gem_throttle_ioctl(struct drm_device *dev, void *data, |
1563 | struct drm_file *file_priv); | |
3ef94daa CW |
1564 | int i915_gem_madvise_ioctl(struct drm_device *dev, void *data, |
1565 | struct drm_file *file_priv); | |
673a394b EA |
1566 | int i915_gem_entervt_ioctl(struct drm_device *dev, void *data, |
1567 | struct drm_file *file_priv); | |
1568 | int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, | |
1569 | struct drm_file *file_priv); | |
1570 | int i915_gem_set_tiling(struct drm_device *dev, void *data, | |
1571 | struct drm_file *file_priv); | |
1572 | int i915_gem_get_tiling(struct drm_device *dev, void *data, | |
1573 | struct drm_file *file_priv); | |
5a125c3c EA |
1574 | int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, |
1575 | struct drm_file *file_priv); | |
23ba4fd0 BW |
1576 | int i915_gem_wait_ioctl(struct drm_device *dev, void *data, |
1577 | struct drm_file *file_priv); | |
673a394b | 1578 | void i915_gem_load(struct drm_device *dev); |
42dcedd4 CW |
1579 | void *i915_gem_object_alloc(struct drm_device *dev); |
1580 | void i915_gem_object_free(struct drm_i915_gem_object *obj); | |
673a394b | 1581 | int i915_gem_init_object(struct drm_gem_object *obj); |
37e680a1 CW |
1582 | void i915_gem_object_init(struct drm_i915_gem_object *obj, |
1583 | const struct drm_i915_gem_object_ops *ops); | |
05394f39 CW |
1584 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
1585 | size_t size); | |
673a394b | 1586 | void i915_gem_free_object(struct drm_gem_object *obj); |
42dcedd4 | 1587 | |
2021746e CW |
1588 | int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj, |
1589 | uint32_t alignment, | |
86a1ee26 CW |
1590 | bool map_and_fenceable, |
1591 | bool nonblocking); | |
05394f39 | 1592 | void i915_gem_object_unpin(struct drm_i915_gem_object *obj); |
2021746e | 1593 | int __must_check i915_gem_object_unbind(struct drm_i915_gem_object *obj); |
dd624afd | 1594 | int i915_gem_object_put_pages(struct drm_i915_gem_object *obj); |
05394f39 | 1595 | void i915_gem_release_mmap(struct drm_i915_gem_object *obj); |
673a394b | 1596 | void i915_gem_lastclose(struct drm_device *dev); |
f787a5f5 | 1597 | |
37e680a1 | 1598 | int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj); |
9da3da66 CW |
1599 | static inline struct page *i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n) |
1600 | { | |
67d5a50c ID |
1601 | struct sg_page_iter sg_iter; |
1602 | ||
1603 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, n) | |
2db76d7c | 1604 | return sg_page_iter_page(&sg_iter); |
67d5a50c ID |
1605 | |
1606 | return NULL; | |
9da3da66 | 1607 | } |
a5570178 CW |
1608 | static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj) |
1609 | { | |
1610 | BUG_ON(obj->pages == NULL); | |
1611 | obj->pages_pin_count++; | |
1612 | } | |
1613 | static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj) | |
1614 | { | |
1615 | BUG_ON(obj->pages_pin_count == 0); | |
1616 | obj->pages_pin_count--; | |
1617 | } | |
1618 | ||
54cf91dc | 1619 | int __must_check i915_mutex_lock_interruptible(struct drm_device *dev); |
2911a35b BW |
1620 | int i915_gem_object_sync(struct drm_i915_gem_object *obj, |
1621 | struct intel_ring_buffer *to); | |
54cf91dc | 1622 | void i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, |
9d773091 | 1623 | struct intel_ring_buffer *ring); |
54cf91dc | 1624 | |
ff72145b DA |
1625 | int i915_gem_dumb_create(struct drm_file *file_priv, |
1626 | struct drm_device *dev, | |
1627 | struct drm_mode_create_dumb *args); | |
1628 | int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev, | |
1629 | uint32_t handle, uint64_t *offset); | |
1630 | int i915_gem_dumb_destroy(struct drm_file *file_priv, struct drm_device *dev, | |
0206e353 | 1631 | uint32_t handle); |
f787a5f5 CW |
1632 | /** |
1633 | * Returns true if seq1 is later than seq2. | |
1634 | */ | |
1635 | static inline bool | |
1636 | i915_seqno_passed(uint32_t seq1, uint32_t seq2) | |
1637 | { | |
1638 | return (int32_t)(seq1 - seq2) >= 0; | |
1639 | } | |
1640 | ||
fca26bb4 MK |
1641 | int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno); |
1642 | int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno); | |
06d98131 | 1643 | int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj); |
d9e86c0e | 1644 | int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj); |
2021746e | 1645 | |
9a5a53b3 | 1646 | static inline bool |
1690e1eb CW |
1647 | i915_gem_object_pin_fence(struct drm_i915_gem_object *obj) |
1648 | { | |
1649 | if (obj->fence_reg != I915_FENCE_REG_NONE) { | |
1650 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
1651 | dev_priv->fence_regs[obj->fence_reg].pin_count++; | |
9a5a53b3 CW |
1652 | return true; |
1653 | } else | |
1654 | return false; | |
1690e1eb CW |
1655 | } |
1656 | ||
1657 | static inline void | |
1658 | i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj) | |
1659 | { | |
1660 | if (obj->fence_reg != I915_FENCE_REG_NONE) { | |
1661 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
1662 | dev_priv->fence_regs[obj->fence_reg].pin_count--; | |
1663 | } | |
1664 | } | |
1665 | ||
b09a1fec | 1666 | void i915_gem_retire_requests(struct drm_device *dev); |
a71d8d94 | 1667 | void i915_gem_retire_requests_ring(struct intel_ring_buffer *ring); |
33196ded | 1668 | int __must_check i915_gem_check_wedge(struct i915_gpu_error *error, |
d6b2c790 | 1669 | bool interruptible); |
1f83fee0 DV |
1670 | static inline bool i915_reset_in_progress(struct i915_gpu_error *error) |
1671 | { | |
1672 | return unlikely(atomic_read(&error->reset_counter) | |
1673 | & I915_RESET_IN_PROGRESS_FLAG); | |
1674 | } | |
1675 | ||
1676 | static inline bool i915_terminally_wedged(struct i915_gpu_error *error) | |
1677 | { | |
1678 | return atomic_read(&error->reset_counter) == I915_WEDGED; | |
1679 | } | |
a71d8d94 | 1680 | |
069efc1d | 1681 | void i915_gem_reset(struct drm_device *dev); |
05394f39 | 1682 | void i915_gem_clflush_object(struct drm_i915_gem_object *obj); |
2021746e CW |
1683 | int __must_check i915_gem_object_set_domain(struct drm_i915_gem_object *obj, |
1684 | uint32_t read_domains, | |
1685 | uint32_t write_domain); | |
a8198eea | 1686 | int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj); |
1070a42b | 1687 | int __must_check i915_gem_init(struct drm_device *dev); |
f691e2f4 | 1688 | int __must_check i915_gem_init_hw(struct drm_device *dev); |
b9524a1e | 1689 | void i915_gem_l3_remap(struct drm_device *dev); |
f691e2f4 | 1690 | void i915_gem_init_swizzling(struct drm_device *dev); |
79e53945 | 1691 | void i915_gem_cleanup_ringbuffer(struct drm_device *dev); |
b2da9fe5 | 1692 | int __must_check i915_gpu_idle(struct drm_device *dev); |
2021746e | 1693 | int __must_check i915_gem_idle(struct drm_device *dev); |
3bb73aba CW |
1694 | int i915_add_request(struct intel_ring_buffer *ring, |
1695 | struct drm_file *file, | |
acb868d3 | 1696 | u32 *seqno); |
199b2bc2 BW |
1697 | int __must_check i915_wait_seqno(struct intel_ring_buffer *ring, |
1698 | uint32_t seqno); | |
de151cf6 | 1699 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf); |
2021746e CW |
1700 | int __must_check |
1701 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, | |
1702 | bool write); | |
1703 | int __must_check | |
dabdfe02 CW |
1704 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write); |
1705 | int __must_check | |
2da3b9b9 CW |
1706 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
1707 | u32 alignment, | |
2021746e | 1708 | struct intel_ring_buffer *pipelined); |
71acb5eb | 1709 | int i915_gem_attach_phys_object(struct drm_device *dev, |
05394f39 | 1710 | struct drm_i915_gem_object *obj, |
6eeefaf3 CW |
1711 | int id, |
1712 | int align); | |
71acb5eb | 1713 | void i915_gem_detach_phys_object(struct drm_device *dev, |
05394f39 | 1714 | struct drm_i915_gem_object *obj); |
71acb5eb | 1715 | void i915_gem_free_all_phys_object(struct drm_device *dev); |
05394f39 | 1716 | void i915_gem_release(struct drm_device *dev, struct drm_file *file); |
673a394b | 1717 | |
0fa87796 ID |
1718 | uint32_t |
1719 | i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode); | |
467cffba | 1720 | uint32_t |
d865110c ID |
1721 | i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size, |
1722 | int tiling_mode, bool fenced); | |
467cffba | 1723 | |
e4ffd173 CW |
1724 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
1725 | enum i915_cache_level cache_level); | |
1726 | ||
1286ff73 DV |
1727 | struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev, |
1728 | struct dma_buf *dma_buf); | |
1729 | ||
1730 | struct dma_buf *i915_gem_prime_export(struct drm_device *dev, | |
1731 | struct drm_gem_object *gem_obj, int flags); | |
1732 | ||
254f965c BW |
1733 | /* i915_gem_context.c */ |
1734 | void i915_gem_context_init(struct drm_device *dev); | |
1735 | void i915_gem_context_fini(struct drm_device *dev); | |
254f965c | 1736 | void i915_gem_context_close(struct drm_device *dev, struct drm_file *file); |
e0556841 BW |
1737 | int i915_switch_context(struct intel_ring_buffer *ring, |
1738 | struct drm_file *file, int to_id); | |
dce3271b MK |
1739 | void i915_gem_context_free(struct kref *ctx_ref); |
1740 | static inline void i915_gem_context_reference(struct i915_hw_context *ctx) | |
1741 | { | |
1742 | kref_get(&ctx->ref); | |
1743 | } | |
1744 | ||
1745 | static inline void i915_gem_context_unreference(struct i915_hw_context *ctx) | |
1746 | { | |
1747 | kref_put(&ctx->ref, i915_gem_context_free); | |
1748 | } | |
1749 | ||
84624813 BW |
1750 | int i915_gem_context_create_ioctl(struct drm_device *dev, void *data, |
1751 | struct drm_file *file); | |
1752 | int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data, | |
1753 | struct drm_file *file); | |
1286ff73 | 1754 | |
76aaf220 | 1755 | /* i915_gem_gtt.c */ |
1d2a314c | 1756 | void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev); |
7bddb01f DV |
1757 | void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt, |
1758 | struct drm_i915_gem_object *obj, | |
1759 | enum i915_cache_level cache_level); | |
1760 | void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt, | |
1761 | struct drm_i915_gem_object *obj); | |
1d2a314c | 1762 | |
76aaf220 | 1763 | void i915_gem_restore_gtt_mappings(struct drm_device *dev); |
74163907 DV |
1764 | int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj); |
1765 | void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj, | |
e4ffd173 | 1766 | enum i915_cache_level cache_level); |
05394f39 | 1767 | void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj); |
74163907 | 1768 | void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj); |
d7e5008f BW |
1769 | void i915_gem_init_global_gtt(struct drm_device *dev); |
1770 | void i915_gem_setup_global_gtt(struct drm_device *dev, unsigned long start, | |
1771 | unsigned long mappable_end, unsigned long end); | |
e76e9aeb | 1772 | int i915_gem_gtt_init(struct drm_device *dev); |
d09105c6 | 1773 | static inline void i915_gem_chipset_flush(struct drm_device *dev) |
e76e9aeb BW |
1774 | { |
1775 | if (INTEL_INFO(dev)->gen < 6) | |
1776 | intel_gtt_chipset_flush(); | |
1777 | } | |
1778 | ||
76aaf220 | 1779 | |
b47eb4a2 | 1780 | /* i915_gem_evict.c */ |
2021746e | 1781 | int __must_check i915_gem_evict_something(struct drm_device *dev, int min_size, |
42d6ab48 CW |
1782 | unsigned alignment, |
1783 | unsigned cache_level, | |
86a1ee26 CW |
1784 | bool mappable, |
1785 | bool nonblock); | |
6c085a72 | 1786 | int i915_gem_evict_everything(struct drm_device *dev); |
b47eb4a2 | 1787 | |
9797fbfb CW |
1788 | /* i915_gem_stolen.c */ |
1789 | int i915_gem_init_stolen(struct drm_device *dev); | |
11be49eb CW |
1790 | int i915_gem_stolen_setup_compression(struct drm_device *dev, int size); |
1791 | void i915_gem_stolen_cleanup_compression(struct drm_device *dev); | |
9797fbfb | 1792 | void i915_gem_cleanup_stolen(struct drm_device *dev); |
0104fdbb CW |
1793 | struct drm_i915_gem_object * |
1794 | i915_gem_object_create_stolen(struct drm_device *dev, u32 size); | |
866d12b4 CW |
1795 | struct drm_i915_gem_object * |
1796 | i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev, | |
1797 | u32 stolen_offset, | |
1798 | u32 gtt_offset, | |
1799 | u32 size); | |
0104fdbb | 1800 | void i915_gem_object_release_stolen(struct drm_i915_gem_object *obj); |
9797fbfb | 1801 | |
673a394b | 1802 | /* i915_gem_tiling.c */ |
e9b73c67 CW |
1803 | inline static bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj) |
1804 | { | |
1805 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; | |
1806 | ||
1807 | return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && | |
1808 | obj->tiling_mode != I915_TILING_NONE; | |
1809 | } | |
1810 | ||
673a394b | 1811 | void i915_gem_detect_bit_6_swizzle(struct drm_device *dev); |
05394f39 CW |
1812 | void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj); |
1813 | void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj); | |
673a394b EA |
1814 | |
1815 | /* i915_gem_debug.c */ | |
05394f39 | 1816 | void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len, |
673a394b | 1817 | const char *where, uint32_t mark); |
23bc5982 CW |
1818 | #if WATCH_LISTS |
1819 | int i915_verify_lists(struct drm_device *dev); | |
673a394b | 1820 | #else |
23bc5982 | 1821 | #define i915_verify_lists(dev) 0 |
673a394b | 1822 | #endif |
05394f39 CW |
1823 | void i915_gem_object_check_coherency(struct drm_i915_gem_object *obj, |
1824 | int handle); | |
1825 | void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len, | |
673a394b | 1826 | const char *where, uint32_t mark); |
1da177e4 | 1827 | |
2017263e | 1828 | /* i915_debugfs.c */ |
27c202ad BG |
1829 | int i915_debugfs_init(struct drm_minor *minor); |
1830 | void i915_debugfs_cleanup(struct drm_minor *minor); | |
edc3d884 MK |
1831 | __printf(2, 3) |
1832 | void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...); | |
2017263e | 1833 | |
317c35d1 JB |
1834 | /* i915_suspend.c */ |
1835 | extern int i915_save_state(struct drm_device *dev); | |
1836 | extern int i915_restore_state(struct drm_device *dev); | |
0a3e67a4 | 1837 | |
d8157a36 DV |
1838 | /* i915_ums.c */ |
1839 | void i915_save_display_reg(struct drm_device *dev); | |
1840 | void i915_restore_display_reg(struct drm_device *dev); | |
317c35d1 | 1841 | |
0136db58 BW |
1842 | /* i915_sysfs.c */ |
1843 | void i915_setup_sysfs(struct drm_device *dev_priv); | |
1844 | void i915_teardown_sysfs(struct drm_device *dev_priv); | |
1845 | ||
f899fc64 CW |
1846 | /* intel_i2c.c */ |
1847 | extern int intel_setup_gmbus(struct drm_device *dev); | |
1848 | extern void intel_teardown_gmbus(struct drm_device *dev); | |
8f375e10 | 1849 | static inline bool intel_gmbus_is_port_valid(unsigned port) |
3bd7d909 | 1850 | { |
2ed06c93 | 1851 | return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD); |
3bd7d909 DK |
1852 | } |
1853 | ||
1854 | extern struct i2c_adapter *intel_gmbus_get_adapter( | |
1855 | struct drm_i915_private *dev_priv, unsigned port); | |
e957d772 CW |
1856 | extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed); |
1857 | extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit); | |
8f375e10 | 1858 | static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter) |
b8232e90 CW |
1859 | { |
1860 | return container_of(adapter, struct intel_gmbus, adapter)->force_bit; | |
1861 | } | |
f899fc64 CW |
1862 | extern void intel_i2c_reset(struct drm_device *dev); |
1863 | ||
3b617967 | 1864 | /* intel_opregion.c */ |
44834a67 CW |
1865 | extern int intel_opregion_setup(struct drm_device *dev); |
1866 | #ifdef CONFIG_ACPI | |
1867 | extern void intel_opregion_init(struct drm_device *dev); | |
1868 | extern void intel_opregion_fini(struct drm_device *dev); | |
3b617967 | 1869 | extern void intel_opregion_asle_intr(struct drm_device *dev); |
65e082c9 | 1870 | #else |
44834a67 CW |
1871 | static inline void intel_opregion_init(struct drm_device *dev) { return; } |
1872 | static inline void intel_opregion_fini(struct drm_device *dev) { return; } | |
3b617967 | 1873 | static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; } |
65e082c9 | 1874 | #endif |
8ee1c3db | 1875 | |
723bfd70 JB |
1876 | /* intel_acpi.c */ |
1877 | #ifdef CONFIG_ACPI | |
1878 | extern void intel_register_dsm_handler(void); | |
1879 | extern void intel_unregister_dsm_handler(void); | |
1880 | #else | |
1881 | static inline void intel_register_dsm_handler(void) { return; } | |
1882 | static inline void intel_unregister_dsm_handler(void) { return; } | |
1883 | #endif /* CONFIG_ACPI */ | |
1884 | ||
79e53945 | 1885 | /* modesetting */ |
f817586c | 1886 | extern void intel_modeset_init_hw(struct drm_device *dev); |
7d708ee4 | 1887 | extern void intel_modeset_suspend_hw(struct drm_device *dev); |
79e53945 | 1888 | extern void intel_modeset_init(struct drm_device *dev); |
2c7111db | 1889 | extern void intel_modeset_gem_init(struct drm_device *dev); |
79e53945 | 1890 | extern void intel_modeset_cleanup(struct drm_device *dev); |
28d52043 | 1891 | extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state); |
45e2b5f6 DV |
1892 | extern void intel_modeset_setup_hw_state(struct drm_device *dev, |
1893 | bool force_restore); | |
44cec740 | 1894 | extern void i915_redisable_vga(struct drm_device *dev); |
ee5382ae | 1895 | extern bool intel_fbc_enabled(struct drm_device *dev); |
43a9539f | 1896 | extern void intel_disable_fbc(struct drm_device *dev); |
7648fa99 | 1897 | extern bool ironlake_set_drps(struct drm_device *dev, u8 val); |
dde86e2d | 1898 | extern void intel_init_pch_refclk(struct drm_device *dev); |
3b8d8d91 | 1899 | extern void gen6_set_rps(struct drm_device *dev, u8 val); |
0a073b84 JB |
1900 | extern void valleyview_set_rps(struct drm_device *dev, u8 val); |
1901 | extern int valleyview_rps_max_freq(struct drm_i915_private *dev_priv); | |
1902 | extern int valleyview_rps_min_freq(struct drm_i915_private *dev_priv); | |
0206e353 AJ |
1903 | extern void intel_detect_pch(struct drm_device *dev); |
1904 | extern int intel_trans_dp_port_sel(struct drm_crtc *crtc); | |
0136db58 | 1905 | extern int intel_enable_rc6(const struct drm_device *dev); |
3bad0781 | 1906 | |
2911a35b | 1907 | extern bool i915_semaphore_is_enabled(struct drm_device *dev); |
c0c7babc BW |
1908 | int i915_reg_read_ioctl(struct drm_device *dev, void *data, |
1909 | struct drm_file *file); | |
575155a9 | 1910 | |
6ef3d427 | 1911 | /* overlay */ |
3bd3c932 | 1912 | #ifdef CONFIG_DEBUG_FS |
6ef3d427 | 1913 | extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev); |
edc3d884 MK |
1914 | extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e, |
1915 | struct intel_overlay_error_state *error); | |
c4a1d9e4 CW |
1916 | |
1917 | extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev); | |
edc3d884 | 1918 | extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e, |
c4a1d9e4 CW |
1919 | struct drm_device *dev, |
1920 | struct intel_display_error_state *error); | |
3bd3c932 | 1921 | #endif |
6ef3d427 | 1922 | |
b7287d80 BW |
1923 | /* On SNB platform, before reading ring registers forcewake bit |
1924 | * must be set to prevent GT core from power down and stale values being | |
1925 | * returned. | |
1926 | */ | |
fcca7926 BW |
1927 | void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv); |
1928 | void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv); | |
67a3744f | 1929 | int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv); |
b7287d80 | 1930 | |
42c0526c BW |
1931 | int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val); |
1932 | int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val); | |
59de0813 JN |
1933 | |
1934 | /* intel_sideband.c */ | |
64936258 JN |
1935 | u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr); |
1936 | void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val); | |
1937 | u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr); | |
ae99258f JN |
1938 | u32 vlv_dpio_read(struct drm_i915_private *dev_priv, int reg); |
1939 | void vlv_dpio_write(struct drm_i915_private *dev_priv, int reg, u32 val); | |
59de0813 JN |
1940 | u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg, |
1941 | enum intel_sbi_destination destination); | |
1942 | void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value, | |
1943 | enum intel_sbi_destination destination); | |
0a073b84 | 1944 | |
855ba3be JB |
1945 | int vlv_gpu_freq(int ddr_freq, int val); |
1946 | int vlv_freq_opcode(int ddr_freq, int val); | |
42c0526c | 1947 | |
5f75377d | 1948 | #define __i915_read(x, y) \ |
f7000883 | 1949 | u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg); |
fcca7926 | 1950 | |
5f75377d KP |
1951 | __i915_read(8, b) |
1952 | __i915_read(16, w) | |
1953 | __i915_read(32, l) | |
1954 | __i915_read(64, q) | |
1955 | #undef __i915_read | |
1956 | ||
1957 | #define __i915_write(x, y) \ | |
f7000883 AK |
1958 | void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val); |
1959 | ||
5f75377d KP |
1960 | __i915_write(8, b) |
1961 | __i915_write(16, w) | |
1962 | __i915_write(32, l) | |
1963 | __i915_write(64, q) | |
1964 | #undef __i915_write | |
1965 | ||
1966 | #define I915_READ8(reg) i915_read8(dev_priv, (reg)) | |
1967 | #define I915_WRITE8(reg, val) i915_write8(dev_priv, (reg), (val)) | |
1968 | ||
1969 | #define I915_READ16(reg) i915_read16(dev_priv, (reg)) | |
1970 | #define I915_WRITE16(reg, val) i915_write16(dev_priv, (reg), (val)) | |
1971 | #define I915_READ16_NOTRACE(reg) readw(dev_priv->regs + (reg)) | |
1972 | #define I915_WRITE16_NOTRACE(reg, val) writew(val, dev_priv->regs + (reg)) | |
1973 | ||
1974 | #define I915_READ(reg) i915_read32(dev_priv, (reg)) | |
1975 | #define I915_WRITE(reg, val) i915_write32(dev_priv, (reg), (val)) | |
cae5852d ZN |
1976 | #define I915_READ_NOTRACE(reg) readl(dev_priv->regs + (reg)) |
1977 | #define I915_WRITE_NOTRACE(reg, val) writel(val, dev_priv->regs + (reg)) | |
5f75377d KP |
1978 | |
1979 | #define I915_WRITE64(reg, val) i915_write64(dev_priv, (reg), (val)) | |
1980 | #define I915_READ64(reg) i915_read64(dev_priv, (reg)) | |
cae5852d ZN |
1981 | |
1982 | #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg) | |
1983 | #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg) | |
1984 | ||
55bc60db VS |
1985 | /* "Broadcast RGB" property */ |
1986 | #define INTEL_BROADCAST_RGB_AUTO 0 | |
1987 | #define INTEL_BROADCAST_RGB_FULL 1 | |
1988 | #define INTEL_BROADCAST_RGB_LIMITED 2 | |
ba4f01a3 | 1989 | |
766aa1c4 VS |
1990 | static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev) |
1991 | { | |
1992 | if (HAS_PCH_SPLIT(dev)) | |
1993 | return CPU_VGACNTRL; | |
1994 | else if (IS_VALLEYVIEW(dev)) | |
1995 | return VLV_VGACNTRL; | |
1996 | else | |
1997 | return VGACNTRL; | |
1998 | } | |
1999 | ||
2bb4629a VS |
2000 | static inline void __user *to_user_ptr(u64 address) |
2001 | { | |
2002 | return (void __user *)(uintptr_t)address; | |
2003 | } | |
2004 | ||
1da177e4 | 2005 | #endif |