Commit | Line | Data |
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1da177e4 LT |
1 | /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- |
2 | */ | |
0d6aa60b | 3 | /* |
bc54fd1a | 4 | * |
1da177e4 LT |
5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
6 | * All Rights Reserved. | |
bc54fd1a DA |
7 | * |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the | |
10 | * "Software"), to deal in the Software without restriction, including | |
11 | * without limitation the rights to use, copy, modify, merge, publish, | |
12 | * distribute, sub license, and/or sell copies of the Software, and to | |
13 | * permit persons to whom the Software is furnished to do so, subject to | |
14 | * the following conditions: | |
15 | * | |
16 | * The above copyright notice and this permission notice (including the | |
17 | * next paragraph) shall be included in all copies or substantial portions | |
18 | * of the Software. | |
19 | * | |
20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
27 | * | |
0d6aa60b | 28 | */ |
1da177e4 LT |
29 | |
30 | #ifndef _I915_DRV_H_ | |
31 | #define _I915_DRV_H_ | |
32 | ||
585fb111 | 33 | #include "i915_reg.h" |
79e53945 | 34 | #include "intel_bios.h" |
8187a2b7 | 35 | #include "intel_ringbuffer.h" |
0839ccb8 | 36 | #include <linux/io-mapping.h> |
f899fc64 | 37 | #include <linux/i2c.h> |
0ade6386 | 38 | #include <drm/intel-gtt.h> |
aaa6fd2a | 39 | #include <linux/backlight.h> |
585fb111 | 40 | |
1da177e4 LT |
41 | /* General customization: |
42 | */ | |
43 | ||
44 | #define DRIVER_AUTHOR "Tungsten Graphics, Inc." | |
45 | ||
46 | #define DRIVER_NAME "i915" | |
47 | #define DRIVER_DESC "Intel Graphics" | |
673a394b | 48 | #define DRIVER_DATE "20080730" |
1da177e4 | 49 | |
317c35d1 JB |
50 | enum pipe { |
51 | PIPE_A = 0, | |
52 | PIPE_B, | |
9db4a9c7 JB |
53 | PIPE_C, |
54 | I915_MAX_PIPES | |
317c35d1 | 55 | }; |
9db4a9c7 | 56 | #define pipe_name(p) ((p) + 'A') |
317c35d1 | 57 | |
80824003 JB |
58 | enum plane { |
59 | PLANE_A = 0, | |
60 | PLANE_B, | |
9db4a9c7 | 61 | PLANE_C, |
80824003 | 62 | }; |
9db4a9c7 | 63 | #define plane_name(p) ((p) + 'A') |
52440211 | 64 | |
62fdfeaf EA |
65 | #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT)) |
66 | ||
9db4a9c7 JB |
67 | #define for_each_pipe(p) for ((p) = 0; (p) < dev_priv->num_pipe; (p)++) |
68 | ||
1da177e4 LT |
69 | /* Interface history: |
70 | * | |
71 | * 1.1: Original. | |
0d6aa60b DA |
72 | * 1.2: Add Power Management |
73 | * 1.3: Add vblank support | |
de227f5f | 74 | * 1.4: Fix cmdbuffer path, add heap destroy |
702880f2 | 75 | * 1.5: Add vblank pipe configuration |
2228ed67 MCA |
76 | * 1.6: - New ioctl for scheduling buffer swaps on vertical blank |
77 | * - Support vertical blank on secondary display pipe | |
1da177e4 LT |
78 | */ |
79 | #define DRIVER_MAJOR 1 | |
2228ed67 | 80 | #define DRIVER_MINOR 6 |
1da177e4 LT |
81 | #define DRIVER_PATCHLEVEL 0 |
82 | ||
673a394b | 83 | #define WATCH_COHERENCY 0 |
23bc5982 | 84 | #define WATCH_LISTS 0 |
673a394b | 85 | |
71acb5eb DA |
86 | #define I915_GEM_PHYS_CURSOR_0 1 |
87 | #define I915_GEM_PHYS_CURSOR_1 2 | |
88 | #define I915_GEM_PHYS_OVERLAY_REGS 3 | |
89 | #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS) | |
90 | ||
91 | struct drm_i915_gem_phys_object { | |
92 | int id; | |
93 | struct page **page_list; | |
94 | drm_dma_handle_t *handle; | |
05394f39 | 95 | struct drm_i915_gem_object *cur_obj; |
71acb5eb DA |
96 | }; |
97 | ||
1da177e4 LT |
98 | struct mem_block { |
99 | struct mem_block *next; | |
100 | struct mem_block *prev; | |
101 | int start; | |
102 | int size; | |
6c340eac | 103 | struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */ |
1da177e4 LT |
104 | }; |
105 | ||
0a3e67a4 JB |
106 | struct opregion_header; |
107 | struct opregion_acpi; | |
108 | struct opregion_swsci; | |
109 | struct opregion_asle; | |
8d715f00 | 110 | struct drm_i915_private; |
0a3e67a4 | 111 | |
8ee1c3db MG |
112 | struct intel_opregion { |
113 | struct opregion_header *header; | |
114 | struct opregion_acpi *acpi; | |
115 | struct opregion_swsci *swsci; | |
116 | struct opregion_asle *asle; | |
44834a67 | 117 | void *vbt; |
01fe9dbd | 118 | u32 __iomem *lid_state; |
8ee1c3db | 119 | }; |
44834a67 | 120 | #define OPREGION_SIZE (8*1024) |
8ee1c3db | 121 | |
6ef3d427 CW |
122 | struct intel_overlay; |
123 | struct intel_overlay_error_state; | |
124 | ||
7c1c2871 DA |
125 | struct drm_i915_master_private { |
126 | drm_local_map_t *sarea; | |
127 | struct _drm_i915_sarea *sarea_priv; | |
128 | }; | |
de151cf6 | 129 | #define I915_FENCE_REG_NONE -1 |
4b9de737 DV |
130 | #define I915_MAX_NUM_FENCES 16 |
131 | /* 16 fences + sign bit for FENCE_REG_NONE */ | |
132 | #define I915_MAX_NUM_FENCE_BITS 5 | |
de151cf6 JB |
133 | |
134 | struct drm_i915_fence_reg { | |
007cc8ac | 135 | struct list_head lru_list; |
caea7476 | 136 | struct drm_i915_gem_object *obj; |
d9e86c0e | 137 | uint32_t setup_seqno; |
1690e1eb | 138 | int pin_count; |
de151cf6 | 139 | }; |
7c1c2871 | 140 | |
9b9d172d | 141 | struct sdvo_device_mapping { |
e957d772 | 142 | u8 initialized; |
9b9d172d | 143 | u8 dvo_port; |
144 | u8 slave_addr; | |
145 | u8 dvo_wiring; | |
e957d772 | 146 | u8 i2c_pin; |
b1083333 | 147 | u8 ddc_pin; |
9b9d172d | 148 | }; |
149 | ||
c4a1d9e4 CW |
150 | struct intel_display_error_state; |
151 | ||
63eeaf38 JB |
152 | struct drm_i915_error_state { |
153 | u32 eir; | |
154 | u32 pgtbl_er; | |
9db4a9c7 | 155 | u32 pipestat[I915_MAX_PIPES]; |
c1cd90ed DV |
156 | u32 tail[I915_NUM_RINGS]; |
157 | u32 head[I915_NUM_RINGS]; | |
d27b1e0e DV |
158 | u32 ipeir[I915_NUM_RINGS]; |
159 | u32 ipehr[I915_NUM_RINGS]; | |
160 | u32 instdone[I915_NUM_RINGS]; | |
161 | u32 acthd[I915_NUM_RINGS]; | |
1d8f38f4 | 162 | u32 error; /* gen6+ */ |
c1cd90ed DV |
163 | u32 instpm[I915_NUM_RINGS]; |
164 | u32 instps[I915_NUM_RINGS]; | |
63eeaf38 | 165 | u32 instdone1; |
d27b1e0e | 166 | u32 seqno[I915_NUM_RINGS]; |
9df30794 | 167 | u64 bbaddr; |
c1cd90ed | 168 | u32 faddr[I915_NUM_RINGS]; |
4b9de737 | 169 | u64 fence[I915_MAX_NUM_FENCES]; |
63eeaf38 | 170 | struct timeval time; |
9df30794 CW |
171 | struct drm_i915_error_object { |
172 | int page_count; | |
173 | u32 gtt_offset; | |
174 | u32 *pages[0]; | |
e2f973d5 | 175 | } *ringbuffer[I915_NUM_RINGS], *batchbuffer[I915_NUM_RINGS]; |
9df30794 | 176 | struct drm_i915_error_buffer { |
a779e5ab | 177 | u32 size; |
9df30794 CW |
178 | u32 name; |
179 | u32 seqno; | |
180 | u32 gtt_offset; | |
181 | u32 read_domains; | |
182 | u32 write_domain; | |
4b9de737 | 183 | s32 fence_reg:I915_MAX_NUM_FENCE_BITS; |
9df30794 CW |
184 | s32 pinned:2; |
185 | u32 tiling:2; | |
186 | u32 dirty:1; | |
187 | u32 purgeable:1; | |
e5c65260 | 188 | u32 ring:4; |
93dfb40c | 189 | u32 cache_level:2; |
c724e8a9 CW |
190 | } *active_bo, *pinned_bo; |
191 | u32 active_bo_count, pinned_bo_count; | |
6ef3d427 | 192 | struct intel_overlay_error_state *overlay; |
c4a1d9e4 | 193 | struct intel_display_error_state *display; |
63eeaf38 JB |
194 | }; |
195 | ||
e70236a8 JB |
196 | struct drm_i915_display_funcs { |
197 | void (*dpms)(struct drm_crtc *crtc, int mode); | |
ee5382ae | 198 | bool (*fbc_enabled)(struct drm_device *dev); |
e70236a8 JB |
199 | void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval); |
200 | void (*disable_fbc)(struct drm_device *dev); | |
201 | int (*get_display_clock_speed)(struct drm_device *dev); | |
202 | int (*get_fifo_size)(struct drm_device *dev, int plane); | |
d210246a | 203 | void (*update_wm)(struct drm_device *dev); |
b840d907 JB |
204 | void (*update_sprite_wm)(struct drm_device *dev, int pipe, |
205 | uint32_t sprite_width, int pixel_size); | |
f564048e EA |
206 | int (*crtc_mode_set)(struct drm_crtc *crtc, |
207 | struct drm_display_mode *mode, | |
208 | struct drm_display_mode *adjusted_mode, | |
209 | int x, int y, | |
210 | struct drm_framebuffer *old_fb); | |
e0dac65e WF |
211 | void (*write_eld)(struct drm_connector *connector, |
212 | struct drm_crtc *crtc); | |
674cf967 | 213 | void (*fdi_link_train)(struct drm_crtc *crtc); |
6067aaea | 214 | void (*init_clock_gating)(struct drm_device *dev); |
645c62a5 | 215 | void (*init_pch_clock_gating)(struct drm_device *dev); |
8c9f3aaf JB |
216 | int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc, |
217 | struct drm_framebuffer *fb, | |
218 | struct drm_i915_gem_object *obj); | |
17638cd6 JB |
219 | int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb, |
220 | int x, int y); | |
8d715f00 KP |
221 | void (*force_wake_get)(struct drm_i915_private *dev_priv); |
222 | void (*force_wake_put)(struct drm_i915_private *dev_priv); | |
e70236a8 JB |
223 | /* clock updates for mode set */ |
224 | /* cursor updates */ | |
225 | /* render clock increase/decrease */ | |
226 | /* display clock increase/decrease */ | |
227 | /* pll clock increase/decrease */ | |
e70236a8 JB |
228 | }; |
229 | ||
cfdf1fa2 | 230 | struct intel_device_info { |
c96c3a8c | 231 | u8 gen; |
0206e353 AJ |
232 | u8 is_mobile:1; |
233 | u8 is_i85x:1; | |
234 | u8 is_i915g:1; | |
235 | u8 is_i945gm:1; | |
236 | u8 is_g33:1; | |
237 | u8 need_gfx_hws:1; | |
238 | u8 is_g4x:1; | |
239 | u8 is_pineview:1; | |
240 | u8 is_broadwater:1; | |
241 | u8 is_crestline:1; | |
242 | u8 is_ivybridge:1; | |
243 | u8 has_fbc:1; | |
244 | u8 has_pipe_cxsr:1; | |
245 | u8 has_hotplug:1; | |
246 | u8 cursor_needs_physical:1; | |
247 | u8 has_overlay:1; | |
248 | u8 overlay_needs_physical:1; | |
249 | u8 supports_tv:1; | |
250 | u8 has_bsd_ring:1; | |
251 | u8 has_blt_ring:1; | |
3d29b842 | 252 | u8 has_llc:1; |
cfdf1fa2 KH |
253 | }; |
254 | ||
b5e50c3f | 255 | enum no_fbc_reason { |
bed4a673 | 256 | FBC_NO_OUTPUT, /* no outputs enabled to compress */ |
b5e50c3f JB |
257 | FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */ |
258 | FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */ | |
259 | FBC_MODE_TOO_LARGE, /* mode too large for compression */ | |
260 | FBC_BAD_PLANE, /* fbc not supported on plane */ | |
261 | FBC_NOT_TILED, /* buffer not tiled */ | |
9c928d16 | 262 | FBC_MULTIPLE_PIPES, /* more than one pipe active */ |
c1a9f047 | 263 | FBC_MODULE_PARAM, |
b5e50c3f JB |
264 | }; |
265 | ||
3bad0781 ZW |
266 | enum intel_pch { |
267 | PCH_IBX, /* Ibexpeak PCH */ | |
268 | PCH_CPT, /* Cougarpoint PCH */ | |
269 | }; | |
270 | ||
b690e96c | 271 | #define QUIRK_PIPEA_FORCE (1<<0) |
435793df | 272 | #define QUIRK_LVDS_SSC_DISABLE (1<<1) |
b690e96c | 273 | |
8be48d92 | 274 | struct intel_fbdev; |
1630fe75 | 275 | struct intel_fbc_work; |
38651674 | 276 | |
1da177e4 | 277 | typedef struct drm_i915_private { |
673a394b EA |
278 | struct drm_device *dev; |
279 | ||
cfdf1fa2 KH |
280 | const struct intel_device_info *info; |
281 | ||
ac5c4e76 | 282 | int has_gem; |
72bfa19c | 283 | int relative_constants_mode; |
ac5c4e76 | 284 | |
3043c60c | 285 | void __iomem *regs; |
95736720 | 286 | u32 gt_fifo_count; |
1da177e4 | 287 | |
f899fc64 CW |
288 | struct intel_gmbus { |
289 | struct i2c_adapter adapter; | |
e957d772 CW |
290 | struct i2c_adapter *force_bit; |
291 | u32 reg0; | |
f899fc64 CW |
292 | } *gmbus; |
293 | ||
ec2a4c3f | 294 | struct pci_dev *bridge_dev; |
1ec14ad3 | 295 | struct intel_ring_buffer ring[I915_NUM_RINGS]; |
6f392d54 | 296 | uint32_t next_seqno; |
1da177e4 | 297 | |
9c8da5eb | 298 | drm_dma_handle_t *status_page_dmah; |
0a3e67a4 | 299 | uint32_t counter; |
dc7a9319 | 300 | drm_local_map_t hws_map; |
05394f39 CW |
301 | struct drm_i915_gem_object *pwrctx; |
302 | struct drm_i915_gem_object *renderctx; | |
1da177e4 | 303 | |
d7658989 JB |
304 | struct resource mch_res; |
305 | ||
a6b54f3f | 306 | unsigned int cpp; |
1da177e4 LT |
307 | int back_offset; |
308 | int front_offset; | |
309 | int current_page; | |
310 | int page_flipping; | |
1da177e4 | 311 | |
1da177e4 | 312 | atomic_t irq_received; |
1ec14ad3 CW |
313 | |
314 | /* protects the irq masks */ | |
315 | spinlock_t irq_lock; | |
ed4cb414 | 316 | /** Cached value of IMR to avoid reads in updating the bitfield */ |
7c463586 | 317 | u32 pipestat[2]; |
1ec14ad3 CW |
318 | u32 irq_mask; |
319 | u32 gt_irq_mask; | |
320 | u32 pch_irq_mask; | |
1da177e4 | 321 | |
5ca58282 JB |
322 | u32 hotplug_supported_mask; |
323 | struct work_struct hotplug_work; | |
324 | ||
1da177e4 LT |
325 | int tex_lru_log_granularity; |
326 | int allow_batchbuffer; | |
0d6aa60b | 327 | unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds; |
702880f2 | 328 | int vblank_pipe; |
a3524f1b | 329 | int num_pipe; |
a6b54f3f | 330 | |
f65d9421 | 331 | /* For hangcheck timer */ |
576ae4b8 | 332 | #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */ |
f65d9421 BG |
333 | struct timer_list hangcheck_timer; |
334 | int hangcheck_count; | |
335 | uint32_t last_acthd; | |
097354eb DV |
336 | uint32_t last_acthd_bsd; |
337 | uint32_t last_acthd_blt; | |
cbb465e7 CW |
338 | uint32_t last_instdone; |
339 | uint32_t last_instdone1; | |
f65d9421 | 340 | |
80824003 | 341 | unsigned long cfb_size; |
016b9b61 CW |
342 | unsigned int cfb_fb; |
343 | enum plane cfb_plane; | |
bed4a673 | 344 | int cfb_y; |
1630fe75 | 345 | struct intel_fbc_work *fbc_work; |
80824003 | 346 | |
8ee1c3db MG |
347 | struct intel_opregion opregion; |
348 | ||
02e792fb DV |
349 | /* overlay */ |
350 | struct intel_overlay *overlay; | |
b840d907 | 351 | bool sprite_scaling_enabled; |
02e792fb | 352 | |
79e53945 | 353 | /* LVDS info */ |
a9573556 | 354 | int backlight_level; /* restore backlight to this value */ |
47356eb6 | 355 | bool backlight_enabled; |
88631706 ML |
356 | struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ |
357 | struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ | |
79e53945 JB |
358 | |
359 | /* Feature bits from the VBIOS */ | |
95281e35 HE |
360 | unsigned int int_tv_support:1; |
361 | unsigned int lvds_dither:1; | |
362 | unsigned int lvds_vbt:1; | |
363 | unsigned int int_crt_support:1; | |
43565a06 | 364 | unsigned int lvds_use_ssc:1; |
abd06860 | 365 | unsigned int display_clock_mode:1; |
43565a06 | 366 | int lvds_ssc_freq; |
5ceb0f9b | 367 | struct { |
9f0e7ff4 JB |
368 | int rate; |
369 | int lanes; | |
370 | int preemphasis; | |
371 | int vswing; | |
372 | ||
373 | bool initialized; | |
374 | bool support; | |
375 | int bpp; | |
376 | struct edp_power_seq pps; | |
5ceb0f9b | 377 | } edp; |
89667383 | 378 | bool no_aux_handshake; |
79e53945 | 379 | |
c1c7af60 JB |
380 | struct notifier_block lid_notifier; |
381 | ||
f899fc64 | 382 | int crt_ddc_pin; |
4b9de737 | 383 | struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */ |
de151cf6 JB |
384 | int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */ |
385 | int num_fence_regs; /* 8 on pre-965, 16 otherwise */ | |
386 | ||
95534263 | 387 | unsigned int fsb_freq, mem_freq, is_ddr3; |
7662c8bd | 388 | |
63eeaf38 JB |
389 | spinlock_t error_lock; |
390 | struct drm_i915_error_state *first_error; | |
8a905236 | 391 | struct work_struct error_work; |
30dbf0c0 | 392 | struct completion error_completion; |
9c9fe1f8 | 393 | struct workqueue_struct *wq; |
63eeaf38 | 394 | |
e70236a8 JB |
395 | /* Display functions */ |
396 | struct drm_i915_display_funcs display; | |
397 | ||
3bad0781 ZW |
398 | /* PCH chipset type */ |
399 | enum intel_pch pch_type; | |
400 | ||
b690e96c JB |
401 | unsigned long quirks; |
402 | ||
ba8bbcf6 | 403 | /* Register state */ |
c9354c85 | 404 | bool modeset_on_lid; |
ba8bbcf6 JB |
405 | u8 saveLBB; |
406 | u32 saveDSPACNTR; | |
407 | u32 saveDSPBCNTR; | |
e948e994 | 408 | u32 saveDSPARB; |
968b503e | 409 | u32 saveHWS; |
ba8bbcf6 JB |
410 | u32 savePIPEACONF; |
411 | u32 savePIPEBCONF; | |
412 | u32 savePIPEASRC; | |
413 | u32 savePIPEBSRC; | |
414 | u32 saveFPA0; | |
415 | u32 saveFPA1; | |
416 | u32 saveDPLL_A; | |
417 | u32 saveDPLL_A_MD; | |
418 | u32 saveHTOTAL_A; | |
419 | u32 saveHBLANK_A; | |
420 | u32 saveHSYNC_A; | |
421 | u32 saveVTOTAL_A; | |
422 | u32 saveVBLANK_A; | |
423 | u32 saveVSYNC_A; | |
424 | u32 saveBCLRPAT_A; | |
5586c8bc | 425 | u32 saveTRANSACONF; |
42048781 ZW |
426 | u32 saveTRANS_HTOTAL_A; |
427 | u32 saveTRANS_HBLANK_A; | |
428 | u32 saveTRANS_HSYNC_A; | |
429 | u32 saveTRANS_VTOTAL_A; | |
430 | u32 saveTRANS_VBLANK_A; | |
431 | u32 saveTRANS_VSYNC_A; | |
0da3ea12 | 432 | u32 savePIPEASTAT; |
ba8bbcf6 JB |
433 | u32 saveDSPASTRIDE; |
434 | u32 saveDSPASIZE; | |
435 | u32 saveDSPAPOS; | |
585fb111 | 436 | u32 saveDSPAADDR; |
ba8bbcf6 JB |
437 | u32 saveDSPASURF; |
438 | u32 saveDSPATILEOFF; | |
439 | u32 savePFIT_PGM_RATIOS; | |
0eb96d6e | 440 | u32 saveBLC_HIST_CTL; |
ba8bbcf6 JB |
441 | u32 saveBLC_PWM_CTL; |
442 | u32 saveBLC_PWM_CTL2; | |
42048781 ZW |
443 | u32 saveBLC_CPU_PWM_CTL; |
444 | u32 saveBLC_CPU_PWM_CTL2; | |
ba8bbcf6 JB |
445 | u32 saveFPB0; |
446 | u32 saveFPB1; | |
447 | u32 saveDPLL_B; | |
448 | u32 saveDPLL_B_MD; | |
449 | u32 saveHTOTAL_B; | |
450 | u32 saveHBLANK_B; | |
451 | u32 saveHSYNC_B; | |
452 | u32 saveVTOTAL_B; | |
453 | u32 saveVBLANK_B; | |
454 | u32 saveVSYNC_B; | |
455 | u32 saveBCLRPAT_B; | |
5586c8bc | 456 | u32 saveTRANSBCONF; |
42048781 ZW |
457 | u32 saveTRANS_HTOTAL_B; |
458 | u32 saveTRANS_HBLANK_B; | |
459 | u32 saveTRANS_HSYNC_B; | |
460 | u32 saveTRANS_VTOTAL_B; | |
461 | u32 saveTRANS_VBLANK_B; | |
462 | u32 saveTRANS_VSYNC_B; | |
0da3ea12 | 463 | u32 savePIPEBSTAT; |
ba8bbcf6 JB |
464 | u32 saveDSPBSTRIDE; |
465 | u32 saveDSPBSIZE; | |
466 | u32 saveDSPBPOS; | |
585fb111 | 467 | u32 saveDSPBADDR; |
ba8bbcf6 JB |
468 | u32 saveDSPBSURF; |
469 | u32 saveDSPBTILEOFF; | |
585fb111 JB |
470 | u32 saveVGA0; |
471 | u32 saveVGA1; | |
472 | u32 saveVGA_PD; | |
ba8bbcf6 JB |
473 | u32 saveVGACNTRL; |
474 | u32 saveADPA; | |
475 | u32 saveLVDS; | |
585fb111 JB |
476 | u32 savePP_ON_DELAYS; |
477 | u32 savePP_OFF_DELAYS; | |
ba8bbcf6 JB |
478 | u32 saveDVOA; |
479 | u32 saveDVOB; | |
480 | u32 saveDVOC; | |
481 | u32 savePP_ON; | |
482 | u32 savePP_OFF; | |
483 | u32 savePP_CONTROL; | |
585fb111 | 484 | u32 savePP_DIVISOR; |
ba8bbcf6 JB |
485 | u32 savePFIT_CONTROL; |
486 | u32 save_palette_a[256]; | |
487 | u32 save_palette_b[256]; | |
06027f91 | 488 | u32 saveDPFC_CB_BASE; |
ba8bbcf6 JB |
489 | u32 saveFBC_CFB_BASE; |
490 | u32 saveFBC_LL_BASE; | |
491 | u32 saveFBC_CONTROL; | |
492 | u32 saveFBC_CONTROL2; | |
0da3ea12 JB |
493 | u32 saveIER; |
494 | u32 saveIIR; | |
495 | u32 saveIMR; | |
42048781 ZW |
496 | u32 saveDEIER; |
497 | u32 saveDEIMR; | |
498 | u32 saveGTIER; | |
499 | u32 saveGTIMR; | |
500 | u32 saveFDI_RXA_IMR; | |
501 | u32 saveFDI_RXB_IMR; | |
1f84e550 | 502 | u32 saveCACHE_MODE_0; |
1f84e550 | 503 | u32 saveMI_ARB_STATE; |
ba8bbcf6 JB |
504 | u32 saveSWF0[16]; |
505 | u32 saveSWF1[16]; | |
506 | u32 saveSWF2[3]; | |
507 | u8 saveMSR; | |
508 | u8 saveSR[8]; | |
123f794f | 509 | u8 saveGR[25]; |
ba8bbcf6 | 510 | u8 saveAR_INDEX; |
a59e122a | 511 | u8 saveAR[21]; |
ba8bbcf6 | 512 | u8 saveDACMASK; |
a59e122a | 513 | u8 saveCR[37]; |
4b9de737 | 514 | uint64_t saveFENCE[I915_MAX_NUM_FENCES]; |
1fd1c624 EA |
515 | u32 saveCURACNTR; |
516 | u32 saveCURAPOS; | |
517 | u32 saveCURABASE; | |
518 | u32 saveCURBCNTR; | |
519 | u32 saveCURBPOS; | |
520 | u32 saveCURBBASE; | |
521 | u32 saveCURSIZE; | |
a4fc5ed6 KP |
522 | u32 saveDP_B; |
523 | u32 saveDP_C; | |
524 | u32 saveDP_D; | |
525 | u32 savePIPEA_GMCH_DATA_M; | |
526 | u32 savePIPEB_GMCH_DATA_M; | |
527 | u32 savePIPEA_GMCH_DATA_N; | |
528 | u32 savePIPEB_GMCH_DATA_N; | |
529 | u32 savePIPEA_DP_LINK_M; | |
530 | u32 savePIPEB_DP_LINK_M; | |
531 | u32 savePIPEA_DP_LINK_N; | |
532 | u32 savePIPEB_DP_LINK_N; | |
42048781 ZW |
533 | u32 saveFDI_RXA_CTL; |
534 | u32 saveFDI_TXA_CTL; | |
535 | u32 saveFDI_RXB_CTL; | |
536 | u32 saveFDI_TXB_CTL; | |
537 | u32 savePFA_CTL_1; | |
538 | u32 savePFB_CTL_1; | |
539 | u32 savePFA_WIN_SZ; | |
540 | u32 savePFB_WIN_SZ; | |
541 | u32 savePFA_WIN_POS; | |
542 | u32 savePFB_WIN_POS; | |
5586c8bc ZW |
543 | u32 savePCH_DREF_CONTROL; |
544 | u32 saveDISP_ARB_CTL; | |
545 | u32 savePIPEA_DATA_M1; | |
546 | u32 savePIPEA_DATA_N1; | |
547 | u32 savePIPEA_LINK_M1; | |
548 | u32 savePIPEA_LINK_N1; | |
549 | u32 savePIPEB_DATA_M1; | |
550 | u32 savePIPEB_DATA_N1; | |
551 | u32 savePIPEB_LINK_M1; | |
552 | u32 savePIPEB_LINK_N1; | |
b5b72e89 | 553 | u32 saveMCHBAR_RENDER_STANDBY; |
cda2bb78 | 554 | u32 savePCH_PORT_HOTPLUG; |
673a394b EA |
555 | |
556 | struct { | |
19966754 | 557 | /** Bridge to intel-gtt-ko */ |
c64f7ba5 | 558 | const struct intel_gtt *gtt; |
19966754 | 559 | /** Memory allocator for GTT stolen memory */ |
fe669bf8 | 560 | struct drm_mm stolen; |
19966754 | 561 | /** Memory allocator for GTT */ |
673a394b | 562 | struct drm_mm gtt_space; |
93a37f20 DV |
563 | /** List of all objects in gtt_space. Used to restore gtt |
564 | * mappings on resume */ | |
565 | struct list_head gtt_list; | |
bee4a186 CW |
566 | |
567 | /** Usable portion of the GTT for GEM */ | |
568 | unsigned long gtt_start; | |
a6e0aa42 | 569 | unsigned long gtt_mappable_end; |
bee4a186 | 570 | unsigned long gtt_end; |
673a394b | 571 | |
0839ccb8 | 572 | struct io_mapping *gtt_mapping; |
ab657db1 | 573 | int gtt_mtrr; |
0839ccb8 | 574 | |
17250b71 | 575 | struct shrinker inactive_shrinker; |
31169714 | 576 | |
69dc4987 CW |
577 | /** |
578 | * List of objects currently involved in rendering. | |
579 | * | |
580 | * Includes buffers having the contents of their GPU caches | |
581 | * flushed, not necessarily primitives. last_rendering_seqno | |
582 | * represents when the rendering involved will be completed. | |
583 | * | |
584 | * A reference is held on the buffer while on this list. | |
585 | */ | |
586 | struct list_head active_list; | |
587 | ||
673a394b EA |
588 | /** |
589 | * List of objects which are not in the ringbuffer but which | |
590 | * still have a write_domain which needs to be flushed before | |
591 | * unbinding. | |
592 | * | |
ce44b0ea EA |
593 | * last_rendering_seqno is 0 while an object is in this list. |
594 | * | |
673a394b EA |
595 | * A reference is held on the buffer while on this list. |
596 | */ | |
597 | struct list_head flushing_list; | |
598 | ||
599 | /** | |
600 | * LRU list of objects which are not in the ringbuffer and | |
601 | * are ready to unbind, but are still in the GTT. | |
602 | * | |
ce44b0ea EA |
603 | * last_rendering_seqno is 0 while an object is in this list. |
604 | * | |
673a394b EA |
605 | * A reference is not held on the buffer while on this list, |
606 | * as merely being GTT-bound shouldn't prevent its being | |
607 | * freed, and we'll pull it off the list in the free path. | |
608 | */ | |
609 | struct list_head inactive_list; | |
610 | ||
f13d3f73 CW |
611 | /** |
612 | * LRU list of objects which are not in the ringbuffer but | |
613 | * are still pinned in the GTT. | |
614 | */ | |
615 | struct list_head pinned_list; | |
616 | ||
a09ba7fa EA |
617 | /** LRU list of objects with fence regs on them. */ |
618 | struct list_head fence_list; | |
619 | ||
be72615b CW |
620 | /** |
621 | * List of objects currently pending being freed. | |
622 | * | |
623 | * These objects are no longer in use, but due to a signal | |
624 | * we were prevented from freeing them at the appointed time. | |
625 | */ | |
626 | struct list_head deferred_free_list; | |
627 | ||
673a394b EA |
628 | /** |
629 | * We leave the user IRQ off as much as possible, | |
630 | * but this means that requests will finish and never | |
631 | * be retired once the system goes idle. Set a timer to | |
632 | * fire periodically while the ring is running. When it | |
633 | * fires, go retire requests. | |
634 | */ | |
635 | struct delayed_work retire_work; | |
636 | ||
ce453d81 CW |
637 | /** |
638 | * Are we in a non-interruptible section of code like | |
639 | * modesetting? | |
640 | */ | |
641 | bool interruptible; | |
642 | ||
673a394b EA |
643 | /** |
644 | * Flag if the X Server, and thus DRM, is not currently in | |
645 | * control of the device. | |
646 | * | |
647 | * This is set between LeaveVT and EnterVT. It needs to be | |
648 | * replaced with a semaphore. It also needs to be | |
649 | * transitioned away from for kernel modesetting. | |
650 | */ | |
651 | int suspended; | |
652 | ||
653 | /** | |
654 | * Flag if the hardware appears to be wedged. | |
655 | * | |
656 | * This is set when attempts to idle the device timeout. | |
25985edc | 657 | * It prevents command submission from occurring and makes |
673a394b EA |
658 | * every pending request fail |
659 | */ | |
ba1234d1 | 660 | atomic_t wedged; |
673a394b EA |
661 | |
662 | /** Bit 6 swizzling required for X tiling */ | |
663 | uint32_t bit_6_swizzle_x; | |
664 | /** Bit 6 swizzling required for Y tiling */ | |
665 | uint32_t bit_6_swizzle_y; | |
71acb5eb DA |
666 | |
667 | /* storage for physical objects */ | |
668 | struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT]; | |
9220434a | 669 | |
73aa808f | 670 | /* accounting, useful for userland debugging */ |
73aa808f | 671 | size_t gtt_total; |
6299f992 CW |
672 | size_t mappable_gtt_total; |
673 | size_t object_memory; | |
73aa808f | 674 | u32 object_count; |
673a394b | 675 | } mm; |
9b9d172d | 676 | struct sdvo_device_mapping sdvo_mappings[2]; |
a3e17eb8 ZY |
677 | /* indicate whether the LVDS_BORDER should be enabled or not */ |
678 | unsigned int lvds_border_bits; | |
1d8e1c75 CW |
679 | /* Panel fitter placement and size for Ironlake+ */ |
680 | u32 pch_pf_pos, pch_pf_size; | |
652c393a | 681 | |
27f8227b JB |
682 | struct drm_crtc *plane_to_crtc_mapping[3]; |
683 | struct drm_crtc *pipe_to_crtc_mapping[3]; | |
6b95a207 | 684 | wait_queue_head_t pending_flip_queue; |
1afe3e9d | 685 | bool flip_pending_is_done; |
6b95a207 | 686 | |
652c393a JB |
687 | /* Reclocking support */ |
688 | bool render_reclock_avail; | |
689 | bool lvds_downclock_avail; | |
18f9ed12 ZY |
690 | /* indicates the reduced downclock for LVDS*/ |
691 | int lvds_downclock; | |
652c393a JB |
692 | struct work_struct idle_work; |
693 | struct timer_list idle_timer; | |
694 | bool busy; | |
695 | u16 orig_clock; | |
6363ee6f ZY |
696 | int child_dev_num; |
697 | struct child_device_config *child_dev; | |
a2565377 | 698 | struct drm_connector *int_lvds_connector; |
aaa6fd2a | 699 | struct drm_connector *int_edp_connector; |
f97108d1 | 700 | |
c4804411 | 701 | bool mchbar_need_disable; |
f97108d1 | 702 | |
4912d041 BW |
703 | struct work_struct rps_work; |
704 | spinlock_t rps_lock; | |
705 | u32 pm_iir; | |
706 | ||
f97108d1 JB |
707 | u8 cur_delay; |
708 | u8 min_delay; | |
709 | u8 max_delay; | |
7648fa99 JB |
710 | u8 fmax; |
711 | u8 fstart; | |
712 | ||
05394f39 CW |
713 | u64 last_count1; |
714 | unsigned long last_time1; | |
4ed0b577 | 715 | unsigned long chipset_power; |
05394f39 CW |
716 | u64 last_count2; |
717 | struct timespec last_time2; | |
718 | unsigned long gfx_power; | |
719 | int c_m; | |
720 | int r_t; | |
721 | u8 corr; | |
7648fa99 | 722 | spinlock_t *mchdev_lock; |
b5e50c3f JB |
723 | |
724 | enum no_fbc_reason no_fbc_reason; | |
38651674 | 725 | |
20bf377e JB |
726 | struct drm_mm_node *compressed_fb; |
727 | struct drm_mm_node *compressed_llb; | |
34dc4d44 | 728 | |
ae681d96 CW |
729 | unsigned long last_gpu_reset; |
730 | ||
8be48d92 DA |
731 | /* list of fbdev register on this device */ |
732 | struct intel_fbdev *fbdev; | |
e953fd7b | 733 | |
aaa6fd2a MG |
734 | struct backlight_device *backlight; |
735 | ||
e953fd7b | 736 | struct drm_property *broadcast_rgb_property; |
3f43c48d | 737 | struct drm_property *force_audio_property; |
fcca7926 BW |
738 | |
739 | atomic_t forcewake_count; | |
1da177e4 LT |
740 | } drm_i915_private_t; |
741 | ||
93dfb40c CW |
742 | enum i915_cache_level { |
743 | I915_CACHE_NONE, | |
744 | I915_CACHE_LLC, | |
745 | I915_CACHE_LLC_MLC, /* gen6+ */ | |
746 | }; | |
747 | ||
673a394b | 748 | struct drm_i915_gem_object { |
c397b908 | 749 | struct drm_gem_object base; |
673a394b EA |
750 | |
751 | /** Current space allocated to this object in the GTT, if any. */ | |
752 | struct drm_mm_node *gtt_space; | |
93a37f20 | 753 | struct list_head gtt_list; |
673a394b EA |
754 | |
755 | /** This object's place on the active/flushing/inactive lists */ | |
69dc4987 CW |
756 | struct list_head ring_list; |
757 | struct list_head mm_list; | |
99fcb766 DV |
758 | /** This object's place on GPU write list */ |
759 | struct list_head gpu_write_list; | |
432e58ed CW |
760 | /** This object's place in the batchbuffer or on the eviction list */ |
761 | struct list_head exec_list; | |
673a394b EA |
762 | |
763 | /** | |
764 | * This is set if the object is on the active or flushing lists | |
765 | * (has pending rendering), and is not set if it's on inactive (ready | |
766 | * to be unbound). | |
767 | */ | |
0206e353 | 768 | unsigned int active:1; |
673a394b EA |
769 | |
770 | /** | |
771 | * This is set if the object has been written to since last bound | |
772 | * to the GTT | |
773 | */ | |
0206e353 | 774 | unsigned int dirty:1; |
778c3544 | 775 | |
87ca9c8a CW |
776 | /** |
777 | * This is set if the object has been written to since the last | |
778 | * GPU flush. | |
779 | */ | |
0206e353 | 780 | unsigned int pending_gpu_write:1; |
87ca9c8a | 781 | |
778c3544 DV |
782 | /** |
783 | * Fence register bits (if any) for this object. Will be set | |
784 | * as needed when mapped into the GTT. | |
785 | * Protected by dev->struct_mutex. | |
778c3544 | 786 | */ |
4b9de737 | 787 | signed int fence_reg:I915_MAX_NUM_FENCE_BITS; |
778c3544 | 788 | |
778c3544 DV |
789 | /** |
790 | * Advice: are the backing pages purgeable? | |
791 | */ | |
0206e353 | 792 | unsigned int madv:2; |
778c3544 | 793 | |
778c3544 DV |
794 | /** |
795 | * Current tiling mode for the object. | |
796 | */ | |
0206e353 AJ |
797 | unsigned int tiling_mode:2; |
798 | unsigned int tiling_changed:1; | |
778c3544 DV |
799 | |
800 | /** How many users have pinned this object in GTT space. The following | |
801 | * users can each hold at most one reference: pwrite/pread, pin_ioctl | |
802 | * (via user_pin_count), execbuffer (objects are not allowed multiple | |
803 | * times for the same batchbuffer), and the framebuffer code. When | |
804 | * switching/pageflipping, the framebuffer code has at most two buffers | |
805 | * pinned per crtc. | |
806 | * | |
807 | * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3 | |
808 | * bits with absolutely no headroom. So use 4 bits. */ | |
0206e353 | 809 | unsigned int pin_count:4; |
778c3544 | 810 | #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf |
673a394b | 811 | |
75e9e915 DV |
812 | /** |
813 | * Is the object at the current location in the gtt mappable and | |
814 | * fenceable? Used to avoid costly recalculations. | |
815 | */ | |
0206e353 | 816 | unsigned int map_and_fenceable:1; |
75e9e915 | 817 | |
fb7d516a DV |
818 | /** |
819 | * Whether the current gtt mapping needs to be mappable (and isn't just | |
820 | * mappable by accident). Track pin and fault separate for a more | |
821 | * accurate mappable working set. | |
822 | */ | |
0206e353 AJ |
823 | unsigned int fault_mappable:1; |
824 | unsigned int pin_mappable:1; | |
fb7d516a | 825 | |
caea7476 CW |
826 | /* |
827 | * Is the GPU currently using a fence to access this buffer, | |
828 | */ | |
829 | unsigned int pending_fenced_gpu_access:1; | |
830 | unsigned int fenced_gpu_access:1; | |
831 | ||
93dfb40c CW |
832 | unsigned int cache_level:2; |
833 | ||
856fa198 | 834 | struct page **pages; |
673a394b | 835 | |
185cbcb3 DV |
836 | /** |
837 | * DMAR support | |
838 | */ | |
839 | struct scatterlist *sg_list; | |
840 | int num_sg; | |
841 | ||
67731b87 CW |
842 | /** |
843 | * Used for performing relocations during execbuffer insertion. | |
844 | */ | |
845 | struct hlist_node exec_node; | |
846 | unsigned long exec_handle; | |
6fe4f140 | 847 | struct drm_i915_gem_exec_object2 *exec_entry; |
67731b87 | 848 | |
673a394b EA |
849 | /** |
850 | * Current offset of the object in GTT space. | |
851 | * | |
852 | * This is the same as gtt_space->start | |
853 | */ | |
854 | uint32_t gtt_offset; | |
e67b8ce1 | 855 | |
673a394b EA |
856 | /** Breadcrumb of last rendering to the buffer. */ |
857 | uint32_t last_rendering_seqno; | |
caea7476 CW |
858 | struct intel_ring_buffer *ring; |
859 | ||
860 | /** Breadcrumb of last fenced GPU access to the buffer. */ | |
861 | uint32_t last_fenced_seqno; | |
862 | struct intel_ring_buffer *last_fenced_ring; | |
673a394b | 863 | |
778c3544 | 864 | /** Current tiling stride for the object, if it's tiled. */ |
de151cf6 | 865 | uint32_t stride; |
673a394b | 866 | |
280b713b | 867 | /** Record of address bit 17 of each page at last unbind. */ |
d312ec25 | 868 | unsigned long *bit_17; |
280b713b | 869 | |
ba1eb1d8 | 870 | |
673a394b | 871 | /** |
e47c68e9 EA |
872 | * If present, while GEM_DOMAIN_CPU is in the read domain this array |
873 | * flags which individual pages are valid. | |
673a394b EA |
874 | */ |
875 | uint8_t *page_cpu_valid; | |
79e53945 JB |
876 | |
877 | /** User space pin count and filp owning the pin */ | |
878 | uint32_t user_pin_count; | |
879 | struct drm_file *pin_filp; | |
71acb5eb DA |
880 | |
881 | /** for phy allocated objects */ | |
882 | struct drm_i915_gem_phys_object *phys_obj; | |
b70d11da | 883 | |
6b95a207 KH |
884 | /** |
885 | * Number of crtcs where this object is currently the fb, but | |
886 | * will be page flipped away on the next vblank. When it | |
887 | * reaches 0, dev_priv->pending_flip_queue will be woken up. | |
888 | */ | |
889 | atomic_t pending_flip; | |
673a394b EA |
890 | }; |
891 | ||
62b8b215 | 892 | #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base) |
23010e43 | 893 | |
673a394b EA |
894 | /** |
895 | * Request queue structure. | |
896 | * | |
897 | * The request queue allows us to note sequence numbers that have been emitted | |
898 | * and may be associated with active buffers to be retired. | |
899 | * | |
900 | * By keeping this list, we can avoid having to do questionable | |
901 | * sequence-number comparisons on buffer last_rendering_seqnos, and associate | |
902 | * an emission time with seqnos for tracking how far ahead of the GPU we are. | |
903 | */ | |
904 | struct drm_i915_gem_request { | |
852835f3 ZN |
905 | /** On Which ring this request was generated */ |
906 | struct intel_ring_buffer *ring; | |
907 | ||
673a394b EA |
908 | /** GEM sequence number associated with this request. */ |
909 | uint32_t seqno; | |
910 | ||
911 | /** Time at which this request was emitted, in jiffies. */ | |
912 | unsigned long emitted_jiffies; | |
913 | ||
b962442e | 914 | /** global list entry for this request */ |
673a394b | 915 | struct list_head list; |
b962442e | 916 | |
f787a5f5 | 917 | struct drm_i915_file_private *file_priv; |
b962442e EA |
918 | /** file_priv list entry for this request */ |
919 | struct list_head client_list; | |
673a394b EA |
920 | }; |
921 | ||
922 | struct drm_i915_file_private { | |
923 | struct { | |
1c25595f | 924 | struct spinlock lock; |
b962442e | 925 | struct list_head request_list; |
673a394b EA |
926 | } mm; |
927 | }; | |
928 | ||
cae5852d ZN |
929 | #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info) |
930 | ||
931 | #define IS_I830(dev) ((dev)->pci_device == 0x3577) | |
932 | #define IS_845G(dev) ((dev)->pci_device == 0x2562) | |
933 | #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x) | |
934 | #define IS_I865G(dev) ((dev)->pci_device == 0x2572) | |
935 | #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g) | |
936 | #define IS_I915GM(dev) ((dev)->pci_device == 0x2592) | |
937 | #define IS_I945G(dev) ((dev)->pci_device == 0x2772) | |
938 | #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm) | |
939 | #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater) | |
940 | #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline) | |
941 | #define IS_GM45(dev) ((dev)->pci_device == 0x2A42) | |
942 | #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x) | |
943 | #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001) | |
944 | #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011) | |
945 | #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview) | |
946 | #define IS_G33(dev) (INTEL_INFO(dev)->is_g33) | |
947 | #define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042) | |
948 | #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046) | |
4b65177b | 949 | #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge) |
cae5852d ZN |
950 | #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) |
951 | ||
85436696 JB |
952 | /* |
953 | * The genX designation typically refers to the render engine, so render | |
954 | * capability related checks should use IS_GEN, while display and other checks | |
955 | * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular | |
956 | * chips, etc.). | |
957 | */ | |
cae5852d ZN |
958 | #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2) |
959 | #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3) | |
960 | #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4) | |
961 | #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5) | |
962 | #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6) | |
85436696 | 963 | #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7) |
cae5852d ZN |
964 | |
965 | #define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring) | |
966 | #define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring) | |
3d29b842 | 967 | #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc) |
cae5852d ZN |
968 | #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws) |
969 | ||
05394f39 | 970 | #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay) |
cae5852d ZN |
971 | #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical) |
972 | ||
973 | /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte | |
974 | * rows, which changed the alignment requirements and fence programming. | |
975 | */ | |
976 | #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \ | |
977 | IS_I915GM(dev))) | |
978 | #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) | |
979 | #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev)) | |
980 | #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev)) | |
981 | #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev)) | |
982 | #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv) | |
983 | #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug) | |
984 | /* dsparb controlled by hw only */ | |
985 | #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev)) | |
986 | ||
987 | #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2) | |
988 | #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr) | |
989 | #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc) | |
cae5852d | 990 | |
eceae481 JB |
991 | #define HAS_PCH_SPLIT(dev) (IS_GEN5(dev) || IS_GEN6(dev) || IS_IVYBRIDGE(dev)) |
992 | #define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5) | |
cae5852d ZN |
993 | |
994 | #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type) | |
995 | #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT) | |
996 | #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX) | |
997 | ||
05394f39 CW |
998 | #include "i915_trace.h" |
999 | ||
c153f45f | 1000 | extern struct drm_ioctl_desc i915_ioctls[]; |
b3a83639 | 1001 | extern int i915_max_ioctl; |
a35d9d3c BW |
1002 | extern unsigned int i915_fbpercrtc __always_unused; |
1003 | extern int i915_panel_ignore_lid __read_mostly; | |
1004 | extern unsigned int i915_powersave __read_mostly; | |
f45b5557 | 1005 | extern int i915_semaphores __read_mostly; |
a35d9d3c | 1006 | extern unsigned int i915_lvds_downclock __read_mostly; |
4415e63b | 1007 | extern int i915_panel_use_ssc __read_mostly; |
a35d9d3c | 1008 | extern int i915_vbt_sdvo_panel_type __read_mostly; |
c0f372b3 | 1009 | extern int i915_enable_rc6 __read_mostly; |
4415e63b | 1010 | extern int i915_enable_fbc __read_mostly; |
a35d9d3c | 1011 | extern bool i915_enable_hangcheck __read_mostly; |
b3a83639 | 1012 | |
6a9ee8af DA |
1013 | extern int i915_suspend(struct drm_device *dev, pm_message_t state); |
1014 | extern int i915_resume(struct drm_device *dev); | |
7c1c2871 DA |
1015 | extern int i915_master_create(struct drm_device *dev, struct drm_master *master); |
1016 | extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master); | |
1017 | ||
1da177e4 | 1018 | /* i915_dma.c */ |
84b1fd10 | 1019 | extern void i915_kernel_lost_context(struct drm_device * dev); |
22eae947 | 1020 | extern int i915_driver_load(struct drm_device *, unsigned long flags); |
ba8bbcf6 | 1021 | extern int i915_driver_unload(struct drm_device *); |
673a394b | 1022 | extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv); |
84b1fd10 | 1023 | extern void i915_driver_lastclose(struct drm_device * dev); |
6c340eac EA |
1024 | extern void i915_driver_preclose(struct drm_device *dev, |
1025 | struct drm_file *file_priv); | |
673a394b EA |
1026 | extern void i915_driver_postclose(struct drm_device *dev, |
1027 | struct drm_file *file_priv); | |
84b1fd10 | 1028 | extern int i915_driver_device_is_agp(struct drm_device * dev); |
0d6aa60b DA |
1029 | extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, |
1030 | unsigned long arg); | |
673a394b | 1031 | extern int i915_emit_box(struct drm_device *dev, |
c4e7a414 CW |
1032 | struct drm_clip_rect *box, |
1033 | int DR1, int DR4); | |
f803aa55 | 1034 | extern int i915_reset(struct drm_device *dev, u8 flags); |
7648fa99 JB |
1035 | extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv); |
1036 | extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv); | |
1037 | extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv); | |
1038 | extern void i915_update_gfx_val(struct drm_i915_private *dev_priv); | |
1039 | ||
af6061af | 1040 | |
1da177e4 | 1041 | /* i915_irq.c */ |
f65d9421 | 1042 | void i915_hangcheck_elapsed(unsigned long data); |
527f9e90 | 1043 | void i915_handle_error(struct drm_device *dev, bool wedged); |
c153f45f EA |
1044 | extern int i915_irq_emit(struct drm_device *dev, void *data, |
1045 | struct drm_file *file_priv); | |
1046 | extern int i915_irq_wait(struct drm_device *dev, void *data, | |
1047 | struct drm_file *file_priv); | |
1da177e4 | 1048 | |
f71d4af4 | 1049 | extern void intel_irq_init(struct drm_device *dev); |
b1f14ad0 | 1050 | |
c153f45f EA |
1051 | extern int i915_vblank_pipe_set(struct drm_device *dev, void *data, |
1052 | struct drm_file *file_priv); | |
1053 | extern int i915_vblank_pipe_get(struct drm_device *dev, void *data, | |
1054 | struct drm_file *file_priv); | |
1055 | extern int i915_vblank_swap(struct drm_device *dev, void *data, | |
1056 | struct drm_file *file_priv); | |
1da177e4 | 1057 | |
7c463586 KP |
1058 | void |
1059 | i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); | |
1060 | ||
1061 | void | |
1062 | i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); | |
1063 | ||
0206e353 | 1064 | void intel_enable_asle(struct drm_device *dev); |
01c66889 | 1065 | |
3bd3c932 CW |
1066 | #ifdef CONFIG_DEBUG_FS |
1067 | extern void i915_destroy_error_state(struct drm_device *dev); | |
1068 | #else | |
1069 | #define i915_destroy_error_state(x) | |
1070 | #endif | |
1071 | ||
7c463586 | 1072 | |
673a394b EA |
1073 | /* i915_gem.c */ |
1074 | int i915_gem_init_ioctl(struct drm_device *dev, void *data, | |
1075 | struct drm_file *file_priv); | |
1076 | int i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
1077 | struct drm_file *file_priv); | |
1078 | int i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
1079 | struct drm_file *file_priv); | |
1080 | int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
1081 | struct drm_file *file_priv); | |
1082 | int i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
1083 | struct drm_file *file_priv); | |
de151cf6 JB |
1084 | int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, |
1085 | struct drm_file *file_priv); | |
673a394b EA |
1086 | int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, |
1087 | struct drm_file *file_priv); | |
1088 | int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
1089 | struct drm_file *file_priv); | |
1090 | int i915_gem_execbuffer(struct drm_device *dev, void *data, | |
1091 | struct drm_file *file_priv); | |
76446cac JB |
1092 | int i915_gem_execbuffer2(struct drm_device *dev, void *data, |
1093 | struct drm_file *file_priv); | |
673a394b EA |
1094 | int i915_gem_pin_ioctl(struct drm_device *dev, void *data, |
1095 | struct drm_file *file_priv); | |
1096 | int i915_gem_unpin_ioctl(struct drm_device *dev, void *data, | |
1097 | struct drm_file *file_priv); | |
1098 | int i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
1099 | struct drm_file *file_priv); | |
1100 | int i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
1101 | struct drm_file *file_priv); | |
3ef94daa CW |
1102 | int i915_gem_madvise_ioctl(struct drm_device *dev, void *data, |
1103 | struct drm_file *file_priv); | |
673a394b EA |
1104 | int i915_gem_entervt_ioctl(struct drm_device *dev, void *data, |
1105 | struct drm_file *file_priv); | |
1106 | int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, | |
1107 | struct drm_file *file_priv); | |
1108 | int i915_gem_set_tiling(struct drm_device *dev, void *data, | |
1109 | struct drm_file *file_priv); | |
1110 | int i915_gem_get_tiling(struct drm_device *dev, void *data, | |
1111 | struct drm_file *file_priv); | |
5a125c3c EA |
1112 | int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, |
1113 | struct drm_file *file_priv); | |
673a394b | 1114 | void i915_gem_load(struct drm_device *dev); |
673a394b | 1115 | int i915_gem_init_object(struct drm_gem_object *obj); |
db53a302 | 1116 | int __must_check i915_gem_flush_ring(struct intel_ring_buffer *ring, |
88241785 CW |
1117 | uint32_t invalidate_domains, |
1118 | uint32_t flush_domains); | |
05394f39 CW |
1119 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
1120 | size_t size); | |
673a394b | 1121 | void i915_gem_free_object(struct drm_gem_object *obj); |
2021746e CW |
1122 | int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj, |
1123 | uint32_t alignment, | |
1124 | bool map_and_fenceable); | |
05394f39 | 1125 | void i915_gem_object_unpin(struct drm_i915_gem_object *obj); |
2021746e | 1126 | int __must_check i915_gem_object_unbind(struct drm_i915_gem_object *obj); |
05394f39 | 1127 | void i915_gem_release_mmap(struct drm_i915_gem_object *obj); |
673a394b | 1128 | void i915_gem_lastclose(struct drm_device *dev); |
f787a5f5 | 1129 | |
54cf91dc | 1130 | int __must_check i915_mutex_lock_interruptible(struct drm_device *dev); |
ce453d81 | 1131 | int __must_check i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj); |
54cf91dc | 1132 | void i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, |
1ec14ad3 CW |
1133 | struct intel_ring_buffer *ring, |
1134 | u32 seqno); | |
54cf91dc | 1135 | |
ff72145b DA |
1136 | int i915_gem_dumb_create(struct drm_file *file_priv, |
1137 | struct drm_device *dev, | |
1138 | struct drm_mode_create_dumb *args); | |
1139 | int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev, | |
1140 | uint32_t handle, uint64_t *offset); | |
1141 | int i915_gem_dumb_destroy(struct drm_file *file_priv, struct drm_device *dev, | |
0206e353 | 1142 | uint32_t handle); |
f787a5f5 CW |
1143 | /** |
1144 | * Returns true if seq1 is later than seq2. | |
1145 | */ | |
1146 | static inline bool | |
1147 | i915_seqno_passed(uint32_t seq1, uint32_t seq2) | |
1148 | { | |
1149 | return (int32_t)(seq1 - seq2) >= 0; | |
1150 | } | |
1151 | ||
54cf91dc | 1152 | static inline u32 |
db53a302 | 1153 | i915_gem_next_request_seqno(struct intel_ring_buffer *ring) |
54cf91dc | 1154 | { |
db53a302 | 1155 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
54cf91dc CW |
1156 | return ring->outstanding_lazy_request = dev_priv->next_seqno; |
1157 | } | |
1158 | ||
d9e86c0e | 1159 | int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj, |
ce453d81 | 1160 | struct intel_ring_buffer *pipelined); |
d9e86c0e | 1161 | int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj); |
2021746e | 1162 | |
1690e1eb CW |
1163 | static inline void |
1164 | i915_gem_object_pin_fence(struct drm_i915_gem_object *obj) | |
1165 | { | |
1166 | if (obj->fence_reg != I915_FENCE_REG_NONE) { | |
1167 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
1168 | dev_priv->fence_regs[obj->fence_reg].pin_count++; | |
1169 | } | |
1170 | } | |
1171 | ||
1172 | static inline void | |
1173 | i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj) | |
1174 | { | |
1175 | if (obj->fence_reg != I915_FENCE_REG_NONE) { | |
1176 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
1177 | dev_priv->fence_regs[obj->fence_reg].pin_count--; | |
1178 | } | |
1179 | } | |
1180 | ||
b09a1fec | 1181 | void i915_gem_retire_requests(struct drm_device *dev); |
069efc1d | 1182 | void i915_gem_reset(struct drm_device *dev); |
05394f39 | 1183 | void i915_gem_clflush_object(struct drm_i915_gem_object *obj); |
2021746e CW |
1184 | int __must_check i915_gem_object_set_domain(struct drm_i915_gem_object *obj, |
1185 | uint32_t read_domains, | |
1186 | uint32_t write_domain); | |
a8198eea | 1187 | int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj); |
2021746e | 1188 | int __must_check i915_gem_init_ringbuffer(struct drm_device *dev); |
79e53945 | 1189 | void i915_gem_cleanup_ringbuffer(struct drm_device *dev); |
2021746e CW |
1190 | void i915_gem_do_init(struct drm_device *dev, |
1191 | unsigned long start, | |
1192 | unsigned long mappable_end, | |
1193 | unsigned long end); | |
b93f9cf1 | 1194 | int __must_check i915_gpu_idle(struct drm_device *dev, bool do_retire); |
2021746e | 1195 | int __must_check i915_gem_idle(struct drm_device *dev); |
db53a302 CW |
1196 | int __must_check i915_add_request(struct intel_ring_buffer *ring, |
1197 | struct drm_file *file, | |
1198 | struct drm_i915_gem_request *request); | |
1199 | int __must_check i915_wait_request(struct intel_ring_buffer *ring, | |
b93f9cf1 BW |
1200 | uint32_t seqno, |
1201 | bool do_retire); | |
de151cf6 | 1202 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf); |
2021746e CW |
1203 | int __must_check |
1204 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, | |
1205 | bool write); | |
1206 | int __must_check | |
2da3b9b9 CW |
1207 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
1208 | u32 alignment, | |
2021746e | 1209 | struct intel_ring_buffer *pipelined); |
71acb5eb | 1210 | int i915_gem_attach_phys_object(struct drm_device *dev, |
05394f39 | 1211 | struct drm_i915_gem_object *obj, |
6eeefaf3 CW |
1212 | int id, |
1213 | int align); | |
71acb5eb | 1214 | void i915_gem_detach_phys_object(struct drm_device *dev, |
05394f39 | 1215 | struct drm_i915_gem_object *obj); |
71acb5eb | 1216 | void i915_gem_free_all_phys_object(struct drm_device *dev); |
05394f39 | 1217 | void i915_gem_release(struct drm_device *dev, struct drm_file *file); |
673a394b | 1218 | |
467cffba | 1219 | uint32_t |
e28f8711 CW |
1220 | i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev, |
1221 | uint32_t size, | |
1222 | int tiling_mode); | |
467cffba | 1223 | |
e4ffd173 CW |
1224 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
1225 | enum i915_cache_level cache_level); | |
1226 | ||
76aaf220 DV |
1227 | /* i915_gem_gtt.c */ |
1228 | void i915_gem_restore_gtt_mappings(struct drm_device *dev); | |
2021746e | 1229 | int __must_check i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj); |
e4ffd173 CW |
1230 | void i915_gem_gtt_rebind_object(struct drm_i915_gem_object *obj, |
1231 | enum i915_cache_level cache_level); | |
05394f39 | 1232 | void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj); |
76aaf220 | 1233 | |
b47eb4a2 | 1234 | /* i915_gem_evict.c */ |
2021746e CW |
1235 | int __must_check i915_gem_evict_something(struct drm_device *dev, int min_size, |
1236 | unsigned alignment, bool mappable); | |
1237 | int __must_check i915_gem_evict_everything(struct drm_device *dev, | |
1238 | bool purgeable_only); | |
1239 | int __must_check i915_gem_evict_inactive(struct drm_device *dev, | |
1240 | bool purgeable_only); | |
b47eb4a2 | 1241 | |
673a394b EA |
1242 | /* i915_gem_tiling.c */ |
1243 | void i915_gem_detect_bit_6_swizzle(struct drm_device *dev); | |
05394f39 CW |
1244 | void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj); |
1245 | void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj); | |
673a394b EA |
1246 | |
1247 | /* i915_gem_debug.c */ | |
05394f39 | 1248 | void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len, |
673a394b | 1249 | const char *where, uint32_t mark); |
23bc5982 CW |
1250 | #if WATCH_LISTS |
1251 | int i915_verify_lists(struct drm_device *dev); | |
673a394b | 1252 | #else |
23bc5982 | 1253 | #define i915_verify_lists(dev) 0 |
673a394b | 1254 | #endif |
05394f39 CW |
1255 | void i915_gem_object_check_coherency(struct drm_i915_gem_object *obj, |
1256 | int handle); | |
1257 | void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len, | |
673a394b | 1258 | const char *where, uint32_t mark); |
1da177e4 | 1259 | |
2017263e | 1260 | /* i915_debugfs.c */ |
27c202ad BG |
1261 | int i915_debugfs_init(struct drm_minor *minor); |
1262 | void i915_debugfs_cleanup(struct drm_minor *minor); | |
2017263e | 1263 | |
317c35d1 JB |
1264 | /* i915_suspend.c */ |
1265 | extern int i915_save_state(struct drm_device *dev); | |
1266 | extern int i915_restore_state(struct drm_device *dev); | |
0a3e67a4 JB |
1267 | |
1268 | /* i915_suspend.c */ | |
1269 | extern int i915_save_state(struct drm_device *dev); | |
1270 | extern int i915_restore_state(struct drm_device *dev); | |
317c35d1 | 1271 | |
f899fc64 CW |
1272 | /* intel_i2c.c */ |
1273 | extern int intel_setup_gmbus(struct drm_device *dev); | |
1274 | extern void intel_teardown_gmbus(struct drm_device *dev); | |
e957d772 CW |
1275 | extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed); |
1276 | extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit); | |
b8232e90 CW |
1277 | extern inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter) |
1278 | { | |
1279 | return container_of(adapter, struct intel_gmbus, adapter)->force_bit; | |
1280 | } | |
f899fc64 CW |
1281 | extern void intel_i2c_reset(struct drm_device *dev); |
1282 | ||
3b617967 | 1283 | /* intel_opregion.c */ |
44834a67 CW |
1284 | extern int intel_opregion_setup(struct drm_device *dev); |
1285 | #ifdef CONFIG_ACPI | |
1286 | extern void intel_opregion_init(struct drm_device *dev); | |
1287 | extern void intel_opregion_fini(struct drm_device *dev); | |
3b617967 CW |
1288 | extern void intel_opregion_asle_intr(struct drm_device *dev); |
1289 | extern void intel_opregion_gse_intr(struct drm_device *dev); | |
1290 | extern void intel_opregion_enable_asle(struct drm_device *dev); | |
65e082c9 | 1291 | #else |
44834a67 CW |
1292 | static inline void intel_opregion_init(struct drm_device *dev) { return; } |
1293 | static inline void intel_opregion_fini(struct drm_device *dev) { return; } | |
3b617967 CW |
1294 | static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; } |
1295 | static inline void intel_opregion_gse_intr(struct drm_device *dev) { return; } | |
1296 | static inline void intel_opregion_enable_asle(struct drm_device *dev) { return; } | |
65e082c9 | 1297 | #endif |
8ee1c3db | 1298 | |
723bfd70 JB |
1299 | /* intel_acpi.c */ |
1300 | #ifdef CONFIG_ACPI | |
1301 | extern void intel_register_dsm_handler(void); | |
1302 | extern void intel_unregister_dsm_handler(void); | |
1303 | #else | |
1304 | static inline void intel_register_dsm_handler(void) { return; } | |
1305 | static inline void intel_unregister_dsm_handler(void) { return; } | |
1306 | #endif /* CONFIG_ACPI */ | |
1307 | ||
79e53945 JB |
1308 | /* modesetting */ |
1309 | extern void intel_modeset_init(struct drm_device *dev); | |
2c7111db | 1310 | extern void intel_modeset_gem_init(struct drm_device *dev); |
79e53945 | 1311 | extern void intel_modeset_cleanup(struct drm_device *dev); |
28d52043 | 1312 | extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state); |
ee5382ae | 1313 | extern bool intel_fbc_enabled(struct drm_device *dev); |
43a9539f | 1314 | extern void intel_disable_fbc(struct drm_device *dev); |
7648fa99 | 1315 | extern bool ironlake_set_drps(struct drm_device *dev, u8 val); |
9fb526db | 1316 | extern void ironlake_init_pch_refclk(struct drm_device *dev); |
d5bb081b | 1317 | extern void ironlake_enable_rc6(struct drm_device *dev); |
3b8d8d91 | 1318 | extern void gen6_set_rps(struct drm_device *dev, u8 val); |
0206e353 AJ |
1319 | extern void intel_detect_pch(struct drm_device *dev); |
1320 | extern int intel_trans_dp_port_sel(struct drm_crtc *crtc); | |
3bad0781 | 1321 | |
8d715f00 KP |
1322 | extern void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv); |
1323 | extern void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv); | |
1324 | extern void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv); | |
1325 | extern void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv); | |
1326 | ||
6ef3d427 | 1327 | /* overlay */ |
3bd3c932 | 1328 | #ifdef CONFIG_DEBUG_FS |
6ef3d427 CW |
1329 | extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev); |
1330 | extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error); | |
c4a1d9e4 CW |
1331 | |
1332 | extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev); | |
1333 | extern void intel_display_print_error_state(struct seq_file *m, | |
1334 | struct drm_device *dev, | |
1335 | struct intel_display_error_state *error); | |
3bd3c932 | 1336 | #endif |
6ef3d427 | 1337 | |
1ec14ad3 CW |
1338 | #define LP_RING(d) (&((struct drm_i915_private *)(d))->ring[RCS]) |
1339 | ||
1340 | #define BEGIN_LP_RING(n) \ | |
1341 | intel_ring_begin(LP_RING(dev_priv), (n)) | |
1342 | ||
1343 | #define OUT_RING(x) \ | |
1344 | intel_ring_emit(LP_RING(dev_priv), x) | |
1345 | ||
1346 | #define ADVANCE_LP_RING() \ | |
1347 | intel_ring_advance(LP_RING(dev_priv)) | |
1348 | ||
546b0974 EA |
1349 | /** |
1350 | * Lock test for when it's just for synchronization of ring access. | |
1351 | * | |
1352 | * In that case, we don't need to do it when GEM is initialized as nobody else | |
1353 | * has access to the ring. | |
1354 | */ | |
05394f39 | 1355 | #define RING_LOCK_TEST_WITH_RETURN(dev, file) do { \ |
1ec14ad3 | 1356 | if (LP_RING(dev->dev_private)->obj == NULL) \ |
05394f39 | 1357 | LOCK_TEST_WITH_RETURN(dev, file); \ |
546b0974 EA |
1358 | } while (0) |
1359 | ||
b7287d80 BW |
1360 | /* On SNB platform, before reading ring registers forcewake bit |
1361 | * must be set to prevent GT core from power down and stale values being | |
1362 | * returned. | |
1363 | */ | |
fcca7926 BW |
1364 | void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv); |
1365 | void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv); | |
b7287d80 BW |
1366 | void __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv); |
1367 | ||
1368 | /* We give fast paths for the really cool registers */ | |
1369 | #define NEEDS_FORCE_WAKE(dev_priv, reg) \ | |
1370 | (((dev_priv)->info->gen >= 6) && \ | |
8d715f00 | 1371 | ((reg) < 0x40000) && \ |
c7dffff7 | 1372 | ((reg) != FORCEWAKE)) |
cae5852d | 1373 | |
5f75377d | 1374 | #define __i915_read(x, y) \ |
f7000883 | 1375 | u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg); |
fcca7926 | 1376 | |
5f75377d KP |
1377 | __i915_read(8, b) |
1378 | __i915_read(16, w) | |
1379 | __i915_read(32, l) | |
1380 | __i915_read(64, q) | |
1381 | #undef __i915_read | |
1382 | ||
1383 | #define __i915_write(x, y) \ | |
f7000883 AK |
1384 | void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val); |
1385 | ||
5f75377d KP |
1386 | __i915_write(8, b) |
1387 | __i915_write(16, w) | |
1388 | __i915_write(32, l) | |
1389 | __i915_write(64, q) | |
1390 | #undef __i915_write | |
1391 | ||
1392 | #define I915_READ8(reg) i915_read8(dev_priv, (reg)) | |
1393 | #define I915_WRITE8(reg, val) i915_write8(dev_priv, (reg), (val)) | |
1394 | ||
1395 | #define I915_READ16(reg) i915_read16(dev_priv, (reg)) | |
1396 | #define I915_WRITE16(reg, val) i915_write16(dev_priv, (reg), (val)) | |
1397 | #define I915_READ16_NOTRACE(reg) readw(dev_priv->regs + (reg)) | |
1398 | #define I915_WRITE16_NOTRACE(reg, val) writew(val, dev_priv->regs + (reg)) | |
1399 | ||
1400 | #define I915_READ(reg) i915_read32(dev_priv, (reg)) | |
1401 | #define I915_WRITE(reg, val) i915_write32(dev_priv, (reg), (val)) | |
cae5852d ZN |
1402 | #define I915_READ_NOTRACE(reg) readl(dev_priv->regs + (reg)) |
1403 | #define I915_WRITE_NOTRACE(reg, val) writel(val, dev_priv->regs + (reg)) | |
5f75377d KP |
1404 | |
1405 | #define I915_WRITE64(reg, val) i915_write64(dev_priv, (reg), (val)) | |
1406 | #define I915_READ64(reg) i915_read64(dev_priv, (reg)) | |
cae5852d ZN |
1407 | |
1408 | #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg) | |
1409 | #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg) | |
1410 | ||
ba4f01a3 | 1411 | |
1da177e4 | 1412 | #endif |