Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- |
2 | */ | |
0d6aa60b | 3 | /* |
bc54fd1a | 4 | * |
1da177e4 LT |
5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
6 | * All Rights Reserved. | |
bc54fd1a DA |
7 | * |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the | |
10 | * "Software"), to deal in the Software without restriction, including | |
11 | * without limitation the rights to use, copy, modify, merge, publish, | |
12 | * distribute, sub license, and/or sell copies of the Software, and to | |
13 | * permit persons to whom the Software is furnished to do so, subject to | |
14 | * the following conditions: | |
15 | * | |
16 | * The above copyright notice and this permission notice (including the | |
17 | * next paragraph) shall be included in all copies or substantial portions | |
18 | * of the Software. | |
19 | * | |
20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
27 | * | |
0d6aa60b | 28 | */ |
1da177e4 LT |
29 | |
30 | #ifndef _I915_DRV_H_ | |
31 | #define _I915_DRV_H_ | |
32 | ||
e9b73c67 | 33 | #include <uapi/drm/i915_drm.h> |
93b81f51 | 34 | #include <uapi/drm/drm_fourcc.h> |
e9b73c67 | 35 | |
585fb111 | 36 | #include "i915_reg.h" |
79e53945 | 37 | #include "intel_bios.h" |
8187a2b7 | 38 | #include "intel_ringbuffer.h" |
b20385f1 | 39 | #include "intel_lrc.h" |
0260c420 | 40 | #include "i915_gem_gtt.h" |
564ddb2f | 41 | #include "i915_gem_render_state.h" |
0839ccb8 | 42 | #include <linux/io-mapping.h> |
f899fc64 | 43 | #include <linux/i2c.h> |
c167a6fc | 44 | #include <linux/i2c-algo-bit.h> |
0ade6386 | 45 | #include <drm/intel-gtt.h> |
ba8286fa | 46 | #include <drm/drm_legacy.h> /* for struct drm_dma_handle */ |
d9fc9413 | 47 | #include <drm/drm_gem.h> |
aaa6fd2a | 48 | #include <linux/backlight.h> |
5cc9ed4b | 49 | #include <linux/hashtable.h> |
2911a35b | 50 | #include <linux/intel-iommu.h> |
742cbee8 | 51 | #include <linux/kref.h> |
9ee32fea | 52 | #include <linux/pm_qos.h> |
585fb111 | 53 | |
1da177e4 LT |
54 | /* General customization: |
55 | */ | |
56 | ||
1da177e4 LT |
57 | #define DRIVER_NAME "i915" |
58 | #define DRIVER_DESC "Intel Graphics" | |
fbb35c19 | 59 | #define DRIVER_DATE "20150619" |
1da177e4 | 60 | |
c883ef1b | 61 | #undef WARN_ON |
5f77eeb0 DV |
62 | /* Many gcc seem to no see through this and fall over :( */ |
63 | #if 0 | |
64 | #define WARN_ON(x) ({ \ | |
65 | bool __i915_warn_cond = (x); \ | |
66 | if (__builtin_constant_p(__i915_warn_cond)) \ | |
67 | BUILD_BUG_ON(__i915_warn_cond); \ | |
68 | WARN(__i915_warn_cond, "WARN_ON(" #x ")"); }) | |
69 | #else | |
70 | #define WARN_ON(x) WARN((x), "WARN_ON(" #x ")") | |
71 | #endif | |
72 | ||
cd9bfacb JN |
73 | #undef WARN_ON_ONCE |
74 | #define WARN_ON_ONCE(x) WARN_ONCE((x), "WARN_ON_ONCE(" #x ")") | |
75 | ||
5f77eeb0 DV |
76 | #define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \ |
77 | (long) (x), __func__); | |
c883ef1b | 78 | |
e2c719b7 RC |
79 | /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and |
80 | * WARN_ON()) for hw state sanity checks to check for unexpected conditions | |
81 | * which may not necessarily be a user visible problem. This will either | |
82 | * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to | |
83 | * enable distros and users to tailor their preferred amount of i915 abrt | |
84 | * spam. | |
85 | */ | |
86 | #define I915_STATE_WARN(condition, format...) ({ \ | |
87 | int __ret_warn_on = !!(condition); \ | |
88 | if (unlikely(__ret_warn_on)) { \ | |
89 | if (i915.verbose_state_checks) \ | |
2f3408c7 | 90 | WARN(1, format); \ |
e2c719b7 RC |
91 | else \ |
92 | DRM_ERROR(format); \ | |
93 | } \ | |
94 | unlikely(__ret_warn_on); \ | |
95 | }) | |
96 | ||
97 | #define I915_STATE_WARN_ON(condition) ({ \ | |
98 | int __ret_warn_on = !!(condition); \ | |
99 | if (unlikely(__ret_warn_on)) { \ | |
100 | if (i915.verbose_state_checks) \ | |
2f3408c7 | 101 | WARN(1, "WARN_ON(" #condition ")\n"); \ |
e2c719b7 RC |
102 | else \ |
103 | DRM_ERROR("WARN_ON(" #condition ")\n"); \ | |
104 | } \ | |
105 | unlikely(__ret_warn_on); \ | |
106 | }) | |
c883ef1b | 107 | |
317c35d1 | 108 | enum pipe { |
752aa88a | 109 | INVALID_PIPE = -1, |
317c35d1 JB |
110 | PIPE_A = 0, |
111 | PIPE_B, | |
9db4a9c7 | 112 | PIPE_C, |
a57c774a AK |
113 | _PIPE_EDP, |
114 | I915_MAX_PIPES = _PIPE_EDP | |
317c35d1 | 115 | }; |
9db4a9c7 | 116 | #define pipe_name(p) ((p) + 'A') |
317c35d1 | 117 | |
a5c961d1 PZ |
118 | enum transcoder { |
119 | TRANSCODER_A = 0, | |
120 | TRANSCODER_B, | |
121 | TRANSCODER_C, | |
a57c774a AK |
122 | TRANSCODER_EDP, |
123 | I915_MAX_TRANSCODERS | |
a5c961d1 PZ |
124 | }; |
125 | #define transcoder_name(t) ((t) + 'A') | |
126 | ||
84139d1e DL |
127 | /* |
128 | * This is the maximum (across all platforms) number of planes (primary + | |
129 | * sprites) that can be active at the same time on one pipe. | |
130 | * | |
131 | * This value doesn't count the cursor plane. | |
132 | */ | |
8232edb5 | 133 | #define I915_MAX_PLANES 4 |
84139d1e | 134 | |
80824003 JB |
135 | enum plane { |
136 | PLANE_A = 0, | |
137 | PLANE_B, | |
9db4a9c7 | 138 | PLANE_C, |
80824003 | 139 | }; |
9db4a9c7 | 140 | #define plane_name(p) ((p) + 'A') |
52440211 | 141 | |
d615a166 | 142 | #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A') |
06da8da2 | 143 | |
2b139522 ED |
144 | enum port { |
145 | PORT_A = 0, | |
146 | PORT_B, | |
147 | PORT_C, | |
148 | PORT_D, | |
149 | PORT_E, | |
150 | I915_MAX_PORTS | |
151 | }; | |
152 | #define port_name(p) ((p) + 'A') | |
153 | ||
a09caddd | 154 | #define I915_NUM_PHYS_VLV 2 |
e4607fcf CML |
155 | |
156 | enum dpio_channel { | |
157 | DPIO_CH0, | |
158 | DPIO_CH1 | |
159 | }; | |
160 | ||
161 | enum dpio_phy { | |
162 | DPIO_PHY0, | |
163 | DPIO_PHY1 | |
164 | }; | |
165 | ||
b97186f0 PZ |
166 | enum intel_display_power_domain { |
167 | POWER_DOMAIN_PIPE_A, | |
168 | POWER_DOMAIN_PIPE_B, | |
169 | POWER_DOMAIN_PIPE_C, | |
170 | POWER_DOMAIN_PIPE_A_PANEL_FITTER, | |
171 | POWER_DOMAIN_PIPE_B_PANEL_FITTER, | |
172 | POWER_DOMAIN_PIPE_C_PANEL_FITTER, | |
173 | POWER_DOMAIN_TRANSCODER_A, | |
174 | POWER_DOMAIN_TRANSCODER_B, | |
175 | POWER_DOMAIN_TRANSCODER_C, | |
f52e353e | 176 | POWER_DOMAIN_TRANSCODER_EDP, |
319be8ae ID |
177 | POWER_DOMAIN_PORT_DDI_A_2_LANES, |
178 | POWER_DOMAIN_PORT_DDI_A_4_LANES, | |
179 | POWER_DOMAIN_PORT_DDI_B_2_LANES, | |
180 | POWER_DOMAIN_PORT_DDI_B_4_LANES, | |
181 | POWER_DOMAIN_PORT_DDI_C_2_LANES, | |
182 | POWER_DOMAIN_PORT_DDI_C_4_LANES, | |
183 | POWER_DOMAIN_PORT_DDI_D_2_LANES, | |
184 | POWER_DOMAIN_PORT_DDI_D_4_LANES, | |
185 | POWER_DOMAIN_PORT_DSI, | |
186 | POWER_DOMAIN_PORT_CRT, | |
187 | POWER_DOMAIN_PORT_OTHER, | |
cdf8dd7f | 188 | POWER_DOMAIN_VGA, |
fbeeaa23 | 189 | POWER_DOMAIN_AUDIO, |
bd2bb1b9 | 190 | POWER_DOMAIN_PLLS, |
1407121a S |
191 | POWER_DOMAIN_AUX_A, |
192 | POWER_DOMAIN_AUX_B, | |
193 | POWER_DOMAIN_AUX_C, | |
194 | POWER_DOMAIN_AUX_D, | |
baa70707 | 195 | POWER_DOMAIN_INIT, |
bddc7645 ID |
196 | |
197 | POWER_DOMAIN_NUM, | |
b97186f0 PZ |
198 | }; |
199 | ||
200 | #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A) | |
201 | #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \ | |
202 | ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER) | |
f52e353e ID |
203 | #define POWER_DOMAIN_TRANSCODER(tran) \ |
204 | ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \ | |
205 | (tran) + POWER_DOMAIN_TRANSCODER_A) | |
b97186f0 | 206 | |
1d843f9d EE |
207 | enum hpd_pin { |
208 | HPD_NONE = 0, | |
209 | HPD_PORT_A = HPD_NONE, /* PORT_A is internal */ | |
210 | HPD_TV = HPD_NONE, /* TV is known to be unreliable */ | |
211 | HPD_CRT, | |
212 | HPD_SDVO_B, | |
213 | HPD_SDVO_C, | |
214 | HPD_PORT_B, | |
215 | HPD_PORT_C, | |
216 | HPD_PORT_D, | |
217 | HPD_NUM_PINS | |
218 | }; | |
219 | ||
c91711f9 JN |
220 | #define for_each_hpd_pin(__pin) \ |
221 | for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++) | |
222 | ||
5fcece80 JN |
223 | struct i915_hotplug { |
224 | struct work_struct hotplug_work; | |
225 | ||
226 | struct { | |
227 | unsigned long last_jiffies; | |
228 | int count; | |
229 | enum { | |
230 | HPD_ENABLED = 0, | |
231 | HPD_DISABLED = 1, | |
232 | HPD_MARK_DISABLED = 2 | |
233 | } state; | |
234 | } stats[HPD_NUM_PINS]; | |
235 | u32 event_bits; | |
236 | struct delayed_work reenable_work; | |
237 | ||
238 | struct intel_digital_port *irq_port[I915_MAX_PORTS]; | |
239 | u32 long_port_mask; | |
240 | u32 short_port_mask; | |
241 | struct work_struct dig_port_work; | |
242 | ||
243 | /* | |
244 | * if we get a HPD irq from DP and a HPD irq from non-DP | |
245 | * the non-DP HPD could block the workqueue on a mode config | |
246 | * mutex getting, that userspace may have taken. However | |
247 | * userspace is waiting on the DP workqueue to run which is | |
248 | * blocked behind the non-DP one. | |
249 | */ | |
250 | struct workqueue_struct *dp_wq; | |
251 | }; | |
252 | ||
2a2d5482 CW |
253 | #define I915_GEM_GPU_DOMAINS \ |
254 | (I915_GEM_DOMAIN_RENDER | \ | |
255 | I915_GEM_DOMAIN_SAMPLER | \ | |
256 | I915_GEM_DOMAIN_COMMAND | \ | |
257 | I915_GEM_DOMAIN_INSTRUCTION | \ | |
258 | I915_GEM_DOMAIN_VERTEX) | |
62fdfeaf | 259 | |
055e393f DL |
260 | #define for_each_pipe(__dev_priv, __p) \ |
261 | for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) | |
dd740780 DL |
262 | #define for_each_plane(__dev_priv, __pipe, __p) \ |
263 | for ((__p) = 0; \ | |
264 | (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \ | |
265 | (__p)++) | |
3bdcfc0c DL |
266 | #define for_each_sprite(__dev_priv, __p, __s) \ |
267 | for ((__s) = 0; \ | |
268 | (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \ | |
269 | (__s)++) | |
9db4a9c7 | 270 | |
d79b814d DL |
271 | #define for_each_crtc(dev, crtc) \ |
272 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) | |
273 | ||
27321ae8 ML |
274 | #define for_each_intel_plane(dev, intel_plane) \ |
275 | list_for_each_entry(intel_plane, \ | |
276 | &dev->mode_config.plane_list, \ | |
277 | base.head) | |
278 | ||
d063ae48 DL |
279 | #define for_each_intel_crtc(dev, intel_crtc) \ |
280 | list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head) | |
281 | ||
b2784e15 DL |
282 | #define for_each_intel_encoder(dev, intel_encoder) \ |
283 | list_for_each_entry(intel_encoder, \ | |
284 | &(dev)->mode_config.encoder_list, \ | |
285 | base.head) | |
286 | ||
3a3371ff ACO |
287 | #define for_each_intel_connector(dev, intel_connector) \ |
288 | list_for_each_entry(intel_connector, \ | |
289 | &dev->mode_config.connector_list, \ | |
290 | base.head) | |
291 | ||
6c2b7c12 DV |
292 | #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \ |
293 | list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \ | |
294 | if ((intel_encoder)->base.crtc == (__crtc)) | |
295 | ||
53f5e3ca JB |
296 | #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \ |
297 | list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \ | |
298 | if ((intel_connector)->base.encoder == (__encoder)) | |
299 | ||
b04c5bd6 BF |
300 | #define for_each_power_domain(domain, mask) \ |
301 | for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \ | |
302 | if ((1 << (domain)) & (mask)) | |
303 | ||
e7b903d2 | 304 | struct drm_i915_private; |
ad46cb53 | 305 | struct i915_mm_struct; |
5cc9ed4b | 306 | struct i915_mmu_object; |
e7b903d2 | 307 | |
a6f766f3 CW |
308 | struct drm_i915_file_private { |
309 | struct drm_i915_private *dev_priv; | |
310 | struct drm_file *file; | |
311 | ||
312 | struct { | |
313 | spinlock_t lock; | |
314 | struct list_head request_list; | |
d0bc54f2 CW |
315 | /* 20ms is a fairly arbitrary limit (greater than the average frame time) |
316 | * chosen to prevent the CPU getting more than a frame ahead of the GPU | |
317 | * (when using lax throttling for the frontbuffer). We also use it to | |
318 | * offer free GPU waitboosts for severely congested workloads. | |
319 | */ | |
320 | #define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20) | |
a6f766f3 CW |
321 | } mm; |
322 | struct idr context_idr; | |
323 | ||
2e1b8730 CW |
324 | struct intel_rps_client { |
325 | struct list_head link; | |
326 | unsigned boosts; | |
327 | } rps; | |
a6f766f3 | 328 | |
2e1b8730 | 329 | struct intel_engine_cs *bsd_ring; |
a6f766f3 CW |
330 | }; |
331 | ||
46edb027 DV |
332 | enum intel_dpll_id { |
333 | DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */ | |
334 | /* real shared dpll ids must be >= 0 */ | |
9cd86933 DV |
335 | DPLL_ID_PCH_PLL_A = 0, |
336 | DPLL_ID_PCH_PLL_B = 1, | |
429d47d5 | 337 | /* hsw/bdw */ |
9cd86933 DV |
338 | DPLL_ID_WRPLL1 = 0, |
339 | DPLL_ID_WRPLL2 = 1, | |
429d47d5 S |
340 | /* skl */ |
341 | DPLL_ID_SKL_DPLL1 = 0, | |
342 | DPLL_ID_SKL_DPLL2 = 1, | |
343 | DPLL_ID_SKL_DPLL3 = 2, | |
46edb027 | 344 | }; |
429d47d5 | 345 | #define I915_NUM_PLLS 3 |
46edb027 | 346 | |
5358901f | 347 | struct intel_dpll_hw_state { |
dcfc3552 | 348 | /* i9xx, pch plls */ |
66e985c0 | 349 | uint32_t dpll; |
8bcc2795 | 350 | uint32_t dpll_md; |
66e985c0 DV |
351 | uint32_t fp0; |
352 | uint32_t fp1; | |
dcfc3552 DL |
353 | |
354 | /* hsw, bdw */ | |
d452c5b6 | 355 | uint32_t wrpll; |
d1a2dc78 S |
356 | |
357 | /* skl */ | |
358 | /* | |
359 | * DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in | |
71cd8423 | 360 | * lower part of ctrl1 and they get shifted into position when writing |
d1a2dc78 S |
361 | * the register. This allows us to easily compare the state to share |
362 | * the DPLL. | |
363 | */ | |
364 | uint32_t ctrl1; | |
365 | /* HDMI only, 0 when used for DP */ | |
366 | uint32_t cfgcr1, cfgcr2; | |
dfb82408 S |
367 | |
368 | /* bxt */ | |
b6dc71f3 | 369 | uint32_t ebb0, pll0, pll1, pll2, pll3, pll6, pll8, pll10, pcsdw12; |
5358901f DV |
370 | }; |
371 | ||
3e369b76 | 372 | struct intel_shared_dpll_config { |
1e6f2ddc | 373 | unsigned crtc_mask; /* mask of CRTCs sharing this PLL */ |
3e369b76 ACO |
374 | struct intel_dpll_hw_state hw_state; |
375 | }; | |
376 | ||
377 | struct intel_shared_dpll { | |
378 | struct intel_shared_dpll_config config; | |
8bd31e67 | 379 | |
ee7b9f93 JB |
380 | int active; /* count of number of active CRTCs (i.e. DPMS on) */ |
381 | bool on; /* is the PLL actually active? Disabled during modeset */ | |
46edb027 DV |
382 | const char *name; |
383 | /* should match the index in the dev_priv->shared_dplls array */ | |
384 | enum intel_dpll_id id; | |
96f6128c DV |
385 | /* The mode_set hook is optional and should be used together with the |
386 | * intel_prepare_shared_dpll function. */ | |
15bdd4cf DV |
387 | void (*mode_set)(struct drm_i915_private *dev_priv, |
388 | struct intel_shared_dpll *pll); | |
e7b903d2 DV |
389 | void (*enable)(struct drm_i915_private *dev_priv, |
390 | struct intel_shared_dpll *pll); | |
391 | void (*disable)(struct drm_i915_private *dev_priv, | |
392 | struct intel_shared_dpll *pll); | |
5358901f DV |
393 | bool (*get_hw_state)(struct drm_i915_private *dev_priv, |
394 | struct intel_shared_dpll *pll, | |
395 | struct intel_dpll_hw_state *hw_state); | |
ee7b9f93 | 396 | }; |
ee7b9f93 | 397 | |
429d47d5 S |
398 | #define SKL_DPLL0 0 |
399 | #define SKL_DPLL1 1 | |
400 | #define SKL_DPLL2 2 | |
401 | #define SKL_DPLL3 3 | |
402 | ||
e69d0bc1 DV |
403 | /* Used by dp and fdi links */ |
404 | struct intel_link_m_n { | |
405 | uint32_t tu; | |
406 | uint32_t gmch_m; | |
407 | uint32_t gmch_n; | |
408 | uint32_t link_m; | |
409 | uint32_t link_n; | |
410 | }; | |
411 | ||
412 | void intel_link_compute_m_n(int bpp, int nlanes, | |
413 | int pixel_clock, int link_clock, | |
414 | struct intel_link_m_n *m_n); | |
415 | ||
1da177e4 LT |
416 | /* Interface history: |
417 | * | |
418 | * 1.1: Original. | |
0d6aa60b DA |
419 | * 1.2: Add Power Management |
420 | * 1.3: Add vblank support | |
de227f5f | 421 | * 1.4: Fix cmdbuffer path, add heap destroy |
702880f2 | 422 | * 1.5: Add vblank pipe configuration |
2228ed67 MCA |
423 | * 1.6: - New ioctl for scheduling buffer swaps on vertical blank |
424 | * - Support vertical blank on secondary display pipe | |
1da177e4 LT |
425 | */ |
426 | #define DRIVER_MAJOR 1 | |
2228ed67 | 427 | #define DRIVER_MINOR 6 |
1da177e4 LT |
428 | #define DRIVER_PATCHLEVEL 0 |
429 | ||
23bc5982 | 430 | #define WATCH_LISTS 0 |
673a394b | 431 | |
0a3e67a4 JB |
432 | struct opregion_header; |
433 | struct opregion_acpi; | |
434 | struct opregion_swsci; | |
435 | struct opregion_asle; | |
436 | ||
8ee1c3db | 437 | struct intel_opregion { |
5bc4418b BW |
438 | struct opregion_header __iomem *header; |
439 | struct opregion_acpi __iomem *acpi; | |
440 | struct opregion_swsci __iomem *swsci; | |
ebde53c7 JN |
441 | u32 swsci_gbda_sub_functions; |
442 | u32 swsci_sbcb_sub_functions; | |
5bc4418b BW |
443 | struct opregion_asle __iomem *asle; |
444 | void __iomem *vbt; | |
01fe9dbd | 445 | u32 __iomem *lid_state; |
91a60f20 | 446 | struct work_struct asle_work; |
8ee1c3db | 447 | }; |
44834a67 | 448 | #define OPREGION_SIZE (8*1024) |
8ee1c3db | 449 | |
6ef3d427 CW |
450 | struct intel_overlay; |
451 | struct intel_overlay_error_state; | |
452 | ||
de151cf6 | 453 | #define I915_FENCE_REG_NONE -1 |
42b5aeab VS |
454 | #define I915_MAX_NUM_FENCES 32 |
455 | /* 32 fences + sign bit for FENCE_REG_NONE */ | |
456 | #define I915_MAX_NUM_FENCE_BITS 6 | |
de151cf6 JB |
457 | |
458 | struct drm_i915_fence_reg { | |
007cc8ac | 459 | struct list_head lru_list; |
caea7476 | 460 | struct drm_i915_gem_object *obj; |
1690e1eb | 461 | int pin_count; |
de151cf6 | 462 | }; |
7c1c2871 | 463 | |
9b9d172d | 464 | struct sdvo_device_mapping { |
e957d772 | 465 | u8 initialized; |
9b9d172d | 466 | u8 dvo_port; |
467 | u8 slave_addr; | |
468 | u8 dvo_wiring; | |
e957d772 | 469 | u8 i2c_pin; |
b1083333 | 470 | u8 ddc_pin; |
9b9d172d | 471 | }; |
472 | ||
c4a1d9e4 CW |
473 | struct intel_display_error_state; |
474 | ||
63eeaf38 | 475 | struct drm_i915_error_state { |
742cbee8 | 476 | struct kref ref; |
585b0288 BW |
477 | struct timeval time; |
478 | ||
cb383002 | 479 | char error_msg[128]; |
48b031e3 | 480 | u32 reset_count; |
62d5d69b | 481 | u32 suspend_count; |
cb383002 | 482 | |
585b0288 | 483 | /* Generic register state */ |
63eeaf38 JB |
484 | u32 eir; |
485 | u32 pgtbl_er; | |
be998e2e | 486 | u32 ier; |
885ea5a8 | 487 | u32 gtier[4]; |
b9a3906b | 488 | u32 ccid; |
0f3b6849 CW |
489 | u32 derrmr; |
490 | u32 forcewake; | |
585b0288 BW |
491 | u32 error; /* gen6+ */ |
492 | u32 err_int; /* gen7 */ | |
6c826f34 MK |
493 | u32 fault_data0; /* gen8, gen9 */ |
494 | u32 fault_data1; /* gen8, gen9 */ | |
585b0288 | 495 | u32 done_reg; |
91ec5d11 BW |
496 | u32 gac_eco; |
497 | u32 gam_ecochk; | |
498 | u32 gab_ctl; | |
499 | u32 gfx_mode; | |
585b0288 | 500 | u32 extra_instdone[I915_NUM_INSTDONE_REG]; |
585b0288 BW |
501 | u64 fence[I915_MAX_NUM_FENCES]; |
502 | struct intel_overlay_error_state *overlay; | |
503 | struct intel_display_error_state *display; | |
0ca36d78 | 504 | struct drm_i915_error_object *semaphore_obj; |
585b0288 | 505 | |
52d39a21 | 506 | struct drm_i915_error_ring { |
372fbb8e | 507 | bool valid; |
362b8af7 BW |
508 | /* Software tracked state */ |
509 | bool waiting; | |
510 | int hangcheck_score; | |
511 | enum intel_ring_hangcheck_action hangcheck_action; | |
512 | int num_requests; | |
513 | ||
514 | /* our own tracking of ring head and tail */ | |
515 | u32 cpu_ring_head; | |
516 | u32 cpu_ring_tail; | |
517 | ||
518 | u32 semaphore_seqno[I915_NUM_RINGS - 1]; | |
519 | ||
520 | /* Register state */ | |
94f8cf10 | 521 | u32 start; |
362b8af7 BW |
522 | u32 tail; |
523 | u32 head; | |
524 | u32 ctl; | |
525 | u32 hws; | |
526 | u32 ipeir; | |
527 | u32 ipehr; | |
528 | u32 instdone; | |
362b8af7 BW |
529 | u32 bbstate; |
530 | u32 instpm; | |
531 | u32 instps; | |
532 | u32 seqno; | |
533 | u64 bbaddr; | |
50877445 | 534 | u64 acthd; |
362b8af7 | 535 | u32 fault_reg; |
13ffadd1 | 536 | u64 faddr; |
362b8af7 BW |
537 | u32 rc_psmi; /* sleep state */ |
538 | u32 semaphore_mboxes[I915_NUM_RINGS - 1]; | |
539 | ||
52d39a21 CW |
540 | struct drm_i915_error_object { |
541 | int page_count; | |
542 | u32 gtt_offset; | |
543 | u32 *pages[0]; | |
ab0e7ff9 | 544 | } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page; |
362b8af7 | 545 | |
52d39a21 CW |
546 | struct drm_i915_error_request { |
547 | long jiffies; | |
548 | u32 seqno; | |
ee4f42b1 | 549 | u32 tail; |
52d39a21 | 550 | } *requests; |
6c7a01ec BW |
551 | |
552 | struct { | |
553 | u32 gfx_mode; | |
554 | union { | |
555 | u64 pdp[4]; | |
556 | u32 pp_dir_base; | |
557 | }; | |
558 | } vm_info; | |
ab0e7ff9 CW |
559 | |
560 | pid_t pid; | |
561 | char comm[TASK_COMM_LEN]; | |
52d39a21 | 562 | } ring[I915_NUM_RINGS]; |
3a448734 | 563 | |
9df30794 | 564 | struct drm_i915_error_buffer { |
a779e5ab | 565 | u32 size; |
9df30794 | 566 | u32 name; |
b4716185 | 567 | u32 rseqno[I915_NUM_RINGS], wseqno; |
9df30794 CW |
568 | u32 gtt_offset; |
569 | u32 read_domains; | |
570 | u32 write_domain; | |
4b9de737 | 571 | s32 fence_reg:I915_MAX_NUM_FENCE_BITS; |
9df30794 CW |
572 | s32 pinned:2; |
573 | u32 tiling:2; | |
574 | u32 dirty:1; | |
575 | u32 purgeable:1; | |
5cc9ed4b | 576 | u32 userptr:1; |
5d1333fc | 577 | s32 ring:4; |
f56383cb | 578 | u32 cache_level:3; |
95f5301d | 579 | } **active_bo, **pinned_bo; |
6c7a01ec | 580 | |
95f5301d | 581 | u32 *active_bo_count, *pinned_bo_count; |
3a448734 | 582 | u32 vm_count; |
63eeaf38 JB |
583 | }; |
584 | ||
7bd688cd | 585 | struct intel_connector; |
820d2d77 | 586 | struct intel_encoder; |
5cec258b | 587 | struct intel_crtc_state; |
5724dbd1 | 588 | struct intel_initial_plane_config; |
0e8ffe1b | 589 | struct intel_crtc; |
ee9300bb DV |
590 | struct intel_limit; |
591 | struct dpll; | |
b8cecdf5 | 592 | |
e70236a8 | 593 | struct drm_i915_display_funcs { |
ee5382ae | 594 | bool (*fbc_enabled)(struct drm_device *dev); |
993495ae | 595 | void (*enable_fbc)(struct drm_crtc *crtc); |
e70236a8 JB |
596 | void (*disable_fbc)(struct drm_device *dev); |
597 | int (*get_display_clock_speed)(struct drm_device *dev); | |
598 | int (*get_fifo_size)(struct drm_device *dev, int plane); | |
ee9300bb DV |
599 | /** |
600 | * find_dpll() - Find the best values for the PLL | |
601 | * @limit: limits for the PLL | |
602 | * @crtc: current CRTC | |
603 | * @target: target frequency in kHz | |
604 | * @refclk: reference clock frequency in kHz | |
605 | * @match_clock: if provided, @best_clock P divider must | |
606 | * match the P divider from @match_clock | |
607 | * used for LVDS downclocking | |
608 | * @best_clock: best PLL values found | |
609 | * | |
610 | * Returns true on success, false on failure. | |
611 | */ | |
612 | bool (*find_dpll)(const struct intel_limit *limit, | |
a93e255f | 613 | struct intel_crtc_state *crtc_state, |
ee9300bb DV |
614 | int target, int refclk, |
615 | struct dpll *match_clock, | |
616 | struct dpll *best_clock); | |
46ba614c | 617 | void (*update_wm)(struct drm_crtc *crtc); |
adf3d35e VS |
618 | void (*update_sprite_wm)(struct drm_plane *plane, |
619 | struct drm_crtc *crtc, | |
ed57cb8a DL |
620 | uint32_t sprite_width, uint32_t sprite_height, |
621 | int pixel_size, bool enable, bool scaled); | |
27c329ed ML |
622 | int (*modeset_calc_cdclk)(struct drm_atomic_state *state); |
623 | void (*modeset_commit_cdclk)(struct drm_atomic_state *state); | |
0e8ffe1b DV |
624 | /* Returns the active state of the crtc, and if the crtc is active, |
625 | * fills out the pipe-config with the hw state. */ | |
626 | bool (*get_pipe_config)(struct intel_crtc *, | |
5cec258b | 627 | struct intel_crtc_state *); |
5724dbd1 DL |
628 | void (*get_initial_plane_config)(struct intel_crtc *, |
629 | struct intel_initial_plane_config *); | |
190f68c5 ACO |
630 | int (*crtc_compute_clock)(struct intel_crtc *crtc, |
631 | struct intel_crtc_state *crtc_state); | |
76e5a89c DV |
632 | void (*crtc_enable)(struct drm_crtc *crtc); |
633 | void (*crtc_disable)(struct drm_crtc *crtc); | |
69bfe1a9 JN |
634 | void (*audio_codec_enable)(struct drm_connector *connector, |
635 | struct intel_encoder *encoder, | |
636 | struct drm_display_mode *mode); | |
637 | void (*audio_codec_disable)(struct intel_encoder *encoder); | |
674cf967 | 638 | void (*fdi_link_train)(struct drm_crtc *crtc); |
6067aaea | 639 | void (*init_clock_gating)(struct drm_device *dev); |
8c9f3aaf JB |
640 | int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc, |
641 | struct drm_framebuffer *fb, | |
ed8d1975 | 642 | struct drm_i915_gem_object *obj, |
a4872ba6 | 643 | struct intel_engine_cs *ring, |
ed8d1975 | 644 | uint32_t flags); |
29b9bde6 DV |
645 | void (*update_primary_plane)(struct drm_crtc *crtc, |
646 | struct drm_framebuffer *fb, | |
647 | int x, int y); | |
20afbda2 | 648 | void (*hpd_irq_setup)(struct drm_device *dev); |
e70236a8 JB |
649 | /* clock updates for mode set */ |
650 | /* cursor updates */ | |
651 | /* render clock increase/decrease */ | |
652 | /* display clock increase/decrease */ | |
653 | /* pll clock increase/decrease */ | |
7bd688cd | 654 | |
6517d273 | 655 | int (*setup_backlight)(struct intel_connector *connector, enum pipe pipe); |
7bd688cd JN |
656 | uint32_t (*get_backlight)(struct intel_connector *connector); |
657 | void (*set_backlight)(struct intel_connector *connector, | |
658 | uint32_t level); | |
659 | void (*disable_backlight)(struct intel_connector *connector); | |
660 | void (*enable_backlight)(struct intel_connector *connector); | |
e70236a8 JB |
661 | }; |
662 | ||
48c1026a MK |
663 | enum forcewake_domain_id { |
664 | FW_DOMAIN_ID_RENDER = 0, | |
665 | FW_DOMAIN_ID_BLITTER, | |
666 | FW_DOMAIN_ID_MEDIA, | |
667 | ||
668 | FW_DOMAIN_ID_COUNT | |
669 | }; | |
670 | ||
671 | enum forcewake_domains { | |
672 | FORCEWAKE_RENDER = (1 << FW_DOMAIN_ID_RENDER), | |
673 | FORCEWAKE_BLITTER = (1 << FW_DOMAIN_ID_BLITTER), | |
674 | FORCEWAKE_MEDIA = (1 << FW_DOMAIN_ID_MEDIA), | |
675 | FORCEWAKE_ALL = (FORCEWAKE_RENDER | | |
676 | FORCEWAKE_BLITTER | | |
677 | FORCEWAKE_MEDIA) | |
678 | }; | |
679 | ||
907b28c5 | 680 | struct intel_uncore_funcs { |
c8d9a590 | 681 | void (*force_wake_get)(struct drm_i915_private *dev_priv, |
48c1026a | 682 | enum forcewake_domains domains); |
c8d9a590 | 683 | void (*force_wake_put)(struct drm_i915_private *dev_priv, |
48c1026a | 684 | enum forcewake_domains domains); |
0b274481 BW |
685 | |
686 | uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, off_t offset, bool trace); | |
687 | uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, off_t offset, bool trace); | |
688 | uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, off_t offset, bool trace); | |
689 | uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, off_t offset, bool trace); | |
690 | ||
691 | void (*mmio_writeb)(struct drm_i915_private *dev_priv, off_t offset, | |
692 | uint8_t val, bool trace); | |
693 | void (*mmio_writew)(struct drm_i915_private *dev_priv, off_t offset, | |
694 | uint16_t val, bool trace); | |
695 | void (*mmio_writel)(struct drm_i915_private *dev_priv, off_t offset, | |
696 | uint32_t val, bool trace); | |
697 | void (*mmio_writeq)(struct drm_i915_private *dev_priv, off_t offset, | |
698 | uint64_t val, bool trace); | |
990bbdad CW |
699 | }; |
700 | ||
907b28c5 CW |
701 | struct intel_uncore { |
702 | spinlock_t lock; /** lock is also taken in irq contexts. */ | |
703 | ||
704 | struct intel_uncore_funcs funcs; | |
705 | ||
706 | unsigned fifo_count; | |
48c1026a | 707 | enum forcewake_domains fw_domains; |
b2cff0db CW |
708 | |
709 | struct intel_uncore_forcewake_domain { | |
710 | struct drm_i915_private *i915; | |
48c1026a | 711 | enum forcewake_domain_id id; |
b2cff0db CW |
712 | unsigned wake_count; |
713 | struct timer_list timer; | |
05a2fb15 MK |
714 | u32 reg_set; |
715 | u32 val_set; | |
716 | u32 val_clear; | |
717 | u32 reg_ack; | |
718 | u32 reg_post; | |
719 | u32 val_reset; | |
b2cff0db | 720 | } fw_domain[FW_DOMAIN_ID_COUNT]; |
b2cff0db CW |
721 | }; |
722 | ||
723 | /* Iterate over initialised fw domains */ | |
724 | #define for_each_fw_domain_mask(domain__, mask__, dev_priv__, i__) \ | |
725 | for ((i__) = 0, (domain__) = &(dev_priv__)->uncore.fw_domain[0]; \ | |
726 | (i__) < FW_DOMAIN_ID_COUNT; \ | |
727 | (i__)++, (domain__) = &(dev_priv__)->uncore.fw_domain[i__]) \ | |
728 | if (((mask__) & (dev_priv__)->uncore.fw_domains) & (1 << (i__))) | |
729 | ||
730 | #define for_each_fw_domain(domain__, dev_priv__, i__) \ | |
731 | for_each_fw_domain_mask(domain__, FORCEWAKE_ALL, dev_priv__, i__) | |
907b28c5 | 732 | |
dc174300 SS |
733 | enum csr_state { |
734 | FW_UNINITIALIZED = 0, | |
735 | FW_LOADED, | |
736 | FW_FAILED | |
737 | }; | |
738 | ||
eb805623 DV |
739 | struct intel_csr { |
740 | const char *fw_path; | |
741 | __be32 *dmc_payload; | |
742 | uint32_t dmc_fw_size; | |
743 | uint32_t mmio_count; | |
744 | uint32_t mmioaddr[8]; | |
745 | uint32_t mmiodata[8]; | |
dc174300 | 746 | enum csr_state state; |
eb805623 DV |
747 | }; |
748 | ||
79fc46df DL |
749 | #define DEV_INFO_FOR_EACH_FLAG(func, sep) \ |
750 | func(is_mobile) sep \ | |
751 | func(is_i85x) sep \ | |
752 | func(is_i915g) sep \ | |
753 | func(is_i945gm) sep \ | |
754 | func(is_g33) sep \ | |
755 | func(need_gfx_hws) sep \ | |
756 | func(is_g4x) sep \ | |
757 | func(is_pineview) sep \ | |
758 | func(is_broadwater) sep \ | |
759 | func(is_crestline) sep \ | |
760 | func(is_ivybridge) sep \ | |
761 | func(is_valleyview) sep \ | |
762 | func(is_haswell) sep \ | |
7201c0b3 | 763 | func(is_skylake) sep \ |
b833d685 | 764 | func(is_preliminary) sep \ |
79fc46df DL |
765 | func(has_fbc) sep \ |
766 | func(has_pipe_cxsr) sep \ | |
767 | func(has_hotplug) sep \ | |
768 | func(cursor_needs_physical) sep \ | |
769 | func(has_overlay) sep \ | |
770 | func(overlay_needs_physical) sep \ | |
771 | func(supports_tv) sep \ | |
dd93be58 | 772 | func(has_llc) sep \ |
30568c45 DL |
773 | func(has_ddi) sep \ |
774 | func(has_fpga_dbg) | |
c96ea64e | 775 | |
a587f779 DL |
776 | #define DEFINE_FLAG(name) u8 name:1 |
777 | #define SEP_SEMICOLON ; | |
c96ea64e | 778 | |
cfdf1fa2 | 779 | struct intel_device_info { |
10fce67a | 780 | u32 display_mmio_offset; |
87f1f465 | 781 | u16 device_id; |
7eb552ae | 782 | u8 num_pipes:3; |
d615a166 | 783 | u8 num_sprites[I915_MAX_PIPES]; |
c96c3a8c | 784 | u8 gen; |
73ae478c | 785 | u8 ring_mask; /* Rings supported by the HW */ |
a587f779 | 786 | DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON); |
a57c774a AK |
787 | /* Register offsets for the various display pipes and transcoders */ |
788 | int pipe_offsets[I915_MAX_TRANSCODERS]; | |
789 | int trans_offsets[I915_MAX_TRANSCODERS]; | |
a57c774a | 790 | int palette_offsets[I915_MAX_PIPES]; |
5efb3e28 | 791 | int cursor_offsets[I915_MAX_PIPES]; |
3873218f JM |
792 | |
793 | /* Slice/subslice/EU info */ | |
794 | u8 slice_total; | |
795 | u8 subslice_total; | |
796 | u8 subslice_per_slice; | |
797 | u8 eu_total; | |
798 | u8 eu_per_subslice; | |
b7668791 DL |
799 | /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */ |
800 | u8 subslice_7eu[3]; | |
3873218f JM |
801 | u8 has_slice_pg:1; |
802 | u8 has_subslice_pg:1; | |
803 | u8 has_eu_pg:1; | |
cfdf1fa2 KH |
804 | }; |
805 | ||
a587f779 DL |
806 | #undef DEFINE_FLAG |
807 | #undef SEP_SEMICOLON | |
808 | ||
7faf1ab2 DV |
809 | enum i915_cache_level { |
810 | I915_CACHE_NONE = 0, | |
350ec881 CW |
811 | I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */ |
812 | I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc | |
813 | caches, eg sampler/render caches, and the | |
814 | large Last-Level-Cache. LLC is coherent with | |
815 | the CPU, but L3 is only visible to the GPU. */ | |
651d794f | 816 | I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */ |
7faf1ab2 DV |
817 | }; |
818 | ||
e59ec13d MK |
819 | struct i915_ctx_hang_stats { |
820 | /* This context had batch pending when hang was declared */ | |
821 | unsigned batch_pending; | |
822 | ||
823 | /* This context had batch active when hang was declared */ | |
824 | unsigned batch_active; | |
be62acb4 MK |
825 | |
826 | /* Time when this context was last blamed for a GPU reset */ | |
827 | unsigned long guilty_ts; | |
828 | ||
676fa572 CW |
829 | /* If the contexts causes a second GPU hang within this time, |
830 | * it is permanently banned from submitting any more work. | |
831 | */ | |
832 | unsigned long ban_period_seconds; | |
833 | ||
be62acb4 MK |
834 | /* This context is banned to submit more work */ |
835 | bool banned; | |
e59ec13d | 836 | }; |
40521054 BW |
837 | |
838 | /* This must match up with the value previously used for execbuf2.rsvd1. */ | |
821d66dd | 839 | #define DEFAULT_CONTEXT_HANDLE 0 |
b1b38278 DW |
840 | |
841 | #define CONTEXT_NO_ZEROMAP (1<<0) | |
31b7a88d OM |
842 | /** |
843 | * struct intel_context - as the name implies, represents a context. | |
844 | * @ref: reference count. | |
845 | * @user_handle: userspace tracking identity for this context. | |
846 | * @remap_slice: l3 row remapping information. | |
b1b38278 DW |
847 | * @flags: context specific flags: |
848 | * CONTEXT_NO_ZEROMAP: do not allow mapping things to page 0. | |
31b7a88d OM |
849 | * @file_priv: filp associated with this context (NULL for global default |
850 | * context). | |
851 | * @hang_stats: information about the role of this context in possible GPU | |
852 | * hangs. | |
7df113e4 | 853 | * @ppgtt: virtual memory space used by this context. |
31b7a88d OM |
854 | * @legacy_hw_ctx: render context backing object and whether it is correctly |
855 | * initialized (legacy ring submission mechanism only). | |
856 | * @link: link in the global list of contexts. | |
857 | * | |
858 | * Contexts are memory images used by the hardware to store copies of their | |
859 | * internal state. | |
860 | */ | |
273497e5 | 861 | struct intel_context { |
dce3271b | 862 | struct kref ref; |
821d66dd | 863 | int user_handle; |
3ccfd19d | 864 | uint8_t remap_slice; |
b1b38278 | 865 | int flags; |
40521054 | 866 | struct drm_i915_file_private *file_priv; |
e59ec13d | 867 | struct i915_ctx_hang_stats hang_stats; |
ae6c4806 | 868 | struct i915_hw_ppgtt *ppgtt; |
a33afea5 | 869 | |
c9e003af | 870 | /* Legacy ring buffer submission */ |
ea0c76f8 OM |
871 | struct { |
872 | struct drm_i915_gem_object *rcs_state; | |
873 | bool initialized; | |
874 | } legacy_hw_ctx; | |
875 | ||
c9e003af | 876 | /* Execlists */ |
564ddb2f | 877 | bool rcs_initialized; |
c9e003af OM |
878 | struct { |
879 | struct drm_i915_gem_object *state; | |
84c2377f | 880 | struct intel_ringbuffer *ringbuf; |
a7cbedec | 881 | int pin_count; |
c9e003af OM |
882 | } engine[I915_NUM_RINGS]; |
883 | ||
a33afea5 | 884 | struct list_head link; |
40521054 BW |
885 | }; |
886 | ||
a4001f1b PZ |
887 | enum fb_op_origin { |
888 | ORIGIN_GTT, | |
889 | ORIGIN_CPU, | |
890 | ORIGIN_CS, | |
891 | ORIGIN_FLIP, | |
892 | }; | |
893 | ||
5c3fe8b0 | 894 | struct i915_fbc { |
60ee5cd2 | 895 | unsigned long uncompressed_size; |
5e59f717 | 896 | unsigned threshold; |
5c3fe8b0 | 897 | unsigned int fb_id; |
dbef0f15 PZ |
898 | unsigned int possible_framebuffer_bits; |
899 | unsigned int busy_bits; | |
e35fef21 | 900 | struct intel_crtc *crtc; |
5c3fe8b0 BW |
901 | int y; |
902 | ||
c4213885 | 903 | struct drm_mm_node compressed_fb; |
5c3fe8b0 BW |
904 | struct drm_mm_node *compressed_llb; |
905 | ||
da46f936 RV |
906 | bool false_color; |
907 | ||
9adccc60 PZ |
908 | /* Tracks whether the HW is actually enabled, not whether the feature is |
909 | * possible. */ | |
910 | bool enabled; | |
911 | ||
5c3fe8b0 BW |
912 | struct intel_fbc_work { |
913 | struct delayed_work work; | |
914 | struct drm_crtc *crtc; | |
915 | struct drm_framebuffer *fb; | |
5c3fe8b0 BW |
916 | } *fbc_work; |
917 | ||
29ebf90f CW |
918 | enum no_fbc_reason { |
919 | FBC_OK, /* FBC is enabled */ | |
920 | FBC_UNSUPPORTED, /* FBC is not supported by this chipset */ | |
5c3fe8b0 BW |
921 | FBC_NO_OUTPUT, /* no outputs enabled to compress */ |
922 | FBC_STOLEN_TOO_SMALL, /* not enough space for buffers */ | |
923 | FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */ | |
924 | FBC_MODE_TOO_LARGE, /* mode too large for compression */ | |
925 | FBC_BAD_PLANE, /* fbc not supported on plane */ | |
926 | FBC_NOT_TILED, /* buffer not tiled */ | |
927 | FBC_MULTIPLE_PIPES, /* more than one pipe active */ | |
928 | FBC_MODULE_PARAM, | |
929 | FBC_CHIP_DEFAULT, /* disabled by default on this chip */ | |
87f5ff01 | 930 | FBC_ROTATION, /* rotation is not supported */ |
5c3fe8b0 | 931 | } no_fbc_reason; |
b5e50c3f JB |
932 | }; |
933 | ||
96178eeb VK |
934 | /** |
935 | * HIGH_RR is the highest eDP panel refresh rate read from EDID | |
936 | * LOW_RR is the lowest eDP panel refresh rate found from EDID | |
937 | * parsing for same resolution. | |
938 | */ | |
939 | enum drrs_refresh_rate_type { | |
940 | DRRS_HIGH_RR, | |
941 | DRRS_LOW_RR, | |
942 | DRRS_MAX_RR, /* RR count */ | |
943 | }; | |
944 | ||
945 | enum drrs_support_type { | |
946 | DRRS_NOT_SUPPORTED = 0, | |
947 | STATIC_DRRS_SUPPORT = 1, | |
948 | SEAMLESS_DRRS_SUPPORT = 2 | |
439d7ac0 PB |
949 | }; |
950 | ||
2807cf69 | 951 | struct intel_dp; |
96178eeb VK |
952 | struct i915_drrs { |
953 | struct mutex mutex; | |
954 | struct delayed_work work; | |
955 | struct intel_dp *dp; | |
956 | unsigned busy_frontbuffer_bits; | |
957 | enum drrs_refresh_rate_type refresh_rate_type; | |
958 | enum drrs_support_type type; | |
959 | }; | |
960 | ||
a031d709 | 961 | struct i915_psr { |
f0355c4a | 962 | struct mutex lock; |
a031d709 RV |
963 | bool sink_support; |
964 | bool source_ok; | |
2807cf69 | 965 | struct intel_dp *enabled; |
7c8f8a70 RV |
966 | bool active; |
967 | struct delayed_work work; | |
9ca15301 | 968 | unsigned busy_frontbuffer_bits; |
474d1ec4 SJ |
969 | bool psr2_support; |
970 | bool aux_frame_sync; | |
3f51e471 | 971 | }; |
5c3fe8b0 | 972 | |
3bad0781 | 973 | enum intel_pch { |
f0350830 | 974 | PCH_NONE = 0, /* No PCH present */ |
3bad0781 ZW |
975 | PCH_IBX, /* Ibexpeak PCH */ |
976 | PCH_CPT, /* Cougarpoint PCH */ | |
eb877ebf | 977 | PCH_LPT, /* Lynxpoint PCH */ |
e7e7ea20 | 978 | PCH_SPT, /* Sunrisepoint PCH */ |
40c7ead9 | 979 | PCH_NOP, |
3bad0781 ZW |
980 | }; |
981 | ||
988d6ee8 PZ |
982 | enum intel_sbi_destination { |
983 | SBI_ICLK, | |
984 | SBI_MPHY, | |
985 | }; | |
986 | ||
b690e96c | 987 | #define QUIRK_PIPEA_FORCE (1<<0) |
435793df | 988 | #define QUIRK_LVDS_SSC_DISABLE (1<<1) |
4dca20ef | 989 | #define QUIRK_INVERT_BRIGHTNESS (1<<2) |
9c72cc6f | 990 | #define QUIRK_BACKLIGHT_PRESENT (1<<3) |
b6b5d049 | 991 | #define QUIRK_PIPEB_FORCE (1<<4) |
656bfa3a | 992 | #define QUIRK_PIN_SWIZZLED_PAGES (1<<5) |
b690e96c | 993 | |
8be48d92 | 994 | struct intel_fbdev; |
1630fe75 | 995 | struct intel_fbc_work; |
38651674 | 996 | |
c2b9152f DV |
997 | struct intel_gmbus { |
998 | struct i2c_adapter adapter; | |
f2ce9faf | 999 | u32 force_bit; |
c2b9152f | 1000 | u32 reg0; |
36c785f0 | 1001 | u32 gpio_reg; |
c167a6fc | 1002 | struct i2c_algo_bit_data bit_algo; |
c2b9152f DV |
1003 | struct drm_i915_private *dev_priv; |
1004 | }; | |
1005 | ||
f4c956ad | 1006 | struct i915_suspend_saved_registers { |
e948e994 | 1007 | u32 saveDSPARB; |
ba8bbcf6 | 1008 | u32 saveLVDS; |
585fb111 JB |
1009 | u32 savePP_ON_DELAYS; |
1010 | u32 savePP_OFF_DELAYS; | |
ba8bbcf6 JB |
1011 | u32 savePP_ON; |
1012 | u32 savePP_OFF; | |
1013 | u32 savePP_CONTROL; | |
585fb111 | 1014 | u32 savePP_DIVISOR; |
ba8bbcf6 | 1015 | u32 saveFBC_CONTROL; |
1f84e550 | 1016 | u32 saveCACHE_MODE_0; |
1f84e550 | 1017 | u32 saveMI_ARB_STATE; |
ba8bbcf6 JB |
1018 | u32 saveSWF0[16]; |
1019 | u32 saveSWF1[16]; | |
1020 | u32 saveSWF2[3]; | |
4b9de737 | 1021 | uint64_t saveFENCE[I915_MAX_NUM_FENCES]; |
cda2bb78 | 1022 | u32 savePCH_PORT_HOTPLUG; |
9f49c376 | 1023 | u16 saveGCDGMBUS; |
f4c956ad | 1024 | }; |
c85aa885 | 1025 | |
ddeea5b0 ID |
1026 | struct vlv_s0ix_state { |
1027 | /* GAM */ | |
1028 | u32 wr_watermark; | |
1029 | u32 gfx_prio_ctrl; | |
1030 | u32 arb_mode; | |
1031 | u32 gfx_pend_tlb0; | |
1032 | u32 gfx_pend_tlb1; | |
1033 | u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM]; | |
1034 | u32 media_max_req_count; | |
1035 | u32 gfx_max_req_count; | |
1036 | u32 render_hwsp; | |
1037 | u32 ecochk; | |
1038 | u32 bsd_hwsp; | |
1039 | u32 blt_hwsp; | |
1040 | u32 tlb_rd_addr; | |
1041 | ||
1042 | /* MBC */ | |
1043 | u32 g3dctl; | |
1044 | u32 gsckgctl; | |
1045 | u32 mbctl; | |
1046 | ||
1047 | /* GCP */ | |
1048 | u32 ucgctl1; | |
1049 | u32 ucgctl3; | |
1050 | u32 rcgctl1; | |
1051 | u32 rcgctl2; | |
1052 | u32 rstctl; | |
1053 | u32 misccpctl; | |
1054 | ||
1055 | /* GPM */ | |
1056 | u32 gfxpause; | |
1057 | u32 rpdeuhwtc; | |
1058 | u32 rpdeuc; | |
1059 | u32 ecobus; | |
1060 | u32 pwrdwnupctl; | |
1061 | u32 rp_down_timeout; | |
1062 | u32 rp_deucsw; | |
1063 | u32 rcubmabdtmr; | |
1064 | u32 rcedata; | |
1065 | u32 spare2gh; | |
1066 | ||
1067 | /* Display 1 CZ domain */ | |
1068 | u32 gt_imr; | |
1069 | u32 gt_ier; | |
1070 | u32 pm_imr; | |
1071 | u32 pm_ier; | |
1072 | u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM]; | |
1073 | ||
1074 | /* GT SA CZ domain */ | |
1075 | u32 tilectl; | |
1076 | u32 gt_fifoctl; | |
1077 | u32 gtlc_wake_ctrl; | |
1078 | u32 gtlc_survive; | |
1079 | u32 pmwgicz; | |
1080 | ||
1081 | /* Display 2 CZ domain */ | |
1082 | u32 gu_ctl0; | |
1083 | u32 gu_ctl1; | |
9c25210f | 1084 | u32 pcbr; |
ddeea5b0 ID |
1085 | u32 clock_gate_dis2; |
1086 | }; | |
1087 | ||
bf225f20 CW |
1088 | struct intel_rps_ei { |
1089 | u32 cz_clock; | |
1090 | u32 render_c0; | |
1091 | u32 media_c0; | |
31685c25 D |
1092 | }; |
1093 | ||
c85aa885 | 1094 | struct intel_gen6_power_mgmt { |
d4d70aa5 ID |
1095 | /* |
1096 | * work, interrupts_enabled and pm_iir are protected by | |
1097 | * dev_priv->irq_lock | |
1098 | */ | |
c85aa885 | 1099 | struct work_struct work; |
d4d70aa5 | 1100 | bool interrupts_enabled; |
c85aa885 | 1101 | u32 pm_iir; |
59cdb63d | 1102 | |
b39fb297 BW |
1103 | /* Frequencies are stored in potentially platform dependent multiples. |
1104 | * In other words, *_freq needs to be multiplied by X to be interesting. | |
1105 | * Soft limits are those which are used for the dynamic reclocking done | |
1106 | * by the driver (raise frequencies under heavy loads, and lower for | |
1107 | * lighter loads). Hard limits are those imposed by the hardware. | |
1108 | * | |
1109 | * A distinction is made for overclocking, which is never enabled by | |
1110 | * default, and is considered to be above the hard limit if it's | |
1111 | * possible at all. | |
1112 | */ | |
1113 | u8 cur_freq; /* Current frequency (cached, may not == HW) */ | |
1114 | u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */ | |
1115 | u8 max_freq_softlimit; /* Max frequency permitted by the driver */ | |
1116 | u8 max_freq; /* Maximum frequency, RP0 if not overclocking */ | |
1117 | u8 min_freq; /* AKA RPn. Minimum frequency */ | |
aed242ff | 1118 | u8 idle_freq; /* Frequency to request when we are idle */ |
b39fb297 BW |
1119 | u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */ |
1120 | u8 rp1_freq; /* "less than" RP0 power/freqency */ | |
1121 | u8 rp0_freq; /* Non-overclocked max frequency. */ | |
67c3bf6f | 1122 | u32 cz_freq; |
1a01ab3b | 1123 | |
8fb55197 CW |
1124 | u8 up_threshold; /* Current %busy required to uplock */ |
1125 | u8 down_threshold; /* Current %busy required to downclock */ | |
1126 | ||
dd75fdc8 CW |
1127 | int last_adj; |
1128 | enum { LOW_POWER, BETWEEN, HIGH_POWER } power; | |
1129 | ||
8d3afd7d CW |
1130 | spinlock_t client_lock; |
1131 | struct list_head clients; | |
1132 | bool client_boost; | |
1133 | ||
c0951f0c | 1134 | bool enabled; |
1a01ab3b | 1135 | struct delayed_work delayed_resume_work; |
1854d5ca | 1136 | unsigned boosts; |
4fc688ce | 1137 | |
2e1b8730 | 1138 | struct intel_rps_client semaphores, mmioflips; |
a6f766f3 | 1139 | |
bf225f20 CW |
1140 | /* manual wa residency calculations */ |
1141 | struct intel_rps_ei up_ei, down_ei; | |
1142 | ||
4fc688ce JB |
1143 | /* |
1144 | * Protects RPS/RC6 register access and PCU communication. | |
8d3afd7d CW |
1145 | * Must be taken after struct_mutex if nested. Note that |
1146 | * this lock may be held for long periods of time when | |
1147 | * talking to hw - so only take it when talking to hw! | |
4fc688ce JB |
1148 | */ |
1149 | struct mutex hw_lock; | |
c85aa885 DV |
1150 | }; |
1151 | ||
1a240d4d DV |
1152 | /* defined intel_pm.c */ |
1153 | extern spinlock_t mchdev_lock; | |
1154 | ||
c85aa885 DV |
1155 | struct intel_ilk_power_mgmt { |
1156 | u8 cur_delay; | |
1157 | u8 min_delay; | |
1158 | u8 max_delay; | |
1159 | u8 fmax; | |
1160 | u8 fstart; | |
1161 | ||
1162 | u64 last_count1; | |
1163 | unsigned long last_time1; | |
1164 | unsigned long chipset_power; | |
1165 | u64 last_count2; | |
5ed0bdf2 | 1166 | u64 last_time2; |
c85aa885 DV |
1167 | unsigned long gfx_power; |
1168 | u8 corr; | |
1169 | ||
1170 | int c_m; | |
1171 | int r_t; | |
1172 | }; | |
1173 | ||
c6cb582e ID |
1174 | struct drm_i915_private; |
1175 | struct i915_power_well; | |
1176 | ||
1177 | struct i915_power_well_ops { | |
1178 | /* | |
1179 | * Synchronize the well's hw state to match the current sw state, for | |
1180 | * example enable/disable it based on the current refcount. Called | |
1181 | * during driver init and resume time, possibly after first calling | |
1182 | * the enable/disable handlers. | |
1183 | */ | |
1184 | void (*sync_hw)(struct drm_i915_private *dev_priv, | |
1185 | struct i915_power_well *power_well); | |
1186 | /* | |
1187 | * Enable the well and resources that depend on it (for example | |
1188 | * interrupts located on the well). Called after the 0->1 refcount | |
1189 | * transition. | |
1190 | */ | |
1191 | void (*enable)(struct drm_i915_private *dev_priv, | |
1192 | struct i915_power_well *power_well); | |
1193 | /* | |
1194 | * Disable the well and resources that depend on it. Called after | |
1195 | * the 1->0 refcount transition. | |
1196 | */ | |
1197 | void (*disable)(struct drm_i915_private *dev_priv, | |
1198 | struct i915_power_well *power_well); | |
1199 | /* Returns the hw enabled state. */ | |
1200 | bool (*is_enabled)(struct drm_i915_private *dev_priv, | |
1201 | struct i915_power_well *power_well); | |
1202 | }; | |
1203 | ||
a38911a3 WX |
1204 | /* Power well structure for haswell */ |
1205 | struct i915_power_well { | |
c1ca727f | 1206 | const char *name; |
6f3ef5dd | 1207 | bool always_on; |
a38911a3 WX |
1208 | /* power well enable/disable usage count */ |
1209 | int count; | |
bfafe93a ID |
1210 | /* cached hw enabled state */ |
1211 | bool hw_enabled; | |
c1ca727f | 1212 | unsigned long domains; |
77961eb9 | 1213 | unsigned long data; |
c6cb582e | 1214 | const struct i915_power_well_ops *ops; |
a38911a3 WX |
1215 | }; |
1216 | ||
83c00f55 | 1217 | struct i915_power_domains { |
baa70707 ID |
1218 | /* |
1219 | * Power wells needed for initialization at driver init and suspend | |
1220 | * time are on. They are kept on until after the first modeset. | |
1221 | */ | |
1222 | bool init_power_on; | |
0d116a29 | 1223 | bool initializing; |
c1ca727f | 1224 | int power_well_count; |
baa70707 | 1225 | |
83c00f55 | 1226 | struct mutex lock; |
1da51581 | 1227 | int domain_use_count[POWER_DOMAIN_NUM]; |
c1ca727f | 1228 | struct i915_power_well *power_wells; |
83c00f55 ID |
1229 | }; |
1230 | ||
35a85ac6 | 1231 | #define MAX_L3_SLICES 2 |
a4da4fa4 | 1232 | struct intel_l3_parity { |
35a85ac6 | 1233 | u32 *remap_info[MAX_L3_SLICES]; |
a4da4fa4 | 1234 | struct work_struct error_work; |
35a85ac6 | 1235 | int which_slice; |
a4da4fa4 DV |
1236 | }; |
1237 | ||
4b5aed62 | 1238 | struct i915_gem_mm { |
4b5aed62 DV |
1239 | /** Memory allocator for GTT stolen memory */ |
1240 | struct drm_mm stolen; | |
4b5aed62 DV |
1241 | /** List of all objects in gtt_space. Used to restore gtt |
1242 | * mappings on resume */ | |
1243 | struct list_head bound_list; | |
1244 | /** | |
1245 | * List of objects which are not bound to the GTT (thus | |
1246 | * are idle and not used by the GPU) but still have | |
1247 | * (presumably uncached) pages still attached. | |
1248 | */ | |
1249 | struct list_head unbound_list; | |
1250 | ||
1251 | /** Usable portion of the GTT for GEM */ | |
1252 | unsigned long stolen_base; /* limited to low memory (32-bit) */ | |
1253 | ||
4b5aed62 DV |
1254 | /** PPGTT used for aliasing the PPGTT with the GTT */ |
1255 | struct i915_hw_ppgtt *aliasing_ppgtt; | |
1256 | ||
2cfcd32a | 1257 | struct notifier_block oom_notifier; |
ceabbba5 | 1258 | struct shrinker shrinker; |
4b5aed62 DV |
1259 | bool shrinker_no_lock_stealing; |
1260 | ||
4b5aed62 DV |
1261 | /** LRU list of objects with fence regs on them. */ |
1262 | struct list_head fence_list; | |
1263 | ||
1264 | /** | |
1265 | * We leave the user IRQ off as much as possible, | |
1266 | * but this means that requests will finish and never | |
1267 | * be retired once the system goes idle. Set a timer to | |
1268 | * fire periodically while the ring is running. When it | |
1269 | * fires, go retire requests. | |
1270 | */ | |
1271 | struct delayed_work retire_work; | |
1272 | ||
b29c19b6 CW |
1273 | /** |
1274 | * When we detect an idle GPU, we want to turn on | |
1275 | * powersaving features. So once we see that there | |
1276 | * are no more requests outstanding and no more | |
1277 | * arrive within a small period of time, we fire | |
1278 | * off the idle_work. | |
1279 | */ | |
1280 | struct delayed_work idle_work; | |
1281 | ||
4b5aed62 DV |
1282 | /** |
1283 | * Are we in a non-interruptible section of code like | |
1284 | * modesetting? | |
1285 | */ | |
1286 | bool interruptible; | |
1287 | ||
f62a0076 CW |
1288 | /** |
1289 | * Is the GPU currently considered idle, or busy executing userspace | |
1290 | * requests? Whilst idle, we attempt to power down the hardware and | |
1291 | * display clocks. In order to reduce the effect on performance, there | |
1292 | * is a slight delay before we do so. | |
1293 | */ | |
1294 | bool busy; | |
1295 | ||
bdf1e7e3 DV |
1296 | /* the indicator for dispatch video commands on two BSD rings */ |
1297 | int bsd_ring_dispatch_index; | |
1298 | ||
4b5aed62 DV |
1299 | /** Bit 6 swizzling required for X tiling */ |
1300 | uint32_t bit_6_swizzle_x; | |
1301 | /** Bit 6 swizzling required for Y tiling */ | |
1302 | uint32_t bit_6_swizzle_y; | |
1303 | ||
4b5aed62 | 1304 | /* accounting, useful for userland debugging */ |
c20e8355 | 1305 | spinlock_t object_stat_lock; |
4b5aed62 DV |
1306 | size_t object_memory; |
1307 | u32 object_count; | |
1308 | }; | |
1309 | ||
edc3d884 | 1310 | struct drm_i915_error_state_buf { |
0a4cd7c8 | 1311 | struct drm_i915_private *i915; |
edc3d884 MK |
1312 | unsigned bytes; |
1313 | unsigned size; | |
1314 | int err; | |
1315 | u8 *buf; | |
1316 | loff_t start; | |
1317 | loff_t pos; | |
1318 | }; | |
1319 | ||
fc16b48b MK |
1320 | struct i915_error_state_file_priv { |
1321 | struct drm_device *dev; | |
1322 | struct drm_i915_error_state *error; | |
1323 | }; | |
1324 | ||
99584db3 DV |
1325 | struct i915_gpu_error { |
1326 | /* For hangcheck timer */ | |
1327 | #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */ | |
1328 | #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD) | |
be62acb4 MK |
1329 | /* Hang gpu twice in this window and your context gets banned */ |
1330 | #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000) | |
1331 | ||
737b1506 CW |
1332 | struct workqueue_struct *hangcheck_wq; |
1333 | struct delayed_work hangcheck_work; | |
99584db3 DV |
1334 | |
1335 | /* For reset and error_state handling. */ | |
1336 | spinlock_t lock; | |
1337 | /* Protected by the above dev->gpu_error.lock. */ | |
1338 | struct drm_i915_error_state *first_error; | |
094f9a54 CW |
1339 | |
1340 | unsigned long missed_irq_rings; | |
1341 | ||
1f83fee0 | 1342 | /** |
2ac0f450 | 1343 | * State variable controlling the reset flow and count |
1f83fee0 | 1344 | * |
2ac0f450 MK |
1345 | * This is a counter which gets incremented when reset is triggered, |
1346 | * and again when reset has been handled. So odd values (lowest bit set) | |
1347 | * means that reset is in progress and even values that | |
1348 | * (reset_counter >> 1):th reset was successfully completed. | |
1349 | * | |
1350 | * If reset is not completed succesfully, the I915_WEDGE bit is | |
1351 | * set meaning that hardware is terminally sour and there is no | |
1352 | * recovery. All waiters on the reset_queue will be woken when | |
1353 | * that happens. | |
1354 | * | |
1355 | * This counter is used by the wait_seqno code to notice that reset | |
1356 | * event happened and it needs to restart the entire ioctl (since most | |
1357 | * likely the seqno it waited for won't ever signal anytime soon). | |
f69061be DV |
1358 | * |
1359 | * This is important for lock-free wait paths, where no contended lock | |
1360 | * naturally enforces the correct ordering between the bail-out of the | |
1361 | * waiter and the gpu reset work code. | |
1f83fee0 DV |
1362 | */ |
1363 | atomic_t reset_counter; | |
1364 | ||
1f83fee0 | 1365 | #define I915_RESET_IN_PROGRESS_FLAG 1 |
2ac0f450 | 1366 | #define I915_WEDGED (1 << 31) |
1f83fee0 DV |
1367 | |
1368 | /** | |
1369 | * Waitqueue to signal when the reset has completed. Used by clients | |
1370 | * that wait for dev_priv->mm.wedged to settle. | |
1371 | */ | |
1372 | wait_queue_head_t reset_queue; | |
33196ded | 1373 | |
88b4aa87 MK |
1374 | /* Userspace knobs for gpu hang simulation; |
1375 | * combines both a ring mask, and extra flags | |
1376 | */ | |
1377 | u32 stop_rings; | |
1378 | #define I915_STOP_RING_ALLOW_BAN (1 << 31) | |
1379 | #define I915_STOP_RING_ALLOW_WARN (1 << 30) | |
094f9a54 CW |
1380 | |
1381 | /* For missed irq/seqno simulation. */ | |
1382 | unsigned int test_irq_rings; | |
6689c167 MA |
1383 | |
1384 | /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */ | |
1385 | bool reload_in_reset; | |
99584db3 DV |
1386 | }; |
1387 | ||
b8efb17b ZR |
1388 | enum modeset_restore { |
1389 | MODESET_ON_LID_OPEN, | |
1390 | MODESET_DONE, | |
1391 | MODESET_SUSPENDED, | |
1392 | }; | |
1393 | ||
6acab15a | 1394 | struct ddi_vbt_port_info { |
ce4dd49e DL |
1395 | /* |
1396 | * This is an index in the HDMI/DVI DDI buffer translation table. | |
1397 | * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't | |
1398 | * populate this field. | |
1399 | */ | |
1400 | #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff | |
6acab15a | 1401 | uint8_t hdmi_level_shift; |
311a2094 PZ |
1402 | |
1403 | uint8_t supports_dvi:1; | |
1404 | uint8_t supports_hdmi:1; | |
1405 | uint8_t supports_dp:1; | |
6acab15a PZ |
1406 | }; |
1407 | ||
bfd7ebda RV |
1408 | enum psr_lines_to_wait { |
1409 | PSR_0_LINES_TO_WAIT = 0, | |
1410 | PSR_1_LINE_TO_WAIT, | |
1411 | PSR_4_LINES_TO_WAIT, | |
1412 | PSR_8_LINES_TO_WAIT | |
83a7280e PB |
1413 | }; |
1414 | ||
41aa3448 RV |
1415 | struct intel_vbt_data { |
1416 | struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ | |
1417 | struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ | |
1418 | ||
1419 | /* Feature bits */ | |
1420 | unsigned int int_tv_support:1; | |
1421 | unsigned int lvds_dither:1; | |
1422 | unsigned int lvds_vbt:1; | |
1423 | unsigned int int_crt_support:1; | |
1424 | unsigned int lvds_use_ssc:1; | |
1425 | unsigned int display_clock_mode:1; | |
1426 | unsigned int fdi_rx_polarity_inverted:1; | |
3e6bd011 | 1427 | unsigned int has_mipi:1; |
41aa3448 RV |
1428 | int lvds_ssc_freq; |
1429 | unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */ | |
1430 | ||
83a7280e PB |
1431 | enum drrs_support_type drrs_type; |
1432 | ||
41aa3448 RV |
1433 | /* eDP */ |
1434 | int edp_rate; | |
1435 | int edp_lanes; | |
1436 | int edp_preemphasis; | |
1437 | int edp_vswing; | |
1438 | bool edp_initialized; | |
1439 | bool edp_support; | |
1440 | int edp_bpp; | |
1441 | struct edp_power_seq edp_pps; | |
1442 | ||
bfd7ebda RV |
1443 | struct { |
1444 | bool full_link; | |
1445 | bool require_aux_wakeup; | |
1446 | int idle_frames; | |
1447 | enum psr_lines_to_wait lines_to_wait; | |
1448 | int tp1_wakeup_time; | |
1449 | int tp2_tp3_wakeup_time; | |
1450 | } psr; | |
1451 | ||
f00076d2 JN |
1452 | struct { |
1453 | u16 pwm_freq_hz; | |
39fbc9c8 | 1454 | bool present; |
f00076d2 | 1455 | bool active_low_pwm; |
1de6068e | 1456 | u8 min_brightness; /* min_brightness/255 of max */ |
f00076d2 JN |
1457 | } backlight; |
1458 | ||
d17c5443 SK |
1459 | /* MIPI DSI */ |
1460 | struct { | |
3e6bd011 | 1461 | u16 port; |
d17c5443 | 1462 | u16 panel_id; |
d3b542fc SK |
1463 | struct mipi_config *config; |
1464 | struct mipi_pps_data *pps; | |
1465 | u8 seq_version; | |
1466 | u32 size; | |
1467 | u8 *data; | |
1468 | u8 *sequence[MIPI_SEQ_MAX]; | |
d17c5443 SK |
1469 | } dsi; |
1470 | ||
41aa3448 RV |
1471 | int crt_ddc_pin; |
1472 | ||
1473 | int child_dev_num; | |
768f69c9 | 1474 | union child_device_config *child_dev; |
6acab15a PZ |
1475 | |
1476 | struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS]; | |
41aa3448 RV |
1477 | }; |
1478 | ||
77c122bc VS |
1479 | enum intel_ddb_partitioning { |
1480 | INTEL_DDB_PART_1_2, | |
1481 | INTEL_DDB_PART_5_6, /* IVB+ */ | |
1482 | }; | |
1483 | ||
1fd527cc VS |
1484 | struct intel_wm_level { |
1485 | bool enable; | |
1486 | uint32_t pri_val; | |
1487 | uint32_t spr_val; | |
1488 | uint32_t cur_val; | |
1489 | uint32_t fbc_val; | |
1490 | }; | |
1491 | ||
820c1980 | 1492 | struct ilk_wm_values { |
609cedef VS |
1493 | uint32_t wm_pipe[3]; |
1494 | uint32_t wm_lp[3]; | |
1495 | uint32_t wm_lp_spr[3]; | |
1496 | uint32_t wm_linetime[3]; | |
1497 | bool enable_fbc_wm; | |
1498 | enum intel_ddb_partitioning partitioning; | |
1499 | }; | |
1500 | ||
0018fda1 | 1501 | struct vlv_wm_values { |
ae80152d VS |
1502 | struct { |
1503 | uint16_t primary; | |
1504 | uint16_t sprite[2]; | |
1505 | uint8_t cursor; | |
1506 | } pipe[3]; | |
1507 | ||
1508 | struct { | |
1509 | uint16_t plane; | |
1510 | uint8_t cursor; | |
1511 | } sr; | |
1512 | ||
0018fda1 VS |
1513 | struct { |
1514 | uint8_t cursor; | |
1515 | uint8_t sprite[2]; | |
1516 | uint8_t primary; | |
1517 | } ddl[3]; | |
1518 | }; | |
1519 | ||
c193924e | 1520 | struct skl_ddb_entry { |
16160e3d | 1521 | uint16_t start, end; /* in number of blocks, 'end' is exclusive */ |
c193924e DL |
1522 | }; |
1523 | ||
1524 | static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry) | |
1525 | { | |
16160e3d | 1526 | return entry->end - entry->start; |
c193924e DL |
1527 | } |
1528 | ||
08db6652 DL |
1529 | static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1, |
1530 | const struct skl_ddb_entry *e2) | |
1531 | { | |
1532 | if (e1->start == e2->start && e1->end == e2->end) | |
1533 | return true; | |
1534 | ||
1535 | return false; | |
1536 | } | |
1537 | ||
c193924e | 1538 | struct skl_ddb_allocation { |
34bb56af | 1539 | struct skl_ddb_entry pipe[I915_MAX_PIPES]; |
2cd601c6 CK |
1540 | struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */ |
1541 | struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* y-plane */ | |
c193924e DL |
1542 | struct skl_ddb_entry cursor[I915_MAX_PIPES]; |
1543 | }; | |
1544 | ||
2ac96d2a PB |
1545 | struct skl_wm_values { |
1546 | bool dirty[I915_MAX_PIPES]; | |
c193924e | 1547 | struct skl_ddb_allocation ddb; |
2ac96d2a PB |
1548 | uint32_t wm_linetime[I915_MAX_PIPES]; |
1549 | uint32_t plane[I915_MAX_PIPES][I915_MAX_PLANES][8]; | |
1550 | uint32_t cursor[I915_MAX_PIPES][8]; | |
1551 | uint32_t plane_trans[I915_MAX_PIPES][I915_MAX_PLANES]; | |
1552 | uint32_t cursor_trans[I915_MAX_PIPES]; | |
1553 | }; | |
1554 | ||
1555 | struct skl_wm_level { | |
1556 | bool plane_en[I915_MAX_PLANES]; | |
b99f58da | 1557 | bool cursor_en; |
2ac96d2a PB |
1558 | uint16_t plane_res_b[I915_MAX_PLANES]; |
1559 | uint8_t plane_res_l[I915_MAX_PLANES]; | |
2ac96d2a PB |
1560 | uint16_t cursor_res_b; |
1561 | uint8_t cursor_res_l; | |
1562 | }; | |
1563 | ||
c67a470b | 1564 | /* |
765dab67 PZ |
1565 | * This struct helps tracking the state needed for runtime PM, which puts the |
1566 | * device in PCI D3 state. Notice that when this happens, nothing on the | |
1567 | * graphics device works, even register access, so we don't get interrupts nor | |
1568 | * anything else. | |
c67a470b | 1569 | * |
765dab67 PZ |
1570 | * Every piece of our code that needs to actually touch the hardware needs to |
1571 | * either call intel_runtime_pm_get or call intel_display_power_get with the | |
1572 | * appropriate power domain. | |
a8a8bd54 | 1573 | * |
765dab67 PZ |
1574 | * Our driver uses the autosuspend delay feature, which means we'll only really |
1575 | * suspend if we stay with zero refcount for a certain amount of time. The | |
f458ebbc | 1576 | * default value is currently very conservative (see intel_runtime_pm_enable), but |
765dab67 | 1577 | * it can be changed with the standard runtime PM files from sysfs. |
c67a470b PZ |
1578 | * |
1579 | * The irqs_disabled variable becomes true exactly after we disable the IRQs and | |
1580 | * goes back to false exactly before we reenable the IRQs. We use this variable | |
1581 | * to check if someone is trying to enable/disable IRQs while they're supposed | |
1582 | * to be disabled. This shouldn't happen and we'll print some error messages in | |
730488b2 | 1583 | * case it happens. |
c67a470b | 1584 | * |
765dab67 | 1585 | * For more, read the Documentation/power/runtime_pm.txt. |
c67a470b | 1586 | */ |
5d584b2e PZ |
1587 | struct i915_runtime_pm { |
1588 | bool suspended; | |
2aeb7d3a | 1589 | bool irqs_enabled; |
c67a470b PZ |
1590 | }; |
1591 | ||
926321d5 DV |
1592 | enum intel_pipe_crc_source { |
1593 | INTEL_PIPE_CRC_SOURCE_NONE, | |
1594 | INTEL_PIPE_CRC_SOURCE_PLANE1, | |
1595 | INTEL_PIPE_CRC_SOURCE_PLANE2, | |
1596 | INTEL_PIPE_CRC_SOURCE_PF, | |
5b3a856b | 1597 | INTEL_PIPE_CRC_SOURCE_PIPE, |
3d099a05 DV |
1598 | /* TV/DP on pre-gen5/vlv can't use the pipe source. */ |
1599 | INTEL_PIPE_CRC_SOURCE_TV, | |
1600 | INTEL_PIPE_CRC_SOURCE_DP_B, | |
1601 | INTEL_PIPE_CRC_SOURCE_DP_C, | |
1602 | INTEL_PIPE_CRC_SOURCE_DP_D, | |
46a19188 | 1603 | INTEL_PIPE_CRC_SOURCE_AUTO, |
926321d5 DV |
1604 | INTEL_PIPE_CRC_SOURCE_MAX, |
1605 | }; | |
1606 | ||
8bf1e9f1 | 1607 | struct intel_pipe_crc_entry { |
ac2300d4 | 1608 | uint32_t frame; |
8bf1e9f1 SH |
1609 | uint32_t crc[5]; |
1610 | }; | |
1611 | ||
b2c88f5b | 1612 | #define INTEL_PIPE_CRC_ENTRIES_NR 128 |
8bf1e9f1 | 1613 | struct intel_pipe_crc { |
d538bbdf DL |
1614 | spinlock_t lock; |
1615 | bool opened; /* exclusive access to the result file */ | |
e5f75aca | 1616 | struct intel_pipe_crc_entry *entries; |
926321d5 | 1617 | enum intel_pipe_crc_source source; |
d538bbdf | 1618 | int head, tail; |
07144428 | 1619 | wait_queue_head_t wq; |
8bf1e9f1 SH |
1620 | }; |
1621 | ||
f99d7069 DV |
1622 | struct i915_frontbuffer_tracking { |
1623 | struct mutex lock; | |
1624 | ||
1625 | /* | |
1626 | * Tracking bits for delayed frontbuffer flushing du to gpu activity or | |
1627 | * scheduled flips. | |
1628 | */ | |
1629 | unsigned busy_bits; | |
1630 | unsigned flip_bits; | |
1631 | }; | |
1632 | ||
7225342a MK |
1633 | struct i915_wa_reg { |
1634 | u32 addr; | |
1635 | u32 value; | |
1636 | /* bitmask representing WA bits */ | |
1637 | u32 mask; | |
1638 | }; | |
1639 | ||
1640 | #define I915_MAX_WA_REGS 16 | |
1641 | ||
1642 | struct i915_workarounds { | |
1643 | struct i915_wa_reg reg[I915_MAX_WA_REGS]; | |
1644 | u32 count; | |
1645 | }; | |
1646 | ||
cf9d2890 YZ |
1647 | struct i915_virtual_gpu { |
1648 | bool active; | |
1649 | }; | |
1650 | ||
5f19e2bf JH |
1651 | struct i915_execbuffer_params { |
1652 | struct drm_device *dev; | |
1653 | struct drm_file *file; | |
1654 | uint32_t dispatch_flags; | |
1655 | uint32_t args_batch_start_offset; | |
1656 | uint32_t batch_obj_vm_offset; | |
1657 | struct intel_engine_cs *ring; | |
1658 | struct drm_i915_gem_object *batch_obj; | |
1659 | struct intel_context *ctx; | |
6a6ae79a | 1660 | struct drm_i915_gem_request *request; |
5f19e2bf JH |
1661 | }; |
1662 | ||
77fec556 | 1663 | struct drm_i915_private { |
f4c956ad | 1664 | struct drm_device *dev; |
efab6d8d | 1665 | struct kmem_cache *objects; |
e20d2ab7 | 1666 | struct kmem_cache *vmas; |
efab6d8d | 1667 | struct kmem_cache *requests; |
f4c956ad | 1668 | |
5c969aa7 | 1669 | const struct intel_device_info info; |
f4c956ad DV |
1670 | |
1671 | int relative_constants_mode; | |
1672 | ||
1673 | void __iomem *regs; | |
1674 | ||
907b28c5 | 1675 | struct intel_uncore uncore; |
f4c956ad | 1676 | |
cf9d2890 YZ |
1677 | struct i915_virtual_gpu vgpu; |
1678 | ||
eb805623 DV |
1679 | struct intel_csr csr; |
1680 | ||
1681 | /* Display CSR-related protection */ | |
1682 | struct mutex csr_lock; | |
1683 | ||
5ea6e5e3 | 1684 | struct intel_gmbus gmbus[GMBUS_NUM_PINS]; |
28c70f16 | 1685 | |
f4c956ad DV |
1686 | /** gmbus_mutex protects against concurrent usage of the single hw gmbus |
1687 | * controller on different i2c buses. */ | |
1688 | struct mutex gmbus_mutex; | |
1689 | ||
1690 | /** | |
1691 | * Base address of the gmbus and gpio block. | |
1692 | */ | |
1693 | uint32_t gpio_mmio_base; | |
1694 | ||
b6fdd0f2 SS |
1695 | /* MMIO base address for MIPI regs */ |
1696 | uint32_t mipi_mmio_base; | |
1697 | ||
28c70f16 DV |
1698 | wait_queue_head_t gmbus_wait_queue; |
1699 | ||
f4c956ad | 1700 | struct pci_dev *bridge_dev; |
a4872ba6 | 1701 | struct intel_engine_cs ring[I915_NUM_RINGS]; |
3e78998a | 1702 | struct drm_i915_gem_object *semaphore_obj; |
f72b3435 | 1703 | uint32_t last_seqno, next_seqno; |
f4c956ad | 1704 | |
ba8286fa | 1705 | struct drm_dma_handle *status_page_dmah; |
f4c956ad DV |
1706 | struct resource mch_res; |
1707 | ||
f4c956ad DV |
1708 | /* protects the irq masks */ |
1709 | spinlock_t irq_lock; | |
1710 | ||
84c33a64 SG |
1711 | /* protects the mmio flip data */ |
1712 | spinlock_t mmio_flip_lock; | |
1713 | ||
f8b79e58 ID |
1714 | bool display_irqs_enabled; |
1715 | ||
9ee32fea DV |
1716 | /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */ |
1717 | struct pm_qos_request pm_qos; | |
1718 | ||
a580516d VS |
1719 | /* Sideband mailbox protection */ |
1720 | struct mutex sb_lock; | |
f4c956ad DV |
1721 | |
1722 | /** Cached value of IMR to avoid reads in updating the bitfield */ | |
abd58f01 BW |
1723 | union { |
1724 | u32 irq_mask; | |
1725 | u32 de_irq_mask[I915_MAX_PIPES]; | |
1726 | }; | |
f4c956ad | 1727 | u32 gt_irq_mask; |
605cd25b | 1728 | u32 pm_irq_mask; |
a6706b45 | 1729 | u32 pm_rps_events; |
91d181dd | 1730 | u32 pipestat_irq_mask[I915_MAX_PIPES]; |
f4c956ad | 1731 | |
5fcece80 | 1732 | struct i915_hotplug hotplug; |
5c3fe8b0 | 1733 | struct i915_fbc fbc; |
439d7ac0 | 1734 | struct i915_drrs drrs; |
f4c956ad | 1735 | struct intel_opregion opregion; |
41aa3448 | 1736 | struct intel_vbt_data vbt; |
f4c956ad | 1737 | |
d9ceb816 JB |
1738 | bool preserve_bios_swizzle; |
1739 | ||
f4c956ad DV |
1740 | /* overlay */ |
1741 | struct intel_overlay *overlay; | |
f4c956ad | 1742 | |
58c68779 | 1743 | /* backlight registers and fields in struct intel_panel */ |
07f11d49 | 1744 | struct mutex backlight_lock; |
31ad8ec6 | 1745 | |
f4c956ad | 1746 | /* LVDS info */ |
f4c956ad DV |
1747 | bool no_aux_handshake; |
1748 | ||
e39b999a VS |
1749 | /* protects panel power sequencer state */ |
1750 | struct mutex pps_mutex; | |
1751 | ||
f4c956ad DV |
1752 | struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */ |
1753 | int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */ | |
1754 | int num_fence_regs; /* 8 on pre-965, 16 otherwise */ | |
1755 | ||
1756 | unsigned int fsb_freq, mem_freq, is_ddr3; | |
5d96d8af | 1757 | unsigned int skl_boot_cdclk; |
44913155 | 1758 | unsigned int cdclk_freq, max_cdclk_freq; |
6bcda4f0 | 1759 | unsigned int hpll_freq; |
f4c956ad | 1760 | |
645416f5 DV |
1761 | /** |
1762 | * wq - Driver workqueue for GEM. | |
1763 | * | |
1764 | * NOTE: Work items scheduled here are not allowed to grab any modeset | |
1765 | * locks, for otherwise the flushing done in the pageflip code will | |
1766 | * result in deadlocks. | |
1767 | */ | |
f4c956ad DV |
1768 | struct workqueue_struct *wq; |
1769 | ||
1770 | /* Display functions */ | |
1771 | struct drm_i915_display_funcs display; | |
1772 | ||
1773 | /* PCH chipset type */ | |
1774 | enum intel_pch pch_type; | |
17a303ec | 1775 | unsigned short pch_id; |
f4c956ad DV |
1776 | |
1777 | unsigned long quirks; | |
1778 | ||
b8efb17b ZR |
1779 | enum modeset_restore modeset_restore; |
1780 | struct mutex modeset_restore_lock; | |
673a394b | 1781 | |
a7bbbd63 | 1782 | struct list_head vm_list; /* Global list of all address spaces */ |
0260c420 | 1783 | struct i915_gtt gtt; /* VM representing the global address space */ |
5d4545ae | 1784 | |
4b5aed62 | 1785 | struct i915_gem_mm mm; |
ad46cb53 CW |
1786 | DECLARE_HASHTABLE(mm_structs, 7); |
1787 | struct mutex mm_lock; | |
8781342d | 1788 | |
8781342d DV |
1789 | /* Kernel Modesetting */ |
1790 | ||
9b9d172d | 1791 | struct sdvo_device_mapping sdvo_mappings[2]; |
652c393a | 1792 | |
76c4ac04 DL |
1793 | struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES]; |
1794 | struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES]; | |
6b95a207 KH |
1795 | wait_queue_head_t pending_flip_queue; |
1796 | ||
c4597872 DV |
1797 | #ifdef CONFIG_DEBUG_FS |
1798 | struct intel_pipe_crc pipe_crc[I915_MAX_PIPES]; | |
1799 | #endif | |
1800 | ||
e72f9fbf DV |
1801 | int num_shared_dpll; |
1802 | struct intel_shared_dpll shared_dplls[I915_NUM_PLLS]; | |
e4607fcf | 1803 | int dpio_phy_iosf_port[I915_NUM_PHYS_VLV]; |
ee7b9f93 | 1804 | |
7225342a | 1805 | struct i915_workarounds workarounds; |
888b5995 | 1806 | |
652c393a JB |
1807 | /* Reclocking support */ |
1808 | bool render_reclock_avail; | |
1809 | bool lvds_downclock_avail; | |
18f9ed12 ZY |
1810 | /* indicates the reduced downclock for LVDS*/ |
1811 | int lvds_downclock; | |
f99d7069 DV |
1812 | |
1813 | struct i915_frontbuffer_tracking fb_tracking; | |
1814 | ||
652c393a | 1815 | u16 orig_clock; |
f97108d1 | 1816 | |
c4804411 | 1817 | bool mchbar_need_disable; |
f97108d1 | 1818 | |
a4da4fa4 DV |
1819 | struct intel_l3_parity l3_parity; |
1820 | ||
59124506 BW |
1821 | /* Cannot be determined by PCIID. You must always read a register. */ |
1822 | size_t ellc_size; | |
1823 | ||
c6a828d3 | 1824 | /* gen6+ rps state */ |
c85aa885 | 1825 | struct intel_gen6_power_mgmt rps; |
c6a828d3 | 1826 | |
20e4d407 DV |
1827 | /* ilk-only ips/rps state. Everything in here is protected by the global |
1828 | * mchdev_lock in intel_pm.c */ | |
c85aa885 | 1829 | struct intel_ilk_power_mgmt ips; |
b5e50c3f | 1830 | |
83c00f55 | 1831 | struct i915_power_domains power_domains; |
a38911a3 | 1832 | |
a031d709 | 1833 | struct i915_psr psr; |
3f51e471 | 1834 | |
99584db3 | 1835 | struct i915_gpu_error gpu_error; |
ae681d96 | 1836 | |
c9cddffc JB |
1837 | struct drm_i915_gem_object *vlv_pctx; |
1838 | ||
4520f53a | 1839 | #ifdef CONFIG_DRM_I915_FBDEV |
8be48d92 DA |
1840 | /* list of fbdev register on this device */ |
1841 | struct intel_fbdev *fbdev; | |
82e3b8c1 | 1842 | struct work_struct fbdev_suspend_work; |
4520f53a | 1843 | #endif |
e953fd7b CW |
1844 | |
1845 | struct drm_property *broadcast_rgb_property; | |
3f43c48d | 1846 | struct drm_property *force_audio_property; |
e3689190 | 1847 | |
58fddc28 ID |
1848 | /* hda/i915 audio component */ |
1849 | bool audio_component_registered; | |
1850 | ||
254f965c | 1851 | uint32_t hw_context_size; |
a33afea5 | 1852 | struct list_head context_list; |
f4c956ad | 1853 | |
3e68320e | 1854 | u32 fdi_rx_config; |
68d18ad7 | 1855 | |
70722468 VS |
1856 | u32 chv_phy_control; |
1857 | ||
842f1c8b | 1858 | u32 suspend_count; |
f4c956ad | 1859 | struct i915_suspend_saved_registers regfile; |
ddeea5b0 | 1860 | struct vlv_s0ix_state vlv_s0ix_state; |
231f42a4 | 1861 | |
53615a5e VS |
1862 | struct { |
1863 | /* | |
1864 | * Raw watermark latency values: | |
1865 | * in 0.1us units for WM0, | |
1866 | * in 0.5us units for WM1+. | |
1867 | */ | |
1868 | /* primary */ | |
1869 | uint16_t pri_latency[5]; | |
1870 | /* sprite */ | |
1871 | uint16_t spr_latency[5]; | |
1872 | /* cursor */ | |
1873 | uint16_t cur_latency[5]; | |
2af30a5c PB |
1874 | /* |
1875 | * Raw watermark memory latency values | |
1876 | * for SKL for all 8 levels | |
1877 | * in 1us units. | |
1878 | */ | |
1879 | uint16_t skl_latency[8]; | |
609cedef | 1880 | |
2d41c0b5 PB |
1881 | /* |
1882 | * The skl_wm_values structure is a bit too big for stack | |
1883 | * allocation, so we keep the staging struct where we store | |
1884 | * intermediate results here instead. | |
1885 | */ | |
1886 | struct skl_wm_values skl_results; | |
1887 | ||
609cedef | 1888 | /* current hardware state */ |
2d41c0b5 PB |
1889 | union { |
1890 | struct ilk_wm_values hw; | |
1891 | struct skl_wm_values skl_hw; | |
0018fda1 | 1892 | struct vlv_wm_values vlv; |
2d41c0b5 | 1893 | }; |
53615a5e VS |
1894 | } wm; |
1895 | ||
8a187455 PZ |
1896 | struct i915_runtime_pm pm; |
1897 | ||
a83014d3 OM |
1898 | /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */ |
1899 | struct { | |
5f19e2bf | 1900 | int (*execbuf_submit)(struct i915_execbuffer_params *params, |
f3dc74c0 | 1901 | struct drm_i915_gem_execbuffer2 *args, |
5f19e2bf | 1902 | struct list_head *vmas); |
a83014d3 OM |
1903 | int (*init_rings)(struct drm_device *dev); |
1904 | void (*cleanup_ring)(struct intel_engine_cs *ring); | |
1905 | void (*stop_ring)(struct intel_engine_cs *ring); | |
1906 | } gt; | |
1907 | ||
9e458034 SJ |
1908 | bool edp_low_vswing; |
1909 | ||
bdf1e7e3 DV |
1910 | /* |
1911 | * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch | |
1912 | * will be rejected. Instead look for a better place. | |
1913 | */ | |
77fec556 | 1914 | }; |
1da177e4 | 1915 | |
2c1792a1 CW |
1916 | static inline struct drm_i915_private *to_i915(const struct drm_device *dev) |
1917 | { | |
1918 | return dev->dev_private; | |
1919 | } | |
1920 | ||
888d0d42 ID |
1921 | static inline struct drm_i915_private *dev_to_i915(struct device *dev) |
1922 | { | |
1923 | return to_i915(dev_get_drvdata(dev)); | |
1924 | } | |
1925 | ||
b4519513 CW |
1926 | /* Iterate over initialised rings */ |
1927 | #define for_each_ring(ring__, dev_priv__, i__) \ | |
1928 | for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \ | |
1929 | if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__))) | |
1930 | ||
b1d7e4b4 WF |
1931 | enum hdmi_force_audio { |
1932 | HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */ | |
1933 | HDMI_AUDIO_OFF, /* force turn off HDMI audio */ | |
1934 | HDMI_AUDIO_AUTO, /* trust EDID */ | |
1935 | HDMI_AUDIO_ON, /* force turn on HDMI audio */ | |
1936 | }; | |
1937 | ||
190d6cd5 | 1938 | #define I915_GTT_OFFSET_NONE ((u32)-1) |
ed2f3452 | 1939 | |
37e680a1 CW |
1940 | struct drm_i915_gem_object_ops { |
1941 | /* Interface between the GEM object and its backing storage. | |
1942 | * get_pages() is called once prior to the use of the associated set | |
1943 | * of pages before to binding them into the GTT, and put_pages() is | |
1944 | * called after we no longer need them. As we expect there to be | |
1945 | * associated cost with migrating pages between the backing storage | |
1946 | * and making them available for the GPU (e.g. clflush), we may hold | |
1947 | * onto the pages after they are no longer referenced by the GPU | |
1948 | * in case they may be used again shortly (for example migrating the | |
1949 | * pages to a different memory domain within the GTT). put_pages() | |
1950 | * will therefore most likely be called when the object itself is | |
1951 | * being released or under memory pressure (where we attempt to | |
1952 | * reap pages for the shrinker). | |
1953 | */ | |
1954 | int (*get_pages)(struct drm_i915_gem_object *); | |
1955 | void (*put_pages)(struct drm_i915_gem_object *); | |
5cc9ed4b CW |
1956 | int (*dmabuf_export)(struct drm_i915_gem_object *); |
1957 | void (*release)(struct drm_i915_gem_object *); | |
37e680a1 CW |
1958 | }; |
1959 | ||
a071fa00 DV |
1960 | /* |
1961 | * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is | |
1962 | * considered to be the frontbuffer for the given plane interface-vise. This | |
1963 | * doesn't mean that the hw necessarily already scans it out, but that any | |
1964 | * rendering (by the cpu or gpu) will land in the frontbuffer eventually. | |
1965 | * | |
1966 | * We have one bit per pipe and per scanout plane type. | |
1967 | */ | |
1968 | #define INTEL_FRONTBUFFER_BITS_PER_PIPE 4 | |
1969 | #define INTEL_FRONTBUFFER_BITS \ | |
1970 | (INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES) | |
1971 | #define INTEL_FRONTBUFFER_PRIMARY(pipe) \ | |
1972 | (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))) | |
1973 | #define INTEL_FRONTBUFFER_CURSOR(pipe) \ | |
1974 | (1 << (1 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))) | |
1975 | #define INTEL_FRONTBUFFER_SPRITE(pipe) \ | |
1976 | (1 << (2 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))) | |
1977 | #define INTEL_FRONTBUFFER_OVERLAY(pipe) \ | |
1978 | (1 << (3 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))) | |
cc36513c DV |
1979 | #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \ |
1980 | (0xf << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))) | |
a071fa00 | 1981 | |
673a394b | 1982 | struct drm_i915_gem_object { |
c397b908 | 1983 | struct drm_gem_object base; |
673a394b | 1984 | |
37e680a1 CW |
1985 | const struct drm_i915_gem_object_ops *ops; |
1986 | ||
2f633156 BW |
1987 | /** List of VMAs backed by this object */ |
1988 | struct list_head vma_list; | |
1989 | ||
c1ad11fc CW |
1990 | /** Stolen memory for this object, instead of being backed by shmem. */ |
1991 | struct drm_mm_node *stolen; | |
35c20a60 | 1992 | struct list_head global_list; |
673a394b | 1993 | |
b4716185 | 1994 | struct list_head ring_list[I915_NUM_RINGS]; |
b25cb2f8 BW |
1995 | /** Used in execbuf to temporarily hold a ref */ |
1996 | struct list_head obj_exec_link; | |
673a394b | 1997 | |
8d9d5744 | 1998 | struct list_head batch_pool_link; |
493018dc | 1999 | |
673a394b | 2000 | /** |
65ce3027 CW |
2001 | * This is set if the object is on the active lists (has pending |
2002 | * rendering and so a non-zero seqno), and is not set if it i s on | |
2003 | * inactive (ready to be unbound) list. | |
673a394b | 2004 | */ |
b4716185 | 2005 | unsigned int active:I915_NUM_RINGS; |
673a394b EA |
2006 | |
2007 | /** | |
2008 | * This is set if the object has been written to since last bound | |
2009 | * to the GTT | |
2010 | */ | |
0206e353 | 2011 | unsigned int dirty:1; |
778c3544 DV |
2012 | |
2013 | /** | |
2014 | * Fence register bits (if any) for this object. Will be set | |
2015 | * as needed when mapped into the GTT. | |
2016 | * Protected by dev->struct_mutex. | |
778c3544 | 2017 | */ |
4b9de737 | 2018 | signed int fence_reg:I915_MAX_NUM_FENCE_BITS; |
778c3544 | 2019 | |
778c3544 DV |
2020 | /** |
2021 | * Advice: are the backing pages purgeable? | |
2022 | */ | |
0206e353 | 2023 | unsigned int madv:2; |
778c3544 | 2024 | |
778c3544 DV |
2025 | /** |
2026 | * Current tiling mode for the object. | |
2027 | */ | |
0206e353 | 2028 | unsigned int tiling_mode:2; |
5d82e3e6 CW |
2029 | /** |
2030 | * Whether the tiling parameters for the currently associated fence | |
2031 | * register have changed. Note that for the purposes of tracking | |
2032 | * tiling changes we also treat the unfenced register, the register | |
2033 | * slot that the object occupies whilst it executes a fenced | |
2034 | * command (such as BLT on gen2/3), as a "fence". | |
2035 | */ | |
2036 | unsigned int fence_dirty:1; | |
778c3544 | 2037 | |
75e9e915 DV |
2038 | /** |
2039 | * Is the object at the current location in the gtt mappable and | |
2040 | * fenceable? Used to avoid costly recalculations. | |
2041 | */ | |
0206e353 | 2042 | unsigned int map_and_fenceable:1; |
75e9e915 | 2043 | |
fb7d516a DV |
2044 | /** |
2045 | * Whether the current gtt mapping needs to be mappable (and isn't just | |
2046 | * mappable by accident). Track pin and fault separate for a more | |
2047 | * accurate mappable working set. | |
2048 | */ | |
0206e353 | 2049 | unsigned int fault_mappable:1; |
fb7d516a | 2050 | |
24f3a8cf AG |
2051 | /* |
2052 | * Is the object to be mapped as read-only to the GPU | |
2053 | * Only honoured if hardware has relevant pte bit | |
2054 | */ | |
2055 | unsigned long gt_ro:1; | |
651d794f | 2056 | unsigned int cache_level:3; |
0f71979a | 2057 | unsigned int cache_dirty:1; |
93dfb40c | 2058 | |
9da3da66 | 2059 | unsigned int has_dma_mapping:1; |
7bddb01f | 2060 | |
a071fa00 DV |
2061 | unsigned int frontbuffer_bits:INTEL_FRONTBUFFER_BITS; |
2062 | ||
8a0c39b1 TU |
2063 | unsigned int pin_display; |
2064 | ||
9da3da66 | 2065 | struct sg_table *pages; |
a5570178 | 2066 | int pages_pin_count; |
ee286370 CW |
2067 | struct get_page { |
2068 | struct scatterlist *sg; | |
2069 | int last; | |
2070 | } get_page; | |
673a394b | 2071 | |
1286ff73 | 2072 | /* prime dma-buf support */ |
9a70cc2a DA |
2073 | void *dma_buf_vmapping; |
2074 | int vmapping_count; | |
2075 | ||
b4716185 CW |
2076 | /** Breadcrumb of last rendering to the buffer. |
2077 | * There can only be one writer, but we allow for multiple readers. | |
2078 | * If there is a writer that necessarily implies that all other | |
2079 | * read requests are complete - but we may only be lazily clearing | |
2080 | * the read requests. A read request is naturally the most recent | |
2081 | * request on a ring, so we may have two different write and read | |
2082 | * requests on one ring where the write request is older than the | |
2083 | * read request. This allows for the CPU to read from an active | |
2084 | * buffer by only waiting for the write to complete. | |
2085 | * */ | |
2086 | struct drm_i915_gem_request *last_read_req[I915_NUM_RINGS]; | |
97b2a6a1 | 2087 | struct drm_i915_gem_request *last_write_req; |
caea7476 | 2088 | /** Breadcrumb of last fenced GPU access to the buffer. */ |
97b2a6a1 | 2089 | struct drm_i915_gem_request *last_fenced_req; |
673a394b | 2090 | |
778c3544 | 2091 | /** Current tiling stride for the object, if it's tiled. */ |
de151cf6 | 2092 | uint32_t stride; |
673a394b | 2093 | |
80075d49 DV |
2094 | /** References from framebuffers, locks out tiling changes. */ |
2095 | unsigned long framebuffer_references; | |
2096 | ||
280b713b | 2097 | /** Record of address bit 17 of each page at last unbind. */ |
d312ec25 | 2098 | unsigned long *bit_17; |
280b713b | 2099 | |
5cc9ed4b | 2100 | union { |
6a2c4232 CW |
2101 | /** for phy allocated objects */ |
2102 | struct drm_dma_handle *phys_handle; | |
2103 | ||
5cc9ed4b CW |
2104 | struct i915_gem_userptr { |
2105 | uintptr_t ptr; | |
2106 | unsigned read_only :1; | |
2107 | unsigned workers :4; | |
2108 | #define I915_GEM_USERPTR_MAX_WORKERS 15 | |
2109 | ||
ad46cb53 CW |
2110 | struct i915_mm_struct *mm; |
2111 | struct i915_mmu_object *mmu_object; | |
5cc9ed4b CW |
2112 | struct work_struct *work; |
2113 | } userptr; | |
2114 | }; | |
2115 | }; | |
62b8b215 | 2116 | #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base) |
23010e43 | 2117 | |
a071fa00 DV |
2118 | void i915_gem_track_fb(struct drm_i915_gem_object *old, |
2119 | struct drm_i915_gem_object *new, | |
2120 | unsigned frontbuffer_bits); | |
2121 | ||
673a394b EA |
2122 | /** |
2123 | * Request queue structure. | |
2124 | * | |
2125 | * The request queue allows us to note sequence numbers that have been emitted | |
2126 | * and may be associated with active buffers to be retired. | |
2127 | * | |
97b2a6a1 JH |
2128 | * By keeping this list, we can avoid having to do questionable sequence |
2129 | * number comparisons on buffer last_read|write_seqno. It also allows an | |
2130 | * emission time to be associated with the request for tracking how far ahead | |
2131 | * of the GPU the submission is. | |
b3a38998 NH |
2132 | * |
2133 | * The requests are reference counted, so upon creation they should have an | |
2134 | * initial reference taken using kref_init | |
673a394b EA |
2135 | */ |
2136 | struct drm_i915_gem_request { | |
abfe262a JH |
2137 | struct kref ref; |
2138 | ||
852835f3 | 2139 | /** On Which ring this request was generated */ |
efab6d8d | 2140 | struct drm_i915_private *i915; |
a4872ba6 | 2141 | struct intel_engine_cs *ring; |
852835f3 | 2142 | |
673a394b EA |
2143 | /** GEM sequence number associated with this request. */ |
2144 | uint32_t seqno; | |
2145 | ||
7d736f4f MK |
2146 | /** Position in the ringbuffer of the start of the request */ |
2147 | u32 head; | |
2148 | ||
72f95afa NH |
2149 | /** |
2150 | * Position in the ringbuffer of the start of the postfix. | |
2151 | * This is required to calculate the maximum available ringbuffer | |
2152 | * space without overwriting the postfix. | |
2153 | */ | |
2154 | u32 postfix; | |
2155 | ||
2156 | /** Position in the ringbuffer of the end of the whole request */ | |
a71d8d94 CW |
2157 | u32 tail; |
2158 | ||
b3a38998 | 2159 | /** |
a8c6ecb3 | 2160 | * Context and ring buffer related to this request |
b3a38998 NH |
2161 | * Contexts are refcounted, so when this request is associated with a |
2162 | * context, we must increment the context's refcount, to guarantee that | |
2163 | * it persists while any request is linked to it. Requests themselves | |
2164 | * are also refcounted, so the request will only be freed when the last | |
2165 | * reference to it is dismissed, and the code in | |
2166 | * i915_gem_request_free() will then decrement the refcount on the | |
2167 | * context. | |
2168 | */ | |
273497e5 | 2169 | struct intel_context *ctx; |
98e1bd4a | 2170 | struct intel_ringbuffer *ringbuf; |
0e50e96b | 2171 | |
7d736f4f MK |
2172 | /** Batch buffer related to this request if any */ |
2173 | struct drm_i915_gem_object *batch_obj; | |
2174 | ||
673a394b EA |
2175 | /** Time at which this request was emitted, in jiffies. */ |
2176 | unsigned long emitted_jiffies; | |
2177 | ||
b962442e | 2178 | /** global list entry for this request */ |
673a394b | 2179 | struct list_head list; |
b962442e | 2180 | |
f787a5f5 | 2181 | struct drm_i915_file_private *file_priv; |
b962442e EA |
2182 | /** file_priv list entry for this request */ |
2183 | struct list_head client_list; | |
67e2937b | 2184 | |
071c92de MK |
2185 | /** process identifier submitting this request */ |
2186 | struct pid *pid; | |
2187 | ||
6d3d8274 NH |
2188 | /** |
2189 | * The ELSP only accepts two elements at a time, so we queue | |
2190 | * context/tail pairs on a given queue (ring->execlist_queue) until the | |
2191 | * hardware is available. The queue serves a double purpose: we also use | |
2192 | * it to keep track of the up to 2 contexts currently in the hardware | |
2193 | * (usually one in execution and the other queued up by the GPU): We | |
2194 | * only remove elements from the head of the queue when the hardware | |
2195 | * informs us that an element has been completed. | |
2196 | * | |
2197 | * All accesses to the queue are mediated by a spinlock | |
2198 | * (ring->execlist_lock). | |
2199 | */ | |
2200 | ||
2201 | /** Execlist link in the submission queue.*/ | |
2202 | struct list_head execlist_link; | |
2203 | ||
2204 | /** Execlists no. of times this request has been sent to the ELSP */ | |
2205 | int elsp_submitted; | |
2206 | ||
673a394b EA |
2207 | }; |
2208 | ||
6689cb2b | 2209 | int i915_gem_request_alloc(struct intel_engine_cs *ring, |
217e46b5 JH |
2210 | struct intel_context *ctx, |
2211 | struct drm_i915_gem_request **req_out); | |
29b1b415 | 2212 | void i915_gem_request_cancel(struct drm_i915_gem_request *req); |
abfe262a JH |
2213 | void i915_gem_request_free(struct kref *req_ref); |
2214 | ||
b793a00a JH |
2215 | static inline uint32_t |
2216 | i915_gem_request_get_seqno(struct drm_i915_gem_request *req) | |
2217 | { | |
2218 | return req ? req->seqno : 0; | |
2219 | } | |
2220 | ||
2221 | static inline struct intel_engine_cs * | |
2222 | i915_gem_request_get_ring(struct drm_i915_gem_request *req) | |
2223 | { | |
2224 | return req ? req->ring : NULL; | |
2225 | } | |
2226 | ||
b2cfe0ab | 2227 | static inline struct drm_i915_gem_request * |
abfe262a JH |
2228 | i915_gem_request_reference(struct drm_i915_gem_request *req) |
2229 | { | |
b2cfe0ab CW |
2230 | if (req) |
2231 | kref_get(&req->ref); | |
2232 | return req; | |
abfe262a JH |
2233 | } |
2234 | ||
2235 | static inline void | |
2236 | i915_gem_request_unreference(struct drm_i915_gem_request *req) | |
2237 | { | |
f245860e | 2238 | WARN_ON(!mutex_is_locked(&req->ring->dev->struct_mutex)); |
abfe262a JH |
2239 | kref_put(&req->ref, i915_gem_request_free); |
2240 | } | |
2241 | ||
41037f9f CW |
2242 | static inline void |
2243 | i915_gem_request_unreference__unlocked(struct drm_i915_gem_request *req) | |
2244 | { | |
b833bb61 ML |
2245 | struct drm_device *dev; |
2246 | ||
2247 | if (!req) | |
2248 | return; | |
41037f9f | 2249 | |
b833bb61 ML |
2250 | dev = req->ring->dev; |
2251 | if (kref_put_mutex(&req->ref, i915_gem_request_free, &dev->struct_mutex)) | |
41037f9f | 2252 | mutex_unlock(&dev->struct_mutex); |
41037f9f CW |
2253 | } |
2254 | ||
abfe262a JH |
2255 | static inline void i915_gem_request_assign(struct drm_i915_gem_request **pdst, |
2256 | struct drm_i915_gem_request *src) | |
2257 | { | |
2258 | if (src) | |
2259 | i915_gem_request_reference(src); | |
2260 | ||
2261 | if (*pdst) | |
2262 | i915_gem_request_unreference(*pdst); | |
2263 | ||
2264 | *pdst = src; | |
2265 | } | |
2266 | ||
1b5a433a JH |
2267 | /* |
2268 | * XXX: i915_gem_request_completed should be here but currently needs the | |
2269 | * definition of i915_seqno_passed() which is below. It will be moved in | |
2270 | * a later patch when the call to i915_seqno_passed() is obsoleted... | |
2271 | */ | |
2272 | ||
351e3db2 BV |
2273 | /* |
2274 | * A command that requires special handling by the command parser. | |
2275 | */ | |
2276 | struct drm_i915_cmd_descriptor { | |
2277 | /* | |
2278 | * Flags describing how the command parser processes the command. | |
2279 | * | |
2280 | * CMD_DESC_FIXED: The command has a fixed length if this is set, | |
2281 | * a length mask if not set | |
2282 | * CMD_DESC_SKIP: The command is allowed but does not follow the | |
2283 | * standard length encoding for the opcode range in | |
2284 | * which it falls | |
2285 | * CMD_DESC_REJECT: The command is never allowed | |
2286 | * CMD_DESC_REGISTER: The command should be checked against the | |
2287 | * register whitelist for the appropriate ring | |
2288 | * CMD_DESC_MASTER: The command is allowed if the submitting process | |
2289 | * is the DRM master | |
2290 | */ | |
2291 | u32 flags; | |
2292 | #define CMD_DESC_FIXED (1<<0) | |
2293 | #define CMD_DESC_SKIP (1<<1) | |
2294 | #define CMD_DESC_REJECT (1<<2) | |
2295 | #define CMD_DESC_REGISTER (1<<3) | |
2296 | #define CMD_DESC_BITMASK (1<<4) | |
2297 | #define CMD_DESC_MASTER (1<<5) | |
2298 | ||
2299 | /* | |
2300 | * The command's unique identification bits and the bitmask to get them. | |
2301 | * This isn't strictly the opcode field as defined in the spec and may | |
2302 | * also include type, subtype, and/or subop fields. | |
2303 | */ | |
2304 | struct { | |
2305 | u32 value; | |
2306 | u32 mask; | |
2307 | } cmd; | |
2308 | ||
2309 | /* | |
2310 | * The command's length. The command is either fixed length (i.e. does | |
2311 | * not include a length field) or has a length field mask. The flag | |
2312 | * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has | |
2313 | * a length mask. All command entries in a command table must include | |
2314 | * length information. | |
2315 | */ | |
2316 | union { | |
2317 | u32 fixed; | |
2318 | u32 mask; | |
2319 | } length; | |
2320 | ||
2321 | /* | |
2322 | * Describes where to find a register address in the command to check | |
2323 | * against the ring's register whitelist. Only valid if flags has the | |
2324 | * CMD_DESC_REGISTER bit set. | |
6a65c5b9 FJ |
2325 | * |
2326 | * A non-zero step value implies that the command may access multiple | |
2327 | * registers in sequence (e.g. LRI), in that case step gives the | |
2328 | * distance in dwords between individual offset fields. | |
351e3db2 BV |
2329 | */ |
2330 | struct { | |
2331 | u32 offset; | |
2332 | u32 mask; | |
6a65c5b9 | 2333 | u32 step; |
351e3db2 BV |
2334 | } reg; |
2335 | ||
2336 | #define MAX_CMD_DESC_BITMASKS 3 | |
2337 | /* | |
2338 | * Describes command checks where a particular dword is masked and | |
2339 | * compared against an expected value. If the command does not match | |
2340 | * the expected value, the parser rejects it. Only valid if flags has | |
2341 | * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero | |
2342 | * are valid. | |
d4d48035 BV |
2343 | * |
2344 | * If the check specifies a non-zero condition_mask then the parser | |
2345 | * only performs the check when the bits specified by condition_mask | |
2346 | * are non-zero. | |
351e3db2 BV |
2347 | */ |
2348 | struct { | |
2349 | u32 offset; | |
2350 | u32 mask; | |
2351 | u32 expected; | |
d4d48035 BV |
2352 | u32 condition_offset; |
2353 | u32 condition_mask; | |
351e3db2 BV |
2354 | } bits[MAX_CMD_DESC_BITMASKS]; |
2355 | }; | |
2356 | ||
2357 | /* | |
2358 | * A table of commands requiring special handling by the command parser. | |
2359 | * | |
2360 | * Each ring has an array of tables. Each table consists of an array of command | |
2361 | * descriptors, which must be sorted with command opcodes in ascending order. | |
2362 | */ | |
2363 | struct drm_i915_cmd_table { | |
2364 | const struct drm_i915_cmd_descriptor *table; | |
2365 | int count; | |
2366 | }; | |
2367 | ||
dbbe9127 | 2368 | /* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */ |
7312e2dd CW |
2369 | #define __I915__(p) ({ \ |
2370 | struct drm_i915_private *__p; \ | |
2371 | if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \ | |
2372 | __p = (struct drm_i915_private *)p; \ | |
2373 | else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \ | |
2374 | __p = to_i915((struct drm_device *)p); \ | |
2375 | else \ | |
2376 | BUILD_BUG(); \ | |
2377 | __p; \ | |
2378 | }) | |
dbbe9127 | 2379 | #define INTEL_INFO(p) (&__I915__(p)->info) |
87f1f465 | 2380 | #define INTEL_DEVID(p) (INTEL_INFO(p)->device_id) |
e90a21d4 | 2381 | #define INTEL_REVID(p) (__I915__(p)->dev->pdev->revision) |
cae5852d | 2382 | |
87f1f465 CW |
2383 | #define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577) |
2384 | #define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562) | |
cae5852d | 2385 | #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x) |
87f1f465 | 2386 | #define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572) |
cae5852d | 2387 | #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g) |
87f1f465 CW |
2388 | #define IS_I915GM(dev) (INTEL_DEVID(dev) == 0x2592) |
2389 | #define IS_I945G(dev) (INTEL_DEVID(dev) == 0x2772) | |
cae5852d ZN |
2390 | #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm) |
2391 | #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater) | |
2392 | #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline) | |
87f1f465 | 2393 | #define IS_GM45(dev) (INTEL_DEVID(dev) == 0x2A42) |
cae5852d | 2394 | #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x) |
87f1f465 CW |
2395 | #define IS_PINEVIEW_G(dev) (INTEL_DEVID(dev) == 0xa001) |
2396 | #define IS_PINEVIEW_M(dev) (INTEL_DEVID(dev) == 0xa011) | |
cae5852d ZN |
2397 | #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview) |
2398 | #define IS_G33(dev) (INTEL_INFO(dev)->is_g33) | |
87f1f465 | 2399 | #define IS_IRONLAKE_M(dev) (INTEL_DEVID(dev) == 0x0046) |
4b65177b | 2400 | #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge) |
87f1f465 CW |
2401 | #define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 || \ |
2402 | INTEL_DEVID(dev) == 0x0152 || \ | |
2403 | INTEL_DEVID(dev) == 0x015a) | |
70a3eb7a | 2404 | #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview) |
6df4027b | 2405 | #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev)) |
4cae9ae0 | 2406 | #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell) |
8179f1f0 | 2407 | #define IS_BROADWELL(dev) (!INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev)) |
7201c0b3 | 2408 | #define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake) |
1feed885 | 2409 | #define IS_BROXTON(dev) (!INTEL_INFO(dev)->is_skylake && IS_GEN9(dev)) |
cae5852d | 2410 | #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) |
ed1c9e2c | 2411 | #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \ |
87f1f465 | 2412 | (INTEL_DEVID(dev) & 0xFF00) == 0x0C00) |
5dd8c4c3 | 2413 | #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \ |
6b96d705 | 2414 | ((INTEL_DEVID(dev) & 0xf) == 0x6 || \ |
0dc6f20b | 2415 | (INTEL_DEVID(dev) & 0xf) == 0xb || \ |
87f1f465 | 2416 | (INTEL_DEVID(dev) & 0xf) == 0xe)) |
ebb72aad VS |
2417 | /* ULX machines are also considered ULT. */ |
2418 | #define IS_BDW_ULX(dev) (IS_BROADWELL(dev) && \ | |
2419 | (INTEL_DEVID(dev) & 0xf) == 0xe) | |
a0fcbd95 RV |
2420 | #define IS_BDW_GT3(dev) (IS_BROADWELL(dev) && \ |
2421 | (INTEL_DEVID(dev) & 0x00F0) == 0x0020) | |
5dd8c4c3 | 2422 | #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \ |
87f1f465 | 2423 | (INTEL_DEVID(dev) & 0xFF00) == 0x0A00) |
9435373e | 2424 | #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \ |
87f1f465 | 2425 | (INTEL_DEVID(dev) & 0x00F0) == 0x0020) |
9bbfd20a | 2426 | /* ULX machines are also considered ULT. */ |
87f1f465 CW |
2427 | #define IS_HSW_ULX(dev) (INTEL_DEVID(dev) == 0x0A0E || \ |
2428 | INTEL_DEVID(dev) == 0x0A1E) | |
b833d685 | 2429 | #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary) |
cae5852d | 2430 | |
e90a21d4 HN |
2431 | #define SKL_REVID_A0 (0x0) |
2432 | #define SKL_REVID_B0 (0x1) | |
2433 | #define SKL_REVID_C0 (0x2) | |
2434 | #define SKL_REVID_D0 (0x3) | |
8bc0ccf6 | 2435 | #define SKL_REVID_E0 (0x4) |
b88baa2a | 2436 | #define SKL_REVID_F0 (0x5) |
e90a21d4 | 2437 | |
6c74c87f NH |
2438 | #define BXT_REVID_A0 (0x0) |
2439 | #define BXT_REVID_B0 (0x3) | |
2440 | #define BXT_REVID_C0 (0x6) | |
2441 | ||
85436696 JB |
2442 | /* |
2443 | * The genX designation typically refers to the render engine, so render | |
2444 | * capability related checks should use IS_GEN, while display and other checks | |
2445 | * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular | |
2446 | * chips, etc.). | |
2447 | */ | |
cae5852d ZN |
2448 | #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2) |
2449 | #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3) | |
2450 | #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4) | |
2451 | #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5) | |
2452 | #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6) | |
85436696 | 2453 | #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7) |
d2980845 | 2454 | #define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8) |
b71252dc | 2455 | #define IS_GEN9(dev) (INTEL_INFO(dev)->gen == 9) |
cae5852d | 2456 | |
73ae478c BW |
2457 | #define RENDER_RING (1<<RCS) |
2458 | #define BSD_RING (1<<VCS) | |
2459 | #define BLT_RING (1<<BCS) | |
2460 | #define VEBOX_RING (1<<VECS) | |
845f74a7 | 2461 | #define BSD2_RING (1<<VCS2) |
63c42e56 | 2462 | #define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING) |
845f74a7 | 2463 | #define HAS_BSD2(dev) (INTEL_INFO(dev)->ring_mask & BSD2_RING) |
63c42e56 BW |
2464 | #define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING) |
2465 | #define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING) | |
2466 | #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc) | |
2467 | #define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \ | |
f2fbc690 | 2468 | __I915__(dev)->ellc_size) |
cae5852d ZN |
2469 | #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws) |
2470 | ||
254f965c | 2471 | #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6) |
d7f621e5 | 2472 | #define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 8) |
692ef70c JB |
2473 | #define USES_PPGTT(dev) (i915.enable_ppgtt) |
2474 | #define USES_FULL_PPGTT(dev) (i915.enable_ppgtt == 2) | |
1d2a314c | 2475 | |
05394f39 | 2476 | #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay) |
cae5852d ZN |
2477 | #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical) |
2478 | ||
b45305fc DV |
2479 | /* Early gen2 have a totally busted CS tlb and require pinned batches. */ |
2480 | #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev)) | |
4e6b788c DV |
2481 | /* |
2482 | * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts | |
2483 | * even when in MSI mode. This results in spurious interrupt warnings if the | |
2484 | * legacy irq no. is shared with another device. The kernel then disables that | |
2485 | * interrupt source and so prevents the other device from working properly. | |
2486 | */ | |
2487 | #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5) | |
2488 | #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5) | |
b45305fc | 2489 | |
cae5852d ZN |
2490 | /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte |
2491 | * rows, which changed the alignment requirements and fence programming. | |
2492 | */ | |
2493 | #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \ | |
2494 | IS_I915GM(dev))) | |
2495 | #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) | |
2496 | #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev)) | |
2497 | #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev)) | |
cae5852d ZN |
2498 | #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv) |
2499 | #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug) | |
cae5852d ZN |
2500 | |
2501 | #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2) | |
2502 | #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr) | |
3a77c4c4 | 2503 | #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc) |
cae5852d | 2504 | |
dbf7786e | 2505 | #define HAS_IPS(dev) (IS_HSW_ULT(dev) || IS_BROADWELL(dev)) |
f5adf94e | 2506 | |
0c9b3715 JN |
2507 | #define HAS_DP_MST(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \ |
2508 | INTEL_INFO(dev)->gen >= 9) | |
2509 | ||
dd93be58 | 2510 | #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi) |
30568c45 | 2511 | #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg) |
b32c6f48 | 2512 | #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \ |
e3d99845 SJ |
2513 | IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || \ |
2514 | IS_SKYLAKE(dev)) | |
6157d3c8 | 2515 | #define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \ |
00776511 SS |
2516 | IS_BROADWELL(dev) || IS_VALLEYVIEW(dev) || \ |
2517 | IS_SKYLAKE(dev)) | |
58abf1da RV |
2518 | #define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6) |
2519 | #define HAS_RC6p(dev) (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev)) | |
affa9354 | 2520 | |
eb805623 DV |
2521 | #define HAS_CSR(dev) (IS_SKYLAKE(dev)) |
2522 | ||
17a303ec PZ |
2523 | #define INTEL_PCH_DEVICE_ID_MASK 0xff00 |
2524 | #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00 | |
2525 | #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00 | |
2526 | #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00 | |
2527 | #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00 | |
2528 | #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00 | |
e7e7ea20 S |
2529 | #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100 |
2530 | #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00 | |
17a303ec | 2531 | |
f2fbc690 | 2532 | #define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type) |
e7e7ea20 | 2533 | #define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT) |
eb877ebf | 2534 | #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT) |
cae5852d ZN |
2535 | #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT) |
2536 | #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX) | |
40c7ead9 | 2537 | #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP) |
45e6e3a1 | 2538 | #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE) |
cae5852d | 2539 | |
5fafe292 SJ |
2540 | #define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev)) |
2541 | ||
040d2baa BW |
2542 | /* DPF == dynamic parity feature */ |
2543 | #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) | |
2544 | #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev)) | |
e1ef7cc2 | 2545 | |
c8735b0c | 2546 | #define GT_FREQUENCY_MULTIPLIER 50 |
de43ae9d | 2547 | #define GEN9_FREQ_SCALER 3 |
c8735b0c | 2548 | |
05394f39 CW |
2549 | #include "i915_trace.h" |
2550 | ||
baa70943 | 2551 | extern const struct drm_ioctl_desc i915_ioctls[]; |
b3a83639 DA |
2552 | extern int i915_max_ioctl; |
2553 | ||
fc49b3da ID |
2554 | extern int i915_suspend_legacy(struct drm_device *dev, pm_message_t state); |
2555 | extern int i915_resume_legacy(struct drm_device *dev); | |
7c1c2871 | 2556 | |
d330a953 JN |
2557 | /* i915_params.c */ |
2558 | struct i915_params { | |
2559 | int modeset; | |
2560 | int panel_ignore_lid; | |
d330a953 JN |
2561 | int semaphores; |
2562 | unsigned int lvds_downclock; | |
2563 | int lvds_channel_mode; | |
2564 | int panel_use_ssc; | |
2565 | int vbt_sdvo_panel_type; | |
2566 | int enable_rc6; | |
2567 | int enable_fbc; | |
d330a953 | 2568 | int enable_ppgtt; |
127f1003 | 2569 | int enable_execlists; |
d330a953 JN |
2570 | int enable_psr; |
2571 | unsigned int preliminary_hw_support; | |
2572 | int disable_power_well; | |
2573 | int enable_ips; | |
e5aa6541 | 2574 | int invert_brightness; |
351e3db2 | 2575 | int enable_cmd_parser; |
e5aa6541 DL |
2576 | /* leave bools at the end to not create holes */ |
2577 | bool enable_hangcheck; | |
2578 | bool fastboot; | |
d330a953 | 2579 | bool prefault_disable; |
5bedeb2d | 2580 | bool load_detect_test; |
d330a953 | 2581 | bool reset; |
a0bae57f | 2582 | bool disable_display; |
7a10dfa6 | 2583 | bool disable_vtd_wa; |
84c33a64 | 2584 | int use_mmio_flip; |
48572edd | 2585 | int mmio_debug; |
e2c719b7 | 2586 | bool verbose_state_checks; |
b2e7723b | 2587 | bool nuclear_pageflip; |
9e458034 | 2588 | int edp_vswing; |
d330a953 JN |
2589 | }; |
2590 | extern struct i915_params i915 __read_mostly; | |
2591 | ||
1da177e4 | 2592 | /* i915_dma.c */ |
22eae947 | 2593 | extern int i915_driver_load(struct drm_device *, unsigned long flags); |
ba8bbcf6 | 2594 | extern int i915_driver_unload(struct drm_device *); |
2885f6ac | 2595 | extern int i915_driver_open(struct drm_device *dev, struct drm_file *file); |
84b1fd10 | 2596 | extern void i915_driver_lastclose(struct drm_device * dev); |
6c340eac | 2597 | extern void i915_driver_preclose(struct drm_device *dev, |
2885f6ac | 2598 | struct drm_file *file); |
673a394b | 2599 | extern void i915_driver_postclose(struct drm_device *dev, |
2885f6ac | 2600 | struct drm_file *file); |
84b1fd10 | 2601 | extern int i915_driver_device_is_agp(struct drm_device * dev); |
c43b5634 | 2602 | #ifdef CONFIG_COMPAT |
0d6aa60b DA |
2603 | extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, |
2604 | unsigned long arg); | |
c43b5634 | 2605 | #endif |
8e96d9c4 | 2606 | extern int intel_gpu_reset(struct drm_device *dev); |
49e4d842 | 2607 | extern bool intel_has_gpu_reset(struct drm_device *dev); |
d4b8bb2a | 2608 | extern int i915_reset(struct drm_device *dev); |
7648fa99 JB |
2609 | extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv); |
2610 | extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv); | |
2611 | extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv); | |
2612 | extern void i915_update_gfx_val(struct drm_i915_private *dev_priv); | |
650ad970 | 2613 | int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on); |
eb805623 | 2614 | void i915_firmware_load_error_print(const char *fw_path, int err); |
7648fa99 | 2615 | |
77913b39 JN |
2616 | /* intel_hotplug.c */ |
2617 | void intel_hpd_irq_handler(struct drm_device *dev, u32 pin_mask, u32 long_mask); | |
2618 | void intel_hpd_init(struct drm_i915_private *dev_priv); | |
2619 | void intel_hpd_init_work(struct drm_i915_private *dev_priv); | |
2620 | void intel_hpd_cancel_work(struct drm_i915_private *dev_priv); | |
2621 | enum port intel_hpd_pin_to_port(enum hpd_pin pin); | |
2622 | ||
1da177e4 | 2623 | /* i915_irq.c */ |
10cd45b6 | 2624 | void i915_queue_hangcheck(struct drm_device *dev); |
58174462 MK |
2625 | __printf(3, 4) |
2626 | void i915_handle_error(struct drm_device *dev, bool wedged, | |
2627 | const char *fmt, ...); | |
1da177e4 | 2628 | |
b963291c | 2629 | extern void intel_irq_init(struct drm_i915_private *dev_priv); |
2aeb7d3a DV |
2630 | int intel_irq_install(struct drm_i915_private *dev_priv); |
2631 | void intel_irq_uninstall(struct drm_i915_private *dev_priv); | |
907b28c5 CW |
2632 | |
2633 | extern void intel_uncore_sanitize(struct drm_device *dev); | |
10018603 ID |
2634 | extern void intel_uncore_early_sanitize(struct drm_device *dev, |
2635 | bool restore_forcewake); | |
907b28c5 | 2636 | extern void intel_uncore_init(struct drm_device *dev); |
907b28c5 | 2637 | extern void intel_uncore_check_errors(struct drm_device *dev); |
aec347ab | 2638 | extern void intel_uncore_fini(struct drm_device *dev); |
156c7ca0 | 2639 | extern void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore); |
48c1026a | 2640 | const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id); |
59bad947 | 2641 | void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv, |
48c1026a | 2642 | enum forcewake_domains domains); |
59bad947 | 2643 | void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv, |
48c1026a | 2644 | enum forcewake_domains domains); |
a6111f7b CW |
2645 | /* Like above but the caller must manage the uncore.lock itself. |
2646 | * Must be used with I915_READ_FW and friends. | |
2647 | */ | |
2648 | void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv, | |
2649 | enum forcewake_domains domains); | |
2650 | void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv, | |
2651 | enum forcewake_domains domains); | |
59bad947 | 2652 | void assert_forcewakes_inactive(struct drm_i915_private *dev_priv); |
cf9d2890 YZ |
2653 | static inline bool intel_vgpu_active(struct drm_device *dev) |
2654 | { | |
2655 | return to_i915(dev)->vgpu.active; | |
2656 | } | |
b1f14ad0 | 2657 | |
7c463586 | 2658 | void |
50227e1c | 2659 | i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, |
755e9019 | 2660 | u32 status_mask); |
7c463586 KP |
2661 | |
2662 | void | |
50227e1c | 2663 | i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, |
755e9019 | 2664 | u32 status_mask); |
7c463586 | 2665 | |
f8b79e58 ID |
2666 | void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv); |
2667 | void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv); | |
47339cd9 DV |
2668 | void |
2669 | ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask); | |
2670 | void | |
2671 | ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask); | |
2672 | void ibx_display_interrupt_update(struct drm_i915_private *dev_priv, | |
2673 | uint32_t interrupt_mask, | |
2674 | uint32_t enabled_irq_mask); | |
2675 | #define ibx_enable_display_interrupt(dev_priv, bits) \ | |
2676 | ibx_display_interrupt_update((dev_priv), (bits), (bits)) | |
2677 | #define ibx_disable_display_interrupt(dev_priv, bits) \ | |
2678 | ibx_display_interrupt_update((dev_priv), (bits), 0) | |
f8b79e58 | 2679 | |
673a394b | 2680 | /* i915_gem.c */ |
673a394b EA |
2681 | int i915_gem_create_ioctl(struct drm_device *dev, void *data, |
2682 | struct drm_file *file_priv); | |
2683 | int i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
2684 | struct drm_file *file_priv); | |
2685 | int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
2686 | struct drm_file *file_priv); | |
2687 | int i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
2688 | struct drm_file *file_priv); | |
de151cf6 JB |
2689 | int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, |
2690 | struct drm_file *file_priv); | |
673a394b EA |
2691 | int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, |
2692 | struct drm_file *file_priv); | |
2693 | int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
2694 | struct drm_file *file_priv); | |
ba8b7ccb OM |
2695 | void i915_gem_execbuffer_move_to_active(struct list_head *vmas, |
2696 | struct intel_engine_cs *ring); | |
adeca76d | 2697 | void i915_gem_execbuffer_retire_commands(struct i915_execbuffer_params *params); |
5f19e2bf | 2698 | int i915_gem_ringbuffer_submission(struct i915_execbuffer_params *params, |
a83014d3 | 2699 | struct drm_i915_gem_execbuffer2 *args, |
5f19e2bf | 2700 | struct list_head *vmas); |
673a394b EA |
2701 | int i915_gem_execbuffer(struct drm_device *dev, void *data, |
2702 | struct drm_file *file_priv); | |
76446cac JB |
2703 | int i915_gem_execbuffer2(struct drm_device *dev, void *data, |
2704 | struct drm_file *file_priv); | |
673a394b EA |
2705 | int i915_gem_busy_ioctl(struct drm_device *dev, void *data, |
2706 | struct drm_file *file_priv); | |
199adf40 BW |
2707 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, |
2708 | struct drm_file *file); | |
2709 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, | |
2710 | struct drm_file *file); | |
673a394b EA |
2711 | int i915_gem_throttle_ioctl(struct drm_device *dev, void *data, |
2712 | struct drm_file *file_priv); | |
3ef94daa CW |
2713 | int i915_gem_madvise_ioctl(struct drm_device *dev, void *data, |
2714 | struct drm_file *file_priv); | |
673a394b EA |
2715 | int i915_gem_set_tiling(struct drm_device *dev, void *data, |
2716 | struct drm_file *file_priv); | |
2717 | int i915_gem_get_tiling(struct drm_device *dev, void *data, | |
2718 | struct drm_file *file_priv); | |
5cc9ed4b CW |
2719 | int i915_gem_init_userptr(struct drm_device *dev); |
2720 | int i915_gem_userptr_ioctl(struct drm_device *dev, void *data, | |
2721 | struct drm_file *file); | |
5a125c3c EA |
2722 | int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, |
2723 | struct drm_file *file_priv); | |
23ba4fd0 BW |
2724 | int i915_gem_wait_ioctl(struct drm_device *dev, void *data, |
2725 | struct drm_file *file_priv); | |
673a394b | 2726 | void i915_gem_load(struct drm_device *dev); |
42dcedd4 CW |
2727 | void *i915_gem_object_alloc(struct drm_device *dev); |
2728 | void i915_gem_object_free(struct drm_i915_gem_object *obj); | |
37e680a1 CW |
2729 | void i915_gem_object_init(struct drm_i915_gem_object *obj, |
2730 | const struct drm_i915_gem_object_ops *ops); | |
05394f39 CW |
2731 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
2732 | size_t size); | |
7e0d96bc BW |
2733 | void i915_init_vm(struct drm_i915_private *dev_priv, |
2734 | struct i915_address_space *vm); | |
673a394b | 2735 | void i915_gem_free_object(struct drm_gem_object *obj); |
2f633156 | 2736 | void i915_gem_vma_destroy(struct i915_vma *vma); |
42dcedd4 | 2737 | |
0875546c DV |
2738 | /* Flags used by pin/bind&friends. */ |
2739 | #define PIN_MAPPABLE (1<<0) | |
2740 | #define PIN_NONBLOCK (1<<1) | |
2741 | #define PIN_GLOBAL (1<<2) | |
2742 | #define PIN_OFFSET_BIAS (1<<3) | |
2743 | #define PIN_USER (1<<4) | |
2744 | #define PIN_UPDATE (1<<5) | |
d23db88c | 2745 | #define PIN_OFFSET_MASK (~4095) |
ec7adb6e JL |
2746 | int __must_check |
2747 | i915_gem_object_pin(struct drm_i915_gem_object *obj, | |
2748 | struct i915_address_space *vm, | |
2749 | uint32_t alignment, | |
2750 | uint64_t flags); | |
2751 | int __must_check | |
2752 | i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj, | |
2753 | const struct i915_ggtt_view *view, | |
2754 | uint32_t alignment, | |
2755 | uint64_t flags); | |
fe14d5f4 TU |
2756 | |
2757 | int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level, | |
2758 | u32 flags); | |
07fe0b12 | 2759 | int __must_check i915_vma_unbind(struct i915_vma *vma); |
dd624afd | 2760 | int i915_gem_object_put_pages(struct drm_i915_gem_object *obj); |
48018a57 | 2761 | void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv); |
05394f39 | 2762 | void i915_gem_release_mmap(struct drm_i915_gem_object *obj); |
f787a5f5 | 2763 | |
4c914c0c BV |
2764 | int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj, |
2765 | int *needs_clflush); | |
2766 | ||
37e680a1 | 2767 | int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj); |
ee286370 CW |
2768 | |
2769 | static inline int __sg_page_count(struct scatterlist *sg) | |
9da3da66 | 2770 | { |
ee286370 CW |
2771 | return sg->length >> PAGE_SHIFT; |
2772 | } | |
67d5a50c | 2773 | |
ee286370 CW |
2774 | static inline struct page * |
2775 | i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n) | |
9da3da66 | 2776 | { |
ee286370 CW |
2777 | if (WARN_ON(n >= obj->base.size >> PAGE_SHIFT)) |
2778 | return NULL; | |
67d5a50c | 2779 | |
ee286370 CW |
2780 | if (n < obj->get_page.last) { |
2781 | obj->get_page.sg = obj->pages->sgl; | |
2782 | obj->get_page.last = 0; | |
2783 | } | |
67d5a50c | 2784 | |
ee286370 CW |
2785 | while (obj->get_page.last + __sg_page_count(obj->get_page.sg) <= n) { |
2786 | obj->get_page.last += __sg_page_count(obj->get_page.sg++); | |
2787 | if (unlikely(sg_is_chain(obj->get_page.sg))) | |
2788 | obj->get_page.sg = sg_chain_ptr(obj->get_page.sg); | |
2789 | } | |
67d5a50c | 2790 | |
ee286370 | 2791 | return nth_page(sg_page(obj->get_page.sg), n - obj->get_page.last); |
9da3da66 | 2792 | } |
ee286370 | 2793 | |
a5570178 CW |
2794 | static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj) |
2795 | { | |
2796 | BUG_ON(obj->pages == NULL); | |
2797 | obj->pages_pin_count++; | |
2798 | } | |
2799 | static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj) | |
2800 | { | |
2801 | BUG_ON(obj->pages_pin_count == 0); | |
2802 | obj->pages_pin_count--; | |
2803 | } | |
2804 | ||
54cf91dc | 2805 | int __must_check i915_mutex_lock_interruptible(struct drm_device *dev); |
2911a35b | 2806 | int i915_gem_object_sync(struct drm_i915_gem_object *obj, |
a4872ba6 | 2807 | struct intel_engine_cs *to); |
e2d05a8b | 2808 | void i915_vma_move_to_active(struct i915_vma *vma, |
a4872ba6 | 2809 | struct intel_engine_cs *ring); |
ff72145b DA |
2810 | int i915_gem_dumb_create(struct drm_file *file_priv, |
2811 | struct drm_device *dev, | |
2812 | struct drm_mode_create_dumb *args); | |
da6b51d0 DA |
2813 | int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev, |
2814 | uint32_t handle, uint64_t *offset); | |
f787a5f5 CW |
2815 | /** |
2816 | * Returns true if seq1 is later than seq2. | |
2817 | */ | |
2818 | static inline bool | |
2819 | i915_seqno_passed(uint32_t seq1, uint32_t seq2) | |
2820 | { | |
2821 | return (int32_t)(seq1 - seq2) >= 0; | |
2822 | } | |
2823 | ||
1b5a433a JH |
2824 | static inline bool i915_gem_request_completed(struct drm_i915_gem_request *req, |
2825 | bool lazy_coherency) | |
2826 | { | |
2827 | u32 seqno; | |
2828 | ||
2829 | BUG_ON(req == NULL); | |
2830 | ||
2831 | seqno = req->ring->get_seqno(req->ring, lazy_coherency); | |
2832 | ||
2833 | return i915_seqno_passed(seqno, req->seqno); | |
2834 | } | |
2835 | ||
fca26bb4 MK |
2836 | int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno); |
2837 | int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno); | |
06d98131 | 2838 | int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj); |
d9e86c0e | 2839 | int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj); |
2021746e | 2840 | |
d8ffa60b DV |
2841 | bool i915_gem_object_pin_fence(struct drm_i915_gem_object *obj); |
2842 | void i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj); | |
1690e1eb | 2843 | |
8d9fc7fd | 2844 | struct drm_i915_gem_request * |
a4872ba6 | 2845 | i915_gem_find_active_request(struct intel_engine_cs *ring); |
8d9fc7fd | 2846 | |
b29c19b6 | 2847 | bool i915_gem_retire_requests(struct drm_device *dev); |
a4872ba6 | 2848 | void i915_gem_retire_requests_ring(struct intel_engine_cs *ring); |
33196ded | 2849 | int __must_check i915_gem_check_wedge(struct i915_gpu_error *error, |
d6b2c790 | 2850 | bool interruptible); |
b6660d59 | 2851 | int __must_check i915_gem_check_olr(struct drm_i915_gem_request *req); |
84c33a64 | 2852 | |
1f83fee0 DV |
2853 | static inline bool i915_reset_in_progress(struct i915_gpu_error *error) |
2854 | { | |
2855 | return unlikely(atomic_read(&error->reset_counter) | |
2ac0f450 | 2856 | & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED)); |
1f83fee0 DV |
2857 | } |
2858 | ||
2859 | static inline bool i915_terminally_wedged(struct i915_gpu_error *error) | |
2860 | { | |
2ac0f450 MK |
2861 | return atomic_read(&error->reset_counter) & I915_WEDGED; |
2862 | } | |
2863 | ||
2864 | static inline u32 i915_reset_count(struct i915_gpu_error *error) | |
2865 | { | |
2866 | return ((atomic_read(&error->reset_counter) & ~I915_WEDGED) + 1) / 2; | |
1f83fee0 | 2867 | } |
a71d8d94 | 2868 | |
88b4aa87 MK |
2869 | static inline bool i915_stop_ring_allow_ban(struct drm_i915_private *dev_priv) |
2870 | { | |
2871 | return dev_priv->gpu_error.stop_rings == 0 || | |
2872 | dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_BAN; | |
2873 | } | |
2874 | ||
2875 | static inline bool i915_stop_ring_allow_warn(struct drm_i915_private *dev_priv) | |
2876 | { | |
2877 | return dev_priv->gpu_error.stop_rings == 0 || | |
2878 | dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_WARN; | |
2879 | } | |
2880 | ||
069efc1d | 2881 | void i915_gem_reset(struct drm_device *dev); |
000433b6 | 2882 | bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force); |
1070a42b | 2883 | int __must_check i915_gem_init(struct drm_device *dev); |
a83014d3 | 2884 | int i915_gem_init_rings(struct drm_device *dev); |
f691e2f4 | 2885 | int __must_check i915_gem_init_hw(struct drm_device *dev); |
a4872ba6 | 2886 | int i915_gem_l3_remap(struct intel_engine_cs *ring, int slice); |
f691e2f4 | 2887 | void i915_gem_init_swizzling(struct drm_device *dev); |
79e53945 | 2888 | void i915_gem_cleanup_ringbuffer(struct drm_device *dev); |
b2da9fe5 | 2889 | int __must_check i915_gpu_idle(struct drm_device *dev); |
45c5f202 | 2890 | int __must_check i915_gem_suspend(struct drm_device *dev); |
bf7dc5b7 JH |
2891 | void __i915_add_request(struct intel_engine_cs *ring, |
2892 | struct drm_file *file, | |
2893 | struct drm_i915_gem_object *batch_obj); | |
9400ae5c JH |
2894 | #define i915_add_request(ring) \ |
2895 | __i915_add_request(ring, NULL, NULL) | |
9c654818 | 2896 | int __i915_wait_request(struct drm_i915_gem_request *req, |
16e9a21f ACO |
2897 | unsigned reset_counter, |
2898 | bool interruptible, | |
2899 | s64 *timeout, | |
2e1b8730 | 2900 | struct intel_rps_client *rps); |
a4b3a571 | 2901 | int __must_check i915_wait_request(struct drm_i915_gem_request *req); |
de151cf6 | 2902 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf); |
2021746e | 2903 | int __must_check |
2e2f351d CW |
2904 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, |
2905 | bool readonly); | |
2906 | int __must_check | |
2021746e CW |
2907 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, |
2908 | bool write); | |
2909 | int __must_check | |
dabdfe02 CW |
2910 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write); |
2911 | int __must_check | |
2da3b9b9 CW |
2912 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
2913 | u32 alignment, | |
e6617330 TU |
2914 | struct intel_engine_cs *pipelined, |
2915 | const struct i915_ggtt_view *view); | |
2916 | void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj, | |
2917 | const struct i915_ggtt_view *view); | |
00731155 | 2918 | int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj, |
6eeefaf3 | 2919 | int align); |
b29c19b6 | 2920 | int i915_gem_open(struct drm_device *dev, struct drm_file *file); |
05394f39 | 2921 | void i915_gem_release(struct drm_device *dev, struct drm_file *file); |
673a394b | 2922 | |
0fa87796 ID |
2923 | uint32_t |
2924 | i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode); | |
467cffba | 2925 | uint32_t |
d865110c ID |
2926 | i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size, |
2927 | int tiling_mode, bool fenced); | |
467cffba | 2928 | |
e4ffd173 CW |
2929 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
2930 | enum i915_cache_level cache_level); | |
2931 | ||
1286ff73 DV |
2932 | struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev, |
2933 | struct dma_buf *dma_buf); | |
2934 | ||
2935 | struct dma_buf *i915_gem_prime_export(struct drm_device *dev, | |
2936 | struct drm_gem_object *gem_obj, int flags); | |
2937 | ||
19b2dbde CW |
2938 | void i915_gem_restore_fences(struct drm_device *dev); |
2939 | ||
ec7adb6e JL |
2940 | unsigned long |
2941 | i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object *o, | |
9abc4648 | 2942 | const struct i915_ggtt_view *view); |
ec7adb6e JL |
2943 | unsigned long |
2944 | i915_gem_obj_offset(struct drm_i915_gem_object *o, | |
2945 | struct i915_address_space *vm); | |
2946 | static inline unsigned long | |
2947 | i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *o) | |
fe14d5f4 | 2948 | { |
9abc4648 | 2949 | return i915_gem_obj_ggtt_offset_view(o, &i915_ggtt_view_normal); |
fe14d5f4 | 2950 | } |
ec7adb6e | 2951 | |
a70a3148 | 2952 | bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o); |
ec7adb6e | 2953 | bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object *o, |
9abc4648 | 2954 | const struct i915_ggtt_view *view); |
a70a3148 | 2955 | bool i915_gem_obj_bound(struct drm_i915_gem_object *o, |
ec7adb6e | 2956 | struct i915_address_space *vm); |
fe14d5f4 | 2957 | |
a70a3148 BW |
2958 | unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o, |
2959 | struct i915_address_space *vm); | |
fe14d5f4 | 2960 | struct i915_vma * |
ec7adb6e JL |
2961 | i915_gem_obj_to_vma(struct drm_i915_gem_object *obj, |
2962 | struct i915_address_space *vm); | |
2963 | struct i915_vma * | |
2964 | i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object *obj, | |
2965 | const struct i915_ggtt_view *view); | |
fe14d5f4 | 2966 | |
accfef2e BW |
2967 | struct i915_vma * |
2968 | i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj, | |
ec7adb6e JL |
2969 | struct i915_address_space *vm); |
2970 | struct i915_vma * | |
2971 | i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj, | |
2972 | const struct i915_ggtt_view *view); | |
5c2abbea | 2973 | |
ec7adb6e JL |
2974 | static inline struct i915_vma * |
2975 | i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj) | |
2976 | { | |
2977 | return i915_gem_obj_to_ggtt_view(obj, &i915_ggtt_view_normal); | |
d7f46fc4 | 2978 | } |
ec7adb6e | 2979 | bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj); |
5c2abbea | 2980 | |
a70a3148 | 2981 | /* Some GGTT VM helpers */ |
5dc383b0 | 2982 | #define i915_obj_to_ggtt(obj) \ |
a70a3148 BW |
2983 | (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base) |
2984 | static inline bool i915_is_ggtt(struct i915_address_space *vm) | |
2985 | { | |
2986 | struct i915_address_space *ggtt = | |
2987 | &((struct drm_i915_private *)(vm)->dev->dev_private)->gtt.base; | |
2988 | return vm == ggtt; | |
2989 | } | |
2990 | ||
841cd773 DV |
2991 | static inline struct i915_hw_ppgtt * |
2992 | i915_vm_to_ppgtt(struct i915_address_space *vm) | |
2993 | { | |
2994 | WARN_ON(i915_is_ggtt(vm)); | |
2995 | ||
2996 | return container_of(vm, struct i915_hw_ppgtt, base); | |
2997 | } | |
2998 | ||
2999 | ||
a70a3148 BW |
3000 | static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj) |
3001 | { | |
9abc4648 | 3002 | return i915_gem_obj_ggtt_bound_view(obj, &i915_ggtt_view_normal); |
a70a3148 BW |
3003 | } |
3004 | ||
3005 | static inline unsigned long | |
3006 | i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj) | |
3007 | { | |
5dc383b0 | 3008 | return i915_gem_obj_size(obj, i915_obj_to_ggtt(obj)); |
a70a3148 | 3009 | } |
c37e2204 BW |
3010 | |
3011 | static inline int __must_check | |
3012 | i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj, | |
3013 | uint32_t alignment, | |
1ec9e26d | 3014 | unsigned flags) |
c37e2204 | 3015 | { |
5dc383b0 DV |
3016 | return i915_gem_object_pin(obj, i915_obj_to_ggtt(obj), |
3017 | alignment, flags | PIN_GLOBAL); | |
c37e2204 | 3018 | } |
a70a3148 | 3019 | |
b287110e DV |
3020 | static inline int |
3021 | i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj) | |
3022 | { | |
3023 | return i915_vma_unbind(i915_gem_obj_to_ggtt(obj)); | |
3024 | } | |
3025 | ||
e6617330 TU |
3026 | void i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object *obj, |
3027 | const struct i915_ggtt_view *view); | |
3028 | static inline void | |
3029 | i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj) | |
3030 | { | |
3031 | i915_gem_object_ggtt_unpin_view(obj, &i915_ggtt_view_normal); | |
3032 | } | |
b287110e | 3033 | |
254f965c | 3034 | /* i915_gem_context.c */ |
8245be31 | 3035 | int __must_check i915_gem_context_init(struct drm_device *dev); |
254f965c | 3036 | void i915_gem_context_fini(struct drm_device *dev); |
acce9ffa | 3037 | void i915_gem_context_reset(struct drm_device *dev); |
e422b888 | 3038 | int i915_gem_context_open(struct drm_device *dev, struct drm_file *file); |
2fa48d8d | 3039 | int i915_gem_context_enable(struct drm_i915_private *dev_priv); |
254f965c | 3040 | void i915_gem_context_close(struct drm_device *dev, struct drm_file *file); |
a4872ba6 | 3041 | int i915_switch_context(struct intel_engine_cs *ring, |
273497e5 OM |
3042 | struct intel_context *to); |
3043 | struct intel_context * | |
41bde553 | 3044 | i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id); |
dce3271b | 3045 | void i915_gem_context_free(struct kref *ctx_ref); |
8c857917 OM |
3046 | struct drm_i915_gem_object * |
3047 | i915_gem_alloc_context_obj(struct drm_device *dev, size_t size); | |
273497e5 | 3048 | static inline void i915_gem_context_reference(struct intel_context *ctx) |
dce3271b | 3049 | { |
691e6415 | 3050 | kref_get(&ctx->ref); |
dce3271b MK |
3051 | } |
3052 | ||
273497e5 | 3053 | static inline void i915_gem_context_unreference(struct intel_context *ctx) |
dce3271b | 3054 | { |
691e6415 | 3055 | kref_put(&ctx->ref, i915_gem_context_free); |
dce3271b MK |
3056 | } |
3057 | ||
273497e5 | 3058 | static inline bool i915_gem_context_is_default(const struct intel_context *c) |
3fac8978 | 3059 | { |
821d66dd | 3060 | return c->user_handle == DEFAULT_CONTEXT_HANDLE; |
3fac8978 MK |
3061 | } |
3062 | ||
84624813 BW |
3063 | int i915_gem_context_create_ioctl(struct drm_device *dev, void *data, |
3064 | struct drm_file *file); | |
3065 | int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data, | |
3066 | struct drm_file *file); | |
c9dc0f35 CW |
3067 | int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data, |
3068 | struct drm_file *file_priv); | |
3069 | int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data, | |
3070 | struct drm_file *file_priv); | |
1286ff73 | 3071 | |
679845ed BW |
3072 | /* i915_gem_evict.c */ |
3073 | int __must_check i915_gem_evict_something(struct drm_device *dev, | |
3074 | struct i915_address_space *vm, | |
3075 | int min_size, | |
3076 | unsigned alignment, | |
3077 | unsigned cache_level, | |
d23db88c CW |
3078 | unsigned long start, |
3079 | unsigned long end, | |
1ec9e26d | 3080 | unsigned flags); |
679845ed BW |
3081 | int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle); |
3082 | int i915_gem_evict_everything(struct drm_device *dev); | |
1d2a314c | 3083 | |
0260c420 | 3084 | /* belongs in i915_gem_gtt.h */ |
d09105c6 | 3085 | static inline void i915_gem_chipset_flush(struct drm_device *dev) |
e76e9aeb BW |
3086 | { |
3087 | if (INTEL_INFO(dev)->gen < 6) | |
3088 | intel_gtt_chipset_flush(); | |
3089 | } | |
246cbfb5 | 3090 | |
9797fbfb CW |
3091 | /* i915_gem_stolen.c */ |
3092 | int i915_gem_init_stolen(struct drm_device *dev); | |
5e59f717 | 3093 | int i915_gem_stolen_setup_compression(struct drm_device *dev, int size, int fb_cpp); |
11be49eb | 3094 | void i915_gem_stolen_cleanup_compression(struct drm_device *dev); |
9797fbfb | 3095 | void i915_gem_cleanup_stolen(struct drm_device *dev); |
0104fdbb CW |
3096 | struct drm_i915_gem_object * |
3097 | i915_gem_object_create_stolen(struct drm_device *dev, u32 size); | |
866d12b4 CW |
3098 | struct drm_i915_gem_object * |
3099 | i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev, | |
3100 | u32 stolen_offset, | |
3101 | u32 gtt_offset, | |
3102 | u32 size); | |
9797fbfb | 3103 | |
be6a0376 DV |
3104 | /* i915_gem_shrinker.c */ |
3105 | unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv, | |
3106 | long target, | |
3107 | unsigned flags); | |
3108 | #define I915_SHRINK_PURGEABLE 0x1 | |
3109 | #define I915_SHRINK_UNBOUND 0x2 | |
3110 | #define I915_SHRINK_BOUND 0x4 | |
3111 | unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv); | |
3112 | void i915_gem_shrinker_init(struct drm_i915_private *dev_priv); | |
3113 | ||
3114 | ||
673a394b | 3115 | /* i915_gem_tiling.c */ |
2c1792a1 | 3116 | static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj) |
e9b73c67 | 3117 | { |
50227e1c | 3118 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
e9b73c67 CW |
3119 | |
3120 | return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && | |
3121 | obj->tiling_mode != I915_TILING_NONE; | |
3122 | } | |
3123 | ||
673a394b | 3124 | void i915_gem_detect_bit_6_swizzle(struct drm_device *dev); |
05394f39 CW |
3125 | void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj); |
3126 | void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj); | |
673a394b EA |
3127 | |
3128 | /* i915_gem_debug.c */ | |
23bc5982 CW |
3129 | #if WATCH_LISTS |
3130 | int i915_verify_lists(struct drm_device *dev); | |
673a394b | 3131 | #else |
23bc5982 | 3132 | #define i915_verify_lists(dev) 0 |
673a394b | 3133 | #endif |
1da177e4 | 3134 | |
2017263e | 3135 | /* i915_debugfs.c */ |
27c202ad BG |
3136 | int i915_debugfs_init(struct drm_minor *minor); |
3137 | void i915_debugfs_cleanup(struct drm_minor *minor); | |
f8c168fa | 3138 | #ifdef CONFIG_DEBUG_FS |
249e87de | 3139 | int i915_debugfs_connector_add(struct drm_connector *connector); |
07144428 DL |
3140 | void intel_display_crc_init(struct drm_device *dev); |
3141 | #else | |
249e87de | 3142 | static inline int i915_debugfs_connector_add(struct drm_connector *connector) {} |
f8c168fa | 3143 | static inline void intel_display_crc_init(struct drm_device *dev) {} |
07144428 | 3144 | #endif |
84734a04 MK |
3145 | |
3146 | /* i915_gpu_error.c */ | |
edc3d884 MK |
3147 | __printf(2, 3) |
3148 | void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...); | |
fc16b48b MK |
3149 | int i915_error_state_to_str(struct drm_i915_error_state_buf *estr, |
3150 | const struct i915_error_state_file_priv *error); | |
4dc955f7 | 3151 | int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb, |
0a4cd7c8 | 3152 | struct drm_i915_private *i915, |
4dc955f7 MK |
3153 | size_t count, loff_t pos); |
3154 | static inline void i915_error_state_buf_release( | |
3155 | struct drm_i915_error_state_buf *eb) | |
3156 | { | |
3157 | kfree(eb->buf); | |
3158 | } | |
58174462 MK |
3159 | void i915_capture_error_state(struct drm_device *dev, bool wedge, |
3160 | const char *error_msg); | |
84734a04 MK |
3161 | void i915_error_state_get(struct drm_device *dev, |
3162 | struct i915_error_state_file_priv *error_priv); | |
3163 | void i915_error_state_put(struct i915_error_state_file_priv *error_priv); | |
3164 | void i915_destroy_error_state(struct drm_device *dev); | |
3165 | ||
3166 | void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone); | |
0a4cd7c8 | 3167 | const char *i915_cache_level_str(struct drm_i915_private *i915, int type); |
2017263e | 3168 | |
351e3db2 | 3169 | /* i915_cmd_parser.c */ |
d728c8ef | 3170 | int i915_cmd_parser_get_version(void); |
a4872ba6 OM |
3171 | int i915_cmd_parser_init_ring(struct intel_engine_cs *ring); |
3172 | void i915_cmd_parser_fini_ring(struct intel_engine_cs *ring); | |
3173 | bool i915_needs_cmd_parser(struct intel_engine_cs *ring); | |
3174 | int i915_parse_cmds(struct intel_engine_cs *ring, | |
351e3db2 | 3175 | struct drm_i915_gem_object *batch_obj, |
78a42377 | 3176 | struct drm_i915_gem_object *shadow_batch_obj, |
351e3db2 | 3177 | u32 batch_start_offset, |
b9ffd80e | 3178 | u32 batch_len, |
351e3db2 BV |
3179 | bool is_master); |
3180 | ||
317c35d1 JB |
3181 | /* i915_suspend.c */ |
3182 | extern int i915_save_state(struct drm_device *dev); | |
3183 | extern int i915_restore_state(struct drm_device *dev); | |
0a3e67a4 | 3184 | |
0136db58 BW |
3185 | /* i915_sysfs.c */ |
3186 | void i915_setup_sysfs(struct drm_device *dev_priv); | |
3187 | void i915_teardown_sysfs(struct drm_device *dev_priv); | |
3188 | ||
f899fc64 CW |
3189 | /* intel_i2c.c */ |
3190 | extern int intel_setup_gmbus(struct drm_device *dev); | |
3191 | extern void intel_teardown_gmbus(struct drm_device *dev); | |
88ac7939 JN |
3192 | extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv, |
3193 | unsigned int pin); | |
3bd7d909 | 3194 | |
0184df46 JN |
3195 | extern struct i2c_adapter * |
3196 | intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin); | |
e957d772 CW |
3197 | extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed); |
3198 | extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit); | |
8f375e10 | 3199 | static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter) |
b8232e90 CW |
3200 | { |
3201 | return container_of(adapter, struct intel_gmbus, adapter)->force_bit; | |
3202 | } | |
f899fc64 CW |
3203 | extern void intel_i2c_reset(struct drm_device *dev); |
3204 | ||
3b617967 | 3205 | /* intel_opregion.c */ |
44834a67 | 3206 | #ifdef CONFIG_ACPI |
27d50c82 | 3207 | extern int intel_opregion_setup(struct drm_device *dev); |
44834a67 CW |
3208 | extern void intel_opregion_init(struct drm_device *dev); |
3209 | extern void intel_opregion_fini(struct drm_device *dev); | |
3b617967 | 3210 | extern void intel_opregion_asle_intr(struct drm_device *dev); |
9c4b0a68 JN |
3211 | extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, |
3212 | bool enable); | |
ecbc5cf3 JN |
3213 | extern int intel_opregion_notify_adapter(struct drm_device *dev, |
3214 | pci_power_t state); | |
65e082c9 | 3215 | #else |
27d50c82 | 3216 | static inline int intel_opregion_setup(struct drm_device *dev) { return 0; } |
44834a67 CW |
3217 | static inline void intel_opregion_init(struct drm_device *dev) { return; } |
3218 | static inline void intel_opregion_fini(struct drm_device *dev) { return; } | |
3b617967 | 3219 | static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; } |
9c4b0a68 JN |
3220 | static inline int |
3221 | intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable) | |
3222 | { | |
3223 | return 0; | |
3224 | } | |
ecbc5cf3 JN |
3225 | static inline int |
3226 | intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state) | |
3227 | { | |
3228 | return 0; | |
3229 | } | |
65e082c9 | 3230 | #endif |
8ee1c3db | 3231 | |
723bfd70 JB |
3232 | /* intel_acpi.c */ |
3233 | #ifdef CONFIG_ACPI | |
3234 | extern void intel_register_dsm_handler(void); | |
3235 | extern void intel_unregister_dsm_handler(void); | |
3236 | #else | |
3237 | static inline void intel_register_dsm_handler(void) { return; } | |
3238 | static inline void intel_unregister_dsm_handler(void) { return; } | |
3239 | #endif /* CONFIG_ACPI */ | |
3240 | ||
79e53945 | 3241 | /* modesetting */ |
f817586c | 3242 | extern void intel_modeset_init_hw(struct drm_device *dev); |
79e53945 | 3243 | extern void intel_modeset_init(struct drm_device *dev); |
2c7111db | 3244 | extern void intel_modeset_gem_init(struct drm_device *dev); |
79e53945 | 3245 | extern void intel_modeset_cleanup(struct drm_device *dev); |
4932e2c3 | 3246 | extern void intel_connector_unregister(struct intel_connector *); |
28d52043 | 3247 | extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state); |
45e2b5f6 DV |
3248 | extern void intel_modeset_setup_hw_state(struct drm_device *dev, |
3249 | bool force_restore); | |
44cec740 | 3250 | extern void i915_redisable_vga(struct drm_device *dev); |
04098753 | 3251 | extern void i915_redisable_vga_power_on(struct drm_device *dev); |
7648fa99 | 3252 | extern bool ironlake_set_drps(struct drm_device *dev, u8 val); |
dde86e2d | 3253 | extern void intel_init_pch_refclk(struct drm_device *dev); |
ffe02b40 | 3254 | extern void intel_set_rps(struct drm_device *dev, u8 val); |
5209b1f4 ID |
3255 | extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, |
3256 | bool enable); | |
0206e353 AJ |
3257 | extern void intel_detect_pch(struct drm_device *dev); |
3258 | extern int intel_trans_dp_port_sel(struct drm_crtc *crtc); | |
0136db58 | 3259 | extern int intel_enable_rc6(const struct drm_device *dev); |
3bad0781 | 3260 | |
2911a35b | 3261 | extern bool i915_semaphore_is_enabled(struct drm_device *dev); |
c0c7babc BW |
3262 | int i915_reg_read_ioctl(struct drm_device *dev, void *data, |
3263 | struct drm_file *file); | |
b6359918 MK |
3264 | int i915_get_reset_stats_ioctl(struct drm_device *dev, void *data, |
3265 | struct drm_file *file); | |
575155a9 | 3266 | |
6ef3d427 CW |
3267 | /* overlay */ |
3268 | extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev); | |
edc3d884 MK |
3269 | extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e, |
3270 | struct intel_overlay_error_state *error); | |
c4a1d9e4 CW |
3271 | |
3272 | extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev); | |
edc3d884 | 3273 | extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e, |
c4a1d9e4 CW |
3274 | struct drm_device *dev, |
3275 | struct intel_display_error_state *error); | |
6ef3d427 | 3276 | |
151a49d0 TR |
3277 | int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val); |
3278 | int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val); | |
59de0813 JN |
3279 | |
3280 | /* intel_sideband.c */ | |
707b6e3d D |
3281 | u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr); |
3282 | void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val); | |
64936258 | 3283 | u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr); |
e9f882a3 JN |
3284 | u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg); |
3285 | void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
3286 | u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg); | |
3287 | void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
3288 | u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg); | |
3289 | void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
f3419158 JB |
3290 | u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg); |
3291 | void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
e9f882a3 JN |
3292 | u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg); |
3293 | void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
5e69f97f CML |
3294 | u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg); |
3295 | void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val); | |
59de0813 JN |
3296 | u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg, |
3297 | enum intel_sbi_destination destination); | |
3298 | void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value, | |
3299 | enum intel_sbi_destination destination); | |
e9fe51c6 SK |
3300 | u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg); |
3301 | void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
0a073b84 | 3302 | |
616bc820 VS |
3303 | int intel_gpu_freq(struct drm_i915_private *dev_priv, int val); |
3304 | int intel_freq_opcode(struct drm_i915_private *dev_priv, int val); | |
c8d9a590 | 3305 | |
0b274481 BW |
3306 | #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true) |
3307 | #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true) | |
3308 | ||
3309 | #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true) | |
3310 | #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true) | |
3311 | #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false) | |
3312 | #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false) | |
3313 | ||
3314 | #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true) | |
3315 | #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true) | |
3316 | #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false) | |
3317 | #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false) | |
3318 | ||
698b3135 CW |
3319 | /* Be very careful with read/write 64-bit values. On 32-bit machines, they |
3320 | * will be implemented using 2 32-bit writes in an arbitrary order with | |
3321 | * an arbitrary delay between them. This can cause the hardware to | |
3322 | * act upon the intermediate value, possibly leading to corruption and | |
3323 | * machine death. You have been warned. | |
3324 | */ | |
0b274481 BW |
3325 | #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true) |
3326 | #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true) | |
cae5852d | 3327 | |
50877445 CW |
3328 | #define I915_READ64_2x32(lower_reg, upper_reg) ({ \ |
3329 | u32 upper = I915_READ(upper_reg); \ | |
3330 | u32 lower = I915_READ(lower_reg); \ | |
3331 | u32 tmp = I915_READ(upper_reg); \ | |
3332 | if (upper != tmp) { \ | |
3333 | upper = tmp; \ | |
3334 | lower = I915_READ(lower_reg); \ | |
3335 | WARN_ON(I915_READ(upper_reg) != upper); \ | |
3336 | } \ | |
3337 | (u64)upper << 32 | lower; }) | |
3338 | ||
cae5852d ZN |
3339 | #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg) |
3340 | #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg) | |
3341 | ||
a6111f7b CW |
3342 | /* These are untraced mmio-accessors that are only valid to be used inside |
3343 | * criticial sections inside IRQ handlers where forcewake is explicitly | |
3344 | * controlled. | |
3345 | * Think twice, and think again, before using these. | |
3346 | * Note: Should only be used between intel_uncore_forcewake_irqlock() and | |
3347 | * intel_uncore_forcewake_irqunlock(). | |
3348 | */ | |
3349 | #define I915_READ_FW(reg__) readl(dev_priv->regs + (reg__)) | |
3350 | #define I915_WRITE_FW(reg__, val__) writel(val__, dev_priv->regs + (reg__)) | |
3351 | #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__) | |
3352 | ||
55bc60db VS |
3353 | /* "Broadcast RGB" property */ |
3354 | #define INTEL_BROADCAST_RGB_AUTO 0 | |
3355 | #define INTEL_BROADCAST_RGB_FULL 1 | |
3356 | #define INTEL_BROADCAST_RGB_LIMITED 2 | |
ba4f01a3 | 3357 | |
766aa1c4 VS |
3358 | static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev) |
3359 | { | |
92e23b99 | 3360 | if (IS_VALLEYVIEW(dev)) |
766aa1c4 | 3361 | return VLV_VGACNTRL; |
92e23b99 SJ |
3362 | else if (INTEL_INFO(dev)->gen >= 5) |
3363 | return CPU_VGACNTRL; | |
766aa1c4 VS |
3364 | else |
3365 | return VGACNTRL; | |
3366 | } | |
3367 | ||
2bb4629a VS |
3368 | static inline void __user *to_user_ptr(u64 address) |
3369 | { | |
3370 | return (void __user *)(uintptr_t)address; | |
3371 | } | |
3372 | ||
df97729f ID |
3373 | static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m) |
3374 | { | |
3375 | unsigned long j = msecs_to_jiffies(m); | |
3376 | ||
3377 | return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1); | |
3378 | } | |
3379 | ||
7bd0e226 DV |
3380 | static inline unsigned long nsecs_to_jiffies_timeout(const u64 n) |
3381 | { | |
3382 | return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1); | |
3383 | } | |
3384 | ||
df97729f ID |
3385 | static inline unsigned long |
3386 | timespec_to_jiffies_timeout(const struct timespec *value) | |
3387 | { | |
3388 | unsigned long j = timespec_to_jiffies(value); | |
3389 | ||
3390 | return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1); | |
3391 | } | |
3392 | ||
dce56b3c PZ |
3393 | /* |
3394 | * If you need to wait X milliseconds between events A and B, but event B | |
3395 | * doesn't happen exactly after event A, you record the timestamp (jiffies) of | |
3396 | * when event A happened, then just before event B you call this function and | |
3397 | * pass the timestamp as the first argument, and X as the second argument. | |
3398 | */ | |
3399 | static inline void | |
3400 | wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms) | |
3401 | { | |
ec5e0cfb | 3402 | unsigned long target_jiffies, tmp_jiffies, remaining_jiffies; |
dce56b3c PZ |
3403 | |
3404 | /* | |
3405 | * Don't re-read the value of "jiffies" every time since it may change | |
3406 | * behind our back and break the math. | |
3407 | */ | |
3408 | tmp_jiffies = jiffies; | |
3409 | target_jiffies = timestamp_jiffies + | |
3410 | msecs_to_jiffies_timeout(to_wait_ms); | |
3411 | ||
3412 | if (time_after(target_jiffies, tmp_jiffies)) { | |
ec5e0cfb ID |
3413 | remaining_jiffies = target_jiffies - tmp_jiffies; |
3414 | while (remaining_jiffies) | |
3415 | remaining_jiffies = | |
3416 | schedule_timeout_uninterruptible(remaining_jiffies); | |
dce56b3c PZ |
3417 | } |
3418 | } | |
3419 | ||
581c26e8 JH |
3420 | static inline void i915_trace_irq_get(struct intel_engine_cs *ring, |
3421 | struct drm_i915_gem_request *req) | |
3422 | { | |
3423 | if (ring->trace_irq_req == NULL && ring->irq_get(ring)) | |
3424 | i915_gem_request_assign(&ring->trace_irq_req, req); | |
3425 | } | |
3426 | ||
1da177e4 | 3427 | #endif |