Commit | Line | Data |
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1da177e4 LT |
1 | /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- |
2 | */ | |
0d6aa60b | 3 | /* |
bc54fd1a | 4 | * |
1da177e4 LT |
5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
6 | * All Rights Reserved. | |
bc54fd1a DA |
7 | * |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the | |
10 | * "Software"), to deal in the Software without restriction, including | |
11 | * without limitation the rights to use, copy, modify, merge, publish, | |
12 | * distribute, sub license, and/or sell copies of the Software, and to | |
13 | * permit persons to whom the Software is furnished to do so, subject to | |
14 | * the following conditions: | |
15 | * | |
16 | * The above copyright notice and this permission notice (including the | |
17 | * next paragraph) shall be included in all copies or substantial portions | |
18 | * of the Software. | |
19 | * | |
20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
27 | * | |
0d6aa60b | 28 | */ |
1da177e4 LT |
29 | |
30 | #ifndef _I915_DRV_H_ | |
31 | #define _I915_DRV_H_ | |
32 | ||
e9b73c67 | 33 | #include <uapi/drm/i915_drm.h> |
93b81f51 | 34 | #include <uapi/drm/drm_fourcc.h> |
e9b73c67 | 35 | |
0839ccb8 | 36 | #include <linux/io-mapping.h> |
f899fc64 | 37 | #include <linux/i2c.h> |
c167a6fc | 38 | #include <linux/i2c-algo-bit.h> |
aaa6fd2a | 39 | #include <linux/backlight.h> |
5cc9ed4b | 40 | #include <linux/hashtable.h> |
2911a35b | 41 | #include <linux/intel-iommu.h> |
742cbee8 | 42 | #include <linux/kref.h> |
9ee32fea | 43 | #include <linux/pm_qos.h> |
e73bdd20 CW |
44 | #include <linux/shmem_fs.h> |
45 | ||
46 | #include <drm/drmP.h> | |
47 | #include <drm/intel-gtt.h> | |
48 | #include <drm/drm_legacy.h> /* for struct drm_dma_handle */ | |
49 | #include <drm/drm_gem.h> | |
3b96a0b1 | 50 | #include <drm/drm_auth.h> |
e73bdd20 CW |
51 | |
52 | #include "i915_params.h" | |
53 | #include "i915_reg.h" | |
54 | ||
55 | #include "intel_bios.h" | |
ac7f11c6 | 56 | #include "intel_dpll_mgr.h" |
e73bdd20 CW |
57 | #include "intel_guc.h" |
58 | #include "intel_lrc.h" | |
59 | #include "intel_ringbuffer.h" | |
60 | ||
d501b1d2 | 61 | #include "i915_gem.h" |
e73bdd20 CW |
62 | #include "i915_gem_gtt.h" |
63 | #include "i915_gem_render_state.h" | |
05235c53 | 64 | #include "i915_gem_request.h" |
585fb111 | 65 | |
0ad35fed ZW |
66 | #include "intel_gvt.h" |
67 | ||
1da177e4 LT |
68 | /* General customization: |
69 | */ | |
70 | ||
1da177e4 LT |
71 | #define DRIVER_NAME "i915" |
72 | #define DRIVER_DESC "Intel Graphics" | |
c4a8a7c7 | 73 | #define DRIVER_DATE "20160902" |
1da177e4 | 74 | |
c883ef1b | 75 | #undef WARN_ON |
5f77eeb0 DV |
76 | /* Many gcc seem to no see through this and fall over :( */ |
77 | #if 0 | |
78 | #define WARN_ON(x) ({ \ | |
79 | bool __i915_warn_cond = (x); \ | |
80 | if (__builtin_constant_p(__i915_warn_cond)) \ | |
81 | BUILD_BUG_ON(__i915_warn_cond); \ | |
82 | WARN(__i915_warn_cond, "WARN_ON(" #x ")"); }) | |
83 | #else | |
152b2262 | 84 | #define WARN_ON(x) WARN((x), "%s", "WARN_ON(" __stringify(x) ")") |
5f77eeb0 DV |
85 | #endif |
86 | ||
cd9bfacb | 87 | #undef WARN_ON_ONCE |
152b2262 | 88 | #define WARN_ON_ONCE(x) WARN_ONCE((x), "%s", "WARN_ON_ONCE(" __stringify(x) ")") |
cd9bfacb | 89 | |
5f77eeb0 DV |
90 | #define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \ |
91 | (long) (x), __func__); | |
c883ef1b | 92 | |
e2c719b7 RC |
93 | /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and |
94 | * WARN_ON()) for hw state sanity checks to check for unexpected conditions | |
95 | * which may not necessarily be a user visible problem. This will either | |
96 | * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to | |
97 | * enable distros and users to tailor their preferred amount of i915 abrt | |
98 | * spam. | |
99 | */ | |
100 | #define I915_STATE_WARN(condition, format...) ({ \ | |
101 | int __ret_warn_on = !!(condition); \ | |
32753cb8 JL |
102 | if (unlikely(__ret_warn_on)) \ |
103 | if (!WARN(i915.verbose_state_checks, format)) \ | |
e2c719b7 | 104 | DRM_ERROR(format); \ |
e2c719b7 RC |
105 | unlikely(__ret_warn_on); \ |
106 | }) | |
107 | ||
152b2262 JL |
108 | #define I915_STATE_WARN_ON(x) \ |
109 | I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")") | |
c883ef1b | 110 | |
4fec15d1 ID |
111 | bool __i915_inject_load_failure(const char *func, int line); |
112 | #define i915_inject_load_failure() \ | |
113 | __i915_inject_load_failure(__func__, __LINE__) | |
114 | ||
42a8ca4c JN |
115 | static inline const char *yesno(bool v) |
116 | { | |
117 | return v ? "yes" : "no"; | |
118 | } | |
119 | ||
87ad3212 JN |
120 | static inline const char *onoff(bool v) |
121 | { | |
122 | return v ? "on" : "off"; | |
123 | } | |
124 | ||
317c35d1 | 125 | enum pipe { |
752aa88a | 126 | INVALID_PIPE = -1, |
317c35d1 JB |
127 | PIPE_A = 0, |
128 | PIPE_B, | |
9db4a9c7 | 129 | PIPE_C, |
a57c774a AK |
130 | _PIPE_EDP, |
131 | I915_MAX_PIPES = _PIPE_EDP | |
317c35d1 | 132 | }; |
9db4a9c7 | 133 | #define pipe_name(p) ((p) + 'A') |
317c35d1 | 134 | |
a5c961d1 PZ |
135 | enum transcoder { |
136 | TRANSCODER_A = 0, | |
137 | TRANSCODER_B, | |
138 | TRANSCODER_C, | |
a57c774a | 139 | TRANSCODER_EDP, |
4d1de975 JN |
140 | TRANSCODER_DSI_A, |
141 | TRANSCODER_DSI_C, | |
a57c774a | 142 | I915_MAX_TRANSCODERS |
a5c961d1 | 143 | }; |
da205630 JN |
144 | |
145 | static inline const char *transcoder_name(enum transcoder transcoder) | |
146 | { | |
147 | switch (transcoder) { | |
148 | case TRANSCODER_A: | |
149 | return "A"; | |
150 | case TRANSCODER_B: | |
151 | return "B"; | |
152 | case TRANSCODER_C: | |
153 | return "C"; | |
154 | case TRANSCODER_EDP: | |
155 | return "EDP"; | |
4d1de975 JN |
156 | case TRANSCODER_DSI_A: |
157 | return "DSI A"; | |
158 | case TRANSCODER_DSI_C: | |
159 | return "DSI C"; | |
da205630 JN |
160 | default: |
161 | return "<invalid>"; | |
162 | } | |
163 | } | |
a5c961d1 | 164 | |
4d1de975 JN |
165 | static inline bool transcoder_is_dsi(enum transcoder transcoder) |
166 | { | |
167 | return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C; | |
168 | } | |
169 | ||
84139d1e | 170 | /* |
31409e97 MR |
171 | * I915_MAX_PLANES in the enum below is the maximum (across all platforms) |
172 | * number of planes per CRTC. Not all platforms really have this many planes, | |
173 | * which means some arrays of size I915_MAX_PLANES may have unused entries | |
174 | * between the topmost sprite plane and the cursor plane. | |
84139d1e | 175 | */ |
80824003 JB |
176 | enum plane { |
177 | PLANE_A = 0, | |
178 | PLANE_B, | |
9db4a9c7 | 179 | PLANE_C, |
31409e97 MR |
180 | PLANE_CURSOR, |
181 | I915_MAX_PLANES, | |
80824003 | 182 | }; |
9db4a9c7 | 183 | #define plane_name(p) ((p) + 'A') |
52440211 | 184 | |
d615a166 | 185 | #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A') |
06da8da2 | 186 | |
2b139522 ED |
187 | enum port { |
188 | PORT_A = 0, | |
189 | PORT_B, | |
190 | PORT_C, | |
191 | PORT_D, | |
192 | PORT_E, | |
193 | I915_MAX_PORTS | |
194 | }; | |
195 | #define port_name(p) ((p) + 'A') | |
196 | ||
a09caddd | 197 | #define I915_NUM_PHYS_VLV 2 |
e4607fcf CML |
198 | |
199 | enum dpio_channel { | |
200 | DPIO_CH0, | |
201 | DPIO_CH1 | |
202 | }; | |
203 | ||
204 | enum dpio_phy { | |
205 | DPIO_PHY0, | |
206 | DPIO_PHY1 | |
207 | }; | |
208 | ||
b97186f0 PZ |
209 | enum intel_display_power_domain { |
210 | POWER_DOMAIN_PIPE_A, | |
211 | POWER_DOMAIN_PIPE_B, | |
212 | POWER_DOMAIN_PIPE_C, | |
213 | POWER_DOMAIN_PIPE_A_PANEL_FITTER, | |
214 | POWER_DOMAIN_PIPE_B_PANEL_FITTER, | |
215 | POWER_DOMAIN_PIPE_C_PANEL_FITTER, | |
216 | POWER_DOMAIN_TRANSCODER_A, | |
217 | POWER_DOMAIN_TRANSCODER_B, | |
218 | POWER_DOMAIN_TRANSCODER_C, | |
f52e353e | 219 | POWER_DOMAIN_TRANSCODER_EDP, |
4d1de975 JN |
220 | POWER_DOMAIN_TRANSCODER_DSI_A, |
221 | POWER_DOMAIN_TRANSCODER_DSI_C, | |
6331a704 PJ |
222 | POWER_DOMAIN_PORT_DDI_A_LANES, |
223 | POWER_DOMAIN_PORT_DDI_B_LANES, | |
224 | POWER_DOMAIN_PORT_DDI_C_LANES, | |
225 | POWER_DOMAIN_PORT_DDI_D_LANES, | |
226 | POWER_DOMAIN_PORT_DDI_E_LANES, | |
319be8ae ID |
227 | POWER_DOMAIN_PORT_DSI, |
228 | POWER_DOMAIN_PORT_CRT, | |
229 | POWER_DOMAIN_PORT_OTHER, | |
cdf8dd7f | 230 | POWER_DOMAIN_VGA, |
fbeeaa23 | 231 | POWER_DOMAIN_AUDIO, |
bd2bb1b9 | 232 | POWER_DOMAIN_PLLS, |
1407121a S |
233 | POWER_DOMAIN_AUX_A, |
234 | POWER_DOMAIN_AUX_B, | |
235 | POWER_DOMAIN_AUX_C, | |
236 | POWER_DOMAIN_AUX_D, | |
f0ab43e6 | 237 | POWER_DOMAIN_GMBUS, |
dfa57627 | 238 | POWER_DOMAIN_MODESET, |
baa70707 | 239 | POWER_DOMAIN_INIT, |
bddc7645 ID |
240 | |
241 | POWER_DOMAIN_NUM, | |
b97186f0 PZ |
242 | }; |
243 | ||
244 | #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A) | |
245 | #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \ | |
246 | ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER) | |
f52e353e ID |
247 | #define POWER_DOMAIN_TRANSCODER(tran) \ |
248 | ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \ | |
249 | (tran) + POWER_DOMAIN_TRANSCODER_A) | |
b97186f0 | 250 | |
1d843f9d EE |
251 | enum hpd_pin { |
252 | HPD_NONE = 0, | |
1d843f9d EE |
253 | HPD_TV = HPD_NONE, /* TV is known to be unreliable */ |
254 | HPD_CRT, | |
255 | HPD_SDVO_B, | |
256 | HPD_SDVO_C, | |
cc24fcdc | 257 | HPD_PORT_A, |
1d843f9d EE |
258 | HPD_PORT_B, |
259 | HPD_PORT_C, | |
260 | HPD_PORT_D, | |
26951caf | 261 | HPD_PORT_E, |
1d843f9d EE |
262 | HPD_NUM_PINS |
263 | }; | |
264 | ||
c91711f9 JN |
265 | #define for_each_hpd_pin(__pin) \ |
266 | for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++) | |
267 | ||
5fcece80 JN |
268 | struct i915_hotplug { |
269 | struct work_struct hotplug_work; | |
270 | ||
271 | struct { | |
272 | unsigned long last_jiffies; | |
273 | int count; | |
274 | enum { | |
275 | HPD_ENABLED = 0, | |
276 | HPD_DISABLED = 1, | |
277 | HPD_MARK_DISABLED = 2 | |
278 | } state; | |
279 | } stats[HPD_NUM_PINS]; | |
280 | u32 event_bits; | |
281 | struct delayed_work reenable_work; | |
282 | ||
283 | struct intel_digital_port *irq_port[I915_MAX_PORTS]; | |
284 | u32 long_port_mask; | |
285 | u32 short_port_mask; | |
286 | struct work_struct dig_port_work; | |
287 | ||
19625e85 L |
288 | struct work_struct poll_init_work; |
289 | bool poll_enabled; | |
290 | ||
5fcece80 JN |
291 | /* |
292 | * if we get a HPD irq from DP and a HPD irq from non-DP | |
293 | * the non-DP HPD could block the workqueue on a mode config | |
294 | * mutex getting, that userspace may have taken. However | |
295 | * userspace is waiting on the DP workqueue to run which is | |
296 | * blocked behind the non-DP one. | |
297 | */ | |
298 | struct workqueue_struct *dp_wq; | |
299 | }; | |
300 | ||
2a2d5482 CW |
301 | #define I915_GEM_GPU_DOMAINS \ |
302 | (I915_GEM_DOMAIN_RENDER | \ | |
303 | I915_GEM_DOMAIN_SAMPLER | \ | |
304 | I915_GEM_DOMAIN_COMMAND | \ | |
305 | I915_GEM_DOMAIN_INSTRUCTION | \ | |
306 | I915_GEM_DOMAIN_VERTEX) | |
62fdfeaf | 307 | |
055e393f DL |
308 | #define for_each_pipe(__dev_priv, __p) \ |
309 | for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) | |
6831f3e3 VS |
310 | #define for_each_pipe_masked(__dev_priv, __p, __mask) \ |
311 | for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) \ | |
312 | for_each_if ((__mask) & (1 << (__p))) | |
dd740780 DL |
313 | #define for_each_plane(__dev_priv, __pipe, __p) \ |
314 | for ((__p) = 0; \ | |
315 | (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \ | |
316 | (__p)++) | |
3bdcfc0c DL |
317 | #define for_each_sprite(__dev_priv, __p, __s) \ |
318 | for ((__s) = 0; \ | |
319 | (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \ | |
320 | (__s)++) | |
9db4a9c7 | 321 | |
c3aeadc8 JN |
322 | #define for_each_port_masked(__port, __ports_mask) \ |
323 | for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++) \ | |
324 | for_each_if ((__ports_mask) & (1 << (__port))) | |
325 | ||
d79b814d | 326 | #define for_each_crtc(dev, crtc) \ |
91c8a326 | 327 | list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head) |
d79b814d | 328 | |
27321ae8 ML |
329 | #define for_each_intel_plane(dev, intel_plane) \ |
330 | list_for_each_entry(intel_plane, \ | |
91c8a326 | 331 | &(dev)->mode_config.plane_list, \ |
27321ae8 ML |
332 | base.head) |
333 | ||
c107acfe | 334 | #define for_each_intel_plane_mask(dev, intel_plane, plane_mask) \ |
91c8a326 CW |
335 | list_for_each_entry(intel_plane, \ |
336 | &(dev)->mode_config.plane_list, \ | |
c107acfe MR |
337 | base.head) \ |
338 | for_each_if ((plane_mask) & \ | |
339 | (1 << drm_plane_index(&intel_plane->base))) | |
340 | ||
262cd2e1 VS |
341 | #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \ |
342 | list_for_each_entry(intel_plane, \ | |
343 | &(dev)->mode_config.plane_list, \ | |
344 | base.head) \ | |
95150bdf | 345 | for_each_if ((intel_plane)->pipe == (intel_crtc)->pipe) |
262cd2e1 | 346 | |
91c8a326 CW |
347 | #define for_each_intel_crtc(dev, intel_crtc) \ |
348 | list_for_each_entry(intel_crtc, \ | |
349 | &(dev)->mode_config.crtc_list, \ | |
350 | base.head) | |
d063ae48 | 351 | |
91c8a326 CW |
352 | #define for_each_intel_crtc_mask(dev, intel_crtc, crtc_mask) \ |
353 | list_for_each_entry(intel_crtc, \ | |
354 | &(dev)->mode_config.crtc_list, \ | |
355 | base.head) \ | |
98d39494 MR |
356 | for_each_if ((crtc_mask) & (1 << drm_crtc_index(&intel_crtc->base))) |
357 | ||
b2784e15 DL |
358 | #define for_each_intel_encoder(dev, intel_encoder) \ |
359 | list_for_each_entry(intel_encoder, \ | |
360 | &(dev)->mode_config.encoder_list, \ | |
361 | base.head) | |
362 | ||
3a3371ff ACO |
363 | #define for_each_intel_connector(dev, intel_connector) \ |
364 | list_for_each_entry(intel_connector, \ | |
91c8a326 | 365 | &(dev)->mode_config.connector_list, \ |
3a3371ff ACO |
366 | base.head) |
367 | ||
6c2b7c12 DV |
368 | #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \ |
369 | list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \ | |
95150bdf | 370 | for_each_if ((intel_encoder)->base.crtc == (__crtc)) |
6c2b7c12 | 371 | |
53f5e3ca JB |
372 | #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \ |
373 | list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \ | |
95150bdf | 374 | for_each_if ((intel_connector)->base.encoder == (__encoder)) |
53f5e3ca | 375 | |
b04c5bd6 BF |
376 | #define for_each_power_domain(domain, mask) \ |
377 | for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \ | |
95150bdf | 378 | for_each_if ((1 << (domain)) & (mask)) |
b04c5bd6 | 379 | |
e7b903d2 | 380 | struct drm_i915_private; |
ad46cb53 | 381 | struct i915_mm_struct; |
5cc9ed4b | 382 | struct i915_mmu_object; |
e7b903d2 | 383 | |
a6f766f3 CW |
384 | struct drm_i915_file_private { |
385 | struct drm_i915_private *dev_priv; | |
386 | struct drm_file *file; | |
387 | ||
388 | struct { | |
389 | spinlock_t lock; | |
390 | struct list_head request_list; | |
d0bc54f2 CW |
391 | /* 20ms is a fairly arbitrary limit (greater than the average frame time) |
392 | * chosen to prevent the CPU getting more than a frame ahead of the GPU | |
393 | * (when using lax throttling for the frontbuffer). We also use it to | |
394 | * offer free GPU waitboosts for severely congested workloads. | |
395 | */ | |
396 | #define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20) | |
a6f766f3 CW |
397 | } mm; |
398 | struct idr context_idr; | |
399 | ||
2e1b8730 CW |
400 | struct intel_rps_client { |
401 | struct list_head link; | |
402 | unsigned boosts; | |
403 | } rps; | |
a6f766f3 | 404 | |
c80ff16e | 405 | unsigned int bsd_engine; |
a6f766f3 CW |
406 | }; |
407 | ||
e69d0bc1 DV |
408 | /* Used by dp and fdi links */ |
409 | struct intel_link_m_n { | |
410 | uint32_t tu; | |
411 | uint32_t gmch_m; | |
412 | uint32_t gmch_n; | |
413 | uint32_t link_m; | |
414 | uint32_t link_n; | |
415 | }; | |
416 | ||
417 | void intel_link_compute_m_n(int bpp, int nlanes, | |
418 | int pixel_clock, int link_clock, | |
419 | struct intel_link_m_n *m_n); | |
420 | ||
1da177e4 LT |
421 | /* Interface history: |
422 | * | |
423 | * 1.1: Original. | |
0d6aa60b DA |
424 | * 1.2: Add Power Management |
425 | * 1.3: Add vblank support | |
de227f5f | 426 | * 1.4: Fix cmdbuffer path, add heap destroy |
702880f2 | 427 | * 1.5: Add vblank pipe configuration |
2228ed67 MCA |
428 | * 1.6: - New ioctl for scheduling buffer swaps on vertical blank |
429 | * - Support vertical blank on secondary display pipe | |
1da177e4 LT |
430 | */ |
431 | #define DRIVER_MAJOR 1 | |
2228ed67 | 432 | #define DRIVER_MINOR 6 |
1da177e4 LT |
433 | #define DRIVER_PATCHLEVEL 0 |
434 | ||
0a3e67a4 JB |
435 | struct opregion_header; |
436 | struct opregion_acpi; | |
437 | struct opregion_swsci; | |
438 | struct opregion_asle; | |
439 | ||
8ee1c3db | 440 | struct intel_opregion { |
115719fc WD |
441 | struct opregion_header *header; |
442 | struct opregion_acpi *acpi; | |
443 | struct opregion_swsci *swsci; | |
ebde53c7 JN |
444 | u32 swsci_gbda_sub_functions; |
445 | u32 swsci_sbcb_sub_functions; | |
115719fc | 446 | struct opregion_asle *asle; |
04ebaadb | 447 | void *rvda; |
82730385 | 448 | const void *vbt; |
ada8f955 | 449 | u32 vbt_size; |
115719fc | 450 | u32 *lid_state; |
91a60f20 | 451 | struct work_struct asle_work; |
8ee1c3db | 452 | }; |
44834a67 | 453 | #define OPREGION_SIZE (8*1024) |
8ee1c3db | 454 | |
6ef3d427 CW |
455 | struct intel_overlay; |
456 | struct intel_overlay_error_state; | |
457 | ||
de151cf6 | 458 | struct drm_i915_fence_reg { |
a1e5afbe | 459 | struct list_head link; |
49ef5294 CW |
460 | struct drm_i915_private *i915; |
461 | struct i915_vma *vma; | |
1690e1eb | 462 | int pin_count; |
49ef5294 CW |
463 | int id; |
464 | /** | |
465 | * Whether the tiling parameters for the currently | |
466 | * associated fence register have changed. Note that | |
467 | * for the purposes of tracking tiling changes we also | |
468 | * treat the unfenced register, the register slot that | |
469 | * the object occupies whilst it executes a fenced | |
470 | * command (such as BLT on gen2/3), as a "fence". | |
471 | */ | |
472 | bool dirty; | |
de151cf6 | 473 | }; |
7c1c2871 | 474 | |
9b9d172d | 475 | struct sdvo_device_mapping { |
e957d772 | 476 | u8 initialized; |
9b9d172d | 477 | u8 dvo_port; |
478 | u8 slave_addr; | |
479 | u8 dvo_wiring; | |
e957d772 | 480 | u8 i2c_pin; |
b1083333 | 481 | u8 ddc_pin; |
9b9d172d | 482 | }; |
483 | ||
7bd688cd | 484 | struct intel_connector; |
820d2d77 | 485 | struct intel_encoder; |
5cec258b | 486 | struct intel_crtc_state; |
5724dbd1 | 487 | struct intel_initial_plane_config; |
0e8ffe1b | 488 | struct intel_crtc; |
ee9300bb DV |
489 | struct intel_limit; |
490 | struct dpll; | |
b8cecdf5 | 491 | |
e70236a8 | 492 | struct drm_i915_display_funcs { |
e70236a8 JB |
493 | int (*get_display_clock_speed)(struct drm_device *dev); |
494 | int (*get_fifo_size)(struct drm_device *dev, int plane); | |
e3bddded | 495 | int (*compute_pipe_wm)(struct intel_crtc_state *cstate); |
ed4a6a7c MR |
496 | int (*compute_intermediate_wm)(struct drm_device *dev, |
497 | struct intel_crtc *intel_crtc, | |
498 | struct intel_crtc_state *newstate); | |
499 | void (*initial_watermarks)(struct intel_crtc_state *cstate); | |
500 | void (*optimize_watermarks)(struct intel_crtc_state *cstate); | |
98d39494 | 501 | int (*compute_global_watermarks)(struct drm_atomic_state *state); |
46ba614c | 502 | void (*update_wm)(struct drm_crtc *crtc); |
27c329ed ML |
503 | int (*modeset_calc_cdclk)(struct drm_atomic_state *state); |
504 | void (*modeset_commit_cdclk)(struct drm_atomic_state *state); | |
0e8ffe1b DV |
505 | /* Returns the active state of the crtc, and if the crtc is active, |
506 | * fills out the pipe-config with the hw state. */ | |
507 | bool (*get_pipe_config)(struct intel_crtc *, | |
5cec258b | 508 | struct intel_crtc_state *); |
5724dbd1 DL |
509 | void (*get_initial_plane_config)(struct intel_crtc *, |
510 | struct intel_initial_plane_config *); | |
190f68c5 ACO |
511 | int (*crtc_compute_clock)(struct intel_crtc *crtc, |
512 | struct intel_crtc_state *crtc_state); | |
4a806558 ML |
513 | void (*crtc_enable)(struct intel_crtc_state *pipe_config, |
514 | struct drm_atomic_state *old_state); | |
515 | void (*crtc_disable)(struct intel_crtc_state *old_crtc_state, | |
516 | struct drm_atomic_state *old_state); | |
896e5bb0 L |
517 | void (*update_crtcs)(struct drm_atomic_state *state, |
518 | unsigned int *crtc_vblank_mask); | |
69bfe1a9 JN |
519 | void (*audio_codec_enable)(struct drm_connector *connector, |
520 | struct intel_encoder *encoder, | |
5e7234c9 | 521 | const struct drm_display_mode *adjusted_mode); |
69bfe1a9 | 522 | void (*audio_codec_disable)(struct intel_encoder *encoder); |
674cf967 | 523 | void (*fdi_link_train)(struct drm_crtc *crtc); |
6067aaea | 524 | void (*init_clock_gating)(struct drm_device *dev); |
5a21b665 DV |
525 | int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc, |
526 | struct drm_framebuffer *fb, | |
527 | struct drm_i915_gem_object *obj, | |
528 | struct drm_i915_gem_request *req, | |
529 | uint32_t flags); | |
91d14251 | 530 | void (*hpd_irq_setup)(struct drm_i915_private *dev_priv); |
e70236a8 JB |
531 | /* clock updates for mode set */ |
532 | /* cursor updates */ | |
533 | /* render clock increase/decrease */ | |
534 | /* display clock increase/decrease */ | |
535 | /* pll clock increase/decrease */ | |
8563b1e8 | 536 | |
b95c5321 ML |
537 | void (*load_csc_matrix)(struct drm_crtc_state *crtc_state); |
538 | void (*load_luts)(struct drm_crtc_state *crtc_state); | |
e70236a8 JB |
539 | }; |
540 | ||
48c1026a MK |
541 | enum forcewake_domain_id { |
542 | FW_DOMAIN_ID_RENDER = 0, | |
543 | FW_DOMAIN_ID_BLITTER, | |
544 | FW_DOMAIN_ID_MEDIA, | |
545 | ||
546 | FW_DOMAIN_ID_COUNT | |
547 | }; | |
548 | ||
549 | enum forcewake_domains { | |
550 | FORCEWAKE_RENDER = (1 << FW_DOMAIN_ID_RENDER), | |
551 | FORCEWAKE_BLITTER = (1 << FW_DOMAIN_ID_BLITTER), | |
552 | FORCEWAKE_MEDIA = (1 << FW_DOMAIN_ID_MEDIA), | |
553 | FORCEWAKE_ALL = (FORCEWAKE_RENDER | | |
554 | FORCEWAKE_BLITTER | | |
555 | FORCEWAKE_MEDIA) | |
556 | }; | |
557 | ||
3756685a TU |
558 | #define FW_REG_READ (1) |
559 | #define FW_REG_WRITE (2) | |
560 | ||
561 | enum forcewake_domains | |
562 | intel_uncore_forcewake_for_reg(struct drm_i915_private *dev_priv, | |
563 | i915_reg_t reg, unsigned int op); | |
564 | ||
907b28c5 | 565 | struct intel_uncore_funcs { |
c8d9a590 | 566 | void (*force_wake_get)(struct drm_i915_private *dev_priv, |
48c1026a | 567 | enum forcewake_domains domains); |
c8d9a590 | 568 | void (*force_wake_put)(struct drm_i915_private *dev_priv, |
48c1026a | 569 | enum forcewake_domains domains); |
0b274481 | 570 | |
f0f59a00 VS |
571 | uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace); |
572 | uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace); | |
573 | uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace); | |
574 | uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace); | |
0b274481 | 575 | |
f0f59a00 | 576 | void (*mmio_writeb)(struct drm_i915_private *dev_priv, i915_reg_t r, |
0b274481 | 577 | uint8_t val, bool trace); |
f0f59a00 | 578 | void (*mmio_writew)(struct drm_i915_private *dev_priv, i915_reg_t r, |
0b274481 | 579 | uint16_t val, bool trace); |
f0f59a00 | 580 | void (*mmio_writel)(struct drm_i915_private *dev_priv, i915_reg_t r, |
0b274481 | 581 | uint32_t val, bool trace); |
990bbdad CW |
582 | }; |
583 | ||
907b28c5 CW |
584 | struct intel_uncore { |
585 | spinlock_t lock; /** lock is also taken in irq contexts. */ | |
586 | ||
587 | struct intel_uncore_funcs funcs; | |
588 | ||
589 | unsigned fifo_count; | |
48c1026a | 590 | enum forcewake_domains fw_domains; |
b2cff0db CW |
591 | |
592 | struct intel_uncore_forcewake_domain { | |
593 | struct drm_i915_private *i915; | |
48c1026a | 594 | enum forcewake_domain_id id; |
33c582c1 | 595 | enum forcewake_domains mask; |
b2cff0db | 596 | unsigned wake_count; |
a57a4a67 | 597 | struct hrtimer timer; |
f0f59a00 | 598 | i915_reg_t reg_set; |
05a2fb15 MK |
599 | u32 val_set; |
600 | u32 val_clear; | |
f0f59a00 VS |
601 | i915_reg_t reg_ack; |
602 | i915_reg_t reg_post; | |
05a2fb15 | 603 | u32 val_reset; |
b2cff0db | 604 | } fw_domain[FW_DOMAIN_ID_COUNT]; |
75714940 MK |
605 | |
606 | int unclaimed_mmio_check; | |
b2cff0db CW |
607 | }; |
608 | ||
609 | /* Iterate over initialised fw domains */ | |
33c582c1 TU |
610 | #define for_each_fw_domain_masked(domain__, mask__, dev_priv__) \ |
611 | for ((domain__) = &(dev_priv__)->uncore.fw_domain[0]; \ | |
612 | (domain__) < &(dev_priv__)->uncore.fw_domain[FW_DOMAIN_ID_COUNT]; \ | |
613 | (domain__)++) \ | |
614 | for_each_if ((mask__) & (domain__)->mask) | |
615 | ||
616 | #define for_each_fw_domain(domain__, dev_priv__) \ | |
617 | for_each_fw_domain_masked(domain__, FORCEWAKE_ALL, dev_priv__) | |
907b28c5 | 618 | |
b6e7d894 DL |
619 | #define CSR_VERSION(major, minor) ((major) << 16 | (minor)) |
620 | #define CSR_VERSION_MAJOR(version) ((version) >> 16) | |
621 | #define CSR_VERSION_MINOR(version) ((version) & 0xffff) | |
622 | ||
eb805623 | 623 | struct intel_csr { |
8144ac59 | 624 | struct work_struct work; |
eb805623 | 625 | const char *fw_path; |
a7f749f9 | 626 | uint32_t *dmc_payload; |
eb805623 | 627 | uint32_t dmc_fw_size; |
b6e7d894 | 628 | uint32_t version; |
eb805623 | 629 | uint32_t mmio_count; |
f0f59a00 | 630 | i915_reg_t mmioaddr[8]; |
eb805623 | 631 | uint32_t mmiodata[8]; |
832dba88 | 632 | uint32_t dc_state; |
a37baf3b | 633 | uint32_t allowed_dc_mask; |
eb805623 DV |
634 | }; |
635 | ||
79fc46df DL |
636 | #define DEV_INFO_FOR_EACH_FLAG(func, sep) \ |
637 | func(is_mobile) sep \ | |
638 | func(is_i85x) sep \ | |
639 | func(is_i915g) sep \ | |
640 | func(is_i945gm) sep \ | |
641 | func(is_g33) sep \ | |
3177659a | 642 | func(hws_needs_physical) sep \ |
79fc46df DL |
643 | func(is_g4x) sep \ |
644 | func(is_pineview) sep \ | |
645 | func(is_broadwater) sep \ | |
646 | func(is_crestline) sep \ | |
647 | func(is_ivybridge) sep \ | |
648 | func(is_valleyview) sep \ | |
666a4537 | 649 | func(is_cherryview) sep \ |
79fc46df | 650 | func(is_haswell) sep \ |
ab0d24ac | 651 | func(is_broadwell) sep \ |
7201c0b3 | 652 | func(is_skylake) sep \ |
7526ac19 | 653 | func(is_broxton) sep \ |
ef11bdb3 | 654 | func(is_kabylake) sep \ |
b833d685 | 655 | func(is_preliminary) sep \ |
79fc46df | 656 | func(has_fbc) sep \ |
6e3b84d8 | 657 | func(has_psr) sep \ |
4aa4c23f | 658 | func(has_runtime_pm) sep \ |
3bacde19 | 659 | func(has_csr) sep \ |
53233f08 | 660 | func(has_resource_streamer) sep \ |
86f3624b | 661 | func(has_rc6) sep \ |
33b5bf82 | 662 | func(has_rc6p) sep \ |
1d3fe53b | 663 | func(has_dp_mst) sep \ |
b355f109 | 664 | func(has_gmbus_irq) sep \ |
e1a52536 | 665 | func(has_hw_contexts) sep \ |
4586f1d0 | 666 | func(has_logical_ring_contexts) sep \ |
ca9c4523 | 667 | func(has_l3_dpf) sep \ |
804b8712 | 668 | func(has_gmch_display) sep \ |
3d810fbe | 669 | func(has_guc) sep \ |
79fc46df DL |
670 | func(has_pipe_cxsr) sep \ |
671 | func(has_hotplug) sep \ | |
672 | func(cursor_needs_physical) sep \ | |
673 | func(has_overlay) sep \ | |
674 | func(overlay_needs_physical) sep \ | |
675 | func(supports_tv) sep \ | |
dd93be58 | 676 | func(has_llc) sep \ |
ca377809 | 677 | func(has_snoop) sep \ |
30568c45 | 678 | func(has_ddi) sep \ |
33e141ed | 679 | func(has_fpga_dbg) sep \ |
680 | func(has_pooled_eu) | |
c96ea64e | 681 | |
a587f779 DL |
682 | #define DEFINE_FLAG(name) u8 name:1 |
683 | #define SEP_SEMICOLON ; | |
c96ea64e | 684 | |
915490d5 | 685 | struct sseu_dev_info { |
f08a0c92 | 686 | u8 slice_mask; |
57ec171e | 687 | u8 subslice_mask; |
915490d5 ID |
688 | u8 eu_total; |
689 | u8 eu_per_subslice; | |
43b67998 ID |
690 | u8 min_eu_in_pool; |
691 | /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */ | |
692 | u8 subslice_7eu[3]; | |
693 | u8 has_slice_pg:1; | |
694 | u8 has_subslice_pg:1; | |
695 | u8 has_eu_pg:1; | |
915490d5 ID |
696 | }; |
697 | ||
57ec171e ID |
698 | static inline unsigned int sseu_subslice_total(const struct sseu_dev_info *sseu) |
699 | { | |
700 | return hweight8(sseu->slice_mask) * hweight8(sseu->subslice_mask); | |
701 | } | |
702 | ||
cfdf1fa2 | 703 | struct intel_device_info { |
10fce67a | 704 | u32 display_mmio_offset; |
87f1f465 | 705 | u16 device_id; |
ac208a8b | 706 | u8 num_pipes; |
d615a166 | 707 | u8 num_sprites[I915_MAX_PIPES]; |
c96c3a8c | 708 | u8 gen; |
ae5702d2 | 709 | u16 gen_mask; |
73ae478c | 710 | u8 ring_mask; /* Rings supported by the HW */ |
c1bb1145 | 711 | u8 num_rings; |
a587f779 | 712 | DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON); |
a57c774a AK |
713 | /* Register offsets for the various display pipes and transcoders */ |
714 | int pipe_offsets[I915_MAX_TRANSCODERS]; | |
715 | int trans_offsets[I915_MAX_TRANSCODERS]; | |
a57c774a | 716 | int palette_offsets[I915_MAX_PIPES]; |
5efb3e28 | 717 | int cursor_offsets[I915_MAX_PIPES]; |
3873218f JM |
718 | |
719 | /* Slice/subslice/EU info */ | |
43b67998 | 720 | struct sseu_dev_info sseu; |
82cf435b LL |
721 | |
722 | struct color_luts { | |
723 | u16 degamma_lut_size; | |
724 | u16 gamma_lut_size; | |
725 | } color; | |
cfdf1fa2 KH |
726 | }; |
727 | ||
a587f779 DL |
728 | #undef DEFINE_FLAG |
729 | #undef SEP_SEMICOLON | |
730 | ||
2bd160a1 CW |
731 | struct intel_display_error_state; |
732 | ||
733 | struct drm_i915_error_state { | |
734 | struct kref ref; | |
735 | struct timeval time; | |
736 | ||
737 | char error_msg[128]; | |
738 | bool simulated; | |
739 | int iommu; | |
740 | u32 reset_count; | |
741 | u32 suspend_count; | |
742 | struct intel_device_info device_info; | |
743 | ||
744 | /* Generic register state */ | |
745 | u32 eir; | |
746 | u32 pgtbl_er; | |
747 | u32 ier; | |
748 | u32 gtier[4]; | |
749 | u32 ccid; | |
750 | u32 derrmr; | |
751 | u32 forcewake; | |
752 | u32 error; /* gen6+ */ | |
753 | u32 err_int; /* gen7 */ | |
754 | u32 fault_data0; /* gen8, gen9 */ | |
755 | u32 fault_data1; /* gen8, gen9 */ | |
756 | u32 done_reg; | |
757 | u32 gac_eco; | |
758 | u32 gam_ecochk; | |
759 | u32 gab_ctl; | |
760 | u32 gfx_mode; | |
761 | u32 extra_instdone[I915_NUM_INSTDONE_REG]; | |
762 | u64 fence[I915_MAX_NUM_FENCES]; | |
763 | struct intel_overlay_error_state *overlay; | |
764 | struct intel_display_error_state *display; | |
51d545d0 | 765 | struct drm_i915_error_object *semaphore; |
2bd160a1 CW |
766 | |
767 | struct drm_i915_error_engine { | |
768 | int engine_id; | |
769 | /* Software tracked state */ | |
770 | bool waiting; | |
771 | int num_waiters; | |
772 | int hangcheck_score; | |
773 | enum intel_engine_hangcheck_action hangcheck_action; | |
774 | struct i915_address_space *vm; | |
775 | int num_requests; | |
776 | ||
777 | /* our own tracking of ring head and tail */ | |
778 | u32 cpu_ring_head; | |
779 | u32 cpu_ring_tail; | |
780 | ||
781 | u32 last_seqno; | |
782 | u32 semaphore_seqno[I915_NUM_ENGINES - 1]; | |
783 | ||
784 | /* Register state */ | |
785 | u32 start; | |
786 | u32 tail; | |
787 | u32 head; | |
788 | u32 ctl; | |
21a2c58a | 789 | u32 mode; |
2bd160a1 CW |
790 | u32 hws; |
791 | u32 ipeir; | |
792 | u32 ipehr; | |
793 | u32 instdone; | |
794 | u32 bbstate; | |
795 | u32 instpm; | |
796 | u32 instps; | |
797 | u32 seqno; | |
798 | u64 bbaddr; | |
799 | u64 acthd; | |
800 | u32 fault_reg; | |
801 | u64 faddr; | |
802 | u32 rc_psmi; /* sleep state */ | |
803 | u32 semaphore_mboxes[I915_NUM_ENGINES - 1]; | |
804 | ||
805 | struct drm_i915_error_object { | |
806 | int page_count; | |
807 | u64 gtt_offset; | |
03382dfb | 808 | u64 gtt_size; |
2bd160a1 CW |
809 | u32 *pages[0]; |
810 | } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page; | |
811 | ||
812 | struct drm_i915_error_object *wa_ctx; | |
813 | ||
814 | struct drm_i915_error_request { | |
815 | long jiffies; | |
c84455b4 | 816 | pid_t pid; |
2bd160a1 CW |
817 | u32 seqno; |
818 | u32 head; | |
819 | u32 tail; | |
820 | } *requests; | |
821 | ||
822 | struct drm_i915_error_waiter { | |
823 | char comm[TASK_COMM_LEN]; | |
824 | pid_t pid; | |
825 | u32 seqno; | |
826 | } *waiters; | |
827 | ||
828 | struct { | |
829 | u32 gfx_mode; | |
830 | union { | |
831 | u64 pdp[4]; | |
832 | u32 pp_dir_base; | |
833 | }; | |
834 | } vm_info; | |
835 | ||
836 | pid_t pid; | |
837 | char comm[TASK_COMM_LEN]; | |
838 | } engine[I915_NUM_ENGINES]; | |
839 | ||
840 | struct drm_i915_error_buffer { | |
841 | u32 size; | |
842 | u32 name; | |
843 | u32 rseqno[I915_NUM_ENGINES], wseqno; | |
844 | u64 gtt_offset; | |
845 | u32 read_domains; | |
846 | u32 write_domain; | |
847 | s32 fence_reg:I915_MAX_NUM_FENCE_BITS; | |
848 | u32 tiling:2; | |
849 | u32 dirty:1; | |
850 | u32 purgeable:1; | |
851 | u32 userptr:1; | |
852 | s32 engine:4; | |
853 | u32 cache_level:3; | |
854 | } *active_bo[I915_NUM_ENGINES], *pinned_bo; | |
855 | u32 active_bo_count[I915_NUM_ENGINES], pinned_bo_count; | |
856 | struct i915_address_space *active_vm[I915_NUM_ENGINES]; | |
857 | }; | |
858 | ||
7faf1ab2 DV |
859 | enum i915_cache_level { |
860 | I915_CACHE_NONE = 0, | |
350ec881 CW |
861 | I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */ |
862 | I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc | |
863 | caches, eg sampler/render caches, and the | |
864 | large Last-Level-Cache. LLC is coherent with | |
865 | the CPU, but L3 is only visible to the GPU. */ | |
651d794f | 866 | I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */ |
7faf1ab2 DV |
867 | }; |
868 | ||
e59ec13d MK |
869 | struct i915_ctx_hang_stats { |
870 | /* This context had batch pending when hang was declared */ | |
871 | unsigned batch_pending; | |
872 | ||
873 | /* This context had batch active when hang was declared */ | |
874 | unsigned batch_active; | |
be62acb4 MK |
875 | |
876 | /* Time when this context was last blamed for a GPU reset */ | |
877 | unsigned long guilty_ts; | |
878 | ||
676fa572 CW |
879 | /* If the contexts causes a second GPU hang within this time, |
880 | * it is permanently banned from submitting any more work. | |
881 | */ | |
882 | unsigned long ban_period_seconds; | |
883 | ||
be62acb4 MK |
884 | /* This context is banned to submit more work */ |
885 | bool banned; | |
e59ec13d | 886 | }; |
40521054 BW |
887 | |
888 | /* This must match up with the value previously used for execbuf2.rsvd1. */ | |
821d66dd | 889 | #define DEFAULT_CONTEXT_HANDLE 0 |
b1b38278 | 890 | |
31b7a88d | 891 | /** |
e2efd130 | 892 | * struct i915_gem_context - as the name implies, represents a context. |
31b7a88d OM |
893 | * @ref: reference count. |
894 | * @user_handle: userspace tracking identity for this context. | |
895 | * @remap_slice: l3 row remapping information. | |
b1b38278 DW |
896 | * @flags: context specific flags: |
897 | * CONTEXT_NO_ZEROMAP: do not allow mapping things to page 0. | |
31b7a88d OM |
898 | * @file_priv: filp associated with this context (NULL for global default |
899 | * context). | |
900 | * @hang_stats: information about the role of this context in possible GPU | |
901 | * hangs. | |
7df113e4 | 902 | * @ppgtt: virtual memory space used by this context. |
31b7a88d OM |
903 | * @legacy_hw_ctx: render context backing object and whether it is correctly |
904 | * initialized (legacy ring submission mechanism only). | |
905 | * @link: link in the global list of contexts. | |
906 | * | |
907 | * Contexts are memory images used by the hardware to store copies of their | |
908 | * internal state. | |
909 | */ | |
e2efd130 | 910 | struct i915_gem_context { |
dce3271b | 911 | struct kref ref; |
9ea4feec | 912 | struct drm_i915_private *i915; |
40521054 | 913 | struct drm_i915_file_private *file_priv; |
ae6c4806 | 914 | struct i915_hw_ppgtt *ppgtt; |
c84455b4 | 915 | struct pid *pid; |
a33afea5 | 916 | |
8d59bc6a CW |
917 | struct i915_ctx_hang_stats hang_stats; |
918 | ||
8d59bc6a | 919 | unsigned long flags; |
bc3d6744 CW |
920 | #define CONTEXT_NO_ZEROMAP BIT(0) |
921 | #define CONTEXT_NO_ERROR_CAPTURE BIT(1) | |
0be81156 DG |
922 | |
923 | /* Unique identifier for this context, used by the hw for tracking */ | |
924 | unsigned int hw_id; | |
8d59bc6a | 925 | u32 user_handle; |
5d1808ec | 926 | |
0cb26a8e CW |
927 | u32 ggtt_alignment; |
928 | ||
9021ad03 | 929 | struct intel_context { |
bf3783e5 | 930 | struct i915_vma *state; |
7e37f889 | 931 | struct intel_ring *ring; |
82352e90 | 932 | uint32_t *lrc_reg_state; |
8d59bc6a CW |
933 | u64 lrc_desc; |
934 | int pin_count; | |
24f1d3cc | 935 | bool initialised; |
666796da | 936 | } engine[I915_NUM_ENGINES]; |
bcd794c2 | 937 | u32 ring_size; |
c01fc532 | 938 | u32 desc_template; |
3c7ba635 | 939 | struct atomic_notifier_head status_notifier; |
80a9a8db | 940 | bool execlists_force_single_submission; |
c9e003af | 941 | |
a33afea5 | 942 | struct list_head link; |
8d59bc6a CW |
943 | |
944 | u8 remap_slice; | |
50e046b6 | 945 | bool closed:1; |
40521054 BW |
946 | }; |
947 | ||
a4001f1b PZ |
948 | enum fb_op_origin { |
949 | ORIGIN_GTT, | |
950 | ORIGIN_CPU, | |
951 | ORIGIN_CS, | |
952 | ORIGIN_FLIP, | |
74b4ea1e | 953 | ORIGIN_DIRTYFB, |
a4001f1b PZ |
954 | }; |
955 | ||
ab34a7e8 | 956 | struct intel_fbc { |
25ad93fd PZ |
957 | /* This is always the inner lock when overlapping with struct_mutex and |
958 | * it's the outer lock when overlapping with stolen_lock. */ | |
959 | struct mutex lock; | |
5e59f717 | 960 | unsigned threshold; |
dbef0f15 PZ |
961 | unsigned int possible_framebuffer_bits; |
962 | unsigned int busy_bits; | |
010cf73d | 963 | unsigned int visible_pipes_mask; |
e35fef21 | 964 | struct intel_crtc *crtc; |
5c3fe8b0 | 965 | |
c4213885 | 966 | struct drm_mm_node compressed_fb; |
5c3fe8b0 BW |
967 | struct drm_mm_node *compressed_llb; |
968 | ||
da46f936 RV |
969 | bool false_color; |
970 | ||
d029bcad | 971 | bool enabled; |
0e631adc | 972 | bool active; |
9adccc60 | 973 | |
aaf78d27 PZ |
974 | struct intel_fbc_state_cache { |
975 | struct { | |
976 | unsigned int mode_flags; | |
977 | uint32_t hsw_bdw_pixel_rate; | |
978 | } crtc; | |
979 | ||
980 | struct { | |
981 | unsigned int rotation; | |
982 | int src_w; | |
983 | int src_h; | |
984 | bool visible; | |
985 | } plane; | |
986 | ||
987 | struct { | |
988 | u64 ilk_ggtt_offset; | |
aaf78d27 PZ |
989 | uint32_t pixel_format; |
990 | unsigned int stride; | |
991 | int fence_reg; | |
992 | unsigned int tiling_mode; | |
993 | } fb; | |
994 | } state_cache; | |
995 | ||
b183b3f1 PZ |
996 | struct intel_fbc_reg_params { |
997 | struct { | |
998 | enum pipe pipe; | |
999 | enum plane plane; | |
1000 | unsigned int fence_y_offset; | |
1001 | } crtc; | |
1002 | ||
1003 | struct { | |
1004 | u64 ggtt_offset; | |
b183b3f1 PZ |
1005 | uint32_t pixel_format; |
1006 | unsigned int stride; | |
1007 | int fence_reg; | |
1008 | } fb; | |
1009 | ||
1010 | int cfb_size; | |
1011 | } params; | |
1012 | ||
5c3fe8b0 | 1013 | struct intel_fbc_work { |
128d7356 | 1014 | bool scheduled; |
ca18d51d | 1015 | u32 scheduled_vblank; |
128d7356 | 1016 | struct work_struct work; |
128d7356 | 1017 | } work; |
5c3fe8b0 | 1018 | |
bf6189c6 | 1019 | const char *no_fbc_reason; |
b5e50c3f JB |
1020 | }; |
1021 | ||
96178eeb VK |
1022 | /** |
1023 | * HIGH_RR is the highest eDP panel refresh rate read from EDID | |
1024 | * LOW_RR is the lowest eDP panel refresh rate found from EDID | |
1025 | * parsing for same resolution. | |
1026 | */ | |
1027 | enum drrs_refresh_rate_type { | |
1028 | DRRS_HIGH_RR, | |
1029 | DRRS_LOW_RR, | |
1030 | DRRS_MAX_RR, /* RR count */ | |
1031 | }; | |
1032 | ||
1033 | enum drrs_support_type { | |
1034 | DRRS_NOT_SUPPORTED = 0, | |
1035 | STATIC_DRRS_SUPPORT = 1, | |
1036 | SEAMLESS_DRRS_SUPPORT = 2 | |
439d7ac0 PB |
1037 | }; |
1038 | ||
2807cf69 | 1039 | struct intel_dp; |
96178eeb VK |
1040 | struct i915_drrs { |
1041 | struct mutex mutex; | |
1042 | struct delayed_work work; | |
1043 | struct intel_dp *dp; | |
1044 | unsigned busy_frontbuffer_bits; | |
1045 | enum drrs_refresh_rate_type refresh_rate_type; | |
1046 | enum drrs_support_type type; | |
1047 | }; | |
1048 | ||
a031d709 | 1049 | struct i915_psr { |
f0355c4a | 1050 | struct mutex lock; |
a031d709 RV |
1051 | bool sink_support; |
1052 | bool source_ok; | |
2807cf69 | 1053 | struct intel_dp *enabled; |
7c8f8a70 RV |
1054 | bool active; |
1055 | struct delayed_work work; | |
9ca15301 | 1056 | unsigned busy_frontbuffer_bits; |
474d1ec4 SJ |
1057 | bool psr2_support; |
1058 | bool aux_frame_sync; | |
60e5ffe3 | 1059 | bool link_standby; |
3f51e471 | 1060 | }; |
5c3fe8b0 | 1061 | |
3bad0781 | 1062 | enum intel_pch { |
f0350830 | 1063 | PCH_NONE = 0, /* No PCH present */ |
3bad0781 ZW |
1064 | PCH_IBX, /* Ibexpeak PCH */ |
1065 | PCH_CPT, /* Cougarpoint PCH */ | |
eb877ebf | 1066 | PCH_LPT, /* Lynxpoint PCH */ |
e7e7ea20 | 1067 | PCH_SPT, /* Sunrisepoint PCH */ |
22dea0be | 1068 | PCH_KBP, /* Kabypoint PCH */ |
40c7ead9 | 1069 | PCH_NOP, |
3bad0781 ZW |
1070 | }; |
1071 | ||
988d6ee8 PZ |
1072 | enum intel_sbi_destination { |
1073 | SBI_ICLK, | |
1074 | SBI_MPHY, | |
1075 | }; | |
1076 | ||
b690e96c | 1077 | #define QUIRK_PIPEA_FORCE (1<<0) |
435793df | 1078 | #define QUIRK_LVDS_SSC_DISABLE (1<<1) |
4dca20ef | 1079 | #define QUIRK_INVERT_BRIGHTNESS (1<<2) |
9c72cc6f | 1080 | #define QUIRK_BACKLIGHT_PRESENT (1<<3) |
b6b5d049 | 1081 | #define QUIRK_PIPEB_FORCE (1<<4) |
656bfa3a | 1082 | #define QUIRK_PIN_SWIZZLED_PAGES (1<<5) |
b690e96c | 1083 | |
8be48d92 | 1084 | struct intel_fbdev; |
1630fe75 | 1085 | struct intel_fbc_work; |
38651674 | 1086 | |
c2b9152f DV |
1087 | struct intel_gmbus { |
1088 | struct i2c_adapter adapter; | |
3e4d44e0 | 1089 | #define GMBUS_FORCE_BIT_RETRY (1U << 31) |
f2ce9faf | 1090 | u32 force_bit; |
c2b9152f | 1091 | u32 reg0; |
f0f59a00 | 1092 | i915_reg_t gpio_reg; |
c167a6fc | 1093 | struct i2c_algo_bit_data bit_algo; |
c2b9152f DV |
1094 | struct drm_i915_private *dev_priv; |
1095 | }; | |
1096 | ||
f4c956ad | 1097 | struct i915_suspend_saved_registers { |
e948e994 | 1098 | u32 saveDSPARB; |
ba8bbcf6 | 1099 | u32 saveFBC_CONTROL; |
1f84e550 | 1100 | u32 saveCACHE_MODE_0; |
1f84e550 | 1101 | u32 saveMI_ARB_STATE; |
ba8bbcf6 JB |
1102 | u32 saveSWF0[16]; |
1103 | u32 saveSWF1[16]; | |
85fa792b | 1104 | u32 saveSWF3[3]; |
4b9de737 | 1105 | uint64_t saveFENCE[I915_MAX_NUM_FENCES]; |
cda2bb78 | 1106 | u32 savePCH_PORT_HOTPLUG; |
9f49c376 | 1107 | u16 saveGCDGMBUS; |
f4c956ad | 1108 | }; |
c85aa885 | 1109 | |
ddeea5b0 ID |
1110 | struct vlv_s0ix_state { |
1111 | /* GAM */ | |
1112 | u32 wr_watermark; | |
1113 | u32 gfx_prio_ctrl; | |
1114 | u32 arb_mode; | |
1115 | u32 gfx_pend_tlb0; | |
1116 | u32 gfx_pend_tlb1; | |
1117 | u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM]; | |
1118 | u32 media_max_req_count; | |
1119 | u32 gfx_max_req_count; | |
1120 | u32 render_hwsp; | |
1121 | u32 ecochk; | |
1122 | u32 bsd_hwsp; | |
1123 | u32 blt_hwsp; | |
1124 | u32 tlb_rd_addr; | |
1125 | ||
1126 | /* MBC */ | |
1127 | u32 g3dctl; | |
1128 | u32 gsckgctl; | |
1129 | u32 mbctl; | |
1130 | ||
1131 | /* GCP */ | |
1132 | u32 ucgctl1; | |
1133 | u32 ucgctl3; | |
1134 | u32 rcgctl1; | |
1135 | u32 rcgctl2; | |
1136 | u32 rstctl; | |
1137 | u32 misccpctl; | |
1138 | ||
1139 | /* GPM */ | |
1140 | u32 gfxpause; | |
1141 | u32 rpdeuhwtc; | |
1142 | u32 rpdeuc; | |
1143 | u32 ecobus; | |
1144 | u32 pwrdwnupctl; | |
1145 | u32 rp_down_timeout; | |
1146 | u32 rp_deucsw; | |
1147 | u32 rcubmabdtmr; | |
1148 | u32 rcedata; | |
1149 | u32 spare2gh; | |
1150 | ||
1151 | /* Display 1 CZ domain */ | |
1152 | u32 gt_imr; | |
1153 | u32 gt_ier; | |
1154 | u32 pm_imr; | |
1155 | u32 pm_ier; | |
1156 | u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM]; | |
1157 | ||
1158 | /* GT SA CZ domain */ | |
1159 | u32 tilectl; | |
1160 | u32 gt_fifoctl; | |
1161 | u32 gtlc_wake_ctrl; | |
1162 | u32 gtlc_survive; | |
1163 | u32 pmwgicz; | |
1164 | ||
1165 | /* Display 2 CZ domain */ | |
1166 | u32 gu_ctl0; | |
1167 | u32 gu_ctl1; | |
9c25210f | 1168 | u32 pcbr; |
ddeea5b0 ID |
1169 | u32 clock_gate_dis2; |
1170 | }; | |
1171 | ||
bf225f20 CW |
1172 | struct intel_rps_ei { |
1173 | u32 cz_clock; | |
1174 | u32 render_c0; | |
1175 | u32 media_c0; | |
31685c25 D |
1176 | }; |
1177 | ||
c85aa885 | 1178 | struct intel_gen6_power_mgmt { |
d4d70aa5 ID |
1179 | /* |
1180 | * work, interrupts_enabled and pm_iir are protected by | |
1181 | * dev_priv->irq_lock | |
1182 | */ | |
c85aa885 | 1183 | struct work_struct work; |
d4d70aa5 | 1184 | bool interrupts_enabled; |
c85aa885 | 1185 | u32 pm_iir; |
59cdb63d | 1186 | |
1800ad25 SAK |
1187 | u32 pm_intr_keep; |
1188 | ||
b39fb297 BW |
1189 | /* Frequencies are stored in potentially platform dependent multiples. |
1190 | * In other words, *_freq needs to be multiplied by X to be interesting. | |
1191 | * Soft limits are those which are used for the dynamic reclocking done | |
1192 | * by the driver (raise frequencies under heavy loads, and lower for | |
1193 | * lighter loads). Hard limits are those imposed by the hardware. | |
1194 | * | |
1195 | * A distinction is made for overclocking, which is never enabled by | |
1196 | * default, and is considered to be above the hard limit if it's | |
1197 | * possible at all. | |
1198 | */ | |
1199 | u8 cur_freq; /* Current frequency (cached, may not == HW) */ | |
1200 | u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */ | |
1201 | u8 max_freq_softlimit; /* Max frequency permitted by the driver */ | |
1202 | u8 max_freq; /* Maximum frequency, RP0 if not overclocking */ | |
1203 | u8 min_freq; /* AKA RPn. Minimum frequency */ | |
29ecd78d | 1204 | u8 boost_freq; /* Frequency to request when wait boosting */ |
aed242ff | 1205 | u8 idle_freq; /* Frequency to request when we are idle */ |
b39fb297 BW |
1206 | u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */ |
1207 | u8 rp1_freq; /* "less than" RP0 power/freqency */ | |
1208 | u8 rp0_freq; /* Non-overclocked max frequency. */ | |
c30fec65 | 1209 | u16 gpll_ref_freq; /* vlv/chv GPLL reference frequency */ |
1a01ab3b | 1210 | |
8fb55197 CW |
1211 | u8 up_threshold; /* Current %busy required to uplock */ |
1212 | u8 down_threshold; /* Current %busy required to downclock */ | |
1213 | ||
dd75fdc8 CW |
1214 | int last_adj; |
1215 | enum { LOW_POWER, BETWEEN, HIGH_POWER } power; | |
1216 | ||
8d3afd7d CW |
1217 | spinlock_t client_lock; |
1218 | struct list_head clients; | |
1219 | bool client_boost; | |
1220 | ||
c0951f0c | 1221 | bool enabled; |
54b4f68f | 1222 | struct delayed_work autoenable_work; |
1854d5ca | 1223 | unsigned boosts; |
4fc688ce | 1224 | |
bf225f20 CW |
1225 | /* manual wa residency calculations */ |
1226 | struct intel_rps_ei up_ei, down_ei; | |
1227 | ||
4fc688ce JB |
1228 | /* |
1229 | * Protects RPS/RC6 register access and PCU communication. | |
8d3afd7d CW |
1230 | * Must be taken after struct_mutex if nested. Note that |
1231 | * this lock may be held for long periods of time when | |
1232 | * talking to hw - so only take it when talking to hw! | |
4fc688ce JB |
1233 | */ |
1234 | struct mutex hw_lock; | |
c85aa885 DV |
1235 | }; |
1236 | ||
1a240d4d DV |
1237 | /* defined intel_pm.c */ |
1238 | extern spinlock_t mchdev_lock; | |
1239 | ||
c85aa885 DV |
1240 | struct intel_ilk_power_mgmt { |
1241 | u8 cur_delay; | |
1242 | u8 min_delay; | |
1243 | u8 max_delay; | |
1244 | u8 fmax; | |
1245 | u8 fstart; | |
1246 | ||
1247 | u64 last_count1; | |
1248 | unsigned long last_time1; | |
1249 | unsigned long chipset_power; | |
1250 | u64 last_count2; | |
5ed0bdf2 | 1251 | u64 last_time2; |
c85aa885 DV |
1252 | unsigned long gfx_power; |
1253 | u8 corr; | |
1254 | ||
1255 | int c_m; | |
1256 | int r_t; | |
1257 | }; | |
1258 | ||
c6cb582e ID |
1259 | struct drm_i915_private; |
1260 | struct i915_power_well; | |
1261 | ||
1262 | struct i915_power_well_ops { | |
1263 | /* | |
1264 | * Synchronize the well's hw state to match the current sw state, for | |
1265 | * example enable/disable it based on the current refcount. Called | |
1266 | * during driver init and resume time, possibly after first calling | |
1267 | * the enable/disable handlers. | |
1268 | */ | |
1269 | void (*sync_hw)(struct drm_i915_private *dev_priv, | |
1270 | struct i915_power_well *power_well); | |
1271 | /* | |
1272 | * Enable the well and resources that depend on it (for example | |
1273 | * interrupts located on the well). Called after the 0->1 refcount | |
1274 | * transition. | |
1275 | */ | |
1276 | void (*enable)(struct drm_i915_private *dev_priv, | |
1277 | struct i915_power_well *power_well); | |
1278 | /* | |
1279 | * Disable the well and resources that depend on it. Called after | |
1280 | * the 1->0 refcount transition. | |
1281 | */ | |
1282 | void (*disable)(struct drm_i915_private *dev_priv, | |
1283 | struct i915_power_well *power_well); | |
1284 | /* Returns the hw enabled state. */ | |
1285 | bool (*is_enabled)(struct drm_i915_private *dev_priv, | |
1286 | struct i915_power_well *power_well); | |
1287 | }; | |
1288 | ||
a38911a3 WX |
1289 | /* Power well structure for haswell */ |
1290 | struct i915_power_well { | |
c1ca727f | 1291 | const char *name; |
6f3ef5dd | 1292 | bool always_on; |
a38911a3 WX |
1293 | /* power well enable/disable usage count */ |
1294 | int count; | |
bfafe93a ID |
1295 | /* cached hw enabled state */ |
1296 | bool hw_enabled; | |
c1ca727f | 1297 | unsigned long domains; |
77961eb9 | 1298 | unsigned long data; |
c6cb582e | 1299 | const struct i915_power_well_ops *ops; |
a38911a3 WX |
1300 | }; |
1301 | ||
83c00f55 | 1302 | struct i915_power_domains { |
baa70707 ID |
1303 | /* |
1304 | * Power wells needed for initialization at driver init and suspend | |
1305 | * time are on. They are kept on until after the first modeset. | |
1306 | */ | |
1307 | bool init_power_on; | |
0d116a29 | 1308 | bool initializing; |
c1ca727f | 1309 | int power_well_count; |
baa70707 | 1310 | |
83c00f55 | 1311 | struct mutex lock; |
1da51581 | 1312 | int domain_use_count[POWER_DOMAIN_NUM]; |
c1ca727f | 1313 | struct i915_power_well *power_wells; |
83c00f55 ID |
1314 | }; |
1315 | ||
35a85ac6 | 1316 | #define MAX_L3_SLICES 2 |
a4da4fa4 | 1317 | struct intel_l3_parity { |
35a85ac6 | 1318 | u32 *remap_info[MAX_L3_SLICES]; |
a4da4fa4 | 1319 | struct work_struct error_work; |
35a85ac6 | 1320 | int which_slice; |
a4da4fa4 DV |
1321 | }; |
1322 | ||
4b5aed62 | 1323 | struct i915_gem_mm { |
4b5aed62 DV |
1324 | /** Memory allocator for GTT stolen memory */ |
1325 | struct drm_mm stolen; | |
92e97d2f PZ |
1326 | /** Protects the usage of the GTT stolen memory allocator. This is |
1327 | * always the inner lock when overlapping with struct_mutex. */ | |
1328 | struct mutex stolen_lock; | |
1329 | ||
4b5aed62 DV |
1330 | /** List of all objects in gtt_space. Used to restore gtt |
1331 | * mappings on resume */ | |
1332 | struct list_head bound_list; | |
1333 | /** | |
1334 | * List of objects which are not bound to the GTT (thus | |
1335 | * are idle and not used by the GPU) but still have | |
1336 | * (presumably uncached) pages still attached. | |
1337 | */ | |
1338 | struct list_head unbound_list; | |
1339 | ||
1340 | /** Usable portion of the GTT for GEM */ | |
1341 | unsigned long stolen_base; /* limited to low memory (32-bit) */ | |
1342 | ||
4b5aed62 DV |
1343 | /** PPGTT used for aliasing the PPGTT with the GTT */ |
1344 | struct i915_hw_ppgtt *aliasing_ppgtt; | |
1345 | ||
2cfcd32a | 1346 | struct notifier_block oom_notifier; |
e87666b5 | 1347 | struct notifier_block vmap_notifier; |
ceabbba5 | 1348 | struct shrinker shrinker; |
4b5aed62 | 1349 | |
4b5aed62 DV |
1350 | /** LRU list of objects with fence regs on them. */ |
1351 | struct list_head fence_list; | |
1352 | ||
4b5aed62 DV |
1353 | /** |
1354 | * Are we in a non-interruptible section of code like | |
1355 | * modesetting? | |
1356 | */ | |
1357 | bool interruptible; | |
1358 | ||
bdf1e7e3 | 1359 | /* the indicator for dispatch video commands on two BSD rings */ |
6f633402 | 1360 | atomic_t bsd_engine_dispatch_index; |
bdf1e7e3 | 1361 | |
4b5aed62 DV |
1362 | /** Bit 6 swizzling required for X tiling */ |
1363 | uint32_t bit_6_swizzle_x; | |
1364 | /** Bit 6 swizzling required for Y tiling */ | |
1365 | uint32_t bit_6_swizzle_y; | |
1366 | ||
4b5aed62 | 1367 | /* accounting, useful for userland debugging */ |
c20e8355 | 1368 | spinlock_t object_stat_lock; |
4b5aed62 DV |
1369 | size_t object_memory; |
1370 | u32 object_count; | |
1371 | }; | |
1372 | ||
edc3d884 | 1373 | struct drm_i915_error_state_buf { |
0a4cd7c8 | 1374 | struct drm_i915_private *i915; |
edc3d884 MK |
1375 | unsigned bytes; |
1376 | unsigned size; | |
1377 | int err; | |
1378 | u8 *buf; | |
1379 | loff_t start; | |
1380 | loff_t pos; | |
1381 | }; | |
1382 | ||
fc16b48b MK |
1383 | struct i915_error_state_file_priv { |
1384 | struct drm_device *dev; | |
1385 | struct drm_i915_error_state *error; | |
1386 | }; | |
1387 | ||
99584db3 DV |
1388 | struct i915_gpu_error { |
1389 | /* For hangcheck timer */ | |
1390 | #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */ | |
1391 | #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD) | |
be62acb4 MK |
1392 | /* Hang gpu twice in this window and your context gets banned */ |
1393 | #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000) | |
1394 | ||
737b1506 | 1395 | struct delayed_work hangcheck_work; |
99584db3 DV |
1396 | |
1397 | /* For reset and error_state handling. */ | |
1398 | spinlock_t lock; | |
1399 | /* Protected by the above dev->gpu_error.lock. */ | |
1400 | struct drm_i915_error_state *first_error; | |
094f9a54 CW |
1401 | |
1402 | unsigned long missed_irq_rings; | |
1403 | ||
1f83fee0 | 1404 | /** |
2ac0f450 | 1405 | * State variable controlling the reset flow and count |
1f83fee0 | 1406 | * |
2ac0f450 | 1407 | * This is a counter which gets incremented when reset is triggered, |
8af29b0c CW |
1408 | * |
1409 | * Before the reset commences, the I915_RESET_IN_PROGRESS bit is set | |
1410 | * meaning that any waiters holding onto the struct_mutex should | |
1411 | * relinquish the lock immediately in order for the reset to start. | |
2ac0f450 MK |
1412 | * |
1413 | * If reset is not completed succesfully, the I915_WEDGE bit is | |
1414 | * set meaning that hardware is terminally sour and there is no | |
1415 | * recovery. All waiters on the reset_queue will be woken when | |
1416 | * that happens. | |
1417 | * | |
1418 | * This counter is used by the wait_seqno code to notice that reset | |
1419 | * event happened and it needs to restart the entire ioctl (since most | |
1420 | * likely the seqno it waited for won't ever signal anytime soon). | |
f69061be DV |
1421 | * |
1422 | * This is important for lock-free wait paths, where no contended lock | |
1423 | * naturally enforces the correct ordering between the bail-out of the | |
1424 | * waiter and the gpu reset work code. | |
1f83fee0 | 1425 | */ |
8af29b0c | 1426 | unsigned long reset_count; |
1f83fee0 | 1427 | |
8af29b0c CW |
1428 | unsigned long flags; |
1429 | #define I915_RESET_IN_PROGRESS 0 | |
1430 | #define I915_WEDGED (BITS_PER_LONG - 1) | |
1f83fee0 | 1431 | |
1f15b76f CW |
1432 | /** |
1433 | * Waitqueue to signal when a hang is detected. Used to for waiters | |
1434 | * to release the struct_mutex for the reset to procede. | |
1435 | */ | |
1436 | wait_queue_head_t wait_queue; | |
1437 | ||
1f83fee0 DV |
1438 | /** |
1439 | * Waitqueue to signal when the reset has completed. Used by clients | |
1440 | * that wait for dev_priv->mm.wedged to settle. | |
1441 | */ | |
1442 | wait_queue_head_t reset_queue; | |
33196ded | 1443 | |
094f9a54 | 1444 | /* For missed irq/seqno simulation. */ |
688e6c72 | 1445 | unsigned long test_irq_rings; |
99584db3 DV |
1446 | }; |
1447 | ||
b8efb17b ZR |
1448 | enum modeset_restore { |
1449 | MODESET_ON_LID_OPEN, | |
1450 | MODESET_DONE, | |
1451 | MODESET_SUSPENDED, | |
1452 | }; | |
1453 | ||
500ea70d RV |
1454 | #define DP_AUX_A 0x40 |
1455 | #define DP_AUX_B 0x10 | |
1456 | #define DP_AUX_C 0x20 | |
1457 | #define DP_AUX_D 0x30 | |
1458 | ||
11c1b657 XZ |
1459 | #define DDC_PIN_B 0x05 |
1460 | #define DDC_PIN_C 0x04 | |
1461 | #define DDC_PIN_D 0x06 | |
1462 | ||
6acab15a | 1463 | struct ddi_vbt_port_info { |
ce4dd49e DL |
1464 | /* |
1465 | * This is an index in the HDMI/DVI DDI buffer translation table. | |
1466 | * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't | |
1467 | * populate this field. | |
1468 | */ | |
1469 | #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff | |
6acab15a | 1470 | uint8_t hdmi_level_shift; |
311a2094 PZ |
1471 | |
1472 | uint8_t supports_dvi:1; | |
1473 | uint8_t supports_hdmi:1; | |
1474 | uint8_t supports_dp:1; | |
500ea70d RV |
1475 | |
1476 | uint8_t alternate_aux_channel; | |
11c1b657 | 1477 | uint8_t alternate_ddc_pin; |
75067dde AK |
1478 | |
1479 | uint8_t dp_boost_level; | |
1480 | uint8_t hdmi_boost_level; | |
6acab15a PZ |
1481 | }; |
1482 | ||
bfd7ebda RV |
1483 | enum psr_lines_to_wait { |
1484 | PSR_0_LINES_TO_WAIT = 0, | |
1485 | PSR_1_LINE_TO_WAIT, | |
1486 | PSR_4_LINES_TO_WAIT, | |
1487 | PSR_8_LINES_TO_WAIT | |
83a7280e PB |
1488 | }; |
1489 | ||
41aa3448 RV |
1490 | struct intel_vbt_data { |
1491 | struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ | |
1492 | struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ | |
1493 | ||
1494 | /* Feature bits */ | |
1495 | unsigned int int_tv_support:1; | |
1496 | unsigned int lvds_dither:1; | |
1497 | unsigned int lvds_vbt:1; | |
1498 | unsigned int int_crt_support:1; | |
1499 | unsigned int lvds_use_ssc:1; | |
1500 | unsigned int display_clock_mode:1; | |
1501 | unsigned int fdi_rx_polarity_inverted:1; | |
3e845c7a | 1502 | unsigned int panel_type:4; |
41aa3448 RV |
1503 | int lvds_ssc_freq; |
1504 | unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */ | |
1505 | ||
83a7280e PB |
1506 | enum drrs_support_type drrs_type; |
1507 | ||
6aa23e65 JN |
1508 | struct { |
1509 | int rate; | |
1510 | int lanes; | |
1511 | int preemphasis; | |
1512 | int vswing; | |
06411f08 | 1513 | bool low_vswing; |
6aa23e65 JN |
1514 | bool initialized; |
1515 | bool support; | |
1516 | int bpp; | |
1517 | struct edp_power_seq pps; | |
1518 | } edp; | |
41aa3448 | 1519 | |
bfd7ebda RV |
1520 | struct { |
1521 | bool full_link; | |
1522 | bool require_aux_wakeup; | |
1523 | int idle_frames; | |
1524 | enum psr_lines_to_wait lines_to_wait; | |
1525 | int tp1_wakeup_time; | |
1526 | int tp2_tp3_wakeup_time; | |
1527 | } psr; | |
1528 | ||
f00076d2 JN |
1529 | struct { |
1530 | u16 pwm_freq_hz; | |
39fbc9c8 | 1531 | bool present; |
f00076d2 | 1532 | bool active_low_pwm; |
1de6068e | 1533 | u8 min_brightness; /* min_brightness/255 of max */ |
9a41e17d | 1534 | enum intel_backlight_type type; |
f00076d2 JN |
1535 | } backlight; |
1536 | ||
d17c5443 SK |
1537 | /* MIPI DSI */ |
1538 | struct { | |
1539 | u16 panel_id; | |
d3b542fc SK |
1540 | struct mipi_config *config; |
1541 | struct mipi_pps_data *pps; | |
1542 | u8 seq_version; | |
1543 | u32 size; | |
1544 | u8 *data; | |
8d3ed2f3 | 1545 | const u8 *sequence[MIPI_SEQ_MAX]; |
d17c5443 SK |
1546 | } dsi; |
1547 | ||
41aa3448 RV |
1548 | int crt_ddc_pin; |
1549 | ||
1550 | int child_dev_num; | |
768f69c9 | 1551 | union child_device_config *child_dev; |
6acab15a PZ |
1552 | |
1553 | struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS]; | |
9d6c875d | 1554 | struct sdvo_device_mapping sdvo_mappings[2]; |
41aa3448 RV |
1555 | }; |
1556 | ||
77c122bc VS |
1557 | enum intel_ddb_partitioning { |
1558 | INTEL_DDB_PART_1_2, | |
1559 | INTEL_DDB_PART_5_6, /* IVB+ */ | |
1560 | }; | |
1561 | ||
1fd527cc VS |
1562 | struct intel_wm_level { |
1563 | bool enable; | |
1564 | uint32_t pri_val; | |
1565 | uint32_t spr_val; | |
1566 | uint32_t cur_val; | |
1567 | uint32_t fbc_val; | |
1568 | }; | |
1569 | ||
820c1980 | 1570 | struct ilk_wm_values { |
609cedef VS |
1571 | uint32_t wm_pipe[3]; |
1572 | uint32_t wm_lp[3]; | |
1573 | uint32_t wm_lp_spr[3]; | |
1574 | uint32_t wm_linetime[3]; | |
1575 | bool enable_fbc_wm; | |
1576 | enum intel_ddb_partitioning partitioning; | |
1577 | }; | |
1578 | ||
262cd2e1 VS |
1579 | struct vlv_pipe_wm { |
1580 | uint16_t primary; | |
1581 | uint16_t sprite[2]; | |
1582 | uint8_t cursor; | |
1583 | }; | |
ae80152d | 1584 | |
262cd2e1 VS |
1585 | struct vlv_sr_wm { |
1586 | uint16_t plane; | |
1587 | uint8_t cursor; | |
1588 | }; | |
ae80152d | 1589 | |
262cd2e1 VS |
1590 | struct vlv_wm_values { |
1591 | struct vlv_pipe_wm pipe[3]; | |
1592 | struct vlv_sr_wm sr; | |
0018fda1 VS |
1593 | struct { |
1594 | uint8_t cursor; | |
1595 | uint8_t sprite[2]; | |
1596 | uint8_t primary; | |
1597 | } ddl[3]; | |
6eb1a681 VS |
1598 | uint8_t level; |
1599 | bool cxsr; | |
0018fda1 VS |
1600 | }; |
1601 | ||
c193924e | 1602 | struct skl_ddb_entry { |
16160e3d | 1603 | uint16_t start, end; /* in number of blocks, 'end' is exclusive */ |
c193924e DL |
1604 | }; |
1605 | ||
1606 | static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry) | |
1607 | { | |
16160e3d | 1608 | return entry->end - entry->start; |
c193924e DL |
1609 | } |
1610 | ||
08db6652 DL |
1611 | static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1, |
1612 | const struct skl_ddb_entry *e2) | |
1613 | { | |
1614 | if (e1->start == e2->start && e1->end == e2->end) | |
1615 | return true; | |
1616 | ||
1617 | return false; | |
1618 | } | |
1619 | ||
c193924e | 1620 | struct skl_ddb_allocation { |
34bb56af | 1621 | struct skl_ddb_entry pipe[I915_MAX_PIPES]; |
2cd601c6 | 1622 | struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */ |
4969d33e | 1623 | struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES]; |
c193924e DL |
1624 | }; |
1625 | ||
2ac96d2a | 1626 | struct skl_wm_values { |
2b4b9f35 | 1627 | unsigned dirty_pipes; |
c193924e | 1628 | struct skl_ddb_allocation ddb; |
2ac96d2a PB |
1629 | uint32_t wm_linetime[I915_MAX_PIPES]; |
1630 | uint32_t plane[I915_MAX_PIPES][I915_MAX_PLANES][8]; | |
2ac96d2a | 1631 | uint32_t plane_trans[I915_MAX_PIPES][I915_MAX_PLANES]; |
2ac96d2a PB |
1632 | }; |
1633 | ||
1634 | struct skl_wm_level { | |
1635 | bool plane_en[I915_MAX_PLANES]; | |
1636 | uint16_t plane_res_b[I915_MAX_PLANES]; | |
1637 | uint8_t plane_res_l[I915_MAX_PLANES]; | |
2ac96d2a PB |
1638 | }; |
1639 | ||
c67a470b | 1640 | /* |
765dab67 PZ |
1641 | * This struct helps tracking the state needed for runtime PM, which puts the |
1642 | * device in PCI D3 state. Notice that when this happens, nothing on the | |
1643 | * graphics device works, even register access, so we don't get interrupts nor | |
1644 | * anything else. | |
c67a470b | 1645 | * |
765dab67 PZ |
1646 | * Every piece of our code that needs to actually touch the hardware needs to |
1647 | * either call intel_runtime_pm_get or call intel_display_power_get with the | |
1648 | * appropriate power domain. | |
a8a8bd54 | 1649 | * |
765dab67 PZ |
1650 | * Our driver uses the autosuspend delay feature, which means we'll only really |
1651 | * suspend if we stay with zero refcount for a certain amount of time. The | |
f458ebbc | 1652 | * default value is currently very conservative (see intel_runtime_pm_enable), but |
765dab67 | 1653 | * it can be changed with the standard runtime PM files from sysfs. |
c67a470b PZ |
1654 | * |
1655 | * The irqs_disabled variable becomes true exactly after we disable the IRQs and | |
1656 | * goes back to false exactly before we reenable the IRQs. We use this variable | |
1657 | * to check if someone is trying to enable/disable IRQs while they're supposed | |
1658 | * to be disabled. This shouldn't happen and we'll print some error messages in | |
730488b2 | 1659 | * case it happens. |
c67a470b | 1660 | * |
765dab67 | 1661 | * For more, read the Documentation/power/runtime_pm.txt. |
c67a470b | 1662 | */ |
5d584b2e | 1663 | struct i915_runtime_pm { |
1f814dac | 1664 | atomic_t wakeref_count; |
2b19efeb | 1665 | atomic_t atomic_seq; |
5d584b2e | 1666 | bool suspended; |
2aeb7d3a | 1667 | bool irqs_enabled; |
c67a470b PZ |
1668 | }; |
1669 | ||
926321d5 DV |
1670 | enum intel_pipe_crc_source { |
1671 | INTEL_PIPE_CRC_SOURCE_NONE, | |
1672 | INTEL_PIPE_CRC_SOURCE_PLANE1, | |
1673 | INTEL_PIPE_CRC_SOURCE_PLANE2, | |
1674 | INTEL_PIPE_CRC_SOURCE_PF, | |
5b3a856b | 1675 | INTEL_PIPE_CRC_SOURCE_PIPE, |
3d099a05 DV |
1676 | /* TV/DP on pre-gen5/vlv can't use the pipe source. */ |
1677 | INTEL_PIPE_CRC_SOURCE_TV, | |
1678 | INTEL_PIPE_CRC_SOURCE_DP_B, | |
1679 | INTEL_PIPE_CRC_SOURCE_DP_C, | |
1680 | INTEL_PIPE_CRC_SOURCE_DP_D, | |
46a19188 | 1681 | INTEL_PIPE_CRC_SOURCE_AUTO, |
926321d5 DV |
1682 | INTEL_PIPE_CRC_SOURCE_MAX, |
1683 | }; | |
1684 | ||
8bf1e9f1 | 1685 | struct intel_pipe_crc_entry { |
ac2300d4 | 1686 | uint32_t frame; |
8bf1e9f1 SH |
1687 | uint32_t crc[5]; |
1688 | }; | |
1689 | ||
b2c88f5b | 1690 | #define INTEL_PIPE_CRC_ENTRIES_NR 128 |
8bf1e9f1 | 1691 | struct intel_pipe_crc { |
d538bbdf DL |
1692 | spinlock_t lock; |
1693 | bool opened; /* exclusive access to the result file */ | |
e5f75aca | 1694 | struct intel_pipe_crc_entry *entries; |
926321d5 | 1695 | enum intel_pipe_crc_source source; |
d538bbdf | 1696 | int head, tail; |
07144428 | 1697 | wait_queue_head_t wq; |
8bf1e9f1 SH |
1698 | }; |
1699 | ||
f99d7069 | 1700 | struct i915_frontbuffer_tracking { |
b5add959 | 1701 | spinlock_t lock; |
f99d7069 DV |
1702 | |
1703 | /* | |
1704 | * Tracking bits for delayed frontbuffer flushing du to gpu activity or | |
1705 | * scheduled flips. | |
1706 | */ | |
1707 | unsigned busy_bits; | |
1708 | unsigned flip_bits; | |
1709 | }; | |
1710 | ||
7225342a | 1711 | struct i915_wa_reg { |
f0f59a00 | 1712 | i915_reg_t addr; |
7225342a MK |
1713 | u32 value; |
1714 | /* bitmask representing WA bits */ | |
1715 | u32 mask; | |
1716 | }; | |
1717 | ||
33136b06 AS |
1718 | /* |
1719 | * RING_MAX_NONPRIV_SLOTS is per-engine but at this point we are only | |
1720 | * allowing it for RCS as we don't foresee any requirement of having | |
1721 | * a whitelist for other engines. When it is really required for | |
1722 | * other engines then the limit need to be increased. | |
1723 | */ | |
1724 | #define I915_MAX_WA_REGS (16 + RING_MAX_NONPRIV_SLOTS) | |
7225342a MK |
1725 | |
1726 | struct i915_workarounds { | |
1727 | struct i915_wa_reg reg[I915_MAX_WA_REGS]; | |
1728 | u32 count; | |
666796da | 1729 | u32 hw_whitelist_count[I915_NUM_ENGINES]; |
7225342a MK |
1730 | }; |
1731 | ||
cf9d2890 YZ |
1732 | struct i915_virtual_gpu { |
1733 | bool active; | |
1734 | }; | |
1735 | ||
aa363136 MR |
1736 | /* used in computing the new watermarks state */ |
1737 | struct intel_wm_config { | |
1738 | unsigned int num_pipes_active; | |
1739 | bool sprites_enabled; | |
1740 | bool sprites_scaled; | |
1741 | }; | |
1742 | ||
77fec556 | 1743 | struct drm_i915_private { |
8f460e2c CW |
1744 | struct drm_device drm; |
1745 | ||
efab6d8d | 1746 | struct kmem_cache *objects; |
e20d2ab7 | 1747 | struct kmem_cache *vmas; |
efab6d8d | 1748 | struct kmem_cache *requests; |
f4c956ad | 1749 | |
5c969aa7 | 1750 | const struct intel_device_info info; |
f4c956ad DV |
1751 | |
1752 | int relative_constants_mode; | |
1753 | ||
1754 | void __iomem *regs; | |
1755 | ||
907b28c5 | 1756 | struct intel_uncore uncore; |
f4c956ad | 1757 | |
cf9d2890 YZ |
1758 | struct i915_virtual_gpu vgpu; |
1759 | ||
0ad35fed ZW |
1760 | struct intel_gvt gvt; |
1761 | ||
33a732f4 AD |
1762 | struct intel_guc guc; |
1763 | ||
eb805623 DV |
1764 | struct intel_csr csr; |
1765 | ||
5ea6e5e3 | 1766 | struct intel_gmbus gmbus[GMBUS_NUM_PINS]; |
28c70f16 | 1767 | |
f4c956ad DV |
1768 | /** gmbus_mutex protects against concurrent usage of the single hw gmbus |
1769 | * controller on different i2c buses. */ | |
1770 | struct mutex gmbus_mutex; | |
1771 | ||
1772 | /** | |
1773 | * Base address of the gmbus and gpio block. | |
1774 | */ | |
1775 | uint32_t gpio_mmio_base; | |
1776 | ||
b6fdd0f2 SS |
1777 | /* MMIO base address for MIPI regs */ |
1778 | uint32_t mipi_mmio_base; | |
1779 | ||
443a389f VS |
1780 | uint32_t psr_mmio_base; |
1781 | ||
44cb734c ID |
1782 | uint32_t pps_mmio_base; |
1783 | ||
28c70f16 DV |
1784 | wait_queue_head_t gmbus_wait_queue; |
1785 | ||
f4c956ad | 1786 | struct pci_dev *bridge_dev; |
0ca5fa3a | 1787 | struct i915_gem_context *kernel_context; |
666796da | 1788 | struct intel_engine_cs engine[I915_NUM_ENGINES]; |
51d545d0 | 1789 | struct i915_vma *semaphore; |
ddf07be7 | 1790 | u32 next_seqno; |
f4c956ad | 1791 | |
ba8286fa | 1792 | struct drm_dma_handle *status_page_dmah; |
f4c956ad DV |
1793 | struct resource mch_res; |
1794 | ||
f4c956ad DV |
1795 | /* protects the irq masks */ |
1796 | spinlock_t irq_lock; | |
1797 | ||
84c33a64 SG |
1798 | /* protects the mmio flip data */ |
1799 | spinlock_t mmio_flip_lock; | |
1800 | ||
f8b79e58 ID |
1801 | bool display_irqs_enabled; |
1802 | ||
9ee32fea DV |
1803 | /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */ |
1804 | struct pm_qos_request pm_qos; | |
1805 | ||
a580516d VS |
1806 | /* Sideband mailbox protection */ |
1807 | struct mutex sb_lock; | |
f4c956ad DV |
1808 | |
1809 | /** Cached value of IMR to avoid reads in updating the bitfield */ | |
abd58f01 BW |
1810 | union { |
1811 | u32 irq_mask; | |
1812 | u32 de_irq_mask[I915_MAX_PIPES]; | |
1813 | }; | |
f4c956ad | 1814 | u32 gt_irq_mask; |
605cd25b | 1815 | u32 pm_irq_mask; |
a6706b45 | 1816 | u32 pm_rps_events; |
91d181dd | 1817 | u32 pipestat_irq_mask[I915_MAX_PIPES]; |
f4c956ad | 1818 | |
5fcece80 | 1819 | struct i915_hotplug hotplug; |
ab34a7e8 | 1820 | struct intel_fbc fbc; |
439d7ac0 | 1821 | struct i915_drrs drrs; |
f4c956ad | 1822 | struct intel_opregion opregion; |
41aa3448 | 1823 | struct intel_vbt_data vbt; |
f4c956ad | 1824 | |
d9ceb816 JB |
1825 | bool preserve_bios_swizzle; |
1826 | ||
f4c956ad DV |
1827 | /* overlay */ |
1828 | struct intel_overlay *overlay; | |
f4c956ad | 1829 | |
58c68779 | 1830 | /* backlight registers and fields in struct intel_panel */ |
07f11d49 | 1831 | struct mutex backlight_lock; |
31ad8ec6 | 1832 | |
f4c956ad | 1833 | /* LVDS info */ |
f4c956ad DV |
1834 | bool no_aux_handshake; |
1835 | ||
e39b999a VS |
1836 | /* protects panel power sequencer state */ |
1837 | struct mutex pps_mutex; | |
1838 | ||
f4c956ad | 1839 | struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */ |
f4c956ad DV |
1840 | int num_fence_regs; /* 8 on pre-965, 16 otherwise */ |
1841 | ||
1842 | unsigned int fsb_freq, mem_freq, is_ddr3; | |
b2045352 | 1843 | unsigned int skl_preferred_vco_freq; |
1a617b77 | 1844 | unsigned int cdclk_freq, max_cdclk_freq, atomic_cdclk_freq; |
adafdc6f | 1845 | unsigned int max_dotclk_freq; |
e7dc33f3 | 1846 | unsigned int rawclk_freq; |
6bcda4f0 | 1847 | unsigned int hpll_freq; |
bfa7df01 | 1848 | unsigned int czclk_freq; |
f4c956ad | 1849 | |
63911d72 | 1850 | struct { |
709e05c3 | 1851 | unsigned int vco, ref; |
63911d72 VS |
1852 | } cdclk_pll; |
1853 | ||
645416f5 DV |
1854 | /** |
1855 | * wq - Driver workqueue for GEM. | |
1856 | * | |
1857 | * NOTE: Work items scheduled here are not allowed to grab any modeset | |
1858 | * locks, for otherwise the flushing done in the pageflip code will | |
1859 | * result in deadlocks. | |
1860 | */ | |
f4c956ad DV |
1861 | struct workqueue_struct *wq; |
1862 | ||
1863 | /* Display functions */ | |
1864 | struct drm_i915_display_funcs display; | |
1865 | ||
1866 | /* PCH chipset type */ | |
1867 | enum intel_pch pch_type; | |
17a303ec | 1868 | unsigned short pch_id; |
f4c956ad DV |
1869 | |
1870 | unsigned long quirks; | |
1871 | ||
b8efb17b ZR |
1872 | enum modeset_restore modeset_restore; |
1873 | struct mutex modeset_restore_lock; | |
e2c8b870 | 1874 | struct drm_atomic_state *modeset_restore_state; |
73974893 | 1875 | struct drm_modeset_acquire_ctx reset_ctx; |
673a394b | 1876 | |
a7bbbd63 | 1877 | struct list_head vm_list; /* Global list of all address spaces */ |
62106b4f | 1878 | struct i915_ggtt ggtt; /* VM representing the global address space */ |
5d4545ae | 1879 | |
4b5aed62 | 1880 | struct i915_gem_mm mm; |
ad46cb53 CW |
1881 | DECLARE_HASHTABLE(mm_structs, 7); |
1882 | struct mutex mm_lock; | |
8781342d | 1883 | |
5d1808ec CW |
1884 | /* The hw wants to have a stable context identifier for the lifetime |
1885 | * of the context (for OA, PASID, faults, etc). This is limited | |
1886 | * in execlists to 21 bits. | |
1887 | */ | |
1888 | struct ida context_hw_ida; | |
1889 | #define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */ | |
1890 | ||
8781342d DV |
1891 | /* Kernel Modesetting */ |
1892 | ||
76c4ac04 DL |
1893 | struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES]; |
1894 | struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES]; | |
6b95a207 KH |
1895 | wait_queue_head_t pending_flip_queue; |
1896 | ||
c4597872 DV |
1897 | #ifdef CONFIG_DEBUG_FS |
1898 | struct intel_pipe_crc pipe_crc[I915_MAX_PIPES]; | |
1899 | #endif | |
1900 | ||
565602d7 | 1901 | /* dpll and cdclk state is protected by connection_mutex */ |
e72f9fbf DV |
1902 | int num_shared_dpll; |
1903 | struct intel_shared_dpll shared_dplls[I915_NUM_PLLS]; | |
f9476a6c | 1904 | const struct intel_dpll_mgr *dpll_mgr; |
565602d7 | 1905 | |
fbf6d879 ML |
1906 | /* |
1907 | * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll. | |
1908 | * Must be global rather than per dpll, because on some platforms | |
1909 | * plls share registers. | |
1910 | */ | |
1911 | struct mutex dpll_lock; | |
1912 | ||
565602d7 ML |
1913 | unsigned int active_crtcs; |
1914 | unsigned int min_pixclk[I915_MAX_PIPES]; | |
1915 | ||
e4607fcf | 1916 | int dpio_phy_iosf_port[I915_NUM_PHYS_VLV]; |
ee7b9f93 | 1917 | |
7225342a | 1918 | struct i915_workarounds workarounds; |
888b5995 | 1919 | |
f99d7069 DV |
1920 | struct i915_frontbuffer_tracking fb_tracking; |
1921 | ||
652c393a | 1922 | u16 orig_clock; |
f97108d1 | 1923 | |
c4804411 | 1924 | bool mchbar_need_disable; |
f97108d1 | 1925 | |
a4da4fa4 DV |
1926 | struct intel_l3_parity l3_parity; |
1927 | ||
59124506 | 1928 | /* Cannot be determined by PCIID. You must always read a register. */ |
3accaf7e | 1929 | u32 edram_cap; |
59124506 | 1930 | |
c6a828d3 | 1931 | /* gen6+ rps state */ |
c85aa885 | 1932 | struct intel_gen6_power_mgmt rps; |
c6a828d3 | 1933 | |
20e4d407 DV |
1934 | /* ilk-only ips/rps state. Everything in here is protected by the global |
1935 | * mchdev_lock in intel_pm.c */ | |
c85aa885 | 1936 | struct intel_ilk_power_mgmt ips; |
b5e50c3f | 1937 | |
83c00f55 | 1938 | struct i915_power_domains power_domains; |
a38911a3 | 1939 | |
a031d709 | 1940 | struct i915_psr psr; |
3f51e471 | 1941 | |
99584db3 | 1942 | struct i915_gpu_error gpu_error; |
ae681d96 | 1943 | |
c9cddffc JB |
1944 | struct drm_i915_gem_object *vlv_pctx; |
1945 | ||
0695726e | 1946 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
8be48d92 DA |
1947 | /* list of fbdev register on this device */ |
1948 | struct intel_fbdev *fbdev; | |
82e3b8c1 | 1949 | struct work_struct fbdev_suspend_work; |
4520f53a | 1950 | #endif |
e953fd7b CW |
1951 | |
1952 | struct drm_property *broadcast_rgb_property; | |
3f43c48d | 1953 | struct drm_property *force_audio_property; |
e3689190 | 1954 | |
58fddc28 | 1955 | /* hda/i915 audio component */ |
51e1d83c | 1956 | struct i915_audio_component *audio_component; |
58fddc28 | 1957 | bool audio_component_registered; |
4a21ef7d LY |
1958 | /** |
1959 | * av_mutex - mutex for audio/video sync | |
1960 | * | |
1961 | */ | |
1962 | struct mutex av_mutex; | |
58fddc28 | 1963 | |
254f965c | 1964 | uint32_t hw_context_size; |
a33afea5 | 1965 | struct list_head context_list; |
f4c956ad | 1966 | |
3e68320e | 1967 | u32 fdi_rx_config; |
68d18ad7 | 1968 | |
c231775c | 1969 | /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */ |
70722468 | 1970 | u32 chv_phy_control; |
c231775c VS |
1971 | /* |
1972 | * Shadows for CHV DPLL_MD regs to keep the state | |
1973 | * checker somewhat working in the presence hardware | |
1974 | * crappiness (can't read out DPLL_MD for pipes B & C). | |
1975 | */ | |
1976 | u32 chv_dpll_md[I915_MAX_PIPES]; | |
adc7f04b | 1977 | u32 bxt_phy_grc; |
70722468 | 1978 | |
842f1c8b | 1979 | u32 suspend_count; |
bc87229f | 1980 | bool suspended_to_idle; |
f4c956ad | 1981 | struct i915_suspend_saved_registers regfile; |
ddeea5b0 | 1982 | struct vlv_s0ix_state vlv_s0ix_state; |
231f42a4 | 1983 | |
656d1b89 L |
1984 | enum { |
1985 | I915_SKL_SAGV_UNKNOWN = 0, | |
1986 | I915_SKL_SAGV_DISABLED, | |
1987 | I915_SKL_SAGV_ENABLED, | |
1988 | I915_SKL_SAGV_NOT_CONTROLLED | |
1989 | } skl_sagv_status; | |
1990 | ||
53615a5e VS |
1991 | struct { |
1992 | /* | |
1993 | * Raw watermark latency values: | |
1994 | * in 0.1us units for WM0, | |
1995 | * in 0.5us units for WM1+. | |
1996 | */ | |
1997 | /* primary */ | |
1998 | uint16_t pri_latency[5]; | |
1999 | /* sprite */ | |
2000 | uint16_t spr_latency[5]; | |
2001 | /* cursor */ | |
2002 | uint16_t cur_latency[5]; | |
2af30a5c PB |
2003 | /* |
2004 | * Raw watermark memory latency values | |
2005 | * for SKL for all 8 levels | |
2006 | * in 1us units. | |
2007 | */ | |
2008 | uint16_t skl_latency[8]; | |
609cedef | 2009 | |
2d41c0b5 PB |
2010 | /* |
2011 | * The skl_wm_values structure is a bit too big for stack | |
2012 | * allocation, so we keep the staging struct where we store | |
2013 | * intermediate results here instead. | |
2014 | */ | |
2015 | struct skl_wm_values skl_results; | |
2016 | ||
609cedef | 2017 | /* current hardware state */ |
2d41c0b5 PB |
2018 | union { |
2019 | struct ilk_wm_values hw; | |
2020 | struct skl_wm_values skl_hw; | |
0018fda1 | 2021 | struct vlv_wm_values vlv; |
2d41c0b5 | 2022 | }; |
58590c14 VS |
2023 | |
2024 | uint8_t max_level; | |
ed4a6a7c MR |
2025 | |
2026 | /* | |
2027 | * Should be held around atomic WM register writing; also | |
2028 | * protects * intel_crtc->wm.active and | |
2029 | * cstate->wm.need_postvbl_update. | |
2030 | */ | |
2031 | struct mutex wm_mutex; | |
279e99d7 MR |
2032 | |
2033 | /* | |
2034 | * Set during HW readout of watermarks/DDB. Some platforms | |
2035 | * need to know when we're still using BIOS-provided values | |
2036 | * (which we don't fully trust). | |
2037 | */ | |
2038 | bool distrust_bios_wm; | |
53615a5e VS |
2039 | } wm; |
2040 | ||
8a187455 PZ |
2041 | struct i915_runtime_pm pm; |
2042 | ||
a83014d3 OM |
2043 | /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */ |
2044 | struct { | |
821ed7df | 2045 | void (*resume)(struct drm_i915_private *); |
117897f4 | 2046 | void (*cleanup_engine)(struct intel_engine_cs *engine); |
67d97da3 CW |
2047 | |
2048 | /** | |
2049 | * Is the GPU currently considered idle, or busy executing | |
2050 | * userspace requests? Whilst idle, we allow runtime power | |
2051 | * management to power down the hardware and display clocks. | |
2052 | * In order to reduce the effect on performance, there | |
2053 | * is a slight delay before we do so. | |
2054 | */ | |
2055 | unsigned int active_engines; | |
2056 | bool awake; | |
2057 | ||
2058 | /** | |
2059 | * We leave the user IRQ off as much as possible, | |
2060 | * but this means that requests will finish and never | |
2061 | * be retired once the system goes idle. Set a timer to | |
2062 | * fire periodically while the ring is running. When it | |
2063 | * fires, go retire requests. | |
2064 | */ | |
2065 | struct delayed_work retire_work; | |
2066 | ||
2067 | /** | |
2068 | * When we detect an idle GPU, we want to turn on | |
2069 | * powersaving features. So once we see that there | |
2070 | * are no more requests outstanding and no more | |
2071 | * arrive within a small period of time, we fire | |
2072 | * off the idle_work. | |
2073 | */ | |
2074 | struct delayed_work idle_work; | |
a83014d3 OM |
2075 | } gt; |
2076 | ||
3be60de9 VS |
2077 | /* perform PHY state sanity checks? */ |
2078 | bool chv_phy_assert[2]; | |
2079 | ||
0bdf5a05 TI |
2080 | struct intel_encoder *dig_port_map[I915_MAX_PORTS]; |
2081 | ||
bdf1e7e3 DV |
2082 | /* |
2083 | * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch | |
2084 | * will be rejected. Instead look for a better place. | |
2085 | */ | |
77fec556 | 2086 | }; |
1da177e4 | 2087 | |
2c1792a1 CW |
2088 | static inline struct drm_i915_private *to_i915(const struct drm_device *dev) |
2089 | { | |
091387c1 | 2090 | return container_of(dev, struct drm_i915_private, drm); |
2c1792a1 CW |
2091 | } |
2092 | ||
c49d13ee | 2093 | static inline struct drm_i915_private *kdev_to_i915(struct device *kdev) |
888d0d42 | 2094 | { |
c49d13ee | 2095 | return to_i915(dev_get_drvdata(kdev)); |
888d0d42 ID |
2096 | } |
2097 | ||
33a732f4 AD |
2098 | static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc) |
2099 | { | |
2100 | return container_of(guc, struct drm_i915_private, guc); | |
2101 | } | |
2102 | ||
b4ac5afc DG |
2103 | /* Simple iterator over all initialised engines */ |
2104 | #define for_each_engine(engine__, dev_priv__) \ | |
2105 | for ((engine__) = &(dev_priv__)->engine[0]; \ | |
2106 | (engine__) < &(dev_priv__)->engine[I915_NUM_ENGINES]; \ | |
2107 | (engine__)++) \ | |
2108 | for_each_if (intel_engine_initialized(engine__)) | |
b4519513 | 2109 | |
c3232b18 DG |
2110 | /* Iterator with engine_id */ |
2111 | #define for_each_engine_id(engine__, dev_priv__, id__) \ | |
2112 | for ((engine__) = &(dev_priv__)->engine[0], (id__) = 0; \ | |
2113 | (engine__) < &(dev_priv__)->engine[I915_NUM_ENGINES]; \ | |
2114 | (engine__)++) \ | |
2115 | for_each_if (((id__) = (engine__)->id, \ | |
2116 | intel_engine_initialized(engine__))) | |
2117 | ||
bafb0fce CW |
2118 | #define __mask_next_bit(mask) ({ \ |
2119 | int __idx = ffs(mask) - 1; \ | |
2120 | mask &= ~BIT(__idx); \ | |
2121 | __idx; \ | |
2122 | }) | |
2123 | ||
c3232b18 | 2124 | /* Iterator over subset of engines selected by mask */ |
bafb0fce CW |
2125 | #define for_each_engine_masked(engine__, dev_priv__, mask__, tmp__) \ |
2126 | for (tmp__ = mask__ & INTEL_INFO(dev_priv__)->ring_mask; \ | |
2127 | tmp__ ? (engine__ = &(dev_priv__)->engine[__mask_next_bit(tmp__)]), 1 : 0; ) | |
ee4b6faf | 2128 | |
b1d7e4b4 WF |
2129 | enum hdmi_force_audio { |
2130 | HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */ | |
2131 | HDMI_AUDIO_OFF, /* force turn off HDMI audio */ | |
2132 | HDMI_AUDIO_AUTO, /* trust EDID */ | |
2133 | HDMI_AUDIO_ON, /* force turn on HDMI audio */ | |
2134 | }; | |
2135 | ||
190d6cd5 | 2136 | #define I915_GTT_OFFSET_NONE ((u32)-1) |
ed2f3452 | 2137 | |
37e680a1 | 2138 | struct drm_i915_gem_object_ops { |
de472664 CW |
2139 | unsigned int flags; |
2140 | #define I915_GEM_OBJECT_HAS_STRUCT_PAGE 0x1 | |
2141 | ||
37e680a1 CW |
2142 | /* Interface between the GEM object and its backing storage. |
2143 | * get_pages() is called once prior to the use of the associated set | |
2144 | * of pages before to binding them into the GTT, and put_pages() is | |
2145 | * called after we no longer need them. As we expect there to be | |
2146 | * associated cost with migrating pages between the backing storage | |
2147 | * and making them available for the GPU (e.g. clflush), we may hold | |
2148 | * onto the pages after they are no longer referenced by the GPU | |
2149 | * in case they may be used again shortly (for example migrating the | |
2150 | * pages to a different memory domain within the GTT). put_pages() | |
2151 | * will therefore most likely be called when the object itself is | |
2152 | * being released or under memory pressure (where we attempt to | |
2153 | * reap pages for the shrinker). | |
2154 | */ | |
2155 | int (*get_pages)(struct drm_i915_gem_object *); | |
2156 | void (*put_pages)(struct drm_i915_gem_object *); | |
de472664 | 2157 | |
5cc9ed4b CW |
2158 | int (*dmabuf_export)(struct drm_i915_gem_object *); |
2159 | void (*release)(struct drm_i915_gem_object *); | |
37e680a1 CW |
2160 | }; |
2161 | ||
a071fa00 DV |
2162 | /* |
2163 | * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is | |
d1b9d039 | 2164 | * considered to be the frontbuffer for the given plane interface-wise. This |
a071fa00 DV |
2165 | * doesn't mean that the hw necessarily already scans it out, but that any |
2166 | * rendering (by the cpu or gpu) will land in the frontbuffer eventually. | |
2167 | * | |
2168 | * We have one bit per pipe and per scanout plane type. | |
2169 | */ | |
d1b9d039 SAK |
2170 | #define INTEL_MAX_SPRITE_BITS_PER_PIPE 5 |
2171 | #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8 | |
a071fa00 DV |
2172 | #define INTEL_FRONTBUFFER_PRIMARY(pipe) \ |
2173 | (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))) | |
2174 | #define INTEL_FRONTBUFFER_CURSOR(pipe) \ | |
d1b9d039 SAK |
2175 | (1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))) |
2176 | #define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \ | |
2177 | (1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))) | |
a071fa00 | 2178 | #define INTEL_FRONTBUFFER_OVERLAY(pipe) \ |
d1b9d039 | 2179 | (1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))) |
cc36513c | 2180 | #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \ |
d1b9d039 | 2181 | (0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))) |
a071fa00 | 2182 | |
673a394b | 2183 | struct drm_i915_gem_object { |
c397b908 | 2184 | struct drm_gem_object base; |
673a394b | 2185 | |
37e680a1 CW |
2186 | const struct drm_i915_gem_object_ops *ops; |
2187 | ||
2f633156 BW |
2188 | /** List of VMAs backed by this object */ |
2189 | struct list_head vma_list; | |
2190 | ||
c1ad11fc CW |
2191 | /** Stolen memory for this object, instead of being backed by shmem. */ |
2192 | struct drm_mm_node *stolen; | |
35c20a60 | 2193 | struct list_head global_list; |
673a394b | 2194 | |
b25cb2f8 BW |
2195 | /** Used in execbuf to temporarily hold a ref */ |
2196 | struct list_head obj_exec_link; | |
673a394b | 2197 | |
8d9d5744 | 2198 | struct list_head batch_pool_link; |
493018dc | 2199 | |
573adb39 | 2200 | unsigned long flags; |
673a394b | 2201 | /** |
65ce3027 CW |
2202 | * This is set if the object is on the active lists (has pending |
2203 | * rendering and so a non-zero seqno), and is not set if it i s on | |
2204 | * inactive (ready to be unbound) list. | |
673a394b | 2205 | */ |
573adb39 CW |
2206 | #define I915_BO_ACTIVE_SHIFT 0 |
2207 | #define I915_BO_ACTIVE_MASK ((1 << I915_NUM_ENGINES) - 1) | |
2208 | #define __I915_BO_ACTIVE(bo) \ | |
2209 | ((READ_ONCE((bo)->flags) >> I915_BO_ACTIVE_SHIFT) & I915_BO_ACTIVE_MASK) | |
673a394b EA |
2210 | |
2211 | /** | |
2212 | * This is set if the object has been written to since last bound | |
2213 | * to the GTT | |
2214 | */ | |
0206e353 | 2215 | unsigned int dirty:1; |
778c3544 | 2216 | |
778c3544 DV |
2217 | /** |
2218 | * Advice: are the backing pages purgeable? | |
2219 | */ | |
0206e353 | 2220 | unsigned int madv:2; |
778c3544 | 2221 | |
fb7d516a DV |
2222 | /** |
2223 | * Whether the current gtt mapping needs to be mappable (and isn't just | |
2224 | * mappable by accident). Track pin and fault separate for a more | |
2225 | * accurate mappable working set. | |
2226 | */ | |
0206e353 | 2227 | unsigned int fault_mappable:1; |
fb7d516a | 2228 | |
24f3a8cf AG |
2229 | /* |
2230 | * Is the object to be mapped as read-only to the GPU | |
2231 | * Only honoured if hardware has relevant pte bit | |
2232 | */ | |
2233 | unsigned long gt_ro:1; | |
651d794f | 2234 | unsigned int cache_level:3; |
0f71979a | 2235 | unsigned int cache_dirty:1; |
93dfb40c | 2236 | |
faf5bf0a | 2237 | atomic_t frontbuffer_bits; |
50349247 | 2238 | unsigned int frontbuffer_ggtt_origin; /* write once */ |
a071fa00 | 2239 | |
9ad36761 | 2240 | /** Current tiling stride for the object, if it's tiled. */ |
3e510a8e CW |
2241 | unsigned int tiling_and_stride; |
2242 | #define FENCE_MINIMUM_STRIDE 128 /* See i915_tiling_ok() */ | |
2243 | #define TILING_MASK (FENCE_MINIMUM_STRIDE-1) | |
2244 | #define STRIDE_MASK (~TILING_MASK) | |
9ad36761 | 2245 | |
15717de2 CW |
2246 | /** Count of VMA actually bound by this object */ |
2247 | unsigned int bind_count; | |
8a0c39b1 TU |
2248 | unsigned int pin_display; |
2249 | ||
9da3da66 | 2250 | struct sg_table *pages; |
a5570178 | 2251 | int pages_pin_count; |
ee286370 CW |
2252 | struct get_page { |
2253 | struct scatterlist *sg; | |
2254 | int last; | |
2255 | } get_page; | |
0a798eb9 | 2256 | void *mapping; |
9a70cc2a | 2257 | |
b4716185 CW |
2258 | /** Breadcrumb of last rendering to the buffer. |
2259 | * There can only be one writer, but we allow for multiple readers. | |
2260 | * If there is a writer that necessarily implies that all other | |
2261 | * read requests are complete - but we may only be lazily clearing | |
2262 | * the read requests. A read request is naturally the most recent | |
2263 | * request on a ring, so we may have two different write and read | |
2264 | * requests on one ring where the write request is older than the | |
2265 | * read request. This allows for the CPU to read from an active | |
2266 | * buffer by only waiting for the write to complete. | |
381f371b CW |
2267 | */ |
2268 | struct i915_gem_active last_read[I915_NUM_ENGINES]; | |
2269 | struct i915_gem_active last_write; | |
673a394b | 2270 | |
80075d49 DV |
2271 | /** References from framebuffers, locks out tiling changes. */ |
2272 | unsigned long framebuffer_references; | |
2273 | ||
280b713b | 2274 | /** Record of address bit 17 of each page at last unbind. */ |
d312ec25 | 2275 | unsigned long *bit_17; |
280b713b | 2276 | |
5cc9ed4b | 2277 | union { |
6a2c4232 CW |
2278 | /** for phy allocated objects */ |
2279 | struct drm_dma_handle *phys_handle; | |
2280 | ||
5cc9ed4b CW |
2281 | struct i915_gem_userptr { |
2282 | uintptr_t ptr; | |
2283 | unsigned read_only :1; | |
2284 | unsigned workers :4; | |
2285 | #define I915_GEM_USERPTR_MAX_WORKERS 15 | |
2286 | ||
ad46cb53 CW |
2287 | struct i915_mm_struct *mm; |
2288 | struct i915_mmu_object *mmu_object; | |
5cc9ed4b CW |
2289 | struct work_struct *work; |
2290 | } userptr; | |
2291 | }; | |
2292 | }; | |
03ac0642 CW |
2293 | |
2294 | static inline struct drm_i915_gem_object * | |
2295 | to_intel_bo(struct drm_gem_object *gem) | |
2296 | { | |
2297 | /* Assert that to_intel_bo(NULL) == NULL */ | |
2298 | BUILD_BUG_ON(offsetof(struct drm_i915_gem_object, base)); | |
2299 | ||
2300 | return container_of(gem, struct drm_i915_gem_object, base); | |
2301 | } | |
2302 | ||
2303 | static inline struct drm_i915_gem_object * | |
2304 | i915_gem_object_lookup(struct drm_file *file, u32 handle) | |
2305 | { | |
2306 | return to_intel_bo(drm_gem_object_lookup(file, handle)); | |
2307 | } | |
2308 | ||
2309 | __deprecated | |
2310 | extern struct drm_gem_object * | |
2311 | drm_gem_object_lookup(struct drm_file *file, u32 handle); | |
23010e43 | 2312 | |
25dc556a CW |
2313 | __attribute__((nonnull)) |
2314 | static inline struct drm_i915_gem_object * | |
2315 | i915_gem_object_get(struct drm_i915_gem_object *obj) | |
2316 | { | |
2317 | drm_gem_object_reference(&obj->base); | |
2318 | return obj; | |
2319 | } | |
2320 | ||
2321 | __deprecated | |
2322 | extern void drm_gem_object_reference(struct drm_gem_object *); | |
2323 | ||
f8c417cd CW |
2324 | __attribute__((nonnull)) |
2325 | static inline void | |
2326 | i915_gem_object_put(struct drm_i915_gem_object *obj) | |
2327 | { | |
2328 | drm_gem_object_unreference(&obj->base); | |
2329 | } | |
2330 | ||
2331 | __deprecated | |
2332 | extern void drm_gem_object_unreference(struct drm_gem_object *); | |
2333 | ||
34911fd3 CW |
2334 | __attribute__((nonnull)) |
2335 | static inline void | |
2336 | i915_gem_object_put_unlocked(struct drm_i915_gem_object *obj) | |
2337 | { | |
2338 | drm_gem_object_unreference_unlocked(&obj->base); | |
2339 | } | |
2340 | ||
2341 | __deprecated | |
2342 | extern void drm_gem_object_unreference_unlocked(struct drm_gem_object *); | |
2343 | ||
b9bcd14a CW |
2344 | static inline bool |
2345 | i915_gem_object_has_struct_page(const struct drm_i915_gem_object *obj) | |
2346 | { | |
2347 | return obj->ops->flags & I915_GEM_OBJECT_HAS_STRUCT_PAGE; | |
2348 | } | |
2349 | ||
573adb39 CW |
2350 | static inline unsigned long |
2351 | i915_gem_object_get_active(const struct drm_i915_gem_object *obj) | |
2352 | { | |
2353 | return (obj->flags >> I915_BO_ACTIVE_SHIFT) & I915_BO_ACTIVE_MASK; | |
2354 | } | |
2355 | ||
2356 | static inline bool | |
2357 | i915_gem_object_is_active(const struct drm_i915_gem_object *obj) | |
2358 | { | |
2359 | return i915_gem_object_get_active(obj); | |
2360 | } | |
2361 | ||
2362 | static inline void | |
2363 | i915_gem_object_set_active(struct drm_i915_gem_object *obj, int engine) | |
2364 | { | |
2365 | obj->flags |= BIT(engine + I915_BO_ACTIVE_SHIFT); | |
2366 | } | |
2367 | ||
2368 | static inline void | |
2369 | i915_gem_object_clear_active(struct drm_i915_gem_object *obj, int engine) | |
2370 | { | |
2371 | obj->flags &= ~BIT(engine + I915_BO_ACTIVE_SHIFT); | |
2372 | } | |
2373 | ||
2374 | static inline bool | |
2375 | i915_gem_object_has_active_engine(const struct drm_i915_gem_object *obj, | |
2376 | int engine) | |
2377 | { | |
2378 | return obj->flags & BIT(engine + I915_BO_ACTIVE_SHIFT); | |
2379 | } | |
2380 | ||
3e510a8e CW |
2381 | static inline unsigned int |
2382 | i915_gem_object_get_tiling(struct drm_i915_gem_object *obj) | |
2383 | { | |
2384 | return obj->tiling_and_stride & TILING_MASK; | |
2385 | } | |
2386 | ||
2387 | static inline bool | |
2388 | i915_gem_object_is_tiled(struct drm_i915_gem_object *obj) | |
2389 | { | |
2390 | return i915_gem_object_get_tiling(obj) != I915_TILING_NONE; | |
2391 | } | |
2392 | ||
2393 | static inline unsigned int | |
2394 | i915_gem_object_get_stride(struct drm_i915_gem_object *obj) | |
2395 | { | |
2396 | return obj->tiling_and_stride & STRIDE_MASK; | |
2397 | } | |
2398 | ||
624192cf CW |
2399 | static inline struct i915_vma *i915_vma_get(struct i915_vma *vma) |
2400 | { | |
2401 | i915_gem_object_get(vma->obj); | |
2402 | return vma; | |
2403 | } | |
2404 | ||
2405 | static inline void i915_vma_put(struct i915_vma *vma) | |
2406 | { | |
2407 | lockdep_assert_held(&vma->vm->dev->struct_mutex); | |
2408 | i915_gem_object_put(vma->obj); | |
2409 | } | |
2410 | ||
85d1225e DG |
2411 | /* |
2412 | * Optimised SGL iterator for GEM objects | |
2413 | */ | |
2414 | static __always_inline struct sgt_iter { | |
2415 | struct scatterlist *sgp; | |
2416 | union { | |
2417 | unsigned long pfn; | |
2418 | dma_addr_t dma; | |
2419 | }; | |
2420 | unsigned int curr; | |
2421 | unsigned int max; | |
2422 | } __sgt_iter(struct scatterlist *sgl, bool dma) { | |
2423 | struct sgt_iter s = { .sgp = sgl }; | |
2424 | ||
2425 | if (s.sgp) { | |
2426 | s.max = s.curr = s.sgp->offset; | |
2427 | s.max += s.sgp->length; | |
2428 | if (dma) | |
2429 | s.dma = sg_dma_address(s.sgp); | |
2430 | else | |
2431 | s.pfn = page_to_pfn(sg_page(s.sgp)); | |
2432 | } | |
2433 | ||
2434 | return s; | |
2435 | } | |
2436 | ||
63d15326 DG |
2437 | /** |
2438 | * __sg_next - return the next scatterlist entry in a list | |
2439 | * @sg: The current sg entry | |
2440 | * | |
2441 | * Description: | |
2442 | * If the entry is the last, return NULL; otherwise, step to the next | |
2443 | * element in the array (@sg@+1). If that's a chain pointer, follow it; | |
2444 | * otherwise just return the pointer to the current element. | |
2445 | **/ | |
2446 | static inline struct scatterlist *__sg_next(struct scatterlist *sg) | |
2447 | { | |
2448 | #ifdef CONFIG_DEBUG_SG | |
2449 | BUG_ON(sg->sg_magic != SG_MAGIC); | |
2450 | #endif | |
2451 | return sg_is_last(sg) ? NULL : | |
2452 | likely(!sg_is_chain(++sg)) ? sg : | |
2453 | sg_chain_ptr(sg); | |
2454 | } | |
2455 | ||
85d1225e DG |
2456 | /** |
2457 | * for_each_sgt_dma - iterate over the DMA addresses of the given sg_table | |
2458 | * @__dmap: DMA address (output) | |
2459 | * @__iter: 'struct sgt_iter' (iterator state, internal) | |
2460 | * @__sgt: sg_table to iterate over (input) | |
2461 | */ | |
2462 | #define for_each_sgt_dma(__dmap, __iter, __sgt) \ | |
2463 | for ((__iter) = __sgt_iter((__sgt)->sgl, true); \ | |
2464 | ((__dmap) = (__iter).dma + (__iter).curr); \ | |
2465 | (((__iter).curr += PAGE_SIZE) < (__iter).max) || \ | |
63d15326 | 2466 | ((__iter) = __sgt_iter(__sg_next((__iter).sgp), true), 0)) |
85d1225e DG |
2467 | |
2468 | /** | |
2469 | * for_each_sgt_page - iterate over the pages of the given sg_table | |
2470 | * @__pp: page pointer (output) | |
2471 | * @__iter: 'struct sgt_iter' (iterator state, internal) | |
2472 | * @__sgt: sg_table to iterate over (input) | |
2473 | */ | |
2474 | #define for_each_sgt_page(__pp, __iter, __sgt) \ | |
2475 | for ((__iter) = __sgt_iter((__sgt)->sgl, false); \ | |
2476 | ((__pp) = (__iter).pfn == 0 ? NULL : \ | |
2477 | pfn_to_page((__iter).pfn + ((__iter).curr >> PAGE_SHIFT))); \ | |
2478 | (((__iter).curr += PAGE_SIZE) < (__iter).max) || \ | |
63d15326 | 2479 | ((__iter) = __sgt_iter(__sg_next((__iter).sgp), false), 0)) |
a071fa00 | 2480 | |
351e3db2 BV |
2481 | /* |
2482 | * A command that requires special handling by the command parser. | |
2483 | */ | |
2484 | struct drm_i915_cmd_descriptor { | |
2485 | /* | |
2486 | * Flags describing how the command parser processes the command. | |
2487 | * | |
2488 | * CMD_DESC_FIXED: The command has a fixed length if this is set, | |
2489 | * a length mask if not set | |
2490 | * CMD_DESC_SKIP: The command is allowed but does not follow the | |
2491 | * standard length encoding for the opcode range in | |
2492 | * which it falls | |
2493 | * CMD_DESC_REJECT: The command is never allowed | |
2494 | * CMD_DESC_REGISTER: The command should be checked against the | |
2495 | * register whitelist for the appropriate ring | |
2496 | * CMD_DESC_MASTER: The command is allowed if the submitting process | |
2497 | * is the DRM master | |
2498 | */ | |
2499 | u32 flags; | |
2500 | #define CMD_DESC_FIXED (1<<0) | |
2501 | #define CMD_DESC_SKIP (1<<1) | |
2502 | #define CMD_DESC_REJECT (1<<2) | |
2503 | #define CMD_DESC_REGISTER (1<<3) | |
2504 | #define CMD_DESC_BITMASK (1<<4) | |
2505 | #define CMD_DESC_MASTER (1<<5) | |
2506 | ||
2507 | /* | |
2508 | * The command's unique identification bits and the bitmask to get them. | |
2509 | * This isn't strictly the opcode field as defined in the spec and may | |
2510 | * also include type, subtype, and/or subop fields. | |
2511 | */ | |
2512 | struct { | |
2513 | u32 value; | |
2514 | u32 mask; | |
2515 | } cmd; | |
2516 | ||
2517 | /* | |
2518 | * The command's length. The command is either fixed length (i.e. does | |
2519 | * not include a length field) or has a length field mask. The flag | |
2520 | * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has | |
2521 | * a length mask. All command entries in a command table must include | |
2522 | * length information. | |
2523 | */ | |
2524 | union { | |
2525 | u32 fixed; | |
2526 | u32 mask; | |
2527 | } length; | |
2528 | ||
2529 | /* | |
2530 | * Describes where to find a register address in the command to check | |
2531 | * against the ring's register whitelist. Only valid if flags has the | |
2532 | * CMD_DESC_REGISTER bit set. | |
6a65c5b9 FJ |
2533 | * |
2534 | * A non-zero step value implies that the command may access multiple | |
2535 | * registers in sequence (e.g. LRI), in that case step gives the | |
2536 | * distance in dwords between individual offset fields. | |
351e3db2 BV |
2537 | */ |
2538 | struct { | |
2539 | u32 offset; | |
2540 | u32 mask; | |
6a65c5b9 | 2541 | u32 step; |
351e3db2 BV |
2542 | } reg; |
2543 | ||
2544 | #define MAX_CMD_DESC_BITMASKS 3 | |
2545 | /* | |
2546 | * Describes command checks where a particular dword is masked and | |
2547 | * compared against an expected value. If the command does not match | |
2548 | * the expected value, the parser rejects it. Only valid if flags has | |
2549 | * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero | |
2550 | * are valid. | |
d4d48035 BV |
2551 | * |
2552 | * If the check specifies a non-zero condition_mask then the parser | |
2553 | * only performs the check when the bits specified by condition_mask | |
2554 | * are non-zero. | |
351e3db2 BV |
2555 | */ |
2556 | struct { | |
2557 | u32 offset; | |
2558 | u32 mask; | |
2559 | u32 expected; | |
d4d48035 BV |
2560 | u32 condition_offset; |
2561 | u32 condition_mask; | |
351e3db2 BV |
2562 | } bits[MAX_CMD_DESC_BITMASKS]; |
2563 | }; | |
2564 | ||
2565 | /* | |
2566 | * A table of commands requiring special handling by the command parser. | |
2567 | * | |
33a051a5 CW |
2568 | * Each engine has an array of tables. Each table consists of an array of |
2569 | * command descriptors, which must be sorted with command opcodes in | |
2570 | * ascending order. | |
351e3db2 BV |
2571 | */ |
2572 | struct drm_i915_cmd_table { | |
2573 | const struct drm_i915_cmd_descriptor *table; | |
2574 | int count; | |
2575 | }; | |
2576 | ||
dbbe9127 | 2577 | /* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */ |
7312e2dd CW |
2578 | #define __I915__(p) ({ \ |
2579 | struct drm_i915_private *__p; \ | |
2580 | if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \ | |
2581 | __p = (struct drm_i915_private *)p; \ | |
2582 | else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \ | |
2583 | __p = to_i915((struct drm_device *)p); \ | |
2584 | else \ | |
2585 | BUILD_BUG(); \ | |
2586 | __p; \ | |
2587 | }) | |
351c3b53 | 2588 | #define INTEL_INFO(p) (&__I915__(p)->info) |
3f10e82f | 2589 | #define INTEL_GEN(p) (INTEL_INFO(p)->gen) |
87f1f465 | 2590 | #define INTEL_DEVID(p) (INTEL_INFO(p)->device_id) |
cae5852d | 2591 | |
e87a005d | 2592 | #define REVID_FOREVER 0xff |
091387c1 | 2593 | #define INTEL_REVID(p) (__I915__(p)->drm.pdev->revision) |
ac657f64 TU |
2594 | |
2595 | #define GEN_FOREVER (0) | |
2596 | /* | |
2597 | * Returns true if Gen is in inclusive range [Start, End]. | |
2598 | * | |
2599 | * Use GEN_FOREVER for unbound start and or end. | |
2600 | */ | |
2601 | #define IS_GEN(p, s, e) ({ \ | |
2602 | unsigned int __s = (s), __e = (e); \ | |
2603 | BUILD_BUG_ON(!__builtin_constant_p(s)); \ | |
2604 | BUILD_BUG_ON(!__builtin_constant_p(e)); \ | |
2605 | if ((__s) != GEN_FOREVER) \ | |
2606 | __s = (s) - 1; \ | |
2607 | if ((__e) == GEN_FOREVER) \ | |
2608 | __e = BITS_PER_LONG - 1; \ | |
2609 | else \ | |
2610 | __e = (e) - 1; \ | |
2611 | !!(INTEL_INFO(p)->gen_mask & GENMASK((__e), (__s))); \ | |
2612 | }) | |
2613 | ||
e87a005d JN |
2614 | /* |
2615 | * Return true if revision is in range [since,until] inclusive. | |
2616 | * | |
2617 | * Use 0 for open-ended since, and REVID_FOREVER for open-ended until. | |
2618 | */ | |
2619 | #define IS_REVID(p, since, until) \ | |
2620 | (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until)) | |
2621 | ||
87f1f465 CW |
2622 | #define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577) |
2623 | #define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562) | |
cae5852d | 2624 | #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x) |
87f1f465 | 2625 | #define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572) |
cae5852d | 2626 | #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g) |
87f1f465 CW |
2627 | #define IS_I915GM(dev) (INTEL_DEVID(dev) == 0x2592) |
2628 | #define IS_I945G(dev) (INTEL_DEVID(dev) == 0x2772) | |
cae5852d ZN |
2629 | #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm) |
2630 | #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater) | |
2631 | #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline) | |
87f1f465 | 2632 | #define IS_GM45(dev) (INTEL_DEVID(dev) == 0x2A42) |
cae5852d | 2633 | #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x) |
87f1f465 CW |
2634 | #define IS_PINEVIEW_G(dev) (INTEL_DEVID(dev) == 0xa001) |
2635 | #define IS_PINEVIEW_M(dev) (INTEL_DEVID(dev) == 0xa011) | |
cae5852d ZN |
2636 | #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview) |
2637 | #define IS_G33(dev) (INTEL_INFO(dev)->is_g33) | |
87f1f465 | 2638 | #define IS_IRONLAKE_M(dev) (INTEL_DEVID(dev) == 0x0046) |
4b65177b | 2639 | #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge) |
87f1f465 CW |
2640 | #define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 || \ |
2641 | INTEL_DEVID(dev) == 0x0152 || \ | |
2642 | INTEL_DEVID(dev) == 0x015a) | |
70a3eb7a | 2643 | #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview) |
666a4537 | 2644 | #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_cherryview) |
4cae9ae0 | 2645 | #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell) |
ab0d24ac | 2646 | #define IS_BROADWELL(dev) (INTEL_INFO(dev)->is_broadwell) |
7201c0b3 | 2647 | #define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake) |
7526ac19 | 2648 | #define IS_BROXTON(dev) (INTEL_INFO(dev)->is_broxton) |
ef11bdb3 | 2649 | #define IS_KABYLAKE(dev) (INTEL_INFO(dev)->is_kabylake) |
cae5852d | 2650 | #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) |
ed1c9e2c | 2651 | #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \ |
87f1f465 | 2652 | (INTEL_DEVID(dev) & 0xFF00) == 0x0C00) |
5dd8c4c3 | 2653 | #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \ |
6b96d705 | 2654 | ((INTEL_DEVID(dev) & 0xf) == 0x6 || \ |
0dc6f20b | 2655 | (INTEL_DEVID(dev) & 0xf) == 0xb || \ |
87f1f465 | 2656 | (INTEL_DEVID(dev) & 0xf) == 0xe)) |
ebb72aad VS |
2657 | /* ULX machines are also considered ULT. */ |
2658 | #define IS_BDW_ULX(dev) (IS_BROADWELL(dev) && \ | |
2659 | (INTEL_DEVID(dev) & 0xf) == 0xe) | |
a0fcbd95 RV |
2660 | #define IS_BDW_GT3(dev) (IS_BROADWELL(dev) && \ |
2661 | (INTEL_DEVID(dev) & 0x00F0) == 0x0020) | |
5dd8c4c3 | 2662 | #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \ |
87f1f465 | 2663 | (INTEL_DEVID(dev) & 0xFF00) == 0x0A00) |
9435373e | 2664 | #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \ |
87f1f465 | 2665 | (INTEL_DEVID(dev) & 0x00F0) == 0x0020) |
9bbfd20a | 2666 | /* ULX machines are also considered ULT. */ |
87f1f465 CW |
2667 | #define IS_HSW_ULX(dev) (INTEL_DEVID(dev) == 0x0A0E || \ |
2668 | INTEL_DEVID(dev) == 0x0A1E) | |
f8896f5d DW |
2669 | #define IS_SKL_ULT(dev) (INTEL_DEVID(dev) == 0x1906 || \ |
2670 | INTEL_DEVID(dev) == 0x1913 || \ | |
2671 | INTEL_DEVID(dev) == 0x1916 || \ | |
2672 | INTEL_DEVID(dev) == 0x1921 || \ | |
2673 | INTEL_DEVID(dev) == 0x1926) | |
2674 | #define IS_SKL_ULX(dev) (INTEL_DEVID(dev) == 0x190E || \ | |
2675 | INTEL_DEVID(dev) == 0x1915 || \ | |
2676 | INTEL_DEVID(dev) == 0x191E) | |
a5b7991c RV |
2677 | #define IS_KBL_ULT(dev) (INTEL_DEVID(dev) == 0x5906 || \ |
2678 | INTEL_DEVID(dev) == 0x5913 || \ | |
2679 | INTEL_DEVID(dev) == 0x5916 || \ | |
2680 | INTEL_DEVID(dev) == 0x5921 || \ | |
2681 | INTEL_DEVID(dev) == 0x5926) | |
2682 | #define IS_KBL_ULX(dev) (INTEL_DEVID(dev) == 0x590E || \ | |
2683 | INTEL_DEVID(dev) == 0x5915 || \ | |
2684 | INTEL_DEVID(dev) == 0x591E) | |
7a58bad0 SAK |
2685 | #define IS_SKL_GT3(dev) (IS_SKYLAKE(dev) && \ |
2686 | (INTEL_DEVID(dev) & 0x00F0) == 0x0020) | |
2687 | #define IS_SKL_GT4(dev) (IS_SKYLAKE(dev) && \ | |
2688 | (INTEL_DEVID(dev) & 0x00F0) == 0x0030) | |
2689 | ||
b833d685 | 2690 | #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary) |
cae5852d | 2691 | |
ef712bb4 JN |
2692 | #define SKL_REVID_A0 0x0 |
2693 | #define SKL_REVID_B0 0x1 | |
2694 | #define SKL_REVID_C0 0x2 | |
2695 | #define SKL_REVID_D0 0x3 | |
2696 | #define SKL_REVID_E0 0x4 | |
2697 | #define SKL_REVID_F0 0x5 | |
4ba9c1f7 MK |
2698 | #define SKL_REVID_G0 0x6 |
2699 | #define SKL_REVID_H0 0x7 | |
ef712bb4 | 2700 | |
e87a005d JN |
2701 | #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until)) |
2702 | ||
ef712bb4 | 2703 | #define BXT_REVID_A0 0x0 |
fffda3f4 | 2704 | #define BXT_REVID_A1 0x1 |
ef712bb4 JN |
2705 | #define BXT_REVID_B0 0x3 |
2706 | #define BXT_REVID_C0 0x9 | |
6c74c87f | 2707 | |
e87a005d JN |
2708 | #define IS_BXT_REVID(p, since, until) (IS_BROXTON(p) && IS_REVID(p, since, until)) |
2709 | ||
c033a37c MK |
2710 | #define KBL_REVID_A0 0x0 |
2711 | #define KBL_REVID_B0 0x1 | |
fe905819 MK |
2712 | #define KBL_REVID_C0 0x2 |
2713 | #define KBL_REVID_D0 0x3 | |
2714 | #define KBL_REVID_E0 0x4 | |
c033a37c MK |
2715 | |
2716 | #define IS_KBL_REVID(p, since, until) \ | |
2717 | (IS_KABYLAKE(p) && IS_REVID(p, since, until)) | |
2718 | ||
85436696 JB |
2719 | /* |
2720 | * The genX designation typically refers to the render engine, so render | |
2721 | * capability related checks should use IS_GEN, while display and other checks | |
2722 | * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular | |
2723 | * chips, etc.). | |
2724 | */ | |
af1346a0 TU |
2725 | #define IS_GEN2(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(1))) |
2726 | #define IS_GEN3(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(2))) | |
2727 | #define IS_GEN4(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(3))) | |
2728 | #define IS_GEN5(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(4))) | |
2729 | #define IS_GEN6(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(5))) | |
2730 | #define IS_GEN7(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(6))) | |
2731 | #define IS_GEN8(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(7))) | |
2732 | #define IS_GEN9(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(8))) | |
cae5852d | 2733 | |
a19d6ff2 TU |
2734 | #define ENGINE_MASK(id) BIT(id) |
2735 | #define RENDER_RING ENGINE_MASK(RCS) | |
2736 | #define BSD_RING ENGINE_MASK(VCS) | |
2737 | #define BLT_RING ENGINE_MASK(BCS) | |
2738 | #define VEBOX_RING ENGINE_MASK(VECS) | |
2739 | #define BSD2_RING ENGINE_MASK(VCS2) | |
2740 | #define ALL_ENGINES (~0) | |
2741 | ||
2742 | #define HAS_ENGINE(dev_priv, id) \ | |
af1346a0 | 2743 | (!!(INTEL_INFO(dev_priv)->ring_mask & ENGINE_MASK(id))) |
a19d6ff2 TU |
2744 | |
2745 | #define HAS_BSD(dev_priv) HAS_ENGINE(dev_priv, VCS) | |
2746 | #define HAS_BSD2(dev_priv) HAS_ENGINE(dev_priv, VCS2) | |
2747 | #define HAS_BLT(dev_priv) HAS_ENGINE(dev_priv, BCS) | |
2748 | #define HAS_VEBOX(dev_priv) HAS_ENGINE(dev_priv, VECS) | |
2749 | ||
63c42e56 | 2750 | #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc) |
ca377809 | 2751 | #define HAS_SNOOP(dev) (INTEL_INFO(dev)->has_snoop) |
af1346a0 | 2752 | #define HAS_EDRAM(dev) (!!(__I915__(dev)->edram_cap & EDRAM_ENABLED)) |
63c42e56 | 2753 | #define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \ |
3accaf7e | 2754 | HAS_EDRAM(dev)) |
3177659a | 2755 | #define HWS_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->hws_needs_physical) |
cae5852d | 2756 | |
e1a52536 | 2757 | #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->has_hw_contexts) |
4586f1d0 | 2758 | #define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->has_logical_ring_contexts) |
692ef70c | 2759 | #define USES_PPGTT(dev) (i915.enable_ppgtt) |
81ba8aef MT |
2760 | #define USES_FULL_PPGTT(dev) (i915.enable_ppgtt >= 2) |
2761 | #define USES_FULL_48BIT_PPGTT(dev) (i915.enable_ppgtt == 3) | |
1d2a314c | 2762 | |
05394f39 | 2763 | #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay) |
cae5852d ZN |
2764 | #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical) |
2765 | ||
b45305fc DV |
2766 | /* Early gen2 have a totally busted CS tlb and require pinned batches. */ |
2767 | #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev)) | |
06e668ac MK |
2768 | |
2769 | /* WaRsDisableCoarsePowerGating:skl,bxt */ | |
61251512 TU |
2770 | #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \ |
2771 | (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1) || \ | |
2772 | IS_SKL_GT3(dev_priv) || \ | |
2773 | IS_SKL_GT4(dev_priv)) | |
185c66e5 | 2774 | |
4e6b788c DV |
2775 | /* |
2776 | * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts | |
2777 | * even when in MSI mode. This results in spurious interrupt warnings if the | |
2778 | * legacy irq no. is shared with another device. The kernel then disables that | |
2779 | * interrupt source and so prevents the other device from working properly. | |
2780 | */ | |
2781 | #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5) | |
b355f109 | 2782 | #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->has_gmbus_irq) |
b45305fc | 2783 | |
cae5852d ZN |
2784 | /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte |
2785 | * rows, which changed the alignment requirements and fence programming. | |
2786 | */ | |
2787 | #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \ | |
2788 | IS_I915GM(dev))) | |
cae5852d ZN |
2789 | #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv) |
2790 | #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug) | |
cae5852d ZN |
2791 | |
2792 | #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2) | |
2793 | #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr) | |
3a77c4c4 | 2794 | #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc) |
cae5852d | 2795 | |
dbf7786e | 2796 | #define HAS_IPS(dev) (IS_HSW_ULT(dev) || IS_BROADWELL(dev)) |
f5adf94e | 2797 | |
1d3fe53b | 2798 | #define HAS_DP_MST(dev) (INTEL_INFO(dev)->has_dp_mst) |
0c9b3715 | 2799 | |
dd93be58 | 2800 | #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi) |
30568c45 | 2801 | #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg) |
6e3b84d8 | 2802 | #define HAS_PSR(dev) (INTEL_INFO(dev)->has_psr) |
4aa4c23f | 2803 | #define HAS_RUNTIME_PM(dev) (INTEL_INFO(dev)->has_runtime_pm) |
86f3624b | 2804 | #define HAS_RC6(dev) (INTEL_INFO(dev)->has_rc6) |
33b5bf82 | 2805 | #define HAS_RC6p(dev) (INTEL_INFO(dev)->has_rc6p) |
affa9354 | 2806 | |
3bacde19 | 2807 | #define HAS_CSR(dev) (INTEL_INFO(dev)->has_csr) |
eb805623 | 2808 | |
1a3d1898 DG |
2809 | /* |
2810 | * For now, anything with a GuC requires uCode loading, and then supports | |
2811 | * command submission once loaded. But these are logically independent | |
2812 | * properties, so we have separate macros to test them. | |
2813 | */ | |
3d810fbe | 2814 | #define HAS_GUC(dev) (INTEL_INFO(dev)->has_guc) |
1a3d1898 DG |
2815 | #define HAS_GUC_UCODE(dev) (HAS_GUC(dev)) |
2816 | #define HAS_GUC_SCHED(dev) (HAS_GUC(dev)) | |
33a732f4 | 2817 | |
53233f08 | 2818 | #define HAS_RESOURCE_STREAMER(dev) (INTEL_INFO(dev)->has_resource_streamer) |
a9ed33ca | 2819 | |
33e141ed | 2820 | #define HAS_POOLED_EU(dev) (INTEL_INFO(dev)->has_pooled_eu) |
2821 | ||
17a303ec PZ |
2822 | #define INTEL_PCH_DEVICE_ID_MASK 0xff00 |
2823 | #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00 | |
2824 | #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00 | |
2825 | #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00 | |
2826 | #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00 | |
2827 | #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00 | |
e7e7ea20 S |
2828 | #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100 |
2829 | #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00 | |
22dea0be | 2830 | #define INTEL_PCH_KBP_DEVICE_ID_TYPE 0xA200 |
30c964a6 | 2831 | #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100 |
1844a66b | 2832 | #define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000 |
39bfcd52 | 2833 | #define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */ |
17a303ec | 2834 | |
f2fbc690 | 2835 | #define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type) |
22dea0be | 2836 | #define HAS_PCH_KBP(dev) (INTEL_PCH_TYPE(dev) == PCH_KBP) |
e7e7ea20 | 2837 | #define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT) |
eb877ebf | 2838 | #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT) |
c2699524 | 2839 | #define HAS_PCH_LPT_LP(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) |
56f5f700 | 2840 | #define HAS_PCH_LPT_H(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) |
cae5852d ZN |
2841 | #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT) |
2842 | #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX) | |
40c7ead9 | 2843 | #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP) |
45e6e3a1 | 2844 | #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE) |
cae5852d | 2845 | |
804b8712 | 2846 | #define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->has_gmch_display) |
5fafe292 | 2847 | |
040d2baa | 2848 | /* DPF == dynamic parity feature */ |
ca9c4523 | 2849 | #define HAS_L3_DPF(dev) (INTEL_INFO(dev)->has_l3_dpf) |
040d2baa | 2850 | #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev)) |
e1ef7cc2 | 2851 | |
c8735b0c | 2852 | #define GT_FREQUENCY_MULTIPLIER 50 |
de43ae9d | 2853 | #define GEN9_FREQ_SCALER 3 |
c8735b0c | 2854 | |
05394f39 CW |
2855 | #include "i915_trace.h" |
2856 | ||
48f112fe CW |
2857 | static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv) |
2858 | { | |
2859 | #ifdef CONFIG_INTEL_IOMMU | |
2860 | if (INTEL_GEN(dev_priv) >= 6 && intel_iommu_gfx_mapped) | |
2861 | return true; | |
2862 | #endif | |
2863 | return false; | |
2864 | } | |
2865 | ||
1751fcf9 ML |
2866 | extern int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state); |
2867 | extern int i915_resume_switcheroo(struct drm_device *dev); | |
7c1c2871 | 2868 | |
c033666a | 2869 | int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv, |
351c3b53 | 2870 | int enable_ppgtt); |
0e4ca100 | 2871 | |
39df9190 CW |
2872 | bool intel_sanitize_semaphores(struct drm_i915_private *dev_priv, int value); |
2873 | ||
0673ad47 | 2874 | /* i915_drv.c */ |
d15d7538 ID |
2875 | void __printf(3, 4) |
2876 | __i915_printk(struct drm_i915_private *dev_priv, const char *level, | |
2877 | const char *fmt, ...); | |
2878 | ||
2879 | #define i915_report_error(dev_priv, fmt, ...) \ | |
2880 | __i915_printk(dev_priv, KERN_ERR, fmt, ##__VA_ARGS__) | |
2881 | ||
c43b5634 | 2882 | #ifdef CONFIG_COMPAT |
0d6aa60b DA |
2883 | extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, |
2884 | unsigned long arg); | |
c43b5634 | 2885 | #endif |
dc97997a CW |
2886 | extern int intel_gpu_reset(struct drm_i915_private *dev_priv, u32 engine_mask); |
2887 | extern bool intel_has_gpu_reset(struct drm_i915_private *dev_priv); | |
780f262a | 2888 | extern void i915_reset(struct drm_i915_private *dev_priv); |
6b332fa2 | 2889 | extern int intel_guc_reset(struct drm_i915_private *dev_priv); |
fc0768ce | 2890 | extern void intel_engine_init_hangcheck(struct intel_engine_cs *engine); |
7648fa99 JB |
2891 | extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv); |
2892 | extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv); | |
2893 | extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv); | |
2894 | extern void i915_update_gfx_val(struct drm_i915_private *dev_priv); | |
650ad970 | 2895 | int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on); |
7648fa99 | 2896 | |
77913b39 | 2897 | /* intel_hotplug.c */ |
91d14251 TU |
2898 | void intel_hpd_irq_handler(struct drm_i915_private *dev_priv, |
2899 | u32 pin_mask, u32 long_mask); | |
77913b39 JN |
2900 | void intel_hpd_init(struct drm_i915_private *dev_priv); |
2901 | void intel_hpd_init_work(struct drm_i915_private *dev_priv); | |
2902 | void intel_hpd_cancel_work(struct drm_i915_private *dev_priv); | |
cc24fcdc | 2903 | bool intel_hpd_pin_to_port(enum hpd_pin pin, enum port *port); |
b236d7c8 L |
2904 | bool intel_hpd_disable(struct drm_i915_private *dev_priv, enum hpd_pin pin); |
2905 | void intel_hpd_enable(struct drm_i915_private *dev_priv, enum hpd_pin pin); | |
77913b39 | 2906 | |
1da177e4 | 2907 | /* i915_irq.c */ |
26a02b8f CW |
2908 | static inline void i915_queue_hangcheck(struct drm_i915_private *dev_priv) |
2909 | { | |
2910 | unsigned long delay; | |
2911 | ||
2912 | if (unlikely(!i915.enable_hangcheck)) | |
2913 | return; | |
2914 | ||
2915 | /* Don't continually defer the hangcheck so that it is always run at | |
2916 | * least once after work has been scheduled on any ring. Otherwise, | |
2917 | * we will ignore a hung ring if a second ring is kept busy. | |
2918 | */ | |
2919 | ||
2920 | delay = round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES); | |
2921 | queue_delayed_work(system_long_wq, | |
2922 | &dev_priv->gpu_error.hangcheck_work, delay); | |
2923 | } | |
2924 | ||
58174462 | 2925 | __printf(3, 4) |
c033666a CW |
2926 | void i915_handle_error(struct drm_i915_private *dev_priv, |
2927 | u32 engine_mask, | |
58174462 | 2928 | const char *fmt, ...); |
1da177e4 | 2929 | |
b963291c | 2930 | extern void intel_irq_init(struct drm_i915_private *dev_priv); |
2aeb7d3a DV |
2931 | int intel_irq_install(struct drm_i915_private *dev_priv); |
2932 | void intel_irq_uninstall(struct drm_i915_private *dev_priv); | |
907b28c5 | 2933 | |
dc97997a CW |
2934 | extern void intel_uncore_sanitize(struct drm_i915_private *dev_priv); |
2935 | extern void intel_uncore_early_sanitize(struct drm_i915_private *dev_priv, | |
10018603 | 2936 | bool restore_forcewake); |
dc97997a | 2937 | extern void intel_uncore_init(struct drm_i915_private *dev_priv); |
fc97618b | 2938 | extern bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv); |
bc3b9346 | 2939 | extern bool intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv); |
dc97997a CW |
2940 | extern void intel_uncore_fini(struct drm_i915_private *dev_priv); |
2941 | extern void intel_uncore_forcewake_reset(struct drm_i915_private *dev_priv, | |
2942 | bool restore); | |
48c1026a | 2943 | const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id); |
59bad947 | 2944 | void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv, |
48c1026a | 2945 | enum forcewake_domains domains); |
59bad947 | 2946 | void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv, |
48c1026a | 2947 | enum forcewake_domains domains); |
a6111f7b CW |
2948 | /* Like above but the caller must manage the uncore.lock itself. |
2949 | * Must be used with I915_READ_FW and friends. | |
2950 | */ | |
2951 | void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv, | |
2952 | enum forcewake_domains domains); | |
2953 | void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv, | |
2954 | enum forcewake_domains domains); | |
3accaf7e MK |
2955 | u64 intel_uncore_edram_size(struct drm_i915_private *dev_priv); |
2956 | ||
59bad947 | 2957 | void assert_forcewakes_inactive(struct drm_i915_private *dev_priv); |
0ad35fed | 2958 | |
1758b90e CW |
2959 | int intel_wait_for_register(struct drm_i915_private *dev_priv, |
2960 | i915_reg_t reg, | |
2961 | const u32 mask, | |
2962 | const u32 value, | |
2963 | const unsigned long timeout_ms); | |
2964 | int intel_wait_for_register_fw(struct drm_i915_private *dev_priv, | |
2965 | i915_reg_t reg, | |
2966 | const u32 mask, | |
2967 | const u32 value, | |
2968 | const unsigned long timeout_ms); | |
2969 | ||
0ad35fed ZW |
2970 | static inline bool intel_gvt_active(struct drm_i915_private *dev_priv) |
2971 | { | |
2972 | return dev_priv->gvt.initialized; | |
2973 | } | |
2974 | ||
c033666a | 2975 | static inline bool intel_vgpu_active(struct drm_i915_private *dev_priv) |
cf9d2890 | 2976 | { |
c033666a | 2977 | return dev_priv->vgpu.active; |
cf9d2890 | 2978 | } |
b1f14ad0 | 2979 | |
7c463586 | 2980 | void |
50227e1c | 2981 | i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, |
755e9019 | 2982 | u32 status_mask); |
7c463586 KP |
2983 | |
2984 | void | |
50227e1c | 2985 | i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, |
755e9019 | 2986 | u32 status_mask); |
7c463586 | 2987 | |
f8b79e58 ID |
2988 | void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv); |
2989 | void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv); | |
0706f17c EE |
2990 | void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv, |
2991 | uint32_t mask, | |
2992 | uint32_t bits); | |
fbdedaea VS |
2993 | void ilk_update_display_irq(struct drm_i915_private *dev_priv, |
2994 | uint32_t interrupt_mask, | |
2995 | uint32_t enabled_irq_mask); | |
2996 | static inline void | |
2997 | ilk_enable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits) | |
2998 | { | |
2999 | ilk_update_display_irq(dev_priv, bits, bits); | |
3000 | } | |
3001 | static inline void | |
3002 | ilk_disable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits) | |
3003 | { | |
3004 | ilk_update_display_irq(dev_priv, bits, 0); | |
3005 | } | |
013d3752 VS |
3006 | void bdw_update_pipe_irq(struct drm_i915_private *dev_priv, |
3007 | enum pipe pipe, | |
3008 | uint32_t interrupt_mask, | |
3009 | uint32_t enabled_irq_mask); | |
3010 | static inline void bdw_enable_pipe_irq(struct drm_i915_private *dev_priv, | |
3011 | enum pipe pipe, uint32_t bits) | |
3012 | { | |
3013 | bdw_update_pipe_irq(dev_priv, pipe, bits, bits); | |
3014 | } | |
3015 | static inline void bdw_disable_pipe_irq(struct drm_i915_private *dev_priv, | |
3016 | enum pipe pipe, uint32_t bits) | |
3017 | { | |
3018 | bdw_update_pipe_irq(dev_priv, pipe, bits, 0); | |
3019 | } | |
47339cd9 DV |
3020 | void ibx_display_interrupt_update(struct drm_i915_private *dev_priv, |
3021 | uint32_t interrupt_mask, | |
3022 | uint32_t enabled_irq_mask); | |
14443261 VS |
3023 | static inline void |
3024 | ibx_enable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits) | |
3025 | { | |
3026 | ibx_display_interrupt_update(dev_priv, bits, bits); | |
3027 | } | |
3028 | static inline void | |
3029 | ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits) | |
3030 | { | |
3031 | ibx_display_interrupt_update(dev_priv, bits, 0); | |
3032 | } | |
3033 | ||
673a394b | 3034 | /* i915_gem.c */ |
673a394b EA |
3035 | int i915_gem_create_ioctl(struct drm_device *dev, void *data, |
3036 | struct drm_file *file_priv); | |
3037 | int i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
3038 | struct drm_file *file_priv); | |
3039 | int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
3040 | struct drm_file *file_priv); | |
3041 | int i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
3042 | struct drm_file *file_priv); | |
de151cf6 JB |
3043 | int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, |
3044 | struct drm_file *file_priv); | |
673a394b EA |
3045 | int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, |
3046 | struct drm_file *file_priv); | |
3047 | int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
3048 | struct drm_file *file_priv); | |
3049 | int i915_gem_execbuffer(struct drm_device *dev, void *data, | |
3050 | struct drm_file *file_priv); | |
76446cac JB |
3051 | int i915_gem_execbuffer2(struct drm_device *dev, void *data, |
3052 | struct drm_file *file_priv); | |
673a394b EA |
3053 | int i915_gem_busy_ioctl(struct drm_device *dev, void *data, |
3054 | struct drm_file *file_priv); | |
199adf40 BW |
3055 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, |
3056 | struct drm_file *file); | |
3057 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, | |
3058 | struct drm_file *file); | |
673a394b EA |
3059 | int i915_gem_throttle_ioctl(struct drm_device *dev, void *data, |
3060 | struct drm_file *file_priv); | |
3ef94daa CW |
3061 | int i915_gem_madvise_ioctl(struct drm_device *dev, void *data, |
3062 | struct drm_file *file_priv); | |
673a394b EA |
3063 | int i915_gem_set_tiling(struct drm_device *dev, void *data, |
3064 | struct drm_file *file_priv); | |
3065 | int i915_gem_get_tiling(struct drm_device *dev, void *data, | |
3066 | struct drm_file *file_priv); | |
72778cb2 | 3067 | void i915_gem_init_userptr(struct drm_i915_private *dev_priv); |
5cc9ed4b CW |
3068 | int i915_gem_userptr_ioctl(struct drm_device *dev, void *data, |
3069 | struct drm_file *file); | |
5a125c3c EA |
3070 | int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, |
3071 | struct drm_file *file_priv); | |
23ba4fd0 BW |
3072 | int i915_gem_wait_ioctl(struct drm_device *dev, void *data, |
3073 | struct drm_file *file_priv); | |
d64aa096 ID |
3074 | void i915_gem_load_init(struct drm_device *dev); |
3075 | void i915_gem_load_cleanup(struct drm_device *dev); | |
40ae4e16 | 3076 | void i915_gem_load_init_fences(struct drm_i915_private *dev_priv); |
461fb99c CW |
3077 | int i915_gem_freeze_late(struct drm_i915_private *dev_priv); |
3078 | ||
42dcedd4 CW |
3079 | void *i915_gem_object_alloc(struct drm_device *dev); |
3080 | void i915_gem_object_free(struct drm_i915_gem_object *obj); | |
37e680a1 CW |
3081 | void i915_gem_object_init(struct drm_i915_gem_object *obj, |
3082 | const struct drm_i915_gem_object_ops *ops); | |
d37cd8a8 | 3083 | struct drm_i915_gem_object *i915_gem_object_create(struct drm_device *dev, |
05394f39 | 3084 | size_t size); |
ea70299d DG |
3085 | struct drm_i915_gem_object *i915_gem_object_create_from_data( |
3086 | struct drm_device *dev, const void *data, size_t size); | |
b1f788c6 | 3087 | void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file); |
673a394b | 3088 | void i915_gem_free_object(struct drm_gem_object *obj); |
42dcedd4 | 3089 | |
058d88c4 | 3090 | struct i915_vma * __must_check |
ec7adb6e JL |
3091 | i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj, |
3092 | const struct i915_ggtt_view *view, | |
91b2db6f | 3093 | u64 size, |
2ffffd0f CW |
3094 | u64 alignment, |
3095 | u64 flags); | |
fe14d5f4 TU |
3096 | |
3097 | int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level, | |
3098 | u32 flags); | |
d0710abb | 3099 | void __i915_vma_set_map_and_fenceable(struct i915_vma *vma); |
07fe0b12 | 3100 | int __must_check i915_vma_unbind(struct i915_vma *vma); |
b1f788c6 CW |
3101 | void i915_vma_close(struct i915_vma *vma); |
3102 | void i915_vma_destroy(struct i915_vma *vma); | |
aa653a68 CW |
3103 | |
3104 | int i915_gem_object_unbind(struct drm_i915_gem_object *obj); | |
dd624afd | 3105 | int i915_gem_object_put_pages(struct drm_i915_gem_object *obj); |
48018a57 | 3106 | void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv); |
05394f39 | 3107 | void i915_gem_release_mmap(struct drm_i915_gem_object *obj); |
f787a5f5 | 3108 | |
37e680a1 | 3109 | int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj); |
ee286370 CW |
3110 | |
3111 | static inline int __sg_page_count(struct scatterlist *sg) | |
9da3da66 | 3112 | { |
ee286370 CW |
3113 | return sg->length >> PAGE_SHIFT; |
3114 | } | |
67d5a50c | 3115 | |
033908ae DG |
3116 | struct page * |
3117 | i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj, int n); | |
3118 | ||
341be1cd CW |
3119 | static inline dma_addr_t |
3120 | i915_gem_object_get_dma_address(struct drm_i915_gem_object *obj, int n) | |
3121 | { | |
3122 | if (n < obj->get_page.last) { | |
3123 | obj->get_page.sg = obj->pages->sgl; | |
3124 | obj->get_page.last = 0; | |
3125 | } | |
3126 | ||
3127 | while (obj->get_page.last + __sg_page_count(obj->get_page.sg) <= n) { | |
3128 | obj->get_page.last += __sg_page_count(obj->get_page.sg++); | |
3129 | if (unlikely(sg_is_chain(obj->get_page.sg))) | |
3130 | obj->get_page.sg = sg_chain_ptr(obj->get_page.sg); | |
3131 | } | |
3132 | ||
3133 | return sg_dma_address(obj->get_page.sg) + ((n - obj->get_page.last) << PAGE_SHIFT); | |
3134 | } | |
3135 | ||
ee286370 CW |
3136 | static inline struct page * |
3137 | i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n) | |
9da3da66 | 3138 | { |
ee286370 CW |
3139 | if (WARN_ON(n >= obj->base.size >> PAGE_SHIFT)) |
3140 | return NULL; | |
67d5a50c | 3141 | |
ee286370 CW |
3142 | if (n < obj->get_page.last) { |
3143 | obj->get_page.sg = obj->pages->sgl; | |
3144 | obj->get_page.last = 0; | |
3145 | } | |
67d5a50c | 3146 | |
ee286370 CW |
3147 | while (obj->get_page.last + __sg_page_count(obj->get_page.sg) <= n) { |
3148 | obj->get_page.last += __sg_page_count(obj->get_page.sg++); | |
3149 | if (unlikely(sg_is_chain(obj->get_page.sg))) | |
3150 | obj->get_page.sg = sg_chain_ptr(obj->get_page.sg); | |
3151 | } | |
67d5a50c | 3152 | |
ee286370 | 3153 | return nth_page(sg_page(obj->get_page.sg), n - obj->get_page.last); |
9da3da66 | 3154 | } |
ee286370 | 3155 | |
a5570178 CW |
3156 | static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj) |
3157 | { | |
3158 | BUG_ON(obj->pages == NULL); | |
3159 | obj->pages_pin_count++; | |
3160 | } | |
0a798eb9 | 3161 | |
a5570178 CW |
3162 | static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj) |
3163 | { | |
3164 | BUG_ON(obj->pages_pin_count == 0); | |
3165 | obj->pages_pin_count--; | |
3166 | } | |
3167 | ||
d31d7cb1 CW |
3168 | enum i915_map_type { |
3169 | I915_MAP_WB = 0, | |
3170 | I915_MAP_WC, | |
3171 | }; | |
3172 | ||
0a798eb9 CW |
3173 | /** |
3174 | * i915_gem_object_pin_map - return a contiguous mapping of the entire object | |
3175 | * @obj - the object to map into kernel address space | |
d31d7cb1 | 3176 | * @type - the type of mapping, used to select pgprot_t |
0a798eb9 CW |
3177 | * |
3178 | * Calls i915_gem_object_pin_pages() to prevent reaping of the object's | |
3179 | * pages and then returns a contiguous mapping of the backing storage into | |
d31d7cb1 CW |
3180 | * the kernel address space. Based on the @type of mapping, the PTE will be |
3181 | * set to either WriteBack or WriteCombine (via pgprot_t). | |
0a798eb9 | 3182 | * |
8305216f DG |
3183 | * The caller must hold the struct_mutex, and is responsible for calling |
3184 | * i915_gem_object_unpin_map() when the mapping is no longer required. | |
0a798eb9 | 3185 | * |
8305216f DG |
3186 | * Returns the pointer through which to access the mapped object, or an |
3187 | * ERR_PTR() on error. | |
0a798eb9 | 3188 | */ |
d31d7cb1 CW |
3189 | void *__must_check i915_gem_object_pin_map(struct drm_i915_gem_object *obj, |
3190 | enum i915_map_type type); | |
0a798eb9 CW |
3191 | |
3192 | /** | |
3193 | * i915_gem_object_unpin_map - releases an earlier mapping | |
3194 | * @obj - the object to unmap | |
3195 | * | |
3196 | * After pinning the object and mapping its pages, once you are finished | |
3197 | * with your access, call i915_gem_object_unpin_map() to release the pin | |
3198 | * upon the mapping. Once the pin count reaches zero, that mapping may be | |
3199 | * removed. | |
3200 | * | |
3201 | * The caller must hold the struct_mutex. | |
3202 | */ | |
3203 | static inline void i915_gem_object_unpin_map(struct drm_i915_gem_object *obj) | |
3204 | { | |
3205 | lockdep_assert_held(&obj->base.dev->struct_mutex); | |
3206 | i915_gem_object_unpin_pages(obj); | |
3207 | } | |
3208 | ||
43394c7d CW |
3209 | int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj, |
3210 | unsigned int *needs_clflush); | |
3211 | int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object *obj, | |
3212 | unsigned int *needs_clflush); | |
3213 | #define CLFLUSH_BEFORE 0x1 | |
3214 | #define CLFLUSH_AFTER 0x2 | |
3215 | #define CLFLUSH_FLAGS (CLFLUSH_BEFORE | CLFLUSH_AFTER) | |
3216 | ||
3217 | static inline void | |
3218 | i915_gem_obj_finish_shmem_access(struct drm_i915_gem_object *obj) | |
3219 | { | |
3220 | i915_gem_object_unpin_pages(obj); | |
3221 | } | |
3222 | ||
54cf91dc | 3223 | int __must_check i915_mutex_lock_interruptible(struct drm_device *dev); |
e2d05a8b | 3224 | void i915_vma_move_to_active(struct i915_vma *vma, |
5cf3d280 CW |
3225 | struct drm_i915_gem_request *req, |
3226 | unsigned int flags); | |
ff72145b DA |
3227 | int i915_gem_dumb_create(struct drm_file *file_priv, |
3228 | struct drm_device *dev, | |
3229 | struct drm_mode_create_dumb *args); | |
da6b51d0 DA |
3230 | int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev, |
3231 | uint32_t handle, uint64_t *offset); | |
4cc69075 | 3232 | int i915_gem_mmap_gtt_version(void); |
85d1225e DG |
3233 | |
3234 | void i915_gem_track_fb(struct drm_i915_gem_object *old, | |
3235 | struct drm_i915_gem_object *new, | |
3236 | unsigned frontbuffer_bits); | |
3237 | ||
fca26bb4 | 3238 | int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno); |
1690e1eb | 3239 | |
8d9fc7fd | 3240 | struct drm_i915_gem_request * |
0bc40be8 | 3241 | i915_gem_find_active_request(struct intel_engine_cs *engine); |
8d9fc7fd | 3242 | |
67d97da3 | 3243 | void i915_gem_retire_requests(struct drm_i915_private *dev_priv); |
84c33a64 | 3244 | |
1f83fee0 DV |
3245 | static inline bool i915_reset_in_progress(struct i915_gpu_error *error) |
3246 | { | |
8af29b0c | 3247 | return unlikely(test_bit(I915_RESET_IN_PROGRESS, &error->flags)); |
c19ae989 CW |
3248 | } |
3249 | ||
8af29b0c | 3250 | static inline bool i915_terminally_wedged(struct i915_gpu_error *error) |
c19ae989 | 3251 | { |
8af29b0c | 3252 | return unlikely(test_bit(I915_WEDGED, &error->flags)); |
1f83fee0 DV |
3253 | } |
3254 | ||
8af29b0c | 3255 | static inline bool i915_reset_in_progress_or_wedged(struct i915_gpu_error *error) |
1f83fee0 | 3256 | { |
8af29b0c | 3257 | return i915_reset_in_progress(error) | i915_terminally_wedged(error); |
2ac0f450 MK |
3258 | } |
3259 | ||
3260 | static inline u32 i915_reset_count(struct i915_gpu_error *error) | |
3261 | { | |
8af29b0c | 3262 | return READ_ONCE(error->reset_count); |
1f83fee0 | 3263 | } |
a71d8d94 | 3264 | |
821ed7df CW |
3265 | void i915_gem_reset(struct drm_i915_private *dev_priv); |
3266 | void i915_gem_set_wedged(struct drm_i915_private *dev_priv); | |
000433b6 | 3267 | bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force); |
1070a42b | 3268 | int __must_check i915_gem_init(struct drm_device *dev); |
f691e2f4 DV |
3269 | int __must_check i915_gem_init_hw(struct drm_device *dev); |
3270 | void i915_gem_init_swizzling(struct drm_device *dev); | |
117897f4 | 3271 | void i915_gem_cleanup_engines(struct drm_device *dev); |
dcff85c8 | 3272 | int __must_check i915_gem_wait_for_idle(struct drm_i915_private *dev_priv, |
ea746f36 | 3273 | unsigned int flags); |
45c5f202 | 3274 | int __must_check i915_gem_suspend(struct drm_device *dev); |
5ab57c70 | 3275 | void i915_gem_resume(struct drm_device *dev); |
de151cf6 | 3276 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf); |
2021746e | 3277 | int __must_check |
2e2f351d CW |
3278 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, |
3279 | bool readonly); | |
3280 | int __must_check | |
2021746e CW |
3281 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, |
3282 | bool write); | |
3283 | int __must_check | |
dabdfe02 | 3284 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write); |
058d88c4 | 3285 | struct i915_vma * __must_check |
2da3b9b9 CW |
3286 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
3287 | u32 alignment, | |
e6617330 | 3288 | const struct i915_ggtt_view *view); |
058d88c4 | 3289 | void i915_gem_object_unpin_from_display_plane(struct i915_vma *vma); |
00731155 | 3290 | int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj, |
6eeefaf3 | 3291 | int align); |
b29c19b6 | 3292 | int i915_gem_open(struct drm_device *dev, struct drm_file *file); |
05394f39 | 3293 | void i915_gem_release(struct drm_device *dev, struct drm_file *file); |
673a394b | 3294 | |
a9f1481f CW |
3295 | u64 i915_gem_get_ggtt_size(struct drm_i915_private *dev_priv, u64 size, |
3296 | int tiling_mode); | |
3297 | u64 i915_gem_get_ggtt_alignment(struct drm_i915_private *dev_priv, u64 size, | |
ad1a7d20 | 3298 | int tiling_mode, bool fenced); |
467cffba | 3299 | |
e4ffd173 CW |
3300 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
3301 | enum i915_cache_level cache_level); | |
3302 | ||
1286ff73 DV |
3303 | struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev, |
3304 | struct dma_buf *dma_buf); | |
3305 | ||
3306 | struct dma_buf *i915_gem_prime_export(struct drm_device *dev, | |
3307 | struct drm_gem_object *gem_obj, int flags); | |
3308 | ||
fe14d5f4 | 3309 | struct i915_vma * |
ec7adb6e | 3310 | i915_gem_obj_to_vma(struct drm_i915_gem_object *obj, |
058d88c4 CW |
3311 | struct i915_address_space *vm, |
3312 | const struct i915_ggtt_view *view); | |
fe14d5f4 | 3313 | |
accfef2e BW |
3314 | struct i915_vma * |
3315 | i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj, | |
058d88c4 CW |
3316 | struct i915_address_space *vm, |
3317 | const struct i915_ggtt_view *view); | |
5c2abbea | 3318 | |
841cd773 DV |
3319 | static inline struct i915_hw_ppgtt * |
3320 | i915_vm_to_ppgtt(struct i915_address_space *vm) | |
3321 | { | |
841cd773 DV |
3322 | return container_of(vm, struct i915_hw_ppgtt, base); |
3323 | } | |
3324 | ||
058d88c4 CW |
3325 | static inline struct i915_vma * |
3326 | i915_gem_object_to_ggtt(struct drm_i915_gem_object *obj, | |
3327 | const struct i915_ggtt_view *view) | |
a70a3148 | 3328 | { |
058d88c4 | 3329 | return i915_gem_obj_to_vma(obj, &to_i915(obj->base.dev)->ggtt.base, view); |
a70a3148 BW |
3330 | } |
3331 | ||
058d88c4 CW |
3332 | static inline unsigned long |
3333 | i915_gem_object_ggtt_offset(struct drm_i915_gem_object *o, | |
3334 | const struct i915_ggtt_view *view) | |
e6617330 | 3335 | { |
bde13ebd | 3336 | return i915_ggtt_offset(i915_gem_object_to_ggtt(o, view)); |
e6617330 | 3337 | } |
b287110e | 3338 | |
41a36b73 | 3339 | /* i915_gem_fence.c */ |
49ef5294 CW |
3340 | int __must_check i915_vma_get_fence(struct i915_vma *vma); |
3341 | int __must_check i915_vma_put_fence(struct i915_vma *vma); | |
3342 | ||
3343 | /** | |
3344 | * i915_vma_pin_fence - pin fencing state | |
3345 | * @vma: vma to pin fencing for | |
3346 | * | |
3347 | * This pins the fencing state (whether tiled or untiled) to make sure the | |
3348 | * vma (and its object) is ready to be used as a scanout target. Fencing | |
3349 | * status must be synchronize first by calling i915_vma_get_fence(): | |
3350 | * | |
3351 | * The resulting fence pin reference must be released again with | |
3352 | * i915_vma_unpin_fence(). | |
3353 | * | |
3354 | * Returns: | |
3355 | * | |
3356 | * True if the vma has a fence, false otherwise. | |
3357 | */ | |
3358 | static inline bool | |
3359 | i915_vma_pin_fence(struct i915_vma *vma) | |
3360 | { | |
3361 | if (vma->fence) { | |
3362 | vma->fence->pin_count++; | |
3363 | return true; | |
3364 | } else | |
3365 | return false; | |
3366 | } | |
41a36b73 | 3367 | |
49ef5294 CW |
3368 | /** |
3369 | * i915_vma_unpin_fence - unpin fencing state | |
3370 | * @vma: vma to unpin fencing for | |
3371 | * | |
3372 | * This releases the fence pin reference acquired through | |
3373 | * i915_vma_pin_fence. It will handle both objects with and without an | |
3374 | * attached fence correctly, callers do not need to distinguish this. | |
3375 | */ | |
3376 | static inline void | |
3377 | i915_vma_unpin_fence(struct i915_vma *vma) | |
3378 | { | |
3379 | if (vma->fence) { | |
3380 | GEM_BUG_ON(vma->fence->pin_count <= 0); | |
3381 | vma->fence->pin_count--; | |
3382 | } | |
3383 | } | |
41a36b73 DV |
3384 | |
3385 | void i915_gem_restore_fences(struct drm_device *dev); | |
3386 | ||
7f96ecaf DV |
3387 | void i915_gem_detect_bit_6_swizzle(struct drm_device *dev); |
3388 | void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj); | |
3389 | void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj); | |
3390 | ||
254f965c | 3391 | /* i915_gem_context.c */ |
8245be31 | 3392 | int __must_check i915_gem_context_init(struct drm_device *dev); |
b2e862d0 | 3393 | void i915_gem_context_lost(struct drm_i915_private *dev_priv); |
254f965c | 3394 | void i915_gem_context_fini(struct drm_device *dev); |
e422b888 | 3395 | int i915_gem_context_open(struct drm_device *dev, struct drm_file *file); |
254f965c | 3396 | void i915_gem_context_close(struct drm_device *dev, struct drm_file *file); |
ba01cc93 | 3397 | int i915_switch_context(struct drm_i915_gem_request *req); |
945657b4 | 3398 | int i915_gem_switch_to_kernel_context(struct drm_i915_private *dev_priv); |
dce3271b | 3399 | void i915_gem_context_free(struct kref *ctx_ref); |
8c857917 OM |
3400 | struct drm_i915_gem_object * |
3401 | i915_gem_alloc_context_obj(struct drm_device *dev, size_t size); | |
c8c35799 ZW |
3402 | struct i915_gem_context * |
3403 | i915_gem_context_create_gvt(struct drm_device *dev); | |
ca585b5d CW |
3404 | |
3405 | static inline struct i915_gem_context * | |
3406 | i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id) | |
3407 | { | |
3408 | struct i915_gem_context *ctx; | |
3409 | ||
091387c1 | 3410 | lockdep_assert_held(&file_priv->dev_priv->drm.struct_mutex); |
ca585b5d CW |
3411 | |
3412 | ctx = idr_find(&file_priv->context_idr, id); | |
3413 | if (!ctx) | |
3414 | return ERR_PTR(-ENOENT); | |
3415 | ||
3416 | return ctx; | |
3417 | } | |
3418 | ||
9a6feaf0 CW |
3419 | static inline struct i915_gem_context * |
3420 | i915_gem_context_get(struct i915_gem_context *ctx) | |
dce3271b | 3421 | { |
691e6415 | 3422 | kref_get(&ctx->ref); |
9a6feaf0 | 3423 | return ctx; |
dce3271b MK |
3424 | } |
3425 | ||
9a6feaf0 | 3426 | static inline void i915_gem_context_put(struct i915_gem_context *ctx) |
dce3271b | 3427 | { |
091387c1 | 3428 | lockdep_assert_held(&ctx->i915->drm.struct_mutex); |
691e6415 | 3429 | kref_put(&ctx->ref, i915_gem_context_free); |
dce3271b MK |
3430 | } |
3431 | ||
e2efd130 | 3432 | static inline bool i915_gem_context_is_default(const struct i915_gem_context *c) |
3fac8978 | 3433 | { |
821d66dd | 3434 | return c->user_handle == DEFAULT_CONTEXT_HANDLE; |
3fac8978 MK |
3435 | } |
3436 | ||
84624813 BW |
3437 | int i915_gem_context_create_ioctl(struct drm_device *dev, void *data, |
3438 | struct drm_file *file); | |
3439 | int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data, | |
3440 | struct drm_file *file); | |
c9dc0f35 CW |
3441 | int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data, |
3442 | struct drm_file *file_priv); | |
3443 | int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data, | |
3444 | struct drm_file *file_priv); | |
d538704b CW |
3445 | int i915_gem_context_reset_stats_ioctl(struct drm_device *dev, void *data, |
3446 | struct drm_file *file); | |
1286ff73 | 3447 | |
679845ed | 3448 | /* i915_gem_evict.c */ |
e522ac23 | 3449 | int __must_check i915_gem_evict_something(struct i915_address_space *vm, |
2ffffd0f | 3450 | u64 min_size, u64 alignment, |
679845ed | 3451 | unsigned cache_level, |
2ffffd0f | 3452 | u64 start, u64 end, |
1ec9e26d | 3453 | unsigned flags); |
506a8e87 | 3454 | int __must_check i915_gem_evict_for_vma(struct i915_vma *target); |
679845ed | 3455 | int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle); |
1d2a314c | 3456 | |
0260c420 | 3457 | /* belongs in i915_gem_gtt.h */ |
c033666a | 3458 | static inline void i915_gem_chipset_flush(struct drm_i915_private *dev_priv) |
e76e9aeb | 3459 | { |
600f4368 | 3460 | wmb(); |
c033666a | 3461 | if (INTEL_GEN(dev_priv) < 6) |
e76e9aeb BW |
3462 | intel_gtt_chipset_flush(); |
3463 | } | |
246cbfb5 | 3464 | |
9797fbfb | 3465 | /* i915_gem_stolen.c */ |
d713fd49 PZ |
3466 | int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv, |
3467 | struct drm_mm_node *node, u64 size, | |
3468 | unsigned alignment); | |
a9da512b PZ |
3469 | int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv, |
3470 | struct drm_mm_node *node, u64 size, | |
3471 | unsigned alignment, u64 start, | |
3472 | u64 end); | |
d713fd49 PZ |
3473 | void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv, |
3474 | struct drm_mm_node *node); | |
9797fbfb CW |
3475 | int i915_gem_init_stolen(struct drm_device *dev); |
3476 | void i915_gem_cleanup_stolen(struct drm_device *dev); | |
0104fdbb CW |
3477 | struct drm_i915_gem_object * |
3478 | i915_gem_object_create_stolen(struct drm_device *dev, u32 size); | |
866d12b4 CW |
3479 | struct drm_i915_gem_object * |
3480 | i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev, | |
3481 | u32 stolen_offset, | |
3482 | u32 gtt_offset, | |
3483 | u32 size); | |
9797fbfb | 3484 | |
be6a0376 DV |
3485 | /* i915_gem_shrinker.c */ |
3486 | unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv, | |
14387540 | 3487 | unsigned long target, |
be6a0376 DV |
3488 | unsigned flags); |
3489 | #define I915_SHRINK_PURGEABLE 0x1 | |
3490 | #define I915_SHRINK_UNBOUND 0x2 | |
3491 | #define I915_SHRINK_BOUND 0x4 | |
5763ff04 | 3492 | #define I915_SHRINK_ACTIVE 0x8 |
eae2c43b | 3493 | #define I915_SHRINK_VMAPS 0x10 |
be6a0376 DV |
3494 | unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv); |
3495 | void i915_gem_shrinker_init(struct drm_i915_private *dev_priv); | |
a8a40589 | 3496 | void i915_gem_shrinker_cleanup(struct drm_i915_private *dev_priv); |
be6a0376 DV |
3497 | |
3498 | ||
673a394b | 3499 | /* i915_gem_tiling.c */ |
2c1792a1 | 3500 | static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj) |
e9b73c67 | 3501 | { |
091387c1 | 3502 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
e9b73c67 CW |
3503 | |
3504 | return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && | |
3e510a8e | 3505 | i915_gem_object_is_tiled(obj); |
e9b73c67 CW |
3506 | } |
3507 | ||
2017263e | 3508 | /* i915_debugfs.c */ |
f8c168fa | 3509 | #ifdef CONFIG_DEBUG_FS |
1dac891c CW |
3510 | int i915_debugfs_register(struct drm_i915_private *dev_priv); |
3511 | void i915_debugfs_unregister(struct drm_i915_private *dev_priv); | |
249e87de | 3512 | int i915_debugfs_connector_add(struct drm_connector *connector); |
36cdd013 | 3513 | void intel_display_crc_init(struct drm_i915_private *dev_priv); |
07144428 | 3514 | #else |
8d35acba CW |
3515 | static inline int i915_debugfs_register(struct drm_i915_private *dev_priv) {return 0;} |
3516 | static inline void i915_debugfs_unregister(struct drm_i915_private *dev_priv) {} | |
101057fa DV |
3517 | static inline int i915_debugfs_connector_add(struct drm_connector *connector) |
3518 | { return 0; } | |
ce5e2ac1 | 3519 | static inline void intel_display_crc_init(struct drm_i915_private *dev_priv) {} |
07144428 | 3520 | #endif |
84734a04 MK |
3521 | |
3522 | /* i915_gpu_error.c */ | |
edc3d884 MK |
3523 | __printf(2, 3) |
3524 | void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...); | |
fc16b48b MK |
3525 | int i915_error_state_to_str(struct drm_i915_error_state_buf *estr, |
3526 | const struct i915_error_state_file_priv *error); | |
4dc955f7 | 3527 | int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb, |
0a4cd7c8 | 3528 | struct drm_i915_private *i915, |
4dc955f7 MK |
3529 | size_t count, loff_t pos); |
3530 | static inline void i915_error_state_buf_release( | |
3531 | struct drm_i915_error_state_buf *eb) | |
3532 | { | |
3533 | kfree(eb->buf); | |
3534 | } | |
c033666a CW |
3535 | void i915_capture_error_state(struct drm_i915_private *dev_priv, |
3536 | u32 engine_mask, | |
58174462 | 3537 | const char *error_msg); |
84734a04 MK |
3538 | void i915_error_state_get(struct drm_device *dev, |
3539 | struct i915_error_state_file_priv *error_priv); | |
3540 | void i915_error_state_put(struct i915_error_state_file_priv *error_priv); | |
3541 | void i915_destroy_error_state(struct drm_device *dev); | |
3542 | ||
c033666a | 3543 | void i915_get_extra_instdone(struct drm_i915_private *dev_priv, uint32_t *instdone); |
0a4cd7c8 | 3544 | const char *i915_cache_level_str(struct drm_i915_private *i915, int type); |
2017263e | 3545 | |
351e3db2 | 3546 | /* i915_cmd_parser.c */ |
1ca3712c | 3547 | int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv); |
7756e454 | 3548 | void intel_engine_init_cmd_parser(struct intel_engine_cs *engine); |
33a051a5 CW |
3549 | void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine); |
3550 | bool intel_engine_needs_cmd_parser(struct intel_engine_cs *engine); | |
3551 | int intel_engine_cmd_parser(struct intel_engine_cs *engine, | |
3552 | struct drm_i915_gem_object *batch_obj, | |
3553 | struct drm_i915_gem_object *shadow_batch_obj, | |
3554 | u32 batch_start_offset, | |
3555 | u32 batch_len, | |
3556 | bool is_master); | |
351e3db2 | 3557 | |
317c35d1 JB |
3558 | /* i915_suspend.c */ |
3559 | extern int i915_save_state(struct drm_device *dev); | |
3560 | extern int i915_restore_state(struct drm_device *dev); | |
0a3e67a4 | 3561 | |
0136db58 | 3562 | /* i915_sysfs.c */ |
694c2828 DW |
3563 | void i915_setup_sysfs(struct drm_i915_private *dev_priv); |
3564 | void i915_teardown_sysfs(struct drm_i915_private *dev_priv); | |
0136db58 | 3565 | |
f899fc64 CW |
3566 | /* intel_i2c.c */ |
3567 | extern int intel_setup_gmbus(struct drm_device *dev); | |
3568 | extern void intel_teardown_gmbus(struct drm_device *dev); | |
88ac7939 JN |
3569 | extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv, |
3570 | unsigned int pin); | |
3bd7d909 | 3571 | |
0184df46 JN |
3572 | extern struct i2c_adapter * |
3573 | intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin); | |
e957d772 CW |
3574 | extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed); |
3575 | extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit); | |
8f375e10 | 3576 | static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter) |
b8232e90 CW |
3577 | { |
3578 | return container_of(adapter, struct intel_gmbus, adapter)->force_bit; | |
3579 | } | |
f899fc64 CW |
3580 | extern void intel_i2c_reset(struct drm_device *dev); |
3581 | ||
8b8e1a89 | 3582 | /* intel_bios.c */ |
98f3a1dc | 3583 | int intel_bios_init(struct drm_i915_private *dev_priv); |
f0067a31 | 3584 | bool intel_bios_is_valid_vbt(const void *buf, size_t size); |
3bdd14d5 | 3585 | bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv); |
5a69d13d | 3586 | bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8 *i2c_pin); |
22f35042 | 3587 | bool intel_bios_is_port_present(struct drm_i915_private *dev_priv, enum port port); |
951d9efe | 3588 | bool intel_bios_is_port_edp(struct drm_i915_private *dev_priv, enum port port); |
d6199256 | 3589 | bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private *dev_priv, enum port port); |
7137aec1 | 3590 | bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv, enum port *port); |
d252bf68 SS |
3591 | bool intel_bios_is_port_hpd_inverted(struct drm_i915_private *dev_priv, |
3592 | enum port port); | |
8b8e1a89 | 3593 | |
3b617967 | 3594 | /* intel_opregion.c */ |
44834a67 | 3595 | #ifdef CONFIG_ACPI |
6f9f4b7a | 3596 | extern int intel_opregion_setup(struct drm_i915_private *dev_priv); |
03d92e47 CW |
3597 | extern void intel_opregion_register(struct drm_i915_private *dev_priv); |
3598 | extern void intel_opregion_unregister(struct drm_i915_private *dev_priv); | |
91d14251 | 3599 | extern void intel_opregion_asle_intr(struct drm_i915_private *dev_priv); |
9c4b0a68 JN |
3600 | extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, |
3601 | bool enable); | |
6f9f4b7a | 3602 | extern int intel_opregion_notify_adapter(struct drm_i915_private *dev_priv, |
ecbc5cf3 | 3603 | pci_power_t state); |
6f9f4b7a | 3604 | extern int intel_opregion_get_panel_type(struct drm_i915_private *dev_priv); |
65e082c9 | 3605 | #else |
6f9f4b7a | 3606 | static inline int intel_opregion_setup(struct drm_i915_private *dev) { return 0; } |
bdaa2dfb RD |
3607 | static inline void intel_opregion_register(struct drm_i915_private *dev_priv) { } |
3608 | static inline void intel_opregion_unregister(struct drm_i915_private *dev_priv) { } | |
91d14251 TU |
3609 | static inline void intel_opregion_asle_intr(struct drm_i915_private *dev_priv) |
3610 | { | |
3611 | } | |
9c4b0a68 JN |
3612 | static inline int |
3613 | intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable) | |
3614 | { | |
3615 | return 0; | |
3616 | } | |
ecbc5cf3 | 3617 | static inline int |
6f9f4b7a | 3618 | intel_opregion_notify_adapter(struct drm_i915_private *dev, pci_power_t state) |
ecbc5cf3 JN |
3619 | { |
3620 | return 0; | |
3621 | } | |
6f9f4b7a | 3622 | static inline int intel_opregion_get_panel_type(struct drm_i915_private *dev) |
a0562819 VS |
3623 | { |
3624 | return -ENODEV; | |
3625 | } | |
65e082c9 | 3626 | #endif |
8ee1c3db | 3627 | |
723bfd70 JB |
3628 | /* intel_acpi.c */ |
3629 | #ifdef CONFIG_ACPI | |
3630 | extern void intel_register_dsm_handler(void); | |
3631 | extern void intel_unregister_dsm_handler(void); | |
3632 | #else | |
3633 | static inline void intel_register_dsm_handler(void) { return; } | |
3634 | static inline void intel_unregister_dsm_handler(void) { return; } | |
3635 | #endif /* CONFIG_ACPI */ | |
3636 | ||
94b4f3ba CW |
3637 | /* intel_device_info.c */ |
3638 | static inline struct intel_device_info * | |
3639 | mkwrite_device_info(struct drm_i915_private *dev_priv) | |
3640 | { | |
3641 | return (struct intel_device_info *)&dev_priv->info; | |
3642 | } | |
3643 | ||
3644 | void intel_device_info_runtime_init(struct drm_i915_private *dev_priv); | |
3645 | void intel_device_info_dump(struct drm_i915_private *dev_priv); | |
3646 | ||
79e53945 | 3647 | /* modesetting */ |
f817586c | 3648 | extern void intel_modeset_init_hw(struct drm_device *dev); |
79e53945 | 3649 | extern void intel_modeset_init(struct drm_device *dev); |
2c7111db | 3650 | extern void intel_modeset_gem_init(struct drm_device *dev); |
79e53945 | 3651 | extern void intel_modeset_cleanup(struct drm_device *dev); |
1ebaa0b9 | 3652 | extern int intel_connector_register(struct drm_connector *); |
c191eca1 | 3653 | extern void intel_connector_unregister(struct drm_connector *); |
28d52043 | 3654 | extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state); |
043e9bda | 3655 | extern void intel_display_resume(struct drm_device *dev); |
44cec740 | 3656 | extern void i915_redisable_vga(struct drm_device *dev); |
04098753 | 3657 | extern void i915_redisable_vga_power_on(struct drm_device *dev); |
91d14251 | 3658 | extern bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val); |
dde86e2d | 3659 | extern void intel_init_pch_refclk(struct drm_device *dev); |
dc97997a | 3660 | extern void intel_set_rps(struct drm_i915_private *dev_priv, u8 val); |
5209b1f4 ID |
3661 | extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, |
3662 | bool enable); | |
3bad0781 | 3663 | |
c0c7babc BW |
3664 | int i915_reg_read_ioctl(struct drm_device *dev, void *data, |
3665 | struct drm_file *file); | |
575155a9 | 3666 | |
6ef3d427 | 3667 | /* overlay */ |
c033666a CW |
3668 | extern struct intel_overlay_error_state * |
3669 | intel_overlay_capture_error_state(struct drm_i915_private *dev_priv); | |
edc3d884 MK |
3670 | extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e, |
3671 | struct intel_overlay_error_state *error); | |
c4a1d9e4 | 3672 | |
c033666a CW |
3673 | extern struct intel_display_error_state * |
3674 | intel_display_capture_error_state(struct drm_i915_private *dev_priv); | |
edc3d884 | 3675 | extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e, |
c4a1d9e4 CW |
3676 | struct drm_device *dev, |
3677 | struct intel_display_error_state *error); | |
6ef3d427 | 3678 | |
151a49d0 TR |
3679 | int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val); |
3680 | int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val); | |
59de0813 JN |
3681 | |
3682 | /* intel_sideband.c */ | |
707b6e3d D |
3683 | u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr); |
3684 | void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val); | |
64936258 | 3685 | u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr); |
dfb19ed2 D |
3686 | u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg); |
3687 | void vlv_iosf_sb_write(struct drm_i915_private *dev_priv, u8 port, u32 reg, u32 val); | |
e9f882a3 JN |
3688 | u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg); |
3689 | void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
3690 | u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg); | |
3691 | void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
f3419158 JB |
3692 | u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg); |
3693 | void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
5e69f97f CML |
3694 | u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg); |
3695 | void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val); | |
59de0813 JN |
3696 | u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg, |
3697 | enum intel_sbi_destination destination); | |
3698 | void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value, | |
3699 | enum intel_sbi_destination destination); | |
e9fe51c6 SK |
3700 | u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg); |
3701 | void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
0a073b84 | 3702 | |
b7fa22d8 ACO |
3703 | /* intel_dpio_phy.c */ |
3704 | void chv_set_phy_signal_level(struct intel_encoder *encoder, | |
3705 | u32 deemph_reg_value, u32 margin_reg_value, | |
3706 | bool uniq_trans_scale); | |
844b2f9a ACO |
3707 | void chv_data_lane_soft_reset(struct intel_encoder *encoder, |
3708 | bool reset); | |
419b1b7a | 3709 | void chv_phy_pre_pll_enable(struct intel_encoder *encoder); |
e7d2a717 ACO |
3710 | void chv_phy_pre_encoder_enable(struct intel_encoder *encoder); |
3711 | void chv_phy_release_cl2_override(struct intel_encoder *encoder); | |
204970b5 | 3712 | void chv_phy_post_pll_disable(struct intel_encoder *encoder); |
b7fa22d8 | 3713 | |
53d98725 ACO |
3714 | void vlv_set_phy_signal_level(struct intel_encoder *encoder, |
3715 | u32 demph_reg_value, u32 preemph_reg_value, | |
3716 | u32 uniqtranscale_reg_value, u32 tx3_demph); | |
6da2e616 | 3717 | void vlv_phy_pre_pll_enable(struct intel_encoder *encoder); |
5f68c275 | 3718 | void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder); |
0f572ebe | 3719 | void vlv_phy_reset_lanes(struct intel_encoder *encoder); |
53d98725 | 3720 | |
616bc820 VS |
3721 | int intel_gpu_freq(struct drm_i915_private *dev_priv, int val); |
3722 | int intel_freq_opcode(struct drm_i915_private *dev_priv, int val); | |
c8d9a590 | 3723 | |
0b274481 BW |
3724 | #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true) |
3725 | #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true) | |
3726 | ||
3727 | #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true) | |
3728 | #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true) | |
3729 | #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false) | |
3730 | #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false) | |
3731 | ||
3732 | #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true) | |
3733 | #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true) | |
3734 | #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false) | |
3735 | #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false) | |
3736 | ||
698b3135 CW |
3737 | /* Be very careful with read/write 64-bit values. On 32-bit machines, they |
3738 | * will be implemented using 2 32-bit writes in an arbitrary order with | |
3739 | * an arbitrary delay between them. This can cause the hardware to | |
3740 | * act upon the intermediate value, possibly leading to corruption and | |
b18c1bb4 CW |
3741 | * machine death. For this reason we do not support I915_WRITE64, or |
3742 | * dev_priv->uncore.funcs.mmio_writeq. | |
3743 | * | |
3744 | * When reading a 64-bit value as two 32-bit values, the delay may cause | |
3745 | * the two reads to mismatch, e.g. a timestamp overflowing. Also note that | |
3746 | * occasionally a 64-bit register does not actualy support a full readq | |
3747 | * and must be read using two 32-bit reads. | |
3748 | * | |
3749 | * You have been warned. | |
698b3135 | 3750 | */ |
0b274481 | 3751 | #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true) |
cae5852d | 3752 | |
50877445 | 3753 | #define I915_READ64_2x32(lower_reg, upper_reg) ({ \ |
acd29f7b CW |
3754 | u32 upper, lower, old_upper, loop = 0; \ |
3755 | upper = I915_READ(upper_reg); \ | |
ee0a227b | 3756 | do { \ |
acd29f7b | 3757 | old_upper = upper; \ |
ee0a227b | 3758 | lower = I915_READ(lower_reg); \ |
acd29f7b CW |
3759 | upper = I915_READ(upper_reg); \ |
3760 | } while (upper != old_upper && loop++ < 2); \ | |
ee0a227b | 3761 | (u64)upper << 32 | lower; }) |
50877445 | 3762 | |
cae5852d ZN |
3763 | #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg) |
3764 | #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg) | |
3765 | ||
75aa3f63 VS |
3766 | #define __raw_read(x, s) \ |
3767 | static inline uint##x##_t __raw_i915_read##x(struct drm_i915_private *dev_priv, \ | |
f0f59a00 | 3768 | i915_reg_t reg) \ |
75aa3f63 | 3769 | { \ |
f0f59a00 | 3770 | return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \ |
75aa3f63 VS |
3771 | } |
3772 | ||
3773 | #define __raw_write(x, s) \ | |
3774 | static inline void __raw_i915_write##x(struct drm_i915_private *dev_priv, \ | |
f0f59a00 | 3775 | i915_reg_t reg, uint##x##_t val) \ |
75aa3f63 | 3776 | { \ |
f0f59a00 | 3777 | write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \ |
75aa3f63 VS |
3778 | } |
3779 | __raw_read(8, b) | |
3780 | __raw_read(16, w) | |
3781 | __raw_read(32, l) | |
3782 | __raw_read(64, q) | |
3783 | ||
3784 | __raw_write(8, b) | |
3785 | __raw_write(16, w) | |
3786 | __raw_write(32, l) | |
3787 | __raw_write(64, q) | |
3788 | ||
3789 | #undef __raw_read | |
3790 | #undef __raw_write | |
3791 | ||
a6111f7b | 3792 | /* These are untraced mmio-accessors that are only valid to be used inside |
351c3b53 | 3793 | * critical sections inside IRQ handlers where forcewake is explicitly |
a6111f7b CW |
3794 | * controlled. |
3795 | * Think twice, and think again, before using these. | |
3796 | * Note: Should only be used between intel_uncore_forcewake_irqlock() and | |
3797 | * intel_uncore_forcewake_irqunlock(). | |
3798 | */ | |
75aa3f63 VS |
3799 | #define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__)) |
3800 | #define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__)) | |
76f8421f | 3801 | #define I915_WRITE64_FW(reg__, val__) __raw_i915_write64(dev_priv, (reg__), (val__)) |
a6111f7b CW |
3802 | #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__) |
3803 | ||
55bc60db VS |
3804 | /* "Broadcast RGB" property */ |
3805 | #define INTEL_BROADCAST_RGB_AUTO 0 | |
3806 | #define INTEL_BROADCAST_RGB_FULL 1 | |
3807 | #define INTEL_BROADCAST_RGB_LIMITED 2 | |
ba4f01a3 | 3808 | |
f0f59a00 | 3809 | static inline i915_reg_t i915_vgacntrl_reg(struct drm_device *dev) |
766aa1c4 | 3810 | { |
666a4537 | 3811 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
766aa1c4 | 3812 | return VLV_VGACNTRL; |
92e23b99 SJ |
3813 | else if (INTEL_INFO(dev)->gen >= 5) |
3814 | return CPU_VGACNTRL; | |
766aa1c4 VS |
3815 | else |
3816 | return VGACNTRL; | |
3817 | } | |
3818 | ||
df97729f ID |
3819 | static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m) |
3820 | { | |
3821 | unsigned long j = msecs_to_jiffies(m); | |
3822 | ||
3823 | return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1); | |
3824 | } | |
3825 | ||
7bd0e226 DV |
3826 | static inline unsigned long nsecs_to_jiffies_timeout(const u64 n) |
3827 | { | |
3828 | return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1); | |
3829 | } | |
3830 | ||
df97729f ID |
3831 | static inline unsigned long |
3832 | timespec_to_jiffies_timeout(const struct timespec *value) | |
3833 | { | |
3834 | unsigned long j = timespec_to_jiffies(value); | |
3835 | ||
3836 | return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1); | |
3837 | } | |
3838 | ||
dce56b3c PZ |
3839 | /* |
3840 | * If you need to wait X milliseconds between events A and B, but event B | |
3841 | * doesn't happen exactly after event A, you record the timestamp (jiffies) of | |
3842 | * when event A happened, then just before event B you call this function and | |
3843 | * pass the timestamp as the first argument, and X as the second argument. | |
3844 | */ | |
3845 | static inline void | |
3846 | wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms) | |
3847 | { | |
ec5e0cfb | 3848 | unsigned long target_jiffies, tmp_jiffies, remaining_jiffies; |
dce56b3c PZ |
3849 | |
3850 | /* | |
3851 | * Don't re-read the value of "jiffies" every time since it may change | |
3852 | * behind our back and break the math. | |
3853 | */ | |
3854 | tmp_jiffies = jiffies; | |
3855 | target_jiffies = timestamp_jiffies + | |
3856 | msecs_to_jiffies_timeout(to_wait_ms); | |
3857 | ||
3858 | if (time_after(target_jiffies, tmp_jiffies)) { | |
ec5e0cfb ID |
3859 | remaining_jiffies = target_jiffies - tmp_jiffies; |
3860 | while (remaining_jiffies) | |
3861 | remaining_jiffies = | |
3862 | schedule_timeout_uninterruptible(remaining_jiffies); | |
dce56b3c PZ |
3863 | } |
3864 | } | |
221fe799 CW |
3865 | |
3866 | static inline bool | |
3867 | __i915_request_irq_complete(struct drm_i915_gem_request *req) | |
688e6c72 | 3868 | { |
f69a02c9 CW |
3869 | struct intel_engine_cs *engine = req->engine; |
3870 | ||
7ec2c73b CW |
3871 | /* Before we do the heavier coherent read of the seqno, |
3872 | * check the value (hopefully) in the CPU cacheline. | |
3873 | */ | |
3874 | if (i915_gem_request_completed(req)) | |
3875 | return true; | |
3876 | ||
688e6c72 CW |
3877 | /* Ensure our read of the seqno is coherent so that we |
3878 | * do not "miss an interrupt" (i.e. if this is the last | |
3879 | * request and the seqno write from the GPU is not visible | |
3880 | * by the time the interrupt fires, we will see that the | |
3881 | * request is incomplete and go back to sleep awaiting | |
3882 | * another interrupt that will never come.) | |
3883 | * | |
3884 | * Strictly, we only need to do this once after an interrupt, | |
3885 | * but it is easier and safer to do it every time the waiter | |
3886 | * is woken. | |
3887 | */ | |
3d5564e9 | 3888 | if (engine->irq_seqno_barrier && |
dbd6ef29 | 3889 | rcu_access_pointer(engine->breadcrumbs.irq_seqno_bh) == current && |
aca34b6e | 3890 | cmpxchg_relaxed(&engine->breadcrumbs.irq_posted, 1, 0)) { |
99fe4a5f CW |
3891 | struct task_struct *tsk; |
3892 | ||
3d5564e9 CW |
3893 | /* The ordering of irq_posted versus applying the barrier |
3894 | * is crucial. The clearing of the current irq_posted must | |
3895 | * be visible before we perform the barrier operation, | |
3896 | * such that if a subsequent interrupt arrives, irq_posted | |
3897 | * is reasserted and our task rewoken (which causes us to | |
3898 | * do another __i915_request_irq_complete() immediately | |
3899 | * and reapply the barrier). Conversely, if the clear | |
3900 | * occurs after the barrier, then an interrupt that arrived | |
3901 | * whilst we waited on the barrier would not trigger a | |
3902 | * barrier on the next pass, and the read may not see the | |
3903 | * seqno update. | |
3904 | */ | |
f69a02c9 | 3905 | engine->irq_seqno_barrier(engine); |
99fe4a5f CW |
3906 | |
3907 | /* If we consume the irq, but we are no longer the bottom-half, | |
3908 | * the real bottom-half may not have serialised their own | |
3909 | * seqno check with the irq-barrier (i.e. may have inspected | |
3910 | * the seqno before we believe it coherent since they see | |
3911 | * irq_posted == false but we are still running). | |
3912 | */ | |
3913 | rcu_read_lock(); | |
dbd6ef29 | 3914 | tsk = rcu_dereference(engine->breadcrumbs.irq_seqno_bh); |
99fe4a5f CW |
3915 | if (tsk && tsk != current) |
3916 | /* Note that if the bottom-half is changed as we | |
3917 | * are sending the wake-up, the new bottom-half will | |
3918 | * be woken by whomever made the change. We only have | |
3919 | * to worry about when we steal the irq-posted for | |
3920 | * ourself. | |
3921 | */ | |
3922 | wake_up_process(tsk); | |
3923 | rcu_read_unlock(); | |
3924 | ||
7ec2c73b CW |
3925 | if (i915_gem_request_completed(req)) |
3926 | return true; | |
3927 | } | |
688e6c72 | 3928 | |
688e6c72 CW |
3929 | return false; |
3930 | } | |
3931 | ||
0b1de5d5 CW |
3932 | void i915_memcpy_init_early(struct drm_i915_private *dev_priv); |
3933 | bool i915_memcpy_from_wc(void *dst, const void *src, unsigned long len); | |
3934 | ||
c58305af CW |
3935 | /* i915_mm.c */ |
3936 | int remap_io_mapping(struct vm_area_struct *vma, | |
3937 | unsigned long addr, unsigned long pfn, unsigned long size, | |
3938 | struct io_mapping *iomap); | |
3939 | ||
4b30cb23 CW |
3940 | #define ptr_mask_bits(ptr) ({ \ |
3941 | unsigned long __v = (unsigned long)(ptr); \ | |
3942 | (typeof(ptr))(__v & PAGE_MASK); \ | |
3943 | }) | |
3944 | ||
d31d7cb1 CW |
3945 | #define ptr_unpack_bits(ptr, bits) ({ \ |
3946 | unsigned long __v = (unsigned long)(ptr); \ | |
3947 | (bits) = __v & ~PAGE_MASK; \ | |
3948 | (typeof(ptr))(__v & PAGE_MASK); \ | |
3949 | }) | |
3950 | ||
3951 | #define ptr_pack_bits(ptr, bits) \ | |
3952 | ((typeof(ptr))((unsigned long)(ptr) | (bits))) | |
3953 | ||
78ef2d9a CW |
3954 | #define fetch_and_zero(ptr) ({ \ |
3955 | typeof(*ptr) __T = *(ptr); \ | |
3956 | *(ptr) = (typeof(*ptr))0; \ | |
3957 | __T; \ | |
3958 | }) | |
3959 | ||
1da177e4 | 3960 | #endif |